[..]
- A
- A0
- A0E
- A0H
- A0L
- A0P
- A0_ECHO
- A0_MARK
- A1
- A10
- A10SR_RESET_BQSPI
- A10SR_RESET_ENET_HPS
- A10SR_RESET_FILE
- A10SR_RESET_NUM
- A10SR_RESET_PCIE
- A10SR_RESET_USB
- A10_DBERR_IRQ
- A10_DDR0_IRQ_MASK
- A10_DERRADDR_OFST
- A10_DIAGINTTEST_OFST
- A10_DIAGINT_TDERRA_MASK
- A10_DIAGINT_TSERRA_MASK
- A10_DRAMADDRW
- A10_DRAMADDRW_BANKBIT_MASK
- A10_DRAMADDRW_BANKBIT_SHIFT
- A10_DRAMADDRW_CSBIT_MASK
- A10_DRAMADDRW_CSBIT_SHIFT
- A10_DRAMADDRW_GRPBIT_MASK
- A10_DRAMADDRW_GRPBIT_SHIFT
- A10_DRAMIFWIDTH
- A10_DRAMIFWIDTH_16B
- A10_DRAMIFWIDTH_32B
- A10_DRAMIFWIDTH_64B
- A10_ECCCTRL1_AWB_CNT_RST
- A10_ECCCTRL1_CNT_RST
- A10_ECCCTRL1_ECC_EN
- A10_ECCCTRL1_OFST
- A10_ECC_CNT_RESET_MASK
- A10_ECC_IRQ_EN_MASK
- A10_ERRINTEN_DERRINTEN
- A10_ERRINTEN_OFST
- A10_ERRINTEN_SERRINTEN
- A10_FPGAMGR_DCLKCNT_OFST
- A10_FPGAMGR_DCLKSTAT_DCLKDONE
- A10_FPGAMGR_DCLKSTAT_OFST
- A10_FPGAMGR_IMGCFG_CTL_00_OFST
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS
- A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE
- A10_FPGAMGR_IMGCFG_CTL_01_OFST
- A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE
- A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG
- A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST
- A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK
- A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT
- A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH
- A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT
- A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL
- A10_FPGAMGR_IMGCFG_CTL_02_OFST
- A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN
- A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR
- A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE
- A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK
- A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT
- A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN
- A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN
- A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE
- A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR
- A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY
- A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE
- A10_FPGAMGR_IMGCFG_STAT_OFST
- A10_INTMASK_CLR_OFST
- A10_INTMODE_OFST
- A10_INTMODE_SB_INT
- A10_INTSTAT_DBEERR
- A10_INTSTAT_OFST
- A10_INTSTAT_SBEERR
- A10_MARK
- A10_MPU_CTRL_L2_ECC_EN
- A10_MPU_CTRL_L2_ECC_OFST
- A10_SBERR_IRQ
- A10_SERRADDR_OFST
- A10_SERRCNTREG_OFST
- A10_SYMAN_INTMASK_CLR
- A10_SYSGMR_MPU_CLEAR_L2_ECC_MB
- A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST
- A10_SYSGMR_MPU_CLEAR_L2_ECC_SB
- A10_SYSMGR_ECC_INTMASK_CLR_L2
- A10_SYSMGR_ECC_INTMASK_CLR_OFST
- A10_SYSMGR_ECC_INTMASK_OCRAM
- A10_SYSMGR_ECC_INTMASK_SET_OFST
- A10_SYSMGR_ECC_INTSTAT_DERR_OFST
- A10_SYSMGR_ECC_INTSTAT_L2
- A10_SYSMGR_ECC_INTSTAT_OCRAM
- A10_SYSMGR_ECC_INTSTAT_SERR_OFST
- A10_SYSMGR_MPU_CLEAR_L2_ECC
- A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST
- A11
- A11_MARK
- A12
- A12_MARK
- A13
- A13_MARK
- A14
- A14_MARK
- A15
- A15_BX_ADDR0
- A15_CLUSTER
- A15_CONF
- A15_MARK
- A15_PERFVAL_BASE
- A15_PWRDN_EN
- A16
- A1655_WIFI_COMMAND
- A1655_WIFI_OFF
- A1655_WIFI_ON
- A16_MARK
- A17
- A17_MARK
- A18
- A18_MARK
- A19
- A19_MARK
- A1CR_OFFSET
- A1E
- A1H
- A1L
- A1P
- A1_CLKSRC
- A1_ECHO
- A1_MARK
- A1_SWAP
- A1_in
- A1_out
- A2
- A20
- A2065_LANCE
- A2065_RAM
- A2065_RAM_SIZE
- A2091_H
- A2091_XFER_MASK
- A20R_PT_CLOCK_BASE
- A20R_PT_TIM0_ACK
- A20R_PT_TIM1_ACK
- A20_ENABLE_LOOPS
- A20_MARK
- A20_TEST_ADDR
- A20_TEST_LONG
- A20_TEST_SHORT
- A21
- A2150_DMA_BUFFER_SIZE
- A21_MARK
- A22
- A22_MARK
- A23
- A23_MARK
- A24
- A24_MARK
- A25
- A25_MARK
- A26_MARK
- A27_MARK
- A2AIOINPUTSEL
- A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1
- A2AIOINPUTSEL_RXSEL_IECI1_MASK
- A2AIOINPUTSEL_RXSEL_MASK
- A2AIOINPUTSEL_RXSEL_PCMI1_HDMIRX1
- A2AIOINPUTSEL_RXSEL_PCMI1_MASK
- A2AIOINPUTSEL_RXSEL_PCMI2_MASK
- A2AIOINPUTSEL_RXSEL_PCMI2_SIF
- A2AIOINPUTSEL_RXSEL_PCMI3_EVEA
- A2AIOINPUTSEL_RXSEL_PCMI3_MASK
- A2APLLCTR0
- A2APLLCTR0_APLLXPOW_MASK
- A2APLLCTR0_APLLXPOW_PWOFF
- A2APLLCTR0_APLLXPOW_PWON
- A2APLLCTR1
- A2APLLCTR1_APLLX_33MHZ
- A2APLLCTR1_APLLX_36MHZ
- A2APLLCTR1_APLLX_MASK
- A2ATNMAPCTR0
- A2CH22_2CTR
- A2CHNMAPCTR0
- A2DP_SRC
- A2DP_STATE
- A2E
- A2EXMCLKSEL0
- A2EXMCLKSEL0_EXMCLK_INPUT
- A2EXMCLKSEL0_EXMCLK_MASK
- A2EXMCLKSEL0_EXMCLK_OUTPUT
- A2H
- A2IIFNMAPCTR0
- A2IPORTNMAPCTR0
- A2IPORTNMAPCTR1
- A2L
- A2L_FAIL_LIMIT
- A2MP_CHANGE_NOTIFY
- A2MP_CHANGE_RSP
- A2MP_COMMAND_REJ
- A2MP_CREATEPHYSLINK_REQ
- A2MP_CREATEPHYSLINK_RSP
- A2MP_DISCONNPHYSLINK_REQ
- A2MP_DISCONNPHYSLINK_RSP
- A2MP_DISCOVER_REQ
- A2MP_DISCOVER_RSP
- A2MP_FEAT_EXT
- A2MP_GETAMPASSOC_REQ
- A2MP_GETAMPASSOC_RSP
- A2MP_GETINFO_REQ
- A2MP_GETINFO_RSP
- A2MP_STATUS_COLLISION_OCCURED
- A2MP_STATUS_DISCONN_REQ_RECVD
- A2MP_STATUS_INVALID_CTRL_ID
- A2MP_STATUS_NO_PHYSICAL_LINK_EXISTS
- A2MP_STATUS_PHYS_LINK_EXISTS
- A2MP_STATUS_SECURITY_VIOLATION
- A2MP_STATUS_SUCCESS
- A2MP_STATUS_UNABLE_START_LINK_CREATION
- A2OIFNMAPCTR0
- A2OPORTNMAPCTR0
- A2OPORTNMAPCTR1
- A2OPORTNMAPCTR2
- A2P
- A2P_HI_PRIORITY
- A2RBNMAPCTR0
- A2SSIFSW
- A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK
- A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT
- A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK
- A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT
- A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK
- A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT
- A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK
- A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT
- A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK
- A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT
- A2S_CNTL3_CL0__FORCE_WR_PH_MASK
- A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT
- A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK
- A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT
- A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK
- A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT
- A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK
- A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT
- A2S_CNTL3_CL1__FORCE_WR_PH_MASK
- A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT
- A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK
- A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT
- A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK
- A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT
- A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK
- A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT
- A2S_CNTL_CL0__BLKLVL_MAP_MASK
- A2S_CNTL_CL0__BLKLVL_MAP__MASK
- A2S_CNTL_CL0__BLKLVL_MAP__SHIFT
- A2S_CNTL_CL0__DATERR_MAP_MASK
- A2S_CNTL_CL0__DATERR_MAP__MASK
- A2S_CNTL_CL0__DATERR_MAP__SHIFT
- A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK
- A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK
- A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT
- A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK
- A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK
- A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT
- A2S_CNTL_CL0__NSNOOP_MAP_MASK
- A2S_CNTL_CL0__NSNOOP_MAP__MASK
- A2S_CNTL_CL0__NSNOOP_MAP__SHIFT
- A2S_CNTL_CL0__RDRSP_ERRMAP_MASK
- A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT
- A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK
- A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT
- A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK
- A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK
- A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK
- A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK
- A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL0__RESP_RD_MAP_MASK
- A2S_CNTL_CL0__RESP_RD_MAP__MASK
- A2S_CNTL_CL0__RESP_RD_MAP__SHIFT
- A2S_CNTL_CL0__RESP_WR_MAP_MASK
- A2S_CNTL_CL0__RESP_WR_MAP__MASK
- A2S_CNTL_CL0__RESP_WR_MAP__SHIFT
- A2S_CNTL_CL1__BLKLVL_MAP_MASK
- A2S_CNTL_CL1__BLKLVL_MAP__MASK
- A2S_CNTL_CL1__BLKLVL_MAP__SHIFT
- A2S_CNTL_CL1__DATERR_MAP_MASK
- A2S_CNTL_CL1__DATERR_MAP__MASK
- A2S_CNTL_CL1__DATERR_MAP__SHIFT
- A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK
- A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK
- A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT
- A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK
- A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK
- A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT
- A2S_CNTL_CL1__NSNOOP_MAP_MASK
- A2S_CNTL_CL1__NSNOOP_MAP__MASK
- A2S_CNTL_CL1__NSNOOP_MAP__SHIFT
- A2S_CNTL_CL1__RDRSP_ERRMAP_MASK
- A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT
- A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK
- A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT
- A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK
- A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK
- A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK
- A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK
- A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL1__RESP_RD_MAP_MASK
- A2S_CNTL_CL1__RESP_RD_MAP__MASK
- A2S_CNTL_CL1__RESP_RD_MAP__SHIFT
- A2S_CNTL_CL1__RESP_WR_MAP_MASK
- A2S_CNTL_CL1__RESP_WR_MAP__MASK
- A2S_CNTL_CL1__RESP_WR_MAP__SHIFT
- A2S_CNTL_CL2__BLKLVL_MAP__MASK
- A2S_CNTL_CL2__BLKLVL_MAP__SHIFT
- A2S_CNTL_CL2__DATERR_MAP__MASK
- A2S_CNTL_CL2__DATERR_MAP__SHIFT
- A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK
- A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT
- A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK
- A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT
- A2S_CNTL_CL2__NSNOOP_MAP__MASK
- A2S_CNTL_CL2__NSNOOP_MAP__SHIFT
- A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL2__RESP_RD_MAP__MASK
- A2S_CNTL_CL2__RESP_RD_MAP__SHIFT
- A2S_CNTL_CL2__RESP_WR_MAP__MASK
- A2S_CNTL_CL2__RESP_WR_MAP__SHIFT
- A2S_CNTL_CL3__BLKLVL_MAP__MASK
- A2S_CNTL_CL3__BLKLVL_MAP__SHIFT
- A2S_CNTL_CL3__DATERR_MAP__MASK
- A2S_CNTL_CL3__DATERR_MAP__SHIFT
- A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK
- A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT
- A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK
- A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT
- A2S_CNTL_CL3__NSNOOP_MAP__MASK
- A2S_CNTL_CL3__NSNOOP_MAP__SHIFT
- A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL3__RESP_RD_MAP__MASK
- A2S_CNTL_CL3__RESP_RD_MAP__SHIFT
- A2S_CNTL_CL3__RESP_WR_MAP__MASK
- A2S_CNTL_CL3__RESP_WR_MAP__SHIFT
- A2S_CNTL_CL4__BLKLVL_MAP__MASK
- A2S_CNTL_CL4__BLKLVL_MAP__SHIFT
- A2S_CNTL_CL4__DATERR_MAP__MASK
- A2S_CNTL_CL4__DATERR_MAP__SHIFT
- A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK
- A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT
- A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK
- A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT
- A2S_CNTL_CL4__NSNOOP_MAP__MASK
- A2S_CNTL_CL4__NSNOOP_MAP__SHIFT
- A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK
- A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT
- A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK
- A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT
- A2S_CNTL_CL4__RESP_RD_MAP__MASK
- A2S_CNTL_CL4__RESP_RD_MAP__SHIFT
- A2S_CNTL_CL4__RESP_WR_MAP__MASK
- A2S_CNTL_CL4__RESP_WR_MAP__SHIFT
- A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK
- A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT
- A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK
- A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT
- A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK
- A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT
- A2S_CNTL_SW0__RSP_REORDER_DIS__MASK
- A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT
- A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK
- A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK
- A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT
- A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK
- A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT
- A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK
- A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK
- A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT
- A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK
- A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK
- A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT
- A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK
- A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT
- A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK
- A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT
- A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK
- A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT
- A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK
- A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT
- A2S_CNTL_SW1__RSP_REORDER_DIS__MASK
- A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT
- A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK
- A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK
- A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT
- A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK
- A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT
- A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK
- A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK
- A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT
- A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK
- A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK
- A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT
- A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK
- A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT
- A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK
- A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT
- A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK
- A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT
- A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK
- A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT
- A2S_CNTL_SW2__RSP_REORDER_DIS__MASK
- A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT
- A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK
- A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK
- A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT
- A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK
- A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT
- A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK
- A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK
- A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK
- A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT
- A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK
- A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK
- A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT
- A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK
- A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK
- A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT
- A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK
- A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK
- A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT
- A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK
- A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT
- A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK
- A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT
- A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK
- A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT
- A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK
- A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK
- A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT
- A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK
- A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK
- A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT
- A2S_MISC_CNTL__RSP_REORDER_DIS_MASK
- A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT
- A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK
- A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT
- A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK
- A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT
- A2S_MISC_CNTL__WRR_ARB_MODE_MASK
- A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT
- A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK
- A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK
- A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK
- A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT
- A2W_PLLA_ANA0
- A2W_PLLA_CCP2
- A2W_PLLA_CORE
- A2W_PLLA_CTRL
- A2W_PLLA_DSI0
- A2W_PLLA_FRAC
- A2W_PLLA_PER
- A2W_PLLB_ANA0
- A2W_PLLB_ARM
- A2W_PLLB_CTRL
- A2W_PLLB_FRAC
- A2W_PLLB_SP0
- A2W_PLLB_SP1
- A2W_PLLB_SP2
- A2W_PLLC_ANA0
- A2W_PLLC_CORE0
- A2W_PLLC_CORE1
- A2W_PLLC_CORE2
- A2W_PLLC_CTRL
- A2W_PLLC_FRAC
- A2W_PLLC_PER
- A2W_PLLD_ANA0
- A2W_PLLD_CORE
- A2W_PLLD_CTRL
- A2W_PLLD_DSI0
- A2W_PLLD_DSI1
- A2W_PLLD_FRAC
- A2W_PLLD_PER
- A2W_PLLH_ANA0
- A2W_PLLH_AUX
- A2W_PLLH_AUXR
- A2W_PLLH_CTRL
- A2W_PLLH_CTRLR
- A2W_PLLH_FRAC
- A2W_PLLH_FRACR
- A2W_PLLH_KA_MASK
- A2W_PLLH_KA_SHIFT
- A2W_PLLH_KI_HIGH_MASK
- A2W_PLLH_KI_HIGH_SHIFT
- A2W_PLLH_KI_LOW_MASK
- A2W_PLLH_KI_LOW_SHIFT
- A2W_PLLH_KP_MASK
- A2W_PLLH_KP_SHIFT
- A2W_PLLH_PIX
- A2W_PLLH_PIXR
- A2W_PLLH_RCAL
- A2W_PLLH_RCALR
- A2W_PLLH_STS
- A2W_PLLH_STSR
- A2W_PLL_CHANNEL_DISABLE
- A2W_PLL_CTRL_NDIV_MASK
- A2W_PLL_CTRL_NDIV_SHIFT
- A2W_PLL_CTRL_PDIV_MASK
- A2W_PLL_CTRL_PDIV_SHIFT
- A2W_PLL_CTRL_PRST_DISABLE
- A2W_PLL_CTRL_PWRDN
- A2W_PLL_DIV_BITS
- A2W_PLL_DIV_SHIFT
- A2W_PLL_FRAC_BITS
- A2W_PLL_FRAC_MASK
- A2W_PLL_KA_MASK
- A2W_PLL_KA_SHIFT
- A2W_PLL_KI_MASK
- A2W_PLL_KI_SHIFT
- A2W_PLL_KP_MASK
- A2W_PLL_KP_SHIFT
- A2W_XOSC_CTRL
- A2W_XOSC_CTRL_CPR1_ENABLE
- A2W_XOSC_CTRL_DDR_ENABLE
- A2W_XOSC_CTRL_HDMI_ENABLE
- A2W_XOSC_CTRL_PLLA_ENABLE
- A2W_XOSC_CTRL_PLLB_ENABLE
- A2W_XOSC_CTRL_PLLC_ENABLE
- A2W_XOSC_CTRL_PLLD_ENABLE
- A2W_XOSC_CTRL_USB_ENABLE
- A2XX
- A2XX_A220_VSC_BIN_SIZE_HEIGHT
- A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK
- A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT
- A2XX_A220_VSC_BIN_SIZE_WIDTH
- A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK
- A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT
- A2XX_CLEAR_COLOR_ALPHA
- A2XX_CLEAR_COLOR_ALPHA__MASK
- A2XX_CLEAR_COLOR_ALPHA__SHIFT
- A2XX_CLEAR_COLOR_BLUE
- A2XX_CLEAR_COLOR_BLUE__MASK
- A2XX_CLEAR_COLOR_BLUE__SHIFT
- A2XX_CLEAR_COLOR_GREEN
- A2XX_CLEAR_COLOR_GREEN__MASK
- A2XX_CLEAR_COLOR_GREEN__SHIFT
- A2XX_CLEAR_COLOR_RED
- A2XX_CLEAR_COLOR_RED__MASK
- A2XX_CLEAR_COLOR_RED__SHIFT
- A2XX_CP_REG_TEST_0_BIT
- A2XX_CP_REG_TEST_0_BIT__MASK
- A2XX_CP_REG_TEST_0_BIT__SHIFT
- A2XX_CP_REG_TEST_0_REG
- A2XX_CP_REG_TEST_0_REG__MASK
- A2XX_CP_REG_TEST_0_REG__SHIFT
- A2XX_CP_REG_TEST_0_UNK25
- A2XX_CP_SET_MARKER_0_IFPC
- A2XX_CP_SET_MARKER_0_MARKER
- A2XX_CP_SET_MARKER_0_MARKER__MASK
- A2XX_CP_SET_MARKER_0_MARKER__SHIFT
- A2XX_CP_SET_MARKER_0_MODE
- A2XX_CP_SET_MARKER_0_MODE__MASK
- A2XX_CP_SET_MARKER_0_MODE__SHIFT
- A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG
- A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK
- A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT
- A2XX_CP_SET_PSEUDO_REG__1_LO
- A2XX_CP_SET_PSEUDO_REG__1_LO__MASK
- A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT
- A2XX_CP_SET_PSEUDO_REG__2_HI
- A2XX_CP_SET_PSEUDO_REG__2_HI__MASK
- A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT
- A2XX_MASTER_INT_SIGNAL_CP_INT_STAT
- A2XX_MASTER_INT_SIGNAL_MH_INT_STAT
- A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT
- A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT
- A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE
- A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT
- A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE
- A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK
- A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT
- A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE
- A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE
- A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL
- A2XX_MH_ARBITER_CONFIG_PAGE_SIZE
- A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK
- A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT
- A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE
- A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE
- A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY
- A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT
- A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK
- A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT
- A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE
- A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE
- A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE
- A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE
- A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR
- A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR
- A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT
- A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_MMU_ENABLE
- A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE
- A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR
- A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK
- A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT
- A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL
- A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC
- A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS
- A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK
- A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT
- A2XX_MH_MMU_VA_RANGE_VA_BASE
- A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK
- A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT
- A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA
- A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE
- A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT
- A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF
- A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK
- A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT
- A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR
- A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN
- A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN
- A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN
- A2XX_PA_CL_GB_HORZ_CLIP_ADJ
- A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK
- A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT
- A2XX_PA_CL_GB_HORZ_DISC_ADJ
- A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK
- A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT
- A2XX_PA_CL_GB_VERT_CLIP_ADJ
- A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK
- A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT
- A2XX_PA_CL_GB_VERT_DISC_ADJ
- A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK
- A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT
- A2XX_PA_CL_VPORT_XOFFSET
- A2XX_PA_CL_VPORT_XOFFSET__MASK
- A2XX_PA_CL_VPORT_XOFFSET__SHIFT
- A2XX_PA_CL_VPORT_XSCALE
- A2XX_PA_CL_VPORT_XSCALE__MASK
- A2XX_PA_CL_VPORT_XSCALE__SHIFT
- A2XX_PA_CL_VPORT_YOFFSET
- A2XX_PA_CL_VPORT_YOFFSET__MASK
- A2XX_PA_CL_VPORT_YOFFSET__SHIFT
- A2XX_PA_CL_VPORT_YSCALE
- A2XX_PA_CL_VPORT_YSCALE__MASK
- A2XX_PA_CL_VPORT_YSCALE__SHIFT
- A2XX_PA_CL_VPORT_ZOFFSET
- A2XX_PA_CL_VPORT_ZOFFSET__MASK
- A2XX_PA_CL_VPORT_ZOFFSET__SHIFT
- A2XX_PA_CL_VPORT_ZSCALE
- A2XX_PA_CL_VPORT_ZSCALE__MASK
- A2XX_PA_CL_VPORT_ZSCALE__SHIFT
- A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF
- A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
- A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
- A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA
- A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA
- A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
- A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT
- A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT
- A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST
- A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK
- A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT
- A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES
- A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK
- A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT
- A2XX_PA_SC_LINE_CNTL_BRES_CNTL
- A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK
- A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT
- A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH
- A2XX_PA_SC_LINE_CNTL_LAST_PIXEL
- A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL
- A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL
- A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK
- A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT
- A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN
- A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK
- A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT
- A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER
- A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK
- A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT
- A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT
- A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK
- A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT
- A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A2XX_PA_SC_SCREEN_SCISSOR_BR_X
- A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK
- A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT
- A2XX_PA_SC_SCREEN_SCISSOR_BR_Y
- A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK
- A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT
- A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A2XX_PA_SC_SCREEN_SCISSOR_TL_X
- A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK
- A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT
- A2XX_PA_SC_SCREEN_SCISSOR_TL_Y
- A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK
- A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT
- A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z
- A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA
- A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID
- A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK
- A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT
- A2XX_PA_SC_WINDOW_OFFSET_DISABLE
- A2XX_PA_SC_WINDOW_OFFSET_X
- A2XX_PA_SC_WINDOW_OFFSET_X__MASK
- A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT
- A2XX_PA_SC_WINDOW_OFFSET_Y
- A2XX_PA_SC_WINDOW_OFFSET_Y__MASK
- A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT
- A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A2XX_PA_SC_WINDOW_SCISSOR_BR_X
- A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK
- A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT
- A2XX_PA_SC_WINDOW_SCISSOR_BR_Y
- A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK
- A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT
- A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A2XX_PA_SC_WINDOW_SCISSOR_TL_X
- A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK
- A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT
- A2XX_PA_SC_WINDOW_SCISSOR_TL_Y
- A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK
- A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT
- A2XX_PA_SU_FACE_DATA_BASE_ADDR
- A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK
- A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT
- A2XX_PA_SU_LINE_CNTL_WIDTH
- A2XX_PA_SU_LINE_CNTL_WIDTH__MASK
- A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT
- A2XX_PA_SU_POINT_MINMAX_MAX
- A2XX_PA_SU_POINT_MINMAX_MAX__MASK
- A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT
- A2XX_PA_SU_POINT_MINMAX_MIN
- A2XX_PA_SU_POINT_MINMAX_MIN__MASK
- A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT
- A2XX_PA_SU_POINT_SIZE_HEIGHT
- A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK
- A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT
- A2XX_PA_SU_POINT_SIZE_WIDTH
- A2XX_PA_SU_POINT_SIZE_WIDTH__MASK
- A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT
- A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE
- A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK
- A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT
- A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS
- A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK
- A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT
- A2XX_PA_SU_SC_MODE_CNTL_FACE
- A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE
- A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK
- A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT
- A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA
- A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS
- A2XX_PA_SU_SC_MODE_CNTL_POLYMODE
- A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK
- A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT
- A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
- A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE
- A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI
- A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE
- A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS
- A2XX_PA_SU_VTX_CNTL_PIX_CENTER
- A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK
- A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT
- A2XX_PA_SU_VTX_CNTL_QUANT_MODE
- A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK
- A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT
- A2XX_PA_SU_VTX_CNTL_ROUND_MODE
- A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK
- A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT
- A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK
- A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK
- A2XX_RBBM_INT_CNTL_RDERR_INT_MASK
- A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE
- A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE
- A2XX_RBBM_STATUS_CFRQ_PENDING
- A2XX_RBBM_STATUS_CMDFIFO_AVAIL
- A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK
- A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT
- A2XX_RBBM_STATUS_CPRQ_PENDING
- A2XX_RBBM_STATUS_CP_NRT_BUSY
- A2XX_RBBM_STATUS_GUI_ACTIVE
- A2XX_RBBM_STATUS_HIRQ_PENDING
- A2XX_RBBM_STATUS_MH_BUSY
- A2XX_RBBM_STATUS_MH_COHERENCY_BUSY
- A2XX_RBBM_STATUS_PA_BUSY
- A2XX_RBBM_STATUS_PFRQ_PENDING
- A2XX_RBBM_STATUS_RBBM_WU_BUSY
- A2XX_RBBM_STATUS_RB_CNTX_BUSY
- A2XX_RBBM_STATUS_SC_CNTX_BUSY
- A2XX_RBBM_STATUS_SQ_CNTX0_BUSY
- A2XX_RBBM_STATUS_SQ_CNTX17_BUSY
- A2XX_RBBM_STATUS_SX_BUSY
- A2XX_RBBM_STATUS_TC_BUSY
- A2XX_RBBM_STATUS_TPC_BUSY
- A2XX_RBBM_STATUS_VGT_BUSY
- A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA
- A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK
- A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK
- A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT
- A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT
- A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK
- A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT
- A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE
- A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT
- A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK
- A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT
- A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT
- A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK
- A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT
- A2XX_RB_BC_CONTROL_CRC_MODE
- A2XX_RB_BC_CONTROL_CRC_SYSTEM
- A2XX_RB_BC_CONTROL_DISABLE_ACCUM
- A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM
- A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH
- A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP
- A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP
- A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS
- A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE
- A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE
- A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE
- A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE
- A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT
- A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK
- A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT
- A2XX_RB_BC_CONTROL_RESERVED6
- A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN
- A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK
- A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT
- A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND
- A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK
- A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT
- A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND
- A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK
- A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT
- A2XX_RB_BLEND_CONTROL_BLEND_FORCE
- A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE
- A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN
- A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK
- A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT
- A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND
- A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK
- A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT
- A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND
- A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK
- A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT
- A2XX_RB_COLORCONTROL_ALPHA_FUNC
- A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK
- A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT
- A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK
- A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT
- A2XX_RB_COLORCONTROL_BLEND_DISABLE
- A2XX_RB_COLORCONTROL_DITHER_MODE
- A2XX_RB_COLORCONTROL_DITHER_MODE__MASK
- A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT
- A2XX_RB_COLORCONTROL_DITHER_TYPE
- A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK
- A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT
- A2XX_RB_COLORCONTROL_PIXEL_FOG
- A2XX_RB_COLORCONTROL_ROP_CODE
- A2XX_RB_COLORCONTROL_ROP_CODE__MASK
- A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT
- A2XX_RB_COLORCONTROL_VOB_ENABLE
- A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG
- A2XX_RB_COLOR_INFO_BASE
- A2XX_RB_COLOR_INFO_BASE__MASK
- A2XX_RB_COLOR_INFO_BASE__SHIFT
- A2XX_RB_COLOR_INFO_ENDIAN
- A2XX_RB_COLOR_INFO_ENDIAN__MASK
- A2XX_RB_COLOR_INFO_ENDIAN__SHIFT
- A2XX_RB_COLOR_INFO_FORMAT
- A2XX_RB_COLOR_INFO_FORMAT__MASK
- A2XX_RB_COLOR_INFO_FORMAT__SHIFT
- A2XX_RB_COLOR_INFO_LINEAR
- A2XX_RB_COLOR_INFO_ROUND_MODE
- A2XX_RB_COLOR_INFO_ROUND_MODE__MASK
- A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT
- A2XX_RB_COLOR_INFO_SWAP
- A2XX_RB_COLOR_INFO_SWAP__MASK
- A2XX_RB_COLOR_INFO_SWAP__SHIFT
- A2XX_RB_COLOR_MASK_WRITE_ALPHA
- A2XX_RB_COLOR_MASK_WRITE_BLUE
- A2XX_RB_COLOR_MASK_WRITE_GREEN
- A2XX_RB_COLOR_MASK_WRITE_RED
- A2XX_RB_COPY_CONTROL_CLEAR_MASK
- A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK
- A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT
- A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT
- A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK
- A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT
- A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE
- A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN
- A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK
- A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT
- A2XX_RB_COPY_DEST_INFO_DITHER_MODE
- A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK
- A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT
- A2XX_RB_COPY_DEST_INFO_DITHER_TYPE
- A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK
- A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT
- A2XX_RB_COPY_DEST_INFO_FORMAT
- A2XX_RB_COPY_DEST_INFO_FORMAT__MASK
- A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
- A2XX_RB_COPY_DEST_INFO_LINEAR
- A2XX_RB_COPY_DEST_INFO_SWAP
- A2XX_RB_COPY_DEST_INFO_SWAP__MASK
- A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT
- A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
- A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
- A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
- A2XX_RB_COPY_DEST_INFO_WRITE_RED
- A2XX_RB_COPY_DEST_OFFSET_X
- A2XX_RB_COPY_DEST_OFFSET_X__MASK
- A2XX_RB_COPY_DEST_OFFSET_X__SHIFT
- A2XX_RB_COPY_DEST_OFFSET_Y
- A2XX_RB_COPY_DEST_OFFSET_Y__MASK
- A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT
- A2XX_RB_COPY_DEST_PITCH
- A2XX_RB_COPY_DEST_PITCH__MASK
- A2XX_RB_COPY_DEST_PITCH__SHIFT
- A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE
- A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
- A2XX_RB_DEPTHCONTROL_STENCILFAIL
- A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF
- A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK
- A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK
- A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILFUNC
- A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF
- A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK
- A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK
- A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK
- A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILZPASS
- A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF
- A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK
- A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK
- A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT
- A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE
- A2XX_RB_DEPTHCONTROL_ZFUNC
- A2XX_RB_DEPTHCONTROL_ZFUNC__MASK
- A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT
- A2XX_RB_DEPTHCONTROL_Z_ENABLE
- A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE
- A2XX_RB_DEPTH_INFO_DEPTH_BASE
- A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
- A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
- A2XX_RB_DEPTH_INFO_DEPTH_FORMAT
- A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
- A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
- A2XX_RB_FOG_COLOR_FOG_BLUE
- A2XX_RB_FOG_COLOR_FOG_BLUE__MASK
- A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT
- A2XX_RB_FOG_COLOR_FOG_GREEN
- A2XX_RB_FOG_COLOR_FOG_GREEN__MASK
- A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT
- A2XX_RB_FOG_COLOR_FOG_RED
- A2XX_RB_FOG_COLOR_FOG_RED__MASK
- A2XX_RB_FOG_COLOR_FOG_RED__SHIFT
- A2XX_RB_MODECONTROL_EDRAM_MODE
- A2XX_RB_MODECONTROL_EDRAM_MODE__MASK
- A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT
- A2XX_RB_STENCILREFMASK_BF_STENCILMASK
- A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
- A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
- A2XX_RB_STENCILREFMASK_BF_STENCILREF
- A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
- A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
- A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK
- A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
- A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
- A2XX_RB_STENCILREFMASK_STENCILMASK
- A2XX_RB_STENCILREFMASK_STENCILMASK__MASK
- A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
- A2XX_RB_STENCILREFMASK_STENCILREF
- A2XX_RB_STENCILREFMASK_STENCILREF__MASK
- A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT
- A2XX_RB_STENCILREFMASK_STENCILWRITEMASK
- A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
- A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
- A2XX_RB_SURFACE_INFO_MSAA_SAMPLES
- A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK
- A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT
- A2XX_RB_SURFACE_INFO_SURFACE_PITCH
- A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK
- A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT
- A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE
- A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS
- A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK
- A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT
- A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF
- A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY
- A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL
- A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK
- A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT
- A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL
- A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE
- A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK
- A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK
- A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT
- A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE
- A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK
- A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT
- A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN
- A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK
- A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT
- A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX
- A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX
- A2XX_SQ_PROGRAM_CNTL_PARAM_GEN
- A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE
- A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK
- A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT
- A2XX_SQ_PROGRAM_CNTL_PS_REGS
- A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK
- A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT
- A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK
- A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT
- A2XX_SQ_PROGRAM_CNTL_VS_REGS
- A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK
- A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT
- A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE
- A2XX_SQ_PS_CONST_BASE
- A2XX_SQ_PS_CONST_BASE__MASK
- A2XX_SQ_PS_CONST_BASE__SHIFT
- A2XX_SQ_PS_CONST_SIZE
- A2XX_SQ_PS_CONST_SIZE__MASK
- A2XX_SQ_PS_CONST_SIZE__SHIFT
- A2XX_SQ_PS_PROGRAM_BASE
- A2XX_SQ_PS_PROGRAM_BASE__MASK
- A2XX_SQ_PS_PROGRAM_BASE__SHIFT
- A2XX_SQ_PS_PROGRAM_SIZE
- A2XX_SQ_PS_PROGRAM_SIZE__MASK
- A2XX_SQ_PS_PROGRAM_SIZE__SHIFT
- A2XX_SQ_TEX_0_CLAMP_X
- A2XX_SQ_TEX_0_CLAMP_X__MASK
- A2XX_SQ_TEX_0_CLAMP_X__SHIFT
- A2XX_SQ_TEX_0_CLAMP_Y
- A2XX_SQ_TEX_0_CLAMP_Y__MASK
- A2XX_SQ_TEX_0_CLAMP_Y__SHIFT
- A2XX_SQ_TEX_0_CLAMP_Z
- A2XX_SQ_TEX_0_CLAMP_Z__MASK
- A2XX_SQ_TEX_0_CLAMP_Z__SHIFT
- A2XX_SQ_TEX_0_PITCH
- A2XX_SQ_TEX_0_PITCH__MASK
- A2XX_SQ_TEX_0_PITCH__SHIFT
- A2XX_SQ_TEX_0_SIGN_W
- A2XX_SQ_TEX_0_SIGN_W__MASK
- A2XX_SQ_TEX_0_SIGN_W__SHIFT
- A2XX_SQ_TEX_0_SIGN_X
- A2XX_SQ_TEX_0_SIGN_X__MASK
- A2XX_SQ_TEX_0_SIGN_X__SHIFT
- A2XX_SQ_TEX_0_SIGN_Y
- A2XX_SQ_TEX_0_SIGN_Y__MASK
- A2XX_SQ_TEX_0_SIGN_Y__SHIFT
- A2XX_SQ_TEX_0_SIGN_Z
- A2XX_SQ_TEX_0_SIGN_Z__MASK
- A2XX_SQ_TEX_0_SIGN_Z__SHIFT
- A2XX_SQ_TEX_0_TILED
- A2XX_SQ_TEX_0_TYPE
- A2XX_SQ_TEX_0_TYPE__MASK
- A2XX_SQ_TEX_0_TYPE__SHIFT
- A2XX_SQ_TEX_1_BASE_ADDRESS
- A2XX_SQ_TEX_1_BASE_ADDRESS__MASK
- A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT
- A2XX_SQ_TEX_1_CLAMP_POLICY
- A2XX_SQ_TEX_1_CLAMP_POLICY__MASK
- A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT
- A2XX_SQ_TEX_1_ENDIANNESS
- A2XX_SQ_TEX_1_ENDIANNESS__MASK
- A2XX_SQ_TEX_1_ENDIANNESS__SHIFT
- A2XX_SQ_TEX_1_FORMAT
- A2XX_SQ_TEX_1_FORMAT__MASK
- A2XX_SQ_TEX_1_FORMAT__SHIFT
- A2XX_SQ_TEX_1_REQUEST_SIZE
- A2XX_SQ_TEX_1_REQUEST_SIZE__MASK
- A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT
- A2XX_SQ_TEX_1_STACKED
- A2XX_SQ_TEX_2_DEPTH
- A2XX_SQ_TEX_2_DEPTH__MASK
- A2XX_SQ_TEX_2_DEPTH__SHIFT
- A2XX_SQ_TEX_2_HEIGHT
- A2XX_SQ_TEX_2_HEIGHT__MASK
- A2XX_SQ_TEX_2_HEIGHT__SHIFT
- A2XX_SQ_TEX_2_WIDTH
- A2XX_SQ_TEX_2_WIDTH__MASK
- A2XX_SQ_TEX_2_WIDTH__SHIFT
- A2XX_SQ_TEX_3_ANISO_FILTER
- A2XX_SQ_TEX_3_ANISO_FILTER__MASK
- A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT
- A2XX_SQ_TEX_3_BORDER_SIZE
- A2XX_SQ_TEX_3_BORDER_SIZE__MASK
- A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT
- A2XX_SQ_TEX_3_EXP_ADJUST
- A2XX_SQ_TEX_3_EXP_ADJUST__MASK
- A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT
- A2XX_SQ_TEX_3_MIP_FILTER
- A2XX_SQ_TEX_3_MIP_FILTER__MASK
- A2XX_SQ_TEX_3_MIP_FILTER__SHIFT
- A2XX_SQ_TEX_3_NUM_FORMAT
- A2XX_SQ_TEX_3_NUM_FORMAT__MASK
- A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT
- A2XX_SQ_TEX_3_SWIZ_W
- A2XX_SQ_TEX_3_SWIZ_W__MASK
- A2XX_SQ_TEX_3_SWIZ_W__SHIFT
- A2XX_SQ_TEX_3_SWIZ_X
- A2XX_SQ_TEX_3_SWIZ_X__MASK
- A2XX_SQ_TEX_3_SWIZ_X__SHIFT
- A2XX_SQ_TEX_3_SWIZ_Y
- A2XX_SQ_TEX_3_SWIZ_Y__MASK
- A2XX_SQ_TEX_3_SWIZ_Y__SHIFT
- A2XX_SQ_TEX_3_SWIZ_Z
- A2XX_SQ_TEX_3_SWIZ_Z__MASK
- A2XX_SQ_TEX_3_SWIZ_Z__SHIFT
- A2XX_SQ_TEX_3_XY_MAG_FILTER
- A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK
- A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT
- A2XX_SQ_TEX_3_XY_MIN_FILTER
- A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK
- A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK
- A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT
- A2XX_SQ_TEX_4_LOD_BIAS
- A2XX_SQ_TEX_4_LOD_BIAS__MASK
- A2XX_SQ_TEX_4_LOD_BIAS__SHIFT
- A2XX_SQ_TEX_4_MAX_ANISO_WALK
- A2XX_SQ_TEX_4_MIN_ANISO_WALK
- A2XX_SQ_TEX_4_MIP_MAX_LEVEL
- A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK
- A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT
- A2XX_SQ_TEX_4_MIP_MIN_LEVEL
- A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK
- A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT
- A2XX_SQ_TEX_4_VOL_MAG_FILTER
- A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK
- A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT
- A2XX_SQ_TEX_4_VOL_MIN_FILTER
- A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK
- A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT
- A2XX_SQ_TEX_5_ANISO_BIAS
- A2XX_SQ_TEX_5_ANISO_BIAS__MASK
- A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT
- A2XX_SQ_TEX_5_BORDER_COLOR
- A2XX_SQ_TEX_5_BORDER_COLOR__MASK
- A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT
- A2XX_SQ_TEX_5_DIMENSION
- A2XX_SQ_TEX_5_DIMENSION__MASK
- A2XX_SQ_TEX_5_DIMENSION__SHIFT
- A2XX_SQ_TEX_5_FORCE_BCW_MAX
- A2XX_SQ_TEX_5_MIP_ADDRESS
- A2XX_SQ_TEX_5_MIP_ADDRESS__MASK
- A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT
- A2XX_SQ_TEX_5_PACKED_MIPS
- A2XX_SQ_TEX_5_TRI_CLAMP
- A2XX_SQ_TEX_5_TRI_CLAMP__MASK
- A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT
- A2XX_SQ_VS_CONST_BASE
- A2XX_SQ_VS_CONST_BASE__MASK
- A2XX_SQ_VS_CONST_BASE__SHIFT
- A2XX_SQ_VS_CONST_SIZE
- A2XX_SQ_VS_CONST_SIZE__MASK
- A2XX_SQ_VS_CONST_SIZE__SHIFT
- A2XX_SQ_VS_PROGRAM_BASE
- A2XX_SQ_VS_PROGRAM_BASE__MASK
- A2XX_SQ_VS_PROGRAM_BASE__SHIFT
- A2XX_SQ_VS_PROGRAM_SIZE
- A2XX_SQ_VS_PROGRAM_SIZE__MASK
- A2XX_SQ_VS_PROGRAM_SIZE__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_0
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_1
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_2
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_3
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_4
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_5
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_6
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_7
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK
- A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_10
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_11
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_12
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_13
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_14
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_15
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_8
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_9
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK
- A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT
- A2XX_TC_CNTL_STATUS_L2_INVALIDATE
- A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN
- A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK
- A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT
- A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK
- A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK
- A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT
- A2XX_VGT_CURRENT_BIN_ID_MAX_ROW
- A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK
- A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT
- A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN
- A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK
- A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT
- A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK
- A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK
- A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT
- A2XX_VGT_CURRENT_BIN_ID_MIN_ROW
- A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK
- A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT
- A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE
- A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK
- A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT
- A2XX_VGT_DRAW_INITIATOR_NOT_EOP
- A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES
- A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK
- A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT
- A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE
- A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE
- A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK
- A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT
- A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX
- A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT
- A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK
- A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT
- A2XX_VGT_DRAW_INITIATOR_VIS_CULL
- A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK
- A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT
- A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST
- A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK
- A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT
- A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH
- A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK
- A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT
- A2XX_XML
- A2_CCR0_PME_DISABLED
- A2_CCR0_PME_DISABLED2
- A2_CCR0_PME_RVW
- A2_CCR0_PME_SLEEP
- A2_CCR2_ENABLE_ICSWX
- A2_CCR2_ENABLE_PC
- A2_CCR2_ENABLE_TRACE
- A2_CCR2_ERAT_ONLY_MODE
- A2_CLKSRC
- A2_DERAT_SIZE
- A2_ECHO
- A2_IERAT_SIZE
- A2_MARK
- A2_SWAP
- A2_in
- A2_out
- A3
- A3000_H
- A3000_XFER_MASK
- A32
- A32_RN_OFFSET
- A32_RT2_OFFSET
- A32_RT_OFFSET
- A3700_SPI_ADDR_CNT_BIT
- A3700_SPI_ADDR_CNT_MASK
- A3700_SPI_ADDR_NOT_CONFIG
- A3700_SPI_ADDR_PIN
- A3700_SPI_AUTO_CS
- A3700_SPI_BYTE_LEN
- A3700_SPI_CLK_CAPT_EDGE
- A3700_SPI_CLK_EVEN_OFFS
- A3700_SPI_CLK_PHA
- A3700_SPI_CLK_POL
- A3700_SPI_CLK_PRESCALE
- A3700_SPI_CLK_PRESCALE_MASK
- A3700_SPI_DATA_IN_REG
- A3700_SPI_DATA_OUT_REG
- A3700_SPI_DATA_PIN0
- A3700_SPI_DATA_PIN1
- A3700_SPI_DATA_PIN_MASK
- A3700_SPI_DMA_RD_EN
- A3700_SPI_DUMMY_CNT_BIT
- A3700_SPI_DUMMY_CNT_MASK
- A3700_SPI_EN
- A3700_SPI_FIFO_FLUSH
- A3700_SPI_FIFO_MODE
- A3700_SPI_FIFO_THRS_MASK
- A3700_SPI_IF_ADDR_REG
- A3700_SPI_IF_CFG_REG
- A3700_SPI_IF_CTRL_REG
- A3700_SPI_IF_DIN_CNT_REG
- A3700_SPI_IF_HDR_CNT_REG
- A3700_SPI_IF_INST_REG
- A3700_SPI_IF_RMODE_REG
- A3700_SPI_IF_TIME_REG
- A3700_SPI_INSTR_CNT_BIT
- A3700_SPI_INSTR_CNT_MASK
- A3700_SPI_INST_PIN
- A3700_SPI_INT_MASK_REG
- A3700_SPI_INT_STAT_REG
- A3700_SPI_MAX_PRESCALE
- A3700_SPI_MAX_SPEED_HZ
- A3700_SPI_RFIFO_EMPTY
- A3700_SPI_RFIFO_FULL
- A3700_SPI_RFIFO_OVERFLOW
- A3700_SPI_RFIFO_RDY
- A3700_SPI_RFIFO_THRS
- A3700_SPI_RFIFO_THRS_BIT
- A3700_SPI_RFIFO_UNDERFLOW
- A3700_SPI_RMODE_CNT_BIT
- A3700_SPI_RMODE_CNT_MASK
- A3700_SPI_RW_EN
- A3700_SPI_SRST
- A3700_SPI_TIMEOUT
- A3700_SPI_WFIFO_EMPTY
- A3700_SPI_WFIFO_FULL
- A3700_SPI_WFIFO_OVERFLOW
- A3700_SPI_WFIFO_RDY
- A3700_SPI_WFIFO_THRS
- A3700_SPI_WFIFO_THRS_BIT
- A3700_SPI_WFIFO_UNDERFLOW
- A3700_SPI_XFER_DONE
- A3700_SPI_XFER_RDY
- A3700_SPI_XFER_START
- A3700_SPI_XFER_STOP
- A370_CPU_TO_DRAMCLK
- A370_CPU_TO_HCLK
- A370_CPU_TO_NBCLK
- A375_CPU_TO_DDR
- A375_CPU_TO_L2
- A375_HW_RESETn
- A375_READOUT_INVERT
- A375_UNIT_CONTROL_MASK
- A375_UNIT_CONTROL_SHIFT
- A380_CPU_TO_DDR
- A380_CPU_TO_L2
- A390_CPU_TO_DCLK
- A390_CPU_TO_HCLK
- A390_CPU_TO_NBCLK
- A3D_A_A12Current
- A3D_A_A21Target
- A3D_A_B01Current
- A3D_A_B10Target
- A3D_A_B2Current
- A3D_A_B2Target
- A3D_A_CoeffTrackTC
- A3D_A_GainCurrent
- A3D_A_GainTarget
- A3D_A_GainTrackTC
- A3D_A_HrtfCurrent
- A3D_A_HrtfDelayLine
- A3D_A_HrtfOutL
- A3D_A_HrtfOutR
- A3D_A_HrtfTarget
- A3D_A_HrtfTrackTC
- A3D_A_ITDCurrent
- A3D_A_ITDDelayLine
- A3D_A_ITDTarget
- A3D_A_ITDTrackTC
- A3D_A_TAIL
- A3D_A_x1
- A3D_A_x2
- A3D_A_y1
- A3D_A_y2
- A3D_B_A12Current
- A3D_B_A21Target
- A3D_B_B01Current
- A3D_B_B10Target
- A3D_B_B2Current
- A3D_B_B2Target
- A3D_B_GainCurrent
- A3D_B_GainTarget
- A3D_B_HrtfCurrent
- A3D_B_HrtfDelayLine
- A3D_B_HrtfTarget
- A3D_B_ITDCurrent
- A3D_B_ITDTarget
- A3D_B_TAIL
- A3D_FUNCTION
- A3D_MAX_LENGTH
- A3D_MAX_START
- A3D_MAX_STROBE
- A3D_MODE_A3D
- A3D_MODE_OEM
- A3D_MODE_PAN
- A3D_MODE_PXL
- A3D_SLICE_ABReg
- A3D_SLICE_BANK_A
- A3D_SLICE_BANK_B
- A3D_SLICE_CReg
- A3D_SLICE_Control
- A3D_SLICE_DebugReserved
- A3D_SLICE_Pointers
- A3D_SLICE_TAIL
- A3D_SLICE_VDBDest
- A3D_SLICE_VDBSource
- A3E
- A3H
- A3L
- A3P
- A3XX
- A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE
- A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
- A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES
- A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK
- A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT
- A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE
- A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE
- A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE
- A3XX_GRAS_CL_CLIP_CNTL_WCOORD
- A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
- A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
- A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z
- A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE
- A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ
- A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
- A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
- A3XX_GRAS_CL_GB_CLIP_ADJ_VERT
- A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
- A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
- A3XX_GRAS_CL_VPORT_XOFFSET
- A3XX_GRAS_CL_VPORT_XOFFSET__MASK
- A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT
- A3XX_GRAS_CL_VPORT_XSCALE
- A3XX_GRAS_CL_VPORT_XSCALE__MASK
- A3XX_GRAS_CL_VPORT_XSCALE__SHIFT
- A3XX_GRAS_CL_VPORT_YOFFSET
- A3XX_GRAS_CL_VPORT_YOFFSET__MASK
- A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT
- A3XX_GRAS_CL_VPORT_YSCALE
- A3XX_GRAS_CL_VPORT_YSCALE__MASK
- A3XX_GRAS_CL_VPORT_YSCALE__SHIFT
- A3XX_GRAS_CL_VPORT_ZOFFSET
- A3XX_GRAS_CL_VPORT_ZOFFSET__MASK
- A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT
- A3XX_GRAS_CL_VPORT_ZSCALE
- A3XX_GRAS_CL_VPORT_ZSCALE__MASK
- A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT
- A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES
- A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
- A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
- A3XX_GRAS_SC_CONTROL_RASTER_MODE
- A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
- A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
- A3XX_GRAS_SC_CONTROL_RENDER_MODE
- A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
- A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
- A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
- A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
- A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK
- A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT
- A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW
- A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH
- A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
- A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
- A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET
- A3XX_GRAS_SU_POINT_MINMAX_MAX
- A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK
- A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
- A3XX_GRAS_SU_POINT_MINMAX_MIN
- A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK
- A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
- A3XX_GRAS_SU_POINT_SIZE
- A3XX_GRAS_SU_POINT_SIZE__MASK
- A3XX_GRAS_SU_POINT_SIZE__SHIFT
- A3XX_GRAS_SU_POLY_OFFSET_OFFSET
- A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
- A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
- A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL
- A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK
- A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK
- A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT
- A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM
- A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK
- A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK
- A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK
- A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT
- A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE
- A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE
- A3XX_HLSQ_CONTROL_0_REG_CONSTMODE
- A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK
- A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT
- A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC
- A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK
- A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT
- A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX
- A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
- A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE
- A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
- A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
- A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE
- A3XX_HLSQ_CONTROL_0_REG_RESERVED2
- A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT
- A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
- A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
- A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK
- A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT
- A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
- A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE
- A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
- A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
- A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID
- A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK
- A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT
- A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID
- A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK
- A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT
- A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD
- A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
- A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
- A3XX_HLSQ_CONTROL_3_REG_REGID
- A3XX_HLSQ_CONTROL_3_REG_REGID__MASK
- A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT
- A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH
- A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
- A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
- A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET
- A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK
- A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
- A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH
- A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
- A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
- A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH
- A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
- A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
- A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET
- A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK
- A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
- A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH
- A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
- A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
- A3XX_INT0_CACHE_FLUSH_TS
- A3XX_INT0_CP_AHB_ERROR_HALT
- A3XX_INT0_CP_DMA
- A3XX_INT0_CP_HW_FAULT
- A3XX_INT0_CP_IB1_INT
- A3XX_INT0_CP_IB2_INT
- A3XX_INT0_CP_OPCODE_ERROR
- A3XX_INT0_CP_PS_DONE_TS
- A3XX_INT0_CP_RB_DONE_TS
- A3XX_INT0_CP_RB_INT
- A3XX_INT0_CP_REG_PROTECT_FAULT
- A3XX_INT0_CP_RESERVED_BIT_ERROR
- A3XX_INT0_CP_SW_INT
- A3XX_INT0_CP_T0_PACKET_IN_IB
- A3XX_INT0_CP_VS_DONE_TS
- A3XX_INT0_MASK
- A3XX_INT0_MISC_HANG_DETECT
- A3XX_INT0_RBBM_AHB_ERROR
- A3XX_INT0_RBBM_ATB_BUS_OVERFLOW
- A3XX_INT0_RBBM_GPU_IDLE
- A3XX_INT0_RBBM_ME_MS_TIMEOUT
- A3XX_INT0_RBBM_PFP_MS_TIMEOUT
- A3XX_INT0_RBBM_REG_TIMEOUT
- A3XX_INT0_UCHE_OOB_ACCESS
- A3XX_INT0_VFD_ERROR
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK
- A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
- A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
- A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
- A3XX_PC_PRIM_VTX_CNTL_PSIZE
- A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC
- A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK
- A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT
- A3XX_PC_VSTREAM_CONTROL_N
- A3XX_PC_VSTREAM_CONTROL_N__MASK
- A3XX_PC_VSTREAM_CONTROL_N__SHIFT
- A3XX_PC_VSTREAM_CONTROL_SIZE
- A3XX_PC_VSTREAM_CONTROL_SIZE__MASK
- A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT
- A3XX_RBBM_PERFCTR_CTL_ENABLE
- A3XX_RBBM_STATUS_ARB_BUSY
- A3XX_RBBM_STATUS_CP_ME_BUSY
- A3XX_RBBM_STATUS_CP_NRT_BUSY
- A3XX_RBBM_STATUS_CP_PFP_BUSY
- A3XX_RBBM_STATUS_GPU_BUSY
- A3XX_RBBM_STATUS_GPU_BUSY_NOHC
- A3XX_RBBM_STATUS_HI_BUSY
- A3XX_RBBM_STATUS_HLSQ_BUSY
- A3XX_RBBM_STATUS_MARB_BUSY
- A3XX_RBBM_STATUS_PC_DCALL_BUSY
- A3XX_RBBM_STATUS_PC_VSD_BUSY
- A3XX_RBBM_STATUS_RAS_BUSY
- A3XX_RBBM_STATUS_RB_BUSY
- A3XX_RBBM_STATUS_SP_BUSY
- A3XX_RBBM_STATUS_TPL1_BUSY
- A3XX_RBBM_STATUS_TSE_BUSY
- A3XX_RBBM_STATUS_UCHE_BUSY
- A3XX_RBBM_STATUS_VBIF_BUSY
- A3XX_RBBM_STATUS_VFD_BUSY
- A3XX_RBBM_STATUS_VPC_BUSY
- A3XX_RBBM_STATUS_VSC_BUSY
- A3XX_RB_ALPHA_REF_FLOAT
- A3XX_RB_ALPHA_REF_FLOAT__MASK
- A3XX_RB_ALPHA_REF_FLOAT__SHIFT
- A3XX_RB_ALPHA_REF_UINT
- A3XX_RB_ALPHA_REF_UINT__MASK
- A3XX_RB_ALPHA_REF_UINT__SHIFT
- A3XX_RB_BLEND_ALPHA_FLOAT
- A3XX_RB_BLEND_ALPHA_FLOAT__MASK
- A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT
- A3XX_RB_BLEND_ALPHA_UINT
- A3XX_RB_BLEND_ALPHA_UINT__MASK
- A3XX_RB_BLEND_ALPHA_UINT__SHIFT
- A3XX_RB_BLEND_BLUE_FLOAT
- A3XX_RB_BLEND_BLUE_FLOAT__MASK
- A3XX_RB_BLEND_BLUE_FLOAT__SHIFT
- A3XX_RB_BLEND_BLUE_UINT
- A3XX_RB_BLEND_BLUE_UINT__MASK
- A3XX_RB_BLEND_BLUE_UINT__SHIFT
- A3XX_RB_BLEND_GREEN_FLOAT
- A3XX_RB_BLEND_GREEN_FLOAT__MASK
- A3XX_RB_BLEND_GREEN_FLOAT__SHIFT
- A3XX_RB_BLEND_GREEN_UINT
- A3XX_RB_BLEND_GREEN_UINT__MASK
- A3XX_RB_BLEND_GREEN_UINT__SHIFT
- A3XX_RB_BLEND_RED_FLOAT
- A3XX_RB_BLEND_RED_FLOAT__MASK
- A3XX_RB_BLEND_RED_FLOAT__SHIFT
- A3XX_RB_BLEND_RED_UINT
- A3XX_RB_BLEND_RED_UINT__MASK
- A3XX_RB_BLEND_RED_UINT__SHIFT
- A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE
- A3XX_RB_COPY_CONTROL_DEPTHCLEAR
- A3XX_RB_COPY_CONTROL_FASTCLEAR
- A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK
- A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT
- A3XX_RB_COPY_CONTROL_GMEM_BASE
- A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK
- A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
- A3XX_RB_COPY_CONTROL_MODE
- A3XX_RB_COPY_CONTROL_MODE__MASK
- A3XX_RB_COPY_CONTROL_MODE__SHIFT
- A3XX_RB_COPY_CONTROL_MSAA_RESOLVE
- A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
- A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
- A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE
- A3XX_RB_COPY_DEST_BASE_BASE
- A3XX_RB_COPY_DEST_BASE_BASE__MASK
- A3XX_RB_COPY_DEST_BASE_BASE__SHIFT
- A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE
- A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
- A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
- A3XX_RB_COPY_DEST_INFO_DITHER_MODE
- A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK
- A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT
- A3XX_RB_COPY_DEST_INFO_ENDIAN
- A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK
- A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
- A3XX_RB_COPY_DEST_INFO_FORMAT
- A3XX_RB_COPY_DEST_INFO_FORMAT__MASK
- A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
- A3XX_RB_COPY_DEST_INFO_SWAP
- A3XX_RB_COPY_DEST_INFO_SWAP__MASK
- A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT
- A3XX_RB_COPY_DEST_INFO_TILE
- A3XX_RB_COPY_DEST_INFO_TILE__MASK
- A3XX_RB_COPY_DEST_INFO_TILE__SHIFT
- A3XX_RB_COPY_DEST_PITCH_PITCH
- A3XX_RB_COPY_DEST_PITCH_PITCH__MASK
- A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
- A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
- A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
- A3XX_RB_DEPTH_CONTROL_ZFUNC
- A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK
- A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
- A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
- A3XX_RB_DEPTH_CONTROL_Z_ENABLE
- A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE
- A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
- A3XX_RB_DEPTH_INFO_DEPTH_BASE
- A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
- A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
- A3XX_RB_DEPTH_INFO_DEPTH_FORMAT
- A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
- A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
- A3XX_RB_DEPTH_PITCH
- A3XX_RB_DEPTH_PITCH__MASK
- A3XX_RB_DEPTH_PITCH__SHIFT
- A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT
- A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK
- A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT
- A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH
- A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK
- A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT
- A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE
- A3XX_RB_MODE_CONTROL_GMEM_BYPASS
- A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE
- A3XX_RB_MODE_CONTROL_MRT
- A3XX_RB_MODE_CONTROL_MRT__MASK
- A3XX_RB_MODE_CONTROL_MRT__SHIFT
- A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE
- A3XX_RB_MODE_CONTROL_RENDER_MODE
- A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
- A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
- A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
- A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE
- A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
- A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR
- A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
- A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
- A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR
- A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
- A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
- A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE
- A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK
- A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT
- A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH
- A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
- A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
- A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT
- A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
- A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
- A3XX_RB_MRT_BUF_INFO_COLOR_SRGB
- A3XX_RB_MRT_BUF_INFO_COLOR_SWAP
- A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
- A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
- A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE
- A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
- A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
- A3XX_RB_MRT_CONTROL_BLEND
- A3XX_RB_MRT_CONTROL_BLEND2
- A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE
- A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
- A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
- A3XX_RB_MRT_CONTROL_DITHER_MODE
- A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
- A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT
- A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
- A3XX_RB_MRT_CONTROL_ROP_CODE
- A3XX_RB_MRT_CONTROL_ROP_CODE__MASK
- A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
- A3XX_RB_MSAA_CONTROL_DISABLE
- A3XX_RB_MSAA_CONTROL_SAMPLES
- A3XX_RB_MSAA_CONTROL_SAMPLES__MASK
- A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
- A3XX_RB_MSAA_CONTROL_SAMPLE_MASK
- A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK
- A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT
- A3XX_RB_RENDER_CONTROL_ALPHA_TEST
- A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC
- A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK
- A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT
- A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE
- A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE
- A3XX_RB_RENDER_CONTROL_BIN_WIDTH
- A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK
- A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT
- A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE
- A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE
- A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
- A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
- A3XX_RB_RENDER_CONTROL_ENABLE_GMEM
- A3XX_RB_RENDER_CONTROL_FACENESS
- A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE
- A3XX_RB_RENDER_CONTROL_WCOORD
- A3XX_RB_RENDER_CONTROL_XCOORD
- A3XX_RB_RENDER_CONTROL_YCOORD
- A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE
- A3XX_RB_RENDER_CONTROL_ZCOORD
- A3XX_RB_SAMPLE_COUNT_CONTROL_COPY
- A3XX_RB_SAMPLE_COUNT_CONTROL_RESET
- A3XX_RB_STENCILREFMASK_BF_STENCILMASK
- A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
- A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
- A3XX_RB_STENCILREFMASK_BF_STENCILREF
- A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
- A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
- A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK
- A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
- A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
- A3XX_RB_STENCILREFMASK_STENCILMASK
- A3XX_RB_STENCILREFMASK_STENCILMASK__MASK
- A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
- A3XX_RB_STENCILREFMASK_STENCILREF
- A3XX_RB_STENCILREFMASK_STENCILREF__MASK
- A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT
- A3XX_RB_STENCILREFMASK_STENCILWRITEMASK
- A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
- A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
- A3XX_RB_STENCIL_CONTROL_FAIL
- A3XX_RB_STENCIL_CONTROL_FAIL_BF
- A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
- A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
- A3XX_RB_STENCIL_CONTROL_FAIL__MASK
- A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT
- A3XX_RB_STENCIL_CONTROL_FUNC
- A3XX_RB_STENCIL_CONTROL_FUNC_BF
- A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
- A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
- A3XX_RB_STENCIL_CONTROL_FUNC__MASK
- A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT
- A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
- A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
- A3XX_RB_STENCIL_CONTROL_STENCIL_READ
- A3XX_RB_STENCIL_CONTROL_ZFAIL
- A3XX_RB_STENCIL_CONTROL_ZFAIL_BF
- A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
- A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
- A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK
- A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
- A3XX_RB_STENCIL_CONTROL_ZPASS
- A3XX_RB_STENCIL_CONTROL_ZPASS_BF
- A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
- A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
- A3XX_RB_STENCIL_CONTROL_ZPASS__MASK
- A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
- A3XX_RB_STENCIL_INFO_STENCIL_BASE
- A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK
- A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT
- A3XX_RB_STENCIL_PITCH
- A3XX_RB_STENCIL_PITCH__MASK
- A3XX_RB_STENCIL_PITCH__SHIFT
- A3XX_RB_WINDOW_OFFSET_X
- A3XX_RB_WINDOW_OFFSET_X__MASK
- A3XX_RB_WINDOW_OFFSET_X__SHIFT
- A3XX_RB_WINDOW_OFFSET_Y
- A3XX_RB_WINDOW_OFFSET_Y__MASK
- A3XX_RB_WINDOW_OFFSET_Y__SHIFT
- A3XX_SP_FS_CTRL_REG0_ALUSCHMODE
- A3XX_SP_FS_CTRL_REG0_CACHEINVALID
- A3XX_SP_FS_CTRL_REG0_COMPUTEMODE
- A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE
- A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT
- A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT
- A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP
- A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE
- A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK
- A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
- A3XX_SP_FS_CTRL_REG0_LENGTH
- A3XX_SP_FS_CTRL_REG0_LENGTH__MASK
- A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT
- A3XX_SP_FS_CTRL_REG0_OUTORDERED
- A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
- A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
- A3XX_SP_FS_CTRL_REG0_THREADMODE
- A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK
- A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
- A3XX_SP_FS_CTRL_REG0_THREADSIZE
- A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
- A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
- A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT
- A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK
- A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
- A3XX_SP_FS_CTRL_REG1_CONSTLENGTH
- A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
- A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
- A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET
- A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK
- A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT
- A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING
- A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK
- A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
- A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT
- A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK
- A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT
- A3XX_SP_FS_LENGTH_REG_SHADERLENGTH
- A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK
- A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT
- A3XX_SP_FS_MRT_REG_HALF_PRECISION
- A3XX_SP_FS_MRT_REG_REGID
- A3XX_SP_FS_MRT_REG_REGID__MASK
- A3XX_SP_FS_MRT_REG_REGID__SHIFT
- A3XX_SP_FS_MRT_REG_SINT
- A3XX_SP_FS_MRT_REG_UINT
- A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET
- A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK
- A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT
- A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
- A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID
- A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK
- A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT
- A3XX_SP_FS_OUTPUT_REG_MRT
- A3XX_SP_FS_OUTPUT_REG_MRT__MASK
- A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT
- A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN
- A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK
- A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT
- A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS
- A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK
- A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK
- A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT
- A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM
- A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK
- A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT
- A3XX_SP_SP_CTRL_REG_BINNING
- A3XX_SP_SP_CTRL_REG_CONSTMODE
- A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK
- A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT
- A3XX_SP_SP_CTRL_REG_L0MODE
- A3XX_SP_SP_CTRL_REG_L0MODE__MASK
- A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT
- A3XX_SP_SP_CTRL_REG_RESOLVE
- A3XX_SP_SP_CTRL_REG_SLEEPMODE
- A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK
- A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT
- A3XX_SP_VS_CTRL_REG0_ALUSCHMODE
- A3XX_SP_VS_CTRL_REG0_CACHEINVALID
- A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT
- A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT
- A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE
- A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK
- A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
- A3XX_SP_VS_CTRL_REG0_LENGTH
- A3XX_SP_VS_CTRL_REG0_LENGTH__MASK
- A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT
- A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
- A3XX_SP_VS_CTRL_REG0_THREADMODE
- A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK
- A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
- A3XX_SP_VS_CTRL_REG0_THREADSIZE
- A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
- A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
- A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT
- A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK
- A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
- A3XX_SP_VS_CTRL_REG1_CONSTLENGTH
- A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
- A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
- A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING
- A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
- A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
- A3XX_SP_VS_LENGTH_REG_SHADERLENGTH
- A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK
- A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT
- A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET
- A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK
- A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT
- A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A3XX_SP_VS_OUT_REG_A_COMPMASK
- A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK
- A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
- A3XX_SP_VS_OUT_REG_A_HALF
- A3XX_SP_VS_OUT_REG_A_REGID
- A3XX_SP_VS_OUT_REG_A_REGID__MASK
- A3XX_SP_VS_OUT_REG_A_REGID__SHIFT
- A3XX_SP_VS_OUT_REG_B_COMPMASK
- A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK
- A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
- A3XX_SP_VS_OUT_REG_B_HALF
- A3XX_SP_VS_OUT_REG_B_REGID
- A3XX_SP_VS_OUT_REG_B_REGID__MASK
- A3XX_SP_VS_OUT_REG_B_REGID__SHIFT
- A3XX_SP_VS_PARAM_REG_POS2DMODE
- A3XX_SP_VS_PARAM_REG_POSREGID
- A3XX_SP_VS_PARAM_REG_POSREGID__MASK
- A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT
- A3XX_SP_VS_PARAM_REG_PSIZEREGID
- A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
- A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
- A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR
- A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
- A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
- A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN
- A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK
- A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT
- A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS
- A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK
- A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK
- A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT
- A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM
- A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK
- A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT
- A3XX_SP_VS_VPC_DST_REG_OUTLOC0
- A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
- A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
- A3XX_SP_VS_VPC_DST_REG_OUTLOC1
- A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
- A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
- A3XX_SP_VS_VPC_DST_REG_OUTLOC2
- A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
- A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
- A3XX_SP_VS_VPC_DST_REG_OUTLOC3
- A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
- A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
- A3XX_TEX_1D
- A3XX_TEX_2D
- A3XX_TEX_3D
- A3XX_TEX_ANISO
- A3XX_TEX_ANISO_1
- A3XX_TEX_ANISO_16
- A3XX_TEX_ANISO_2
- A3XX_TEX_ANISO_4
- A3XX_TEX_ANISO_8
- A3XX_TEX_CLAMP_TO_BORDER
- A3XX_TEX_CLAMP_TO_EDGE
- A3XX_TEX_CONST_0_FMT
- A3XX_TEX_CONST_0_FMT__MASK
- A3XX_TEX_CONST_0_FMT__SHIFT
- A3XX_TEX_CONST_0_MIPLVLS
- A3XX_TEX_CONST_0_MIPLVLS__MASK
- A3XX_TEX_CONST_0_MIPLVLS__SHIFT
- A3XX_TEX_CONST_0_MSAATEX
- A3XX_TEX_CONST_0_MSAATEX__MASK
- A3XX_TEX_CONST_0_MSAATEX__SHIFT
- A3XX_TEX_CONST_0_NOCONVERT
- A3XX_TEX_CONST_0_SRGB
- A3XX_TEX_CONST_0_SWIZ_W
- A3XX_TEX_CONST_0_SWIZ_W__MASK
- A3XX_TEX_CONST_0_SWIZ_W__SHIFT
- A3XX_TEX_CONST_0_SWIZ_X
- A3XX_TEX_CONST_0_SWIZ_X__MASK
- A3XX_TEX_CONST_0_SWIZ_X__SHIFT
- A3XX_TEX_CONST_0_SWIZ_Y
- A3XX_TEX_CONST_0_SWIZ_Y__MASK
- A3XX_TEX_CONST_0_SWIZ_Y__SHIFT
- A3XX_TEX_CONST_0_SWIZ_Z
- A3XX_TEX_CONST_0_SWIZ_Z__MASK
- A3XX_TEX_CONST_0_SWIZ_Z__SHIFT
- A3XX_TEX_CONST_0_TILED
- A3XX_TEX_CONST_0_TYPE
- A3XX_TEX_CONST_0_TYPE__MASK
- A3XX_TEX_CONST_0_TYPE__SHIFT
- A3XX_TEX_CONST_1_FETCHSIZE
- A3XX_TEX_CONST_1_FETCHSIZE__MASK
- A3XX_TEX_CONST_1_FETCHSIZE__SHIFT
- A3XX_TEX_CONST_1_HEIGHT
- A3XX_TEX_CONST_1_HEIGHT__MASK
- A3XX_TEX_CONST_1_HEIGHT__SHIFT
- A3XX_TEX_CONST_1_WIDTH
- A3XX_TEX_CONST_1_WIDTH__MASK
- A3XX_TEX_CONST_1_WIDTH__SHIFT
- A3XX_TEX_CONST_2_INDX
- A3XX_TEX_CONST_2_INDX__MASK
- A3XX_TEX_CONST_2_INDX__SHIFT
- A3XX_TEX_CONST_2_PITCH
- A3XX_TEX_CONST_2_PITCH__MASK
- A3XX_TEX_CONST_2_PITCH__SHIFT
- A3XX_TEX_CONST_2_SWAP
- A3XX_TEX_CONST_2_SWAP__MASK
- A3XX_TEX_CONST_2_SWAP__SHIFT
- A3XX_TEX_CONST_3_DEPTH
- A3XX_TEX_CONST_3_DEPTH__MASK
- A3XX_TEX_CONST_3_DEPTH__SHIFT
- A3XX_TEX_CONST_3_LAYERSZ1
- A3XX_TEX_CONST_3_LAYERSZ1__MASK
- A3XX_TEX_CONST_3_LAYERSZ1__SHIFT
- A3XX_TEX_CONST_3_LAYERSZ2
- A3XX_TEX_CONST_3_LAYERSZ2__MASK
- A3XX_TEX_CONST_3_LAYERSZ2__SHIFT
- A3XX_TEX_CUBE
- A3XX_TEX_LINEAR
- A3XX_TEX_MIRROR_CLAMP
- A3XX_TEX_MIRROR_REPEAT
- A3XX_TEX_NEAREST
- A3XX_TEX_ONE
- A3XX_TEX_REPEAT
- A3XX_TEX_SAMP_0_ANISO
- A3XX_TEX_SAMP_0_ANISO__MASK
- A3XX_TEX_SAMP_0_ANISO__SHIFT
- A3XX_TEX_SAMP_0_CLAMPENABLE
- A3XX_TEX_SAMP_0_COMPARE_FUNC
- A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK
- A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT
- A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF
- A3XX_TEX_SAMP_0_MIPFILTER_LINEAR
- A3XX_TEX_SAMP_0_UNNORM_COORDS
- A3XX_TEX_SAMP_0_WRAP_R
- A3XX_TEX_SAMP_0_WRAP_R__MASK
- A3XX_TEX_SAMP_0_WRAP_R__SHIFT
- A3XX_TEX_SAMP_0_WRAP_S
- A3XX_TEX_SAMP_0_WRAP_S__MASK
- A3XX_TEX_SAMP_0_WRAP_S__SHIFT
- A3XX_TEX_SAMP_0_WRAP_T
- A3XX_TEX_SAMP_0_WRAP_T__MASK
- A3XX_TEX_SAMP_0_WRAP_T__SHIFT
- A3XX_TEX_SAMP_0_XY_MAG
- A3XX_TEX_SAMP_0_XY_MAG__MASK
- A3XX_TEX_SAMP_0_XY_MAG__SHIFT
- A3XX_TEX_SAMP_0_XY_MIN
- A3XX_TEX_SAMP_0_XY_MIN__MASK
- A3XX_TEX_SAMP_0_XY_MIN__SHIFT
- A3XX_TEX_SAMP_1_LOD_BIAS
- A3XX_TEX_SAMP_1_LOD_BIAS__MASK
- A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT
- A3XX_TEX_SAMP_1_MAX_LOD
- A3XX_TEX_SAMP_1_MAX_LOD__MASK
- A3XX_TEX_SAMP_1_MAX_LOD__SHIFT
- A3XX_TEX_SAMP_1_MIN_LOD
- A3XX_TEX_SAMP_1_MIN_LOD__MASK
- A3XX_TEX_SAMP_1_MIN_LOD__SHIFT
- A3XX_TEX_W
- A3XX_TEX_X
- A3XX_TEX_Y
- A3XX_TEX_Z
- A3XX_TEX_ZERO
- A3XX_TPL1_MSAA1X
- A3XX_TPL1_MSAA2X
- A3XX_TPL1_MSAA4X
- A3XX_TPL1_MSAA8X
- A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR
- A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK
- A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT
- A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET
- A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK
- A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
- A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET
- A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK
- A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
- A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR
- A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK
- A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT
- A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET
- A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK
- A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
- A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET
- A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK
- A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
- A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR
- A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK
- A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT
- A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR
- A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK
- A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT
- A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE
- A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE
- A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK
- A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT
- A3XX_VBIF_PERF_CNT_CLR_CNT0
- A3XX_VBIF_PERF_CNT_CLR_CNT1
- A3XX_VBIF_PERF_CNT_CLR_PWRCNT0
- A3XX_VBIF_PERF_CNT_CLR_PWRCNT1
- A3XX_VBIF_PERF_CNT_CLR_PWRCNT2
- A3XX_VBIF_PERF_CNT_EN_CNT0
- A3XX_VBIF_PERF_CNT_EN_CNT1
- A3XX_VBIF_PERF_CNT_EN_PWRCNT0
- A3XX_VBIF_PERF_CNT_EN_PWRCNT1
- A3XX_VBIF_PERF_CNT_EN_PWRCNT2
- A3XX_VFD_CONTROL_0_PACKETSIZE
- A3XX_VFD_CONTROL_0_PACKETSIZE__MASK
- A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT
- A3XX_VFD_CONTROL_0_STRMDECINSTRCNT
- A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
- A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
- A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT
- A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
- A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
- A3XX_VFD_CONTROL_0_TOTALATTRTOVS
- A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
- A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
- A3XX_VFD_CONTROL_1_MAXSTORAGE
- A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK
- A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
- A3XX_VFD_CONTROL_1_MAXTHRESHOLD
- A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK
- A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT
- A3XX_VFD_CONTROL_1_MINTHRESHOLD
- A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK
- A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT
- A3XX_VFD_CONTROL_1_REGID4INST
- A3XX_VFD_CONTROL_1_REGID4INST__MASK
- A3XX_VFD_CONTROL_1_REGID4INST__SHIFT
- A3XX_VFD_CONTROL_1_REGID4VTX
- A3XX_VFD_CONTROL_1_REGID4VTX__MASK
- A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT
- A3XX_VFD_DECODE_INSTR_CONSTFILL
- A3XX_VFD_DECODE_INSTR_FORMAT
- A3XX_VFD_DECODE_INSTR_FORMAT__MASK
- A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT
- A3XX_VFD_DECODE_INSTR_INT
- A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
- A3XX_VFD_DECODE_INSTR_REGID
- A3XX_VFD_DECODE_INSTR_REGID__MASK
- A3XX_VFD_DECODE_INSTR_REGID__SHIFT
- A3XX_VFD_DECODE_INSTR_SHIFTCNT
- A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
- A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
- A3XX_VFD_DECODE_INSTR_SWAP
- A3XX_VFD_DECODE_INSTR_SWAP__MASK
- A3XX_VFD_DECODE_INSTR_SWAP__SHIFT
- A3XX_VFD_DECODE_INSTR_SWITCHNEXT
- A3XX_VFD_DECODE_INSTR_WRITEMASK
- A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK
- A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
- A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE
- A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
- A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
- A3XX_VFD_FETCH_INSTR_0_FETCHSIZE
- A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
- A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
- A3XX_VFD_FETCH_INSTR_0_INDEXCODE
- A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK
- A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT
- A3XX_VFD_FETCH_INSTR_0_INSTANCED
- A3XX_VFD_FETCH_INSTR_0_STEPRATE
- A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK
- A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT
- A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK
- A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT
- A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE
- A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK
- A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT
- A3XX_VGT_DRAW_INITIATOR_NOT_EOP
- A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES
- A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK
- A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT
- A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE
- A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE
- A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK
- A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT
- A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX
- A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT
- A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK
- A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT
- A3XX_VGT_DRAW_INITIATOR_VIS_CULL
- A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK
- A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT
- A3XX_VPC_ATTR_LMSIZE
- A3XX_VPC_ATTR_LMSIZE__MASK
- A3XX_VPC_ATTR_LMSIZE__SHIFT
- A3XX_VPC_ATTR_PSIZE
- A3XX_VPC_ATTR_THRDASSIGN
- A3XX_VPC_ATTR_THRDASSIGN__MASK
- A3XX_VPC_ATTR_THRDASSIGN__SHIFT
- A3XX_VPC_ATTR_TOTALATTR
- A3XX_VPC_ATTR_TOTALATTR__MASK
- A3XX_VPC_ATTR_TOTALATTR__SHIFT
- A3XX_VPC_PACK_NUMFPNONPOSVAR
- A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK
- A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
- A3XX_VPC_PACK_NUMNONPOSVSVAR
- A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK
- A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C0
- A3XX_VPC_VARYING_INTERP_MODE_C0__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C1
- A3XX_VPC_VARYING_INTERP_MODE_C1__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C2
- A3XX_VPC_VARYING_INTERP_MODE_C2__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C3
- A3XX_VPC_VARYING_INTERP_MODE_C3__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C4
- A3XX_VPC_VARYING_INTERP_MODE_C4__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C5
- A3XX_VPC_VARYING_INTERP_MODE_C5__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C6
- A3XX_VPC_VARYING_INTERP_MODE_C6__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C7
- A3XX_VPC_VARYING_INTERP_MODE_C7__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C8
- A3XX_VPC_VARYING_INTERP_MODE_C8__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_C9
- A3XX_VPC_VARYING_INTERP_MODE_C9__MASK
- A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CA
- A3XX_VPC_VARYING_INTERP_MODE_CA__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CB
- A3XX_VPC_VARYING_INTERP_MODE_CB__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CC
- A3XX_VPC_VARYING_INTERP_MODE_CC__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CD
- A3XX_VPC_VARYING_INTERP_MODE_CD__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CE
- A3XX_VPC_VARYING_INTERP_MODE_CE__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT
- A3XX_VPC_VARYING_INTERP_MODE_CF
- A3XX_VPC_VARYING_INTERP_MODE_CF__MASK
- A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C0
- A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C1
- A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C2
- A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C3
- A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C4
- A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C5
- A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C6
- A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C7
- A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C8
- A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_C9
- A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CA
- A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CB
- A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CC
- A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CD
- A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CE
- A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT
- A3XX_VPC_VARYING_PS_REPL_MODE_CF
- A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK
- A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT
- A3XX_VSC_BIN_CONTROL_BINNING_ENABLE
- A3XX_VSC_BIN_SIZE_HEIGHT
- A3XX_VSC_BIN_SIZE_HEIGHT__MASK
- A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT
- A3XX_VSC_BIN_SIZE_WIDTH
- A3XX_VSC_BIN_SIZE_WIDTH__MASK
- A3XX_VSC_BIN_SIZE_WIDTH__SHIFT
- A3XX_VSC_PIPE_CONFIG_H
- A3XX_VSC_PIPE_CONFIG_H__MASK
- A3XX_VSC_PIPE_CONFIG_H__SHIFT
- A3XX_VSC_PIPE_CONFIG_W
- A3XX_VSC_PIPE_CONFIG_W__MASK
- A3XX_VSC_PIPE_CONFIG_W__SHIFT
- A3XX_VSC_PIPE_CONFIG_X
- A3XX_VSC_PIPE_CONFIG_X__MASK
- A3XX_VSC_PIPE_CONFIG_X__SHIFT
- A3XX_VSC_PIPE_CONFIG_Y
- A3XX_VSC_PIPE_CONFIG_Y__MASK
- A3XX_VSC_PIPE_CONFIG_Y__SHIFT
- A3XX_XML
- A3_EMU32IN
- A3_EMU32OUT
- A3_MARK
- A4
- A4000T_SCSI_OFFSET
- A4XX
- A4XX_CGC_HLSQ_EARLY_CYC
- A4XX_CGC_HLSQ_EARLY_CYC__MASK
- A4XX_CGC_HLSQ_EARLY_CYC__SHIFT
- A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE
- A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK
- A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT
- A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE
- A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK
- A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT
- A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT
- A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK
- A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT
- A4XX_CP_DRAW_INDIRECT_0_TESS_MODE
- A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK
- A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT
- A4XX_CP_DRAW_INDIRECT_0_VIS_CULL
- A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK
- A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT
- A4XX_CP_DRAW_INDIRECT_1_INDIRECT
- A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK
- A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE
- A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE
- A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT
- A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE
- A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL
- A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE
- A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE
- A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT
- A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT
- A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK
- A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT
- A4XX_CP_EXEC_CS_INDIRECT_1_ADDR
- A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK
- A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK
- A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT
- A4XX_CP_PROTECT_REG_BASE_ADDR
- A4XX_CP_PROTECT_REG_BASE_ADDR__MASK
- A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT
- A4XX_CP_PROTECT_REG_MASK_LEN
- A4XX_CP_PROTECT_REG_MASK_LEN__MASK
- A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT
- A4XX_CP_PROTECT_REG_TRAP_READ
- A4XX_CP_PROTECT_REG_TRAP_WRITE
- A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
- A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
- A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
- A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE
- A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z
- A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE
- A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE
- A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ
- A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
- A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
- A4XX_GRAS_CL_GB_CLIP_ADJ_VERT
- A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
- A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
- A4XX_GRAS_CL_VPORT_XOFFSET_0
- A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK
- A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT
- A4XX_GRAS_CL_VPORT_XSCALE_0
- A4XX_GRAS_CL_VPORT_XSCALE_0__MASK
- A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT
- A4XX_GRAS_CL_VPORT_YOFFSET_0
- A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK
- A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT
- A4XX_GRAS_CL_VPORT_YSCALE_0
- A4XX_GRAS_CL_VPORT_YSCALE_0__MASK
- A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT
- A4XX_GRAS_CL_VPORT_ZOFFSET_0
- A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK
- A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT
- A4XX_GRAS_CL_VPORT_ZSCALE_0
- A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK
- A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT
- A4XX_GRAS_DEPTH_CONTROL_FORMAT
- A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK
- A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT
- A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
- A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES
- A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
- A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
- A4XX_GRAS_SC_CONTROL_RASTER_MODE
- A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
- A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
- A4XX_GRAS_SC_CONTROL_RENDER_MODE
- A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
- A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_X
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK
- A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_X
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK
- A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
- A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
- A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
- A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
- A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
- A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK
- A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT
- A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW
- A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH
- A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
- A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
- A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE
- A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET
- A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
- A4XX_GRAS_SU_POINT_MINMAX_MAX
- A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK
- A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
- A4XX_GRAS_SU_POINT_MINMAX_MIN
- A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK
- A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
- A4XX_GRAS_SU_POINT_SIZE
- A4XX_GRAS_SU_POINT_SIZE__MASK
- A4XX_GRAS_SU_POINT_SIZE__SHIFT
- A4XX_GRAS_SU_POLY_OFFSET_CLAMP
- A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK
- A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT
- A4XX_GRAS_SU_POLY_OFFSET_OFFSET
- A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
- A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
- A4XX_GRAS_SU_POLY_OFFSET_SCALE
- A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
- A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT
- A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID
- A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK
- A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT
- A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID
- A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK
- A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT
- A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM
- A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK
- A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK
- A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT
- A4XX_HLSQ_CL_NDRANGE_1_SIZE_X
- A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK
- A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT
- A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y
- A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK
- A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT
- A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z
- A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK
- A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT
- A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE
- A4XX_HLSQ_CONTROL_0_REG_CONSTMODE
- A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK
- A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT
- A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
- A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE
- A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
- A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
- A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE
- A4XX_HLSQ_CONTROL_0_REG_RESERVED2
- A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT
- A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
- A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
- A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE
- A4XX_HLSQ_CONTROL_1_REG_COORDREGID
- A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK
- A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT
- A4XX_HLSQ_CONTROL_1_REG_RESERVED1
- A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
- A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE
- A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
- A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
- A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID
- A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK
- A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT
- A4XX_HLSQ_CONTROL_2_REG_FACEREGID
- A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
- A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT
- A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD
- A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
- A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK
- A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT
- A4XX_HLSQ_CONTROL_3_REG_REGID
- A4XX_HLSQ_CONTROL_3_REG_REGID__MASK
- A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT
- A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_CS_CONTROL_REG_ENABLED
- A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE
- A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_DS_CONTROL_REG_ENABLED
- A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE
- A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_FS_CONTROL_REG_ENABLED
- A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE
- A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_GS_CONTROL_REG_ENABLED
- A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE
- A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_HS_CONTROL_REG_ENABLED
- A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE
- A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH
- A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
- A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
- A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET
- A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
- A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_HLSQ_VS_CONTROL_REG_ENABLED
- A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH
- A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
- A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
- A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET
- A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK
- A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
- A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE
- A4XX_INT0_CACHE_FLUSH_TS
- A4XX_INT0_CP_AHB_ERROR_HALT
- A4XX_INT0_CP_DMA
- A4XX_INT0_CP_HW_FAULT
- A4XX_INT0_CP_IB1_INT
- A4XX_INT0_CP_IB2_INT
- A4XX_INT0_CP_OPCODE_ERROR
- A4XX_INT0_CP_PS_DONE_TS
- A4XX_INT0_CP_RB_DONE_TS
- A4XX_INT0_CP_RB_INT
- A4XX_INT0_CP_REG_PROTECT_FAULT
- A4XX_INT0_CP_RESERVED_BIT_ERROR
- A4XX_INT0_CP_SW_INT
- A4XX_INT0_CP_T0_PACKET_IN_IB
- A4XX_INT0_CP_VS_DONE_TS
- A4XX_INT0_MASK
- A4XX_INT0_MISC_HANG_DETECT
- A4XX_INT0_RBBM_AHB_ERROR
- A4XX_INT0_RBBM_ATB_BUS_OVERFLOW
- A4XX_INT0_RBBM_GPU_IDLE
- A4XX_INT0_RBBM_ME_MS_TIMEOUT
- A4XX_INT0_RBBM_PFP_MS_TIMEOUT
- A4XX_INT0_RBBM_REG_TIMEOUT
- A4XX_INT0_UCHE_OOB_ACCESS
- A4XX_INT0_VFD_ERROR
- A4XX_PC_BINNING_COMMAND_BINNING_ENABLE
- A4XX_PC_GS_PARAM_INVOCATIONS
- A4XX_PC_GS_PARAM_INVOCATIONS__MASK
- A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT
- A4XX_PC_GS_PARAM_LAYER
- A4XX_PC_GS_PARAM_MAX_VERTICES
- A4XX_PC_GS_PARAM_MAX_VERTICES__MASK
- A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT
- A4XX_PC_GS_PARAM_PRIMTYPE
- A4XX_PC_GS_PARAM_PRIMTYPE__MASK
- A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT
- A4XX_PC_HS_PARAM_CONNECTED
- A4XX_PC_HS_PARAM_CW
- A4XX_PC_HS_PARAM_SPACING
- A4XX_PC_HS_PARAM_SPACING__MASK
- A4XX_PC_HS_PARAM_SPACING__SHIFT
- A4XX_PC_HS_PARAM_VERTICES_OUT
- A4XX_PC_HS_PARAM_VERTICES_OUT__MASK
- A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK
- A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT
- A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
- A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
- A4XX_PC_PRIM_VTX_CNTL_PSIZE
- A4XX_PC_PRIM_VTX_CNTL_VAROUT
- A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK
- A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT
- A4XX_PC_VSTREAM_CONTROL_N
- A4XX_PC_VSTREAM_CONTROL_N__MASK
- A4XX_PC_VSTREAM_CONTROL_N__SHIFT
- A4XX_PC_VSTREAM_CONTROL_SIZE
- A4XX_PC_VSTREAM_CONTROL_SIZE__MASK
- A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT
- A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON
- A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE
- A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON
- A4XX_RBBM_STATUS_ARB_BUSY
- A4XX_RBBM_STATUS_CP_ME_BUSY
- A4XX_RBBM_STATUS_CP_NRT_BUSY
- A4XX_RBBM_STATUS_CP_PFP_BUSY
- A4XX_RBBM_STATUS_GPU_BUSY
- A4XX_RBBM_STATUS_GPU_BUSY_NOHC
- A4XX_RBBM_STATUS_HI_BUSY
- A4XX_RBBM_STATUS_HLSQ_BUSY
- A4XX_RBBM_STATUS_MARB_BUSY
- A4XX_RBBM_STATUS_PC_DCALL_BUSY
- A4XX_RBBM_STATUS_PC_VSD_BUSY
- A4XX_RBBM_STATUS_RAS_BUSY
- A4XX_RBBM_STATUS_RB_BUSY
- A4XX_RBBM_STATUS_SP_BUSY
- A4XX_RBBM_STATUS_TPL1_BUSY
- A4XX_RBBM_STATUS_TSE_BUSY
- A4XX_RBBM_STATUS_UCHE_BUSY
- A4XX_RBBM_STATUS_VBIF_BUSY
- A4XX_RBBM_STATUS_VFD_BUSY
- A4XX_RBBM_STATUS_VPC_BUSY
- A4XX_RBBM_STATUS_VSC_BUSY
- A4XX_RB_ALPHA_CONTROL_ALPHA_REF
- A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
- A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT
- A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
- A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC
- A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
- A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT
- A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE
- A4XX_RB_BIN_OFFSET_X
- A4XX_RB_BIN_OFFSET_X__MASK
- A4XX_RB_BIN_OFFSET_X__SHIFT
- A4XX_RB_BIN_OFFSET_Y
- A4XX_RB_BIN_OFFSET_Y__MASK
- A4XX_RB_BIN_OFFSET_Y__SHIFT
- A4XX_RB_BLEND_ALPHA_F32
- A4XX_RB_BLEND_ALPHA_F32__MASK
- A4XX_RB_BLEND_ALPHA_F32__SHIFT
- A4XX_RB_BLEND_ALPHA_FLOAT
- A4XX_RB_BLEND_ALPHA_FLOAT__MASK
- A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT
- A4XX_RB_BLEND_ALPHA_SINT
- A4XX_RB_BLEND_ALPHA_SINT__MASK
- A4XX_RB_BLEND_ALPHA_SINT__SHIFT
- A4XX_RB_BLEND_ALPHA_UINT
- A4XX_RB_BLEND_ALPHA_UINT__MASK
- A4XX_RB_BLEND_ALPHA_UINT__SHIFT
- A4XX_RB_BLEND_BLUE_F32
- A4XX_RB_BLEND_BLUE_F32__MASK
- A4XX_RB_BLEND_BLUE_F32__SHIFT
- A4XX_RB_BLEND_BLUE_FLOAT
- A4XX_RB_BLEND_BLUE_FLOAT__MASK
- A4XX_RB_BLEND_BLUE_FLOAT__SHIFT
- A4XX_RB_BLEND_BLUE_SINT
- A4XX_RB_BLEND_BLUE_SINT__MASK
- A4XX_RB_BLEND_BLUE_SINT__SHIFT
- A4XX_RB_BLEND_BLUE_UINT
- A4XX_RB_BLEND_BLUE_UINT__MASK
- A4XX_RB_BLEND_BLUE_UINT__SHIFT
- A4XX_RB_BLEND_GREEN_F32
- A4XX_RB_BLEND_GREEN_F32__MASK
- A4XX_RB_BLEND_GREEN_F32__SHIFT
- A4XX_RB_BLEND_GREEN_FLOAT
- A4XX_RB_BLEND_GREEN_FLOAT__MASK
- A4XX_RB_BLEND_GREEN_FLOAT__SHIFT
- A4XX_RB_BLEND_GREEN_SINT
- A4XX_RB_BLEND_GREEN_SINT__MASK
- A4XX_RB_BLEND_GREEN_SINT__SHIFT
- A4XX_RB_BLEND_GREEN_UINT
- A4XX_RB_BLEND_GREEN_UINT__MASK
- A4XX_RB_BLEND_GREEN_UINT__SHIFT
- A4XX_RB_BLEND_RED_F32
- A4XX_RB_BLEND_RED_F32__MASK
- A4XX_RB_BLEND_RED_F32__SHIFT
- A4XX_RB_BLEND_RED_FLOAT
- A4XX_RB_BLEND_RED_FLOAT__MASK
- A4XX_RB_BLEND_RED_FLOAT__SHIFT
- A4XX_RB_BLEND_RED_SINT
- A4XX_RB_BLEND_RED_SINT__MASK
- A4XX_RB_BLEND_RED_SINT__SHIFT
- A4XX_RB_BLEND_RED_UINT
- A4XX_RB_BLEND_RED_UINT__MASK
- A4XX_RB_BLEND_RED_UINT__SHIFT
- A4XX_RB_COPY_CONTROL_FASTCLEAR
- A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK
- A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT
- A4XX_RB_COPY_CONTROL_GMEM_BASE
- A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK
- A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
- A4XX_RB_COPY_CONTROL_MODE
- A4XX_RB_COPY_CONTROL_MODE__MASK
- A4XX_RB_COPY_CONTROL_MODE__SHIFT
- A4XX_RB_COPY_CONTROL_MSAA_RESOLVE
- A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
- A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
- A4XX_RB_COPY_DEST_BASE_BASE
- A4XX_RB_COPY_DEST_BASE_BASE__MASK
- A4XX_RB_COPY_DEST_BASE_BASE__SHIFT
- A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE
- A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
- A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
- A4XX_RB_COPY_DEST_INFO_DITHER_MODE
- A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK
- A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT
- A4XX_RB_COPY_DEST_INFO_ENDIAN
- A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK
- A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
- A4XX_RB_COPY_DEST_INFO_FORMAT
- A4XX_RB_COPY_DEST_INFO_FORMAT__MASK
- A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
- A4XX_RB_COPY_DEST_INFO_SWAP
- A4XX_RB_COPY_DEST_INFO_SWAP__MASK
- A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT
- A4XX_RB_COPY_DEST_INFO_TILE
- A4XX_RB_COPY_DEST_INFO_TILE__MASK
- A4XX_RB_COPY_DEST_INFO_TILE__SHIFT
- A4XX_RB_COPY_DEST_PITCH_PITCH
- A4XX_RB_COPY_DEST_PITCH_PITCH__MASK
- A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
- A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
- A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
- A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
- A4XX_RB_DEPTH_CONTROL_ZFUNC
- A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK
- A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
- A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
- A4XX_RB_DEPTH_CONTROL_Z_ENABLE
- A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE
- A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
- A4XX_RB_DEPTH_INFO_DEPTH_BASE
- A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
- A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
- A4XX_RB_DEPTH_INFO_DEPTH_FORMAT
- A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
- A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
- A4XX_RB_DEPTH_PITCH
- A4XX_RB_DEPTH_PITCH2
- A4XX_RB_DEPTH_PITCH2__MASK
- A4XX_RB_DEPTH_PITCH2__SHIFT
- A4XX_RB_DEPTH_PITCH__MASK
- A4XX_RB_DEPTH_PITCH__SHIFT
- A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT
- A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK
- A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT
- A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH
- A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK
- A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT
- A4XX_RB_FS_OUTPUT_ENABLE_BLEND
- A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK
- A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT
- A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND
- A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z
- A4XX_RB_FS_OUTPUT_REG_MRT
- A4XX_RB_FS_OUTPUT_REG_MRT__MASK
- A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT
- A4XX_RB_FS_OUTPUT_SAMPLE_MASK
- A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK
- A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT
- A4XX_RB_MODE_CONTROL_ENABLE_GMEM
- A4XX_RB_MODE_CONTROL_HEIGHT
- A4XX_RB_MODE_CONTROL_HEIGHT__MASK
- A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT
- A4XX_RB_MODE_CONTROL_WIDTH
- A4XX_RB_MODE_CONTROL_WIDTH__MASK
- A4XX_RB_MODE_CONTROL_WIDTH__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
- A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE
- A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
- A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR
- A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
- A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
- A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR
- A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
- A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
- A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH
- A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
- A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
- A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT
- A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
- A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
- A4XX_RB_MRT_BUF_INFO_COLOR_SRGB
- A4XX_RB_MRT_BUF_INFO_COLOR_SWAP
- A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
- A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
- A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE
- A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
- A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
- A4XX_RB_MRT_BUF_INFO_DITHER_MODE
- A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK
- A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT
- A4XX_RB_MRT_CONTROL3_STRIDE
- A4XX_RB_MRT_CONTROL3_STRIDE__MASK
- A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT
- A4XX_RB_MRT_CONTROL_BLEND
- A4XX_RB_MRT_CONTROL_BLEND2
- A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE
- A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
- A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
- A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE
- A4XX_RB_MRT_CONTROL_ROP_CODE
- A4XX_RB_MRT_CONTROL_ROP_CODE__MASK
- A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
- A4XX_RB_MRT_CONTROL_ROP_ENABLE
- A4XX_RB_MSAA_CONTROL_DISABLE
- A4XX_RB_MSAA_CONTROL_SAMPLES
- A4XX_RB_MSAA_CONTROL_SAMPLES__MASK
- A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT0
- A4XX_RB_RENDER_COMPONENTS_RT0__MASK
- A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT1
- A4XX_RB_RENDER_COMPONENTS_RT1__MASK
- A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT2
- A4XX_RB_RENDER_COMPONENTS_RT2__MASK
- A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT3
- A4XX_RB_RENDER_COMPONENTS_RT3__MASK
- A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT4
- A4XX_RB_RENDER_COMPONENTS_RT4__MASK
- A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT5
- A4XX_RB_RENDER_COMPONENTS_RT5__MASK
- A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT6
- A4XX_RB_RENDER_COMPONENTS_RT6__MASK
- A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT
- A4XX_RB_RENDER_COMPONENTS_RT7
- A4XX_RB_RENDER_COMPONENTS_RT7__MASK
- A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT
- A4XX_RB_RENDER_CONTROL2_FACENESS
- A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES
- A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK
- A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT
- A4XX_RB_RENDER_CONTROL2_SAMPLEID
- A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR
- A4XX_RB_RENDER_CONTROL2_SAMPLEMASK
- A4XX_RB_RENDER_CONTROL2_VARYING
- A4XX_RB_RENDER_CONTROL2_WCOORD
- A4XX_RB_RENDER_CONTROL2_XCOORD
- A4XX_RB_RENDER_CONTROL2_YCOORD
- A4XX_RB_RENDER_CONTROL2_ZCOORD
- A4XX_RB_RENDER_CONTROL_BINNING_PASS
- A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
- A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR
- A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK
- A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT
- A4XX_RB_SAMPLE_COUNT_CONTROL_COPY
- A4XX_RB_STENCILREFMASK_BF_STENCILMASK
- A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
- A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
- A4XX_RB_STENCILREFMASK_BF_STENCILREF
- A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
- A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
- A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK
- A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
- A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
- A4XX_RB_STENCILREFMASK_STENCILMASK
- A4XX_RB_STENCILREFMASK_STENCILMASK__MASK
- A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
- A4XX_RB_STENCILREFMASK_STENCILREF
- A4XX_RB_STENCILREFMASK_STENCILREF__MASK
- A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT
- A4XX_RB_STENCILREFMASK_STENCILWRITEMASK
- A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
- A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
- A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER
- A4XX_RB_STENCIL_CONTROL_FAIL
- A4XX_RB_STENCIL_CONTROL_FAIL_BF
- A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
- A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
- A4XX_RB_STENCIL_CONTROL_FAIL__MASK
- A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT
- A4XX_RB_STENCIL_CONTROL_FUNC
- A4XX_RB_STENCIL_CONTROL_FUNC_BF
- A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
- A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
- A4XX_RB_STENCIL_CONTROL_FUNC__MASK
- A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT
- A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
- A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
- A4XX_RB_STENCIL_CONTROL_STENCIL_READ
- A4XX_RB_STENCIL_CONTROL_ZFAIL
- A4XX_RB_STENCIL_CONTROL_ZFAIL_BF
- A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
- A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
- A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK
- A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
- A4XX_RB_STENCIL_CONTROL_ZPASS
- A4XX_RB_STENCIL_CONTROL_ZPASS_BF
- A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
- A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
- A4XX_RB_STENCIL_CONTROL_ZPASS__MASK
- A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
- A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL
- A4XX_RB_STENCIL_INFO_STENCIL_BASE
- A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK
- A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT
- A4XX_RB_STENCIL_PITCH
- A4XX_RB_STENCIL_PITCH__MASK
- A4XX_RB_STENCIL_PITCH__SHIFT
- A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A4XX_SP_DS_OUT_REG_A_COMPMASK
- A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK
- A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT
- A4XX_SP_DS_OUT_REG_A_REGID
- A4XX_SP_DS_OUT_REG_A_REGID__MASK
- A4XX_SP_DS_OUT_REG_A_REGID__SHIFT
- A4XX_SP_DS_OUT_REG_B_COMPMASK
- A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK
- A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT
- A4XX_SP_DS_OUT_REG_B_REGID
- A4XX_SP_DS_OUT_REG_B_REGID__MASK
- A4XX_SP_DS_OUT_REG_B_REGID__SHIFT
- A4XX_SP_DS_PARAM_REG_POSREGID
- A4XX_SP_DS_PARAM_REG_POSREGID__MASK
- A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT
- A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR
- A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK
- A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT
- A4XX_SP_DS_VPC_DST_REG_OUTLOC0
- A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK
- A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT
- A4XX_SP_DS_VPC_DST_REG_OUTLOC1
- A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK
- A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT
- A4XX_SP_DS_VPC_DST_REG_OUTLOC2
- A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK
- A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT
- A4XX_SP_DS_VPC_DST_REG_OUTLOC3
- A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK
- A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT
- A4XX_SP_FS_CTRL_REG0_CACHEINVALID
- A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT
- A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT
- A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP
- A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK
- A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
- A4XX_SP_FS_CTRL_REG0_PIXLODENABLE
- A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
- A4XX_SP_FS_CTRL_REG0_THREADMODE
- A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK
- A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
- A4XX_SP_FS_CTRL_REG0_THREADSIZE
- A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
- A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
- A4XX_SP_FS_CTRL_REG0_VARYING
- A4XX_SP_FS_CTRL_REG1_CONSTLENGTH
- A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
- A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
- A4XX_SP_FS_CTRL_REG1_FACENESS
- A4XX_SP_FS_CTRL_REG1_FRAGCOORD
- A4XX_SP_FS_CTRL_REG1_VARYING
- A4XX_SP_FS_MRT_REG_COLOR_SRGB
- A4XX_SP_FS_MRT_REG_HALF_PRECISION
- A4XX_SP_FS_MRT_REG_MRTFORMAT
- A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK
- A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT
- A4XX_SP_FS_MRT_REG_REGID
- A4XX_SP_FS_MRT_REG_REGID__MASK
- A4XX_SP_FS_MRT_REG_REGID__SHIFT
- A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
- A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID
- A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK
- A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT
- A4XX_SP_FS_OUTPUT_REG_MRT
- A4XX_SP_FS_OUTPUT_REG_MRT__MASK
- A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT
- A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID
- A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK
- A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT
- A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A4XX_SP_GS_OUT_REG_A_COMPMASK
- A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK
- A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT
- A4XX_SP_GS_OUT_REG_A_REGID
- A4XX_SP_GS_OUT_REG_A_REGID__MASK
- A4XX_SP_GS_OUT_REG_A_REGID__SHIFT
- A4XX_SP_GS_OUT_REG_B_COMPMASK
- A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK
- A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT
- A4XX_SP_GS_OUT_REG_B_REGID
- A4XX_SP_GS_OUT_REG_B_REGID__MASK
- A4XX_SP_GS_OUT_REG_B_REGID__SHIFT
- A4XX_SP_GS_PARAM_REG_POSREGID
- A4XX_SP_GS_PARAM_REG_POSREGID__MASK
- A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT
- A4XX_SP_GS_PARAM_REG_PRIMREGID
- A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK
- A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT
- A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR
- A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK
- A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT
- A4XX_SP_GS_VPC_DST_REG_OUTLOC0
- A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK
- A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT
- A4XX_SP_GS_VPC_DST_REG_OUTLOC1
- A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK
- A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT
- A4XX_SP_GS_VPC_DST_REG_OUTLOC2
- A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK
- A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT
- A4XX_SP_GS_VPC_DST_REG_OUTLOC3
- A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK
- A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT
- A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER
- A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER
- A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER
- A4XX_SP_SP_CTRL_REG_BINNING_PASS
- A4XX_SP_VS_CTRL_REG0_CACHEINVALID
- A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT
- A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT
- A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP
- A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK
- A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
- A4XX_SP_VS_CTRL_REG0_PIXLODENABLE
- A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
- A4XX_SP_VS_CTRL_REG0_THREADMODE
- A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK
- A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
- A4XX_SP_VS_CTRL_REG0_THREADSIZE
- A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
- A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
- A4XX_SP_VS_CTRL_REG0_VARYING
- A4XX_SP_VS_CTRL_REG1_CONSTLENGTH
- A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
- A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
- A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING
- A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
- A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
- A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET
- A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
- A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
- A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET
- A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
- A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
- A4XX_SP_VS_OUT_REG_A_COMPMASK
- A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK
- A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
- A4XX_SP_VS_OUT_REG_A_REGID
- A4XX_SP_VS_OUT_REG_A_REGID__MASK
- A4XX_SP_VS_OUT_REG_A_REGID__SHIFT
- A4XX_SP_VS_OUT_REG_B_COMPMASK
- A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK
- A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
- A4XX_SP_VS_OUT_REG_B_REGID
- A4XX_SP_VS_OUT_REG_B_REGID__MASK
- A4XX_SP_VS_OUT_REG_B_REGID__SHIFT
- A4XX_SP_VS_PARAM_REG_POSREGID
- A4XX_SP_VS_PARAM_REG_POSREGID__MASK
- A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT
- A4XX_SP_VS_PARAM_REG_PSIZEREGID
- A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
- A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
- A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR
- A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
- A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
- A4XX_SP_VS_VPC_DST_REG_OUTLOC0
- A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
- A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
- A4XX_SP_VS_VPC_DST_REG_OUTLOC1
- A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
- A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
- A4XX_SP_VS_VPC_DST_REG_OUTLOC2
- A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
- A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
- A4XX_SP_VS_VPC_DST_REG_OUTLOC3
- A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
- A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
- A4XX_SSBO_0_0_BASE
- A4XX_SSBO_0_0_BASE__MASK
- A4XX_SSBO_0_0_BASE__SHIFT
- A4XX_SSBO_0_1_PITCH
- A4XX_SSBO_0_1_PITCH__MASK
- A4XX_SSBO_0_1_PITCH__SHIFT
- A4XX_SSBO_0_2_ARRAY_PITCH
- A4XX_SSBO_0_2_ARRAY_PITCH__MASK
- A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT
- A4XX_SSBO_0_3_CPP
- A4XX_SSBO_0_3_CPP__MASK
- A4XX_SSBO_0_3_CPP__SHIFT
- A4XX_SSBO_1_0_CPP
- A4XX_SSBO_1_0_CPP__MASK
- A4XX_SSBO_1_0_CPP__SHIFT
- A4XX_SSBO_1_0_FMT
- A4XX_SSBO_1_0_FMT__MASK
- A4XX_SSBO_1_0_FMT__SHIFT
- A4XX_SSBO_1_0_WIDTH
- A4XX_SSBO_1_0_WIDTH__MASK
- A4XX_SSBO_1_0_WIDTH__SHIFT
- A4XX_SSBO_1_1_DEPTH
- A4XX_SSBO_1_1_DEPTH__MASK
- A4XX_SSBO_1_1_DEPTH__SHIFT
- A4XX_SSBO_1_1_HEIGHT
- A4XX_SSBO_1_1_HEIGHT__MASK
- A4XX_SSBO_1_1_HEIGHT__SHIFT
- A4XX_TEX_1D
- A4XX_TEX_2D
- A4XX_TEX_3D
- A4XX_TEX_ANISO
- A4XX_TEX_ANISO_1
- A4XX_TEX_ANISO_16
- A4XX_TEX_ANISO_2
- A4XX_TEX_ANISO_4
- A4XX_TEX_ANISO_8
- A4XX_TEX_CLAMP_TO_BORDER
- A4XX_TEX_CLAMP_TO_EDGE
- A4XX_TEX_CONST_0_FMT
- A4XX_TEX_CONST_0_FMT__MASK
- A4XX_TEX_CONST_0_FMT__SHIFT
- A4XX_TEX_CONST_0_MIPLVLS
- A4XX_TEX_CONST_0_MIPLVLS__MASK
- A4XX_TEX_CONST_0_MIPLVLS__SHIFT
- A4XX_TEX_CONST_0_SRGB
- A4XX_TEX_CONST_0_SWIZ_W
- A4XX_TEX_CONST_0_SWIZ_W__MASK
- A4XX_TEX_CONST_0_SWIZ_W__SHIFT
- A4XX_TEX_CONST_0_SWIZ_X
- A4XX_TEX_CONST_0_SWIZ_X__MASK
- A4XX_TEX_CONST_0_SWIZ_X__SHIFT
- A4XX_TEX_CONST_0_SWIZ_Y
- A4XX_TEX_CONST_0_SWIZ_Y__MASK
- A4XX_TEX_CONST_0_SWIZ_Y__SHIFT
- A4XX_TEX_CONST_0_SWIZ_Z
- A4XX_TEX_CONST_0_SWIZ_Z__MASK
- A4XX_TEX_CONST_0_SWIZ_Z__SHIFT
- A4XX_TEX_CONST_0_TILED
- A4XX_TEX_CONST_0_TYPE
- A4XX_TEX_CONST_0_TYPE__MASK
- A4XX_TEX_CONST_0_TYPE__SHIFT
- A4XX_TEX_CONST_1_HEIGHT
- A4XX_TEX_CONST_1_HEIGHT__MASK
- A4XX_TEX_CONST_1_HEIGHT__SHIFT
- A4XX_TEX_CONST_1_WIDTH
- A4XX_TEX_CONST_1_WIDTH__MASK
- A4XX_TEX_CONST_1_WIDTH__SHIFT
- A4XX_TEX_CONST_2_FETCHSIZE
- A4XX_TEX_CONST_2_FETCHSIZE__MASK
- A4XX_TEX_CONST_2_FETCHSIZE__SHIFT
- A4XX_TEX_CONST_2_PITCH
- A4XX_TEX_CONST_2_PITCH__MASK
- A4XX_TEX_CONST_2_PITCH__SHIFT
- A4XX_TEX_CONST_2_SWAP
- A4XX_TEX_CONST_2_SWAP__MASK
- A4XX_TEX_CONST_2_SWAP__SHIFT
- A4XX_TEX_CONST_3_DEPTH
- A4XX_TEX_CONST_3_DEPTH__MASK
- A4XX_TEX_CONST_3_DEPTH__SHIFT
- A4XX_TEX_CONST_3_LAYERSZ
- A4XX_TEX_CONST_3_LAYERSZ__MASK
- A4XX_TEX_CONST_3_LAYERSZ__SHIFT
- A4XX_TEX_CONST_4_BASE
- A4XX_TEX_CONST_4_BASE__MASK
- A4XX_TEX_CONST_4_BASE__SHIFT
- A4XX_TEX_CONST_4_LAYERSZ
- A4XX_TEX_CONST_4_LAYERSZ__MASK
- A4XX_TEX_CONST_4_LAYERSZ__SHIFT
- A4XX_TEX_CUBE
- A4XX_TEX_LINEAR
- A4XX_TEX_MIRROR_CLAMP
- A4XX_TEX_MIRROR_REPEAT
- A4XX_TEX_NEAREST
- A4XX_TEX_ONE
- A4XX_TEX_REPEAT
- A4XX_TEX_SAMP_0_ANISO
- A4XX_TEX_SAMP_0_ANISO__MASK
- A4XX_TEX_SAMP_0_ANISO__SHIFT
- A4XX_TEX_SAMP_0_LOD_BIAS
- A4XX_TEX_SAMP_0_LOD_BIAS__MASK
- A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT
- A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR
- A4XX_TEX_SAMP_0_WRAP_R
- A4XX_TEX_SAMP_0_WRAP_R__MASK
- A4XX_TEX_SAMP_0_WRAP_R__SHIFT
- A4XX_TEX_SAMP_0_WRAP_S
- A4XX_TEX_SAMP_0_WRAP_S__MASK
- A4XX_TEX_SAMP_0_WRAP_S__SHIFT
- A4XX_TEX_SAMP_0_WRAP_T
- A4XX_TEX_SAMP_0_WRAP_T__MASK
- A4XX_TEX_SAMP_0_WRAP_T__SHIFT
- A4XX_TEX_SAMP_0_XY_MAG
- A4XX_TEX_SAMP_0_XY_MAG__MASK
- A4XX_TEX_SAMP_0_XY_MAG__SHIFT
- A4XX_TEX_SAMP_0_XY_MIN
- A4XX_TEX_SAMP_0_XY_MIN__MASK
- A4XX_TEX_SAMP_0_XY_MIN__SHIFT
- A4XX_TEX_SAMP_1_COMPARE_FUNC
- A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK
- A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT
- A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF
- A4XX_TEX_SAMP_1_MAX_LOD
- A4XX_TEX_SAMP_1_MAX_LOD__MASK
- A4XX_TEX_SAMP_1_MAX_LOD__SHIFT
- A4XX_TEX_SAMP_1_MIN_LOD
- A4XX_TEX_SAMP_1_MIN_LOD__MASK
- A4XX_TEX_SAMP_1_MIN_LOD__SHIFT
- A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR
- A4XX_TEX_SAMP_1_UNNORM_COORDS
- A4XX_TEX_W
- A4XX_TEX_X
- A4XX_TEX_Y
- A4XX_TEX_Z
- A4XX_TEX_ZERO
- A4XX_TPL1_TP_TEX_COUNT_DS
- A4XX_TPL1_TP_TEX_COUNT_DS__MASK
- A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT
- A4XX_TPL1_TP_TEX_COUNT_GS
- A4XX_TPL1_TP_TEX_COUNT_GS__MASK
- A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT
- A4XX_TPL1_TP_TEX_COUNT_HS
- A4XX_TPL1_TP_TEX_COUNT_HS__MASK
- A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT
- A4XX_TPL1_TP_TEX_COUNT_VS
- A4XX_TPL1_TP_TEX_COUNT_VS__MASK
- A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT
- A4XX_VBIF_CLKON_FORCE_ON_TESTBUS
- A4XX_VFD_CONTROL_0_BYPASSATTROVS
- A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK
- A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT
- A4XX_VFD_CONTROL_0_STRMDECINSTRCNT
- A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
- A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
- A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT
- A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
- A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
- A4XX_VFD_CONTROL_0_TOTALATTRTOVS
- A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
- A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
- A4XX_VFD_CONTROL_1_MAXSTORAGE
- A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK
- A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
- A4XX_VFD_CONTROL_1_REGID4INST
- A4XX_VFD_CONTROL_1_REGID4INST__MASK
- A4XX_VFD_CONTROL_1_REGID4INST__SHIFT
- A4XX_VFD_CONTROL_1_REGID4VTX
- A4XX_VFD_CONTROL_1_REGID4VTX__MASK
- A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT
- A4XX_VFD_CONTROL_3_REGID_TESSX
- A4XX_VFD_CONTROL_3_REGID_TESSX__MASK
- A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT
- A4XX_VFD_CONTROL_3_REGID_TESSY
- A4XX_VFD_CONTROL_3_REGID_TESSY__MASK
- A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT
- A4XX_VFD_CONTROL_3_REGID_VTXCNT
- A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK
- A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT
- A4XX_VFD_DECODE_INSTR_CONSTFILL
- A4XX_VFD_DECODE_INSTR_FORMAT
- A4XX_VFD_DECODE_INSTR_FORMAT__MASK
- A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT
- A4XX_VFD_DECODE_INSTR_INT
- A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
- A4XX_VFD_DECODE_INSTR_REGID
- A4XX_VFD_DECODE_INSTR_REGID__MASK
- A4XX_VFD_DECODE_INSTR_REGID__SHIFT
- A4XX_VFD_DECODE_INSTR_SHIFTCNT
- A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
- A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
- A4XX_VFD_DECODE_INSTR_SWAP
- A4XX_VFD_DECODE_INSTR_SWAP__MASK
- A4XX_VFD_DECODE_INSTR_SWAP__SHIFT
- A4XX_VFD_DECODE_INSTR_SWITCHNEXT
- A4XX_VFD_DECODE_INSTR_WRITEMASK
- A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK
- A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
- A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE
- A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
- A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
- A4XX_VFD_FETCH_INSTR_0_FETCHSIZE
- A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
- A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
- A4XX_VFD_FETCH_INSTR_0_INSTANCED
- A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
- A4XX_VFD_FETCH_INSTR_2_SIZE
- A4XX_VFD_FETCH_INSTR_2_SIZE__MASK
- A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT
- A4XX_VFD_FETCH_INSTR_3_STEPRATE
- A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK
- A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT
- A4XX_VPC_ATTR_ENABLE
- A4XX_VPC_ATTR_PSIZE
- A4XX_VPC_ATTR_THRDASSIGN
- A4XX_VPC_ATTR_THRDASSIGN__MASK
- A4XX_VPC_ATTR_THRDASSIGN__SHIFT
- A4XX_VPC_ATTR_TOTALATTR
- A4XX_VPC_ATTR_TOTALATTR__MASK
- A4XX_VPC_ATTR_TOTALATTR__SHIFT
- A4XX_VPC_PACK_NUMBYPASSVAR
- A4XX_VPC_PACK_NUMBYPASSVAR__MASK
- A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT
- A4XX_VPC_PACK_NUMFPNONPOSVAR
- A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK
- A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
- A4XX_VPC_PACK_NUMNONPOSVSVAR
- A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK
- A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
- A4XX_VSC_BIN_SIZE_HEIGHT
- A4XX_VSC_BIN_SIZE_HEIGHT__MASK
- A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT
- A4XX_VSC_BIN_SIZE_WIDTH
- A4XX_VSC_BIN_SIZE_WIDTH__MASK
- A4XX_VSC_BIN_SIZE_WIDTH__SHIFT
- A4XX_VSC_PIPE_CONFIG_REG_H
- A4XX_VSC_PIPE_CONFIG_REG_H__MASK
- A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT
- A4XX_VSC_PIPE_CONFIG_REG_W
- A4XX_VSC_PIPE_CONFIG_REG_W__MASK
- A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT
- A4XX_VSC_PIPE_CONFIG_REG_X
- A4XX_VSC_PIPE_CONFIG_REG_X__MASK
- A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT
- A4XX_VSC_PIPE_CONFIG_REG_Y
- A4XX_VSC_PIPE_CONFIG_REG_Y__MASK
- A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT
- A4XX_XML
- A4_2WHEEL_MOUSE_HACK_7
- A4_2WHEEL_MOUSE_HACK_B8
- A4_FOE_MARK
- A4_MARK
- A4_WHEEL_ORIENTATION
- A5
- A53_GATE
- A5XX
- A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI
- A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK
- A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT
- A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO
- A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK
- A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT
- A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI
- A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK
- A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT
- A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES
- A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK
- A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT
- A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO
- A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK
- A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT
- A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI
- A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK
- A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT
- A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO
- A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK
- A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT
- A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI
- A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK
- A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK
- A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT
- A5XX_CP_INT_CP_AHB_ERROR
- A5XX_CP_INT_CP_DMA_ERROR
- A5XX_CP_INT_CP_HW_FAULT_ERROR
- A5XX_CP_INT_CP_OPCODE_ERROR
- A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR
- A5XX_CP_INT_CP_RESERVED_BIT_ERROR
- A5XX_CP_PROTECT_REG_BASE_ADDR
- A5XX_CP_PROTECT_REG_BASE_ADDR__MASK
- A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT
- A5XX_CP_PROTECT_REG_MASK_LEN
- A5XX_CP_PROTECT_REG_MASK_LEN__MASK
- A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT
- A5XX_CP_PROTECT_REG_TRAP_READ
- A5XX_CP_PROTECT_REG_TRAP_WRITE
- A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON
- A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON
- A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT
- A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK
- A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT
- A5XX_GRAS_2D_DST_INFO_COLOR_SWAP
- A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK
- A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT
- A5XX_GRAS_2D_DST_INFO_FLAGS
- A5XX_GRAS_2D_DST_INFO_TILE_MODE
- A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK
- A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT
- A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT
- A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK
- A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT
- A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP
- A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK
- A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT
- A5XX_GRAS_2D_SRC_INFO_FLAGS
- A5XX_GRAS_2D_SRC_INFO_TILE_MODE
- A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK
- A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT
- A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK
- A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT
- A5XX_GRAS_CL_VPORT_XOFFSET_0
- A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK
- A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT
- A5XX_GRAS_CL_VPORT_XSCALE_0
- A5XX_GRAS_CL_VPORT_XSCALE_0__MASK
- A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT
- A5XX_GRAS_CL_VPORT_YOFFSET_0
- A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK
- A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT
- A5XX_GRAS_CL_VPORT_YSCALE_0
- A5XX_GRAS_CL_VPORT_YSCALE_0__MASK
- A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT
- A5XX_GRAS_CL_VPORT_ZOFFSET_0
- A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK
- A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT
- A5XX_GRAS_CL_VPORT_ZSCALE_0
- A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK
- A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT
- A5XX_GRAS_CNTL_UNK3
- A5XX_GRAS_CNTL_VARYING
- A5XX_GRAS_CNTL_WCOORD
- A5XX_GRAS_CNTL_XCOORD
- A5XX_GRAS_CNTL_YCOORD
- A5XX_GRAS_CNTL_ZCOORD
- A5XX_GRAS_LRZ_BUFFER_PITCH
- A5XX_GRAS_LRZ_BUFFER_PITCH__MASK
- A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT
- A5XX_GRAS_LRZ_CNTL_ENABLE
- A5XX_GRAS_LRZ_CNTL_GREATER
- A5XX_GRAS_LRZ_CNTL_LRZ_WRITE
- A5XX_GRAS_SC_CNTL_BINNING_PASS
- A5XX_GRAS_SC_CNTL_SAMPLES_PASSED
- A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE
- A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES
- A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK
- A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES
- A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK
- A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK
- A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK
- A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK
- A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
- A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
- A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
- A5XX_GRAS_SU_CNTL_CULL_BACK
- A5XX_GRAS_SU_CNTL_CULL_FRONT
- A5XX_GRAS_SU_CNTL_FRONT_CW
- A5XX_GRAS_SU_CNTL_LINEHALFWIDTH
- A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
- A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT
- A5XX_GRAS_SU_CNTL_MSAA_ENABLE
- A5XX_GRAS_SU_CNTL_POLY_OFFSET
- A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT
- A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
- A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
- A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
- A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
- A5XX_GRAS_SU_POINT_MINMAX_MAX
- A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK
- A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
- A5XX_GRAS_SU_POINT_MINMAX_MIN
- A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK
- A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
- A5XX_GRAS_SU_POINT_SIZE
- A5XX_GRAS_SU_POINT_SIZE__MASK
- A5XX_GRAS_SU_POINT_SIZE__SHIFT
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
- A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
- A5XX_GRAS_SU_POLY_OFFSET_SCALE
- A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
- A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT
- A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE
- A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK
- A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT
- A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE
- A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
- A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
- A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD
- A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK
- A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT
- A5XX_HLSQ_CONTROL_2_REG_FACEREGID
- A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
- A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEID
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK
- A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT
- A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID
- A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK
- A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT
- A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID
- A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
- A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT
- A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID
- A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
- A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT
- A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID
- A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK
- A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT
- A5XX_HLSQ_CS_CNTL_0_UNK0
- A5XX_HLSQ_CS_CNTL_0_UNK0__MASK
- A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT
- A5XX_HLSQ_CS_CNTL_0_UNK1
- A5XX_HLSQ_CS_CNTL_0_UNK1__MASK
- A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT
- A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID
- A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK
- A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT
- A5XX_HLSQ_CS_CNTL_INSTRLEN
- A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_CS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_CS_CONFIG_ENABLED
- A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM
- A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK
- A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK
- A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT
- A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X
- A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK
- A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT
- A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X
- A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK
- A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT
- A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y
- A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK
- A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT
- A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y
- A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK
- A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT
- A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z
- A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK
- A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT
- A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z
- A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK
- A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT
- A5XX_HLSQ_DS_CNTL_INSTRLEN
- A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_DS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_DS_CONFIG_ENABLED
- A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_HLSQ_FS_CNTL_INSTRLEN
- A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_FS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_FS_CONFIG_ENABLED
- A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_HLSQ_GS_CNTL_INSTRLEN
- A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_GS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_GS_CONFIG_ENABLED
- A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_HLSQ_HS_CNTL_INSTRLEN
- A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_HS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_HS_CONFIG_ENABLED
- A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_HLSQ_VS_CNTL_INSTRLEN
- A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK
- A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT
- A5XX_HLSQ_VS_CNTL_SSBO_ENABLE
- A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET
- A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_HLSQ_VS_CONFIG_ENABLED
- A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET
- A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_INT0_CP_CACHE_FLUSH_TS
- A5XX_INT0_CP_CCU_FLUSH_COLOR_TS
- A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS
- A5XX_INT0_CP_CCU_RESOLVE_TS
- A5XX_INT0_CP_HW_ERROR
- A5XX_INT0_CP_IB1
- A5XX_INT0_CP_IB2
- A5XX_INT0_CP_RB
- A5XX_INT0_CP_RB_DONE_TS
- A5XX_INT0_CP_SW
- A5XX_INT0_CP_UNUSED_1
- A5XX_INT0_CP_WT_DONE_TS
- A5XX_INT0_DEBBUS_INTR_0
- A5XX_INT0_DEBBUS_INTR_1
- A5XX_INT0_GPMU_FIRMWARE
- A5XX_INT0_GPMU_VOLTAGE_DROOP
- A5XX_INT0_ISDB_CPU_IRQ
- A5XX_INT0_ISDB_UNDER_DEBUG
- A5XX_INT0_MISC_HANG_DETECT
- A5XX_INT0_RBBM_AHB_ERROR
- A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW
- A5XX_INT0_RBBM_ATB_BUS_OVERFLOW
- A5XX_INT0_RBBM_ETS_MS_TIMEOUT
- A5XX_INT0_RBBM_GPC_ERROR
- A5XX_INT0_RBBM_GPU_IDLE
- A5XX_INT0_RBBM_ME_MS_TIMEOUT
- A5XX_INT0_RBBM_PFP_MS_TIMEOUT
- A5XX_INT0_RBBM_TRANSFER_TIMEOUT
- A5XX_INT0_UCHE_OOB_ACCESS
- A5XX_INT0_UCHE_TRAP_INTR
- A5XX_INT0_UNKNOWN_1
- A5XX_INT0_UNUSED_2
- A5XX_INT_MASK
- A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI
- A5XX_PC_GS_PARAM_INVOCATIONS
- A5XX_PC_GS_PARAM_INVOCATIONS__MASK
- A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT
- A5XX_PC_GS_PARAM_MAX_VERTICES
- A5XX_PC_GS_PARAM_MAX_VERTICES__MASK
- A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT
- A5XX_PC_GS_PARAM_PRIMTYPE
- A5XX_PC_GS_PARAM_PRIMTYPE__MASK
- A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT
- A5XX_PC_HS_PARAM_CONNECTED
- A5XX_PC_HS_PARAM_CW
- A5XX_PC_HS_PARAM_SPACING
- A5XX_PC_HS_PARAM_SPACING__MASK
- A5XX_PC_HS_PARAM_SPACING__SHIFT
- A5XX_PC_HS_PARAM_VERTICES_OUT
- A5XX_PC_HS_PARAM_VERTICES_OUT__MASK
- A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT
- A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES
- A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART
- A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST
- A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC
- A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK
- A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT
- A5XX_PC_PRIM_VTX_CNTL_PSIZE
- A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE
- A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK
- A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT
- A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE
- A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE
- A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK
- A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
- A5XX_PREEMPT_COUNTER_SIZE
- A5XX_PREEMPT_RECORD_MAGIC
- A5XX_PREEMPT_RECORD_SIZE
- A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS
- A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS
- A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS
- A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS
- A5XX_RBBM_INT_0_MASK_CP_HW_ERROR
- A5XX_RBBM_INT_0_MASK_CP_IB1
- A5XX_RBBM_INT_0_MASK_CP_IB2
- A5XX_RBBM_INT_0_MASK_CP_RB
- A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS
- A5XX_RBBM_INT_0_MASK_CP_SW
- A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS
- A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0
- A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1
- A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE
- A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP
- A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ
- A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG
- A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT
- A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR
- A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW
- A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW
- A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT
- A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR
- A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE
- A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT
- A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT
- A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT
- A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS
- A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR
- A5XX_RBBM_STATUS_A2D_DSP_BUSY
- A5XX_RBBM_STATUS_CCUFCHE_BUSY
- A5XX_RBBM_STATUS_COM_BUSY
- A5XX_RBBM_STATUS_CP_BUSY
- A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST
- A5XX_RBBM_STATUS_CP_CRASH_BUSY
- A5XX_RBBM_STATUS_CP_ETS_BUSY
- A5XX_RBBM_STATUS_CP_ME_BUSY
- A5XX_RBBM_STATUS_CP_PFP_BUSY
- A5XX_RBBM_STATUS_DCOM_BUSY
- A5XX_RBBM_STATUS_GPMU_MASTER_BUSY
- A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY
- A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB
- A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP
- A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST
- A5XX_RBBM_STATUS_HI_BUSY
- A5XX_RBBM_STATUS_HLSQ_BUSY
- A5XX_RBBM_STATUS_LRZ_BUZY
- A5XX_RBBM_STATUS_PC_DCALL_BUSY
- A5XX_RBBM_STATUS_PC_VSD_BUSY
- A5XX_RBBM_STATUS_RAS_BUSY
- A5XX_RBBM_STATUS_RB_BUSY
- A5XX_RBBM_STATUS_SP_BUSY
- A5XX_RBBM_STATUS_TESS_BUSY
- A5XX_RBBM_STATUS_TPL1_BUSY
- A5XX_RBBM_STATUS_TSE_BUSY
- A5XX_RBBM_STATUS_UCHE_BUSY
- A5XX_RBBM_STATUS_VBIF_BUSY
- A5XX_RBBM_STATUS_VFDP_BUSY
- A5XX_RBBM_STATUS_VFD_BUSY
- A5XX_RBBM_STATUS_VPC_BUSY
- A5XX_RBBM_STATUS_VSC_BUSY
- A5XX_RB_2D_DST_INFO_COLOR_FORMAT
- A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK
- A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT
- A5XX_RB_2D_DST_INFO_COLOR_SWAP
- A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK
- A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT
- A5XX_RB_2D_DST_INFO_FLAGS
- A5XX_RB_2D_DST_INFO_TILE_MODE
- A5XX_RB_2D_DST_INFO_TILE_MODE__MASK
- A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT
- A5XX_RB_2D_DST_SIZE_ARRAY_PITCH
- A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK
- A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT
- A5XX_RB_2D_DST_SIZE_PITCH
- A5XX_RB_2D_DST_SIZE_PITCH__MASK
- A5XX_RB_2D_DST_SIZE_PITCH__SHIFT
- A5XX_RB_2D_SRC_INFO_COLOR_FORMAT
- A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK
- A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT
- A5XX_RB_2D_SRC_INFO_COLOR_SWAP
- A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK
- A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT
- A5XX_RB_2D_SRC_INFO_FLAGS
- A5XX_RB_2D_SRC_INFO_TILE_MODE
- A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK
- A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT
- A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH
- A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK
- A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT
- A5XX_RB_2D_SRC_SIZE_PITCH
- A5XX_RB_2D_SRC_SIZE_PITCH__MASK
- A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT
- A5XX_RB_ALPHA_CONTROL_ALPHA_REF
- A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
- A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT
- A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
- A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC
- A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
- A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT
- A5XX_RB_BLEND_ALPHA_F32
- A5XX_RB_BLEND_ALPHA_F32__MASK
- A5XX_RB_BLEND_ALPHA_F32__SHIFT
- A5XX_RB_BLEND_ALPHA_FLOAT
- A5XX_RB_BLEND_ALPHA_FLOAT__MASK
- A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT
- A5XX_RB_BLEND_ALPHA_SINT
- A5XX_RB_BLEND_ALPHA_SINT__MASK
- A5XX_RB_BLEND_ALPHA_SINT__SHIFT
- A5XX_RB_BLEND_ALPHA_UINT
- A5XX_RB_BLEND_ALPHA_UINT__MASK
- A5XX_RB_BLEND_ALPHA_UINT__SHIFT
- A5XX_RB_BLEND_BLUE_F32
- A5XX_RB_BLEND_BLUE_F32__MASK
- A5XX_RB_BLEND_BLUE_F32__SHIFT
- A5XX_RB_BLEND_BLUE_FLOAT
- A5XX_RB_BLEND_BLUE_FLOAT__MASK
- A5XX_RB_BLEND_BLUE_FLOAT__SHIFT
- A5XX_RB_BLEND_BLUE_SINT
- A5XX_RB_BLEND_BLUE_SINT__MASK
- A5XX_RB_BLEND_BLUE_SINT__SHIFT
- A5XX_RB_BLEND_BLUE_UINT
- A5XX_RB_BLEND_BLUE_UINT__MASK
- A5XX_RB_BLEND_BLUE_UINT__SHIFT
- A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
- A5XX_RB_BLEND_CNTL_ENABLE_BLEND
- A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
- A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
- A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
- A5XX_RB_BLEND_CNTL_SAMPLE_MASK
- A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK
- A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT
- A5XX_RB_BLEND_GREEN_F32
- A5XX_RB_BLEND_GREEN_F32__MASK
- A5XX_RB_BLEND_GREEN_F32__SHIFT
- A5XX_RB_BLEND_GREEN_FLOAT
- A5XX_RB_BLEND_GREEN_FLOAT__MASK
- A5XX_RB_BLEND_GREEN_FLOAT__SHIFT
- A5XX_RB_BLEND_GREEN_SINT
- A5XX_RB_BLEND_GREEN_SINT__MASK
- A5XX_RB_BLEND_GREEN_SINT__SHIFT
- A5XX_RB_BLEND_GREEN_UINT
- A5XX_RB_BLEND_GREEN_UINT__MASK
- A5XX_RB_BLEND_GREEN_UINT__SHIFT
- A5XX_RB_BLEND_RED_F32
- A5XX_RB_BLEND_RED_F32__MASK
- A5XX_RB_BLEND_RED_F32__SHIFT
- A5XX_RB_BLEND_RED_FLOAT
- A5XX_RB_BLEND_RED_FLOAT__MASK
- A5XX_RB_BLEND_RED_FLOAT__SHIFT
- A5XX_RB_BLEND_RED_SINT
- A5XX_RB_BLEND_RED_SINT__MASK
- A5XX_RB_BLEND_RED_SINT__SHIFT
- A5XX_RB_BLEND_RED_UINT
- A5XX_RB_BLEND_RED_UINT__MASK
- A5XX_RB_BLEND_RED_UINT__SHIFT
- A5XX_RB_BLIT_CNTL_BUF
- A5XX_RB_BLIT_CNTL_BUF__MASK
- A5XX_RB_BLIT_CNTL_BUF__SHIFT
- A5XX_RB_BLIT_DST_ARRAY_PITCH
- A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK
- A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT
- A5XX_RB_BLIT_DST_PITCH
- A5XX_RB_BLIT_DST_PITCH__MASK
- A5XX_RB_BLIT_DST_PITCH__SHIFT
- A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH
- A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK
- A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT
- A5XX_RB_BLIT_FLAG_DST_PITCH
- A5XX_RB_BLIT_FLAG_DST_PITCH__MASK
- A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT
- A5XX_RB_CLEAR_CNTL_FAST_CLEAR
- A5XX_RB_CLEAR_CNTL_MASK
- A5XX_RB_CLEAR_CNTL_MASK__MASK
- A5XX_RB_CLEAR_CNTL_MASK__SHIFT
- A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE
- A5XX_RB_CNTL_BYPASS
- A5XX_RB_CNTL_HEIGHT
- A5XX_RB_CNTL_HEIGHT__MASK
- A5XX_RB_CNTL_HEIGHT__SHIFT
- A5XX_RB_CNTL_WIDTH
- A5XX_RB_CNTL_WIDTH__MASK
- A5XX_RB_CNTL_WIDTH__SHIFT
- A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH
- A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK
- A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT
- A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT
- A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
- A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
- A5XX_RB_DEPTH_BUFFER_PITCH
- A5XX_RB_DEPTH_BUFFER_PITCH__MASK
- A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT
- A5XX_RB_DEPTH_CNTL_ZFUNC
- A5XX_RB_DEPTH_CNTL_ZFUNC__MASK
- A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT
- A5XX_RB_DEPTH_CNTL_Z_ENABLE
- A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
- A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
- A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
- A5XX_RB_DEPTH_PLANE_CNTL_UNK1
- A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
- A5XX_RB_DEST_MSAA_CNTL_SAMPLES
- A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK
- A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
- A5XX_RB_FS_OUTPUT_CNTL_MRT
- A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK
- A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT
- A5XX_RB_MRT_ARRAY_PITCH
- A5XX_RB_MRT_ARRAY_PITCH__MASK
- A5XX_RB_MRT_ARRAY_PITCH__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
- A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE
- A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
- A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR
- A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
- A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
- A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR
- A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
- A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
- A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT
- A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
- A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
- A5XX_RB_MRT_BUF_INFO_COLOR_SRGB
- A5XX_RB_MRT_BUF_INFO_COLOR_SWAP
- A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
- A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
- A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE
- A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
- A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
- A5XX_RB_MRT_BUF_INFO_DITHER_MODE
- A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK
- A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT
- A5XX_RB_MRT_CONTROL_BLEND
- A5XX_RB_MRT_CONTROL_BLEND2
- A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE
- A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
- A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
- A5XX_RB_MRT_CONTROL_ROP_CODE
- A5XX_RB_MRT_CONTROL_ROP_CODE__MASK
- A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
- A5XX_RB_MRT_CONTROL_ROP_ENABLE
- A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH
- A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK
- A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT
- A5XX_RB_MRT_FLAG_BUFFER_PITCH
- A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK
- A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT
- A5XX_RB_MRT_PITCH
- A5XX_RB_MRT_PITCH__MASK
- A5XX_RB_MRT_PITCH__SHIFT
- A5XX_RB_RAS_MSAA_CNTL_SAMPLES
- A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK
- A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_RB_RENDER_CNTL_BINNING_PASS
- A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE
- A5XX_RB_RENDER_CNTL_FLAG_DEPTH
- A5XX_RB_RENDER_CNTL_FLAG_DEPTH2
- A5XX_RB_RENDER_CNTL_FLAG_MRTS
- A5XX_RB_RENDER_CNTL_FLAG_MRTS2
- A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK
- A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT
- A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK
- A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT
- A5XX_RB_RENDER_CNTL_SAMPLES_PASSED
- A5XX_RB_RENDER_COMPONENTS_RT0
- A5XX_RB_RENDER_COMPONENTS_RT0__MASK
- A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT1
- A5XX_RB_RENDER_COMPONENTS_RT1__MASK
- A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT2
- A5XX_RB_RENDER_COMPONENTS_RT2__MASK
- A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT3
- A5XX_RB_RENDER_COMPONENTS_RT3__MASK
- A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT4
- A5XX_RB_RENDER_COMPONENTS_RT4__MASK
- A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT5
- A5XX_RB_RENDER_COMPONENTS_RT5__MASK
- A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT6
- A5XX_RB_RENDER_COMPONENTS_RT6__MASK
- A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT
- A5XX_RB_RENDER_COMPONENTS_RT7
- A5XX_RB_RENDER_COMPONENTS_RT7__MASK
- A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT
- A5XX_RB_RENDER_CONTROL0_UNK3
- A5XX_RB_RENDER_CONTROL0_VARYING
- A5XX_RB_RENDER_CONTROL0_WCOORD
- A5XX_RB_RENDER_CONTROL0_XCOORD
- A5XX_RB_RENDER_CONTROL0_YCOORD
- A5XX_RB_RENDER_CONTROL0_ZCOORD
- A5XX_RB_RENDER_CONTROL1_FACENESS
- A5XX_RB_RENDER_CONTROL1_SAMPLEID
- A5XX_RB_RENDER_CONTROL1_SAMPLEMASK
- A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE
- A5XX_RB_RESOLVE_CNTL_1_X
- A5XX_RB_RESOLVE_CNTL_1_X__MASK
- A5XX_RB_RESOLVE_CNTL_1_X__SHIFT
- A5XX_RB_RESOLVE_CNTL_1_Y
- A5XX_RB_RESOLVE_CNTL_1_Y__MASK
- A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT
- A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE
- A5XX_RB_RESOLVE_CNTL_2_X
- A5XX_RB_RESOLVE_CNTL_2_X__MASK
- A5XX_RB_RESOLVE_CNTL_2_X__SHIFT
- A5XX_RB_RESOLVE_CNTL_2_Y
- A5XX_RB_RESOLVE_CNTL_2_Y__MASK
- A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT
- A5XX_RB_RESOLVE_CNTL_3_TILED
- A5XX_RB_SAMPLE_COUNT_CONTROL_COPY
- A5XX_RB_STENCILREFMASK_BF_STENCILMASK
- A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
- A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
- A5XX_RB_STENCILREFMASK_BF_STENCILREF
- A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
- A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
- A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK
- A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
- A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
- A5XX_RB_STENCILREFMASK_STENCILMASK
- A5XX_RB_STENCILREFMASK_STENCILMASK__MASK
- A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
- A5XX_RB_STENCILREFMASK_STENCILREF
- A5XX_RB_STENCILREFMASK_STENCILREF__MASK
- A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT
- A5XX_RB_STENCILREFMASK_STENCILWRITEMASK
- A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
- A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
- A5XX_RB_STENCIL_ARRAY_PITCH
- A5XX_RB_STENCIL_ARRAY_PITCH__MASK
- A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT
- A5XX_RB_STENCIL_CONTROL_FAIL
- A5XX_RB_STENCIL_CONTROL_FAIL_BF
- A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
- A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
- A5XX_RB_STENCIL_CONTROL_FAIL__MASK
- A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT
- A5XX_RB_STENCIL_CONTROL_FUNC
- A5XX_RB_STENCIL_CONTROL_FUNC_BF
- A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
- A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
- A5XX_RB_STENCIL_CONTROL_FUNC__MASK
- A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT
- A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
- A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
- A5XX_RB_STENCIL_CONTROL_STENCIL_READ
- A5XX_RB_STENCIL_CONTROL_ZFAIL
- A5XX_RB_STENCIL_CONTROL_ZFAIL_BF
- A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
- A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
- A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK
- A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
- A5XX_RB_STENCIL_CONTROL_ZPASS
- A5XX_RB_STENCIL_CONTROL_ZPASS_BF
- A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
- A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
- A5XX_RB_STENCIL_CONTROL_ZPASS__MASK
- A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
- A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL
- A5XX_RB_STENCIL_PITCH
- A5XX_RB_STENCIL_PITCH__MASK
- A5XX_RB_STENCIL_PITCH__SHIFT
- A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE
- A5XX_RB_WINDOW_OFFSET_X
- A5XX_RB_WINDOW_OFFSET_X__MASK
- A5XX_RB_WINDOW_OFFSET_X__SHIFT
- A5XX_RB_WINDOW_OFFSET_Y
- A5XX_RB_WINDOW_OFFSET_Y__MASK
- A5XX_RB_WINDOW_OFFSET_Y__SHIFT
- A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
- A5XX_SP_BLEND_CNTL_ENABLED
- A5XX_SP_BLEND_CNTL_UNK8
- A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_CS_CONFIG_ENABLED
- A5XX_SP_CS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_CS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_CS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_CS_CTRL_REG0_THREADSIZE
- A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_CS_CTRL_REG0_VARYING
- A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_DS_CONFIG_ENABLED
- A5XX_SP_DS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_DS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_DS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_DS_CTRL_REG0_THREADSIZE
- A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_DS_CTRL_REG0_VARYING
- A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_FS_CONFIG_ENABLED
- A5XX_SP_FS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_FS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_FS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_FS_CTRL_REG0_THREADSIZE
- A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_FS_CTRL_REG0_VARYING
- A5XX_SP_FS_MRT_REG_COLOR_FORMAT
- A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK
- A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT
- A5XX_SP_FS_MRT_REG_COLOR_SINT
- A5XX_SP_FS_MRT_REG_COLOR_SRGB
- A5XX_SP_FS_MRT_REG_COLOR_UINT
- A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID
- A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK
- A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT
- A5XX_SP_FS_OUTPUT_CNTL_MRT
- A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK
- A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT
- A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID
- A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK
- A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT
- A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION
- A5XX_SP_FS_OUTPUT_REG_REGID
- A5XX_SP_FS_OUTPUT_REG_REGID__MASK
- A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT
- A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_GS_CONFIG_ENABLED
- A5XX_SP_GS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_GS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_GS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_GS_CTRL_REG0_THREADSIZE
- A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_GS_CTRL_REG0_VARYING
- A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_HS_CONFIG_ENABLED
- A5XX_SP_HS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_HS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_HS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_HS_CTRL_REG0_THREADSIZE
- A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_HS_CTRL_REG0_VARYING
- A5XX_SP_PRIMITIVE_CNTL_VSOUT
- A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK
- A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT
- A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET
- A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK
- A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT
- A5XX_SP_VS_CONFIG_ENABLED
- A5XX_SP_VS_CONFIG_SHADEROBJOFFSET
- A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK
- A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT
- A5XX_SP_VS_CTRL_REG0_BRANCHSTACK
- A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK
- A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT
- A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT
- A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT
- A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A5XX_SP_VS_CTRL_REG0_PIXLODENABLE
- A5XX_SP_VS_CTRL_REG0_THREADSIZE
- A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
- A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
- A5XX_SP_VS_CTRL_REG0_VARYING
- A5XX_SP_VS_OUT_REG_A_COMPMASK
- A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK
- A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
- A5XX_SP_VS_OUT_REG_A_REGID
- A5XX_SP_VS_OUT_REG_A_REGID__MASK
- A5XX_SP_VS_OUT_REG_A_REGID__SHIFT
- A5XX_SP_VS_OUT_REG_B_COMPMASK
- A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK
- A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
- A5XX_SP_VS_OUT_REG_B_REGID
- A5XX_SP_VS_OUT_REG_B_REGID__MASK
- A5XX_SP_VS_OUT_REG_B_REGID__SHIFT
- A5XX_SP_VS_VPC_DST_REG_OUTLOC0
- A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
- A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
- A5XX_SP_VS_VPC_DST_REG_OUTLOC1
- A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
- A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
- A5XX_SP_VS_VPC_DST_REG_OUTLOC2
- A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
- A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
- A5XX_SP_VS_VPC_DST_REG_OUTLOC3
- A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
- A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
- A5XX_SSBO_0_0_BASE_LO
- A5XX_SSBO_0_0_BASE_LO__MASK
- A5XX_SSBO_0_0_BASE_LO__SHIFT
- A5XX_SSBO_0_1_PITCH
- A5XX_SSBO_0_1_PITCH__MASK
- A5XX_SSBO_0_1_PITCH__SHIFT
- A5XX_SSBO_0_2_ARRAY_PITCH
- A5XX_SSBO_0_2_ARRAY_PITCH__MASK
- A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT
- A5XX_SSBO_0_3_CPP
- A5XX_SSBO_0_3_CPP__MASK
- A5XX_SSBO_0_3_CPP__SHIFT
- A5XX_SSBO_1_0_FMT
- A5XX_SSBO_1_0_FMT__MASK
- A5XX_SSBO_1_0_FMT__SHIFT
- A5XX_SSBO_1_0_WIDTH
- A5XX_SSBO_1_0_WIDTH__MASK
- A5XX_SSBO_1_0_WIDTH__SHIFT
- A5XX_SSBO_1_1_DEPTH
- A5XX_SSBO_1_1_DEPTH__MASK
- A5XX_SSBO_1_1_DEPTH__SHIFT
- A5XX_SSBO_1_1_HEIGHT
- A5XX_SSBO_1_1_HEIGHT__MASK
- A5XX_SSBO_1_1_HEIGHT__SHIFT
- A5XX_SSBO_2_0_BASE_LO
- A5XX_SSBO_2_0_BASE_LO__MASK
- A5XX_SSBO_2_0_BASE_LO__SHIFT
- A5XX_SSBO_2_1_BASE_HI
- A5XX_SSBO_2_1_BASE_HI__MASK
- A5XX_SSBO_2_1_BASE_HI__SHIFT
- A5XX_TEX_1D
- A5XX_TEX_2D
- A5XX_TEX_3D
- A5XX_TEX_ANISO
- A5XX_TEX_ANISO_1
- A5XX_TEX_ANISO_16
- A5XX_TEX_ANISO_2
- A5XX_TEX_ANISO_4
- A5XX_TEX_ANISO_8
- A5XX_TEX_CLAMP_TO_BORDER
- A5XX_TEX_CLAMP_TO_EDGE
- A5XX_TEX_CONST_0_FMT
- A5XX_TEX_CONST_0_FMT__MASK
- A5XX_TEX_CONST_0_FMT__SHIFT
- A5XX_TEX_CONST_0_MIPLVLS
- A5XX_TEX_CONST_0_MIPLVLS__MASK
- A5XX_TEX_CONST_0_MIPLVLS__SHIFT
- A5XX_TEX_CONST_0_SAMPLES
- A5XX_TEX_CONST_0_SAMPLES__MASK
- A5XX_TEX_CONST_0_SAMPLES__SHIFT
- A5XX_TEX_CONST_0_SRGB
- A5XX_TEX_CONST_0_SWAP
- A5XX_TEX_CONST_0_SWAP__MASK
- A5XX_TEX_CONST_0_SWAP__SHIFT
- A5XX_TEX_CONST_0_SWIZ_W
- A5XX_TEX_CONST_0_SWIZ_W__MASK
- A5XX_TEX_CONST_0_SWIZ_W__SHIFT
- A5XX_TEX_CONST_0_SWIZ_X
- A5XX_TEX_CONST_0_SWIZ_X__MASK
- A5XX_TEX_CONST_0_SWIZ_X__SHIFT
- A5XX_TEX_CONST_0_SWIZ_Y
- A5XX_TEX_CONST_0_SWIZ_Y__MASK
- A5XX_TEX_CONST_0_SWIZ_Y__SHIFT
- A5XX_TEX_CONST_0_SWIZ_Z
- A5XX_TEX_CONST_0_SWIZ_Z__MASK
- A5XX_TEX_CONST_0_SWIZ_Z__SHIFT
- A5XX_TEX_CONST_0_TILE_MODE
- A5XX_TEX_CONST_0_TILE_MODE__MASK
- A5XX_TEX_CONST_0_TILE_MODE__SHIFT
- A5XX_TEX_CONST_1_HEIGHT
- A5XX_TEX_CONST_1_HEIGHT__MASK
- A5XX_TEX_CONST_1_HEIGHT__SHIFT
- A5XX_TEX_CONST_1_WIDTH
- A5XX_TEX_CONST_1_WIDTH__MASK
- A5XX_TEX_CONST_1_WIDTH__SHIFT
- A5XX_TEX_CONST_2_FETCHSIZE
- A5XX_TEX_CONST_2_FETCHSIZE__MASK
- A5XX_TEX_CONST_2_FETCHSIZE__SHIFT
- A5XX_TEX_CONST_2_PITCH
- A5XX_TEX_CONST_2_PITCH__MASK
- A5XX_TEX_CONST_2_PITCH__SHIFT
- A5XX_TEX_CONST_2_TYPE
- A5XX_TEX_CONST_2_TYPE__MASK
- A5XX_TEX_CONST_2_TYPE__SHIFT
- A5XX_TEX_CONST_3_ARRAY_PITCH
- A5XX_TEX_CONST_3_ARRAY_PITCH__MASK
- A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT
- A5XX_TEX_CONST_3_FLAG
- A5XX_TEX_CONST_4_BASE_LO
- A5XX_TEX_CONST_4_BASE_LO__MASK
- A5XX_TEX_CONST_4_BASE_LO__SHIFT
- A5XX_TEX_CONST_5_BASE_HI
- A5XX_TEX_CONST_5_BASE_HI__MASK
- A5XX_TEX_CONST_5_BASE_HI__SHIFT
- A5XX_TEX_CONST_5_DEPTH
- A5XX_TEX_CONST_5_DEPTH__MASK
- A5XX_TEX_CONST_5_DEPTH__SHIFT
- A5XX_TEX_CUBE
- A5XX_TEX_LINEAR
- A5XX_TEX_MIRROR_CLAMP
- A5XX_TEX_MIRROR_REPEAT
- A5XX_TEX_NEAREST
- A5XX_TEX_ONE
- A5XX_TEX_REPEAT
- A5XX_TEX_SAMP_0_ANISO
- A5XX_TEX_SAMP_0_ANISO__MASK
- A5XX_TEX_SAMP_0_ANISO__SHIFT
- A5XX_TEX_SAMP_0_LOD_BIAS
- A5XX_TEX_SAMP_0_LOD_BIAS__MASK
- A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT
- A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR
- A5XX_TEX_SAMP_0_WRAP_R
- A5XX_TEX_SAMP_0_WRAP_R__MASK
- A5XX_TEX_SAMP_0_WRAP_R__SHIFT
- A5XX_TEX_SAMP_0_WRAP_S
- A5XX_TEX_SAMP_0_WRAP_S__MASK
- A5XX_TEX_SAMP_0_WRAP_S__SHIFT
- A5XX_TEX_SAMP_0_WRAP_T
- A5XX_TEX_SAMP_0_WRAP_T__MASK
- A5XX_TEX_SAMP_0_WRAP_T__SHIFT
- A5XX_TEX_SAMP_0_XY_MAG
- A5XX_TEX_SAMP_0_XY_MAG__MASK
- A5XX_TEX_SAMP_0_XY_MAG__SHIFT
- A5XX_TEX_SAMP_0_XY_MIN
- A5XX_TEX_SAMP_0_XY_MIN__MASK
- A5XX_TEX_SAMP_0_XY_MIN__SHIFT
- A5XX_TEX_SAMP_1_COMPARE_FUNC
- A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK
- A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT
- A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF
- A5XX_TEX_SAMP_1_MAX_LOD
- A5XX_TEX_SAMP_1_MAX_LOD__MASK
- A5XX_TEX_SAMP_1_MAX_LOD__SHIFT
- A5XX_TEX_SAMP_1_MIN_LOD
- A5XX_TEX_SAMP_1_MIN_LOD__MASK
- A5XX_TEX_SAMP_1_MIN_LOD__SHIFT
- A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR
- A5XX_TEX_SAMP_1_UNNORM_COORDS
- A5XX_TEX_SAMP_2_BCOLOR_OFFSET
- A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK
- A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT
- A5XX_TEX_W
- A5XX_TEX_X
- A5XX_TEX_Y
- A5XX_TEX_Z
- A5XX_TEX_ZERO
- A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE
- A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES
- A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK
- A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES
- A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK
- A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A5XX_VFD_CONTROL_0_VTXCNT
- A5XX_VFD_CONTROL_0_VTXCNT__MASK
- A5XX_VFD_CONTROL_0_VTXCNT__SHIFT
- A5XX_VFD_CONTROL_1_REGID4INST
- A5XX_VFD_CONTROL_1_REGID4INST__MASK
- A5XX_VFD_CONTROL_1_REGID4INST__SHIFT
- A5XX_VFD_CONTROL_1_REGID4PRIMID
- A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK
- A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT
- A5XX_VFD_CONTROL_1_REGID4VTX
- A5XX_VFD_CONTROL_1_REGID4VTX__MASK
- A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT
- A5XX_VFD_CONTROL_2_REGID_PATCHID
- A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK
- A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT
- A5XX_VFD_CONTROL_3_REGID_PATCHID
- A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK
- A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT
- A5XX_VFD_CONTROL_3_REGID_TESSX
- A5XX_VFD_CONTROL_3_REGID_TESSX__MASK
- A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT
- A5XX_VFD_CONTROL_3_REGID_TESSY
- A5XX_VFD_CONTROL_3_REGID_TESSY__MASK
- A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT
- A5XX_VFD_DECODE_INSTR_FLOAT
- A5XX_VFD_DECODE_INSTR_FORMAT
- A5XX_VFD_DECODE_INSTR_FORMAT__MASK
- A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT
- A5XX_VFD_DECODE_INSTR_IDX
- A5XX_VFD_DECODE_INSTR_IDX__MASK
- A5XX_VFD_DECODE_INSTR_IDX__SHIFT
- A5XX_VFD_DECODE_INSTR_INSTANCED
- A5XX_VFD_DECODE_INSTR_SWAP
- A5XX_VFD_DECODE_INSTR_SWAP__MASK
- A5XX_VFD_DECODE_INSTR_SWAP__SHIFT
- A5XX_VFD_DECODE_INSTR_UNK30
- A5XX_VFD_DEST_CNTL_INSTR_REGID
- A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK
- A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT
- A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK
- A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK
- A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT
- A5XX_VPC_CNTL_0_STRIDE_IN_VPC
- A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK
- A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT
- A5XX_VPC_CNTL_0_VARYING
- A5XX_VPC_MODE_CNTL_BINNING_PASS
- A5XX_VPC_PACK_NUMNONPOSVAR
- A5XX_VPC_PACK_NUMNONPOSVAR__MASK
- A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT
- A5XX_VPC_PACK_PSIZELOC
- A5XX_VPC_PACK_PSIZELOC__MASK
- A5XX_VPC_PACK_PSIZELOC__SHIFT
- A5XX_VPC_SO_BUF_CNTL_BUF0
- A5XX_VPC_SO_BUF_CNTL_BUF1
- A5XX_VPC_SO_BUF_CNTL_BUF2
- A5XX_VPC_SO_BUF_CNTL_BUF3
- A5XX_VPC_SO_BUF_CNTL_ENABLE
- A5XX_VPC_SO_CNTL_ENABLE
- A5XX_VPC_SO_OVERRIDE_SO_DISABLE
- A5XX_VPC_SO_PROG_A_BUF
- A5XX_VPC_SO_PROG_A_BUF__MASK
- A5XX_VPC_SO_PROG_A_BUF__SHIFT
- A5XX_VPC_SO_PROG_A_EN
- A5XX_VPC_SO_PROG_A_OFF
- A5XX_VPC_SO_PROG_A_OFF__MASK
- A5XX_VPC_SO_PROG_A_OFF__SHIFT
- A5XX_VPC_SO_PROG_B_BUF
- A5XX_VPC_SO_PROG_B_BUF__MASK
- A5XX_VPC_SO_PROG_B_BUF__SHIFT
- A5XX_VPC_SO_PROG_B_EN
- A5XX_VPC_SO_PROG_B_OFF
- A5XX_VPC_SO_PROG_B_OFF__MASK
- A5XX_VPC_SO_PROG_B_OFF__SHIFT
- A5XX_VSC_BIN_SIZE_HEIGHT
- A5XX_VSC_BIN_SIZE_HEIGHT__MASK
- A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT
- A5XX_VSC_BIN_SIZE_WIDTH
- A5XX_VSC_BIN_SIZE_WIDTH__MASK
- A5XX_VSC_BIN_SIZE_WIDTH__SHIFT
- A5XX_VSC_PIPE_CONFIG_REG_H
- A5XX_VSC_PIPE_CONFIG_REG_H__MASK
- A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT
- A5XX_VSC_PIPE_CONFIG_REG_W
- A5XX_VSC_PIPE_CONFIG_REG_W__MASK
- A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT
- A5XX_VSC_PIPE_CONFIG_REG_X
- A5XX_VSC_PIPE_CONFIG_REG_X__MASK
- A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT
- A5XX_VSC_PIPE_CONFIG_REG_Y
- A5XX_VSC_PIPE_CONFIG_REG_Y__MASK
- A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT
- A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE
- A5XX_VSC_RESOLVE_CNTL_X
- A5XX_VSC_RESOLVE_CNTL_X__MASK
- A5XX_VSC_RESOLVE_CNTL_X__SHIFT
- A5XX_VSC_RESOLVE_CNTL_Y
- A5XX_VSC_RESOLVE_CNTL_Y__MASK
- A5XX_VSC_RESOLVE_CNTL_Y__SHIFT
- A5XX_XML
- A5_FCDE_MARK
- A5_MARK
- A6
- A64_ADD
- A64_ADDSUB_IMM
- A64_ADDSUB_SREG
- A64_ADD_I
- A64_AND
- A64_ANDS
- A64_ASR
- A64_ASRV
- A64_B
- A64_BITFIELD
- A64_BL
- A64_BLR
- A64_BR
- A64_BRANCH
- A64_B_
- A64_CBNZ
- A64_CBZ
- A64_CMP
- A64_COMP_BRANCH
- A64_COND_BRANCH
- A64_COND_CC
- A64_COND_CS
- A64_COND_EQ
- A64_COND_GE
- A64_COND_GT
- A64_COND_HI
- A64_COND_LE
- A64_COND_LS
- A64_COND_LT
- A64_COND_NE
- A64_DATA1
- A64_DATA2
- A64_EOR
- A64_FP
- A64_LDR32
- A64_LDR64
- A64_LDRB
- A64_LDRH
- A64_LDXR
- A64_LOGIC_SREG
- A64_LR
- A64_LSL
- A64_LSLV
- A64_LSR
- A64_LSRV
- A64_LSX
- A64_LS_PAIR
- A64_LS_REG
- A64_MADD
- A64_MOV
- A64_MOVEW
- A64_MOVK
- A64_MOVN
- A64_MOVZ
- A64_MSUB
- A64_MUL
- A64_NEG
- A64_ORR
- A64_POP
- A64_PUSH
- A64_R
- A64_RET
- A64_REV16
- A64_REV32
- A64_REV64
- A64_SBFM
- A64_SIZE
- A64_SP
- A64_STADD
- A64_STR32
- A64_STR64
- A64_STRB
- A64_STRH
- A64_STXR
- A64_SUB
- A64_SUBS
- A64_SUB_I
- A64_TST
- A64_UBFM
- A64_UDIV
- A64_UXTH
- A64_UXTW
- A64_VARIANT
- A64_ZR
- A6XX
- A6XX_CD_DATA_OFFSET
- A6XX_CD_DATA_SIZE
- A6XX_CP_INT_CP_AHB_ERROR
- A6XX_CP_INT_CP_HW_FAULT_ERROR
- A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR
- A6XX_CP_INT_CP_OPCODE_ERROR
- A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR
- A6XX_CP_INT_CP_UCODE_ERROR
- A6XX_CP_INT_CP_VSD_PARITY_ERROR
- A6XX_CP_PROTECT_REG_BASE_ADDR
- A6XX_CP_PROTECT_REG_BASE_ADDR__MASK
- A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT
- A6XX_CP_PROTECT_REG_MASK_LEN
- A6XX_CP_PROTECT_REG_MASK_LEN__MASK
- A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT
- A6XX_CP_PROTECT_REG_READ
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK
- A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT
- A6XX_DBGBUS_A2D
- A6XX_DBGBUS_CCUFCHE
- A6XX_DBGBUS_CCU_0
- A6XX_DBGBUS_CCU_1
- A6XX_DBGBUS_COM
- A6XX_DBGBUS_CP
- A6XX_DBGBUS_CX
- A6XX_DBGBUS_DBGC
- A6XX_DBGBUS_DCS
- A6XX_DBGBUS_DPM
- A6XX_DBGBUS_GBIF_GX
- A6XX_DBGBUS_GMU_CX
- A6XX_DBGBUS_GMU_GX
- A6XX_DBGBUS_GPC
- A6XX_DBGBUS_HLSQ
- A6XX_DBGBUS_HLSQ_SPTP
- A6XX_DBGBUS_LARC
- A6XX_DBGBUS_LRZ
- A6XX_DBGBUS_PC
- A6XX_DBGBUS_RAS
- A6XX_DBGBUS_RBBM
- A6XX_DBGBUS_RBP
- A6XX_DBGBUS_RB_0
- A6XX_DBGBUS_RB_1
- A6XX_DBGBUS_SP_0
- A6XX_DBGBUS_SP_1
- A6XX_DBGBUS_TESS
- A6XX_DBGBUS_TPFCHE
- A6XX_DBGBUS_TPL1_0
- A6XX_DBGBUS_TPL1_1
- A6XX_DBGBUS_TPL1_2
- A6XX_DBGBUS_TPL1_3
- A6XX_DBGBUS_TSE
- A6XX_DBGBUS_UCHE
- A6XX_DBGBUS_UCHE_WRAPPER
- A6XX_DBGBUS_VBIF
- A6XX_DBGBUS_VFDP
- A6XX_DBGBUS_VFD_0
- A6XX_DBGBUS_VFD_1
- A6XX_DBGBUS_VFD_2
- A6XX_DBGBUS_VFD_3
- A6XX_DBGBUS_VPC
- A6XX_DBGBUS_VSC
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK
- A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT
- A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE
- A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK
- A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT
- A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU
- A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK
- A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT
- A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT
- A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK
- A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT
- A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN
- A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK
- A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK
- A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP
- A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE
- A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT
- A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ
- A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB
- A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB
- A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE
- A6XX_GMU_GPU_NAP_CTRL_SID
- A6XX_GMU_GPU_NAP_CTRL_SID__MASK
- A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT
- A6XX_GMU_IRQ_MASK
- A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK
- A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK
- A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK
- A6XX_GMU_OOB_DCVS_CHECK_MASK
- A6XX_GMU_OOB_DCVS_CLEAR_MASK
- A6XX_GMU_OOB_DCVS_SET_MASK
- A6XX_GMU_OOB_GPU_CHECK_MASK
- A6XX_GMU_OOB_GPU_CLEAR_MASK
- A6XX_GMU_OOB_GPU_SET_MASK
- A6XX_GMU_OOB_PERFCNTR_CHECK_MASK
- A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK
- A6XX_GMU_OOB_PERFCNTR_SET_MASK
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT
- A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE
- A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE
- A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON
- A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF
- A6XX_GMU_XML
- A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB
- A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT
- A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK
- A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT
- A6XX_GRAS_2D_BLIT_CNTL_SCISSOR
- A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT
- A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK
- A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT
- A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_2D_DST_BR_X
- A6XX_GRAS_2D_DST_BR_X__MASK
- A6XX_GRAS_2D_DST_BR_X__SHIFT
- A6XX_GRAS_2D_DST_BR_Y
- A6XX_GRAS_2D_DST_BR_Y__MASK
- A6XX_GRAS_2D_DST_BR_Y__SHIFT
- A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_2D_DST_TL_X
- A6XX_GRAS_2D_DST_TL_X__MASK
- A6XX_GRAS_2D_DST_TL_X__SHIFT
- A6XX_GRAS_2D_DST_TL_Y
- A6XX_GRAS_2D_DST_TL_Y__MASK
- A6XX_GRAS_2D_DST_TL_Y__SHIFT
- A6XX_GRAS_2D_SRC_BR_X_X
- A6XX_GRAS_2D_SRC_BR_X_X__MASK
- A6XX_GRAS_2D_SRC_BR_X_X__SHIFT
- A6XX_GRAS_2D_SRC_BR_Y_Y
- A6XX_GRAS_2D_SRC_BR_Y_Y__MASK
- A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT
- A6XX_GRAS_2D_SRC_TL_X_X
- A6XX_GRAS_2D_SRC_TL_X_X__MASK
- A6XX_GRAS_2D_SRC_TL_X_X__SHIFT
- A6XX_GRAS_2D_SRC_TL_Y_Y
- A6XX_GRAS_2D_SRC_TL_Y_Y__MASK
- A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT
- A6XX_GRAS_BIN_CONTROL_BINH
- A6XX_GRAS_BIN_CONTROL_BINH__MASK
- A6XX_GRAS_BIN_CONTROL_BINH__SHIFT
- A6XX_GRAS_BIN_CONTROL_BINNING_PASS
- A6XX_GRAS_BIN_CONTROL_BINW
- A6XX_GRAS_BIN_CONTROL_BINW__MASK
- A6XX_GRAS_BIN_CONTROL_BINW__SHIFT
- A6XX_GRAS_BIN_CONTROL_USE_VIZ
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK
- A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT
- A6XX_GRAS_CL_VPORT_XOFFSET_0
- A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK
- A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT
- A6XX_GRAS_CL_VPORT_XSCALE_0
- A6XX_GRAS_CL_VPORT_XSCALE_0__MASK
- A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT
- A6XX_GRAS_CL_VPORT_YOFFSET_0
- A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK
- A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT
- A6XX_GRAS_CL_VPORT_YSCALE_0
- A6XX_GRAS_CL_VPORT_YSCALE_0__MASK
- A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT
- A6XX_GRAS_CL_VPORT_ZOFFSET_0
- A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK
- A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT
- A6XX_GRAS_CL_VPORT_ZSCALE_0
- A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK
- A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT
- A6XX_GRAS_CNTL_UNK3
- A6XX_GRAS_CNTL_VARYING
- A6XX_GRAS_CNTL_WCOORD
- A6XX_GRAS_CNTL_XCOORD
- A6XX_GRAS_CNTL_YCOORD
- A6XX_GRAS_CNTL_ZCOORD
- A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
- A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES
- A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK
- A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH
- A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK
- A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT
- A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH
- A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK
- A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT
- A6XX_GRAS_LRZ_CNTL_ENABLE
- A6XX_GRAS_LRZ_CNTL_GREATER
- A6XX_GRAS_LRZ_CNTL_LRZ_WRITE
- A6XX_GRAS_LRZ_CNTL_UNK3
- A6XX_GRAS_LRZ_CNTL_UNK4
- A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES
- A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK
- A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_RESOLVE_CNTL_1_X
- A6XX_GRAS_RESOLVE_CNTL_1_X__MASK
- A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT
- A6XX_GRAS_RESOLVE_CNTL_1_Y
- A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK
- A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT
- A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_RESOLVE_CNTL_2_X
- A6XX_GRAS_RESOLVE_CNTL_2_X__MASK
- A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT
- A6XX_GRAS_RESOLVE_CNTL_2_Y
- A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK
- A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK
- A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
- A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
- A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
- A6XX_GRAS_SU_CNTL_CULL_BACK
- A6XX_GRAS_SU_CNTL_CULL_FRONT
- A6XX_GRAS_SU_CNTL_FRONT_CW
- A6XX_GRAS_SU_CNTL_LINEHALFWIDTH
- A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
- A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT
- A6XX_GRAS_SU_CNTL_MSAA_ENABLE
- A6XX_GRAS_SU_CNTL_POLY_OFFSET
- A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT
- A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
- A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
- A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
- A6XX_GRAS_SU_POINT_MINMAX_MAX
- A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK
- A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
- A6XX_GRAS_SU_POINT_MINMAX_MIN
- A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK
- A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
- A6XX_GRAS_SU_POINT_SIZE
- A6XX_GRAS_SU_POINT_SIZE__MASK
- A6XX_GRAS_SU_POINT_SIZE__SHIFT
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
- A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
- A6XX_GRAS_SU_POLY_OFFSET_SCALE
- A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
- A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT
- A6XX_HFI_H2F_IRQ_MASK_BIT
- A6XX_HFI_IRQ_BLOCKED_MSG_MASK
- A6XX_HFI_IRQ_CM3_FAULT_MASK
- A6XX_HFI_IRQ_DSGQ_MASK
- A6XX_HFI_IRQ_GMU_ERR_MASK
- A6XX_HFI_IRQ_GMU_ERR_MASK__MASK
- A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT
- A6XX_HFI_IRQ_MASK
- A6XX_HFI_IRQ_MSGQ_MASK
- A6XX_HFI_IRQ_OOB_MASK
- A6XX_HFI_IRQ_OOB_MASK__MASK
- A6XX_HFI_IRQ_OOB_MASK__SHIFT
- A6XX_HLSQ_BACKEND_META
- A6XX_HLSQ_CHUNK_CPS_RAM
- A6XX_HLSQ_CHUNK_CPS_RAM_TAG
- A6XX_HLSQ_CHUNK_CVS_RAM
- A6XX_HLSQ_CHUNK_CVS_RAM_TAG
- A6XX_HLSQ_CONTROL_2_REG_FACEREGID
- A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
- A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEID
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT
- A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID
- A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK
- A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT
- A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID
- A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
- A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT
- A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID
- A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
- A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT
- A6XX_HLSQ_CPS_MISC_RAM
- A6XX_HLSQ_CPS_MISC_RAM_TAG
- A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID
- A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK
- A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT
- A6XX_HLSQ_CS_CNTL_0_UNK0
- A6XX_HLSQ_CS_CNTL_0_UNK0__MASK
- A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT
- A6XX_HLSQ_CS_CNTL_0_UNK1
- A6XX_HLSQ_CS_CNTL_0_UNK1__MASK
- A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT
- A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID
- A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK
- A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT
- A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM
- A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK
- A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK
- A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT
- A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X
- A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK
- A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT
- A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X
- A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK
- A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT
- A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y
- A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK
- A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT
- A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y
- A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK
- A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT
- A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z
- A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK
- A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT
- A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z
- A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK
- A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT
- A6XX_HLSQ_CVS_MISC_RAM
- A6XX_HLSQ_CVS_MISC_RAM_TAG
- A6XX_HLSQ_DATAPATH_META
- A6XX_HLSQ_DS_CNTL_CONSTLEN
- A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK
- A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT
- A6XX_HLSQ_FRONTEND_META
- A6XX_HLSQ_FS_CNTL_CONSTLEN
- A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK
- A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT
- A6XX_HLSQ_GFX_CPS_CONST_RAM
- A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG
- A6XX_HLSQ_GFX_CVS_CONST_RAM
- A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG
- A6XX_HLSQ_GS_CNTL_CONSTLEN
- A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK
- A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT
- A6XX_HLSQ_HS_CNTL_CONSTLEN
- A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK
- A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT
- A6XX_HLSQ_ICB_CPS_CB_BASE_TAG
- A6XX_HLSQ_ICB_CVS_CB_BASE_TAG
- A6XX_HLSQ_INDIRECT_META
- A6XX_HLSQ_INST_RAM
- A6XX_HLSQ_INST_RAM_TAG
- A6XX_HLSQ_PWR_REST_RAM
- A6XX_HLSQ_PWR_REST_TAG
- A6XX_HLSQ_VS_CNTL_CONSTLEN
- A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK
- A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT
- A6XX_INT_MASK
- A6XX_NUM_CONTEXTS
- A6XX_NUM_SHADER_BANKS
- A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART
- A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST
- A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
- A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC
- A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK
- A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT
- A6XX_PROTECT_RDONLY
- A6XX_PROTECT_RW
- A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR
- A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS
- A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS
- A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS
- A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS
- A6XX_RBBM_INT_0_MASK_CP_HW_ERROR
- A6XX_RBBM_INT_0_MASK_CP_IB1
- A6XX_RBBM_INT_0_MASK_CP_IB2
- A6XX_RBBM_INT_0_MASK_CP_RB
- A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS
- A6XX_RBBM_INT_0_MASK_CP_SW
- A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS
- A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0
- A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1
- A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ
- A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG
- A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW
- A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW
- A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR
- A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE
- A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT
- A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS
- A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR
- A6XX_RBBM_STATUS_A2D_BUSY
- A6XX_RBBM_STATUS_CCU_BUSY
- A6XX_RBBM_STATUS_COM_DCOM_BUSY
- A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER
- A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER
- A6XX_RBBM_STATUS_CP_BUSY
- A6XX_RBBM_STATUS_GFX_DBGC_BUSY
- A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB
- A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP
- A6XX_RBBM_STATUS_HLSQ_BUSY
- A6XX_RBBM_STATUS_LRZ_BUSY
- A6XX_RBBM_STATUS_PC_DCALL_BUSY
- A6XX_RBBM_STATUS_PC_VSD_BUSY
- A6XX_RBBM_STATUS_RAS_BUSY
- A6XX_RBBM_STATUS_RB_BUSY
- A6XX_RBBM_STATUS_SP_BUSY
- A6XX_RBBM_STATUS_TESS_BUSY
- A6XX_RBBM_STATUS_TPL1_BUSY
- A6XX_RBBM_STATUS_TSE_BUSY
- A6XX_RBBM_STATUS_UCHE_BUSY
- A6XX_RBBM_STATUS_VBIF_BUSY
- A6XX_RBBM_STATUS_VFD_BUSY
- A6XX_RBBM_STATUS_VPC_BUSY
- A6XX_RBBM_STATUS_VSC_BUSY
- A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT
- A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK
- A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT
- A6XX_RB_2D_BLIT_CNTL_SCISSOR
- A6XX_RB_2D_DST_INFO_COLOR_FORMAT
- A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK
- A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT
- A6XX_RB_2D_DST_INFO_COLOR_SWAP
- A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK
- A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT
- A6XX_RB_2D_DST_INFO_FLAGS
- A6XX_RB_2D_DST_INFO_TILE_MODE
- A6XX_RB_2D_DST_INFO_TILE_MODE__MASK
- A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT
- A6XX_RB_2D_DST_SIZE_PITCH
- A6XX_RB_2D_DST_SIZE_PITCH__MASK
- A6XX_RB_2D_DST_SIZE_PITCH__SHIFT
- A6XX_RB_ALPHA_CONTROL_ALPHA_REF
- A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
- A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT
- A6XX_RB_ALPHA_CONTROL_ALPHA_TEST
- A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC
- A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
- A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT
- A6XX_RB_BIN_CONTROL2_BINH
- A6XX_RB_BIN_CONTROL2_BINH__MASK
- A6XX_RB_BIN_CONTROL2_BINH__SHIFT
- A6XX_RB_BIN_CONTROL2_BINW
- A6XX_RB_BIN_CONTROL2_BINW__MASK
- A6XX_RB_BIN_CONTROL2_BINW__SHIFT
- A6XX_RB_BIN_CONTROL_BINH
- A6XX_RB_BIN_CONTROL_BINH__MASK
- A6XX_RB_BIN_CONTROL_BINH__SHIFT
- A6XX_RB_BIN_CONTROL_BINNING_PASS
- A6XX_RB_BIN_CONTROL_BINW
- A6XX_RB_BIN_CONTROL_BINW__MASK
- A6XX_RB_BIN_CONTROL_BINW__SHIFT
- A6XX_RB_BIN_CONTROL_USE_VIZ
- A6XX_RB_BLEND_ALPHA_F32
- A6XX_RB_BLEND_ALPHA_F32__MASK
- A6XX_RB_BLEND_ALPHA_F32__SHIFT
- A6XX_RB_BLEND_BLUE_F32
- A6XX_RB_BLEND_BLUE_F32__MASK
- A6XX_RB_BLEND_BLUE_F32__SHIFT
- A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
- A6XX_RB_BLEND_CNTL_ENABLE_BLEND
- A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
- A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
- A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
- A6XX_RB_BLEND_CNTL_SAMPLE_MASK
- A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK
- A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT
- A6XX_RB_BLEND_GREEN_F32
- A6XX_RB_BLEND_GREEN_F32__MASK
- A6XX_RB_BLEND_GREEN_F32__SHIFT
- A6XX_RB_BLEND_RED_F32
- A6XX_RB_BLEND_RED_F32__MASK
- A6XX_RB_BLEND_RED_F32__SHIFT
- A6XX_RB_BLIT_DST_ARRAY_PITCH
- A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK
- A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT
- A6XX_RB_BLIT_DST_INFO_COLOR_SWAP
- A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK
- A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT
- A6XX_RB_BLIT_DST_INFO_FLAGS
- A6XX_RB_BLIT_DST_INFO_SAMPLES
- A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK
- A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT
- A6XX_RB_BLIT_DST_INFO_TILE_MODE
- A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK
- A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT
- A6XX_RB_BLIT_DST_PITCH
- A6XX_RB_BLIT_DST_PITCH__MASK
- A6XX_RB_BLIT_DST_PITCH__SHIFT
- A6XX_RB_BLIT_INFO_CLEAR_MASK
- A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK
- A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT
- A6XX_RB_BLIT_INFO_DEPTH
- A6XX_RB_BLIT_INFO_GMEM
- A6XX_RB_BLIT_INFO_INTEGER
- A6XX_RB_BLIT_INFO_UNK0
- A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE
- A6XX_RB_BLIT_SCISSOR_BR_X
- A6XX_RB_BLIT_SCISSOR_BR_X__MASK
- A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT
- A6XX_RB_BLIT_SCISSOR_BR_Y
- A6XX_RB_BLIT_SCISSOR_BR_Y__MASK
- A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT
- A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE
- A6XX_RB_BLIT_SCISSOR_TL_X
- A6XX_RB_BLIT_SCISSOR_TL_X__MASK
- A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT
- A6XX_RB_BLIT_SCISSOR_TL_Y
- A6XX_RB_BLIT_SCISSOR_TL_Y__MASK
- A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT
- A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH
- A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK
- A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT
- A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT
- A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
- A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
- A6XX_RB_DEPTH_BUFFER_PITCH
- A6XX_RB_DEPTH_BUFFER_PITCH__MASK
- A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT
- A6XX_RB_DEPTH_CNTL_ZFUNC
- A6XX_RB_DEPTH_CNTL_ZFUNC__MASK
- A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT
- A6XX_RB_DEPTH_CNTL_Z_ENABLE
- A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
- A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
- A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
- A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
- A6XX_RB_DEST_MSAA_CNTL_SAMPLES
- A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK
- A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK
- A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT
- A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
- A6XX_RB_FS_OUTPUT_CNTL1_MRT
- A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK
- A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT
- A6XX_RB_LRZ_CNTL_ENABLE
- A6XX_RB_MRT_ARRAY_PITCH
- A6XX_RB_MRT_ARRAY_PITCH__MASK
- A6XX_RB_MRT_ARRAY_PITCH__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
- A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE
- A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
- A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR
- A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
- A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
- A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR
- A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
- A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
- A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT
- A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
- A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
- A6XX_RB_MRT_BUF_INFO_COLOR_SWAP
- A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
- A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
- A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE
- A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
- A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
- A6XX_RB_MRT_CONTROL_BLEND
- A6XX_RB_MRT_CONTROL_BLEND2
- A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE
- A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
- A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
- A6XX_RB_MRT_CONTROL_ROP_CODE
- A6XX_RB_MRT_CONTROL_ROP_CODE__MASK
- A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
- A6XX_RB_MRT_CONTROL_ROP_ENABLE
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT
- A6XX_RB_MRT_PITCH
- A6XX_RB_MRT_PITCH__MASK
- A6XX_RB_MRT_PITCH__SHIFT
- A6XX_RB_MSAA_CNTL_SAMPLES
- A6XX_RB_MSAA_CNTL_SAMPLES__MASK
- A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_RB_RAS_MSAA_CNTL_SAMPLES
- A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK
- A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_RB_RENDER_CNTL_BINNING
- A6XX_RB_RENDER_CNTL_FLAG_DEPTH
- A6XX_RB_RENDER_CNTL_FLAG_MRTS
- A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK
- A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT
- A6XX_RB_RENDER_CNTL_UNK4
- A6XX_RB_RENDER_COMPONENTS_RT0
- A6XX_RB_RENDER_COMPONENTS_RT0__MASK
- A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT1
- A6XX_RB_RENDER_COMPONENTS_RT1__MASK
- A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT2
- A6XX_RB_RENDER_COMPONENTS_RT2__MASK
- A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT3
- A6XX_RB_RENDER_COMPONENTS_RT3__MASK
- A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT4
- A6XX_RB_RENDER_COMPONENTS_RT4__MASK
- A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT5
- A6XX_RB_RENDER_COMPONENTS_RT5__MASK
- A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT6
- A6XX_RB_RENDER_COMPONENTS_RT6__MASK
- A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT
- A6XX_RB_RENDER_COMPONENTS_RT7
- A6XX_RB_RENDER_COMPONENTS_RT7__MASK
- A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT
- A6XX_RB_RENDER_CONTROL0_UNK10
- A6XX_RB_RENDER_CONTROL0_UNK3
- A6XX_RB_RENDER_CONTROL0_VARYING
- A6XX_RB_RENDER_CONTROL0_WCOORD
- A6XX_RB_RENDER_CONTROL0_XCOORD
- A6XX_RB_RENDER_CONTROL0_YCOORD
- A6XX_RB_RENDER_CONTROL0_ZCOORD
- A6XX_RB_RENDER_CONTROL1_FACENESS
- A6XX_RB_RENDER_CONTROL1_SAMPLEID
- A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
- A6XX_RB_SAMPLE_COUNT_CONTROL_COPY
- A6XX_RB_SRGB_CNTL_SRGB_MRT0
- A6XX_RB_SRGB_CNTL_SRGB_MRT1
- A6XX_RB_SRGB_CNTL_SRGB_MRT2
- A6XX_RB_SRGB_CNTL_SRGB_MRT3
- A6XX_RB_SRGB_CNTL_SRGB_MRT4
- A6XX_RB_SRGB_CNTL_SRGB_MRT5
- A6XX_RB_SRGB_CNTL_SRGB_MRT6
- A6XX_RB_SRGB_CNTL_SRGB_MRT7
- A6XX_RB_STENCILMASK_BFMASK
- A6XX_RB_STENCILMASK_BFMASK__MASK
- A6XX_RB_STENCILMASK_BFMASK__SHIFT
- A6XX_RB_STENCILMASK_MASK
- A6XX_RB_STENCILMASK_MASK__MASK
- A6XX_RB_STENCILMASK_MASK__SHIFT
- A6XX_RB_STENCILREF_BFREF
- A6XX_RB_STENCILREF_BFREF__MASK
- A6XX_RB_STENCILREF_BFREF__SHIFT
- A6XX_RB_STENCILREF_REF
- A6XX_RB_STENCILREF_REF__MASK
- A6XX_RB_STENCILREF_REF__SHIFT
- A6XX_RB_STENCILWRMASK_BFWRMASK
- A6XX_RB_STENCILWRMASK_BFWRMASK__MASK
- A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT
- A6XX_RB_STENCILWRMASK_WRMASK
- A6XX_RB_STENCILWRMASK_WRMASK__MASK
- A6XX_RB_STENCILWRMASK_WRMASK__SHIFT
- A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH
- A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK
- A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT
- A6XX_RB_STENCIL_BUFFER_PITCH
- A6XX_RB_STENCIL_BUFFER_PITCH__MASK
- A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT
- A6XX_RB_STENCIL_CONTROL_FAIL
- A6XX_RB_STENCIL_CONTROL_FAIL_BF
- A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
- A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
- A6XX_RB_STENCIL_CONTROL_FAIL__MASK
- A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT
- A6XX_RB_STENCIL_CONTROL_FUNC
- A6XX_RB_STENCIL_CONTROL_FUNC_BF
- A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
- A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
- A6XX_RB_STENCIL_CONTROL_FUNC__MASK
- A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT
- A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
- A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
- A6XX_RB_STENCIL_CONTROL_STENCIL_READ
- A6XX_RB_STENCIL_CONTROL_ZFAIL
- A6XX_RB_STENCIL_CONTROL_ZFAIL_BF
- A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
- A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
- A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK
- A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
- A6XX_RB_STENCIL_CONTROL_ZPASS
- A6XX_RB_STENCIL_CONTROL_ZPASS_BF
- A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
- A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
- A6XX_RB_STENCIL_CONTROL_ZPASS__MASK
- A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
- A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL
- A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE
- A6XX_RB_WINDOW_OFFSET2_X
- A6XX_RB_WINDOW_OFFSET2_X__MASK
- A6XX_RB_WINDOW_OFFSET2_X__SHIFT
- A6XX_RB_WINDOW_OFFSET2_Y
- A6XX_RB_WINDOW_OFFSET2_Y__MASK
- A6XX_RB_WINDOW_OFFSET2_Y__SHIFT
- A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE
- A6XX_RB_WINDOW_OFFSET_X
- A6XX_RB_WINDOW_OFFSET_X__MASK
- A6XX_RB_WINDOW_OFFSET_X__SHIFT
- A6XX_RB_WINDOW_OFFSET_Y
- A6XX_RB_WINDOW_OFFSET_Y__MASK
- A6XX_RB_WINDOW_OFFSET_Y__SHIFT
- A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
- A6XX_SP_BLEND_CNTL_ENABLED
- A6XX_SP_BLEND_CNTL_UNK8
- A6XX_SP_CB_BINDLESS_DATA
- A6XX_SP_CB_BINDLESS_TAG
- A6XX_SP_CB_LEGACY_DATA
- A6XX_SP_CS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_CS_CTRL_REG0_MERGEDREGS
- A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_CS_CTRL_REG0_THREADSIZE
- A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_CS_CTRL_REG0_VARYING
- A6XX_SP_DS_CONFIG_ENABLED
- A6XX_SP_DS_CONFIG_NSAMP
- A6XX_SP_DS_CONFIG_NSAMP__MASK
- A6XX_SP_DS_CONFIG_NSAMP__SHIFT
- A6XX_SP_DS_CONFIG_NTEX
- A6XX_SP_DS_CONFIG_NTEX__MASK
- A6XX_SP_DS_CONFIG_NTEX__SHIFT
- A6XX_SP_DS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_DS_CTRL_REG0_MERGEDREGS
- A6XX_SP_DS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_DS_CTRL_REG0_THREADSIZE
- A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_DS_CTRL_REG0_VARYING
- A6XX_SP_FS_CONFIG_ENABLED
- A6XX_SP_FS_CONFIG_NSAMP
- A6XX_SP_FS_CONFIG_NSAMP__MASK
- A6XX_SP_FS_CONFIG_NSAMP__SHIFT
- A6XX_SP_FS_CONFIG_NTEX
- A6XX_SP_FS_CONFIG_NTEX__MASK
- A6XX_SP_FS_CONFIG_NTEX__SHIFT
- A6XX_SP_FS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_FS_CTRL_REG0_MERGEDREGS
- A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_FS_CTRL_REG0_THREADSIZE
- A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_FS_CTRL_REG0_VARYING
- A6XX_SP_FS_MRT_REG_COLOR_FORMAT
- A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK
- A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT
- A6XX_SP_FS_MRT_REG_COLOR_SINT
- A6XX_SP_FS_MRT_REG_COLOR_UINT
- A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID
- A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK
- A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT
- A6XX_SP_FS_OUTPUT_CNTL1_MRT
- A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK
- A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT
- A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
- A6XX_SP_FS_OUTPUT_REG_REGID
- A6XX_SP_FS_OUTPUT_REG_REGID__MASK
- A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT0
- A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT1
- A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT2
- A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT3
- A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT4
- A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT5
- A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT6
- A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT
- A6XX_SP_FS_RENDER_COMPONENTS_RT7
- A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK
- A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT
- A6XX_SP_GS_CONFIG_ENABLED
- A6XX_SP_GS_CONFIG_NSAMP
- A6XX_SP_GS_CONFIG_NSAMP__MASK
- A6XX_SP_GS_CONFIG_NSAMP__SHIFT
- A6XX_SP_GS_CONFIG_NTEX
- A6XX_SP_GS_CONFIG_NTEX__MASK
- A6XX_SP_GS_CONFIG_NTEX__SHIFT
- A6XX_SP_GS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_GS_CTRL_REG0_MERGEDREGS
- A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_GS_CTRL_REG0_THREADSIZE
- A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_GS_CTRL_REG0_VARYING
- A6XX_SP_HS_CONFIG_ENABLED
- A6XX_SP_HS_CONFIG_NSAMP
- A6XX_SP_HS_CONFIG_NSAMP__MASK
- A6XX_SP_HS_CONFIG_NSAMP__SHIFT
- A6XX_SP_HS_CONFIG_NTEX
- A6XX_SP_HS_CONFIG_NTEX__MASK
- A6XX_SP_HS_CONFIG_NTEX__SHIFT
- A6XX_SP_HS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_HS_CTRL_REG0_MERGEDREGS
- A6XX_SP_HS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_HS_CTRL_REG0_THREADSIZE
- A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_HS_CTRL_REG0_VARYING
- A6XX_SP_INST_DATA
- A6XX_SP_INST_TAG
- A6XX_SP_LB_0_DATA
- A6XX_SP_LB_1_DATA
- A6XX_SP_LB_2_DATA
- A6XX_SP_LB_3_DATA
- A6XX_SP_LB_4_DATA
- A6XX_SP_LB_5_DATA
- A6XX_SP_PRIMITIVE_CNTL_VSOUT
- A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK
- A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT
- A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT
- A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK
- A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT
- A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP
- A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK
- A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT
- A6XX_SP_PS_2D_SRC_INFO_FILTER
- A6XX_SP_PS_2D_SRC_INFO_FLAGS
- A6XX_SP_PS_2D_SRC_INFO_TILE_MODE
- A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK
- A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT
- A6XX_SP_PS_2D_SRC_PITCH_PITCH
- A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK
- A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT
- A6XX_SP_PS_2D_SRC_SIZE_HEIGHT
- A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK
- A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT
- A6XX_SP_PS_2D_SRC_SIZE_WIDTH
- A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK
- A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT
- A6XX_SP_SMO_TAG
- A6XX_SP_SRGB_CNTL_SRGB_MRT0
- A6XX_SP_SRGB_CNTL_SRGB_MRT1
- A6XX_SP_SRGB_CNTL_SRGB_MRT2
- A6XX_SP_SRGB_CNTL_SRGB_MRT3
- A6XX_SP_SRGB_CNTL_SRGB_MRT4
- A6XX_SP_SRGB_CNTL_SRGB_MRT5
- A6XX_SP_SRGB_CNTL_SRGB_MRT6
- A6XX_SP_SRGB_CNTL_SRGB_MRT7
- A6XX_SP_STATE_DATA
- A6XX_SP_TMO_UMO_TAG
- A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
- A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES
- A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK
- A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES
- A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK
- A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT
- A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE
- A6XX_SP_TP_WINDOW_OFFSET_X
- A6XX_SP_TP_WINDOW_OFFSET_X__MASK
- A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT
- A6XX_SP_TP_WINDOW_OFFSET_Y
- A6XX_SP_TP_WINDOW_OFFSET_Y__MASK
- A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT
- A6XX_SP_UAV_DATA
- A6XX_SP_VS_CONFIG_ENABLED
- A6XX_SP_VS_CONFIG_NSAMP
- A6XX_SP_VS_CONFIG_NSAMP__MASK
- A6XX_SP_VS_CONFIG_NSAMP__SHIFT
- A6XX_SP_VS_CONFIG_NTEX
- A6XX_SP_VS_CONFIG_NTEX__MASK
- A6XX_SP_VS_CONFIG_NTEX__SHIFT
- A6XX_SP_VS_CTRL_REG0_BRANCHSTACK
- A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK
- A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT
- A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT
- A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
- A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
- A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT
- A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
- A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
- A6XX_SP_VS_CTRL_REG0_MERGEDREGS
- A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
- A6XX_SP_VS_CTRL_REG0_THREADSIZE
- A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
- A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
- A6XX_SP_VS_CTRL_REG0_VARYING
- A6XX_SP_VS_OUT_REG_A_COMPMASK
- A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK
- A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
- A6XX_SP_VS_OUT_REG_A_REGID
- A6XX_SP_VS_OUT_REG_A_REGID__MASK
- A6XX_SP_VS_OUT_REG_A_REGID__SHIFT
- A6XX_SP_VS_OUT_REG_B_COMPMASK
- A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK
- A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
- A6XX_SP_VS_OUT_REG_B_REGID
- A6XX_SP_VS_OUT_REG_B_REGID__MASK
- A6XX_SP_VS_OUT_REG_B_REGID__SHIFT
- A6XX_SP_VS_VPC_DST_REG_OUTLOC0
- A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
- A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
- A6XX_SP_VS_VPC_DST_REG_OUTLOC1
- A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
- A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
- A6XX_SP_VS_VPC_DST_REG_OUTLOC2
- A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
- A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
- A6XX_SP_VS_VPC_DST_REG_OUTLOC3
- A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
- A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
- A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE
- A6XX_SP_WINDOW_OFFSET_X
- A6XX_SP_WINDOW_OFFSET_X__MASK
- A6XX_SP_WINDOW_OFFSET_X__SHIFT
- A6XX_SP_WINDOW_OFFSET_Y
- A6XX_SP_WINDOW_OFFSET_Y__MASK
- A6XX_SP_WINDOW_OFFSET_Y__SHIFT
- A6XX_TEX_1D
- A6XX_TEX_2D
- A6XX_TEX_3D
- A6XX_TEX_ANISO
- A6XX_TEX_ANISO_1
- A6XX_TEX_ANISO_16
- A6XX_TEX_ANISO_2
- A6XX_TEX_ANISO_4
- A6XX_TEX_ANISO_8
- A6XX_TEX_CLAMP_TO_BORDER
- A6XX_TEX_CLAMP_TO_EDGE
- A6XX_TEX_CONST_0_FMT
- A6XX_TEX_CONST_0_FMT__MASK
- A6XX_TEX_CONST_0_FMT__SHIFT
- A6XX_TEX_CONST_0_MIPLVLS
- A6XX_TEX_CONST_0_MIPLVLS__MASK
- A6XX_TEX_CONST_0_MIPLVLS__SHIFT
- A6XX_TEX_CONST_0_SAMPLES
- A6XX_TEX_CONST_0_SAMPLES__MASK
- A6XX_TEX_CONST_0_SAMPLES__SHIFT
- A6XX_TEX_CONST_0_SRGB
- A6XX_TEX_CONST_0_SWAP
- A6XX_TEX_CONST_0_SWAP__MASK
- A6XX_TEX_CONST_0_SWAP__SHIFT
- A6XX_TEX_CONST_0_SWIZ_W
- A6XX_TEX_CONST_0_SWIZ_W__MASK
- A6XX_TEX_CONST_0_SWIZ_W__SHIFT
- A6XX_TEX_CONST_0_SWIZ_X
- A6XX_TEX_CONST_0_SWIZ_X__MASK
- A6XX_TEX_CONST_0_SWIZ_X__SHIFT
- A6XX_TEX_CONST_0_SWIZ_Y
- A6XX_TEX_CONST_0_SWIZ_Y__MASK
- A6XX_TEX_CONST_0_SWIZ_Y__SHIFT
- A6XX_TEX_CONST_0_SWIZ_Z
- A6XX_TEX_CONST_0_SWIZ_Z__MASK
- A6XX_TEX_CONST_0_SWIZ_Z__SHIFT
- A6XX_TEX_CONST_0_TILE_MODE
- A6XX_TEX_CONST_0_TILE_MODE__MASK
- A6XX_TEX_CONST_0_TILE_MODE__SHIFT
- A6XX_TEX_CONST_1_HEIGHT
- A6XX_TEX_CONST_1_HEIGHT__MASK
- A6XX_TEX_CONST_1_HEIGHT__SHIFT
- A6XX_TEX_CONST_1_WIDTH
- A6XX_TEX_CONST_1_WIDTH__MASK
- A6XX_TEX_CONST_1_WIDTH__SHIFT
- A6XX_TEX_CONST_2_FETCHSIZE
- A6XX_TEX_CONST_2_FETCHSIZE__MASK
- A6XX_TEX_CONST_2_FETCHSIZE__SHIFT
- A6XX_TEX_CONST_2_PITCH
- A6XX_TEX_CONST_2_PITCH__MASK
- A6XX_TEX_CONST_2_PITCH__SHIFT
- A6XX_TEX_CONST_2_TYPE
- A6XX_TEX_CONST_2_TYPE__MASK
- A6XX_TEX_CONST_2_TYPE__SHIFT
- A6XX_TEX_CONST_3_ARRAY_PITCH
- A6XX_TEX_CONST_3_ARRAY_PITCH__MASK
- A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT
- A6XX_TEX_CONST_3_FLAG
- A6XX_TEX_CONST_4_BASE_LO
- A6XX_TEX_CONST_4_BASE_LO__MASK
- A6XX_TEX_CONST_4_BASE_LO__SHIFT
- A6XX_TEX_CONST_5_BASE_HI
- A6XX_TEX_CONST_5_BASE_HI__MASK
- A6XX_TEX_CONST_5_BASE_HI__SHIFT
- A6XX_TEX_CONST_5_DEPTH
- A6XX_TEX_CONST_5_DEPTH__MASK
- A6XX_TEX_CONST_5_DEPTH__SHIFT
- A6XX_TEX_CONST_7_FLAG_LO
- A6XX_TEX_CONST_7_FLAG_LO__MASK
- A6XX_TEX_CONST_7_FLAG_LO__SHIFT
- A6XX_TEX_CONST_8_FLAG_HI
- A6XX_TEX_CONST_8_FLAG_HI__MASK
- A6XX_TEX_CONST_8_FLAG_HI__SHIFT
- A6XX_TEX_CUBE
- A6XX_TEX_LINEAR
- A6XX_TEX_MIRROR_CLAMP
- A6XX_TEX_MIRROR_REPEAT
- A6XX_TEX_NEAREST
- A6XX_TEX_ONE
- A6XX_TEX_REPEAT
- A6XX_TEX_SAMP_0_ANISO
- A6XX_TEX_SAMP_0_ANISO__MASK
- A6XX_TEX_SAMP_0_ANISO__SHIFT
- A6XX_TEX_SAMP_0_LOD_BIAS
- A6XX_TEX_SAMP_0_LOD_BIAS__MASK
- A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT
- A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR
- A6XX_TEX_SAMP_0_WRAP_R
- A6XX_TEX_SAMP_0_WRAP_R__MASK
- A6XX_TEX_SAMP_0_WRAP_R__SHIFT
- A6XX_TEX_SAMP_0_WRAP_S
- A6XX_TEX_SAMP_0_WRAP_S__MASK
- A6XX_TEX_SAMP_0_WRAP_S__SHIFT
- A6XX_TEX_SAMP_0_WRAP_T
- A6XX_TEX_SAMP_0_WRAP_T__MASK
- A6XX_TEX_SAMP_0_WRAP_T__SHIFT
- A6XX_TEX_SAMP_0_XY_MAG
- A6XX_TEX_SAMP_0_XY_MAG__MASK
- A6XX_TEX_SAMP_0_XY_MAG__SHIFT
- A6XX_TEX_SAMP_0_XY_MIN
- A6XX_TEX_SAMP_0_XY_MIN__MASK
- A6XX_TEX_SAMP_0_XY_MIN__SHIFT
- A6XX_TEX_SAMP_1_COMPARE_FUNC
- A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK
- A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT
- A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF
- A6XX_TEX_SAMP_1_MAX_LOD
- A6XX_TEX_SAMP_1_MAX_LOD__MASK
- A6XX_TEX_SAMP_1_MAX_LOD__SHIFT
- A6XX_TEX_SAMP_1_MIN_LOD
- A6XX_TEX_SAMP_1_MIN_LOD__MASK
- A6XX_TEX_SAMP_1_MIN_LOD__SHIFT
- A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR
- A6XX_TEX_SAMP_1_UNNORM_COORDS
- A6XX_TEX_SAMP_2_BCOLOR_OFFSET
- A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK
- A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT
- A6XX_TEX_W
- A6XX_TEX_X
- A6XX_TEX_Y
- A6XX_TEX_Z
- A6XX_TEX_ZERO
- A6XX_TP0_MIPMAP_BASE_DATA
- A6XX_TP0_SMO_DATA
- A6XX_TP0_TMO_DATA
- A6XX_TP1_MIPMAP_BASE_DATA
- A6XX_TP1_SMO_DATA
- A6XX_TP1_TMO_DATA
- A6XX_UCHE_CLIENT_PF_PERFSEL
- A6XX_UCHE_CLIENT_PF_PERFSEL__MASK
- A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT
- A6XX_VBIF_CLKON_FORCE_ON_TESTBUS
- A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL
- A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK
- A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT
- A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL
- A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK
- A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT
- A6XX_VFD_CONTROL_0_VTXCNT
- A6XX_VFD_CONTROL_0_VTXCNT__MASK
- A6XX_VFD_CONTROL_0_VTXCNT__SHIFT
- A6XX_VFD_CONTROL_1_REGID4INST
- A6XX_VFD_CONTROL_1_REGID4INST__MASK
- A6XX_VFD_CONTROL_1_REGID4INST__SHIFT
- A6XX_VFD_CONTROL_1_REGID4PRIMID
- A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK
- A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT
- A6XX_VFD_CONTROL_1_REGID4VTX
- A6XX_VFD_CONTROL_1_REGID4VTX__MASK
- A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT
- A6XX_VFD_CONTROL_2_REGID_PATCHID
- A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK
- A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT
- A6XX_VFD_CONTROL_3_REGID_PATCHID
- A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK
- A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT
- A6XX_VFD_CONTROL_3_REGID_TESSX
- A6XX_VFD_CONTROL_3_REGID_TESSX__MASK
- A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT
- A6XX_VFD_CONTROL_3_REGID_TESSY
- A6XX_VFD_CONTROL_3_REGID_TESSY__MASK
- A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT
- A6XX_VFD_DECODE_INSTR_FLOAT
- A6XX_VFD_DECODE_INSTR_FORMAT
- A6XX_VFD_DECODE_INSTR_FORMAT__MASK
- A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT
- A6XX_VFD_DECODE_INSTR_IDX
- A6XX_VFD_DECODE_INSTR_IDX__MASK
- A6XX_VFD_DECODE_INSTR_IDX__SHIFT
- A6XX_VFD_DECODE_INSTR_INSTANCED
- A6XX_VFD_DECODE_INSTR_SWAP
- A6XX_VFD_DECODE_INSTR_SWAP__MASK
- A6XX_VFD_DECODE_INSTR_SWAP__SHIFT
- A6XX_VFD_DECODE_INSTR_UNK30
- A6XX_VFD_DEST_CNTL_INSTR_REGID
- A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK
- A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT
- A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK
- A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK
- A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT
- A6XX_VFD_MODE_CNTL_BINNING_PASS
- A6XX_VPC_CNTL_0_NUMNONPOSVAR
- A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK
- A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT
- A6XX_VPC_CNTL_0_VARYING
- A6XX_VPC_PACK_NUMNONPOSVAR
- A6XX_VPC_PACK_NUMNONPOSVAR__MASK
- A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT
- A6XX_VPC_PACK_PSIZELOC
- A6XX_VPC_PACK_PSIZELOC__MASK
- A6XX_VPC_PACK_PSIZELOC__SHIFT
- A6XX_VPC_PACK_STRIDE_IN_VPC
- A6XX_VPC_PACK_STRIDE_IN_VPC__MASK
- A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT
- A6XX_VPC_SO_BUF_CNTL_BUF0
- A6XX_VPC_SO_BUF_CNTL_BUF1
- A6XX_VPC_SO_BUF_CNTL_BUF2
- A6XX_VPC_SO_BUF_CNTL_BUF3
- A6XX_VPC_SO_BUF_CNTL_ENABLE
- A6XX_VPC_SO_CNTL_ENABLE
- A6XX_VPC_SO_OVERRIDE_SO_DISABLE
- A6XX_VPC_SO_PROG_A_BUF
- A6XX_VPC_SO_PROG_A_BUF__MASK
- A6XX_VPC_SO_PROG_A_BUF__SHIFT
- A6XX_VPC_SO_PROG_A_EN
- A6XX_VPC_SO_PROG_A_OFF
- A6XX_VPC_SO_PROG_A_OFF__MASK
- A6XX_VPC_SO_PROG_A_OFF__SHIFT
- A6XX_VPC_SO_PROG_B_BUF
- A6XX_VPC_SO_PROG_B_BUF__MASK
- A6XX_VPC_SO_PROG_B_BUF__SHIFT
- A6XX_VPC_SO_PROG_B_EN
- A6XX_VPC_SO_PROG_B_OFF
- A6XX_VPC_SO_PROG_B_OFF__MASK
- A6XX_VPC_SO_PROG_B_OFF__SHIFT
- A6XX_VSC_BIN_COUNT_NX
- A6XX_VSC_BIN_COUNT_NX__MASK
- A6XX_VSC_BIN_COUNT_NX__SHIFT
- A6XX_VSC_BIN_COUNT_NY
- A6XX_VSC_BIN_COUNT_NY__MASK
- A6XX_VSC_BIN_COUNT_NY__SHIFT
- A6XX_VSC_BIN_SIZE_HEIGHT
- A6XX_VSC_BIN_SIZE_HEIGHT__MASK
- A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT
- A6XX_VSC_BIN_SIZE_WIDTH
- A6XX_VSC_BIN_SIZE_WIDTH__MASK
- A6XX_VSC_BIN_SIZE_WIDTH__SHIFT
- A6XX_VSC_PIPE_CONFIG_REG_H
- A6XX_VSC_PIPE_CONFIG_REG_H__MASK
- A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT
- A6XX_VSC_PIPE_CONFIG_REG_W
- A6XX_VSC_PIPE_CONFIG_REG_W__MASK
- A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT
- A6XX_VSC_PIPE_CONFIG_REG_X
- A6XX_VSC_PIPE_CONFIG_REG_X__MASK
- A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT
- A6XX_VSC_PIPE_CONFIG_REG_Y
- A6XX_VSC_PIPE_CONFIG_REG_Y__MASK
- A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT
- A6XX_VSC_PIPE_DATA2_ARRAY_PITCH
- A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK
- A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT
- A6XX_VSC_PIPE_DATA_ARRAY_PITCH
- A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK
- A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT
- A6XX_XML
- A6_CRY_MD_CIPHER_DECR
- A6_CRY_MD_CIPHER_DSEQ
- A6_CRY_MD_CIPHER_LEN
- A6_CRY_MD_CIPHER_TWEAK
- A6_CRY_MD_HASH_HMAC_FIN
- A6_CRY_MD_HASH_SEL_CTX
- A6_CRY_MD_OPER
- A6_MARK
- A6_PDMA_ACK_INTR
- A6_PDMA_INTR_MASK
- A6_PDMA_INTR_MASK_IN_DATA
- A6_PDMA_INTR_MASK_IN_EOP
- A6_PDMA_INTR_MASK_IN_EOP_FLUSH
- A6_PDMA_IN_BUF_CFG
- A6_PDMA_IN_CFG
- A6_PDMA_IN_CMD
- A6_PDMA_IN_CMD_FLUSH_STAT
- A6_PDMA_IN_CMD_STOP
- A6_PDMA_IN_DESCRQ_PUSH
- A6_PDMA_IN_DESCRQ_STAT
- A6_PDMA_IN_STATQ_PUSH
- A6_PDMA_MASKED_INTR
- A6_PDMA_OUT_CMD_STOP
- A7
- A72_GATE
- A7MODE
- A7_BX_ADDR0
- A7_CLUSTER
- A7_CONF
- A7_CRY_MD_CIPHER_DECR
- A7_CRY_MD_CIPHER_DSEQ
- A7_CRY_MD_CIPHER_LEN
- A7_CRY_MD_CIPHER_TWEAK
- A7_CRY_MD_HASH_HMAC_FIN
- A7_CRY_MD_HASH_SEL_CTX
- A7_CRY_MD_OPER
- A7_MARK
- A7_PDMA_ACK_INTR
- A7_PDMA_INTR_MASK
- A7_PDMA_INTR_MASK_IN_DATA
- A7_PDMA_INTR_MASK_IN_EOP
- A7_PDMA_INTR_MASK_IN_EOP_FLUSH
- A7_PDMA_IN_BUF_CFG
- A7_PDMA_IN_CFG
- A7_PDMA_IN_CMD
- A7_PDMA_IN_CMD_FLUSH_STAT
- A7_PDMA_IN_CMD_STOP
- A7_PDMA_IN_DESCRQ_PUSH
- A7_PDMA_IN_DESCRQ_STAT
- A7_PDMA_IN_STATQ_PUSH
- A7_PDMA_MASKED_INTR
- A7_PDMA_OUT_CMD_STOP
- A7_PERFVAL_BASE
- A7_PWRDN_EN
- A8
- A8293_H
- A84_CLEANUP_CMD
- A84_DIAG_LOGIN_COMPLETE
- A84_GOLD_LOGIN_COMPLETE
- A84_ISSUE_READ_TYPE_CMD
- A84_ISSUE_RESET_DIAG_FW
- A84_ISSUE_RESET_OP_FW
- A84_ISSUE_UPDATE_DIAGFW_CMD
- A84_ISSUE_UPDATE_OPFW_CMD
- A84_ISSUE_WRITE_TYPE_CMD
- A84_OP_LOGIN_COMPLETE
- A84_PANIC_RECOVERY
- A860_DELAY_L
- A8_MARK
- A9
- A9SM_AND_MPMC_BASE
- A9SM_PERIP_BASE
- A9WDOG_AUTO_OFF_DIS
- A9WDOG_AUTO_OFF_EN
- A9WDOG_ID_MASK
- A9_BOOT
- A9_EXTCLK
- A9_MARK
- A9_OFF
- A9_OPPT1
- A9_OPPT2
- A9_SOURCE
- AA
- AA1
- AA11
- AA12
- AA15_1610_UART1_RTS
- AA16
- AA17
- AA17_7XX_USB_DM
- AA19
- AA1_DESC
- AA2
- AA20
- AA20_1610_GPIO_41
- AA20_DESC
- AA21
- AA21_DESC
- AA22
- AA22_DESC
- AA23
- AA24
- AA25
- AA26
- AA2_DESC
- AA3
- AA3_DESC
- AA4
- AA5
- AA6
- AA7
- AA9
- AA9_USB0_VP
- AA9_USB2_VP
- AACI_ALLINTS
- AACI_CSCH1
- AACI_CSCH2
- AACI_CSCH3
- AACI_CSCH4
- AACI_DEV_PM_OPS
- AACI_DR1
- AACI_DR2
- AACI_DR3
- AACI_DR4
- AACI_H
- AACI_IE
- AACI_INTCLR
- AACI_ISR
- AACI_MAINCR
- AACI_MAINFR
- AACI_RESET
- AACI_RXCR
- AACI_SL12RX
- AACI_SL12TX
- AACI_SL1RX
- AACI_SL1TX
- AACI_SL2RX
- AACI_SL2TX
- AACI_SLFR
- AACI_SLIEN
- AACI_SLISTAT
- AACI_SR
- AACI_SYNC
- AACI_TXCR
- AAC_BAT_NOT_SUPPORTED
- AAC_BAT_OPT_NOTPRESENT
- AAC_BAT_OPT_PRESENT
- AAC_BAT_REQ_NOTPRESENT
- AAC_BAT_REQ_PRESENT
- AAC_BIT_STREAM_ADIF
- AAC_BIT_STREAM_ADTS
- AAC_BIT_STREAM_RAW
- AAC_BUS_TARGET_LOOP
- AAC_CHARDEV_NEEDS_REINIT
- AAC_CHARDEV_UNREGISTERED
- AAC_CLEAR_AIF_BIT
- AAC_CLEAR_SYNC_BIT
- AAC_COMM_MESSAGE
- AAC_COMM_MESSAGE_TYPE1
- AAC_COMM_MESSAGE_TYPE2
- AAC_COMM_MESSAGE_TYPE3
- AAC_COMM_PRODUCER
- AAC_CPU_I960
- AAC_CPU_SIMULATOR
- AAC_CPU_STRONGARM
- AAC_DEBUG_INSTRUMENT_AIF_DELETE
- AAC_DEBUG_POSTAMBLE
- AAC_DEBUG_PREAMBLE
- AAC_DEVTYPE_ARC_RAW
- AAC_DEVTYPE_NATIVE_RAW
- AAC_DEVTYPE_RAID_MEMBER
- AAC_DISABLE_INTERRUPT
- AAC_DISABLE_MSIX
- AAC_DRIVERNAME
- AAC_DRIVER_BRANCH
- AAC_DRIVER_BUILD
- AAC_DRIVER_FULL_VERSION
- AAC_DRIVER_VERSION
- AAC_ENABLE_INTERRUPT
- AAC_ENABLE_INTX
- AAC_ENABLE_MSIX
- AAC_EXTOPT_SA_FIRMWARE
- AAC_EXTOPT_SOFT_RESET
- AAC_FEATURE_FALCON
- AAC_FEATURE_JBOD
- AAC_INIT
- AAC_INT_DISABLE_ALL
- AAC_INT_ENABLE_TYPE1_INTX
- AAC_INT_ENABLE_TYPE1_MSIX
- AAC_INT_MODE_AIF
- AAC_INT_MODE_INTX
- AAC_INT_MODE_MSI
- AAC_INT_MODE_MSIX
- AAC_INT_MODE_SYNC
- AAC_MAX_32BIT_SGBCOUNT
- AAC_MAX_BUSES
- AAC_MAX_HOSTPHYSMEMPAGES
- AAC_MAX_HRRQ
- AAC_MAX_LUN
- AAC_MAX_MSIX
- AAC_MAX_NATIVE_SIZE
- AAC_MAX_NATIVE_TARGETS
- AAC_MAX_TARGETS
- AAC_MIN_FOOTPRINT_SIZE
- AAC_MIN_SRCV_BAR0_SIZE
- AAC_MIN_SRCV_BAR1_SIZE
- AAC_MIN_SRC_BAR0_SIZE
- AAC_MIN_SRC_BAR1_SIZE
- AAC_NUM_FIB
- AAC_NUM_IO_FIB
- AAC_NUM_IO_FIB_RKT
- AAC_NUM_MGT_FIB
- AAC_OPTION_DOORBELL_RESET
- AAC_OPTION_IGNORE_RESET
- AAC_OPTION_MU_RESET
- AAC_OPTION_POWER_MANAGEMENT
- AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP
- AAC_OPTION_SUPPORTED_240_VOLUMES
- AAC_OPTION_VARIABLE_BLOCK_SIZE
- AAC_OPT_4GB_WINDOW
- AAC_OPT_64BIT_DATA
- AAC_OPT_ALARM
- AAC_OPT_CLUSTERS
- AAC_OPT_EXTENDED
- AAC_OPT_HOST_TIME_FIB
- AAC_OPT_NATIVE_HBA
- AAC_OPT_NEW_COMM
- AAC_OPT_NEW_COMM_64
- AAC_OPT_NEW_COMM_TYPE1
- AAC_OPT_NEW_COMM_TYPE2
- AAC_OPT_NEW_COMM_TYPE3
- AAC_OPT_NEW_COMM_TYPE4
- AAC_OPT_NONDASD
- AAC_OPT_RAID50
- AAC_OPT_RAID_SCSI_MODE
- AAC_OPT_SCSI_MANAGED
- AAC_OPT_SCSI_UPGRADEABLE
- AAC_OPT_SGMAP_HOST64
- AAC_OPT_SNAPSHOT
- AAC_OPT_SOFT_ERR_REPORT
- AAC_OPT_SUPPLEMENT_ADAPTER_INFO
- AAC_OPT_SUPPORTED_RECONDITION
- AAC_OPT_WRITE_CACHE
- AAC_OWNER_ERROR_HANDLER
- AAC_OWNER_FIRMWARE
- AAC_OWNER_LOWLEVEL
- AAC_OWNER_MIDLEVEL
- AAC_PCI_MSI_ENABLE
- AAC_QUIRK_17SG
- AAC_QUIRK_31BIT
- AAC_QUIRK_34SG
- AAC_QUIRK_MASTER
- AAC_QUIRK_SCSI_32
- AAC_QUIRK_SLAVE
- AAC_QUIRK_SRC
- AAC_RESCAN
- AAC_SAFW_RESCAN_DELAY
- AAC_SENSE_BUFFERSIZE
- AAC_SIS_SLOT_UNKNOWN
- AAC_SIS_VERSION_V3
- AADCPOW
- AADCPOW_AADC_POWD
- AAD_LEN
- AAFS_LOADDATA_ABI
- AAFS_LOADDATA_DATA
- AAFS_LOADDATA_DIR
- AAFS_LOADDATA_HASH
- AAFS_LOADDATA_NDENTS
- AAFS_LOADDATA_REVISION
- AAFS_MAGIC
- AAFS_NAME
- AAFS_NS_COUNT
- AAFS_NS_DIR
- AAFS_NS_LOAD
- AAFS_NS_MAX_COUNT
- AAFS_NS_MAX_SIZE
- AAFS_NS_NS
- AAFS_NS_OWNER
- AAFS_NS_PROFS
- AAFS_NS_RAW_DATA
- AAFS_NS_REMOVE
- AAFS_NS_REPLACE
- AAFS_NS_REVISION
- AAFS_NS_SIZE
- AAFS_NS_SIZEOF
- AAFS_PROF_ATTACH
- AAFS_PROF_DIR
- AAFS_PROF_HASH
- AAFS_PROF_MODE
- AAFS_PROF_NAME
- AAFS_PROF_PROFS
- AAFS_PROF_RAW_ABI
- AAFS_PROF_RAW_DATA
- AAFS_PROF_RAW_HASH
- AAFS_PROF_SIZEOF
- AAGC_CTL
- AAGC_DEF
- AAGC_GAIN
- AAGC_HYST
- AAGC_STATUS
- AAGC_STATUS_REG
- AAI_PROGRAM
- AAL0_RX_BUFFER_SIZE
- AAL0_TX_MULTIPLIER
- AAL5
- AAL5_LEN
- AAL5_PKT_REASSEMBLED
- AAL5_PKT_TERMINATED
- AAL5_RX_MULTIPLIER
- AAL5_TRAILER
- AAL5_TX_MULTIPLIER
- AALG_AE_EN
- AALG_AE_EN_MASK
- AALG_ALL_EN
- AALG_ALL_EN_MASK
- AALG_DIVLEI_EN
- AALG_DIVLEI_EN_MASK
- AALG_FIT_EN
- AALG_FIT_EN_MASK
- AALG_FLICKER_EN
- AALG_FLICKER_EN_MASK
- AALG_USE_WB_FOR_ISP
- AALG_WB_EN
- AALG_WB_EN_MASK
- AALG_WRHW_EN
- AALG_WRHW_EN_MASK
- AAL_EN
- AANAPOW
- AANAPOW_A_POWD
- AAP
- AAP1
- AAP1_MEMMAP
- AAP1_RDUMP
- AARCH32_BREAK_ARM
- AARCH32_BREAK_THUMB
- AARCH32_BREAK_THUMB2_HI
- AARCH32_BREAK_THUMB2_LO
- AARCH32_VECTORS_BASE
- AARCH64_BREAKPOINT_EL0
- AARCH64_BREAKPOINT_EL1
- AARCH64_BREAK_FAULT
- AARCH64_BREAK_KGDB_DYN_DBG
- AARCH64_BREAK_MON
- AARCH64_DBG_READ
- AARCH64_DBG_REG_BCR
- AARCH64_DBG_REG_BVR
- AARCH64_DBG_REG_NAME_BCR
- AARCH64_DBG_REG_NAME_BVR
- AARCH64_DBG_REG_NAME_WCR
- AARCH64_DBG_REG_NAME_WVR
- AARCH64_DBG_REG_WCR
- AARCH64_DBG_REG_WVR
- AARCH64_DBG_WRITE
- AARCH64_ESR_ACCESS_MASK
- AARCH64_INSN_ADR_TYPE_ADR
- AARCH64_INSN_ADR_TYPE_ADRP
- AARCH64_INSN_ADSB_ADD
- AARCH64_INSN_ADSB_ADD_SETFLAGS
- AARCH64_INSN_ADSB_SUB
- AARCH64_INSN_ADSB_SUB_SETFLAGS
- AARCH64_INSN_BITFIELD_MOVE
- AARCH64_INSN_BITFIELD_MOVE_SIGNED
- AARCH64_INSN_BITFIELD_MOVE_UNSIGNED
- AARCH64_INSN_BRANCH_COMP_NONZERO
- AARCH64_INSN_BRANCH_COMP_ZERO
- AARCH64_INSN_BRANCH_LINK
- AARCH64_INSN_BRANCH_NOLINK
- AARCH64_INSN_BRANCH_RETURN
- AARCH64_INSN_CLS_BR_SYS
- AARCH64_INSN_CLS_DP_FPSIMD
- AARCH64_INSN_CLS_DP_IMM
- AARCH64_INSN_CLS_DP_REG
- AARCH64_INSN_CLS_LDST
- AARCH64_INSN_CLS_UNKNOWN
- AARCH64_INSN_COND_AL
- AARCH64_INSN_COND_CC
- AARCH64_INSN_COND_CS
- AARCH64_INSN_COND_EQ
- AARCH64_INSN_COND_GE
- AARCH64_INSN_COND_GT
- AARCH64_INSN_COND_HI
- AARCH64_INSN_COND_LE
- AARCH64_INSN_COND_LS
- AARCH64_INSN_COND_LT
- AARCH64_INSN_COND_MI
- AARCH64_INSN_COND_NE
- AARCH64_INSN_COND_PL
- AARCH64_INSN_COND_VC
- AARCH64_INSN_COND_VS
- AARCH64_INSN_DATA1_REVERSE_16
- AARCH64_INSN_DATA1_REVERSE_32
- AARCH64_INSN_DATA1_REVERSE_64
- AARCH64_INSN_DATA2_ASRV
- AARCH64_INSN_DATA2_LSLV
- AARCH64_INSN_DATA2_LSRV
- AARCH64_INSN_DATA2_RORV
- AARCH64_INSN_DATA2_SDIV
- AARCH64_INSN_DATA2_UDIV
- AARCH64_INSN_DATA3_MADD
- AARCH64_INSN_DATA3_MSUB
- AARCH64_INSN_HINT_NOP
- AARCH64_INSN_HINT_SEV
- AARCH64_INSN_HINT_SEVL
- AARCH64_INSN_HINT_WFE
- AARCH64_INSN_HINT_WFI
- AARCH64_INSN_HINT_YIELD
- AARCH64_INSN_IMM_12
- AARCH64_INSN_IMM_14
- AARCH64_INSN_IMM_16
- AARCH64_INSN_IMM_19
- AARCH64_INSN_IMM_26
- AARCH64_INSN_IMM_6
- AARCH64_INSN_IMM_7
- AARCH64_INSN_IMM_9
- AARCH64_INSN_IMM_ADR
- AARCH64_INSN_IMM_MAX
- AARCH64_INSN_IMM_MOVKZ
- AARCH64_INSN_IMM_MOVNZ
- AARCH64_INSN_IMM_N
- AARCH64_INSN_IMM_R
- AARCH64_INSN_IMM_S
- AARCH64_INSN_LDST_LOAD_EX
- AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX
- AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX
- AARCH64_INSN_LDST_LOAD_REG_OFFSET
- AARCH64_INSN_LDST_STORE_EX
- AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX
- AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX
- AARCH64_INSN_LDST_STORE_REG_OFFSET
- AARCH64_INSN_LOGIC_AND
- AARCH64_INSN_LOGIC_AND_SETFLAGS
- AARCH64_INSN_LOGIC_BIC
- AARCH64_INSN_LOGIC_BIC_SETFLAGS
- AARCH64_INSN_LOGIC_EON
- AARCH64_INSN_LOGIC_EOR
- AARCH64_INSN_LOGIC_ORN
- AARCH64_INSN_LOGIC_ORR
- AARCH64_INSN_LSL_12
- AARCH64_INSN_MOVEWIDE_INVERSE
- AARCH64_INSN_MOVEWIDE_KEEP
- AARCH64_INSN_MOVEWIDE_ZERO
- AARCH64_INSN_N_BIT
- AARCH64_INSN_PRFM_POLICY_KEEP
- AARCH64_INSN_PRFM_POLICY_STRM
- AARCH64_INSN_PRFM_TARGET_L1
- AARCH64_INSN_PRFM_TARGET_L2
- AARCH64_INSN_PRFM_TARGET_L3
- AARCH64_INSN_PRFM_TYPE_PLD
- AARCH64_INSN_PRFM_TYPE_PLI
- AARCH64_INSN_PRFM_TYPE_PST
- AARCH64_INSN_REGTYPE_RA
- AARCH64_INSN_REGTYPE_RD
- AARCH64_INSN_REGTYPE_RM
- AARCH64_INSN_REGTYPE_RN
- AARCH64_INSN_REGTYPE_RS
- AARCH64_INSN_REGTYPE_RT
- AARCH64_INSN_REGTYPE_RT2
- AARCH64_INSN_REG_0
- AARCH64_INSN_REG_1
- AARCH64_INSN_REG_10
- AARCH64_INSN_REG_11
- AARCH64_INSN_REG_12
- AARCH64_INSN_REG_13
- AARCH64_INSN_REG_14
- AARCH64_INSN_REG_15
- AARCH64_INSN_REG_16
- AARCH64_INSN_REG_17
- AARCH64_INSN_REG_18
- AARCH64_INSN_REG_19
- AARCH64_INSN_REG_2
- AARCH64_INSN_REG_20
- AARCH64_INSN_REG_21
- AARCH64_INSN_REG_22
- AARCH64_INSN_REG_23
- AARCH64_INSN_REG_24
- AARCH64_INSN_REG_25
- AARCH64_INSN_REG_26
- AARCH64_INSN_REG_27
- AARCH64_INSN_REG_28
- AARCH64_INSN_REG_29
- AARCH64_INSN_REG_3
- AARCH64_INSN_REG_30
- AARCH64_INSN_REG_4
- AARCH64_INSN_REG_5
- AARCH64_INSN_REG_6
- AARCH64_INSN_REG_7
- AARCH64_INSN_REG_8
- AARCH64_INSN_REG_9
- AARCH64_INSN_REG_FP
- AARCH64_INSN_REG_LR
- AARCH64_INSN_REG_SP
- AARCH64_INSN_REG_ZR
- AARCH64_INSN_SF_BIT
- AARCH64_INSN_SIZE
- AARCH64_INSN_SIZE_16
- AARCH64_INSN_SIZE_32
- AARCH64_INSN_SIZE_64
- AARCH64_INSN_SIZE_8
- AARCH64_INSN_SPCLREG_CURRENTEL
- AARCH64_INSN_SPCLREG_DAIF
- AARCH64_INSN_SPCLREG_DLR_EL0
- AARCH64_INSN_SPCLREG_DSPSR_EL0
- AARCH64_INSN_SPCLREG_ELR_EL1
- AARCH64_INSN_SPCLREG_ELR_EL2
- AARCH64_INSN_SPCLREG_ELR_EL3
- AARCH64_INSN_SPCLREG_FPCR
- AARCH64_INSN_SPCLREG_NZCV
- AARCH64_INSN_SPCLREG_SPSEL
- AARCH64_INSN_SPCLREG_SPSR_ABT
- AARCH64_INSN_SPCLREG_SPSR_EL1
- AARCH64_INSN_SPCLREG_SPSR_EL2
- AARCH64_INSN_SPCLREG_SPSR_EL3
- AARCH64_INSN_SPCLREG_SPSR_FIQ
- AARCH64_INSN_SPCLREG_SPSR_INQ
- AARCH64_INSN_SPCLREG_SPSR_UND
- AARCH64_INSN_SPCLREG_SP_EL0
- AARCH64_INSN_SPCLREG_SP_EL1
- AARCH64_INSN_SPCLREG_SP_EL2
- AARCH64_INSN_VARIANT_32BIT
- AARCH64_INSN_VARIANT_64BIT
- AARP_EXPIRY_TIME
- AARP_HASH_SIZE
- AARP_HW_TYPE_ETHERNET
- AARP_HW_TYPE_TOKENRING
- AARP_PA_ALEN
- AARP_PROBE
- AARP_REPLY
- AARP_REQUEST
- AARP_RESOLVE_TIME
- AARP_RETRANSMIT_LIMIT
- AARP_TICK_TIME
- AAT1290_EN_SET_TICK_TIME_US
- AAT1290_FLASH_SAFETY_TIMER_ADDR
- AAT1290_FLASH_TM_NUM_LEVELS
- AAT1290_FLEN_OFF_DELAY_TIME_US
- AAT1290_LATCH_TIME_MAX_US
- AAT1290_LATCH_TIME_MIN_US
- AAT1290_MAX_MM_CURRENT
- AAT1290_MAX_MM_CURR_PERCENT_0
- AAT1290_MAX_MM_CURR_PERCENT_100
- AAT1290_MM_CURRENT_RATIO_ADDR
- AAT1290_MM_CURRENT_SCALE_SIZE
- AAT1290_MM_TO_FL_1_92
- AAT1290_MM_TO_FL_RATIO
- AAT1290_MOVIE_MODE_CONFIG_ADDR
- AAT1290_MOVIE_MODE_CURRENT_ADDR
- AAT1290_MOVIE_MODE_OFF
- AAT1290_MOVIE_MODE_ON
- AAT1290_NAME
- AAT2870_ALS0
- AAT2870_ALS1
- AAT2870_ALS2
- AAT2870_ALS3
- AAT2870_ALS4
- AAT2870_ALS5
- AAT2870_ALS6
- AAT2870_ALS7
- AAT2870_ALS8
- AAT2870_ALS9
- AAT2870_ALSA
- AAT2870_ALSB
- AAT2870_ALSC
- AAT2870_ALSD
- AAT2870_ALSE
- AAT2870_ALSF
- AAT2870_ALS_CFG0
- AAT2870_ALS_CFG1
- AAT2870_ALS_CFG2
- AAT2870_AMB
- AAT2870_BL1
- AAT2870_BL2
- AAT2870_BL3
- AAT2870_BL4
- AAT2870_BL5
- AAT2870_BL6
- AAT2870_BL7
- AAT2870_BL8
- AAT2870_BLM
- AAT2870_BLS
- AAT2870_BL_CH1
- AAT2870_BL_CH2
- AAT2870_BL_CH3
- AAT2870_BL_CH4
- AAT2870_BL_CH5
- AAT2870_BL_CH6
- AAT2870_BL_CH7
- AAT2870_BL_CH8
- AAT2870_BL_CH_ALL
- AAT2870_BL_CH_EN
- AAT2870_CURRENT_0_45
- AAT2870_CURRENT_0_90
- AAT2870_CURRENT_10_8
- AAT2870_CURRENT_11_7
- AAT2870_CURRENT_12_6
- AAT2870_CURRENT_13_5
- AAT2870_CURRENT_14_4
- AAT2870_CURRENT_15_3
- AAT2870_CURRENT_16_2
- AAT2870_CURRENT_17_1
- AAT2870_CURRENT_18_0
- AAT2870_CURRENT_18_9
- AAT2870_CURRENT_19_8
- AAT2870_CURRENT_1_80
- AAT2870_CURRENT_20_7
- AAT2870_CURRENT_21_6
- AAT2870_CURRENT_22_5
- AAT2870_CURRENT_23_4
- AAT2870_CURRENT_24_3
- AAT2870_CURRENT_25_2
- AAT2870_CURRENT_26_1
- AAT2870_CURRENT_27_0
- AAT2870_CURRENT_27_9
- AAT2870_CURRENT_2_70
- AAT2870_CURRENT_3_60
- AAT2870_CURRENT_4_50
- AAT2870_CURRENT_5_40
- AAT2870_CURRENT_6_30
- AAT2870_CURRENT_7_20
- AAT2870_CURRENT_8_10
- AAT2870_CURRENT_9_00
- AAT2870_CURRENT_9_90
- AAT2870_FLR
- AAT2870_FM
- AAT2870_FS
- AAT2870_ID_BL
- AAT2870_ID_LDOA
- AAT2870_ID_LDOB
- AAT2870_ID_LDOC
- AAT2870_ID_LDOD
- AAT2870_LDO
- AAT2870_LDO_AB
- AAT2870_LDO_CD
- AAT2870_LDO_EN
- AAT2870_REG_NUM
- AAT2870_SUB_CTRL
- AAT2870_SUB_SET
- AAU_ABCR
- AAU_ACR
- AAU_ADAR
- AAU_ADCR
- AAU_ANDAR
- AAU_ASR
- AAU_DAR
- AAU_EDCR0_IDX
- AAU_EDCR1_IDX
- AAU_EDCR2_IDX
- AAU_ID
- AAU_SAR
- AAU_SAR_EDCR
- AA_ARRAY
- AA_ARRAYEND
- AA_AUDIT_DATA
- AA_AUDIT_FILE_MASK
- AA_BLOB
- AA_BUG
- AA_BUG_FMT
- AA_BUG_PREEMPT_ENABLED
- AA_CHANGE_CHILD
- AA_CHANGE_NOFLAGS
- AA_CHANGE_ONEXEC
- AA_CHANGE_STACK
- AA_CHANGE_TEST
- AA_CLASS_CAP
- AA_CLASS_DEPRECATED
- AA_CLASS_DOMAIN
- AA_CLASS_ENTRY
- AA_CLASS_FILE
- AA_CLASS_LABEL
- AA_CLASS_LAST
- AA_CLASS_MOUNT
- AA_CLASS_NET
- AA_CLASS_PTRACE
- AA_CLASS_RLIMITS
- AA_CLASS_SIGNAL
- AA_CLASS_UNKNOWN
- AA_CONT_MATCH
- AA_DEBUG
- AA_ERROR
- AA_EXEC_MMAP
- AA_FIRST_SECID
- AA_LINK_SUBSET
- AA_LIST
- AA_LISTEND
- AA_MAY_ACCEPT
- AA_MAY_APPEND
- AA_MAY_BE_READ
- AA_MAY_BE_TRACED
- AA_MAY_BIND
- AA_MAY_CHANGEHAT
- AA_MAY_CHANGE_PROFILE
- AA_MAY_CHGRP
- AA_MAY_CHMOD
- AA_MAY_CHOWN
- AA_MAY_CONNECT
- AA_MAY_CREATE
- AA_MAY_DELEGATE
- AA_MAY_DELETE
- AA_MAY_EXEC
- AA_MAY_GETATTR
- AA_MAY_GETCRED
- AA_MAY_GETOPT
- AA_MAY_LINK
- AA_MAY_LISTEN
- AA_MAY_LOAD_POLICY
- AA_MAY_LOCK
- AA_MAY_MOUNT
- AA_MAY_MPROT
- AA_MAY_ONEXEC
- AA_MAY_OPEN
- AA_MAY_PIVOTROOT
- AA_MAY_READ
- AA_MAY_RECEIVE
- AA_MAY_REMOVE_POLICY
- AA_MAY_RENAME
- AA_MAY_REPLACE_POLICY
- AA_MAY_SEND
- AA_MAY_SETATTR
- AA_MAY_SETCRED
- AA_MAY_SETOPT
- AA_MAY_SHUTDOWN
- AA_MAY_SNAPSHOT
- AA_MAY_STACK
- AA_MAY_UMOUNT
- AA_MAY_WRITE
- AA_MNT_CONT_MATCH
- AA_MS_IGNORE_MASK
- AA_NAME
- AA_PTRACE_PERM_MASK
- AA_PTRACE_READ
- AA_PTRACE_TRACE
- AA_SECID_INVALID
- AA_SECID_WILDCARD
- AA_SFS_DIR
- AA_SFS_FILE_BOOLEAN
- AA_SFS_FILE_FOPS
- AA_SFS_FILE_STRING
- AA_SFS_FILE_U64
- AA_SFS_SIG_MASK
- AA_SFS_TYPE_BOOLEAN
- AA_SFS_TYPE_DIR
- AA_SFS_TYPE_FOPS
- AA_SFS_TYPE_STRING
- AA_SFS_TYPE_U64
- AA_SIGNAL_PERM_MASK
- AA_STRING
- AA_STRUCT
- AA_STRUCTEND
- AA_TEXT
- AA_U16
- AA_U32
- AA_U64
- AA_U8
- AA_WARN
- AA_X_CHILD
- AA_X_INDEX_MASK
- AA_X_INHERIT
- AA_X_NAME
- AA_X_NONE
- AA_X_TABLE
- AA_X_TYPE_MASK
- AA_X_TYPE_SHIFT
- AA_X_UNCONFINED
- AA_X_UNSAFE
- AB
- AB0801
- AB0803
- AB0804
- AB0805
- AB1
- AB10
- AB11
- AB12
- AB15
- AB16
- AB17
- AB18
- AB1801
- AB1803
- AB1804
- AB1805
- AB19
- AB1_DESC
- AB2
- AB20
- AB20_DESC
- AB21
- AB21_DESC
- AB22
- AB23
- AB24
- AB25
- AB26
- AB2_DESC
- AB3
- AB3100_AL0
- AB3100_AL1
- AB3100_AL2
- AB3100_AL3
- AB3100_BUCK
- AB3100_BUCK_SLEEP
- AB3100_CID
- AB3100_D0C
- AB3100_D1C
- AB3100_D2C
- AB3100_D3C
- AB3100_DIS
- AB3100_EVENTA1
- AB3100_EVENTA1_DCIO
- AB3100_EVENTA1_ONSWA
- AB3100_EVENTA1_ONSWB
- AB3100_EVENTA1_ONSWC
- AB3100_EVENTA1_OVER_TEMP
- AB3100_EVENTA1_SIM_OFF
- AB3100_EVENTA1_VBUS
- AB3100_EVENTA1_VSET_USB
- AB3100_EVENTA2
- AB3100_EVENTA2_ALARM
- AB3100_EVENTA2_BATTERY_REM
- AB3100_EVENTA2_CHARG_OVERCURRENT
- AB3100_EVENTA2_FRAMING_ERROR
- AB3100_EVENTA2_MIDR
- AB3100_EVENTA2_OVERRUN_ERROR
- AB3100_EVENTA2_READY_RX
- AB3100_EVENTA2_READY_TX
- AB3100_EVENTA3
- AB3100_EVENTA3_ADC_TRIG0
- AB3100_EVENTA3_ADC_TRIG1
- AB3100_EVENTA3_ADC_TRIG2
- AB3100_EVENTA3_ADC_TRIG3
- AB3100_EVENTA3_ADC_TRIG4
- AB3100_EVENTA3_ADC_TRIG5
- AB3100_EVENTA3_ADC_TRIGVBAT
- AB3100_EVENTA3_ADC_TRIGVTX
- AB3100_IMRA1
- AB3100_IMRA2
- AB3100_IMRA3
- AB3100_IMRB1
- AB3100_IMRB2
- AB3100_IMRB3
- AB3100_LDO_A
- AB3100_LDO_C
- AB3100_LDO_D
- AB3100_LDO_E
- AB3100_LDO_EXT
- AB3100_LDO_E_SLEEP
- AB3100_LDO_F
- AB3100_LDO_G
- AB3100_LDO_H
- AB3100_LDO_H_SLEEP_EN
- AB3100_LDO_H_SLEEP_MODE
- AB3100_LDO_H_VSEL_AC
- AB3100_LDO_K
- AB3100_LDO_ON
- AB3100_MCA
- AB3100_MCB
- AB3100_NUM_REGULATORS
- AB3100_OTP0
- AB3100_OTP1
- AB3100_OTP2
- AB3100_OTP3
- AB3100_OTP4
- AB3100_OTP5
- AB3100_OTP6
- AB3100_OTP7
- AB3100_OTPP
- AB3100_P1A
- AB3100_P1B
- AB3100_P1C
- AB3100_P1D
- AB3100_P1E
- AB3100_P1F
- AB3100_P1G
- AB3100_R2A
- AB3100_R2B
- AB3100_REG_ON_MASK
- AB3100_RTC
- AB3100_RTC_CLOCK_RATE
- AB3100_STR_BATT_REMOVAL
- AB3100_STR_BOOT_MODE
- AB3100_STR_DCIO
- AB3100_STR_ONSWA
- AB3100_STR_ONSWB
- AB3100_STR_ONSWC
- AB3100_STR_SIM_OFF
- AB3100_STR_VBUS
- AB3100_SUP
- AB3100_TI0
- AB3100_TI1
- AB3100_TI2
- AB3100_TI3
- AB3100_TI4
- AB3100_TI5
- AB4
- AB5
- AB6
- AB7
- AB8
- AB8500_ADC_NAME_STRING
- AB8500_ADDIGGAIN1
- AB8500_ADDIGGAIN2
- AB8500_ADDIGGAIN3
- AB8500_ADDIGGAIN4
- AB8500_ADDIGGAIN5
- AB8500_ADDIGGAIN6
- AB8500_ADDIGGAINX_ADXGAIN_MAX
- AB8500_ADDIGGAINX_FADEDISADX
- AB8500_ADDIGLOOPGAIN1
- AB8500_ADDIGLOOPGAIN2
- AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX
- AB8500_ADDIGLOOPGAINX_FADEDISADXL
- AB8500_ADFILTCONF
- AB8500_ADFILTCONF_AD1NH
- AB8500_ADFILTCONF_AD1VOICE
- AB8500_ADFILTCONF_AD2NH
- AB8500_ADFILTCONF_AD2VOICE
- AB8500_ADFILTCONF_AD3NH
- AB8500_ADFILTCONF_AD3VOICE
- AB8500_ADFILTCONF_AD4NH
- AB8500_ADFILTCONF_AD4VOICE
- AB8500_ADPATHENA
- AB8500_ADPATHENA_ENAD12
- AB8500_ADPATHENA_ENAD34
- AB8500_ADPATHENA_ENAD5768
- AB8500_ADSLOTHIZCTRL1
- AB8500_ADSLOTHIZCTRL2
- AB8500_ADSLOTHIZCTRL3
- AB8500_ADSLOTHIZCTRL4
- AB8500_ADSLOTSEL
- AB8500_ADSLOTSEL1
- AB8500_ADSLOTSEL10
- AB8500_ADSLOTSEL11
- AB8500_ADSLOTSEL12
- AB8500_ADSLOTSEL13
- AB8500_ADSLOTSEL14
- AB8500_ADSLOTSEL15
- AB8500_ADSLOTSEL16
- AB8500_ADSLOTSEL2
- AB8500_ADSLOTSEL3
- AB8500_ADSLOTSEL4
- AB8500_ADSLOTSEL5
- AB8500_ADSLOTSEL6
- AB8500_ADSLOTSEL7
- AB8500_ADSLOTSEL8
- AB8500_ADSLOTSEL9
- AB8500_ADSLOTSELX_AD_OUT_TO_SLOT
- AB8500_ADSLOTSELX_EVEN_SHIFT
- AB8500_ADSLOTSELX_ODD_SHIFT
- AB8500_AD_DATA0_OFFSET
- AB8500_AD_DATA1_OFFSET
- AB8500_AD_OUT1
- AB8500_AD_OUT2
- AB8500_AD_OUT3
- AB8500_AD_OUT4
- AB8500_AD_OUT5
- AB8500_AD_OUT6
- AB8500_AD_OUT7
- AB8500_AD_OUT8
- AB8500_ALARM_MIN_LOW
- AB8500_ALARM_MIN_MID
- AB8500_ANACONF1
- AB8500_ANACONF1_DACLOWPOW0
- AB8500_ANACONF1_DACLOWPOW1
- AB8500_ANACONF1_EARDACLOWPOW
- AB8500_ANACONF1_EARDRVLOWPOW
- AB8500_ANACONF1_EARSELCM
- AB8500_ANACONF1_HSHPEN
- AB8500_ANACONF1_HSLOWPOW
- AB8500_ANACONF2
- AB8500_ANACONF2_ENLINL
- AB8500_ANACONF2_ENLINR
- AB8500_ANACONF2_ENMIC1
- AB8500_ANACONF2_ENMIC2
- AB8500_ANACONF2_MUTLINL
- AB8500_ANACONF2_MUTLINR
- AB8500_ANACONF2_MUTMIC1
- AB8500_ANACONF2_MUTMIC2
- AB8500_ANACONF3
- AB8500_ANACONF3_ENADCLINL
- AB8500_ANACONF3_ENADCLINR
- AB8500_ANACONF3_ENADCMIC
- AB8500_ANACONF3_ENDRVHSL
- AB8500_ANACONF3_ENDRVHSR
- AB8500_ANACONF3_LINRSEL
- AB8500_ANACONF3_MIC1SEL
- AB8500_ANACONF4
- AB8500_ANACONF4_DISPDVSS
- AB8500_ANACONF4_ENEAR
- AB8500_ANACONF4_ENHFL
- AB8500_ANACONF4_ENHFR
- AB8500_ANACONF4_ENHSL
- AB8500_ANACONF4_ENHSR
- AB8500_ANACONF4_ENVIB1
- AB8500_ANACONF4_ENVIB2
- AB8500_ANACONF5
- AB8500_ANACONF5_ENCPHS
- AB8500_ANACONF5_ENLOL
- AB8500_ANACONF5_ENLOR
- AB8500_ANACONF5_HSAUTOEN
- AB8500_ANACONF5_HSLDACTOLOL
- AB8500_ANACONF5_HSRDACTOLOR
- AB8500_ANAGAIN1
- AB8500_ANAGAIN2
- AB8500_ANAGAIN3
- AB8500_ANAGAIN3_HSLGAIN
- AB8500_ANAGAIN3_HSRGAIN
- AB8500_ANAGAIN3_HSXGAIN_MAX
- AB8500_ANAGAIN4
- AB8500_ANAGAIN4_LINLGAIN
- AB8500_ANAGAIN4_LINRGAIN
- AB8500_ANAGAIN4_LINXGAIN_MAX
- AB8500_ANAGAINX_ENSEMICX
- AB8500_ANAGAINX_LOWPOWMICX
- AB8500_ANAGAINX_MICXGAIN
- AB8500_ANAGAINX_MICXGAIN_MAX
- AB8500_ANCCONF1
- AB8500_ANCCONF10
- AB8500_ANCCONF11
- AB8500_ANCCONF12
- AB8500_ANCCONF13
- AB8500_ANCCONF14
- AB8500_ANCCONF1_ANCFIRUPDATE
- AB8500_ANCCONF1_ANCIIRINIT
- AB8500_ANCCONF1_ANCIIRUPDATE
- AB8500_ANCCONF1_ENANC
- AB8500_ANCCONF2
- AB8500_ANCCONF2_MAX
- AB8500_ANCCONF2_MIN
- AB8500_ANCCONF2_SHIFT
- AB8500_ANCCONF3
- AB8500_ANCCONF3_MAX
- AB8500_ANCCONF3_MIN
- AB8500_ANCCONF3_SHIFT
- AB8500_ANCCONF4
- AB8500_ANCCONF4_MAX
- AB8500_ANCCONF4_MIN
- AB8500_ANCCONF4_SHIFT
- AB8500_ANCCONF5
- AB8500_ANCCONF6
- AB8500_ANCCONF7
- AB8500_ANCCONF8
- AB8500_ANCCONF9
- AB8500_ANC_FIR_COEFFS
- AB8500_ANC_FIR_COEFF_MAX
- AB8500_ANC_FIR_COEFF_MIN
- AB8500_ANC_IIR_COEFFS
- AB8500_ANC_IIR_COEFF_MAX
- AB8500_ANC_IIR_COEFF_MIN
- AB8500_ANC_SM_DELAY
- AB8500_ANC_WARP_DELAY_MAX
- AB8500_ANC_WARP_DELAY_MIN
- AB8500_ANC_WARP_DELAY_SHIFT
- AB8500_AUDINTMASK1
- AB8500_AUDINTMASK2
- AB8500_AUDINTSOURCE1
- AB8500_AUDINTSOURCE2
- AB8500_AUDIO
- AB8500_AUDREV
- AB8500_AUDSWRESET
- AB8500_AUDSWRESET_SWRESET
- AB8500_BANK12_ACCESS
- AB8500_BATTOK
- AB8500_BATTOK_BATTOKSEL0THF_MASK
- AB8500_BATTOK_BATTOKSEL0THF_SHIFT
- AB8500_BATTOK_BATTOKSEL1THF_MASK
- AB8500_BATTOK_BATTOKSEL1THF_SHIFT
- AB8500_BATT_OK_REG
- AB8500_BATT_OVV
- AB8500_BAT_CTRL_CURRENT_SOURCE
- AB8500_BIT_OTG_STAT_ID
- AB8500_BIT_PHY_CTRL_DEVICE_EN
- AB8500_BIT_PHY_CTRL_HOST_EN
- AB8500_BIT_SOURCE2_VBUSDET
- AB8500_BIT_WD_CTRL_ENABLE
- AB8500_BIT_WD_CTRL_KICK
- AB8500_BM_USB_STATE_CONFIGURED
- AB8500_BM_USB_STATE_MAX
- AB8500_BM_USB_STATE_RESET_FS
- AB8500_BM_USB_STATE_RESET_HS
- AB8500_BM_USB_STATE_RESUME
- AB8500_BM_USB_STATE_SUSPEND
- AB8500_BTEMP_HIGH_TH
- AB8500_CACHEREGNUM
- AB8500_CHARGER
- AB8500_CHARGER_CTRL
- AB8500_CHARG_WD_CTRL
- AB8500_CH_OPT_CRNTLVL_MAX_REG
- AB8500_CH_OPT_CRNTLVL_REG
- AB8500_CH_STATUS1_REG
- AB8500_CH_STATUS2_REG
- AB8500_CH_STAT_REG
- AB8500_CH_USBCH_STAT1_REG
- AB8500_CH_USBCH_STAT2_REG
- AB8500_CH_VOLT_LVL_MAX_REG
- AB8500_CH_VOLT_LVL_REG
- AB8500_CH_WD_REG
- AB8500_CH_WD_TIMER_REG
- AB8500_CLASSDCONF1
- AB8500_CLASSDCONF1_HFLSWAPEN
- AB8500_CLASSDCONF1_HFRSWAPEN
- AB8500_CLASSDCONF1_PARLHF
- AB8500_CLASSDCONF1_PARLVIB
- AB8500_CLASSDCONF1_VIB1SWAPEN
- AB8500_CLASSDCONF1_VIB2SWAPEN
- AB8500_CLASSDCONF2
- AB8500_CLASSDCONF2_FIRBYP0
- AB8500_CLASSDCONF2_FIRBYP1
- AB8500_CLASSDCONF2_FIRBYP2
- AB8500_CLASSDCONF2_FIRBYP3
- AB8500_CLASSDCONF2_HIGHVOLEN0
- AB8500_CLASSDCONF2_HIGHVOLEN1
- AB8500_CLASSDCONF2_HIGHVOLEN2
- AB8500_CLASSDCONF2_HIGHVOLEN3
- AB8500_CLASSDCONF3
- AB8500_CLASSDCONF3_DITHHPGAIN
- AB8500_CLASSDCONF3_DITHHPGAIN_MAX
- AB8500_CLASSDCONF3_DITHWGAIN
- AB8500_CLASSDCONF3_DITHWGAIN_MAX
- AB8500_CODEC_REGISTERS_H
- AB8500_CORE_CODEC_H
- AB8500_CUT1P0
- AB8500_CUT1P1
- AB8500_CUT1P2
- AB8500_CUT2P0
- AB8500_CUT3P0
- AB8500_CUT3P3
- AB8500_CUTEARLY
- AB8500_DADIGGAIN1
- AB8500_DADIGGAIN2
- AB8500_DADIGGAIN3
- AB8500_DADIGGAIN4
- AB8500_DADIGGAIN5
- AB8500_DADIGGAIN6
- AB8500_DADIGGAINX_DAXGAIN_MAX
- AB8500_DADIGGAINX_FADEDISDAX
- AB8500_DAPATHCONF
- AB8500_DAPATHCONF_ENDACEAR
- AB8500_DAPATHCONF_ENDACHFL
- AB8500_DAPATHCONF_ENDACHFR
- AB8500_DAPATHCONF_ENDACHSL
- AB8500_DAPATHCONF_ENDACHSR
- AB8500_DAPATHCONF_ENDACVIB1
- AB8500_DAPATHCONF_ENDACVIB2
- AB8500_DAPATHENA
- AB8500_DAPATHENA_ENDA1
- AB8500_DAPATHENA_ENDA2
- AB8500_DAPATHENA_ENDA3
- AB8500_DAPATHENA_ENDA4
- AB8500_DAPATHENA_ENDA5
- AB8500_DAPATHENA_ENDA6
- AB8500_DASLOTCONF1
- AB8500_DASLOTCONF1_DA12VOICE
- AB8500_DASLOTCONF1_DAI7TOADO1
- AB8500_DASLOTCONF1_SWAPDA12_34
- AB8500_DASLOTCONF2
- AB8500_DASLOTCONF2_DAI8TOADO2
- AB8500_DASLOTCONF3
- AB8500_DASLOTCONF3_DA34VOICE
- AB8500_DASLOTCONF3_DAI7TOADO3
- AB8500_DASLOTCONF4
- AB8500_DASLOTCONF4_DAI8TOADO4
- AB8500_DASLOTCONF5
- AB8500_DASLOTCONF5_DA56VOICE
- AB8500_DASLOTCONF5_DAI7TOADO5
- AB8500_DASLOTCONF6
- AB8500_DASLOTCONF6_DAI8TOADO6
- AB8500_DASLOTCONF7
- AB8500_DASLOTCONF7_DAI8TOADO7
- AB8500_DASLOTCONF8
- AB8500_DASLOTCONF8_DAI7TOADO8
- AB8500_DASLOTCONFX_SLTODAX_MASK
- AB8500_DASLOTCONFX_SLTODAX_SHIFT
- AB8500_DA_DATA0_OFFSET
- AB8500_DA_DATA1_OFFSET
- AB8500_DBI
- AB8500_DEBUG
- AB8500_DEBUG_FIELD_LAST
- AB8500_DEVELOPMENT
- AB8500_DIGIFCONF1
- AB8500_DIGIFCONF1_ENFSBITCLK0
- AB8500_DIGIFCONF1_ENFSBITCLK1
- AB8500_DIGIFCONF1_ENMASTGEN
- AB8500_DIGIFCONF1_IF0BITCLKOS0
- AB8500_DIGIFCONF1_IF0BITCLKOS1
- AB8500_DIGIFCONF1_IF1BITCLKOS0
- AB8500_DIGIFCONF1_IF1BITCLKOS1
- AB8500_DIGIFCONF2
- AB8500_DIGIFCONF2_BITCLK0P
- AB8500_DIGIFCONF2_FSYNC0P
- AB8500_DIGIFCONF2_IF0DEL
- AB8500_DIGIFCONF2_IF0FORMAT0
- AB8500_DIGIFCONF2_IF0FORMAT1
- AB8500_DIGIFCONF2_IF0WL0
- AB8500_DIGIFCONF2_IF0WL1
- AB8500_DIGIFCONF3
- AB8500_DIGIFCONF3_IF0BFIFOEN
- AB8500_DIGIFCONF3_IF0CLKTOIF1CLK
- AB8500_DIGIFCONF3_IF0DATOIF1AD
- AB8500_DIGIFCONF3_IF0MASTER
- AB8500_DIGIFCONF3_IF1CLKTOIF0CLK
- AB8500_DIGIFCONF3_IF1DATOIF0AD
- AB8500_DIGIFCONF3_IF1MASTER
- AB8500_DIGIFCONF4
- AB8500_DIGIFCONF4_BITCLK1P
- AB8500_DIGIFCONF4_FSYNC1P
- AB8500_DIGIFCONF4_IF1DEL
- AB8500_DIGIFCONF4_IF1FORMAT0
- AB8500_DIGIFCONF4_IF1FORMAT1
- AB8500_DIGIFCONF4_IF1WL0
- AB8500_DIGIFCONF4_IF1WL1
- AB8500_DIGLINHSLGAIN
- AB8500_DIGLINHSRGAIN
- AB8500_DIGLINHSXGAIN_LINTOHSXGAIN
- AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX
- AB8500_DIGMICCONF
- AB8500_DIGMICCONF_ENDMIC1
- AB8500_DIGMICCONF_ENDMIC2
- AB8500_DIGMICCONF_ENDMIC3
- AB8500_DIGMICCONF_ENDMIC4
- AB8500_DIGMICCONF_ENDMIC5
- AB8500_DIGMICCONF_ENDMIC6
- AB8500_DIGMICCONF_HSFADSPEED
- AB8500_DIGMULTCONF1
- AB8500_DIGMULTCONF1_AD1SEL
- AB8500_DIGMULTCONF1_AD2SEL
- AB8500_DIGMULTCONF1_AD3SEL
- AB8500_DIGMULTCONF1_AD5SEL
- AB8500_DIGMULTCONF1_AD6SEL
- AB8500_DIGMULTCONF1_ANCSEL
- AB8500_DIGMULTCONF1_DATOHSLEN
- AB8500_DIGMULTCONF1_DATOHSREN
- AB8500_DIGMULTCONF2
- AB8500_DIGMULTCONF2_DATOHFLEN
- AB8500_DIGMULTCONF2_DATOHFREN
- AB8500_DIGMULTCONF2_FIRSID1SEL
- AB8500_DIGMULTCONF2_FIRSID2SEL
- AB8500_DIGMULTCONF2_HFLSEL
- AB8500_DIGMULTCONF2_HFRSEL
- AB8500_DITHERCLKCTRL
- AB8500_DITHERCLKCTRL_DITHERDEL_MASK
- AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT
- AB8500_DITHERCLKCTRL_VAPEDITHERENA
- AB8500_DITHERCLKCTRL_VARMDITHERENA
- AB8500_DITHERCLKCTRL_VMODDITHERENA
- AB8500_DITHERCLKCTRL_VSMPS1DITHERENA
- AB8500_DITHERCLKCTRL_VSMPS2DITHERENA
- AB8500_DITHERCLKCTRL_VSMPS3DITHERENA
- AB8500_DMICFILTCONF
- AB8500_DMICFILTCONF_ANCINSEL
- AB8500_DMICFILTCONF_DA3TOEAR
- AB8500_DMICFILTCONF_DMIC1SINC3
- AB8500_DMICFILTCONF_DMIC2SINC3
- AB8500_DMICFILTCONF_DMIC3SINC3
- AB8500_DMICFILTCONF_DMIC4SINC3
- AB8500_DMICFILTCONF_DMIC5SINC3
- AB8500_DMICFILTCONF_DMIC6SINC3
- AB8500_ECI_AV_ACC
- AB8500_ENABLE_WD
- AB8500_ENVCPCONF
- AB8500_ENVCPCONF_ENVDETHTHRE
- AB8500_ENVCPCONF_ENVDETHTHRE_MAX
- AB8500_ENVCPCONF_ENVDETLTHRE
- AB8500_ENVCPCONF_ENVDETLTHRE_MAX
- AB8500_EXTSUPPLYREGU
- AB8500_EXT_SUPPLY1
- AB8500_EXT_SUPPLY2
- AB8500_EXT_SUPPLY3
- AB8500_FG_CALIB_END
- AB8500_FG_CALIB_INIT
- AB8500_FG_CALIB_WAIT
- AB8500_FG_CHARGE_INIT
- AB8500_FG_CHARGE_READOUT
- AB8500_FG_DISCHARGE_INIT
- AB8500_FG_DISCHARGE_INITMEASURING
- AB8500_FG_DISCHARGE_INIT_RECOVERY
- AB8500_FG_DISCHARGE_READOUT
- AB8500_FG_DISCHARGE_READOUT_INIT
- AB8500_FG_DISCHARGE_RECOVERY
- AB8500_FG_DISCHARGE_WAKEUP
- AB8500_FIFOCONF1
- AB8500_FIFOCONF1_BFIFO19M2
- AB8500_FIFOCONF1_BFIFOINT_MAX
- AB8500_FIFOCONF1_BFIFOINT_SHIFT
- AB8500_FIFOCONF1_BFIFOMASK
- AB8500_FIFOCONF2
- AB8500_FIFOCONF2_BFIFOTX_MAX
- AB8500_FIFOCONF2_BFIFOTX_SHIFT
- AB8500_FIFOCONF3
- AB8500_FIFOCONF3_BFIFOEXSL_MAX
- AB8500_FIFOCONF3_BFIFOEXSL_SHIFT
- AB8500_FIFOCONF3_BFIFOMAST_SHIFT
- AB8500_FIFOCONF3_BFIFORUN_SHIFT
- AB8500_FIFOCONF3_PREBITCLK0_MAX
- AB8500_FIFOCONF3_PREBITCLK0_SHIFT
- AB8500_FIFOCONF4
- AB8500_FIFOCONF4_BFIFOFRAMSW_MAX
- AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT
- AB8500_FIFOCONF5
- AB8500_FIFOCONF5_BFIFOWAKEUP_MAX
- AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT
- AB8500_FIFOCONF6
- AB8500_FIFOCONF6_BFIFOSAMPLE_MAX
- AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT
- AB8500_FILTER_ANC_FIR
- AB8500_FILTER_ANC_IIR
- AB8500_FILTER_CONTROL
- AB8500_FILTER_SID_FIR
- AB8500_FIRST_REG
- AB8500_FIRST_SIM_REG
- AB8500_FUNC_GROUPS
- AB8500_GASG_CC_ACCU1_REG
- AB8500_GASG_CC_ACCU2_REG
- AB8500_GASG_CC_ACCU3_REG
- AB8500_GASG_CC_ACCU4_REG
- AB8500_GASG_CC_CNTR_AVGOFF_REG
- AB8500_GASG_CC_CTRL_REG
- AB8500_GASG_CC_NCOV_ACCU
- AB8500_GASG_CC_NCOV_ACCU_CTRL
- AB8500_GASG_CC_NCOV_ACCU_HIGH
- AB8500_GASG_CC_NCOV_ACCU_LOW
- AB8500_GASG_CC_NCOV_ACCU_MED
- AB8500_GASG_CC_OFFSET_REG
- AB8500_GASG_CC_SMPL_CNTRH_REG
- AB8500_GASG_CC_SMPL_CNTRL_REG
- AB8500_GASG_CC_SMPL_CNVH_REG
- AB8500_GASG_CC_SMPL_CNVL_REG
- AB8500_GAS_GAUGE
- AB8500_GPADC
- AB8500_GPADC_AUTODATAH_REG
- AB8500_GPADC_AUTODATAL_REG
- AB8500_GPADC_AUTO_TIMER_REG
- AB8500_GPADC_CAL_1
- AB8500_GPADC_CAL_2
- AB8500_GPADC_CAL_3
- AB8500_GPADC_CAL_4
- AB8500_GPADC_CAL_5
- AB8500_GPADC_CAL_6
- AB8500_GPADC_CAL_7
- AB8500_GPADC_CTRL1_REG
- AB8500_GPADC_CTRL2_REG
- AB8500_GPADC_CTRL3_REG
- AB8500_GPADC_MANDATAH_REG
- AB8500_GPADC_MANDATAL_REG
- AB8500_GPADC_MUX_CTRL_REG
- AB8500_GPADC_STAT_REG
- AB8500_GPIO_ALTFUN_REG
- AB8500_GPIO_DIR1_REG
- AB8500_GPIO_DIR2_REG
- AB8500_GPIO_DIR3_REG
- AB8500_GPIO_DIR4_REG
- AB8500_GPIO_DIR5_REG
- AB8500_GPIO_DIR6_REG
- AB8500_GPIO_IN1_REG
- AB8500_GPIO_IN2_REG
- AB8500_GPIO_IN3_REG
- AB8500_GPIO_IN4_REG
- AB8500_GPIO_IN5_REG
- AB8500_GPIO_IN6_REG
- AB8500_GPIO_MAX_NUMBER
- AB8500_GPIO_OUT1_REG
- AB8500_GPIO_OUT2_REG
- AB8500_GPIO_OUT3_REG
- AB8500_GPIO_OUT4_REG
- AB8500_GPIO_OUT5_REG
- AB8500_GPIO_OUT6_REG
- AB8500_GPIO_PUD1_REG
- AB8500_GPIO_PUD2_REG
- AB8500_GPIO_PUD3_REG
- AB8500_GPIO_PUD4_REG
- AB8500_GPIO_PUD5_REG
- AB8500_GPIO_PUD6_REG
- AB8500_GPIO_SEL1_REG
- AB8500_GPIO_SEL2_REG
- AB8500_GPIO_SEL3_REG
- AB8500_GPIO_SEL4_REG
- AB8500_GPIO_SEL5_REG
- AB8500_GPIO_SEL6_REG
- AB8500_HIQCLKCTRL
- AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID
- AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID
- AB8500_HSLEARDIGGAIN
- AB8500_HSLEARDIGGAIN_FADEDISHSL
- AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX
- AB8500_HSLEARDIGGAIN_HSSINC1
- AB8500_HSRDIGGAIN
- AB8500_HSRDIGGAIN_FADEDISHSR
- AB8500_HSRDIGGAIN_FADESPEED
- AB8500_HSRDIGGAIN_HSRDGAIN_MAX
- AB8500_IC_NAME_REG
- AB8500_INTERRUPT
- AB8500_INT_ACC_DETECT_1DB_F
- AB8500_INT_ACC_DETECT_1DB_R
- AB8500_INT_ACC_DETECT_21DB_F
- AB8500_INT_ACC_DETECT_21DB_R
- AB8500_INT_ACC_DETECT_22DB_F
- AB8500_INT_ACC_DETECT_22DB_R
- AB8500_INT_ADP_PROBE_PLUG
- AB8500_INT_ADP_PROBE_UNPLUG
- AB8500_INT_ADP_SENSE_OFF
- AB8500_INT_ADP_SINK_ERROR
- AB8500_INT_ADP_SOURCE_ERROR
- AB8500_INT_BATT_OVV
- AB8500_INT_BAT_CTRL_INDB
- AB8500_INT_BTEMP_HIGH
- AB8500_INT_BTEMP_LOW
- AB8500_INT_BTEMP_LOW_MEDIUM
- AB8500_INT_BTEMP_MEDIUM_HIGH
- AB8500_INT_BUP_CHG_NOT_OK
- AB8500_INT_BUP_CHG_OK
- AB8500_INT_CCEOC
- AB8500_INT_CCN_CONV_ACC
- AB8500_INT_CC_INT_CALIB
- AB8500_INT_CHAUTORESTARTAFTSEC
- AB8500_INT_CHCURLIMHSCHIRP
- AB8500_INT_CHCURLIMNOHSCHIRP
- AB8500_INT_CHSTOPBYSEC
- AB8500_INT_CH_WD_EXP
- AB8500_INT_GPIO10F
- AB8500_INT_GPIO10R
- AB8500_INT_GPIO11F
- AB8500_INT_GPIO11R
- AB8500_INT_GPIO12F
- AB8500_INT_GPIO12R
- AB8500_INT_GPIO13F
- AB8500_INT_GPIO13R
- AB8500_INT_GPIO24F
- AB8500_INT_GPIO24R
- AB8500_INT_GPIO25F
- AB8500_INT_GPIO25R
- AB8500_INT_GPIO36F
- AB8500_INT_GPIO36R
- AB8500_INT_GPIO37F
- AB8500_INT_GPIO37R
- AB8500_INT_GPIO38F
- AB8500_INT_GPIO38R
- AB8500_INT_GPIO39F
- AB8500_INT_GPIO39R
- AB8500_INT_GPIO40F
- AB8500_INT_GPIO40R
- AB8500_INT_GPIO41F
- AB8500_INT_GPIO41R
- AB8500_INT_GPIO6F
- AB8500_INT_GPIO6R
- AB8500_INT_GPIO7F
- AB8500_INT_GPIO7R
- AB8500_INT_GPIO8F
- AB8500_INT_GPIO8R
- AB8500_INT_GPIO9F
- AB8500_INT_GPIO9R
- AB8500_INT_GP_HW_ADC_CONV_END
- AB8500_INT_GP_SW_ADC_CONV_END
- AB8500_INT_HOOK_DET_NEG_F
- AB8500_INT_HOOK_DET_NEG_R
- AB8500_INT_HOOK_DET_POS_F
- AB8500_INT_HOOK_DET_POS_R
- AB8500_INT_ID_DET_PLUGF
- AB8500_INT_ID_DET_PLUGR
- AB8500_INT_ID_DET_R1F
- AB8500_INT_ID_DET_R1R
- AB8500_INT_ID_DET_R2F
- AB8500_INT_ID_DET_R2R
- AB8500_INT_ID_DET_R3F
- AB8500_INT_ID_DET_R3R
- AB8500_INT_ID_DET_R4F
- AB8500_INT_ID_DET_R4R
- AB8500_INT_ID_WAKEUP_F
- AB8500_INT_ID_WAKEUP_R
- AB8500_INT_INT_AUD
- AB8500_INT_LOW_BAT_F
- AB8500_INT_LOW_BAT_R
- AB8500_INT_MAIN_CH_DROP_END
- AB8500_INT_MAIN_CH_PLUG_DET
- AB8500_INT_MAIN_CH_TH_PROT_F
- AB8500_INT_MAIN_CH_TH_PROT_R
- AB8500_INT_MAIN_CH_UNPLUG_DET
- AB8500_INT_MAIN_EXT_CH_NOT_OK
- AB8500_INT_PLUG_DET_COMP_F
- AB8500_INT_PLUG_DET_COMP_R
- AB8500_INT_PLUG_TV_DET
- AB8500_INT_PON_KEY1DB_F
- AB8500_INT_PON_KEY1DB_R
- AB8500_INT_PON_KEY2DB_F
- AB8500_INT_PON_KEY2DB_R
- AB8500_INT_RTC_60S
- AB8500_INT_RTC_ALARM
- AB8500_INT_SRP_DETECT
- AB8500_INT_TEMP_WARM
- AB8500_INT_UN_PLUG_TV_DET
- AB8500_INT_USB_CHARGER_NOT_OKR
- AB8500_INT_USB_CH_TH_PROT_F
- AB8500_INT_USB_CH_TH_PROT_R
- AB8500_INT_USB_LINK_STATUS
- AB8500_INT_USB_PHY_POWER_ERR
- AB8500_INT_VBUS_CH_DROP_END
- AB8500_INT_VBUS_DET_F
- AB8500_INT_VBUS_DET_R
- AB8500_INT_VBUS_OVV
- AB8500_INT_XTAL32K_KO
- AB8500_IT_LATCH10_REG
- AB8500_IT_LATCH12_REG
- AB8500_IT_LATCH19_REG
- AB8500_IT_LATCH1_REG
- AB8500_IT_LATCH20_REG
- AB8500_IT_LATCH21_REG
- AB8500_IT_LATCH22_REG
- AB8500_IT_LATCH23_REG
- AB8500_IT_LATCH24_REG
- AB8500_IT_LATCH2_REG
- AB8500_IT_LATCH3_REG
- AB8500_IT_LATCH4_REG
- AB8500_IT_LATCH5_REG
- AB8500_IT_LATCH6_REG
- AB8500_IT_LATCH7_REG
- AB8500_IT_LATCH8_REG
- AB8500_IT_LATCH9_REG
- AB8500_IT_LATCHHIER1_REG
- AB8500_IT_LATCHHIER2_REG
- AB8500_IT_LATCHHIER3_REG
- AB8500_IT_LATCHHIER_NUM
- AB8500_IT_MASK10_REG
- AB8500_IT_MASK11_REG
- AB8500_IT_MASK12_REG
- AB8500_IT_MASK13_REG
- AB8500_IT_MASK14_REG
- AB8500_IT_MASK15_REG
- AB8500_IT_MASK16_REG
- AB8500_IT_MASK17_REG
- AB8500_IT_MASK18_REG
- AB8500_IT_MASK19_REG
- AB8500_IT_MASK1_REG
- AB8500_IT_MASK20_REG
- AB8500_IT_MASK21_REG
- AB8500_IT_MASK22_REG
- AB8500_IT_MASK23_REG
- AB8500_IT_MASK24_REG
- AB8500_IT_MASK25_REG
- AB8500_IT_MASK2_REG
- AB8500_IT_MASK3_REG
- AB8500_IT_MASK4_REG
- AB8500_IT_MASK5_REG
- AB8500_IT_MASK6_REG
- AB8500_IT_MASK7_REG
- AB8500_IT_MASK8_REG
- AB8500_IT_MASK9_REG
- AB8500_IT_SOURCE19_REG
- AB8500_IT_SOURCE1_REG
- AB8500_IT_SOURCE20_REG
- AB8500_IT_SOURCE21_REG
- AB8500_IT_SOURCE22_REG
- AB8500_IT_SOURCE23_REG
- AB8500_IT_SOURCE24_REG
- AB8500_IT_SOURCE2_REG
- AB8500_IT_SOURCE3_REG
- AB8500_IT_SOURCE4_REG
- AB8500_IT_SOURCE5_REG
- AB8500_IT_SOURCE6_REG
- AB8500_IT_SOURCE7_REG
- AB8500_IT_SOURCE8_REG
- AB8500_KICK_WD
- AB8500_LAST_REG
- AB8500_LAST_SIM_REG
- AB8500_LDO_ANA
- AB8500_LDO_ANAMIC1
- AB8500_LDO_ANAMIC2
- AB8500_LDO_AUDIO
- AB8500_LDO_AUX1
- AB8500_LDO_AUX2
- AB8500_LDO_AUX3
- AB8500_LDO_DMIC
- AB8500_LDO_INTCORE
- AB8500_LDO_TVOUT
- AB8500_LED_INDICATOR_PWM_CTRL
- AB8500_LED_INDICATOR_PWM_DUTY
- AB8500_LOWBAT
- AB8500_LOWBAT_LOWBATENA
- AB8500_LOWBAT_LOWBAT_MASK
- AB8500_LOWBAT_LOWBAT_SHIFT
- AB8500_LOW_BAT_REG
- AB8500_MAINWDOGCTRL
- AB8500_MAINWDOGCTRL_MAINWDOGENA
- AB8500_MAINWDOGCTRL_MAINWDOGKICK
- AB8500_MAINWDOGCTRL_WDEXPTURNONVALID
- AB8500_MAINWDOGTIMER
- AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK
- AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT
- AB8500_MAIN_CH_DET
- AB8500_MAIN_WDOG_CTRL_REG
- AB8500_MAIN_WD_CTRL_REG
- AB8500_MASK_ALL
- AB8500_MASK_NONE
- AB8500_MASK_SLOT
- AB8500_MAX_NR_IRQS
- AB8500_MCH_CTRL1
- AB8500_MCH_CTRL2
- AB8500_MCH_IPT_CURLVL_REG
- AB8500_MISC
- AB8500_MUTECONF
- AB8500_MUTECONF_MUTDACEAR
- AB8500_MUTECONF_MUTDACHSL
- AB8500_MUTECONF_MUTDACHSR
- AB8500_MUTECONF_MUTEAR
- AB8500_MUTECONF_MUTHSL
- AB8500_MUTECONF_MUTHSR
- AB8500_M_FSM_RANK
- AB8500_NAME_STRING
- AB8500_NR_IRQS
- AB8500_NR_OF_ANC_COEFF_BANKS
- AB8500_NUM_BANKS
- AB8500_NUM_CLKS
- AB8500_NUM_EXT_REGULATORS
- AB8500_NUM_IRQ_REGS
- AB8500_NUM_REGULATORS
- AB8500_NUM_REGULATOR_REGISTERS
- AB8500_OTP_CONF_15
- AB8500_OTP_EMUL
- AB8500_PIN_A17
- AB8500_PIN_AA18
- AB8500_PIN_AA19
- AB8500_PIN_AA20
- AB8500_PIN_B17
- AB8500_PIN_C17
- AB8500_PIN_E15
- AB8500_PIN_E16
- AB8500_PIN_F14
- AB8500_PIN_F15
- AB8500_PIN_F5
- AB8500_PIN_G19
- AB8500_PIN_G20
- AB8500_PIN_G5
- AB8500_PIN_G6
- AB8500_PIN_GROUP
- AB8500_PIN_H19
- AB8500_PIN_H6
- AB8500_PIN_J6
- AB8500_PIN_K6
- AB8500_PIN_M16
- AB8500_PIN_P5
- AB8500_PIN_R16
- AB8500_PIN_R17
- AB8500_PIN_R5
- AB8500_PIN_T10
- AB8500_PIN_T14
- AB8500_PIN_T19
- AB8500_PIN_T5
- AB8500_PIN_T9
- AB8500_PIN_U16
- AB8500_PIN_U17
- AB8500_PIN_U19
- AB8500_PIN_U2
- AB8500_PIN_U5
- AB8500_PIN_U9
- AB8500_PIN_W15
- AB8500_PIN_W17
- AB8500_PIN_W18
- AB8500_PIN_W2
- AB8500_PIN_Y18
- AB8500_PONKEY1PRESSSTATUS
- AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK
- AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT
- AB8500_POR_ON_VBAT
- AB8500_POWERUP
- AB8500_POWERUP_ENANA
- AB8500_POWERUP_POWERUP
- AB8500_POW_KEY_1_ON
- AB8500_POW_KEY_2_ON
- AB8500_PROD_TEST
- AB8500_PWMGENCONF1
- AB8500_PWMGENCONF1_PWM1CTRL
- AB8500_PWMGENCONF1_PWM1NCTRL
- AB8500_PWMGENCONF1_PWM1PCTRL
- AB8500_PWMGENCONF1_PWM2CTRL
- AB8500_PWMGENCONF1_PWM2NCTRL
- AB8500_PWMGENCONF1_PWM2PCTRL
- AB8500_PWMGENCONF1_PWMTOVIB1
- AB8500_PWMGENCONF1_PWMTOVIB2
- AB8500_PWMGENCONF2
- AB8500_PWMGENCONF3
- AB8500_PWMGENCONF4
- AB8500_PWMGENCONF5
- AB8500_PWMGENCONFX_PWMVIBXDUTCYC
- AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX
- AB8500_PWMGENCONFX_PWMVIBXPOL
- AB8500_PWM_OUT_CTRL1_REG
- AB8500_PWM_OUT_CTRL2_REG
- AB8500_PWM_OUT_CTRL7_REG
- AB8500_REGUCTRL1VAMIC
- AB8500_REGUCTRL2SPARE
- AB8500_REGUCTRLDISCH
- AB8500_REGUCTRLDISCH2
- AB8500_REGUHWHPREQ1VALID1
- AB8500_REGUHWHPREQ1VALID2
- AB8500_REGUHWHPREQ2VALID1
- AB8500_REGUHWHPREQ2VALID2
- AB8500_REGUMISC1
- AB8500_REGUREQUESTCTRL2
- AB8500_REGUREQUESTCTRL3
- AB8500_REGUREQUESTCTRL4
- AB8500_REGUSWHPREQVALID1
- AB8500_REGUSWHPREQVALID2
- AB8500_REGUSYSCLKREQ1HPVALID1
- AB8500_REGUSYSCLKREQ1HPVALID2
- AB8500_REGUSYSCLKREQVALID1
- AB8500_REGUSYSCLKREQVALID2
- AB8500_REGU_CTRL1
- AB8500_REGU_CTRL2
- AB8500_RESERVED
- AB8500_RESETSTATUS
- AB8500_RESETSTATUS_RESETN4500NSTATUS
- AB8500_RESETSTATUS_SWRESETN4500NSTATUS
- AB8500_REV_REG
- AB8500_RTC
- AB8500_RTC_ALARM
- AB8500_RTC_ALRM_MIN_HI_REG
- AB8500_RTC_ALRM_MIN_LOW_REG
- AB8500_RTC_ALRM_MIN_MID_REG
- AB8500_RTC_BACKUP_CHG_REG
- AB8500_RTC_BKUP_CHG_REG
- AB8500_RTC_CALIB_REG
- AB8500_RTC_CC_CONF_REG
- AB8500_RTC_CTRL1_REG
- AB8500_RTC_CTRL_REG
- AB8500_RTC_FORCE_BKUP_REG
- AB8500_RTC_READ_REQ_REG
- AB8500_RTC_SOFF_STAT_REG
- AB8500_RTC_STAT_REG
- AB8500_RTC_SWITCH_STAT_REG
- AB8500_RTC_WATCH_TMIN_HI_REG
- AB8500_RTC_WATCH_TMIN_LOW_REG
- AB8500_RTC_WATCH_TMIN_MID_REG
- AB8500_RTC_WATCH_TSECHI_REG
- AB8500_RTC_WATCH_TSECMID_REG
- AB8500_SHORTCIRCONF
- AB8500_SHORTCIRCONF_EARSHORTDIS
- AB8500_SHORTCIRCONF_ENSHORTPWD
- AB8500_SHORTCIRCONF_HSFADDIS
- AB8500_SHORTCIRCONF_HSOSCEN
- AB8500_SHORTCIRCONF_HSPULLDEN
- AB8500_SHORTCIRCONF_HSSHORTDIS
- AB8500_SHORTCIRCONF_HSZCDDIS
- AB8500_SIDFIRADR
- AB8500_SIDFIRADR_ADDRESS_MAX
- AB8500_SIDFIRADR_ADDRESS_SHIFT
- AB8500_SIDFIRADR_FIRSIDSET
- AB8500_SIDFIRCOEF1
- AB8500_SIDFIRCOEF2
- AB8500_SIDFIRCONF
- AB8500_SIDFIRCONF_ENFIRSIDS
- AB8500_SIDFIRCONF_FIRSIDBUSY
- AB8500_SIDFIRCONF_FIRSIDSTOIF1
- AB8500_SIDFIRGAIN1
- AB8500_SIDFIRGAIN2
- AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX
- AB8500_SID_FIR_COEFFS
- AB8500_SID_FIR_COEFF_MAX
- AB8500_SID_FIR_COEFF_MIN
- AB8500_SIGENVCONF
- AB8500_SIGENVCONF_CPLVEN
- AB8500_SIGENVCONF_ENVDETCPEN
- AB8500_SIGENVCONF_ENVDETTIME
- AB8500_SIGENVCONF_ENVDETTIME_MAX
- AB8500_SMPSCLKCTRL
- AB8500_SMPSCLKCTRL_3M2CLKINTENA
- AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK
- AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT
- AB8500_SMPSCLKSEL1
- AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK
- AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT
- AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK
- AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT
- AB8500_SMPSCLKSEL2
- AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK
- AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT
- AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK
- AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT
- AB8500_SMPSCLKSEL3
- AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK
- AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT
- AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK
- AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT
- AB8500_STD_HOST_SUSP
- AB8500_STE_TEST
- AB8500_STW4500CTRL1
- AB8500_STW4500CTRL1_SWOFF
- AB8500_STW4500CTRL1_SWRESET4500N
- AB8500_STW4500CTRL1_THDB8500SWOFF
- AB8500_STW4500CTRL2
- AB8500_STW4500CTRL2_RESETNVAUX1VALID
- AB8500_STW4500CTRL2_RESETNVAUX2VALID
- AB8500_STW4500CTRL2_RESETNVAUX3VALID
- AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID
- AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID
- AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID
- AB8500_STW4500CTRL2_RESETNVMODVALID
- AB8500_STW4500CTRL2_RESETNVSMPS1VALID
- AB8500_STW4500CTRL3
- AB8500_STW4500CTRL3_CLK32KOUT2DIS
- AB8500_STW4500CTRL3_RESETAUDN
- AB8500_STW4500CTRL3_RESETDENCN
- AB8500_STW4500CTRL3_THSDENA
- AB8500_SUPPLY_CONTROL_CONFIG_1
- AB8500_SUPPLY_CONTROL_REG
- AB8500_SUPPORTED_FMT
- AB8500_SUPPORTED_RATE
- AB8500_SWATCTRL
- AB8500_SWATCTRL_RFOFFTIMER_MASK
- AB8500_SWATCTRL_RFOFFTIMER_SHIFT
- AB8500_SWATCTRL_SWATBIT5
- AB8500_SWATCTRL_SWATENABLE
- AB8500_SWATCTRL_UPDATERF
- AB8500_SWITCH_OFF_STATUS
- AB8500_SW_CONTROL_FALLBACK
- AB8500_SYSCLKCTRL
- AB8500_SYSCLKCTRL_TVOUTCLKENA
- AB8500_SYSCLKCTRL_TVOUTPLLENA
- AB8500_SYSCLKCTRL_USBCLKENA
- AB8500_SYSCLKREQ1RFCLKBUF
- AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2
- AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3
- AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4
- AB8500_SYSCLKREQ1VALID
- AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID
- AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID
- AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID
- AB8500_SYSCLKREQ2RFCLKBUF
- AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2
- AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3
- AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4
- AB8500_SYSCLKREQ3RFCLKBUF
- AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2
- AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3
- AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4
- AB8500_SYSCLKREQ4RFCLKBUF
- AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2
- AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3
- AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4
- AB8500_SYSCLKREQ5RFCLKBUF
- AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2
- AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3
- AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4
- AB8500_SYSCLKREQ6RFCLKBUF
- AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2
- AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3
- AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4
- AB8500_SYSCLKREQ7RFCLKBUF
- AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2
- AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3
- AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4
- AB8500_SYSCLKREQ8RFCLKBUF
- AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2
- AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3
- AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4
- AB8500_SYSCLKREQSTATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS
- AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS
- AB8500_SYSCLKTIMER
- AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK
- AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT
- AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK
- AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT
- AB8500_SYSCLK_AUDIO
- AB8500_SYSCLK_BUF2
- AB8500_SYSCLK_BUF3
- AB8500_SYSCLK_BUF4
- AB8500_SYSCLK_INT
- AB8500_SYSCLK_ULP
- AB8500_SYSTEMCTRLSUP
- AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK
- AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT
- AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK
- AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT
- AB8500_SYSTEMCTRLSUP_INTDB8500NOD
- AB8500_SYSULPCLKCONF
- AB8500_SYSULPCLKCONF_CLK27MHZBUFENA
- AB8500_SYSULPCLKCONF_CLK27MHZPDENA
- AB8500_SYSULPCLKCONF_CLK27MHZSTRE
- AB8500_SYSULPCLKCONF_TVOUTCLKDELN
- AB8500_SYSULPCLKCONF_TVOUTCLKINV
- AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK
- AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT
- AB8500_SYSULPCLKCONF_ULPCLKSTRE
- AB8500_SYSULPCLKCTRL1
- AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ
- AB8500_SYSULPCLKCTRL1_AUDIOCLKENA
- AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ
- AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ
- AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ
- AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK
- AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT
- AB8500_SYSULPCLKCTRL1_ULPCLKREQ
- AB8500_SYS_CHARGER_CONTROL_REG
- AB8500_SYS_CTRL1_BLOCK
- AB8500_SYS_CTRL2_BLOCK
- AB8500_TRISTATE
- AB8500_TURNONSTATUS
- AB8500_TURNONSTATUS_MAINCHDET
- AB8500_TURNONSTATUS_PONKEY1DBF
- AB8500_TURNONSTATUS_PONKEY2DBF
- AB8500_TURNONSTATUS_PORNVBAT
- AB8500_TURNONSTATUS_RTCALARM
- AB8500_TURNONSTATUS_USBIDDETECT
- AB8500_TURNONSTATUS_VBUSDET
- AB8500_TURN_ON_STATUS
- AB8500_TVOUT
- AB8500_USB
- AB8500_USBCH_CTRL1_REG
- AB8500_USBCH_CTRL2_REG
- AB8500_USBCH_IPT_CRNTLVL_REG
- AB8500_USB_FLAG_REGULATOR_SET_VOLTAGE
- AB8500_USB_FLAG_USE_AB_IDDET
- AB8500_USB_FLAG_USE_ID_WAKEUP_IRQ
- AB8500_USB_FLAG_USE_LINK_STATUS_IRQ
- AB8500_USB_FLAG_USE_VBUS_DET_IRQ
- AB8500_USB_ID_DET
- AB8500_USB_LINE_CTRL2_REG
- AB8500_USB_LINE_STAT_REG
- AB8500_USB_LINK1_STAT_REG
- AB8500_USB_LINK_STATUS
- AB8500_USB_PHY_CTRL_REG
- AB8500_USB_PHY_TUNE1
- AB8500_USB_PHY_TUNE2
- AB8500_USB_PHY_TUNE3
- AB8500_V20_31952_DISABLE_DELAY_US
- AB8500_VAUDIOSUPPLY
- AB8500_VAUX12REGU
- AB8500_VAUX1SEL
- AB8500_VAUX2SEL
- AB8500_VBUS_DET
- AB8500_VERSION_AB8500
- AB8500_VERSION_AB8505
- AB8500_VERSION_AB8540
- AB8500_VERSION_AB9540
- AB8500_VERSION_UNDEFINED
- AB8500_VPLLVANAREGU
- AB8500_VREFDDR
- AB8500_VRF1VAUX3REGU
- AB8500_VRF1VAUX3SEL
- AB8500_VSIMSYSCLKCTRL
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID
- AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID
- AB8500_WD_KICK_DELAY_US
- AB8500_WD_RESTART_ON_EXPIRE
- AB8500_WD_V11_DISABLE_DELAY_US
- AB8500_ZEROES
- AB8505_CTRLVAUX5
- AB8505_CTRLVAUX6
- AB8505_EXTSUPPLYREGU
- AB8505_FUNC_GROUPS
- AB8505_GPIO_MAX_NUMBER
- AB8505_INT_ACC_INT
- AB8505_INT_COLL
- AB8505_INT_COMERR
- AB8505_INT_DREC
- AB8505_INT_DSENT
- AB8505_INT_FRAERR
- AB8505_INT_IKP
- AB8505_INT_IKR
- AB8505_INT_KEYDEGLITCH
- AB8505_INT_KEYSTUCK
- AB8505_INT_KP
- AB8505_INT_MODPWRSTATUSF
- AB8505_INT_MODPWRSTATUSR
- AB8505_INT_NOPINT
- AB8505_INT_RESERR
- AB8505_INT_SPDSET
- AB8505_LAST_SIM_REG
- AB8505_LDO_ADC
- AB8505_LDO_ANA
- AB8505_LDO_ANAMIC1
- AB8505_LDO_ANAMIC2
- AB8505_LDO_AUDIO
- AB8505_LDO_AUX1
- AB8505_LDO_AUX2
- AB8505_LDO_AUX3
- AB8505_LDO_AUX4
- AB8505_LDO_AUX5
- AB8505_LDO_AUX6
- AB8505_LDO_AUX8
- AB8505_LDO_INTCORE
- AB8505_NR_IRQS
- AB8505_NUM_REGULATORS
- AB8505_NUM_REGULATOR_REGISTERS
- AB8505_PIN_B16
- AB8505_PIN_B17
- AB8505_PIN_C16
- AB8505_PIN_D15
- AB8505_PIN_D16
- AB8505_PIN_D17
- AB8505_PIN_GROUP
- AB8505_PIN_H14
- AB8505_PIN_J14
- AB8505_PIN_J15
- AB8505_PIN_L4
- AB8505_PIN_N3
- AB8505_PIN_N4
- AB8505_PIN_P2
- AB8505_PIN_P3
- AB8505_PIN_P5
- AB8505_PIN_R5
- AB8505_PIN_T1
- AB8505_REGUCTRL1VAMIC
- AB8505_REGUCTRLDISCH
- AB8505_REGUCTRLDISCH2
- AB8505_REGUCTRLDISCH3
- AB8505_REGUHWHPREQ1VALID1
- AB8505_REGUHWHPREQ1VALID2
- AB8505_REGUHWHPREQ2VALID1
- AB8505_REGUHWHPREQ2VALID2
- AB8505_REGUMISC1
- AB8505_REGUREQUESTCTRL1
- AB8505_REGUREQUESTCTRL2
- AB8505_REGUREQUESTCTRL3
- AB8505_REGUREQUESTCTRL4
- AB8505_REGUSWHPREQVALID1
- AB8505_REGUSWHPREQVALID2
- AB8505_REGUSYSCLKREQ1HPVALID1
- AB8505_REGUSYSCLKREQ1HPVALID2
- AB8505_REGUSYSCLKREQVALID1
- AB8505_REGUSYSCLKREQVALID2
- AB8505_REGUVAUX4REQVALID
- AB8505_RTC_PCUT_CTL_STATUS_REG
- AB8505_RTC_PCUT_DEBOUNCE_REG
- AB8505_RTC_PCUT_FLAG_TIME_REG
- AB8505_RTC_PCUT_MAX_TIME_REG
- AB8505_RTC_PCUT_RESTART_REG
- AB8505_RTC_PCUT_TIME_REG
- AB8505_TURN_ON_STATUS_2
- AB8505_USB_LINE_STAT_REG
- AB8505_USB_LINK_STATUS
- AB8505_VAUDIOSUPPLY
- AB8505_VAUX12REGU
- AB8505_VAUX1SEL
- AB8505_VAUX2SEL
- AB8505_VAUX4REGU
- AB8505_VAUX4REQCTRL
- AB8505_VAUX4SEL
- AB8505_VPLLVANAREGU
- AB8505_VRF1VAUX3REGU
- AB8505_VRF1VAUX3SEL
- AB8505_VSAFEREGU
- AB8505_VSAFESEL1
- AB8505_VSAFESEL2
- AB8505_VSAFESEL3
- AB8505_VSMPSAREGU
- AB8505_VSMPSASEL1
- AB8505_VSMPSASEL2
- AB8505_VSMPSASEL3
- AB8505_VSMPSBREGU
- AB8505_VSMPSBSEL1
- AB8505_VSMPSBSEL2
- AB8505_VSMPSBSEL3
- AB8540_CH_USBCH_STAT3_REG
- AB8540_GPADC_APEAAH_REG
- AB8540_GPADC_APEAAL_REG
- AB8540_GPADC_APEAAM_REG
- AB8540_GPADC_APEAAT_REG
- AB8540_GPADC_APEAAX_REG
- AB8540_GPADC_MANDATA2H_REG
- AB8540_GPADC_MANDATA2L_REG
- AB8540_GPADC_OTP4_REG_5
- AB8540_GPADC_OTP4_REG_6
- AB8540_GPADC_OTP4_REG_7
- AB8540_INT_ADDATA2F
- AB8540_INT_ADDATA2R
- AB8540_INT_BIF_INT
- AB8540_INT_BITCLK2F
- AB8540_INT_BITCLK2R
- AB8540_INT_DADATA2F
- AB8540_INT_DADATA2R
- AB8540_INT_FMDETCOMPHIF
- AB8540_INT_FMDETCOMPHIR
- AB8540_INT_FMDETCOMPLOF
- AB8540_INT_FMDETCOMPLOR
- AB8540_INT_FSYNC2F
- AB8540_INT_FSYNC2R
- AB8540_INT_GPIO1VBATF
- AB8540_INT_GPIO1VBATR
- AB8540_INT_GPIO2VBATF
- AB8540_INT_GPIO2VBATR
- AB8540_INT_GPIO3VBATF
- AB8540_INT_GPIO3VBATR
- AB8540_INT_GPIO43F
- AB8540_INT_GPIO43R
- AB8540_INT_GPIO44F
- AB8540_INT_GPIO44R
- AB8540_INT_GPIO4VBATF
- AB8540_INT_GPIO4VBATR
- AB8540_INT_ID5VDETCOMPF
- AB8540_INT_ID5VDETCOMPR
- AB8540_INT_IDPLUGDETCOMPF
- AB8540_INT_IDPLUGDETCOMPR
- AB8540_INT_KEYNEGDETCOMPF
- AB8540_INT_KEYNEGDETCOMPR
- AB8540_INT_KEYPOSDETCOMPF
- AB8540_INT_KEYPOSDETCOMPR
- AB8540_INT_PWMCTRL0F
- AB8540_INT_PWMCTRL0R
- AB8540_INT_PWMCTRL1F
- AB8540_INT_PWMCTRL1R
- AB8540_INT_PWMEXTVIBRA1F
- AB8540_INT_PWMEXTVIBRA1R
- AB8540_INT_PWMEXTVIBRA2F
- AB8540_INT_PWMEXTVIBRA2R
- AB8540_INT_PWMOUT1F
- AB8540_INT_PWMOUT1R
- AB8540_INT_PWMOUT2F
- AB8540_INT_PWMOUT2R
- AB8540_INT_PWMOUT3F
- AB8540_INT_PWMOUT3R
- AB8540_INT_RTC_1S
- AB8540_INT_SYSCLKREQ2F
- AB8540_INT_SYSCLKREQ2R
- AB8540_INT_SYSCLKREQ3F
- AB8540_INT_SYSCLKREQ3R
- AB8540_INT_SYSCLKREQ4F
- AB8540_INT_SYSCLKREQ4R
- AB8540_INT_SYSCLKREQ5F
- AB8540_INT_SYSCLKREQ5R
- AB8540_INT_SYSCLKREQ6F
- AB8540_INT_SYSCLKREQ6R
- AB8540_IT_LATCHHIER4_REG
- AB8540_IT_LATCHHIER_NUM
- AB8540_NR_IRQS
- AB8540_NUM_IRQ_REGS
- AB8540_USB_PP_CHR_REG
- AB8540_USB_PP_MODE_REG
- AB9
- AB9540_INT_GPIO50F
- AB9540_INT_GPIO50R
- AB9540_INT_GPIO51F
- AB9540_INT_GPIO51R
- AB9540_INT_GPIO52F
- AB9540_INT_GPIO52R
- AB9540_INT_GPIO53F
- AB9540_INT_GPIO53R
- AB9540_INT_GPIO54F
- AB9540_INT_GPIO54R
- AB9540_INT_IEXT_CH_RF_BFN_F
- AB9540_INT_IEXT_CH_RF_BFN_R
- AB9540_IT_LATCH13_REG
- AB9540_IT_SOURCE13_REG
- AB9540_MODEM_CTRL2_REG
- AB9540_MODEM_CTRL2_SWDBBRSTN_BIT
- AB9540_NR_IRQS
- AB9540_NUM_IRQ_REGS
- AB9540_SYSCLK12BUF1VALID
- AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK
- AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT
- AB9540_SYSCLK12BUF2VALID
- AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK
- AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT
- AB9540_SYSCLK12BUF3VALID
- AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK
- AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT
- AB9540_SYSCLK12BUF4VALID
- AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK
- AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT
- AB9540_SYSCLK12BUFCTRL
- AB9540_SYSCLK12BUFCTRL2
- AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA
- AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA
- AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA
- AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK
- AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK
- AB9540_SYSCLK12CONFCTRL
- AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0
- AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1
- AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA
- AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX
- AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX
- AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL
- AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID
- ABB5ZES3_ALRM_SEC_LEN
- ABB5ZES3_CTRL_SEC_LEN
- ABB5ZES3_MEM_MAP_LEN
- ABB5ZES3_REG_ALRM_DT
- ABB5ZES3_REG_ALRM_DT_AE
- ABB5ZES3_REG_ALRM_DW
- ABB5ZES3_REG_ALRM_DW_AE
- ABB5ZES3_REG_ALRM_HR
- ABB5ZES3_REG_ALRM_HR_AE
- ABB5ZES3_REG_ALRM_MN
- ABB5ZES3_REG_ALRM_MN_AE
- ABB5ZES3_REG_CTRL1
- ABB5ZES3_REG_CTRL1_AIE
- ABB5ZES3_REG_CTRL1_CAP
- ABB5ZES3_REG_CTRL1_CIE
- ABB5ZES3_REG_CTRL1_PM
- ABB5ZES3_REG_CTRL1_SIE
- ABB5ZES3_REG_CTRL1_SR
- ABB5ZES3_REG_CTRL1_STOP
- ABB5ZES3_REG_CTRL2
- ABB5ZES3_REG_CTRL2_AF
- ABB5ZES3_REG_CTRL2_CTAF
- ABB5ZES3_REG_CTRL2_CTAIE
- ABB5ZES3_REG_CTRL2_CTBF
- ABB5ZES3_REG_CTRL2_CTBIE
- ABB5ZES3_REG_CTRL2_SF
- ABB5ZES3_REG_CTRL2_WTAF
- ABB5ZES3_REG_CTRL2_WTAIE
- ABB5ZES3_REG_CTRL3
- ABB5ZES3_REG_CTRL3_BLF
- ABB5ZES3_REG_CTRL3_BLIE
- ABB5ZES3_REG_CTRL3_BSF
- ABB5ZES3_REG_CTRL3_BSIE
- ABB5ZES3_REG_CTRL3_PM0
- ABB5ZES3_REG_CTRL3_PM1
- ABB5ZES3_REG_CTRL3_PM2
- ABB5ZES3_REG_FREQ_OF
- ABB5ZES3_REG_FREQ_OF_MODE
- ABB5ZES3_REG_RTC_DT
- ABB5ZES3_REG_RTC_DW
- ABB5ZES3_REG_RTC_HR
- ABB5ZES3_REG_RTC_HR_PM
- ABB5ZES3_REG_RTC_MN
- ABB5ZES3_REG_RTC_MO
- ABB5ZES3_REG_RTC_SC
- ABB5ZES3_REG_RTC_SC_OSC
- ABB5ZES3_REG_RTC_YR
- ABB5ZES3_REG_TIMA
- ABB5ZES3_REG_TIMA_CLK
- ABB5ZES3_REG_TIMA_CLK_TAQ0
- ABB5ZES3_REG_TIMA_CLK_TAQ1
- ABB5ZES3_REG_TIMA_CLK_TAQ2
- ABB5ZES3_REG_TIMB
- ABB5ZES3_REG_TIMB_CLK
- ABB5ZES3_REG_TIMB_CLK_TAQ0
- ABB5ZES3_REG_TIMB_CLK_TAQ1
- ABB5ZES3_REG_TIMB_CLK_TAQ2
- ABB5ZES3_REG_TIMB_CLK_TBW0
- ABB5ZES3_REG_TIMB_CLK_TBW1
- ABB5ZES3_REG_TIMB_CLK_TBW2
- ABB5ZES3_REG_TIM_CLK
- ABB5ZES3_REG_TIM_CLK_COF0
- ABB5ZES3_REG_TIM_CLK_COF1
- ABB5ZES3_REG_TIM_CLK_COF2
- ABB5ZES3_REG_TIM_CLK_TAC0
- ABB5ZES3_REG_TIM_CLK_TAC1
- ABB5ZES3_REG_TIM_CLK_TAM
- ABB5ZES3_REG_TIM_CLK_TBC
- ABB5ZES3_REG_TIM_CLK_TBM
- ABB5ZES3_RTC_SEC_LEN
- ABB5ZES3_TIMA_SEC_LEN
- ABB5ZES3_TIMB_SEC_LEN
- ABBOTT_PRODUCT_ID
- ABBOTT_STEREO_PLUG_ID
- ABBOTT_STRIP_PORT_ID
- ABBOTT_VENDOR_ID
- ABBREV_DIC
- ABB_END
- ABB_SRT
- ABC
- ABCCR
- ABCD
- ABCNTH
- ABCNTL
- ABD_STATE
- ABEF_SAVE
- ABEOZ953_TEMP_MAX
- ABEOZ953_TEMP_MIN
- ABEOZ9_HOURS_PM
- ABEOZ9_REG_CTRL1
- ABEOZ9_REG_CTRL1_CLKINT
- ABEOZ9_REG_CTRL1_EERE
- ABEOZ9_REG_CTRL1_MASK
- ABEOZ9_REG_CTRL1_SRON
- ABEOZ9_REG_CTRL1_TAR
- ABEOZ9_REG_CTRL1_TD0
- ABEOZ9_REG_CTRL1_TD1
- ABEOZ9_REG_CTRL1_TE
- ABEOZ9_REG_CTRL1_WE
- ABEOZ9_REG_CTRL_INT
- ABEOZ9_REG_CTRL_INT_AIE
- ABEOZ9_REG_CTRL_INT_FLAG
- ABEOZ9_REG_CTRL_INT_FLAG_AF
- ABEOZ9_REG_CTRL_INT_FLAG_SRF
- ABEOZ9_REG_CTRL_INT_FLAG_TF
- ABEOZ9_REG_CTRL_INT_FLAG_V1IF
- ABEOZ9_REG_CTRL_INT_FLAG_V2IF
- ABEOZ9_REG_CTRL_INT_SRIE
- ABEOZ9_REG_CTRL_INT_TIE
- ABEOZ9_REG_CTRL_INT_V1IE
- ABEOZ9_REG_CTRL_INT_V2IE
- ABEOZ9_REG_CTRL_STATUS
- ABEOZ9_REG_CTRL_STATUS_EEBUSY
- ABEOZ9_REG_CTRL_STATUS_PON
- ABEOZ9_REG_CTRL_STATUS_SR
- ABEOZ9_REG_CTRL_STATUS_V1F
- ABEOZ9_REG_CTRL_STATUS_V2F
- ABEOZ9_REG_DAYS
- ABEOZ9_REG_EEPROM
- ABEOZ9_REG_EEPROM_FD0
- ABEOZ9_REG_EEPROM_FD1
- ABEOZ9_REG_EEPROM_MASK
- ABEOZ9_REG_EEPROM_R1K
- ABEOZ9_REG_EEPROM_R20K
- ABEOZ9_REG_EEPROM_R5K
- ABEOZ9_REG_EEPROM_R80K
- ABEOZ9_REG_EEPROM_THE
- ABEOZ9_REG_EEPROM_THP
- ABEOZ9_REG_HOURS
- ABEOZ9_REG_MIN
- ABEOZ9_REG_MONTHS
- ABEOZ9_REG_REG_TEMP
- ABEOZ9_REG_SEC
- ABEOZ9_REG_WEEKDAYS
- ABEOZ9_REG_YEARS
- ABEOZ9_SEC_LEN
- ABGR_TO_A_BG_G_RB
- ABI16_IOCTL_ARGS
- ABID
- ABID_MASK
- ABID_SHIFT
- ABIGAP
- ABIS
- ABIST_ADC_CAL
- ABIST_BIN1_VGA0
- ABIST_BIN2_VGA1
- ABIST_BIN3_VGA2
- ABIST_BIN4_VGA3
- ABIST_BIN5_VGA4
- ABIST_BIN6_VGA5
- ABIST_BIN7_VGA6
- ABIST_CLAMP_A
- ABIST_CLAMP_B
- ABIST_CLAMP_C
- ABIST_CLAMP_D
- ABIST_CLAMP_E
- ABIST_CLAMP_F
- ABIST_COEF12
- ABIST_COEF34
- ABIST_COEF56
- ABIST_COEF7_SNR
- ABIST_CTRL_STATUS
- ABIST_DATA_FMT
- ABIST_EN
- ABIST_FREQ
- ABIST_GOERT_SHIFT
- ABITUGURU_FAN_NAMES_LENGTH
- ABITUGURU_IN_NAMES_LENGTH
- ABITUGURU_PWM_NAMES_LENGTH
- ABITUGURU_SYSFS_NAMES_LENGTH
- ABITUGURU_TEMP_NAMES_LENGTH
- ABIT_UGURU3_ALARMS_START
- ABIT_UGURU3_BASE
- ABIT_UGURU3_BEEP_ENABLE
- ABIT_UGURU3_BOARD_ID
- ABIT_UGURU3_CMD
- ABIT_UGURU3_DATA
- ABIT_UGURU3_DEBUG
- ABIT_UGURU3_FAN_LOW_ALARM_ENABLE
- ABIT_UGURU3_FAN_NAMES_LENGTH
- ABIT_UGURU3_FAN_SENSOR
- ABIT_UGURU3_IN_NAMES_LENGTH
- ABIT_UGURU3_IN_SENSOR
- ABIT_UGURU3_MAX_DMI_NAMES
- ABIT_UGURU3_MAX_NO_SENSORS
- ABIT_UGURU3_MISC_BANK
- ABIT_UGURU3_NAME
- ABIT_UGURU3_PM
- ABIT_UGURU3_REGION_LENGTH
- ABIT_UGURU3_SENSORS_BANK
- ABIT_UGURU3_SETTINGS_BANK
- ABIT_UGURU3_SETTINGS_START
- ABIT_UGURU3_SHUTDOWN_ENABLE
- ABIT_UGURU3_STATUS_BUSY
- ABIT_UGURU3_STATUS_READY_FOR_READ
- ABIT_UGURU3_SUCCESS
- ABIT_UGURU3_SYNCHRONIZE_TIMEOUT
- ABIT_UGURU3_SYSFS_NAMES_LENGTH
- ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE
- ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG
- ABIT_UGURU3_TEMP_NAMES_LENGTH
- ABIT_UGURU3_TEMP_SENSOR
- ABIT_UGURU3_VALUES_START
- ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE
- ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG
- ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE
- ABIT_UGURU3_VOLT_LOW_ALARM_FLAG
- ABIT_UGURU3_WAIT_TIMEOUT
- ABIT_UGURU_ALARM_BANK
- ABIT_UGURU_BASE
- ABIT_UGURU_BEEP_ENABLE
- ABIT_UGURU_CMD
- ABIT_UGURU_DATA
- ABIT_UGURU_DEBUG
- ABIT_UGURU_FAN_LOW_ALARM_ENABLE
- ABIT_UGURU_FAN_MAX
- ABIT_UGURU_FAN_PWM
- ABIT_UGURU_FAN_PWM_ENABLE
- ABIT_UGURU_IN_SENSOR
- ABIT_UGURU_MAX_BANK1_SENSORS
- ABIT_UGURU_MAX_BANK2_SENSORS
- ABIT_UGURU_MAX_PWMS
- ABIT_UGURU_MAX_RETRIES
- ABIT_UGURU_MAX_TIMEOUTS
- ABIT_UGURU_NAME
- ABIT_UGURU_NC
- ABIT_UGURU_PM
- ABIT_UGURU_READY_TIMEOUT
- ABIT_UGURU_REGION_LENGTH
- ABIT_UGURU_RETRY_DELAY
- ABIT_UGURU_SENSOR_BANK1
- ABIT_UGURU_SENSOR_BANK2
- ABIT_UGURU_SHUTDOWN_ENABLE
- ABIT_UGURU_STATUS_INPUT
- ABIT_UGURU_STATUS_READ
- ABIT_UGURU_STATUS_READY
- ABIT_UGURU_STATUS_WRITE
- ABIT_UGURU_TEMP_HIGH_ALARM_ENABLE
- ABIT_UGURU_TEMP_HIGH_ALARM_FLAG
- ABIT_UGURU_TEMP_SENSOR
- ABIT_UGURU_VOLT_HIGH_ALARM_ENABLE
- ABIT_UGURU_VOLT_HIGH_ALARM_FLAG
- ABIT_UGURU_VOLT_LOW_ALARM_ENABLE
- ABIT_UGURU_VOLT_LOW_ALARM_FLAG
- ABIT_UGURU_WAIT_TIMEOUT
- ABIT_UGURU_WAIT_TIMEOUT_SLEEP
- ABI_0_ESZ
- ABI_ALL
- ABI_DEFHANDLER_COFF
- ABI_DEFHANDLER_ELF
- ABI_DEFHANDLER_LCALL7
- ABI_DEFHANDLER_LIBCSO
- ABI_FAKE_UTSNAME
- ABI_MAS_ADDR_BMP_IDX_MASK
- ABI_MAS_ADDR_BMP_IDX_SHIFT
- ABI_MAS_FBR_ANT_PTN_MASK
- ABI_MAS_FBR_ANT_PTN_SHIFT
- ABI_MAS_MRT_ANT_PTN_MASK
- ABI_N32
- ABI_N64
- ABI_O32
- ABI_TRACE
- ABLKCIPHER_WALK_SLOW
- ABLK_CTX
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK
- ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT
- ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK
- ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK
- ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT
- ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK
- ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK
- ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT
- ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK
- ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT
- ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK
- ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT
- ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK
- ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT
- ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK
- ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT
- ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK
- ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK
- ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK
- ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK
- ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT
- ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK
- ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT
- ABM0_DC_ABM1_CNTL__ABM1_EN_MASK
- ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT
- ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK
- ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK
- ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT
- ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK
- ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT
- ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK
- ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT
- ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK
- ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT
- ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK
- ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT
- ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK
- ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK
- ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT
- ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK
- ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT
- ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK
- ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT
- ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK
- ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT
- ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK
- ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT
- ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK
- ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT
- ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK
- ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT
- ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK
- ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT
- ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK
- ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT
- ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK
- ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT
- ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK
- ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT
- ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK
- ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT
- ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK
- ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT
- ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK
- ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT
- ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK
- ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT
- ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK
- ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT
- ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK
- ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT
- ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK
- ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT
- ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK
- ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT
- ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK
- ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT
- ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK
- ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT
- ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK
- ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT
- ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK
- ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT
- ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK
- ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT
- ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK
- ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK
- ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT
- ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK
- ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT
- ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK
- ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT
- ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK
- ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT
- ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK
- ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT
- ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK
- ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK
- ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT
- ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK
- ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT
- ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK
- ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT
- ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK
- ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK
- ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK
- ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT
- ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK
- ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK
- ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT
- ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK
- ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK
- ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT
- ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK
- ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT
- ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK
- ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT
- ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK
- ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT
- ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK
- ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT
- ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK
- ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK
- ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK
- ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK
- ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT
- ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK
- ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT
- ABM1_DC_ABM1_CNTL__ABM1_EN_MASK
- ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT
- ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK
- ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK
- ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT
- ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK
- ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT
- ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK
- ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT
- ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK
- ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT
- ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK
- ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT
- ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK
- ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK
- ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT
- ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK
- ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT
- ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK
- ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT
- ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK
- ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT
- ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK
- ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT
- ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK
- ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT
- ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK
- ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT
- ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK
- ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT
- ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK
- ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT
- ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK
- ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT
- ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK
- ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT
- ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK
- ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT
- ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK
- ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT
- ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK
- ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT
- ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK
- ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT
- ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK
- ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT
- ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK
- ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT
- ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK
- ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT
- ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK
- ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT
- ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK
- ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT
- ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK
- ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT
- ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK
- ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT
- ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK
- ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT
- ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK
- ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT
- ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK
- ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK
- ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT
- ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK
- ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT
- ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK
- ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT
- ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK
- ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT
- ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK
- ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT
- ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK
- ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK
- ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT
- ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK
- ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT
- ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK
- ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT
- ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK
- ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK
- ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT
- ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK
- ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT
- ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE
- ABM_COMMON_REG_LIST_DCE_BASE
- ABM_DCE110_COMMON_REG_LIST
- ABM_DCN10_REG_LIST
- ABM_DCN20_REG_LIST
- ABM_MASK_SH_LIST_DCE110
- ABM_MASK_SH_LIST_DCN10
- ABM_MASK_SH_LIST_DCN20
- ABM_REG_FIELD_LIST
- ABM_SF
- ABM_SOFT_RESET
- ABM_SOFT_RESET_0
- ABM_SOFT_RESET_1
- ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK
- ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT
- ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK
- ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT
- ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK
- ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT
- ABNORMAL_INT
- ABORT
- ABORTED
- ABORTED_COMMAND
- ABORTED_ONLINE_VERIFY
- ABORTED_RESYNC
- ABORTING
- ABORTING_OR_DISCONNECTING
- ABORTION
- ABORTTX
- ABORTXFER
- ABORT_ADDR
- ABORT_ALL
- ABORT_CONN
- ABORT_DEV
- ABORT_DEV_
- ABORT_DISK_IO
- ABORT_DONE
- ABORT_DUMP
- ABORT_ERR
- ABORT_INT
- ABORT_IOCB_TYPE
- ABORT_IOCB_TYPE_FX00
- ABORT_MASK
- ABORT_ON
- ABORT_ON_BUS_RESET
- ABORT_OPERATION
- ABORT_POLLING_PERIOD
- ABORT_RATE_CHANGE
- ABORT_REQ_IN_PROGRESS
- ABORT_RSS_SRQIDX_G
- ABORT_RSS_SRQIDX_M
- ABORT_RSS_SRQIDX_S
- ABORT_RSS_SRQIDX_V
- ABORT_RSS_STATUS_G
- ABORT_RSS_STATUS_M
- ABORT_RSS_STATUS_S
- ABORT_RSS_STATUS_V
- ABORT_SINGLE
- ABORT_ST
- ABORT_STATUS
- ABORT_TAG
- ABORT_TASK
- ABORT_TASK_SET
- ABORT_TIMEOUT
- ABORT_UPCALL
- ABORT_WAIT_ITER
- ABOUT
- ABP001GG
- ABP001PD
- ABP001PG
- ABP005PD
- ABP005PG
- ABP006KD
- ABP006KG
- ABP010KD
- ABP010KG
- ABP015PD
- ABP015PG
- ABP016KD
- ABP016KG
- ABP025KD
- ABP025KG
- ABP030PD
- ABP030PG
- ABP040KD
- ABP040KG
- ABP060KD
- ABP060KG
- ABP060MG_ERROR_MASK
- ABP060MG_MAX_COUNTS
- ABP060MG_MIN_COUNTS
- ABP060MG_NUM_COUNTS
- ABP060MG_RESP_TIME_MS
- ABP060PD
- ABP060PG
- ABP100KD
- ABP100KG
- ABP100PG
- ABP150PG
- ABP160KD
- ABP160KG
- ABP250KD
- ABP250KG
- ABP400KD
- ABP400KG
- ABP600KG
- ABR
- ABRNEXTLINK
- ABRT
- ABRT_10ADDR1_NOACK
- ABRT_10ADDR2_NOACK
- ABRT_10B_RD_NORSTRT
- ABRT_7B_ADDR_NOACK
- ABRT_CMD
- ABRT_GCALL_NOACK
- ABRT_GCALL_READ
- ABRT_MASTER_DIS
- ABRT_MODE
- ABRT_SBYTE_ACKDET
- ABRT_SBYTE_NORSTRT
- ABRT_SLAVE_ARBLOST
- ABRT_SLAVE_FLUSH_TXFIFO
- ABRT_SLAVE_RD_INTX
- ABRT_TXDATA_NOACK
- ABRUBR_ARB
- ABRWQ_BASE
- ABRWQ_RDPTR
- ABRWQ_WRPTR
- ABR_CELL_COUNT_REACHED_MASK
- ABR_CELL_COUNT_REACHED_MULT
- ABR_EN
- ABR_LKUP_BASE
- ABR_RATE_TYPE
- ABR_ROUND_ROBIN
- ABR_SBPTR_BASE
- ABR_SBVC
- ABR_SCHED_TABLE
- ABR_STATE
- ABR_TX_CELL_COUNT_INT
- ABR_VC_TABLE
- ABR_WAIT_Q
- ABS
- ABSCENT_RATIO
- ABSMAX_ACC_VAL
- ABSMIN_ACC_VAL
- ABS_ADDR
- ABS_BRAKE
- ABS_CNT
- ABS_CODE
- ABS_DIFF
- ABS_DISTANCE
- ABS_EDGE_MOTION_MASK
- ABS_GAS
- ABS_HAT0X
- ABS_HAT0Y
- ABS_HAT1X
- ABS_HAT1Y
- ABS_HAT2X
- ABS_HAT2Y
- ABS_HAT3X
- ABS_HAT3Y
- ABS_HSCROLL_BIT
- ABS_LSB_X_REG
- ABS_LSB_Y_REG
- ABS_MAX
- ABS_MIN_FREQ_2595
- ABS_MISC
- ABS_MSB_X_REG
- ABS_MSB_Y_REG
- ABS_MT_BLOB_ID
- ABS_MT_DISTANCE
- ABS_MT_FIRST
- ABS_MT_LAST
- ABS_MT_ORIENTATION
- ABS_MT_POSITION_X
- ABS_MT_POSITION_Y
- ABS_MT_PRESSURE
- ABS_MT_SLOT
- ABS_MT_TOOL_TYPE
- ABS_MT_TOOL_X
- ABS_MT_TOOL_Y
- ABS_MT_TOUCH_MAJOR
- ABS_MT_TOUCH_MINOR
- ABS_MT_TRACKING_ID
- ABS_MT_WIDTH_MAJOR
- ABS_MT_WIDTH_MINOR
- ABS_MULTIFINGER_TAP
- ABS_POS_BITS
- ABS_PRESSURE
- ABS_PRESSURE_REG
- ABS_RESERVED
- ABS_RUDDER
- ABS_RX
- ABS_RY
- ABS_RZ
- ABS_THROTTLE
- ABS_TILT_X
- ABS_TILT_Y
- ABS_TOOL_WIDTH
- ABS_VOLUME
- ABS_VSCROLL_BIT
- ABS_WHEEL
- ABS_X
- ABS_Y
- ABS_Z
- ABT
- ABTA_SENT
- ABTB_SENT
- ABTC_SENT
- ABTD
- ABTD_SENT
- ABTS_CONTR_FLG_TERM_EXCHG
- ABTS_PARAM_ABORT_SEQ
- ABTS_RECV_24XX
- ABTS_RESP_24XX
- ABTS_RESP_COMPL_SUBCODE_ERROR
- ABTS_RESP_COMPL_SUCCESS
- ABTS_RESP_SUBCODE_ERR_ABORTED_EXCH_NOT_TERM
- ABT_MODE
- ABUNDER
- ABURST
- ABURST_MASK
- ABURST_SHIFT
- ABX500_ALT_A
- ABX500_ALT_B
- ABX500_ALT_C
- ABX500_DEFAULT
- ABX500_GPIO
- ABX500_GPIO_INPUT
- ABX500_GPIO_OUTPUT
- ABX500_GPIO_PULL_DOWN
- ABX500_GPIO_PULL_NONE
- ABX500_GPIO_PULL_UP
- ABX500_GPIO_VINSEL_VBAT
- ABX500_GPIO_VINSEL_VDD_BIF
- ABX500_GPIO_VINSEL_VIN_1V8
- ABX500_PINRANGE
- ABX80X
- ABX8XX_CFG_KEY_MISC
- ABX8XX_CFG_KEY_OSC
- ABX8XX_CTRL2_RSVD
- ABX8XX_CTRL_12_24
- ABX8XX_CTRL_ARST
- ABX8XX_CTRL_WRITE
- ABX8XX_IRQ_AIE
- ABX8XX_IRQ_IM_1_4
- ABX8XX_OSC_ACAL_1024
- ABX8XX_OSC_ACAL_512
- ABX8XX_OSC_BOS
- ABX8XX_OSC_FOS
- ABX8XX_OSC_OSEL
- ABX8XX_OSS_OF
- ABX8XX_OSS_OMODE
- ABX8XX_OUT_CTRL_EXDS
- ABX8XX_REG_ADA
- ABX8XX_REG_AHR
- ABX8XX_REG_AHTH
- ABX8XX_REG_AMN
- ABX8XX_REG_AMO
- ABX8XX_REG_ASC
- ABX8XX_REG_AWD
- ABX8XX_REG_CD_TIMER_CTL
- ABX8XX_REG_CFG_KEY
- ABX8XX_REG_CTRL1
- ABX8XX_REG_CTRL2
- ABX8XX_REG_DA
- ABX8XX_REG_HR
- ABX8XX_REG_HTH
- ABX8XX_REG_ID0
- ABX8XX_REG_IRQ
- ABX8XX_REG_MN
- ABX8XX_REG_MO
- ABX8XX_REG_OSC
- ABX8XX_REG_OSS
- ABX8XX_REG_OUT_CTRL
- ABX8XX_REG_SC
- ABX8XX_REG_STATUS
- ABX8XX_REG_TRICKLE
- ABX8XX_REG_WD
- ABX8XX_REG_WDT
- ABX8XX_REG_YR
- ABX8XX_STATUS_AF
- ABX8XX_STATUS_BLF
- ABX8XX_STATUS_WDT
- ABX8XX_TRICKLE_CHARGE_ENABLE
- ABX8XX_TRICKLE_SCHOTTKY_DIODE
- ABX8XX_TRICKLE_STANDARD_DIODE
- ABX8XX_WDT_BMB_MASK
- ABX8XX_WDT_BMB_SHIFT
- ABX8XX_WDT_MAX_TIME
- ABX8XX_WDT_WDS
- ABX8XX_WDT_WRB_1HZ
- ABX8XX_WDT_WRB_MASK
- AB_A17_MARK
- AB_A18_MARK
- AB_A19_MARK
- AB_A20_MARK
- AB_A21_MARK
- AB_A22_MARK
- AB_A23_MARK
- AB_A24_MARK
- AB_A25_MARK
- AB_A26_MARK
- AB_A27_MARK
- AB_A28_MARK
- AB_AD0_MARK
- AB_AD10_MARK
- AB_AD11_MARK
- AB_AD12_MARK
- AB_AD13_MARK
- AB_AD14_MARK
- AB_AD15_MARK
- AB_AD1_MARK
- AB_AD2_MARK
- AB_AD3_MARK
- AB_AD4_MARK
- AB_AD5_MARK
- AB_AD6_MARK
- AB_AD7_MARK
- AB_AD8_MARK
- AB_AD9_MARK
- AB_ADV_MARK
- AB_BEN0_MARK
- AB_BEN1_MARK
- AB_CLK_MARK
- AB_CSB0_MARK
- AB_CSB1_MARK
- AB_CSB2_MARK
- AB_CSB3_MARK
- AB_DATA
- AB_INDX
- AB_IO
- AB_IRQCTL_INT_ENABLE
- AB_IRQCTL_INT_FORCE
- AB_IRQCTL_INT_MODE
- AB_IRQCTL_INT_POLARITY
- AB_IRQCTL_INT_STATUS
- AB_IRQCTL_MAXIRQ
- AB_IRQCTL_SRC_MODE
- AB_IRQCTL_SRC_POLARITY
- AB_OFFL_MODE_CLEAR
- AB_OFFL_MODE_FREEZE
- AB_OFFL_MODE_SET
- AB_RDB_MARK
- AB_REG_BAR_HIGH
- AB_REG_BAR_LOW
- AB_REG_BAR_SB700
- AB_WAIT_MARK
- AB_WRB_MARK
- ABx500_ADC_THERM_BATCTRL
- ABx500_ADC_THERM_BATTEMP
- AC
- AC0CLR
- AC0_BASE_CSR
- AC0_BASE_CSR_RING_REGISTER
- AC0_BE
- AC0_BIT
- AC0_TXPTR_CSR
- AC1
- AC10
- AC100_ADC_APC_CTRL
- AC100_ADC_DAP_ENA
- AC100_ADC_DAP_H_HPF_C
- AC100_ADC_DAP_L_A_T
- AC100_ADC_DAP_L_CTRL
- AC100_ADC_DAP_L_D_T
- AC100_ADC_DAP_L_HPF_C
- AC100_ADC_DAP_L_H_A_C
- AC100_ADC_DAP_L_H_N_A_C
- AC100_ADC_DAP_L_L_A_C
- AC100_ADC_DAP_L_L_N_A_C
- AC100_ADC_DAP_L_STA
- AC100_ADC_DAP_L_T_L
- AC100_ADC_DAP_N_TH
- AC100_ADC_DAP_OPT
- AC100_ADC_DAP_R_A_T
- AC100_ADC_DAP_R_CTRL
- AC100_ADC_DAP_R_D_T
- AC100_ADC_DAP_R_H_A_C
- AC100_ADC_DAP_R_H_N_A_C
- AC100_ADC_DAP_R_L_A_C
- AC100_ADC_DAP_R_L_N_A_C
- AC100_ADC_DAP_R_STA
- AC100_ADC_DAP_R_T_L
- AC100_ADC_DIG_CTRL
- AC100_ADC_SRC
- AC100_ADC_SRC_BST_CTRL
- AC100_ADC_VOL_CTRL
- AC100_ALM_DAY
- AC100_ALM_DAY_MASK
- AC100_ALM_ENABLE_FLAG
- AC100_ALM_HOU
- AC100_ALM_HOU_MASK
- AC100_ALM_INT_ENA
- AC100_ALM_INT_ENABLE
- AC100_ALM_INT_STA
- AC100_ALM_MIN
- AC100_ALM_MIN_MASK
- AC100_ALM_MON
- AC100_ALM_MON_MASK
- AC100_ALM_SEC
- AC100_ALM_SEC_MASK
- AC100_ALM_UPD
- AC100_ALM_UPD_TRIGGER
- AC100_ALM_WEE
- AC100_ALM_WEE_MASK
- AC100_ALM_YEA
- AC100_ALM_YEA_MASK
- AC100_CHIP_AUDIO_RST
- AC100_CLK32K_ANALOG_CTRL
- AC100_CLKOUT_CTRL1
- AC100_CLKOUT_CTRL2
- AC100_CLKOUT_CTRL3
- AC100_CLKOUT_DIV_SHIFT
- AC100_CLKOUT_DIV_WIDTH
- AC100_CLKOUT_EN
- AC100_CLKOUT_MUX_SHIFT
- AC100_CLKOUT_MUX_WIDTH
- AC100_CLKOUT_NUM
- AC100_CLKOUT_PRE_DIV_SHIFT
- AC100_CLKOUT_PRE_DIV_WIDTH
- AC100_DAC_DAP_CTRL
- AC100_DAC_DAP_ENA
- AC100_DAC_DAP_H_E_TH
- AC100_DAC_DAP_H_G_A_T_C
- AC100_DAC_DAP_H_G_D_T_C
- AC100_DAC_DAP_H_G_K
- AC100_DAC_DAP_H_G_OFF
- AC100_DAC_DAP_H_HPF_C
- AC100_DAC_DAP_L_E_TH
- AC100_DAC_DAP_L_G_A_T_C
- AC100_DAC_DAP_L_G_D_T_C
- AC100_DAC_DAP_L_G_K
- AC100_DAC_DAP_L_G_OFF
- AC100_DAC_DAP_L_HPF_C
- AC100_DAC_DAP_L_H_E_A_C
- AC100_DAC_DAP_L_L_E_A_C
- AC100_DAC_DAP_OPT
- AC100_DAC_DAP_R_H_E_A_C
- AC100_DAC_DAP_R_L_E_A_C
- AC100_DAC_DIG_CTRL
- AC100_DAC_MXR_GAIN
- AC100_DAC_MXR_SRC
- AC100_DAC_VOL_CTRL
- AC100_ERPOUT_CTRL
- AC100_HMIC_CTRL1
- AC100_HMIC_CTRL2
- AC100_HMIC_STATUS
- AC100_HPOUT_CTRL
- AC100_I2S1_CLK_CTRL
- AC100_I2S1_MXR_GAIN
- AC100_I2S1_MXR_SRC
- AC100_I2S1_SND_IN_CTRL
- AC100_I2S1_SND_OUT_CTRL
- AC100_I2S1_VOL_CTRL1
- AC100_I2S1_VOL_CTRL2
- AC100_I2S1_VOL_CTRL3
- AC100_I2S1_VOL_CTRL4
- AC100_I2S2_CLK_CTRL
- AC100_I2S2_MXR_GAIN
- AC100_I2S2_MXR_SRC
- AC100_I2S2_SND_IN_CTRL
- AC100_I2S2_SND_OUT_CTRL
- AC100_I2S2_VOL_CTRL1
- AC100_I2S2_VOL_CTRL2
- AC100_I2S2_VOL_CTRL3
- AC100_I2S2_VOL_CTRL4
- AC100_I2S3_CLK_CTRL
- AC100_I2S3_SIG_PATH_CTRL
- AC100_I2S3_SND_IN_CTRL
- AC100_I2S3_SND_OUT_CTRL
- AC100_I2S_SR_CTRL
- AC100_LINEOUT_CTRL
- AC100_MOD_CLK_ENA
- AC100_MOD_RST_CTRL
- AC100_OUT_MXR_DAC_A_CTRL
- AC100_OUT_MXR_SRC
- AC100_OUT_MXR_SRC_BST
- AC100_PLL_CTRL1
- AC100_PLL_CTRL2
- AC100_RTC_32K_NAME
- AC100_RTC_32K_RATE
- AC100_RTC_CTRL
- AC100_RTC_CTRL_24HOUR
- AC100_RTC_DAY
- AC100_RTC_DAY_MASK
- AC100_RTC_GP
- AC100_RTC_HOU
- AC100_RTC_HOU_MASK
- AC100_RTC_MIN
- AC100_RTC_MIN_MASK
- AC100_RTC_MON
- AC100_RTC_MON_MASK
- AC100_RTC_RST
- AC100_RTC_SEC
- AC100_RTC_SEC_MASK
- AC100_RTC_UPD
- AC100_RTC_UPD_TRIGGER
- AC100_RTC_WEE
- AC100_RTC_WEE_MASK
- AC100_RTC_YEA
- AC100_RTC_YEA_LEAP
- AC100_RTC_YEA_MASK
- AC100_SPKOUT_CTRL
- AC100_SRC1_CTRL1
- AC100_SRC1_CTRL2
- AC100_SRC1_CTRL3
- AC100_SRC1_CTRL4
- AC100_SRC2_CTRL1
- AC100_SRC2_CTRL2
- AC100_SRC2_CTRL3
- AC100_SRC2_CTRL4
- AC100_SYSCLK_CTRL
- AC100_YEAR_MAX
- AC100_YEAR_MIN
- AC100_YEAR_OFF
- AC11
- AC12
- AC12_SCLK_SEL
- AC12_V1V8_SIGEN
- AC15
- AC16
- AC17
- AC18
- AC19
- AC1CLR
- AC1_AUTOMATIC_SYNC_ON_OUT_PCI
- AC1_AUTOMATIC_SYNC_ON_THININT
- AC1_BASE_CSR
- AC1_BASE_CSR_RING_REGISTER
- AC1_BIT
- AC1_BK
- AC1_SC_QEBSM_AVAILABLE
- AC1_SC_QEBSM_ENABLED
- AC1_SIGA_INPUT_NEEDED
- AC1_SIGA_OUTPUT_NEEDED
- AC1_SIGA_SYNC_NEEDED
- AC1_TXPTR_CSR
- AC2
- AC22
- AC23
- AC24
- AC26
- AC2UP
- AC2_BASE_CSR
- AC2_BASE_CSR_RING_REGISTER
- AC2_TXPTR_CSR
- AC2_VI
- AC3
- AC3_BASE_CSR
- AC3_BASE_CSR_RING_REGISTER
- AC3_TXPTR_CSR
- AC3_VO
- AC4
- AC5
- AC6
- AC7
- AC8
- AC9
- AC97A
- AC97ADDRESS
- AC97ADDRESS_ADDRESS
- AC97ADDRESS_READY
- AC97CH
- AC97CTL
- AC97C_CAMR
- AC97C_CARCR
- AC97C_CARHR
- AC97C_CARNCR
- AC97C_CARNPR
- AC97C_CARPR
- AC97C_CASR
- AC97C_CATCR
- AC97C_CATHR
- AC97C_CATNCR
- AC97C_CATNPR
- AC97C_CATPR
- AC97C_CHANNEL_A
- AC97C_CHANNEL_NONE
- AC97C_CH_ASSIGN
- AC97C_CH_MASK
- AC97C_CMR_CEM_BIG
- AC97C_CMR_CEM_LITTLE
- AC97C_CMR_CENA
- AC97C_CMR_DMAEN
- AC97C_CMR_SIZE_10
- AC97C_CMR_SIZE_16
- AC97C_CMR_SIZE_18
- AC97C_CMR_SIZE_20
- AC97C_COMR
- AC97C_CORHR
- AC97C_COSR
- AC97C_COTHR
- AC97C_CSR_ENDRX
- AC97C_CSR_ENDTX
- AC97C_CSR_OVRUN
- AC97C_CSR_RXRDY
- AC97C_CSR_TXEMPTY
- AC97C_CSR_TXRDY
- AC97C_CSR_UNRUN
- AC97C_ICA
- AC97C_IDR
- AC97C_IER
- AC97C_IMR
- AC97C_MR
- AC97C_MR_ENA
- AC97C_MR_VRA
- AC97C_MR_WRST
- AC97C_OCA
- AC97C_PTCR
- AC97C_SR
- AC97C_SR_CAEVT
- AC97C_SR_COEVT
- AC97C_SR_SOF
- AC97C_SR_WKUP
- AC97C_VERSION
- AC97D
- AC97DATA
- AC97DR
- AC97EOI
- AC97EOI_CODECREADY
- AC97EOI_WINT
- AC97GCR
- AC97GCR_AC97IFE
- AC97GIS
- AC97IE
- AC97IM
- AC97ISR
- AC97PCR_CLRFIFO
- AC97PCR_START
- AC97PCR_STOP
- AC97RESET
- AC97RESET_TIMEDRESET
- AC97RGIS
- AC97RISR
- AC97RXCR
- AC97RXCR_CM
- AC97RXCR_REN
- AC97RXCR_RX3
- AC97RXCR_RX4
- AC97S12DATA
- AC97S1DATA
- AC97S2DATA
- AC97SLOT
- AC97SLOT_CNTR
- AC97SLOT_LFE
- AC97SLOT_REAR_LEFT
- AC97SLOT_REAR_RIGHT
- AC97SR
- AC97SR_TXFE
- AC97SR_TXUE
- AC97STAT_BUSY
- AC97SYNC
- AC97SYNC_TIMEDSYNC
- AC97TXCR
- AC97TXCR_CM
- AC97TXCR_TEN
- AC97TXCR_TX3
- AC97TXCR_TX4
- AC97_3D_CONTROL
- AC97_ACCESS
- AC97_AD1986_2MIC
- AC97_AD1986_AC97NC
- AC97_AD1986_CLDIS
- AC97_AD1986_CVREF0
- AC97_AD1986_CVREF1
- AC97_AD1986_CVREF2
- AC97_AD1986_CVREF_MASK
- AC97_AD1986_DACZ
- AC97_AD1986_DMIX0
- AC97_AD1986_DMIX1
- AC97_AD1986_GPO
- AC97_AD1986_HPSEL0
- AC97_AD1986_HPSEL1
- AC97_AD1986_JSINVA
- AC97_AD1986_JSINVB
- AC97_AD1986_JSMAP
- AC97_AD1986_LISEL0
- AC97_AD1986_LISEL1
- AC97_AD1986_LISEL_LI
- AC97_AD1986_LISEL_MASK
- AC97_AD1986_LISEL_MIC
- AC97_AD1986_LISEL_SURR
- AC97_AD1986_LOHPEN
- AC97_AD1986_LOSEL
- AC97_AD1986_LVREF0
- AC97_AD1986_LVREF1
- AC97_AD1986_LVREF2
- AC97_AD1986_LVREF_MASK
- AC97_AD1986_MBC
- AC97_AD1986_MBC_10
- AC97_AD1986_MBC_20
- AC97_AD1986_MBC_30
- AC97_AD1986_MMDIS
- AC97_AD1986_MMIX
- AC97_AD1986_MSPLT
- AC97_AD1986_MVREF0
- AC97_AD1986_MVREF1
- AC97_AD1986_MVREF2
- AC97_AD1986_MVREF_MASK
- AC97_AD1986_OMS0
- AC97_AD1986_OMS1
- AC97_AD1986_OMS2
- AC97_AD1986_OMS_C
- AC97_AD1986_OMS_L
- AC97_AD1986_OMS_LC
- AC97_AD1986_OMS_M
- AC97_AD1986_OMS_MASK
- AC97_AD1986_OMS_MC
- AC97_AD1986_OMS_ML
- AC97_AD1986_OMS_MLC
- AC97_AD1986_SODIS
- AC97_AD1986_SOSEL
- AC97_AD1986_SPRD
- AC97_AD1986_SRU
- AC97_AD198X_2MIC
- AC97_AD198X_AC97NC
- AC97_AD198X_CLDIS
- AC97_AD198X_DACZ
- AC97_AD198X_DMIX0
- AC97_AD198X_DMIX1
- AC97_AD198X_HPSEL
- AC97_AD198X_LODIS
- AC97_AD198X_LOSEL
- AC97_AD198X_MBC
- AC97_AD198X_MBC_10
- AC97_AD198X_MBC_20
- AC97_AD198X_MBC_30
- AC97_AD198X_MSPLT
- AC97_AD198X_SPRD
- AC97_AD198X_SRU
- AC97_AD198X_VREFD
- AC97_AD198X_VREFH
- AC97_AD198X_VREF_0
- AC97_AD198X_VREF_MASK
- AC97_AD198X_VREF_SHIFT
- AC97_AD_CODEC_CFG
- AC97_AD_HPFD_SHIFT
- AC97_AD_JACK_SPDIF
- AC97_AD_MISC
- AC97_AD_MISC2
- AC97_AD_MISC3
- AC97_AD_MULTI
- AC97_AD_SERIAL_CFG
- AC97_AD_TEST
- AC97_AD_TEST2
- AC97_AD_VREFD_SHIFT
- AC97_ALC650_CC_MASK
- AC97_ALC650_CC_SHIFT
- AC97_ALC650_CHANNEL_MASK
- AC97_ALC650_CHANNEL_SHIFT
- AC97_ALC650_CLOCK
- AC97_ALC650_CLOCK_ACCURACY
- AC97_ALC650_CLOCK_LOCK
- AC97_ALC650_CLOCK_SHIFT
- AC97_ALC650_COPY
- AC97_ALC650_GPIO_SETUP
- AC97_ALC650_GPIO_STATUS
- AC97_ALC650_L
- AC97_ALC650_LFE_DAC_VOL
- AC97_ALC650_MISC
- AC97_ALC650_MODE
- AC97_ALC650_MODE_SHIFT
- AC97_ALC650_MULTICH
- AC97_ALC650_NAUDIO
- AC97_ALC650_PRE
- AC97_ALC650_PRE_SHIFT
- AC97_ALC650_PRO
- AC97_ALC650_REVISION
- AC97_ALC650_SOUCE_MASK
- AC97_ALC650_SPDIF_INPUT_STATUS1
- AC97_ALC650_SPDIF_INPUT_STATUS2
- AC97_ALC650_SPSR_32K
- AC97_ALC650_SPSR_44K
- AC97_ALC650_SPSR_48K
- AC97_ALC650_SPSR_MASK
- AC97_ALC650_SPSR_SHIFT
- AC97_ALC650_SURR_DAC_VOL
- AC97_ALC650_UNKNOWN1
- AC97_ALC650_UNKNOWN2
- AC97_ALC650_UNKNOWN3
- AC97_ALC650_UNKNOWN4
- AC97_ALC650_V
- AC97_ALC850_JACK_SELECT
- AC97_ALC850_MISC1
- AC97_ALC850_MULTICH
- AC97_AUX
- AC97_BC_16BIT_ADC
- AC97_BC_16BIT_DAC
- AC97_BC_18BIT_ADC
- AC97_BC_18BIT_DAC
- AC97_BC_20BIT_ADC
- AC97_BC_20BIT_DAC
- AC97_BC_3D_TECH_ID_MASK
- AC97_BC_ADC_MASK
- AC97_BC_BASS_TREBLE
- AC97_BC_DAC_MASK
- AC97_BC_DEDICATED_MIC
- AC97_BC_HEADPHONE
- AC97_BC_LOUDNESS
- AC97_BC_RESERVED1
- AC97_BC_SIM_STEREO
- AC97_BUSY
- AC97_BUS_MAX_CODECS
- AC97_BUS_MAX_DEVICES
- AC97_CD
- AC97_CDC
- AC97_CD_INPUT
- AC97_CENTER_LFE_MASTER
- AC97_CFG
- AC97_CHANNEL_MODE_4CH_CTL
- AC97_CHANNEL_MODE_8CH_CTL
- AC97_CHANNEL_MODE_CTL
- AC97_CM9738_VENDOR_CTRL
- AC97_CM9739_MULTI_CHAN
- AC97_CM9739_SPDIF_CTRL
- AC97_CM9739_SPDIF_IN_STATUS
- AC97_CM9761_FUNC
- AC97_CM9761_MULTI_CHAN
- AC97_CM9761_SPDIF_CTRL
- AC97_CM9780_JACK
- AC97_CM9780_MIXER
- AC97_CM9780_MULTI_CHAN
- AC97_CM9780_SIDE
- AC97_CM9780_SPDIF
- AC97_CMDRESP
- AC97_CMD_DISABLE
- AC97_CMD_ENABLE
- AC97_CMD_FCSAMPLE
- AC97_CMD_RESET
- AC97_CMD_VPSAMPLE
- AC97_CODECREADY
- AC97_CODEC_CLASS_REV
- AC97_CODEC_REG
- AC97_CODEC_TEST
- AC97_CODEC_VAL
- AC97_CODEC_WRITECOMPLETE
- AC97_COMPAT_H
- AC97_CONFIG
- AC97_CONTROLLER_H
- AC97_CSR_ACMODE
- AC97_CSR_BDI_STATUS
- AC97_CSR_MISC_CRYSTAL
- AC97_CSR_SERIAL
- AC97_CSR_SPDIF
- AC97_CSR_SPECF_ADDR
- AC97_CSR_SPECF_DATA
- AC97_CS_SPDIF
- AC97_CTL
- AC97_CXR_AUDIO_MISC
- AC97_CXR_COPYRGT
- AC97_CXR_SPDIFEN
- AC97_CXR_SPDIF_AC3
- AC97_CXR_SPDIF_MASK
- AC97_CXR_SPDIF_PCM
- AC97_CX_SPDIF
- AC97_DATA
- AC97_DATA_AVAIL
- AC97_DBL_RATE
- AC97_DEFAULT_POWER_OFF
- AC97_DIR
- AC97_DIV
- AC97_DOUBLE
- AC97_DOUBLE_RATE
- AC97_DRIVER_ID
- AC97_EA_CDAC
- AC97_EA_DRA
- AC97_EA_LDAC
- AC97_EA_MDAC
- AC97_EA_PRI
- AC97_EA_PRJ
- AC97_EA_PRK
- AC97_EA_PRL
- AC97_EA_SDAC
- AC97_EA_SPCV
- AC97_EA_SPDIF
- AC97_EA_SPSA_10_11
- AC97_EA_SPSA_3_4
- AC97_EA_SPSA_6_9
- AC97_EA_SPSA_7_8
- AC97_EA_SPSA_SLOT_MASK
- AC97_EA_SPSA_SLOT_SHIFT
- AC97_EA_VRA
- AC97_EA_VRM
- AC97_EI_ADDR_MASK
- AC97_EI_ADDR_SHIFT
- AC97_EI_AMAP
- AC97_EI_CDAC
- AC97_EI_DACS_SLOT_MASK
- AC97_EI_DACS_SLOT_SHIFT
- AC97_EI_DRA
- AC97_EI_LDAC
- AC97_EI_REV_22
- AC97_EI_REV_23
- AC97_EI_REV_MASK
- AC97_EI_REV_SHIFT
- AC97_EI_SDAC
- AC97_EI_SPDIF
- AC97_EI_VRA
- AC97_EI_VRM
- AC97_EN
- AC97_ENABLE
- AC97_ENUM
- AC97_ENUM_DOUBLE
- AC97_ENUM_SINGLE
- AC97_EVNT
- AC97_EXTENDED_ID
- AC97_EXTENDED_MID
- AC97_EXTENDED_MSTATUS
- AC97_EXTENDED_STATUS
- AC97_FMIC_SWITCH
- AC97_FMTS
- AC97_FUNC_INFO
- AC97_FUNC_SELECT
- AC97_GENERAL_3D
- AC97_GENERAL_LOOPBACK
- AC97_GENERAL_LOUDNESS
- AC97_GENERAL_MIC
- AC97_GENERAL_MONO
- AC97_GENERAL_PCM_OUT
- AC97_GENERAL_PURPOSE
- AC97_GENERAL_STEREO_ENHANCEMENT
- AC97_GPIO_CFG
- AC97_GPIO_LINE12_AC
- AC97_GPIO_LINE12_DC
- AC97_GPIO_LINE12_RS
- AC97_GPIO_LINE1_CID
- AC97_GPIO_LINE1_HL1R
- AC97_GPIO_LINE1_HOHD
- AC97_GPIO_LINE1_LCS
- AC97_GPIO_LINE1_OH
- AC97_GPIO_LINE1_PULSE
- AC97_GPIO_LINE1_RI
- AC97_GPIO_LINE2_CID
- AC97_GPIO_LINE2_HL1R
- AC97_GPIO_LINE2_LCS
- AC97_GPIO_LINE2_OH
- AC97_GPIO_LINE2_PULSE
- AC97_GPIO_LINE2_RI
- AC97_GPIO_POLARITY
- AC97_GPIO_PULL
- AC97_GPIO_RESET
- AC97_GPIO_STATUS
- AC97_GPIO_STICKY
- AC97_GPIO_TXD
- AC97_GPIO_TXFS
- AC97_GPIO_WAKEUP
- AC97_GP_DRSS_1011
- AC97_GP_DRSS_78
- AC97_GP_DRSS_MASK
- AC97_HANDSET_LEVEL
- AC97_HANDSET_RATE
- AC97_HAS_8CH
- AC97_HAS_NO_AUX
- AC97_HAS_NO_CD
- AC97_HAS_NO_MASTER_VOL
- AC97_HAS_NO_MIC
- AC97_HAS_NO_PCM_VOL
- AC97_HAS_NO_PC_BEEP
- AC97_HAS_NO_PHONE
- AC97_HAS_NO_REC_GAIN
- AC97_HAS_NO_STD_PCM
- AC97_HAS_NO_TONE
- AC97_HAS_NO_VIDEO
- AC97_HAS_PC_BEEP
- AC97_HEADPHONE
- AC97_ID
- AC97_ID_AD1819
- AC97_ID_AD1881
- AC97_ID_AD1881A
- AC97_ID_AD1885
- AC97_ID_AD1886
- AC97_ID_AD1886A
- AC97_ID_AD1887
- AC97_ID_AD1980
- AC97_ID_AK4540
- AC97_ID_AK4542
- AC97_ID_ALC100
- AC97_ID_ALC650
- AC97_ID_ALC650D
- AC97_ID_ALC650E
- AC97_ID_ALC650F
- AC97_ID_ALC655
- AC97_ID_ALC658
- AC97_ID_ALC658D
- AC97_ID_ALC850
- AC97_ID_CM9738
- AC97_ID_CM9739
- AC97_ID_CM9761_78
- AC97_ID_CM9761_82
- AC97_ID_CM9761_83
- AC97_ID_CS4201
- AC97_ID_CS4205
- AC97_ID_CS4297A
- AC97_ID_CS4299
- AC97_ID_CS_MASK
- AC97_ID_ST7597
- AC97_ID_STAC9700
- AC97_ID_STAC9704
- AC97_ID_STAC9705
- AC97_ID_STAC9708
- AC97_ID_STAC9721
- AC97_ID_STAC9744
- AC97_ID_STAC9756
- AC97_ID_STAC9758
- AC97_ID_ST_AC97_ID4
- AC97_ID_TR28028
- AC97_ID_VT1616
- AC97_ID_YMF743
- AC97_ID_YMF753
- AC97_INT_CAUSE_GPIO
- AC97_INT_CAUSE_SENSE
- AC97_INT_ENABLE
- AC97_INT_PAGING
- AC97_INT_SENSE
- AC97_INT_STATUS
- AC97_LINE
- AC97_LINE1_LEVEL
- AC97_LINE1_RATE
- AC97_LINE2_LEVEL
- AC97_LINE2_RATE
- AC97_LINK_FRAME
- AC97_MASTER
- AC97_MASTER_MONO
- AC97_MASTER_TONE
- AC97_MEA_ADC1
- AC97_MEA_ADC2
- AC97_MEA_DAC1
- AC97_MEA_DAC2
- AC97_MEA_GPIO
- AC97_MEA_HADC
- AC97_MEA_HDAC
- AC97_MEA_MREF
- AC97_MEA_PRA
- AC97_MEA_PRB
- AC97_MEA_PRC
- AC97_MEA_PRD
- AC97_MEA_PRE
- AC97_MEA_PRF
- AC97_MEA_PRG
- AC97_MEA_PRH
- AC97_MEI_ADDR_MASK
- AC97_MEI_ADDR_SHIFT
- AC97_MEI_CID1
- AC97_MEI_CID2
- AC97_MEI_HANDSET
- AC97_MEI_LINE1
- AC97_MEI_LINE2
- AC97_MIC
- AC97_MISC_AFE
- AC97_MODEM_PATCH
- AC97_MUTE_MASK_MONO
- AC97_MUTE_MASK_STEREO
- AC97_NUM_GPIOS
- AC97_PAGE_1
- AC97_PAGE_MASK
- AC97_PAGE_SINGLE
- AC97_PAGE_SINGLE_VALUE
- AC97_PAGE_VENDOR
- AC97_PCI_SID
- AC97_PCI_SVID
- AC97_PCM
- AC97_PCM_CFG_40
- AC97_PCM_CFG_51
- AC97_PCM_CFG_FRONT
- AC97_PCM_CFG_LFE
- AC97_PCM_CFG_REAR
- AC97_PCM_CFG_SPDIF
- AC97_PCM_FRONT_DAC_RATE
- AC97_PCM_LFE_DAC_RATE
- AC97_PCM_LR_ADC_RATE
- AC97_PCM_MIC_ADC_RATE
- AC97_PCM_SURR_DAC_RATE
- AC97_PCR
- AC97_PC_BEEP
- AC97_PD_ADC_STATUS
- AC97_PD_DAC_STATUS
- AC97_PD_EAPD
- AC97_PD_MIXER_STATUS
- AC97_PD_PR0
- AC97_PD_PR1
- AC97_PD_PR2
- AC97_PD_PR3
- AC97_PD_PR4
- AC97_PD_PR5
- AC97_PD_PR6
- AC97_PD_VREF_STATUS
- AC97_PHONE
- AC97_POWERDOWN
- AC97_RATES
- AC97_RATES_ADC
- AC97_RATES_FRONT_DAC
- AC97_RATES_LFE_DAC
- AC97_RATES_MIC_ADC
- AC97_RATES_SPDIF
- AC97_RATES_SURR_DAC
- AC97_READ
- AC97_READ_RETRY
- AC97_REC_GAIN
- AC97_REC_GAIN_MIC
- AC97_REC_SEL
- AC97_RESET
- AC97_RST
- AC97_RW_RETRIES
- AC97_SCAP_AUDIO
- AC97_SCAP_CENTER_LFE_DAC
- AC97_SCAP_DETECT_BY_VENDOR
- AC97_SCAP_EAPD_LED
- AC97_SCAP_INDEP_SDIN
- AC97_SCAP_INV_EAPD
- AC97_SCAP_MODEM
- AC97_SCAP_NO_SPDIF
- AC97_SCAP_POWER_SAVE
- AC97_SCAP_SKIP_AUDIO
- AC97_SCAP_SKIP_MODEM
- AC97_SCAP_SURROUND_DAC
- AC97_SC_CC_MASK
- AC97_SC_CC_SHIFT
- AC97_SC_COPY
- AC97_SC_DRS
- AC97_SC_L
- AC97_SC_NAUDIO
- AC97_SC_PRE
- AC97_SC_PRO
- AC97_SC_SPSR_32K
- AC97_SC_SPSR_44K
- AC97_SC_SPSR_48K
- AC97_SC_SPSR_MASK
- AC97_SC_SPSR_SHIFT
- AC97_SC_V
- AC97_SENSE_INFO
- AC97_SHUT
- AC97_SI3036_CHIP_ID
- AC97_SI3036_LINE_CFG
- AC97_SIGMATEL_ANALOG
- AC97_SIGMATEL_BIAS1
- AC97_SIGMATEL_BIAS2
- AC97_SIGMATEL_CIC1
- AC97_SIGMATEL_CIC2
- AC97_SIGMATEL_DAC2INVERT
- AC97_SIGMATEL_INSEL
- AC97_SIGMATEL_IOMISC
- AC97_SIGMATEL_MULTICHN
- AC97_SIGMATEL_OUTSEL
- AC97_SIGMATEL_VARIOUS
- AC97_SINGLE
- AC97_SINGLE_VALUE
- AC97_SLOT2RXVALID
- AC97_SLOT2TXCOMPLETE
- AC97_SLOTS_AVAILABLE_ALL
- AC97_SLOT_CMD_ADDR
- AC97_SLOT_CMD_DATA
- AC97_SLOT_HANDSET
- AC97_SLOT_LFE
- AC97_SLOT_MIC
- AC97_SLOT_MODEM_GPIO
- AC97_SLOT_MODEM_LINE1
- AC97_SLOT_MODEM_LINE2
- AC97_SLOT_PCM_CENTER
- AC97_SLOT_PCM_CENTER_1
- AC97_SLOT_PCM_LEFT
- AC97_SLOT_PCM_LEFT_0
- AC97_SLOT_PCM_LEFT_1
- AC97_SLOT_PCM_RIGHT
- AC97_SLOT_PCM_RIGHT_0
- AC97_SLOT_PCM_RIGHT_1
- AC97_SLOT_PCM_SLEFT
- AC97_SLOT_PCM_SRIGHT
- AC97_SLOT_SPDIF_LEFT
- AC97_SLOT_SPDIF_LEFT1
- AC97_SLOT_SPDIF_LEFT2
- AC97_SLOT_SPDIF_RIGHT
- AC97_SLOT_SPDIF_RIGHT1
- AC97_SLOT_SPDIF_RIGHT2
- AC97_SLOT_TAG
- AC97_SPDIF
- AC97_STAC_ANALOG_SPECIAL
- AC97_STAC_DA_CONTROL
- AC97_STAC_STEREO_MIC
- AC97_STAT
- AC97_STATUS
- AC97_STEREO_MUTES
- AC97_SURROUND_JACK_MODE_CTL
- AC97_SURROUND_MASTER
- AC97_SWITCH
- AC97_TIMEOUT
- AC97_TUNE_AD_SHARING
- AC97_TUNE_ALC_JACK
- AC97_TUNE_DEFAULT
- AC97_TUNE_HP_MUTE_LED
- AC97_TUNE_HP_ONLY
- AC97_TUNE_INV_EAPD
- AC97_TUNE_MUTE_LED
- AC97_TUNE_NONE
- AC97_TUNE_SWAP_HP
- AC97_TUNE_SWAP_SURROUND
- AC97_VENDOR_ID1
- AC97_VENDOR_ID2
- AC97_VIDEO
- AC97_VOLUME
- AC97_WM9704_RMIXER_VOL
- AC97_WM9704_RPCM_VOL
- AC97_WM9704_TEST
- AC97_WM9711_OUT3VOL
- AC97_WM9712_POWER
- AC97_WM9712_REV
- AC97_WM9713_DIG1
- AC97_WM9713_DIG2
- AC97_WM9713_DIG3
- AC97_WM97XX_DIGITISER1
- AC97_WM97XX_DIGITISER2
- AC97_WM97XX_DIGITISER_RD
- AC97_WM97XX_FMIXER_VOL
- AC97_WRITE_RETRY
- AC97_YMF7X3_3D_MODE_SEL
- AC97_YMF7X3_DIT_CTRL
- ACA
- ACACHE_KOBJ_ID
- ACARD_AHCI_RX_FIS_SZ
- ACAUDIDAT
- ACAUDODAT
- ACA_ACTIVE
- ACA_ENABLE_COMPLETE_TIME
- ACA_Q
- ACA_TYPE
- ACBADDR
- ACBCST
- ACBCST_BB
- ACBCTL1
- ACBCTL1_ACK
- ACBCTL1_NMINTE
- ACBCTL1_START
- ACBCTL1_STASTRE
- ACBCTL1_STOP
- ACBCTL2
- ACBCTL2_ENABLE
- ACBSDA
- ACBST
- ACBST_BER
- ACBST_MASTER
- ACBST_NEGACK
- ACBST_SDAST
- ACBST_STASTR
- ACB_ADAPTER_TYPE_A
- ACB_ADAPTER_TYPE_B
- ACB_ADAPTER_TYPE_C
- ACB_ADAPTER_TYPE_D
- ACB_ADAPTER_TYPE_E
- ACB_ALGO
- ACB_ALGORITHM
- ACB_CONFIG_DISABLE
- ACB_CONFIG_SET
- ACB_CONTROL
- ACB_EN
- ACB_FLUSH_MASK
- ACB_FLUSH_SHIFT
- ACB_F_ABORT
- ACB_F_ADAPTER_REMOVED
- ACB_F_BUS_RESET
- ACB_F_FIRMWARE_TRAP
- ACB_F_IOPDATA_OVERFLOW
- ACB_F_IOP_INITED
- ACB_F_MESSAGE_RQBUFFER_CLEARED
- ACB_F_MESSAGE_WQBUFFER_CLEARED
- ACB_F_MESSAGE_WQBUFFER_READED
- ACB_F_MSG_GET_CONFIG
- ACB_F_MSG_START_BGRB
- ACB_F_MSG_STOP_BGRB
- ACB_F_SCSISTOPADAPTER
- ACB_NOT_SUPPORTED
- ACB_QUEUE_0_CFG
- ACB_QUEUE_CFG
- ACB_SUPPORTED
- ACCAD2_CI_MASK
- ACCAD2_CI_SHIFT
- ACCAD_CI_MASK
- ACCAD_CI_SHIFT
- ACCC_CHROMA_CB_MASK
- ACCC_CHROMA_CB_SHIFT
- ACCC_CHROMA_CR_MASK
- ACCC_CHROMA_CR_SHIFT
- ACCC_REG
- ACCDA2_CD_MASK
- ACCDA2_CD_SHIFT
- ACCDA_CD_MASK
- ACCDA_CD_SHIFT
- ACCE
- ACCEL
- ACCEL_1
- ACCEL_2
- ACCEL_3
- ACCEL_3D_CHANNEL_MAX
- ACCEL_4
- ACCEL_DEV
- ACCEL_H__
- ACCEL_LEGACY_NSCALE
- ACCEPT
- ACCEPT1_FLAGS
- ACCEPT2_FLAGS
- ACCEPTLERR
- ACCEPT_ACK_FRAMES
- ACCEPT_ALL_ADDRESS
- ACCEPT_BEACON_FRAMES
- ACCEPT_DATA_FRAMES
- ACCEPT_IRQ
- ACCEPT_MACCMD_FRAMES
- ACCEPT_MSG
- ACCEPT_MSG_ATN
- ACCEPT_QUEUE
- ACCEPT_RESERVED_FRAMES
- ACCEPT_TABLE
- ACCEPT_TABLE2
- ACCEPT_TGT_IO_TYPE
- ACCEPT_UNSOLICITED_RESPONSE_ENABLE
- ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE
- ACCESIO_COM4SM_PID
- ACCESS
- ACCESSMODE
- ACCESS_16
- ACCESS_16BIT
- ACCESS_32
- ACCESS_ALLOWED
- ACCESS_ALLOWED_ACE
- ACCESS_ALLOWED_ACE_TYPE
- ACCESS_ALLOWED_CALLBACK_ACE_TYPE
- ACCESS_ALLOWED_CALLBACK_OBJECT_ACE_TYPE
- ACCESS_ALLOWED_COMPOUND_ACE_TYPE
- ACCESS_ALLOWED_OBJECT_ACE
- ACCESS_ALLOWED_OBJECT_ACE_TYPE
- ACCESS_ATTR
- ACCESS_CHIP_IOCB_TYPE
- ACCESS_CONTROL_IN
- ACCESS_CONTROL_OUT
- ACCESS_DENIED
- ACCESS_DENIED_ACE
- ACCESS_DENIED_ACE_TYPE
- ACCESS_DENIED_CALLBACK_ACE_TYPE
- ACCESS_DENIED_CALLBACK_OBJECT_ACE_TYPE
- ACCESS_DENIED_OBJECT_ACE
- ACCESS_DENIED_OBJECT_ACE_TYPE
- ACCESS_ENABLE
- ACCESS_INTR_MASK
- ACCESS_MASK
- ACCESS_MAX_MS_ACE_TYPE
- ACCESS_MAX_MS_OBJECT_ACE_TYPE
- ACCESS_MAX_MS_V2_ACE_TYPE
- ACCESS_MAX_MS_V3_ACE_TYPE
- ACCESS_MAX_MS_V4_ACE_TYPE
- ACCESS_MIN_MS_ACE_TYPE
- ACCESS_MIN_MS_OBJECT_ACE_TYPE
- ACCESS_NO_IRQ_SUSPEND
- ACCESS_PLACEHOLDER
- ACCESS_PORT
- ACCESS_PRIVATE
- ACCESS_READ
- ACCESS_REG
- ACCESS_RO
- ACCESS_RW
- ACCESS_SWAP
- ACCESS_SYSTEM_SECURITY
- ACCESS_TYPE_BYTE
- ACCESS_TYPE_LONG
- ACCESS_TYPE_LONG_AUTO_INCREMENT
- ACCESS_TYPE_WORD
- ACCESS_UNKNOWN
- ACCESS_VIOL_SHIFT
- ACCESS_WO
- ACCESS_WRITE
- ACCESS_WR_ENABLE
- ACCLEN
- ACCOUNT_CPU_USER_ENTRY
- ACCOUNT_CPU_USER_EXIT
- ACCOUNT_GET_STAMP
- ACCOUNT_INTERVAL_SHIFT
- ACCOUNT_STOLEN_TIME
- ACCOUNT_SYS_ENTER
- ACCR
- ACCRC_CHROMA_MASK
- ACCRC_CHROMA_SHIFT
- ACCRC_REG
- ACCR_D0CS
- ACCR_DDR_D0CS
- ACCR_DMCFS
- ACCR_DMCFS_MASK
- ACCR_HSS
- ACCR_HSS_MASK
- ACCR_PCCE
- ACCR_SFLFS
- ACCR_SFLFS_MASK
- ACCR_SMCFS
- ACCR_SMCFS_MASK
- ACCR_SPDIS
- ACCR_XL
- ACCR_XL_MASK
- ACCR_XN
- ACCR_XN_MASK
- ACCR_XPDIS
- ACCR_XSPCLK
- ACCR_XSPCLK_MASK
- ACCTIMING
- ACCTL2_ASYN
- ACCTL2_CRW
- ACCTL2_DCV
- ACCTL2_ESYN
- ACCTL2_RSTN
- ACCTL2_VFRM
- ACCTLDIS
- ACCTLEN
- ACCTL_ASYN
- ACCTL_AUDIDMA
- ACCTL_AUDIEHLT
- ACCTL_AUDODMA
- ACCTL_AUDOEHLT
- ACCTL_CRW
- ACCTL_DCV
- ACCTL_ENLINK
- ACCTL_ESYN
- ACCTL_RSTN
- ACCTL_TC
- ACCTL_VFRM
- ACCTON
- ACCT_BYTEORDER
- ACCT_COMM
- ACCT_TIMEOUT
- ACCT_VERSION
- ACCUM
- ACCUM_LS
- ACCUM_MIDDLE
- ACCUM_MS
- ACCURACY
- ACCURATE_BIT
- ACC_ALL
- ACC_BIT
- ACC_BM0_CMD
- ACC_BM0_PNTR
- ACC_BM0_PRD
- ACC_BM0_STATUS
- ACC_BM1_CMD
- ACC_BM1_PNTR
- ACC_BM1_PRD
- ACC_BM1_STATUS
- ACC_CAP
- ACC_CFG_MULTI_QUEUE
- ACC_CHANNEL_INT_BASE
- ACC_CLKS
- ACC_CLKS__VALUE
- ACC_CLK_SRC
- ACC_CLOCK_OFFSET
- ACC_CMD_DISABLE_CHANNEL
- ACC_CMD_ENABLE_CHANNEL
- ACC_CODEC_CNTL
- ACC_CODEC_CNTL_LNK_SHUTDOWN
- ACC_CODEC_CNTL_LNK_WRM_RST
- ACC_CODEC_CNTL_RD_CMD
- ACC_CODEC_CNTL_WR_CMD
- ACC_CODEC_STATUS
- ACC_CONFIG
- ACC_CONTROL_CACHE_MODE
- ACC_CONTROL_FAST_PGM_RDIN
- ACC_CONTROL_PAGE_HIT
- ACC_CONTROL_PARTIAL_PAGE
- ACC_CONTROL_PREFETCH
- ACC_CONTROL_RD_ECC
- ACC_CONTROL_RD_ERASED
- ACC_CONTROL_WR_ECC
- ACC_CONTROL_WR_PREEMPT
- ACC_CRC
- ACC_DEFAULT_PERIOD
- ACC_DEFER
- ACC_DESCS_MASK
- ACC_DESCS_MAX
- ACC_DETECT1
- ACC_DETECT2
- ACC_DIAG
- ACC_ERROR
- ACC_EXEC_MASK
- ACC_GPIO_STATUS
- ACC_IMMED
- ACC_INTD_OFFSET_COUNT
- ACC_INTD_OFFSET_EOI
- ACC_INTD_OFFSET_STATUS
- ACC_IRQ_STATUS
- ACC_LIST_ENTRY_DESC_IDX
- ACC_LIST_ENTRY_QUEUE_IDX
- ACC_LIST_ENTRY_TYPE
- ACC_LIST_ENTRY_WORDS
- ACC_MAX_CHANNEL
- ACC_MODE
- ACC_MSR_REG
- ACC_MS_ECC_MEM_0_MAX_OFFSET
- ACC_MS_ECC_MEM_0_SECTION
- ACC_MS_ECC_MEM_1_MAX_OFFSET
- ACC_MS_ECC_MEM_1_SECTION
- ACC_MS_ECC_MEM_2_MAX_OFFSET
- ACC_MS_ECC_MEM_2_SECTION
- ACC_MS_ECC_MEM_3_MAX_OFFSET
- ACC_MS_ECC_MEM_3_SECTION
- ACC_PM
- ACC_RET_ACTIVE_CHANNEL
- ACC_RET_IDLE
- ACC_RET_INACTIVE_CHANNEL
- ACC_RET_INVALID_CHANNEL
- ACC_RET_INVALID_COMMAND
- ACC_RET_INVALID_QUEUE
- ACC_RET_INVALID_RET
- ACC_RET_SUCCESS
- ACC_SMI
- ACC_UDP
- ACC_USER_MASK
- ACC_WRITE_MASK
- ACDMASTS
- ACDMA_AUDI
- ACDMA_AUDO
- ACD_BTN_BRIGHT_DOWN
- ACD_BTN_BRIGHT_UP
- ACD_BTN_NONE
- ACD_FLAG_ABORT
- ACD_FLAG_DONE
- ACD_FLAG_ENG_ACCUM_ERROR
- ACD_FLAG_ENG_ACCUM_SHORT
- ACD_MSG_BUFFER_LEN
- ACD_URB_BUFFER_LEN
- ACD_USB_BRIGHTNESS
- ACD_USB_EDID
- ACD_USB_TIMEOUT
- ACE
- ACEB
- ACEECA_MEZ1000_ID
- ACEECA_VENDOR_ID
- ACEN_ACMD23
- ACERHDF_FAN_AUTO
- ACERHDF_FAN_OFF
- ACERHDF_MAX_FANON
- ACERHDF_MAX_INTERVAL
- ACERHDF_TEMP_CRIT
- ACERWMID_EVENT_GUID
- ACER_AMW0
- ACER_AMW0_BLUETOOTH_MASK
- ACER_AMW0_MAILLED_MASK
- ACER_AMW0_V2
- ACER_AMW0_WIRELESS_MASK
- ACER_AMW0_WRITE
- ACER_CAP_ACCEL
- ACER_CAP_ANY
- ACER_CAP_BLUETOOTH
- ACER_CAP_BRIGHTNESS
- ACER_CAP_MAILLED
- ACER_CAP_RFBTN
- ACER_CAP_THREEG
- ACER_CAP_WIRELESS
- ACER_DEFAULT_BLUETOOTH
- ACER_DEFAULT_MAILLED
- ACER_DEFAULT_THREEG
- ACER_DEFAULT_WIRELESS
- ACER_S10_ID
- ACER_VENDOR_ID
- ACER_WMID
- ACER_WMID3_GDS_BLUETOOTH
- ACER_WMID3_GDS_RFBTN
- ACER_WMID3_GDS_THREEG
- ACER_WMID3_GDS_TOUCHPAD
- ACER_WMID3_GDS_WIMAX
- ACER_WMID3_GDS_WIRELESS
- ACER_WMID_GET_BLUETOOTH_METHODID
- ACER_WMID_GET_BRIGHTNESS_METHODID
- ACER_WMID_GET_THREEG_METHODID
- ACER_WMID_GET_WIRELESS_METHODID
- ACER_WMID_SET_BLUETOOTH_METHODID
- ACER_WMID_SET_BRIGHTNESS_METHODID
- ACER_WMID_SET_THREEG_METHODID
- ACER_WMID_SET_WIRELESS_METHODID
- ACER_WMID_v2
- ACE_BUF_PER_SECTOR
- ACE_BUSMODE
- ACE_BUS_WIDTH_16
- ACE_BUS_WIDTH_8
- ACE_BYTE_SWAP_BD
- ACE_BYTE_SWAP_DMA
- ACE_CFGLBA
- ACE_CTRL
- ACE_CTRL_CFGADDR_MASK
- ACE_CTRL_CFGDONEIRQ
- ACE_CTRL_CFGMODE
- ACE_CTRL_CFGPROG
- ACE_CTRL_CFGRESET
- ACE_CTRL_CFGSEL
- ACE_CTRL_CFGSTART
- ACE_CTRL_DATABUFRDYIRQ
- ACE_CTRL_ERRORIRQ
- ACE_CTRL_FORCECFGADDR
- ACE_CTRL_FORCECFGMODE
- ACE_CTRL_FORCELOCKREQ
- ACE_CTRL_LOCKREQ
- ACE_CTRL_RESETIRQ
- ACE_EN
- ACE_ENABLED
- ACE_ERROR
- ACE_FATAL
- ACE_FATSTAT
- ACE_FCR
- ACE_FIFO_SIZE
- ACE_FLAGS
- ACE_FSM_NUM_STATES
- ACE_FSM_NUM_TASKS
- ACE_FSM_STATE_ERROR
- ACE_FSM_STATE_IDENTIFY_COMPLETE
- ACE_FSM_STATE_IDENTIFY_PREPARE
- ACE_FSM_STATE_IDENTIFY_TRANSFER
- ACE_FSM_STATE_IDLE
- ACE_FSM_STATE_REQ_COMPLETE
- ACE_FSM_STATE_REQ_LOCK
- ACE_FSM_STATE_REQ_PREPARE
- ACE_FSM_STATE_REQ_TRANSFER
- ACE_FSM_STATE_WAIT_CFREADY
- ACE_FSM_STATE_WAIT_LOCK
- ACE_HEADER
- ACE_INHERITED_OBJECT_TYPE_PRESENT
- ACE_INVALID_PORT
- ACE_IS_TIGON_I
- ACE_JUMBO_BUFSIZE
- ACE_JUMBO_MTU
- ACE_LITE_PORT
- ACE_LONG_DELAY
- ACE_MAX_MOD_PARMS
- ACE_MINI_BUFSIZE
- ACE_MINI_SIZE
- ACE_MPULBA
- ACE_NO_JUMBO_FRAG
- ACE_NUM_MINORS
- ACE_OBJECT_TYPE_PRESENT
- ACE_PORT
- ACE_PRESENT
- ACE_SECCNTCMD
- ACE_SECCNTCMD_ABORT
- ACE_SECCNTCMD_IDENTIFY
- ACE_SECCNTCMD_READ_DATA
- ACE_SECCNTCMD_RESET
- ACE_SECCNTCMD_WRITE_DATA
- ACE_SECTOR_SIZE
- ACE_SHORT_DELAY
- ACE_STATUS
- ACE_STATUS_CFBSY
- ACE_STATUS_CFCERROR
- ACE_STATUS_CFCORR
- ACE_STATUS_CFDETECT
- ACE_STATUS_CFDRQ
- ACE_STATUS_CFDSC
- ACE_STATUS_CFDWF
- ACE_STATUS_CFERR
- ACE_STATUS_CFGADDR_MASK
- ACE_STATUS_CFGDONE
- ACE_STATUS_CFGERROR
- ACE_STATUS_CFGLOCK
- ACE_STATUS_CFGMODEPIN
- ACE_STATUS_CFRDY
- ACE_STATUS_DATABUFMODE
- ACE_STATUS_DATABUFRDY
- ACE_STATUS_MPULOCK
- ACE_STATUS_RDYFORCFCMD
- ACE_STD_BUFSIZE
- ACE_STD_MTU
- ACE_TASK_IDENTIFY
- ACE_TASK_IDLE
- ACE_TASK_READ
- ACE_TASK_WRITE
- ACE_TRACE_SIZE
- ACE_TX_RING_ENTRIES
- ACE_TYPES
- ACE_VERSION
- ACE_VERSION_MAJOR_MASK
- ACE_VERSION_MINOR_MASK
- ACE_VERSION_REVISION_MASK
- ACE_WARN
- ACE_WINDOW_SIZE
- ACE_WORD_SWAP_BD
- ACF
- ACGPIO_IRQ
- ACH_TXDONE_DELAY_MASK
- ACH_TXDONE_DELAY_SHIFT
- ACIA
- ACIA_BAS
- ACIA_CTS
- ACIA_D7E1S
- ACIA_D7E2S
- ACIA_D7O1S
- ACIA_D7O2S
- ACIA_D8E1S
- ACIA_D8N1S
- ACIA_D8N2S
- ACIA_D8O1S
- ACIA_DCD
- ACIA_DIV1
- ACIA_DIV16
- ACIA_DIV64
- ACIA_FE
- ACIA_IRQ
- ACIA_OVRN
- ACIA_PE
- ACIA_RDRF
- ACIA_RESET
- ACIA_RHTID
- ACIA_RID
- ACIA_RIE
- ACIA_RLTID
- ACIA_RLTIDSB
- ACIA_RLTIE
- ACIA_TDRE
- ACIE
- ACINTDIS
- ACINTEN
- ACINTMSTS
- ACINTSTS
- ACINT_AUDIERR
- ACINT_AUDOERR
- ACINT_CODECRDY
- ACINT_REGACCRDY
- ACISV2_ISV10
- ACISV2_ISV11
- ACISV2_ISV12
- ACISV2_ISV3
- ACISV2_ISV4
- ACISV2_ISV5
- ACISV2_ISV6
- ACISV2_ISV7
- ACISV2_ISV8
- ACISV2_ISV9
- ACISV_ISV10
- ACISV_ISV11
- ACISV_ISV12
- ACISV_ISV3
- ACISV_ISV4
- ACISV_ISV5
- ACISV_ISV6
- ACISV_ISV7
- ACISV_ISV8
- ACISV_ISV9
- ACI_DETECTION_EVENT_ID
- ACI_ERROR_OP
- ACI_GET_CD
- ACI_GET_EQ1
- ACI_GET_EQ2
- ACI_GET_EQ3
- ACI_GET_EQ4
- ACI_GET_EQ5
- ACI_GET_EQ6
- ACI_GET_EQ7
- ACI_GET_LINE
- ACI_GET_LINE1
- ACI_GET_LINE2
- ACI_GET_MASTER
- ACI_GET_MIC
- ACI_GET_PCM
- ACI_GET_PREAMP
- ACI_GET_SYNTH
- ACI_INIT
- ACI_MINTIME
- ACI_READ_IDCODE
- ACI_READ_TUNERSTATION
- ACI_READ_TUNERSTEREO
- ACI_READ_VERSION
- ACI_REG_BUSY
- ACI_REG_COMMAND
- ACI_REG_RDS
- ACI_REG_STATUS
- ACI_SET_CD
- ACI_SET_EQ1
- ACI_SET_EQ2
- ACI_SET_EQ3
- ACI_SET_EQ4
- ACI_SET_EQ5
- ACI_SET_EQ6
- ACI_SET_EQ7
- ACI_SET_IDE
- ACI_SET_LINE
- ACI_SET_LINE1
- ACI_SET_LINE2
- ACI_SET_MASTER
- ACI_SET_MIC
- ACI_SET_MUTE
- ACI_SET_PCM
- ACI_SET_POWERAMP
- ACI_SET_PREAMP
- ACI_SET_SOLOMODE
- ACI_SET_SYNTH
- ACI_SET_TUNERMONO
- ACI_SET_TUNERMUTE
- ACI_SET_WSS
- ACI_STATUS
- ACI_S_GENERAL
- ACI_WRITE_TUNE
- ACK
- ACKCNT0
- ACKCNT1
- ACKCNTLD
- ACKCNT_UP
- ACKD
- ACKE
- ACKENB
- ACKMD_MASK
- ACKNOWLEDGE
- ACKNOWLEDGE_ACK
- ACKNOWLEDGE_NACK
- ACKNOWLEDGE_NONE
- ACKSUMCHECKRD
- ACKTO
- ACKWIDTH
- ACK_BIT
- ACK_BUSY
- ACK_BUSY_A
- ACK_BUSY_B
- ACK_BUSY_X
- ACK_BYTE
- ACK_CLEAR
- ACK_CNA
- ACK_COMPLETE
- ACK_COUNTER
- ACK_COUNTER_CLEAR
- ACK_COUNTER_CLR
- ACK_CX
- ACK_DATA
- ACK_DATA_ERROR
- ACK_DEC
- ACK_DELAY
- ACK_DONE
- ACK_ERROR
- ACK_FIT
- ACK_FLUSH_CTL
- ACK_FR
- ACK_FROM_PC_READY
- ACK_F_ASPM_CTRL_OFF
- ACK_GOOD_MORE_ACKS_TO_COME
- ACK_GOOD_NORMAL
- ACK_H
- ACK_HDR_LEN
- ACK_INT_CLR_REG
- ACK_INT_DIS_REG
- ACK_INT_ENA_REG
- ACK_INT_MSK_REG
- ACK_INT_RAW_REG
- ACK_INT_REQ0
- ACK_INT_REQ1
- ACK_INT_STAT_REG
- ACK_IR_INT
- ACK_L
- ACK_LENGTH_12_CL
- ACK_LENGTH_16_CL
- ACK_LENGTH_20_CL
- ACK_LENGTH_8_CL
- ACK_LINE
- ACK_MASK
- ACK_NAK_TO
- ACK_NONE
- ACK_NOT_DELAY
- ACK_NO_ACK
- ACK_N_FTS
- ACK_N_FTS_MASK
- ACK_PENDING
- ACK_PORT
- ACK_R
- ACK_RATIO_SHIFT
- ACK_RC6_INT
- ACK_RCVD
- ACK_RECV
- ACK_RNR
- ACK_RQST_EN
- ACK_SENT
- ACK_SER
- ACK_SET
- ACK_SIZE
- ACK_TIMEOUT
- ACK_TYPE_ERROR
- ACK_W
- ACK_WAIT_MASK
- ACK_WAIT_SHIFT
- ACK_WIDTH
- ACK_WITH_ERR_RCVD
- ACK_WITH_NO_ERROR
- ACL
- ACL3_getaclargs_sz
- ACL3_getaclres_sz
- ACL3_setaclargs_sz
- ACL3_setaclres_sz
- ACL4_SUPPORT_ALARM_ACL
- ACL4_SUPPORT_ALLOW_ACL
- ACL4_SUPPORT_AUDIT_ACL
- ACL4_SUPPORT_DENY_ACL
- ACLC
- ACLC2S216A
- ACLC2S232A
- ACLC2S28
- ACLC2S2Q
- ACLKRDIV
- ACLKRDIV_MASK
- ACLKRE
- ACLKRPOL
- ACLKXDIV
- ACLKXDIV_MASK
- ACLKXE
- ACLKXPOL
- ACLK_ADB400M_PD_CORE_B
- ACLK_ADB400M_PD_CORE_L
- ACLK_ADMA
- ACLK_AHB2APB_MSCL0P
- ACLK_AHB2APB_MSCL1P
- ACLK_AXI2ACEL_BRIDGE
- ACLK_AXISRAM
- ACLK_AXIUS_USBDRD30X_FSYS0X
- ACLK_AXI_FREQUENCY
- ACLK_BUS
- ACLK_BUS_PRE
- ACLK_BUS_SRC
- ACLK_CCI
- ACLK_CCI_GRF
- ACLK_CCI_NOC0
- ACLK_CCI_NOC1
- ACLK_CCORE_133
- ACLK_CENTER
- ACLK_CENTER_MAIN_NOC
- ACLK_CENTER_PERI_NOC
- ACLK_CIF
- ACLK_CIF0
- ACLK_CIF1
- ACLK_CIF2
- ACLK_CIF3
- ACLK_CORE
- ACLK_CORE_ADB400_CORE_B_2_CCI500
- ACLK_CORE_ADB400_CORE_L_2_CCI500
- ACLK_CPU
- ACLK_CRYPTO
- ACLK_DCF
- ACLK_DMA1
- ACLK_DMA2
- ACLK_DMAC
- ACLK_DMAC0
- ACLK_DMAC0_PERILP
- ACLK_DMAC1
- ACLK_DMAC1_PERILP
- ACLK_DMAC2
- ACLK_DMAC_BUS
- ACLK_DMAC_PERI
- ACLK_EMMC
- ACLK_EMMC_CORE
- ACLK_EMMC_GRF
- ACLK_EMMC_NOC
- ACLK_ENMCORE
- ACLK_G2D
- ACLK_GIC
- ACLK_GIC_ADB400_CORE_B_2_GIC
- ACLK_GIC_ADB400_CORE_L_2_GIC
- ACLK_GIC_ADB400_GIC_2_CORE_B
- ACLK_GIC_ADB400_GIC_2_CORE_L
- ACLK_GIC_NOC
- ACLK_GIC_PRE
- ACLK_GMAC
- ACLK_GMAC_NOC
- ACLK_GPS
- ACLK_GPU
- ACLK_GPU_CFG
- ACLK_GPU_GRF
- ACLK_GPU_MEM
- ACLK_H264
- ACLK_H265
- ACLK_HDCP
- ACLK_HDCP22
- ACLK_HDCP_NOC
- ACLK_HDCP_PRE
- ACLK_HEVC
- ACLK_IEP
- ACLK_IEP_NOC
- ACLK_IEP_PRE
- ACLK_INTMEM
- ACLK_IPP
- ACLK_ISP
- ACLK_ISP0
- ACLK_ISP0_NOC
- ACLK_ISP0_WRAPPER
- ACLK_ISP1
- ACLK_ISP1_NOC
- ACLK_ISP1_WRAPPER
- ACLK_JPEG
- ACLK_LCDC
- ACLK_LCDC0
- ACLK_LCDC1
- ACLK_LH_ASYNC_SI_MSCL_0
- ACLK_LH_ASYNC_SI_MSCL_1
- ACLK_MAC
- ACLK_MAC2IO
- ACLK_MAC2PHY
- ACLK_MMC0
- ACLK_MMC1
- ACLK_MMC2
- ACLK_MMU
- ACLK_MSCLNP_133
- ACLK_MSCL_0
- ACLK_MSCL_1
- ACLK_MSCL_532
- ACLK_PCIE
- ACLK_PDMA0
- ACLK_PDMA1
- ACLK_PERF_CORE_B
- ACLK_PERF_CORE_L
- ACLK_PERF_GMAC
- ACLK_PERF_GPU
- ACLK_PERF_PCIE
- ACLK_PERI
- ACLK_PERIHP
- ACLK_PERIHP_NOC
- ACLK_PERILP0
- ACLK_PERILP0_NOC
- ACLK_PERIS_66
- ACLK_PERI_MMU
- ACLK_PERI_PRE
- ACLK_PERI_SRC
- ACLK_PPMU_MSCL_0
- ACLK_PPMU_MSCL_1
- ACLK_PRE
- ACLK_QE_G2D
- ACLK_QE_JPEG
- ACLK_QE_MSCL_0
- ACLK_QE_MSCL_1
- ACLK_RGA
- ACLK_RGA_NIU
- ACLK_RGA_NOC
- ACLK_RGA_PRE
- ACLK_RKVDEC
- ACLK_RKVDEC_PRE
- ACLK_RKVENC
- ACLK_SMC
- ACLK_TSP
- ACLK_TZMA
- ACLK_UFS20_LINK
- ACLK_USB3
- ACLK_USB3OTG
- ACLK_USB3OTG0
- ACLK_USB3OTG1
- ACLK_USB3_GRF
- ACLK_USB3_NOC
- ACLK_USB3_RKSOC_AXI_PERF
- ACLK_USBDRD300
- ACLK_VCODEC
- ACLK_VCODEC_NOC
- ACLK_VDPU
- ACLK_VDU
- ACLK_VDU_NOC
- ACLK_VEPU
- ACLK_VIDEO
- ACLK_VIO
- ACLK_VIO0
- ACLK_VIO0_NIU
- ACLK_VIO0_NOC
- ACLK_VIO1
- ACLK_VIO1_NIU
- ACLK_VIO1_NOC
- ACLK_VIO_NOC
- ACLK_VIO_PRE
- ACLK_VIP
- ACLK_VI_PRE
- ACLK_VLD
- ACLK_VOP
- ACLK_VOP0
- ACLK_VOP0_NOC
- ACLK_VOP0_PRE
- ACLK_VOP1
- ACLK_VOP1_NOC
- ACLK_VOP1_PRE
- ACLK_VOPB
- ACLK_VOPL
- ACLK_VOP_IEP
- ACLK_VOP_PRE
- ACLK_VO_PRE
- ACLK_VPU
- ACLK_VPU_PRE
- ACLK_XIU_MSCLX_0
- ACLK_XIU_MSCLX_1
- ACLNK2HNDMIC
- ACLNK2MIC
- ACLNK2MODEM0RX
- ACLNK2MODEM1RX
- ACLNK2PADC
- ACLPROC2_ACCESS
- ACLPROC2_GETACL
- ACLPROC2_GETATTR
- ACLPROC2_SETACL
- ACLPROC3_GETACL
- ACLPROC3_SETACL
- ACLRM
- ACL_ACTION_ENABLE
- ACL_ACTION_LEN
- ACL_ACTION_START
- ACL_ACTIVE_BCAST
- ACL_BYTE_ENABLE
- ACL_BYTE_EN_MSB_M
- ACL_CHANGE_INDICATION
- ACL_CNT_M
- ACL_CNT_S
- ACL_COMPLETE
- ACL_CONSTANTS
- ACL_CONT
- ACL_CONTROL_DC
- ACL_CONTROL_DD
- ACL_CONTROL_DI
- ACL_CONTROL_DP
- ACL_CONTROL_DT
- ACL_CONTROL_GD
- ACL_CONTROL_OD
- ACL_CONTROL_PD
- ACL_CONTROL_PS
- ACL_CONTROL_RM
- ACL_CONTROL_SC
- ACL_CONTROL_SD
- ACL_CONTROL_SI
- ACL_CONTROL_SP
- ACL_CONTROL_SR
- ACL_CONTROL_SS
- ACL_DONT_CACHE
- ACL_ENABLE_2_BOTH
- ACL_ENABLE_2_COUNT
- ACL_ENABLE_2_MAC
- ACL_ENABLE_2_TYPE
- ACL_ENABLE_3_IP
- ACL_ENABLE_3_SRC_DST_COMP
- ACL_ENABLE_4_PROTOCOL
- ACL_ENABLE_4_TCP_PORT_COMP
- ACL_ENABLE_4_TCP_SEQN_COMP
- ACL_ENABLE_4_UDP_PORT_COMP
- ACL_ENABLE_M
- ACL_ENABLE_S
- ACL_EQUAL
- ACL_ETH_TYPE
- ACL_EXECUTE
- ACL_FIRST_RULE_M
- ACL_GROUP
- ACL_GROUP_OBJ
- ACL_I
- ACL_INTR_CNT_START
- ACL_INTR_MODE
- ACL_IP_ADDR
- ACL_IP_M
- ACL_LINK
- ACL_MAP_MODE_AND
- ACL_MAP_MODE_DISABLE
- ACL_MAP_MODE_M
- ACL_MAP_MODE_OR
- ACL_MAP_MODE_REPLACE
- ACL_MAP_MODE_S
- ACL_MAP_PORT_M
- ACL_MASK
- ACL_MATCH_ENABLE
- ACL_MAX_PORT
- ACL_MIN_PORT
- ACL_MODE_DISABLE
- ACL_MODE_ENABLE
- ACL_MODE_LAYER_2
- ACL_MODE_LAYER_3
- ACL_MODE_LAYER_4
- ACL_MODE_M
- ACL_MODE_S
- ACL_MSEC_UNIT
- ACL_NOT_CACHED
- ACL_NO_MODE
- ACL_OTHER
- ACL_PICO_BCAST
- ACL_PORT_MAP
- ACL_PORT_MODE_DISABLE
- ACL_PORT_MODE_EITHER
- ACL_PORT_MODE_IN_RANGE
- ACL_PORT_MODE_M
- ACL_PORT_MODE_OUT_OF_RANGE
- ACL_PORT_MODE_S
- ACL_PRIO_M
- ACL_PRIO_MODE_DISABLE
- ACL_PRIO_MODE_HIGHER
- ACL_PRIO_MODE_LOWER
- ACL_PRIO_MODE_M
- ACL_PRIO_MODE_REPLACE
- ACL_PRIO_MODE_S
- ACL_PRIO_S
- ACL_PTYPE_MASK
- ACL_QUERY
- ACL_QUERY_RSP
- ACL_READ
- ACL_RESERVED
- ACL_REVISION
- ACL_REVISION1
- ACL_REVISION2
- ACL_REVISION3
- ACL_REVISION4
- ACL_REVISION_DS
- ACL_RULESET_ENABLE
- ACL_RULESET_LEN
- ACL_RULESET_START
- ACL_SRC
- ACL_START
- ACL_START_NO_FLUSH
- ACL_STATE
- ACL_TABLE_LEN
- ACL_TCP_FLAG
- ACL_TCP_FLAG_ENABLE
- ACL_TCP_FLAG_M
- ACL_TCP_SEQNUM
- ACL_TYPE_ACCESS
- ACL_TYPE_DEFAULT
- ACL_UNDEFINED_ID
- ACL_USER
- ACL_USER_OBJ
- ACL_VLAN_PRIO_HI_M
- ACL_VLAN_PRIO_LO_M
- ACL_VLAN_PRIO_M
- ACL_VLAN_PRIO_REPLACE
- ACL_VLAN_PRIO_S
- ACL_WRITE
- ACL_to_cifs_posix
- ACMAVG
- ACMHWCTRL
- ACMHW_BEQEN
- ACMHW_BEQSTATUS
- ACMHW_HWEN
- ACMHW_VIQEN
- ACMHW_VIQSTATUS
- ACMHW_VOQEN
- ACMHW_VOQSTATUS
- ACM_CTRL_BRK
- ACM_CTRL_DCD
- ACM_CTRL_DSR
- ACM_CTRL_DTR
- ACM_CTRL_FRAMING
- ACM_CTRL_IDX
- ACM_CTRL_OVERRUN
- ACM_CTRL_PARITY
- ACM_CTRL_RI
- ACM_CTRL_RTS
- ACM_DATA_IDX
- ACM_ERROR_DELAY
- ACM_HW_CTRL_BE
- ACM_HW_CTRL_BK
- ACM_HW_CTRL_VI
- ACM_HW_CTRL_VO
- ACM_IAD_IDX
- ACM_MS_PRODUCT_NUM
- ACM_MS_VENDOR_NUM
- ACM_NR
- ACM_NW
- ACM_SACCES_MODE
- ACM_THROTTLED
- ACM_TTY_MAJOR
- ACM_TTY_MINORS
- ACNE
- ACNTL
- ACNTL1
- ACNTL1_PDN_MASK
- ACNTL2
- ACNTL2_PDN_MASK
- ACOMMAND
- ACOMPAT
- ACON1
- ACON2
- ACORE
- ACORN8x8_IDX
- ACORNSCSI_H
- ACOSV2_SLV10
- ACOSV2_SLV11
- ACOSV2_SLV12
- ACOSV2_SLV3
- ACOSV2_SLV4
- ACOSV2_SLV5
- ACOSV2_SLV6
- ACOSV2_SLV7
- ACOSV2_SLV8
- ACOSV2_SLV9
- ACOSV_SLV10
- ACOSV_SLV11
- ACOSV_SLV12
- ACOSV_SLV3
- ACOSV_SLV4
- ACOSV_SLV5
- ACOSV_SLV6
- ACOSV_SLV7
- ACOSV_SLV8
- ACOSV_SLV9
- ACO_CHANGE_CONFIG_PARAM
- ACO_DUMP_MEMORY
- ACO_LOAD_MEMORY
- ACO_REQUEST_INFO
- ACP3x_I2S_MODE
- ACP3x_PHY_BASE_ADDRESS
- ACP3x_POWER_OFF
- ACP3x_POWER_OFF_IN_PROGRESS
- ACP3x_POWER_ON
- ACP3x_POWER_ON_IN_PROGRESS
- ACP3x_REG_END
- ACP3x_REG_START
- ACP3x_SOFT_RESET__SoftResetAudDone_MASK
- ACPI5_VENDOR_BIT
- ACPIBASE
- ACPIBASE_GCS_END
- ACPIBASE_GCS_OFF
- ACPIBASE_GPE_END
- ACPIBASE_GPE_OFF
- ACPIBASE_PMC_END
- ACPIBASE_PMC_OFF
- ACPIBASE_SMI_END
- ACPIBASE_SMI_OFF
- ACPIBASE_TCO_END
- ACPIBASE_TCO_OFF
- ACPICA_COPYRIGHT
- ACPICA_NAME
- ACPICTRL_PMCBASE
- ACPIDMAP_RESET
- ACPIHID_HID_LEN
- ACPIHID_UID_LEN
- ACPI_100NSEC_PER_MSEC
- ACPI_100NSEC_PER_SEC
- ACPI_100NSEC_PER_USEC
- ACPI_16BIT_MASK
- ACPI_1BIT_MASK
- ACPI_20_TABLE_GUID
- ACPI_24BIT_MASK
- ACPI_2BIT_MASK
- ACPI_32BIT_PHYSICAL_ADDRESS
- ACPI_3BIT_MASK
- ACPI_4BIT_MASK
- ACPI_5BIT_MASK
- ACPI_6BIT_MASK
- ACPI_7BIT_MASK
- ACPI_8BIT_MASK
- ACPI_ACCEPTABLE_CONFIGURATION
- ACPI_ACCESS_BIT_WIDTH
- ACPI_ACCESS_BYTE_WIDTH
- ACPI_ACQUIRE_GLOBAL_LOCK
- ACPI_ACTIVE_BOTH
- ACPI_ACTIVE_HIGH
- ACPI_ACTIVE_LOW
- ACPI_ACTUAL_DEBUG
- ACPI_ACTUAL_DEBUG_RAW
- ACPI_AC_CLASS
- ACPI_AC_COMPONENT
- ACPI_AC_DEVICE_NAME
- ACPI_AC_DIR_NAME
- ACPI_AC_FILE_STATE
- ACPI_AC_NOTIFY_STATUS
- ACPI_AC_STATUS_OFFLINE
- ACPI_AC_STATUS_ONLINE
- ACPI_AC_STATUS_UNKNOWN
- ACPI_ADDRESS_FIXED
- ACPI_ADDRESS_NOT_FIXED
- ACPI_ADDRESS_RANGE_ACPI
- ACPI_ADDRESS_RANGE_COUNT
- ACPI_ADDRESS_RANGE_MAX
- ACPI_ADDRESS_RANGE_MEMORY
- ACPI_ADDRESS_RANGE_NVS
- ACPI_ADDRESS_RANGE_RESERVED
- ACPI_ADDRESS_TYPE_BUS_NUMBER_RANGE
- ACPI_ADDRESS_TYPE_IO_RANGE
- ACPI_ADDRESS_TYPE_MEMORY_RANGE
- ACPI_ADDR_HANDLER_DEFAULT_INSTALLED
- ACPI_ADD_PTR
- ACPI_ADR_SPACE_CMOS
- ACPI_ADR_SPACE_DATA_TABLE
- ACPI_ADR_SPACE_EC
- ACPI_ADR_SPACE_FIXED_HARDWARE
- ACPI_ADR_SPACE_GPIO
- ACPI_ADR_SPACE_GSBUS
- ACPI_ADR_SPACE_IPMI
- ACPI_ADR_SPACE_PCI_BAR_TARGET
- ACPI_ADR_SPACE_PCI_CONFIG
- ACPI_ADR_SPACE_PLATFORM_COMM
- ACPI_ADR_SPACE_SMBUS
- ACPI_ADR_SPACE_SYSTEM_IO
- ACPI_ADR_SPACE_SYSTEM_MEMORY
- ACPI_ADXL_PATH
- ACPI_ALLOCATE
- ACPI_ALLOCATE_BUFFER
- ACPI_ALLOCATE_LOCAL_BUFFER
- ACPI_ALLOCATE_ZEROED
- ACPI_ALL_COMPONENTS
- ACPI_ALL_DRIVERS
- ACPI_ALL_NOTIFY
- ACPI_ALL_PACKAGE_ELEMENTS
- ACPI_ALS_CHROMATICITY
- ACPI_ALS_CLASS
- ACPI_ALS_COLOR_TEMP
- ACPI_ALS_DEVICE_NAME
- ACPI_ALS_EVT_BUFFER_SIZE
- ACPI_ALS_EVT_NR_SOURCES
- ACPI_ALS_ILLUMINANCE
- ACPI_ALS_NOTIFY_ILLUMINANCE
- ACPI_ALS_POLLING
- ACPI_ALS_TABLES
- ACPI_ALWAYS_ILLEGAL
- ACPI_AML_BATCH
- ACPI_AML_BATCH_DO
- ACPI_AML_BATCH_READ_LOG
- ACPI_AML_BATCH_WRITE_CMD
- ACPI_AML_BATCH_WRITE_LOG
- ACPI_AML_BUF_ALIGN
- ACPI_AML_BUF_SIZE
- ACPI_AML_BUSY
- ACPI_AML_CLOSED
- ACPI_AML_DO
- ACPI_AML_EXCEPTION
- ACPI_AML_FILE
- ACPI_AML_INTERACTIVE
- ACPI_AML_IN_KERN
- ACPI_AML_IN_USER
- ACPI_AML_KERN
- ACPI_AML_LOG_START
- ACPI_AML_LOG_STOP
- ACPI_AML_OPEN
- ACPI_AML_OPENED
- ACPI_AML_OUT_KERN
- ACPI_AML_OUT_USER
- ACPI_AML_PACKAGE_TYPE1
- ACPI_AML_PACKAGE_TYPE2
- ACPI_AML_PACKAGE_TYPE3
- ACPI_AML_PACKAGE_TYPE4
- ACPI_AML_PROMPT_ROLL
- ACPI_AML_PROMPT_START
- ACPI_AML_PROMPT_STOP
- ACPI_AML_SEC_TICK
- ACPI_AML_SIZE_LARGE
- ACPI_AML_SIZE_SMALL
- ACPI_AML_USEC_PEEK
- ACPI_AML_USER
- ACPI_AMZN_OEM_ID
- ACPI_ANY_BASE
- ACPI_APD_PM
- ACPI_APD_SYSFS
- ACPI_APEI_H
- ACPI_APPLICATION
- ACPI_APP_DEPENDENT_RETURN_VOID
- ACPI_ARRAY_LENGTH
- ACPI_ASCII_MAX
- ACPI_ASCII_ZERO
- ACPI_ASF_SMBUS_PROTOCOLS
- ACPI_ASF_TYPE_ADDRESS
- ACPI_ASF_TYPE_ALERT
- ACPI_ASF_TYPE_BOOT
- ACPI_ASF_TYPE_CONTROL
- ACPI_ASF_TYPE_INFO
- ACPI_ASF_TYPE_RESERVED
- ACPI_ATLAS_CLASS
- ACPI_ATLAS_NAME
- ACPI_ATTR_INDEX_SHOW
- ACPI_ATTR_LABEL_SHOW
- ACPI_BAR
- ACPI_BASE
- ACPI_BASE_ADDR_MASK
- ACPI_BASE_ADDR_OFFSET
- ACPI_BATTERY_ALARM_PRESENT
- ACPI_BATTERY_CAPACITY_VALID
- ACPI_BATTERY_CLASS
- ACPI_BATTERY_COMPONENT
- ACPI_BATTERY_DEVICE_NAME
- ACPI_BATTERY_DIR_NAME
- ACPI_BATTERY_NOTIFY_INFO
- ACPI_BATTERY_NOTIFY_STATUS
- ACPI_BATTERY_NOTIFY_THRESHOLD
- ACPI_BATTERY_POWER_UNIT_MA
- ACPI_BATTERY_QUIRK_DEGRADED_FULL_CHARGE
- ACPI_BATTERY_QUIRK_PERCENTAGE_CAPACITY
- ACPI_BATTERY_QUIRK_THINKPAD_MAH
- ACPI_BATTERY_STATE_CHARGING
- ACPI_BATTERY_STATE_CRITICAL
- ACPI_BATTERY_STATE_DISCHARGING
- ACPI_BATTERY_VALUE_UNKNOWN
- ACPI_BATTERY_XINFO_PRESENT
- ACPI_BAY_HID
- ACPI_BERT_CORRECTABLE
- ACPI_BERT_ERROR_CORRECTABLE
- ACPI_BERT_ERROR_CORRECTED
- ACPI_BERT_ERROR_ENTRY_COUNT
- ACPI_BERT_ERROR_FATAL
- ACPI_BERT_ERROR_NONE
- ACPI_BERT_ERROR_RESERVED
- ACPI_BERT_MULTIPLE_CORRECTABLE
- ACPI_BERT_MULTIPLE_UNCORRECTABLE
- ACPI_BERT_UNCORRECTABLE
- ACPI_BGRT_DISPLAYED
- ACPI_BGRT_ORIENTATION_OFFSET
- ACPI_BINARY_SEMAPHORE
- ACPI_BIOS_CAN_DETECT
- ACPI_BIOS_ERROR
- ACPI_BIOS_ERROR_PREDEFINED
- ACPI_BIOS_EXCEPTION
- ACPI_BIOS_WARNING
- ACPI_BITMASK_ALL_FIXED_STATUS
- ACPI_BITMASK_ARB_DISABLE
- ACPI_BITMASK_BUS_MASTER_RLD
- ACPI_BITMASK_BUS_MASTER_STATUS
- ACPI_BITMASK_GLOBAL_LOCK_ENABLE
- ACPI_BITMASK_GLOBAL_LOCK_RELEASE
- ACPI_BITMASK_GLOBAL_LOCK_STATUS
- ACPI_BITMASK_PCIEXP_WAKE_DISABLE
- ACPI_BITMASK_PCIEXP_WAKE_STATUS
- ACPI_BITMASK_POWER_BUTTON_ENABLE
- ACPI_BITMASK_POWER_BUTTON_STATUS
- ACPI_BITMASK_RT_CLOCK_ENABLE
- ACPI_BITMASK_RT_CLOCK_STATUS
- ACPI_BITMASK_SCI_ENABLE
- ACPI_BITMASK_SLEEP_BUTTON_ENABLE
- ACPI_BITMASK_SLEEP_BUTTON_STATUS
- ACPI_BITMASK_SLEEP_ENABLE
- ACPI_BITMASK_SLEEP_TYPE
- ACPI_BITMASK_TIMER_ENABLE
- ACPI_BITMASK_TIMER_STATUS
- ACPI_BITMASK_WAKE_STATUS
- ACPI_BITPOSITION_ARB_DISABLE
- ACPI_BITPOSITION_BUS_MASTER_RLD
- ACPI_BITPOSITION_BUS_MASTER_STATUS
- ACPI_BITPOSITION_GLOBAL_LOCK_ENABLE
- ACPI_BITPOSITION_GLOBAL_LOCK_RELEASE
- ACPI_BITPOSITION_GLOBAL_LOCK_STATUS
- ACPI_BITPOSITION_PCIEXP_WAKE_DISABLE
- ACPI_BITPOSITION_PCIEXP_WAKE_STATUS
- ACPI_BITPOSITION_POWER_BUTTON_ENABLE
- ACPI_BITPOSITION_POWER_BUTTON_STATUS
- ACPI_BITPOSITION_RT_CLOCK_ENABLE
- ACPI_BITPOSITION_RT_CLOCK_STATUS
- ACPI_BITPOSITION_SCI_ENABLE
- ACPI_BITPOSITION_SLEEP_BUTTON_ENABLE
- ACPI_BITPOSITION_SLEEP_BUTTON_STATUS
- ACPI_BITPOSITION_SLEEP_ENABLE
- ACPI_BITPOSITION_SLEEP_TYPE
- ACPI_BITPOSITION_TIMER_ENABLE
- ACPI_BITPOSITION_TIMER_STATUS
- ACPI_BITPOSITION_WAKE_STATUS
- ACPI_BITREG_ARB_DISABLE
- ACPI_BITREG_BUS_MASTER_RLD
- ACPI_BITREG_BUS_MASTER_STATUS
- ACPI_BITREG_GLOBAL_LOCK_ENABLE
- ACPI_BITREG_GLOBAL_LOCK_RELEASE
- ACPI_BITREG_GLOBAL_LOCK_STATUS
- ACPI_BITREG_MAX
- ACPI_BITREG_PCIEXP_WAKE_DISABLE
- ACPI_BITREG_PCIEXP_WAKE_STATUS
- ACPI_BITREG_POWER_BUTTON_ENABLE
- ACPI_BITREG_POWER_BUTTON_STATUS
- ACPI_BITREG_RT_CLOCK_ENABLE
- ACPI_BITREG_RT_CLOCK_STATUS
- ACPI_BITREG_SCI_ENABLE
- ACPI_BITREG_SLEEP_BUTTON_ENABLE
- ACPI_BITREG_SLEEP_BUTTON_STATUS
- ACPI_BITREG_SLEEP_ENABLE
- ACPI_BITREG_SLEEP_TYPE
- ACPI_BITREG_TIMER_ENABLE
- ACPI_BITREG_TIMER_STATUS
- ACPI_BITREG_WAKE_STATUS
- ACPI_BTYPE_ALL_OBJECTS
- ACPI_BTYPE_ANY
- ACPI_BTYPE_BUFFER
- ACPI_BTYPE_BUFFER_FIELD
- ACPI_BTYPE_COMPUTE_DATA
- ACPI_BTYPE_DATA
- ACPI_BTYPE_DATA_REFERENCE
- ACPI_BTYPE_DDB_HANDLE
- ACPI_BTYPE_DEBUG_OBJECT
- ACPI_BTYPE_DEVICE
- ACPI_BTYPE_DEVICE_OBJECTS
- ACPI_BTYPE_EVENT
- ACPI_BTYPE_FIELD_UNIT
- ACPI_BTYPE_INTEGER
- ACPI_BTYPE_METHOD
- ACPI_BTYPE_MUTEX
- ACPI_BTYPE_NAMED_REFERENCE
- ACPI_BTYPE_OBJECTS_AND_REFS
- ACPI_BTYPE_PACKAGE
- ACPI_BTYPE_POWER
- ACPI_BTYPE_PROCESSOR
- ACPI_BTYPE_REFERENCE_OBJECT
- ACPI_BTYPE_REGION
- ACPI_BTYPE_RESOURCE
- ACPI_BTYPE_STRING
- ACPI_BTYPE_THERMAL
- ACPI_BUS_CLASS
- ACPI_BUS_COMPONENT
- ACPI_BUS_DEVICE_NAME
- ACPI_BUS_DEVICE_TYPE_COUNT
- ACPI_BUS_FILE_ROOT
- ACPI_BUS_HID
- ACPI_BUS_MASTER
- ACPI_BUS_NUMBER_RANGE
- ACPI_BUS_TYPE_DEVICE
- ACPI_BUS_TYPE_ECDT_EC
- ACPI_BUS_TYPE_POWER
- ACPI_BUS_TYPE_POWER_BUTTON
- ACPI_BUS_TYPE_PROCESSOR
- ACPI_BUS_TYPE_SLEEP_BUTTON
- ACPI_BUS_TYPE_THERMAL
- ACPI_BUTTON_CLASS
- ACPI_BUTTON_COMPONENT
- ACPI_BUTTON_DEVICE_NAME_LID
- ACPI_BUTTON_DEVICE_NAME_POWER
- ACPI_BUTTON_DEVICE_NAME_SLEEP
- ACPI_BUTTON_FILE_INFO
- ACPI_BUTTON_FILE_STATE
- ACPI_BUTTON_H
- ACPI_BUTTON_HID_LID
- ACPI_BUTTON_HID_POWER
- ACPI_BUTTON_HID_POWERF
- ACPI_BUTTON_HID_SLEEP
- ACPI_BUTTON_HID_SLEEPF
- ACPI_BUTTON_LID_INIT_IGNORE
- ACPI_BUTTON_LID_INIT_METHOD
- ACPI_BUTTON_LID_INIT_OPEN
- ACPI_BUTTON_NOTIFY_STATUS
- ACPI_BUTTON_SUBCLASS_LID
- ACPI_BUTTON_SUBCLASS_POWER
- ACPI_BUTTON_SUBCLASS_SLEEP
- ACPI_BUTTON_TYPE_LID
- ACPI_BUTTON_TYPE_POWER
- ACPI_BUTTON_TYPE_SLEEP
- ACPI_BUTTON_TYPE_UNKNOWN
- ACPI_CACHABLE_MEMORY
- ACPI_CAST16
- ACPI_CAST32
- ACPI_CAST64
- ACPI_CAST8
- ACPI_CAST_INDIRECT_PTR
- ACPI_CAST_PTHREAD_T
- ACPI_CAST_PTR
- ACPI_CA_DEBUGGER
- ACPI_CA_DISASSEMBLER
- ACPI_CA_SUPPORT_LEVEL
- ACPI_CA_VERSION
- ACPI_CDCK
- ACPI_CHECKSUM_ABORT
- ACPI_CHECK_OK
- ACPI_CHECK_STATUS
- ACPI_CLEAR_BIT
- ACPI_CLEAR_STATUS
- ACPI_CLID
- ACPI_CNTL_EXCEPTION
- ACPI_COMMON_BUFFER_INFO
- ACPI_COMMON_BUILD_TIME
- ACPI_COMMON_DEBUG_MEM_HEADER
- ACPI_COMMON_FIELD_INFO
- ACPI_COMMON_HEADER
- ACPI_COMMON_NOTIFY_INFO
- ACPI_COMMON_SIGNON
- ACPI_COMPANION
- ACPI_COMPANION_SET
- ACPI_COMPARE_NAMESEG
- ACPI_COMPATIBILITY
- ACPI_COMPILER
- ACPI_COMPONENT_DEFAULT
- ACPI_CONSTANT_EVAL_ONLY
- ACPI_CONSUMER
- ACPI_CONTAINER_COMPONENT
- ACPI_CONTROLLER_INITIATED
- ACPI_CONTROL_CONDITIONAL_EXECUTING
- ACPI_CONTROL_NORMAL
- ACPI_CONTROL_PREDICATE_EXECUTING
- ACPI_CONTROL_PREDICATE_FALSE
- ACPI_CONTROL_PREDICATE_TRUE
- ACPI_CONVERTER_ONLY_MEMBERS
- ACPI_COPY_ADDRESS
- ACPI_COPY_FIELD
- ACPI_COPY_NAMESEG
- ACPI_COPY_TYPE_PACKAGE
- ACPI_COPY_TYPE_SIMPLE
- ACPI_CORESIGHT_LINK_MASTER
- ACPI_CORESIGHT_LINK_SLAVE
- ACPI_CREATE_PREDEFINED_TABLE
- ACPI_CSRT_DMA_CHANNEL
- ACPI_CSRT_DMA_CONTROLLER
- ACPI_CSRT_TIMER
- ACPI_CSRT_TYPE_DMA
- ACPI_CSRT_TYPE_INTERRUPT
- ACPI_CSRT_TYPE_TIMER
- ACPI_CSRT_XRUPT_CONTROLLER
- ACPI_CSRT_XRUPT_LINE
- ACPI_CSTATE_FFH
- ACPI_CSTATE_HALT
- ACPI_CSTATE_INTEGER
- ACPI_CSTATE_SYSTEMIO
- ACPI_CX_DESC_LEN
- ACPI_C_STATES_MAX
- ACPI_C_STATE_COUNT
- ACPI_DASM_BUFFER
- ACPI_DASM_CASE
- ACPI_DASM_DEFAULT
- ACPI_DASM_EISAID
- ACPI_DASM_HID_STRING
- ACPI_DASM_IGNORE_SINGLE
- ACPI_DASM_LNOT_PREFIX
- ACPI_DASM_LNOT_SUFFIX
- ACPI_DASM_MATCHOP
- ACPI_DASM_PLD_METHOD
- ACPI_DASM_RESOURCE
- ACPI_DASM_STRING
- ACPI_DASM_SWITCH
- ACPI_DASM_SWITCH_PREDICATE
- ACPI_DASM_UNICODE
- ACPI_DASM_UUID
- ACPI_DATA_TABLE_DISASSEMBLY
- ACPI_DBG2_1394_PORT
- ACPI_DBG2_1394_STANDARD
- ACPI_DBG2_16550_COMPATIBLE
- ACPI_DBG2_16550_SUBSET
- ACPI_DBG2_ARM_DCC
- ACPI_DBG2_ARM_PL011
- ACPI_DBG2_ARM_SBSA_32BIT
- ACPI_DBG2_ARM_SBSA_GENERIC
- ACPI_DBG2_BCM2835
- ACPI_DBG2_NET_PORT
- ACPI_DBG2_SERIAL_PORT
- ACPI_DBG2_USB_EHCI
- ACPI_DBG2_USB_PORT
- ACPI_DBG2_USB_XHCI
- ACPI_DBG_DEPENDENT_RETURN_VOID
- ACPI_DBG_TRACK_ALLOCATIONS
- ACPI_DBR_DEPENDENT_RETURN_OK
- ACPI_DBR_DEPENDENT_RETURN_VOID
- ACPI_DB_ALL
- ACPI_DB_ALLOCATIONS
- ACPI_DB_ALL_EXCEPTIONS
- ACPI_DB_BFIELD
- ACPI_DB_CONSOLE_OUTPUT
- ACPI_DB_DEBUG_OBJECT
- ACPI_DB_DISABLE_OUTPUT
- ACPI_DB_DISPATCH
- ACPI_DB_DUPLICATE_OUTPUT
- ACPI_DB_EVALUATION
- ACPI_DB_EVENTS
- ACPI_DB_EXEC
- ACPI_DB_FUNCTIONS
- ACPI_DB_INFO
- ACPI_DB_INIT
- ACPI_DB_INIT_NAMES
- ACPI_DB_INTERRUPTS
- ACPI_DB_IO
- ACPI_DB_LINE_BUFFER_SIZE
- ACPI_DB_LOAD
- ACPI_DB_MUTEX
- ACPI_DB_NAMES
- ACPI_DB_OBJECTS
- ACPI_DB_OPREGION
- ACPI_DB_OPTIMIZATIONS
- ACPI_DB_PACKAGE
- ACPI_DB_PARSE
- ACPI_DB_PARSE_TREES
- ACPI_DB_READ_METHOD
- ACPI_DB_REDIRECTABLE_OUTPUT
- ACPI_DB_REPAIR
- ACPI_DB_RESOURCES
- ACPI_DB_TABLES
- ACPI_DB_THREADS
- ACPI_DB_TRACE_POINT
- ACPI_DB_USER_REQUESTS
- ACPI_DB_VALUES
- ACPI_DB_WRITE_METHOD
- ACPI_DEBUGGER
- ACPI_DEBUGGER_COMMAND_PROMPT
- ACPI_DEBUGGER_EXECUTE_PROMPT
- ACPI_DEBUGGER_MAX_ARGS
- ACPI_DEBUG_ALL
- ACPI_DEBUG_BUFFER_SIZE
- ACPI_DEBUG_DEFAULT
- ACPI_DEBUG_EXEC
- ACPI_DEBUG_INIT
- ACPI_DEBUG_INITIALIZE
- ACPI_DEBUG_LENGTH_FORMAT
- ACPI_DEBUG_LEVEL
- ACPI_DEBUG_OBJECT
- ACPI_DEBUG_ONLY_MEMBERS
- ACPI_DEBUG_OUTPUT
- ACPI_DEBUG_PARAMETERS
- ACPI_DEBUG_PRINT
- ACPI_DEBUG_PRINT_RAW
- ACPI_DECLARE_PROBE_ENTRY
- ACPI_DECODE_10
- ACPI_DECODE_16
- ACPI_DEFAULT_HANDLER
- ACPI_DEFAULT_PAGE_SIZE
- ACPI_DEFINE_EXCEPTION_TABLE
- ACPI_DEPENDS_ON_VGA
- ACPI_DESC
- ACPI_DESC_TYPE_CACHED
- ACPI_DESC_TYPE_MAX
- ACPI_DESC_TYPE_NAMED
- ACPI_DESC_TYPE_OPERAND
- ACPI_DESC_TYPE_PARSER
- ACPI_DESC_TYPE_STATE
- ACPI_DESC_TYPE_STATE_CONTROL
- ACPI_DESC_TYPE_STATE_NOTIFY
- ACPI_DESC_TYPE_STATE_PACKAGE
- ACPI_DESC_TYPE_STATE_PSCOPE
- ACPI_DESC_TYPE_STATE_RESULT
- ACPI_DESC_TYPE_STATE_RPSCOPE
- ACPI_DESC_TYPE_STATE_THREAD
- ACPI_DESC_TYPE_STATE_UPDATE
- ACPI_DESC_TYPE_STATE_WSCOPE
- ACPI_DESC_TYPE_WALK
- ACPI_DEVFLAG_ATSDIS
- ACPI_DEVFLAG_EXTINT
- ACPI_DEVFLAG_INITPASS
- ACPI_DEVFLAG_LINT0
- ACPI_DEVFLAG_LINT1
- ACPI_DEVFLAG_NMI
- ACPI_DEVFLAG_SYSMGT1
- ACPI_DEVFLAG_SYSMGT2
- ACPI_DEVICE_CLASS
- ACPI_DEVICE_HANDLER_LIST
- ACPI_DEVICE_ID_SCHEME
- ACPI_DEVICE_INITIATED
- ACPI_DEVICE_NOTIFY
- ACPI_DISABLE_ALL_FEATURE_STRINGS
- ACPI_DISABLE_ALL_STRINGS
- ACPI_DISABLE_ALL_VENDOR_STRINGS
- ACPI_DISABLE_EVENT
- ACPI_DISABLE_INTERFACES
- ACPI_DISASM_ONLY_MEMBERS
- ACPI_DISASSEMBLER
- ACPI_DISPATCHER
- ACPI_DISPLAY_INDEX_MASK
- ACPI_DISPLAY_INDEX_SHIFT
- ACPI_DISPLAY_MASK
- ACPI_DISPLAY_OBJECTS
- ACPI_DISPLAY_PORT_ATTACHMENT_MASK
- ACPI_DISPLAY_PORT_ATTACHMENT_SHIFT
- ACPI_DISPLAY_SHORT
- ACPI_DISPLAY_SUMMARY
- ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL
- ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL
- ACPI_DISPLAY_TYPE_MASK
- ACPI_DISPLAY_TYPE_OTHER
- ACPI_DISPLAY_TYPE_SHIFT
- ACPI_DISPLAY_TYPE_TV
- ACPI_DISPLAY_TYPE_VGA
- ACPI_DIV_16
- ACPI_DIV_2
- ACPI_DIV_32
- ACPI_DIV_4
- ACPI_DIV_64_BY_32
- ACPI_DIV_8
- ACPI_DMAR_ALLOW_ALL
- ACPI_DMAR_ALL_PORTS
- ACPI_DMAR_INCLUDE_ALL
- ACPI_DMAR_INTR_REMAP
- ACPI_DMAR_SCOPE_TYPE_BRIDGE
- ACPI_DMAR_SCOPE_TYPE_ENDPOINT
- ACPI_DMAR_SCOPE_TYPE_HPET
- ACPI_DMAR_SCOPE_TYPE_IOAPIC
- ACPI_DMAR_SCOPE_TYPE_NAMESPACE
- ACPI_DMAR_SCOPE_TYPE_NOT_USED
- ACPI_DMAR_SCOPE_TYPE_RESERVED
- ACPI_DMAR_TYPE_HARDWARE_AFFINITY
- ACPI_DMAR_TYPE_HARDWARE_UNIT
- ACPI_DMAR_TYPE_NAMESPACE
- ACPI_DMAR_TYPE_RESERVED
- ACPI_DMAR_TYPE_RESERVED_MEMORY
- ACPI_DMAR_TYPE_ROOT_ATS
- ACPI_DMAR_X2APIC_MODE
- ACPI_DMAR_X2APIC_OPT_OUT
- ACPI_DMA_WIDTH128
- ACPI_DMA_WIDTH16
- ACPI_DMA_WIDTH256
- ACPI_DMA_WIDTH32
- ACPI_DMA_WIDTH64
- ACPI_DMA_WIDTH8
- ACPI_DOCK_HID
- ACPI_DO_DEBUG_PRINT
- ACPI_DO_NOT_WAIT
- ACPI_DO_WHILE0
- ACPI_DRIVER
- ACPI_DRIVER_ALL_NOTIFY_EVENTS
- ACPI_DRTM_ACCESS_ALLOWED
- ACPI_DRTM_AUTHORITY_ORDER
- ACPI_DRTM_ENABLE_GAP_CODE
- ACPI_DRTM_INCOMPLETE_MEASUREMENTS
- ACPI_DRV_NAME
- ACPI_DT_NAMESPACE_HID
- ACPI_DUMP_BUFFER
- ACPI_DUMP_ENTRY
- ACPI_DUMP_OPERANDS
- ACPI_DUMP_PATHNAME
- ACPI_DUMP_STACK_ENTRY
- ACPI_D_STATES_MAX
- ACPI_D_STATE_COUNT
- ACPI_EBDA_PTR_LENGTH
- ACPI_EBDA_PTR_LOCATION
- ACPI_EBDA_WINDOW_SIZE
- ACPI_ECDT_HID
- ACPI_ECKV_METHOD
- ACPI_ECKV_WIFI_DATA_SIZE
- ACPI_EC_BURST_DISABLE
- ACPI_EC_BURST_ENABLE
- ACPI_EC_CLASS
- ACPI_EC_CLEAR_MAX
- ACPI_EC_COMMAND_COMPLETE
- ACPI_EC_COMMAND_POLL
- ACPI_EC_COMMAND_QUERY
- ACPI_EC_COMMAND_READ
- ACPI_EC_COMMAND_WRITE
- ACPI_EC_DELAY
- ACPI_EC_DEVICE_NAME
- ACPI_EC_EVT_TIMING_EVENT
- ACPI_EC_EVT_TIMING_QUERY
- ACPI_EC_EVT_TIMING_STATUS
- ACPI_EC_FILE_INFO
- ACPI_EC_FLAG_BURST
- ACPI_EC_FLAG_CMD
- ACPI_EC_FLAG_IBF
- ACPI_EC_FLAG_OBF
- ACPI_EC_FLAG_SCI
- ACPI_EC_MAX_QUERIES
- ACPI_EC_UDELAY_GLK
- ACPI_EC_UDELAY_POLL
- ACPI_EDGE_SENSITIVE
- ACPI_EINJ_ACTION_RESERVED
- ACPI_EINJ_BEGIN_OPERATION
- ACPI_EINJ_CHECK_BUSY_STATUS
- ACPI_EINJ_END_OPERATION
- ACPI_EINJ_EXECUTE_OPERATION
- ACPI_EINJ_FAILURE
- ACPI_EINJ_FLUSH_CACHELINE
- ACPI_EINJ_GET_COMMAND_STATUS
- ACPI_EINJ_GET_ERROR_TYPE
- ACPI_EINJ_GET_EXECUTE_TIMINGS
- ACPI_EINJ_GET_TRIGGER_TABLE
- ACPI_EINJ_INSTRUCTION_RESERVED
- ACPI_EINJ_INVALID_ACCESS
- ACPI_EINJ_MEMORY_CORRECTABLE
- ACPI_EINJ_MEMORY_FATAL
- ACPI_EINJ_MEMORY_UNCORRECTABLE
- ACPI_EINJ_NOOP
- ACPI_EINJ_PCIX_CORRECTABLE
- ACPI_EINJ_PCIX_FATAL
- ACPI_EINJ_PCIX_UNCORRECTABLE
- ACPI_EINJ_PLATFORM_CORRECTABLE
- ACPI_EINJ_PLATFORM_FATAL
- ACPI_EINJ_PLATFORM_UNCORRECTABLE
- ACPI_EINJ_PRESERVE
- ACPI_EINJ_PROCESSOR_CORRECTABLE
- ACPI_EINJ_PROCESSOR_FATAL
- ACPI_EINJ_PROCESSOR_UNCORRECTABLE
- ACPI_EINJ_READ_REGISTER
- ACPI_EINJ_READ_REGISTER_VALUE
- ACPI_EINJ_SET_ERROR_TYPE
- ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS
- ACPI_EINJ_STATUS_RESERVED
- ACPI_EINJ_SUCCESS
- ACPI_EINJ_TRIGGER_ERROR
- ACPI_EINJ_VENDOR_DEFINED
- ACPI_EINJ_WRITE_REGISTER
- ACPI_EINJ_WRITE_REGISTER_VALUE
- ACPI_EISAID_STRING_SIZE
- ACPI_ENABLE_ALL_FEATURE_STRINGS
- ACPI_ENABLE_ALL_STRINGS
- ACPI_ENABLE_ALL_VENDOR_STRINGS
- ACPI_ENABLE_EVENT
- ACPI_ENABLE_INTERFACES
- ACPI_END
- ACPI_ENTIRE_RANGE
- ACPI_ENTRY_NOT_FOUND
- ACPI_ENV_EXCEPTION
- ACPI_ERROR
- ACPI_ERROR_METHOD
- ACPI_ERROR_NAMESPACE
- ACPI_ERROR_ONLY
- ACPI_ERST_ACTION_RESERVED
- ACPI_ERST_ADD
- ACPI_ERST_ADD_VALUE
- ACPI_ERST_BEGIN_CLEAR
- ACPI_ERST_BEGIN_DUMMY_WRIITE
- ACPI_ERST_BEGIN_READ
- ACPI_ERST_BEGIN_WRITE
- ACPI_ERST_CHECK_BUSY_STATUS
- ACPI_ERST_END
- ACPI_ERST_EXECUTE_OPERATION
- ACPI_ERST_EXECUTE_TIMINGS
- ACPI_ERST_FAILURE
- ACPI_ERST_GET_COMMAND_STATUS
- ACPI_ERST_GET_ERROR_ATTRIBUTES
- ACPI_ERST_GET_ERROR_LENGTH
- ACPI_ERST_GET_ERROR_RANGE
- ACPI_ERST_GET_RECORD_COUNT
- ACPI_ERST_GET_RECORD_ID
- ACPI_ERST_GOTO
- ACPI_ERST_INSTRUCTION_RESERVED
- ACPI_ERST_LOAD_VAR1
- ACPI_ERST_LOAD_VAR2
- ACPI_ERST_MOVE_DATA
- ACPI_ERST_NOOP
- ACPI_ERST_NOT_AVAILABLE
- ACPI_ERST_NOT_FOUND
- ACPI_ERST_NOT_USED
- ACPI_ERST_NO_SPACE
- ACPI_ERST_PRESERVE
- ACPI_ERST_READ_REGISTER
- ACPI_ERST_READ_REGISTER_VALUE
- ACPI_ERST_RECORD_EMPTY
- ACPI_ERST_SET_DST_ADDRESS_BASE
- ACPI_ERST_SET_RECORD_ID
- ACPI_ERST_SET_RECORD_OFFSET
- ACPI_ERST_SET_SRC_ADDRESS_BASE
- ACPI_ERST_SKIP_NEXT_IF_TRUE
- ACPI_ERST_STALL
- ACPI_ERST_STALL_WHILE_TRUE
- ACPI_ERST_STATUS_RESERVED
- ACPI_ERST_STORE_VAR1
- ACPI_ERST_SUBTRACT
- ACPI_ERST_SUBTRACT_VALUE
- ACPI_ERST_SUCESS
- ACPI_ERST_WRITE_REGISTER
- ACPI_ERST_WRITE_REGISTER_VALUE
- ACPI_EVENTS
- ACPI_EVENT_FLAG_DISABLED
- ACPI_EVENT_FLAG_ENABLED
- ACPI_EVENT_FLAG_ENABLE_SET
- ACPI_EVENT_FLAG_HAS_HANDLER
- ACPI_EVENT_FLAG_MASKED
- ACPI_EVENT_FLAG_SET
- ACPI_EVENT_FLAG_STATUS_SET
- ACPI_EVENT_FLAG_WAKE_ENABLED
- ACPI_EVENT_GLOBAL
- ACPI_EVENT_MAX
- ACPI_EVENT_PMTIMER
- ACPI_EVENT_POWER_BUTTON
- ACPI_EVENT_RTC
- ACPI_EVENT_SLEEP_BUTTON
- ACPI_EVENT_TYPE_FIXED
- ACPI_EVENT_TYPE_GPE
- ACPI_EV_DISPLAY_SWITCH
- ACPI_EV_DOCK
- ACPI_EV_LID
- ACPI_EWRD_METHOD
- ACPI_EWRD_WIFI_DATA_SIZE
- ACPI_EXAMPLE
- ACPI_EXCEPTION
- ACPI_EXCLUSIVE
- ACPI_EXD_ADDRESS
- ACPI_EXD_BUFFER
- ACPI_EXD_FIELD
- ACPI_EXD_HDLR_LIST
- ACPI_EXD_INIT
- ACPI_EXD_LIST
- ACPI_EXD_LITERAL
- ACPI_EXD_NODE
- ACPI_EXD_NSOFFSET
- ACPI_EXD_OFFSET
- ACPI_EXD_PACKAGE
- ACPI_EXD_POINTER
- ACPI_EXD_REFERENCE
- ACPI_EXD_RGN_LIST
- ACPI_EXD_STRING
- ACPI_EXD_TABLE_SIZE
- ACPI_EXD_TYPE
- ACPI_EXD_UINT16
- ACPI_EXD_UINT32
- ACPI_EXD_UINT64
- ACPI_EXD_UINT8
- ACPI_EXECUTER
- ACPI_EXPLICIT_BYTE_COPY
- ACPI_EXPLICIT_CONVERT_DECIMAL
- ACPI_EXPLICIT_CONVERT_HEX
- ACPI_EXPORT_SYMBOL
- ACPI_EXPORT_SYMBOL_INIT
- ACPI_EXTERNAL_RETURN_OK
- ACPI_EXTERNAL_RETURN_PTR
- ACPI_EXTERNAL_RETURN_STATUS
- ACPI_EXTERNAL_RETURN_UINT32
- ACPI_EXTERNAL_RETURN_VOID
- ACPI_EXTERNAL_XFACE
- ACPI_EXTRACT_1BIT_FLAG
- ACPI_EXTRACT_2BIT_FLAG
- ACPI_EXTRACT_3BIT_FLAG
- ACPI_EXTRACT_4BIT_FLAG
- ACPI_EXT_CONFLICTING_DECLARATION
- ACPI_EXT_EXTERNAL_EMITTED
- ACPI_EXT_INTERNAL_PATH_ALLOCATED
- ACPI_EXT_ORIGIN_FROM_FILE
- ACPI_EXT_ORIGIN_FROM_OPCODE
- ACPI_EXT_RESOLVED_REFERENCE
- ACPI_FACS_64BIT_ENVIRONMENT
- ACPI_FACS_64BIT_WAKE
- ACPI_FACS_S4_BIOS_PRESENT
- ACPI_FADT_32BIT_TIMER
- ACPI_FADT_8042
- ACPI_FADT_APIC_CLUSTER
- ACPI_FADT_APIC_PHYSICAL
- ACPI_FADT_C1_SUPPORTED
- ACPI_FADT_C2_MP_SUPPORTED
- ACPI_FADT_CONFORMANCE
- ACPI_FADT_DOCKING_SUPPORTED
- ACPI_FADT_FIXED_RTC
- ACPI_FADT_GPE_REGISTER
- ACPI_FADT_HEADLESS
- ACPI_FADT_HW_REDUCED
- ACPI_FADT_INFO_ENTRIES
- ACPI_FADT_LEGACY_DEVICES
- ACPI_FADT_LOW_POWER_S0
- ACPI_FADT_NO_ASPM
- ACPI_FADT_NO_CMOS_RTC
- ACPI_FADT_NO_MSI
- ACPI_FADT_NO_VGA
- ACPI_FADT_OFFSET
- ACPI_FADT_OPTIONAL
- ACPI_FADT_PCI_EXPRESS_WAKE
- ACPI_FADT_PLATFORM_CLOCK
- ACPI_FADT_PM_INFO_ENTRIES
- ACPI_FADT_POWER_BUTTON
- ACPI_FADT_PSCI_COMPLIANT
- ACPI_FADT_PSCI_USE_HVC
- ACPI_FADT_REMOTE_POWER_ON
- ACPI_FADT_REQUIRED
- ACPI_FADT_RESET_REGISTER
- ACPI_FADT_S4_RTC_VALID
- ACPI_FADT_S4_RTC_WAKE
- ACPI_FADT_SEALED_CASE
- ACPI_FADT_SEPARATE_LENGTH
- ACPI_FADT_SLEEP_BUTTON
- ACPI_FADT_SLEEP_TYPE
- ACPI_FADT_V1_SIZE
- ACPI_FADT_V2_SIZE
- ACPI_FADT_V3_SIZE
- ACPI_FADT_V5_SIZE
- ACPI_FADT_V6_SIZE
- ACPI_FADT_WBINVD
- ACPI_FADT_WBINVD_FLUSH
- ACPI_FAILURE
- ACPI_FAN_COMPONENT
- ACPI_FDE_BYTE_BUFFER_SIZE
- ACPI_FDE_DWORD_BUFFER_SIZE
- ACPI_FDE_FIELD_COUNT
- ACPI_FEATURE_STRINGS
- ACPI_FIELD_BYTE_GRANULARITY
- ACPI_FIELD_DWORD_GRANULARITY
- ACPI_FIELD_QWORD_GRANULARITY
- ACPI_FIELD_WORD_GRANULARITY
- ACPI_FILE
- ACPI_FILE_ERR
- ACPI_FILE_OUT
- ACPI_FIND_FIRST_BIT_16
- ACPI_FIND_FIRST_BIT_32
- ACPI_FIND_FIRST_BIT_64
- ACPI_FIND_FIRST_BIT_8
- ACPI_FIND_LAST_BIT_16
- ACPI_FIND_LAST_BIT_32
- ACPI_FIND_LAST_BIT_64
- ACPI_FIND_LAST_BIT_8
- ACPI_FIXED_HARDWARE_EVENT
- ACPI_FIXED_LENGTH
- ACPI_FLUSH_CPU_CACHE
- ACPI_FORMAT_LEFT
- ACPI_FORMAT_PREFIX
- ACPI_FORMAT_SIGN
- ACPI_FORMAT_SIGN_PLUS
- ACPI_FORMAT_SIGN_PLUS_SPACE
- ACPI_FORMAT_UINT64
- ACPI_FORMAT_UPPER
- ACPI_FORMAT_ZERO
- ACPI_FPDT_BOOT_PERFORMANCE
- ACPI_FPDT_TYPE_BOOT
- ACPI_FPDT_TYPE_S3PERF
- ACPI_FREE
- ACPI_FUJITSU_BL_DEVICE_NAME
- ACPI_FUJITSU_BL_DRIVER_NAME
- ACPI_FUJITSU_BL_HID
- ACPI_FUJITSU_CLASS
- ACPI_FUJITSU_LAPTOP_DEVICE_NAME
- ACPI_FUJITSU_LAPTOP_DRIVER_NAME
- ACPI_FUJITSU_LAPTOP_HID
- ACPI_FUJITSU_NOTIFY_CODE
- ACPI_FULL_DEBUG
- ACPI_FULL_INITIALIZATION
- ACPI_FULL_PATHNAME
- ACPI_FULL_PATHNAME_NO_TRAILING
- ACPI_FUNCTION_ENTRY
- ACPI_FUNCTION_NAME
- ACPI_FUNCTION_TRACE
- ACPI_FUNCTION_TRACE_PTR
- ACPI_FUNCTION_TRACE_STR
- ACPI_FUNCTION_TRACE_U32
- ACPI_GENERIC_NOTIFY_MAX
- ACPI_GENL_ATTR_EVENT
- ACPI_GENL_ATTR_MAX
- ACPI_GENL_ATTR_UNSPEC
- ACPI_GENL_CMD_EVENT
- ACPI_GENL_CMD_MAX
- ACPI_GENL_CMD_UNSPEC
- ACPI_GENL_FAMILY_NAME
- ACPI_GENL_MCAST_GROUP_NAME
- ACPI_GENL_VERSION
- ACPI_GEO_PER_CHAIN_SIZE
- ACPI_GEO_TABLE_SIZE
- ACPI_GET16
- ACPI_GET32
- ACPI_GET64
- ACPI_GET8
- ACPI_GET_1BIT_FLAG
- ACPI_GET_2BIT_FLAG
- ACPI_GET_3BIT_FLAG
- ACPI_GET_4BIT_FLAG
- ACPI_GET_ALL_TABLES
- ACPI_GET_BITS
- ACPI_GET_DESCRIPTOR_PTR
- ACPI_GET_DESCRIPTOR_TYPE
- ACPI_GET_FUNCTION_NAME
- ACPI_GET_ONLY_AML_TABLES
- ACPI_GICV2_DIST_MEM_SIZE
- ACPI_GICV2_VCPU_MEM_SIZE
- ACPI_GICV2_VCTRL_MEM_SIZE
- ACPI_GICV3_DIST_MEM_SIZE
- ACPI_GICV3_ITS_MEM_SIZE
- ACPI_GIC_CPU_IF_MEM_SIZE
- ACPI_GLOBAL
- ACPI_GLOBAL_LOCK
- ACPI_GLOCK_OWNED
- ACPI_GLOCK_PENDING
- ACPI_GLUE_DEBUG
- ACPI_GOOD_CONFIGURATION
- ACPI_GPE0_BLK
- ACPI_GPE_AUTO_ENABLED
- ACPI_GPE_CAN_WAKE
- ACPI_GPE_CONDITIONAL_ENABLE
- ACPI_GPE_DISABLE
- ACPI_GPE_DISPATCH_HANDLER
- ACPI_GPE_DISPATCH_MASK
- ACPI_GPE_DISPATCH_METHOD
- ACPI_GPE_DISPATCH_NONE
- ACPI_GPE_DISPATCH_NOTIFY
- ACPI_GPE_DISPATCH_RAW_HANDLER
- ACPI_GPE_DISPATCH_TYPE
- ACPI_GPE_EDGE_TRIGGERED
- ACPI_GPE_ENABLE
- ACPI_GPE_INITIALIZED
- ACPI_GPE_IS_POLLING_NEEDED
- ACPI_GPE_LEVEL_TRIGGERED
- ACPI_GPE_REGISTER_WIDTH
- ACPI_GPE_XRUPT_TYPE_MASK
- ACPI_GPIO_QUIRK_NO_IO_RESTRICTION
- ACPI_GPIO_QUIRK_ONLY_GPIOIO
- ACPI_GSB_ACCESS_ATTRIB_BLOCK
- ACPI_GSB_ACCESS_ATTRIB_BLOCK_CALL
- ACPI_GSB_ACCESS_ATTRIB_BYTE
- ACPI_GSB_ACCESS_ATTRIB_MULTIBYTE
- ACPI_GSB_ACCESS_ATTRIB_QUICK
- ACPI_GSB_ACCESS_ATTRIB_RAW_BYTES
- ACPI_GSB_ACCESS_ATTRIB_RAW_PROCESS
- ACPI_GSB_ACCESS_ATTRIB_SEND_RCV
- ACPI_GSB_ACCESS_ATTRIB_WORD
- ACPI_GSB_ACCESS_ATTRIB_WORD_CALL
- ACPI_GTDT_ALWAYS_ON
- ACPI_GTDT_GT_ALWAYS_ON
- ACPI_GTDT_GT_IRQ_MODE
- ACPI_GTDT_GT_IRQ_POLARITY
- ACPI_GTDT_GT_IS_SECURE_TIMER
- ACPI_GTDT_INTERRUPT_MODE
- ACPI_GTDT_INTERRUPT_POLARITY
- ACPI_GTDT_TYPE_RESERVED
- ACPI_GTDT_TYPE_TIMER_BLOCK
- ACPI_GTDT_TYPE_WATCHDOG
- ACPI_GTDT_WATCHDOG_IRQ_MODE
- ACPI_GTDT_WATCHDOG_IRQ_POLARITY
- ACPI_GTDT_WATCHDOG_SECURE
- ACPI_HANDLE
- ACPI_HANDLER_NAME_STRING
- ACPI_HANDLER_NOT_PRESENT_STRING
- ACPI_HANDLER_PRESENT_STRING
- ACPI_HANDLER_PRESENT_STRING2
- ACPI_HANDLE_FWNODE
- ACPI_HARDWARE
- ACPI_HAVE_ARCH_GET_ROOT_POINTER
- ACPI_HAVE_ARCH_SET_ROOT_POINTER
- ACPI_HEADER_SIZE
- ACPI_HED_H
- ACPI_HEST_BUS
- ACPI_HEST_CORRECTABLE
- ACPI_HEST_ERROR_ENTRY_COUNT
- ACPI_HEST_ERR_THRESHOLD_VALUE
- ACPI_HEST_ERR_THRESHOLD_WINDOW
- ACPI_HEST_FIRMWARE_FIRST
- ACPI_HEST_GEN_ERROR_CORRECTED
- ACPI_HEST_GEN_ERROR_FATAL
- ACPI_HEST_GEN_ERROR_NONE
- ACPI_HEST_GEN_ERROR_RECOVERABLE
- ACPI_HEST_GEN_VALID_FRU_ID
- ACPI_HEST_GEN_VALID_FRU_STRING
- ACPI_HEST_GEN_VALID_TIMESTAMP
- ACPI_HEST_GHES_ASSIST
- ACPI_HEST_GLOBAL
- ACPI_HEST_MULTIPLE_CORRECTABLE
- ACPI_HEST_MULTIPLE_UNCORRECTABLE
- ACPI_HEST_NOTIFY_CMCI
- ACPI_HEST_NOTIFY_EXTERNAL
- ACPI_HEST_NOTIFY_GPIO
- ACPI_HEST_NOTIFY_GSIV
- ACPI_HEST_NOTIFY_LOCAL
- ACPI_HEST_NOTIFY_MCE
- ACPI_HEST_NOTIFY_NMI
- ACPI_HEST_NOTIFY_POLLED
- ACPI_HEST_NOTIFY_RESERVED
- ACPI_HEST_NOTIFY_SCI
- ACPI_HEST_NOTIFY_SEA
- ACPI_HEST_NOTIFY_SEI
- ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED
- ACPI_HEST_POLL_INTERVAL
- ACPI_HEST_POLL_THRESHOLD_VALUE
- ACPI_HEST_POLL_THRESHOLD_WINDOW
- ACPI_HEST_SEGMENT
- ACPI_HEST_TYPE
- ACPI_HEST_TYPE_AER_BRIDGE
- ACPI_HEST_TYPE_AER_ENDPOINT
- ACPI_HEST_TYPE_AER_ROOT_PORT
- ACPI_HEST_TYPE_GENERIC_ERROR
- ACPI_HEST_TYPE_GENERIC_ERROR_V2
- ACPI_HEST_TYPE_IA32_CHECK
- ACPI_HEST_TYPE_IA32_CORRECTED_CHECK
- ACPI_HEST_TYPE_IA32_DEFERRED_CHECK
- ACPI_HEST_TYPE_IA32_NMI
- ACPI_HEST_TYPE_NOT_USED3
- ACPI_HEST_TYPE_NOT_USED4
- ACPI_HEST_TYPE_NOT_USED5
- ACPI_HEST_TYPE_RESERVED
- ACPI_HEST_UNCORRECTABLE
- ACPI_HIBYTE
- ACPI_HIDWORD
- ACPI_HIWORD
- ACPI_HI_RSDP_WINDOW_BASE
- ACPI_HI_RSDP_WINDOW_SIZE
- ACPI_HMAT_1ST_LEVEL_CACHE
- ACPI_HMAT_2ND_LEVEL_CACHE
- ACPI_HMAT_3RD_LEVEL_CACHE
- ACPI_HMAT_ACCESS_BANDWIDTH
- ACPI_HMAT_ACCESS_LATENCY
- ACPI_HMAT_CACHE_ASSOCIATIVITY
- ACPI_HMAT_CACHE_LEVEL
- ACPI_HMAT_CACHE_LINE_SIZE
- ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING
- ACPI_HMAT_CA_DIRECT_MAPPED
- ACPI_HMAT_CA_NONE
- ACPI_HMAT_CP_NONE
- ACPI_HMAT_CP_WB
- ACPI_HMAT_CP_WT
- ACPI_HMAT_LAST_LEVEL_CACHE
- ACPI_HMAT_MEMORY
- ACPI_HMAT_MEMORY_HIERARCHY
- ACPI_HMAT_MEMORY_PD_VALID
- ACPI_HMAT_PROCESSOR_PD_VALID
- ACPI_HMAT_READ_BANDWIDTH
- ACPI_HMAT_READ_LATENCY
- ACPI_HMAT_RESERVATION_HINT
- ACPI_HMAT_TOTAL_CACHE_LEVEL
- ACPI_HMAT_TYPE_CACHE
- ACPI_HMAT_TYPE_LOCALITY
- ACPI_HMAT_TYPE_PROXIMITY
- ACPI_HMAT_TYPE_RESERVED
- ACPI_HMAT_WRITE_BANDWIDTH
- ACPI_HMAT_WRITE_LATENCY
- ACPI_HMAT_WRITE_POLICY
- ACPI_HOTKEY_COMPONENT
- ACPI_HOTPLUG_OST
- ACPI_HPET_NO_PAGE_PROTECT
- ACPI_HPET_PAGE_PROTECT4
- ACPI_HPET_PAGE_PROTECT64
- ACPI_HPET_PAGE_PROTECT_MASK
- ACPI_HW_DEPENDENT_RETURN_OK
- ACPI_HW_DEPENDENT_RETURN_STATUS
- ACPI_HW_DEPENDENT_RETURN_UINT32
- ACPI_HW_DEPENDENT_RETURN_VOID
- ACPI_HW_OPTIONAL_FUNCTION
- ACPI_HW_PATROL_SCRUB_SUPPORTED
- ACPI_I2C_10BIT_MODE
- ACPI_I2C_7BIT_MODE
- ACPI_IBFT_TYPE_CONTROL
- ACPI_IBFT_TYPE_EXTENSIONS
- ACPI_IBFT_TYPE_INITIATOR
- ACPI_IBFT_TYPE_NIC
- ACPI_IBFT_TYPE_NOT_USED
- ACPI_IBFT_TYPE_RESERVED
- ACPI_IBFT_TYPE_TARGET
- ACPI_IDLE_STATE_START
- ACPI_ID_INTEL_BSW
- ACPI_ID_LEN
- ACPI_IGNORE_PACKAGE_RESOLUTION_ERRORS
- ACPI_IGNORE_RETURN_VALUE
- ACPI_IMODE_EXECUTE
- ACPI_IMODE_LOAD_PASS1
- ACPI_IMODE_LOAD_PASS2
- ACPI_IMPLICIT_CONVERSION
- ACPI_IMPLICIT_CONVERT_HEX
- ACPI_INFO
- ACPI_INFO_PREDEFINED
- ACPI_INITIALIZED_OK
- ACPI_INIT_DEVICE_INI
- ACPI_INIT_DSM_ARGV4
- ACPI_INIT_FUNCTION
- ACPI_INIT_GLOBAL
- ACPI_INIT_UUID
- ACPI_INLINE
- ACPI_INSERT_BITS
- ACPI_INST_SIZE
- ACPI_INTEGER_BIT_SIZE
- ACPI_INTEGER_MAX
- ACPI_INTERNAL_VAR_XFACE
- ACPI_INTERNAL_XFACE
- ACPI_INTERRUPT_COUNT
- ACPI_INTERRUPT_CPEI
- ACPI_INTERRUPT_HANDLED
- ACPI_INTERRUPT_INIT
- ACPI_INTERRUPT_NOT_HANDLED
- ACPI_INTERRUPT_PMI
- ACPI_INVALID_PROTOCOL_ID
- ACPI_INVALID_RESOURCE
- ACPI_INVALID_TABLE_INDEX
- ACPI_INVALID_THREAD_ID
- ACPI_IORT_ATS_SUPPORTED
- ACPI_IORT_ATS_UNSUPPORTED
- ACPI_IORT_HT_OVERRIDE
- ACPI_IORT_HT_READ
- ACPI_IORT_HT_TRANSIENT
- ACPI_IORT_HT_WRITE
- ACPI_IORT_ID_SINGLE_MAPPING
- ACPI_IORT_MF_ATTRIBUTES
- ACPI_IORT_MF_COHERENCY
- ACPI_IORT_NC_PASID_BITS
- ACPI_IORT_NC_STALL_SUPPORTED
- ACPI_IORT_NODE_COHERENT
- ACPI_IORT_NODE_ITS_GROUP
- ACPI_IORT_NODE_NAMED_COMPONENT
- ACPI_IORT_NODE_NOT_COHERENT
- ACPI_IORT_NODE_PCI_ROOT_COMPLEX
- ACPI_IORT_NODE_PMCG
- ACPI_IORT_NODE_SMMU
- ACPI_IORT_NODE_SMMU_V3
- ACPI_IORT_SMMU_CAVIUM_THUNDERX
- ACPI_IORT_SMMU_COHERENT_WALK
- ACPI_IORT_SMMU_CORELINK_MMU400
- ACPI_IORT_SMMU_CORELINK_MMU401
- ACPI_IORT_SMMU_CORELINK_MMU500
- ACPI_IORT_SMMU_DVM_SUPPORTED
- ACPI_IORT_SMMU_V1
- ACPI_IORT_SMMU_V2
- ACPI_IORT_SMMU_V3_CAVIUM_CN99XX
- ACPI_IORT_SMMU_V3_COHACC_OVERRIDE
- ACPI_IORT_SMMU_V3_GENERIC
- ACPI_IORT_SMMU_V3_HISILICON_HI161X
- ACPI_IORT_SMMU_V3_HTTU_OVERRIDE
- ACPI_IORT_SMMU_V3_PXM_VALID
- ACPI_IO_MASK
- ACPI_IO_RANGE
- ACPI_IO_RESTRICT_INPUT
- ACPI_IO_RESTRICT_NONE
- ACPI_IO_RESTRICT_NONE_PRESERVE
- ACPI_IO_RESTRICT_OUTPUT
- ACPI_IPMI_BUFFER_SIZE
- ACPI_IPMI_DATA_SIZE
- ACPI_IPMI_MAX_MSG_LENGTH
- ACPI_IPMI_OK
- ACPI_IPMI_TIMEOUT
- ACPI_IPMI_UNKNOWN
- ACPI_IRQ_MODEL_COUNT
- ACPI_IRQ_MODEL_GIC
- ACPI_IRQ_MODEL_IOAPIC
- ACPI_IRQ_MODEL_IOSAPIC
- ACPI_IRQ_MODEL_PIC
- ACPI_IRQ_MODEL_PLATFORM
- ACPI_ISA_ONLY_RANGES
- ACPI_ISR
- ACPI_IS_ALIGNED
- ACPI_IS_ASCII
- ACPI_IS_DEBUG_ENABLED
- ACPI_IS_MISALIGNED
- ACPI_IS_OCTAL_DIGIT
- ACPI_IS_OEM_SIG
- ACPI_IS_PARENT_PREFIX
- ACPI_IS_PATH_SEPARATOR
- ACPI_IS_POWER_OF_TWO
- ACPI_IS_ROOT_DEVICE
- ACPI_IS_ROOT_PREFIX
- ACPI_IVHD_ATS_DISABLED
- ACPI_IVHD_EINT_PASS
- ACPI_IVHD_ENTRY_LENGTH
- ACPI_IVHD_HPET
- ACPI_IVHD_INIT_PASS
- ACPI_IVHD_IOAPIC
- ACPI_IVHD_IOTLB
- ACPI_IVHD_ISOC
- ACPI_IVHD_LINT0_PASS
- ACPI_IVHD_LINT1_PASS
- ACPI_IVHD_MSI_NUMBER_MASK
- ACPI_IVHD_NMI_PASS
- ACPI_IVHD_PASS_PW
- ACPI_IVHD_RES_PASS_PW
- ACPI_IVHD_SYSTEM_MGMT
- ACPI_IVHD_TT_ENABLE
- ACPI_IVHD_TYPE_MAX_SUPPORTED
- ACPI_IVHD_UNIT_ID_MASK
- ACPI_IVMD_EXCLUSION_RANGE
- ACPI_IVMD_READ
- ACPI_IVMD_TYPE
- ACPI_IVMD_TYPE_ALL
- ACPI_IVMD_TYPE_RANGE
- ACPI_IVMD_UNITY
- ACPI_IVMD_WRITE
- ACPI_IVRS_ATS_RESERVED
- ACPI_IVRS_PHYSICAL_SIZE
- ACPI_IVRS_TYPE_ALIAS_SELECT
- ACPI_IVRS_TYPE_ALIAS_START
- ACPI_IVRS_TYPE_ALL
- ACPI_IVRS_TYPE_END
- ACPI_IVRS_TYPE_EXT_SELECT
- ACPI_IVRS_TYPE_EXT_START
- ACPI_IVRS_TYPE_HARDWARE
- ACPI_IVRS_TYPE_MEMORY1
- ACPI_IVRS_TYPE_MEMORY2
- ACPI_IVRS_TYPE_MEMORY3
- ACPI_IVRS_TYPE_NOT_USED
- ACPI_IVRS_TYPE_PAD4
- ACPI_IVRS_TYPE_PAD8
- ACPI_IVRS_TYPE_SELECT
- ACPI_IVRS_TYPE_SPECIAL
- ACPI_IVRS_TYPE_START
- ACPI_IVRS_VIRTUAL_SIZE
- ACPI_KEYBOARD_BACKLIGHT_DEVICE
- ACPI_KEYBOARD_BACKLIGHT_MAX
- ACPI_KEYBOARD_BACKLIGHT_READ
- ACPI_KEYBOARD_BACKLIGHT_WRITE
- ACPI_LABELS_LOCKED
- ACPI_LARGE_NAMESPACE_NODE
- ACPI_LENOFF_LEN_MASK
- ACPI_LENOFF_LEN_SHIFT
- ACPI_LENOFF_OFF_MASK
- ACPI_LENOFF_OFF_SHIFT
- ACPI_LEVEL_SENSITIVE
- ACPI_LOBYTE
- ACPI_LOCK_GPES
- ACPI_LOCK_HARDWARE
- ACPI_LODWORD
- ACPI_LOWORD
- ACPI_LPAT_H
- ACPI_LPIT_NO_COUNTER
- ACPI_LPIT_STATE_DISABLED
- ACPI_LPIT_TYPE_NATIVE_CSTATE
- ACPI_LPIT_TYPE_RESERVED
- ACPI_LPI_STATE_FLAGS_ENABLED
- ACPI_LPS0_DSM_UUID
- ACPI_LPS0_ENTRY
- ACPI_LPS0_EXIT
- ACPI_LPS0_GET_DEVICE_CONSTRAINTS
- ACPI_LPS0_SCREEN_OFF
- ACPI_LPS0_SCREEN_ON
- ACPI_LV_ALL
- ACPI_LV_ALLOCATIONS
- ACPI_LV_ALL_EXCEPTIONS
- ACPI_LV_AML_DISASSEMBLE
- ACPI_LV_BFIELD
- ACPI_LV_DEBUG_OBJECT
- ACPI_LV_DISPATCH
- ACPI_LV_EVALUATION
- ACPI_LV_EVENTS
- ACPI_LV_EXEC
- ACPI_LV_FULL_TABLES
- ACPI_LV_FUNCTIONS
- ACPI_LV_INFO
- ACPI_LV_INIT
- ACPI_LV_INIT_NAMES
- ACPI_LV_INTERRUPTS
- ACPI_LV_IO
- ACPI_LV_LOAD
- ACPI_LV_MUTEX
- ACPI_LV_NAMES
- ACPI_LV_OBJECTS
- ACPI_LV_OPREGION
- ACPI_LV_OPTIMIZATIONS
- ACPI_LV_PACKAGE
- ACPI_LV_PARSE
- ACPI_LV_PARSE_TREES
- ACPI_LV_REPAIR
- ACPI_LV_RESOURCES
- ACPI_LV_TABLES
- ACPI_LV_THREADS
- ACPI_LV_TRACE_POINT
- ACPI_LV_USER_REQUESTS
- ACPI_LV_VALUES
- ACPI_LV_VERBOSE
- ACPI_LV_VERBOSE_INFO
- ACPI_LV_VERBOSITY1
- ACPI_LV_VERBOSITY2
- ACPI_LV_VERBOSITY3
- ACPI_MACHINE_WIDTH
- ACPI_MADT_CPEI_OVERRIDE
- ACPI_MADT_DUAL_PIC
- ACPI_MADT_ENABLED
- ACPI_MADT_GICC_MIN_LENGTH
- ACPI_MADT_GICC_SPE
- ACPI_MADT_GIC_VERSION_NONE
- ACPI_MADT_GIC_VERSION_RESERVED
- ACPI_MADT_GIC_VERSION_V1
- ACPI_MADT_GIC_VERSION_V2
- ACPI_MADT_GIC_VERSION_V3
- ACPI_MADT_GIC_VERSION_V4
- ACPI_MADT_MULTIPLE_APIC
- ACPI_MADT_OVERRIDE_SPI_VALUES
- ACPI_MADT_PCAT_COMPAT
- ACPI_MADT_PERFORMANCE_IRQ_MODE
- ACPI_MADT_POLARITY_ACTIVE_HIGH
- ACPI_MADT_POLARITY_ACTIVE_LOW
- ACPI_MADT_POLARITY_CONFORMS
- ACPI_MADT_POLARITY_MASK
- ACPI_MADT_POLARITY_RESERVED
- ACPI_MADT_TRIGGER_CONFORMS
- ACPI_MADT_TRIGGER_EDGE
- ACPI_MADT_TRIGGER_LEVEL
- ACPI_MADT_TRIGGER_MASK
- ACPI_MADT_TRIGGER_RESERVED
- ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
- ACPI_MADT_TYPE_GENERIC_INTERRUPT
- ACPI_MADT_TYPE_GENERIC_MSI_FRAME
- ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR
- ACPI_MADT_TYPE_GENERIC_TRANSLATOR
- ACPI_MADT_TYPE_INTERRUPT_OVERRIDE
- ACPI_MADT_TYPE_INTERRUPT_SOURCE
- ACPI_MADT_TYPE_IO_APIC
- ACPI_MADT_TYPE_IO_SAPIC
- ACPI_MADT_TYPE_LOCAL_APIC
- ACPI_MADT_TYPE_LOCAL_APIC_NMI
- ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE
- ACPI_MADT_TYPE_LOCAL_SAPIC
- ACPI_MADT_TYPE_LOCAL_X2APIC
- ACPI_MADT_TYPE_LOCAL_X2APIC_NMI
- ACPI_MADT_TYPE_NMI_SOURCE
- ACPI_MADT_TYPE_RESERVED
- ACPI_MADT_VGIC_IRQ_MODE
- ACPI_MAKE_RSDP_SIG
- ACPI_MASKABLE_GPE_MAX
- ACPI_MASK_BITS_ABOVE
- ACPI_MASK_BITS_ABOVE_32
- ACPI_MASK_BITS_ABOVE_64
- ACPI_MASK_BITS_BELOW
- ACPI_MASK_BITS_BELOW_32
- ACPI_MASK_BITS_BELOW_64
- ACPI_MAX
- ACPI_MAX16_DECIMAL_DIGITS
- ACPI_MAX32_DECIMAL_DIGITS
- ACPI_MAX64_DECIMAL_DIGITS
- ACPI_MAX8_DECIMAL_DIGITS
- ACPI_MAX_ADDRESS_SPACE
- ACPI_MAX_COMMENT_CACHE_DEPTH
- ACPI_MAX_DECIMAL_DIGITS
- ACPI_MAX_DEVICE_SPECIFIC_NOTIFY
- ACPI_MAX_EXTPARSE_CACHE_DEPTH
- ACPI_MAX_GPE_BLOCKS
- ACPI_MAX_GSBUS_BUFFER_SIZE
- ACPI_MAX_GSBUS_DATA_SIZE
- ACPI_MAX_HANDLES
- ACPI_MAX_ISA_IRQS
- ACPI_MAX_LOCK
- ACPI_MAX_LOOP_TIMEOUT
- ACPI_MAX_MATCH_OPCODE
- ACPI_MAX_MODULE_NAME
- ACPI_MAX_MUTEX
- ACPI_MAX_NAMESPACE_CACHE_DEPTH
- ACPI_MAX_NOTIFY_HANDLER_TYPE
- ACPI_MAX_OBJECT_CACHE_DEPTH
- ACPI_MAX_OVERRIDE_LEN
- ACPI_MAX_PARSEOP_NAME
- ACPI_MAX_PARSE_CACHE_DEPTH
- ACPI_MAX_PLATFORM_INTERRUPTS
- ACPI_MAX_PROTOCOL_ID
- ACPI_MAX_PTR
- ACPI_MAX_REFERENCE_COUNT
- ACPI_MAX_SEMAPHORE_COUNT
- ACPI_MAX_SLEEP
- ACPI_MAX_STATE_CACHE_DEPTH
- ACPI_MAX_STRING
- ACPI_MAX_SYS_NOTIFY
- ACPI_MAX_TABLES
- ACPI_MAX_TABLE_INSTANCES
- ACPI_MAX_TABLE_VALIDATIONS
- ACPI_MDPS_CLASS
- ACPI_MEMORY_DEVICE_CLASS
- ACPI_MEMORY_DEVICE_COMPONENT
- ACPI_MEMORY_DEVICE_HID
- ACPI_MEMORY_DEVICE_NAME
- ACPI_MEMORY_RANGE
- ACPI_MEM_CALLOC
- ACPI_MEM_LIST_GLOBAL
- ACPI_MEM_LIST_MAX
- ACPI_MEM_LIST_NSNODE
- ACPI_MEM_MALLOC
- ACPI_MEM_PARAMETERS
- ACPI_MEM_TRACKING
- ACPI_METHOD_IGNORE_SYNC_LEVEL
- ACPI_METHOD_INTERNAL_ONLY
- ACPI_METHOD_MAX_ARG
- ACPI_METHOD_MAX_LOCAL
- ACPI_METHOD_MODIFIED_NAMESPACE
- ACPI_METHOD_MODULE_LEVEL
- ACPI_METHOD_NUM_ARGS
- ACPI_METHOD_NUM_LOCALS
- ACPI_METHOD_SERIALIZED
- ACPI_METHOD_SERIALIZED_PENDING
- ACPI_MIN
- ACPI_MISALIGNMENT_NOT_SUPPORTED
- ACPI_MMIO_REG_LEN
- ACPI_MODULE_NAME
- ACPI_MOD_16
- ACPI_MOD_2
- ACPI_MOD_32
- ACPI_MOD_4
- ACPI_MOD_8
- ACPI_MOTHERBOARD_RESOURCE_HID
- ACPI_MOVE_16_TO_16
- ACPI_MOVE_16_TO_32
- ACPI_MOVE_16_TO_64
- ACPI_MOVE_32_TO_16
- ACPI_MOVE_32_TO_32
- ACPI_MOVE_32_TO_64
- ACPI_MOVE_64_TO_16
- ACPI_MOVE_64_TO_32
- ACPI_MOVE_64_TO_64
- ACPI_MPST_AUTOENTRY
- ACPI_MPST_AUTOEXIT
- ACPI_MPST_CHANNEL_INFO
- ACPI_MPST_ENABLED
- ACPI_MPST_HOT_PLUG_CAPABLE
- ACPI_MPST_POWER_MANAGED
- ACPI_MPST_PRESERVE
- ACPI_MSEC_PER_SEC
- ACPI_MSG_BIOS_ERROR
- ACPI_MSG_BIOS_WARNING
- ACPI_MSG_DEPENDENT_RETURN_VOID
- ACPI_MSG_ERROR
- ACPI_MSG_EXCEPTION
- ACPI_MSG_INFO
- ACPI_MSG_REDIRECT_BEGIN
- ACPI_MSG_REDIRECT_END
- ACPI_MSG_SUFFIX
- ACPI_MSG_WARNING
- ACPI_MTX_CACHES
- ACPI_MTX_DO_NOT_LOCK
- ACPI_MTX_EVENTS
- ACPI_MTX_INTERPRETER
- ACPI_MTX_LOCK
- ACPI_MTX_MEMORY
- ACPI_MTX_NAMESPACE
- ACPI_MTX_TABLES
- ACPI_MUL_16
- ACPI_MUL_2
- ACPI_MUL_32
- ACPI_MUL_4
- ACPI_MUL_8
- ACPI_MUTEX_DEBUG
- ACPI_MUTEX_NOT_ACQUIRED
- ACPI_MUTEX_SEM
- ACPI_MUTEX_TYPE
- ACPI_NAMESEG_SIZE
- ACPI_NAMESPACE
- ACPI_NAMESPACE_ROOT
- ACPI_NAME_TYPE_MAX
- ACPI_NEXT_OP_DOWNWARD
- ACPI_NEXT_OP_UPWARD
- ACPI_NEXT_RESOURCE
- ACPI_NFIT_ADD_ONLINE_ONLY
- ACPI_NFIT_BUILD_DEVICE_HANDLE
- ACPI_NFIT_CAPABILITY_CACHE_FLUSH
- ACPI_NFIT_CAPABILITY_MEM_FLUSH
- ACPI_NFIT_CAPABILITY_MEM_MIRRORING
- ACPI_NFIT_CHANNEL_NUMBER_MASK
- ACPI_NFIT_CHANNEL_NUMBER_OFFSET
- ACPI_NFIT_CONTROL_BUFFERED
- ACPI_NFIT_CONTROL_MFG_INFO_VALID
- ACPI_NFIT_DIMM_NUMBER_MASK
- ACPI_NFIT_DIMM_NUMBER_OFFSET
- ACPI_NFIT_GET_CHANNEL_NUMBER
- ACPI_NFIT_GET_DIMM_NUMBER
- ACPI_NFIT_GET_MEMORY_ID
- ACPI_NFIT_GET_NODE_ID
- ACPI_NFIT_GET_SOCKET_ID
- ACPI_NFIT_MEMORY_ID_MASK
- ACPI_NFIT_MEMORY_ID_OFFSET
- ACPI_NFIT_MEM_FAILED_MASK
- ACPI_NFIT_MEM_FLUSH_FAILED
- ACPI_NFIT_MEM_HEALTH_ENABLED
- ACPI_NFIT_MEM_HEALTH_OBSERVED
- ACPI_NFIT_MEM_MAP_FAILED
- ACPI_NFIT_MEM_NOT_ARMED
- ACPI_NFIT_MEM_RESTORE_FAILED
- ACPI_NFIT_MEM_SAVE_FAILED
- ACPI_NFIT_NODE_ID_MASK
- ACPI_NFIT_NODE_ID_OFFSET
- ACPI_NFIT_PROXIMITY_VALID
- ACPI_NFIT_SOCKET_ID_MASK
- ACPI_NFIT_SOCKET_ID_OFFSET
- ACPI_NFIT_TYPE_CAPABILITIES
- ACPI_NFIT_TYPE_CONTROL_REGION
- ACPI_NFIT_TYPE_DATA_REGION
- ACPI_NFIT_TYPE_FLUSH_ADDRESS
- ACPI_NFIT_TYPE_INTERLEAVE
- ACPI_NFIT_TYPE_MEMORY_MAP
- ACPI_NFIT_TYPE_RESERVED
- ACPI_NFIT_TYPE_SMBIOS
- ACPI_NFIT_TYPE_SYSTEM_ADDRESS
- ACPI_NON_CACHEABLE_MEMORY
- ACPI_NON_ISA_ONLY_RANGES
- ACPI_NORMAL_DEFAULT
- ACPI_NOTIFY_AFFINITY_UPDATE
- ACPI_NOTIFY_BUS_CHECK
- ACPI_NOTIFY_BUS_MODE_MISMATCH
- ACPI_NOTIFY_CAPABILITIES_CHECK
- ACPI_NOTIFY_DEVICE_CHECK
- ACPI_NOTIFY_DEVICE_CHECK_LIGHT
- ACPI_NOTIFY_DEVICE_PLD_CHECK
- ACPI_NOTIFY_DEVICE_WAKE
- ACPI_NOTIFY_DISCONNECT_RECOVER
- ACPI_NOTIFY_EJECT_REQUEST
- ACPI_NOTIFY_FREQUENCY_MISMATCH
- ACPI_NOTIFY_LOCALITY_UPDATE
- ACPI_NOTIFY_MEMORY_UPDATE
- ACPI_NOTIFY_POWER_FAULT
- ACPI_NOTIFY_RESERVED
- ACPI_NOTIFY_SHUTDOWN_REQUEST
- ACPI_NOT_BUS_MASTER
- ACPI_NOT_ISR
- ACPI_NOT_METHOD_CALL
- ACPI_NOT_PACKAGE_ELEMENT
- ACPI_NOT_WAKE_CAPABLE
- ACPI_NO_ACPI_ENABLE
- ACPI_NO_ADDRESS_SPACE_INIT
- ACPI_NO_BUFFER
- ACPI_NO_DEVICE_INIT
- ACPI_NO_ERROR_MESSAGES
- ACPI_NO_EVENT_INIT
- ACPI_NO_FACS_INIT
- ACPI_NO_HANDLER_INIT
- ACPI_NO_HARDWARE_INIT
- ACPI_NO_IMPLICIT_CONVERSION
- ACPI_NO_MEM_ALLOCATIONS
- ACPI_NO_OBJECT_INIT
- ACPI_NO_UNIT_LIMIT
- ACPI_NR_ART_ELEMENTS
- ACPI_NSEC_PER_MSEC
- ACPI_NSEC_PER_SEC
- ACPI_NSEC_PER_USEC
- ACPI_NS_ALL
- ACPI_NS_DONT_OPEN_SCOPE
- ACPI_NS_EARLY_INIT
- ACPI_NS_ERROR_IF_FOUND
- ACPI_NS_EXTERNAL
- ACPI_NS_LOCAL
- ACPI_NS_NEWSCOPE
- ACPI_NS_NORMAL
- ACPI_NS_NO_PEER_SEARCH
- ACPI_NS_NO_UPSEARCH
- ACPI_NS_OVERRIDE_IF_FOUND
- ACPI_NS_PREFIX_IS_SCOPE
- ACPI_NS_PREFIX_MUST_EXIST
- ACPI_NS_ROOT_PATH
- ACPI_NS_SEARCH_PARENT
- ACPI_NS_TEMPORARY
- ACPI_NS_WALK_NO_UNLOCK
- ACPI_NS_WALK_TEMP_NODES
- ACPI_NS_WALK_UNLOCK
- ACPI_NUM_BITREG
- ACPI_NUM_DEFAULT_SPACES
- ACPI_NUM_FIXED_EVENTS
- ACPI_NUM_GEO_PROFILES
- ACPI_NUM_LOCK
- ACPI_NUM_MEM_LISTS
- ACPI_NUM_MUTEX
- ACPI_NUM_NOTIFY_TYPES
- ACPI_NUM_NS_TYPES
- ACPI_NUM_OWNERID_MASKS
- ACPI_NUM_PREDEFINED_REGIONS
- ACPI_NUM_RTYPES
- ACPI_NUM_TABLE_EVENTS
- ACPI_NUM_TYPES
- ACPI_NUM_sx_d_METHODS
- ACPI_NUM_sx_w_METHODS
- ACPI_OBJECT_COMMON_HEADER
- ACPI_OBJECT_REPAIRED
- ACPI_OBJECT_WRAPPED
- ACPI_OBJ_MAX_OPERAND
- ACPI_OBJ_NUM_OPERANDS
- ACPI_OEM_ID_SIZE
- ACPI_OEM_NAME
- ACPI_OEM_TABLE_ID_SIZE
- ACPI_OFFSET
- ACPI_OP
- ACPI_OPTION
- ACPI_OPTION_ERROR
- ACPI_OPT_END
- ACPI_OSI_DEFAULT_INVALID
- ACPI_OSI_DYNAMIC
- ACPI_OSI_FEATURE
- ACPI_OSI_INVALID
- ACPI_OSI_OPTIONAL_FEATURE
- ACPI_OSI_WINSRV_2003
- ACPI_OSI_WINSRV_2003_SP1
- ACPI_OSI_WINSRV_2008
- ACPI_OSI_WIN_10
- ACPI_OSI_WIN_10_19H1
- ACPI_OSI_WIN_10_RS1
- ACPI_OSI_WIN_10_RS2
- ACPI_OSI_WIN_10_RS3
- ACPI_OSI_WIN_10_RS4
- ACPI_OSI_WIN_10_RS5
- ACPI_OSI_WIN_2000
- ACPI_OSI_WIN_7
- ACPI_OSI_WIN_8
- ACPI_OSI_WIN_8_1
- ACPI_OSI_WIN_VISTA
- ACPI_OSI_WIN_VISTA_SP1
- ACPI_OSI_WIN_VISTA_SP2
- ACPI_OSI_WIN_XP
- ACPI_OSI_WIN_XP_SP1
- ACPI_OSI_WIN_XP_SP2
- ACPI_OSL_MUTEX
- ACPI_OST_EC_OSPM_EJECT
- ACPI_OST_EC_OSPM_INSERTION
- ACPI_OST_EC_OSPM_SHUTDOWN
- ACPI_OST_SC_DEVICE_BUSY
- ACPI_OST_SC_DEVICE_IN_USE
- ACPI_OST_SC_DRIVER_LOAD_FAILURE
- ACPI_OST_SC_EJECT_DEPENDENCY_BUSY
- ACPI_OST_SC_EJECT_IN_PROGRESS
- ACPI_OST_SC_EJECT_NOT_SUPPORTED
- ACPI_OST_SC_INSERT_IN_PROGRESS
- ACPI_OST_SC_INSERT_NOT_SUPPORTED
- ACPI_OST_SC_NON_SPECIFIC_FAILURE
- ACPI_OST_SC_OS_SHUTDOWN_COMPLETED
- ACPI_OST_SC_OS_SHUTDOWN_DENIED
- ACPI_OST_SC_OS_SHUTDOWN_IN_PROGRESS
- ACPI_OST_SC_OS_SHUTDOWN_NOT_SUPPORTED
- ACPI_OST_SC_SUCCESS
- ACPI_OST_SC_UNRECOGNIZED_NOTIFY
- ACPI_OS_NAME
- ACPI_OS_SERVICES
- ACPI_OWNER_ID_MAX
- ACPI_PARSEOP_ASSIGNMENT
- ACPI_PARSEOP_BYTELIST
- ACPI_PARSEOP_CLOSING_PAREN
- ACPI_PARSEOP_COMPOUND_ASSIGNMENT
- ACPI_PARSEOP_DEFERRED
- ACPI_PARSEOP_ELSEIF
- ACPI_PARSEOP_EMPTY_TERMLIST
- ACPI_PARSEOP_GENERIC
- ACPI_PARSEOP_IGNORE
- ACPI_PARSEOP_IN_CACHE
- ACPI_PARSEOP_IN_STACK
- ACPI_PARSEOP_LEGACY_ASL_ONLY
- ACPI_PARSEOP_NAMED_OBJECT
- ACPI_PARSEOP_PARAMETER_LIST
- ACPI_PARSEOP_PREDEFINED_CHECKED
- ACPI_PARSEOP_TARGET
- ACPI_PARSER
- ACPI_PARSE_COMMON
- ACPI_PARSE_DEFERRED_OP
- ACPI_PARSE_DELETE_TREE
- ACPI_PARSE_DISASSEMBLE
- ACPI_PARSE_EXECUTE
- ACPI_PARSE_LOAD_PASS1
- ACPI_PARSE_LOAD_PASS2
- ACPI_PARSE_MODE_MASK
- ACPI_PARSE_MODULE_LEVEL
- ACPI_PARSE_NO_TREE_DELETE
- ACPI_PARSE_TREE_MASK
- ACPI_PATH_PUT8
- ACPI_PATH_SEGMENT_LENGTH
- ACPI_PATH_SEPARATOR
- ACPI_PCCT_DOORBELL
- ACPI_PCCT_INTERRUPT_MODE
- ACPI_PCCT_INTERRUPT_POLARITY
- ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE
- ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE
- ACPI_PCCT_TYPE_GENERIC_SUBSPACE
- ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE
- ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2
- ACPI_PCCT_TYPE_RESERVED
- ACPI_PCC_CLASS
- ACPI_PCC_DEVICE_NAME
- ACPI_PCC_DRIVER_NAME
- ACPI_PCC_INPUT_PHYS
- ACPI_PCICLS_STRING_SIZE
- ACPI_PCIE_REQ_SUPPORT
- ACPI_PCI_COMPONENT
- ACPI_PCI_CONFIGURED
- ACPI_PCI_LINK_CLASS
- ACPI_PCI_LINK_DEVICE_NAME
- ACPI_PCI_LINK_FILE_INFO
- ACPI_PCI_LINK_FILE_STATUS
- ACPI_PCI_LINK_MAX_POSSIBLE
- ACPI_PCI_ROOT_BRIDGE
- ACPI_PCI_ROOT_CLASS
- ACPI_PCI_ROOT_DEVICE_NAME
- ACPI_PDC_C_C1_FFH
- ACPI_PDC_C_C1_HALT
- ACPI_PDC_C_C2C3_FFH
- ACPI_PDC_C_CAPABILITY_SMP
- ACPI_PDC_EST_CAPABILITY_SMP
- ACPI_PDC_EST_CAPABILITY_SWSMP
- ACPI_PDC_P_FFH
- ACPI_PDC_REVISION_ID
- ACPI_PDC_SMP_C1PT
- ACPI_PDC_SMP_C2C3
- ACPI_PDC_SMP_C_SWCOORD
- ACPI_PDC_SMP_P_HWCOORD
- ACPI_PDC_SMP_P_SWCOORD
- ACPI_PDC_SMP_T_SWCOORD
- ACPI_PDC_T_FFH
- ACPI_PDTT_RUNTIME_TRIGGER
- ACPI_PDTT_TRIGGER_ORDER
- ACPI_PDTT_WAIT_COMPLETION
- ACPI_PHYSADDR_TO_PTR
- ACPI_PIN_CONFIG_BIAS_BUS_HOLD
- ACPI_PIN_CONFIG_BIAS_DEFAULT
- ACPI_PIN_CONFIG_BIAS_DISABLE
- ACPI_PIN_CONFIG_BIAS_HIGH_IMPEDANCE
- ACPI_PIN_CONFIG_BIAS_PULL_DOWN
- ACPI_PIN_CONFIG_BIAS_PULL_UP
- ACPI_PIN_CONFIG_DEFAULT
- ACPI_PIN_CONFIG_DRIVE_OPEN_DRAIN
- ACPI_PIN_CONFIG_DRIVE_OPEN_SOURCE
- ACPI_PIN_CONFIG_DRIVE_PUSH_PULL
- ACPI_PIN_CONFIG_DRIVE_STRENGTH
- ACPI_PIN_CONFIG_INPUT_DEBOUNCE
- ACPI_PIN_CONFIG_INPUT_SCHMITT_TRIGGER
- ACPI_PIN_CONFIG_NOPULL
- ACPI_PIN_CONFIG_PULLDOWN
- ACPI_PIN_CONFIG_PULLUP
- ACPI_PIN_CONFIG_SLEW_RATE
- ACPI_PIPE_ID_MASK
- ACPI_PIPE_ID_SHIFT
- ACPI_PLD_BUFFER_SIZE
- ACPI_PLD_GET_BAY
- ACPI_PLD_GET_BLUE
- ACPI_PLD_GET_CABINET
- ACPI_PLD_GET_CARD_CAGE
- ACPI_PLD_GET_DOCK
- ACPI_PLD_GET_EJECTABLE
- ACPI_PLD_GET_GREEN
- ACPI_PLD_GET_HEIGHT
- ACPI_PLD_GET_HORIZONTAL
- ACPI_PLD_GET_HORIZ_OFFSET
- ACPI_PLD_GET_IGNORE_COLOR
- ACPI_PLD_GET_LID
- ACPI_PLD_GET_ORDER
- ACPI_PLD_GET_ORIENTATION
- ACPI_PLD_GET_OSPM_EJECT
- ACPI_PLD_GET_PANEL
- ACPI_PLD_GET_POSITION
- ACPI_PLD_GET_RED
- ACPI_PLD_GET_REFERENCE
- ACPI_PLD_GET_REVISION
- ACPI_PLD_GET_ROTATION
- ACPI_PLD_GET_SHAPE
- ACPI_PLD_GET_TOKEN
- ACPI_PLD_GET_USER_VISIBLE
- ACPI_PLD_GET_VERTICAL
- ACPI_PLD_GET_VERT_OFFSET
- ACPI_PLD_GET_WIDTH
- ACPI_PLD_OUTPUT
- ACPI_PLD_REV1_BUFFER_SIZE
- ACPI_PLD_REV2_BUFFER_SIZE
- ACPI_PLD_SET_BAY
- ACPI_PLD_SET_BLUE
- ACPI_PLD_SET_CABINET
- ACPI_PLD_SET_CARD_CAGE
- ACPI_PLD_SET_DOCK
- ACPI_PLD_SET_EJECTABLE
- ACPI_PLD_SET_GREEN
- ACPI_PLD_SET_HEIGHT
- ACPI_PLD_SET_HORIZONTAL
- ACPI_PLD_SET_HORIZ_OFFSET
- ACPI_PLD_SET_IGNORE_COLOR
- ACPI_PLD_SET_LID
- ACPI_PLD_SET_ORDER
- ACPI_PLD_SET_ORIENTATION
- ACPI_PLD_SET_OSPM_EJECT
- ACPI_PLD_SET_PANEL
- ACPI_PLD_SET_POSITION
- ACPI_PLD_SET_RED
- ACPI_PLD_SET_REFERENCE
- ACPI_PLD_SET_REVISION
- ACPI_PLD_SET_ROTATION
- ACPI_PLD_SET_SHAPE
- ACPI_PLD_SET_TOKEN
- ACPI_PLD_SET_USER_VISIBLE
- ACPI_PLD_SET_VERTICAL
- ACPI_PLD_SET_VERT_OFFSET
- ACPI_PLD_SET_WIDTH
- ACPI_PM1_CONTROL_IGNORED_BITS
- ACPI_PM1_CONTROL_PRESERVED_BITS
- ACPI_PM1_CONTROL_RESERVED_BITS
- ACPI_PM1_CONTROL_WRITEONLY_BITS
- ACPI_PM1_REGISTER_WIDTH
- ACPI_PM1_STATUS_PRESERVED_BITS
- ACPI_PM2_CONTROL_PRESERVED_BITS
- ACPI_PM2_REGISTER_WIDTH
- ACPI_PMA_CNT_BLK
- ACPI_PME_CIR_BIT
- ACPI_PMTT_MEMORY_TYPE
- ACPI_PMTT_PHYSICAL
- ACPI_PMTT_TOP_LEVEL
- ACPI_PMTT_TYPE_CONTROLLER
- ACPI_PMTT_TYPE_DIMM
- ACPI_PMTT_TYPE_RESERVED
- ACPI_PMTT_TYPE_SOCKET
- ACPI_PM_CNT_BLK
- ACPI_PM_EVT_BLK
- ACPI_PM_MASK
- ACPI_PM_MONOTONICITY_CHECKS
- ACPI_PM_OVRRUN
- ACPI_PM_READ_CHECKS
- ACPI_PM_TIMER_FREQUENCY
- ACPI_PM_TIMER_WIDTH
- ACPI_PM_TMR_BLK
- ACPI_PNP_H
- ACPI_PORT_INFO_ENTRIES
- ACPI_POSSIBLE_METHOD_CALL
- ACPI_POS_DECODE
- ACPI_POWER_CLASS
- ACPI_POWER_COMPONENT
- ACPI_POWER_DEVICE_NAME
- ACPI_POWER_FILE_INFO
- ACPI_POWER_FILE_STATUS
- ACPI_POWER_HID
- ACPI_POWER_METER_CLASS
- ACPI_POWER_METER_DEVICE_NAME
- ACPI_POWER_METER_NAME
- ACPI_POWER_RESOURCE_STATE_OFF
- ACPI_POWER_RESOURCE_STATE_ON
- ACPI_POWER_RESOURCE_STATE_UNKNOWN
- ACPI_PPAG_MAX_HB
- ACPI_PPAG_MAX_LB
- ACPI_PPAG_METHOD
- ACPI_PPAG_MIN_HB
- ACPI_PPAG_MIN_LB
- ACPI_PPAG_NUM_CHAINS
- ACPI_PPAG_NUM_SUB_BANDS
- ACPI_PPAG_WIFI_DATA_SIZE
- ACPI_PPTT_ACPI_IDENTICAL
- ACPI_PPTT_ACPI_LEAF_NODE
- ACPI_PPTT_ACPI_PROCESSOR_ID_VALID
- ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD
- ACPI_PPTT_ALLOCATION_TYPE_VALID
- ACPI_PPTT_ASSOCIATIVITY_VALID
- ACPI_PPTT_CACHE_POLICY_WB
- ACPI_PPTT_CACHE_POLICY_WT
- ACPI_PPTT_CACHE_READ_ALLOCATE
- ACPI_PPTT_CACHE_RW_ALLOCATE
- ACPI_PPTT_CACHE_RW_ALLOCATE_ALT
- ACPI_PPTT_CACHE_TYPE_DATA
- ACPI_PPTT_CACHE_TYPE_INSTR
- ACPI_PPTT_CACHE_TYPE_UNIFIED
- ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT
- ACPI_PPTT_CACHE_TYPE_VALID
- ACPI_PPTT_CACHE_WRITE_ALLOCATE
- ACPI_PPTT_LINE_SIZE_VALID
- ACPI_PPTT_MASK_ALLOCATION_TYPE
- ACPI_PPTT_MASK_CACHE_TYPE
- ACPI_PPTT_MASK_WRITE_POLICY
- ACPI_PPTT_NUMBER_OF_SETS_VALID
- ACPI_PPTT_PHYSICAL_PACKAGE
- ACPI_PPTT_SIZE_PROPERTY_VALID
- ACPI_PPTT_TYPE_CACHE
- ACPI_PPTT_TYPE_ID
- ACPI_PPTT_TYPE_PROCESSOR
- ACPI_PPTT_TYPE_RESERVED
- ACPI_PPTT_WRITE_POLICY_VALID
- ACPI_PREDEFINED_PREFIX
- ACPI_PREFETCHABLE_MEMORY
- ACPI_PREFIX_LOWER
- ACPI_PREFIX_MIXED
- ACPI_PRINTF_LIKE
- ACPI_PROBE_TABLE
- ACPI_PROBE_TABLE_END
- ACPI_PROCESSOR_AGGREGATOR_CLASS
- ACPI_PROCESSOR_AGGREGATOR_DEVICE_NAME
- ACPI_PROCESSOR_AGGREGATOR_NOTIFY
- ACPI_PROCESSOR_BUSY_METRIC
- ACPI_PROCESSOR_CLASS
- ACPI_PROCESSOR_COMPONENT
- ACPI_PROCESSOR_CONTAINER_HID
- ACPI_PROCESSOR_DEVICE_HID
- ACPI_PROCESSOR_DEVICE_NAME
- ACPI_PROCESSOR_FILE_PERFORMANCE
- ACPI_PROCESSOR_LIMIT_DECREMENT
- ACPI_PROCESSOR_LIMIT_INCREMENT
- ACPI_PROCESSOR_LIMIT_NONE
- ACPI_PROCESSOR_MAX_C2_LATENCY
- ACPI_PROCESSOR_MAX_C3_LATENCY
- ACPI_PROCESSOR_MAX_DUTY_WIDTH
- ACPI_PROCESSOR_MAX_POWER
- ACPI_PROCESSOR_MAX_THROTTLE
- ACPI_PROCESSOR_MAX_THROTTLING
- ACPI_PROCESSOR_NOTIFY_PERFORMANCE
- ACPI_PROCESSOR_NOTIFY_POWER
- ACPI_PROCESSOR_NOTIFY_THROTTLING
- ACPI_PROCESSOR_OBJECT_HID
- ACPI_PRODUCER
- ACPI_PROG_EXCEPTION
- ACPI_PRT_OFFSET
- ACPI_PSD_REV0_ENTRIES
- ACPI_PSD_REV0_REVISION
- ACPI_PTR
- ACPI_PTR_DIFF
- ACPI_PTR_TO_PHYSADDR
- ACPI_PTYPE1_FIXED
- ACPI_PTYPE1_OPTION
- ACPI_PTYPE1_VAR
- ACPI_PTYPE2
- ACPI_PTYPE2_COUNT
- ACPI_PTYPE2_FIXED
- ACPI_PTYPE2_FIX_VAR
- ACPI_PTYPE2_MIN
- ACPI_PTYPE2_PKG_COUNT
- ACPI_PTYPE2_REV_FIXED
- ACPI_PTYPE2_UUID_PAIR
- ACPI_PTYPE2_VAR_VAR
- ACPI_PTYPE_CUSTOM
- ACPI_PWR_DOWN_EN
- ACPI_RASF_ABORTED
- ACPI_RASF_BUSY
- ACPI_RASF_COMMAND_COMPLETE
- ACPI_RASF_ERROR
- ACPI_RASF_EXECUTE_RASF_COMMAND
- ACPI_RASF_FAILED
- ACPI_RASF_GENERATE_SCI
- ACPI_RASF_GET_PATROL_PARAMETERS
- ACPI_RASF_INVALID_DATA
- ACPI_RASF_NOT_SUPPORTED
- ACPI_RASF_NOT_VALID
- ACPI_RASF_SCI_DOORBELL
- ACPI_RASF_SCRUBBER_RUNNING
- ACPI_RASF_SPEED
- ACPI_RASF_SPEED_FAST
- ACPI_RASF_SPEED_MEDIUM
- ACPI_RASF_SPEED_SLOW
- ACPI_RASF_START_PATROL_SCRUBBER
- ACPI_RASF_STATUS
- ACPI_RASF_STOP_PATROL_SCRUBBER
- ACPI_RASF_SUCCESS
- ACPI_READ
- ACPI_READ_ONLY_MEMORY
- ACPI_READ_WRITE_MEMORY
- ACPI_RECONFIG_DEVICE_ADD
- ACPI_RECONFIG_DEVICE_REMOVE
- ACPI_REDUCED_HARDWARE
- ACPI_REENABLE_GPE
- ACPI_REFCLASS_ARG
- ACPI_REFCLASS_DEBUG
- ACPI_REFCLASS_INDEX
- ACPI_REFCLASS_LOCAL
- ACPI_REFCLASS_MAX
- ACPI_REFCLASS_NAME
- ACPI_REFCLASS_REFOF
- ACPI_REFCLASS_TABLE
- ACPI_REFERENCE_CLASSES
- ACPI_REGION_ACTIVATE
- ACPI_REGION_DEACTIVATE
- ACPI_REGISTER_INSERT_VALUE
- ACPI_REGISTER_PM1_CONTROL
- ACPI_REGISTER_PM1_ENABLE
- ACPI_REGISTER_PM1_STATUS
- ACPI_REGISTER_PM2_CONTROL
- ACPI_REGISTER_PM_TIMER
- ACPI_REGISTER_PREPARE_BITS
- ACPI_REGISTER_PROCESSOR_BLOCK
- ACPI_REGISTER_SMI_COMMAND_BLOCK
- ACPI_REG_CONNECT
- ACPI_REG_DISCONNECT
- ACPI_RELEASE_GLOBAL_LOCK
- ACPI_RESET_REGISTER_WIDTH
- ACPI_RESOURCES
- ACPI_RESOURCE_ADDRESS_COMMON
- ACPI_RESOURCE_FLAG_DEC
- ACPI_RESOURCE_FLAG_MAF
- ACPI_RESOURCE_FLAG_MIF
- ACPI_RESOURCE_GPIO_TYPE_INT
- ACPI_RESOURCE_GPIO_TYPE_IO
- ACPI_RESOURCE_NAME_ADDRESS16
- ACPI_RESOURCE_NAME_ADDRESS32
- ACPI_RESOURCE_NAME_ADDRESS64
- ACPI_RESOURCE_NAME_DMA
- ACPI_RESOURCE_NAME_END_DEPENDENT
- ACPI_RESOURCE_NAME_END_TAG
- ACPI_RESOURCE_NAME_EXTENDED_ADDRESS64
- ACPI_RESOURCE_NAME_EXTENDED_IRQ
- ACPI_RESOURCE_NAME_FIXED_DMA
- ACPI_RESOURCE_NAME_FIXED_IO
- ACPI_RESOURCE_NAME_FIXED_MEMORY32
- ACPI_RESOURCE_NAME_GENERIC_REGISTER
- ACPI_RESOURCE_NAME_GPIO
- ACPI_RESOURCE_NAME_IO
- ACPI_RESOURCE_NAME_IRQ
- ACPI_RESOURCE_NAME_LARGE
- ACPI_RESOURCE_NAME_LARGE_MASK
- ACPI_RESOURCE_NAME_LARGE_MAX
- ACPI_RESOURCE_NAME_MEMORY24
- ACPI_RESOURCE_NAME_MEMORY32
- ACPI_RESOURCE_NAME_PIN_CONFIG
- ACPI_RESOURCE_NAME_PIN_FUNCTION
- ACPI_RESOURCE_NAME_PIN_GROUP
- ACPI_RESOURCE_NAME_PIN_GROUP_CONFIG
- ACPI_RESOURCE_NAME_PIN_GROUP_FUNCTION
- ACPI_RESOURCE_NAME_RESERVED_L1
- ACPI_RESOURCE_NAME_RESERVED_S2
- ACPI_RESOURCE_NAME_RESERVED_S3
- ACPI_RESOURCE_NAME_RESERVED_S4
- ACPI_RESOURCE_NAME_SERIAL_BUS
- ACPI_RESOURCE_NAME_SMALL
- ACPI_RESOURCE_NAME_SMALL_LENGTH_MASK
- ACPI_RESOURCE_NAME_SMALL_MASK
- ACPI_RESOURCE_NAME_START_DEPENDENT
- ACPI_RESOURCE_NAME_VENDOR_LARGE
- ACPI_RESOURCE_NAME_VENDOR_SMALL
- ACPI_RESOURCE_SERIAL_COMMON
- ACPI_RESOURCE_SERIAL_TYPE_I2C
- ACPI_RESOURCE_SERIAL_TYPE_SPI
- ACPI_RESOURCE_SERIAL_TYPE_UART
- ACPI_RESOURCE_TYPE_ADDRESS16
- ACPI_RESOURCE_TYPE_ADDRESS32
- ACPI_RESOURCE_TYPE_ADDRESS64
- ACPI_RESOURCE_TYPE_DMA
- ACPI_RESOURCE_TYPE_END_DEPENDENT
- ACPI_RESOURCE_TYPE_END_TAG
- ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64
- ACPI_RESOURCE_TYPE_EXTENDED_IRQ
- ACPI_RESOURCE_TYPE_FIXED_DMA
- ACPI_RESOURCE_TYPE_FIXED_IO
- ACPI_RESOURCE_TYPE_FIXED_MEMORY32
- ACPI_RESOURCE_TYPE_GENERIC_REGISTER
- ACPI_RESOURCE_TYPE_GPIO
- ACPI_RESOURCE_TYPE_IO
- ACPI_RESOURCE_TYPE_IRQ
- ACPI_RESOURCE_TYPE_MAX
- ACPI_RESOURCE_TYPE_MEMORY24
- ACPI_RESOURCE_TYPE_MEMORY32
- ACPI_RESOURCE_TYPE_PIN_CONFIG
- ACPI_RESOURCE_TYPE_PIN_FUNCTION
- ACPI_RESOURCE_TYPE_PIN_GROUP
- ACPI_RESOURCE_TYPE_PIN_GROUP_CONFIG
- ACPI_RESOURCE_TYPE_PIN_GROUP_FUNCTION
- ACPI_RESOURCE_TYPE_SERIAL_BUS
- ACPI_RESOURCE_TYPE_START_DEPENDENT
- ACPI_RESOURCE_TYPE_VENDOR
- ACPI_RESTAG_ACCESSSIZE
- ACPI_RESTAG_ADDRESS
- ACPI_RESTAG_ADDRESSSPACE
- ACPI_RESTAG_ALIGNMENT
- ACPI_RESTAG_BASEADDRESS
- ACPI_RESTAG_BUSMASTER
- ACPI_RESTAG_DEBOUNCETIME
- ACPI_RESTAG_DECODE
- ACPI_RESTAG_DEVICEPOLARITY
- ACPI_RESTAG_DMA
- ACPI_RESTAG_DMATYPE
- ACPI_RESTAG_DRIVESTRENGTH
- ACPI_RESTAG_ENDIANNESS
- ACPI_RESTAG_FLOWCONTROL
- ACPI_RESTAG_FUNCTION
- ACPI_RESTAG_GRANULARITY
- ACPI_RESTAG_INTERRUPT
- ACPI_RESTAG_INTERRUPTLEVEL
- ACPI_RESTAG_INTERRUPTSHARE
- ACPI_RESTAG_INTERRUPTTYPE
- ACPI_RESTAG_IORESTRICTION
- ACPI_RESTAG_LENGTH
- ACPI_RESTAG_LENGTH_RX
- ACPI_RESTAG_LENGTH_TX
- ACPI_RESTAG_LINE
- ACPI_RESTAG_MAXADDR
- ACPI_RESTAG_MAXTYPE
- ACPI_RESTAG_MEMATTRIBUTES
- ACPI_RESTAG_MEMTYPE
- ACPI_RESTAG_MINADDR
- ACPI_RESTAG_MINTYPE
- ACPI_RESTAG_MODE
- ACPI_RESTAG_PARITY
- ACPI_RESTAG_PHASE
- ACPI_RESTAG_PIN
- ACPI_RESTAG_PINCONFIG
- ACPI_RESTAG_PINCONFIG_TYPE
- ACPI_RESTAG_PINCONFIG_VALUE
- ACPI_RESTAG_POLARITY
- ACPI_RESTAG_RANGETYPE
- ACPI_RESTAG_READWRITETYPE
- ACPI_RESTAG_REGISTERBITOFFSET
- ACPI_RESTAG_REGISTERBITWIDTH
- ACPI_RESTAG_SLAVEMODE
- ACPI_RESTAG_SPEED
- ACPI_RESTAG_STOPBITS
- ACPI_RESTAG_TRANSLATION
- ACPI_RESTAG_TRANSTYPE
- ACPI_RESTAG_TYPE
- ACPI_RESTAG_TYPESPECIFICATTRIBUTES
- ACPI_RESTAG_VENDORDATA
- ACPI_RESTAG_XFERTYPE
- ACPI_RESULTS_FRAME_OBJ_NUM
- ACPI_RESULTS_OBJ_NUM_MAX
- ACPI_ROOT_ALLOW_RESIZE
- ACPI_ROOT_NAME
- ACPI_ROOT_OBJECT
- ACPI_ROOT_ORIGIN_ALLOCATED
- ACPI_ROOT_ORIGIN_UNKNOWN
- ACPI_ROOT_PATHNAME
- ACPI_ROOT_TABLE_SIZE_INCREMENT
- ACPI_ROUND_BITS_DOWN_TO_BYTES
- ACPI_ROUND_BITS_UP_TO_BYTES
- ACPI_ROUND_DOWN
- ACPI_ROUND_DOWN_POWER_OF_TWO_16
- ACPI_ROUND_DOWN_POWER_OF_TWO_32
- ACPI_ROUND_DOWN_POWER_OF_TWO_8
- ACPI_ROUND_DOWN_TO_32BIT
- ACPI_ROUND_DOWN_TO_64BIT
- ACPI_ROUND_DOWN_TO_NATIVE_WORD
- ACPI_ROUND_UP
- ACPI_ROUND_UP_POWER_OF_TWO_16
- ACPI_ROUND_UP_POWER_OF_TWO_32
- ACPI_ROUND_UP_POWER_OF_TWO_8
- ACPI_ROUND_UP_TO
- ACPI_ROUND_UP_TO_1K
- ACPI_ROUND_UP_TO_32BIT
- ACPI_ROUND_UP_TO_64BIT
- ACPI_ROUND_UP_TO_NATIVE_WORD
- ACPI_RSCONVERT_OPCODES
- ACPI_RSC_1BITFLAG
- ACPI_RSC_2BITFLAG
- ACPI_RSC_3BITFLAG
- ACPI_RSC_ADDRESS
- ACPI_RSC_BITMASK
- ACPI_RSC_BITMASK16
- ACPI_RSC_COMPARE_AML_LENGTH
- ACPI_RSC_COMPARE_VALUE
- ACPI_RSC_COUNT
- ACPI_RSC_COUNT16
- ACPI_RSC_COUNT_GPIO_PIN
- ACPI_RSC_COUNT_GPIO_RES
- ACPI_RSC_COUNT_GPIO_VEN
- ACPI_RSC_COUNT_SERIAL_RES
- ACPI_RSC_COUNT_SERIAL_VEN
- ACPI_RSC_DATA8
- ACPI_RSC_EXIT_EQ
- ACPI_RSC_EXIT_LE
- ACPI_RSC_EXIT_NE
- ACPI_RSC_FLAGINIT
- ACPI_RSC_INITGET
- ACPI_RSC_INITSET
- ACPI_RSC_LENGTH
- ACPI_RSC_MOVE16
- ACPI_RSC_MOVE32
- ACPI_RSC_MOVE64
- ACPI_RSC_MOVE8
- ACPI_RSC_MOVE_GPIO_PIN
- ACPI_RSC_MOVE_GPIO_RES
- ACPI_RSC_MOVE_SERIAL_RES
- ACPI_RSC_MOVE_SERIAL_VEN
- ACPI_RSC_SET8
- ACPI_RSC_SOURCE
- ACPI_RSC_SOURCEX
- ACPI_RSC_TABLE_SIZE
- ACPI_RSDP_CHECKSUM_LENGTH
- ACPI_RSDP_NAME
- ACPI_RSDP_SCAN_STEP
- ACPI_RSDP_XCHECKSUM_LENGTH
- ACPI_RSDT_ENTRY_SIZE
- ACPI_RSDUMP_OPCODES
- ACPI_RSD_1BITFLAG
- ACPI_RSD_2BITFLAG
- ACPI_RSD_3BITFLAG
- ACPI_RSD_ADDRESS
- ACPI_RSD_DWORDLIST
- ACPI_RSD_LABEL
- ACPI_RSD_LITERAL
- ACPI_RSD_LONGLIST
- ACPI_RSD_OFFSET
- ACPI_RSD_SHORTLIST
- ACPI_RSD_SHORTLISTX
- ACPI_RSD_SOURCE
- ACPI_RSD_SOURCE_LABEL
- ACPI_RSD_STRING
- ACPI_RSD_TABLE_SIZE
- ACPI_RSD_TITLE
- ACPI_RSD_UINT16
- ACPI_RSD_UINT32
- ACPI_RSD_UINT64
- ACPI_RSD_UINT8
- ACPI_RSD_WORDLIST
- ACPI_RS_DUMP_COMMON_SERIAL_BUS
- ACPI_RS_OFFSET
- ACPI_RS_SIZE
- ACPI_RS_SIZE_MIN
- ACPI_RS_SIZE_NO_DATA
- ACPI_RTYPE_ALL
- ACPI_RTYPE_ANY
- ACPI_RTYPE_BUFFER
- ACPI_RTYPE_INTEGER
- ACPI_RTYPE_NONE
- ACPI_RTYPE_PACKAGE
- ACPI_RTYPE_REFERENCE
- ACPI_RTYPE_STRING
- ACPI_S3PT_TYPE_RESUME
- ACPI_S3PT_TYPE_SUSPEND
- ACPI_SAR_NUM_CHAIN_LIMITS
- ACPI_SAR_NUM_SUB_BANDS
- ACPI_SAR_PROFILE_NUM
- ACPI_SAR_TABLE_SIZE
- ACPI_SBS_BATTERY
- ACPI_SBS_BLOCK_MAX
- ACPI_SBS_CHARGER
- ACPI_SBS_CLASS
- ACPI_SBS_COMPONENT
- ACPI_SBS_DEVICE_NAME
- ACPI_SBS_FILE_ALARM
- ACPI_SBS_FILE_INFO
- ACPI_SBS_FILE_STATE
- ACPI_SBS_MANAGER
- ACPI_SBS_NOTIFY_INFO
- ACPI_SBS_NOTIFY_STATUS
- ACPI_SB_INDICATE_INTERVAL
- ACPI_SB_NOTIFY_SHUTDOWN_REQUEST
- ACPI_SDEV_HANDOFF_TO_UNSECURE_OS
- ACPI_SDEV_TYPE_NAMESPACE_DEVICE
- ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE
- ACPI_SDEV_TYPE_RESERVED
- ACPI_SERIALIZED
- ACPI_SERIAL_HEADER_SIZE
- ACPI_SET16
- ACPI_SET32
- ACPI_SET64
- ACPI_SET8
- ACPI_SET_BIT
- ACPI_SET_BITS
- ACPI_SET_DESCRIPTOR_PTR
- ACPI_SET_DESCRIPTOR_TYPE
- ACPI_SHARED
- ACPI_SHIFT_RIGHT_64
- ACPI_SIGNAL_BREAKPOINT
- ACPI_SIGNAL_FATAL
- ACPI_SIGN_NEGATIVE
- ACPI_SIGN_POSITIVE
- ACPI_SIG_ASF
- ACPI_SIG_ATKG
- ACPI_SIG_BERT
- ACPI_SIG_BGRT
- ACPI_SIG_BOOT
- ACPI_SIG_CPEP
- ACPI_SIG_CSRT
- ACPI_SIG_DBG2
- ACPI_SIG_DBGP
- ACPI_SIG_DMAR
- ACPI_SIG_DRTM
- ACPI_SIG_DSDT
- ACPI_SIG_ECDT
- ACPI_SIG_EINJ
- ACPI_SIG_ERST
- ACPI_SIG_FACS
- ACPI_SIG_FADT
- ACPI_SIG_FPDT
- ACPI_SIG_GSCI
- ACPI_SIG_GTDT
- ACPI_SIG_HEST
- ACPI_SIG_HMAT
- ACPI_SIG_HPET
- ACPI_SIG_IBFT
- ACPI_SIG_IEIT
- ACPI_SIG_IORT
- ACPI_SIG_IVRS
- ACPI_SIG_LPIT
- ACPI_SIG_MADT
- ACPI_SIG_MATR
- ACPI_SIG_MCFG
- ACPI_SIG_MCHI
- ACPI_SIG_MPST
- ACPI_SIG_MSCT
- ACPI_SIG_MSDM
- ACPI_SIG_MTMR
- ACPI_SIG_NFIT
- ACPI_SIG_OSDT
- ACPI_SIG_PCCS
- ACPI_SIG_PCCT
- ACPI_SIG_PDTT
- ACPI_SIG_PMTT
- ACPI_SIG_PPTT
- ACPI_SIG_PSDT
- ACPI_SIG_RASF
- ACPI_SIG_RSDP
- ACPI_SIG_RSDT
- ACPI_SIG_S3PT
- ACPI_SIG_SBST
- ACPI_SIG_SDEI
- ACPI_SIG_SDEV
- ACPI_SIG_SLIC
- ACPI_SIG_SLIT
- ACPI_SIG_SPCR
- ACPI_SIG_SPMI
- ACPI_SIG_SRAT
- ACPI_SIG_SSDT
- ACPI_SIG_STAO
- ACPI_SIG_TCPA
- ACPI_SIG_TPM2
- ACPI_SIG_UEFI
- ACPI_SIG_VRTC
- ACPI_SIG_WAET
- ACPI_SIG_WDAT
- ACPI_SIG_WDDT
- ACPI_SIG_WDRT
- ACPI_SIG_WPBT
- ACPI_SIG_WSMT
- ACPI_SIG_XENV
- ACPI_SIG_XSDT
- ACPI_SIG_XXXX
- ACPI_SINGLE_NAME
- ACPI_SINGLE_THREADED
- ACPI_SIZE_MAX
- ACPI_SLEEP_TYPE_INVALID
- ACPI_SLEEP_TYPE_MAX
- ACPI_SMALL_VARIABLE_LENGTH
- ACPI_SMBUS_BUFFER_SIZE
- ACPI_SMBUS_DATA_SIZE
- ACPI_SMBUS_HC_CLASS
- ACPI_SMBUS_HC_DEVICE_NAME
- ACPI_SMBUS_IBM_HID
- ACPI_SMBUS_MS_HID
- ACPI_SMBUS_PRTCL_BLOCK_DATA
- ACPI_SMBUS_PRTCL_BYTE
- ACPI_SMBUS_PRTCL_BYTE_DATA
- ACPI_SMBUS_PRTCL_QUICK
- ACPI_SMBUS_PRTCL_READ
- ACPI_SMBUS_PRTCL_WORD_DATA
- ACPI_SMBUS_PRTCL_WRITE
- ACPI_SMBUS_STATUS_ACC_DENY
- ACPI_SMBUS_STATUS_BUSY
- ACPI_SMBUS_STATUS_CMD_DENY
- ACPI_SMBUS_STATUS_DERR
- ACPI_SMBUS_STATUS_DNAK
- ACPI_SMBUS_STATUS_FAIL
- ACPI_SMBUS_STATUS_NOTSUP
- ACPI_SMBUS_STATUS_OK
- ACPI_SMBUS_STATUS_PEC
- ACPI_SMBUS_STATUS_TIMEOUT
- ACPI_SMBUS_STATUS_UNKNOWN
- ACPI_SMB_ADDRESS
- ACPI_SMB_ALARM_ADDRESS
- ACPI_SMB_ALARM_DATA
- ACPI_SMB_BLOCK_COUNT
- ACPI_SMB_COMMAND
- ACPI_SMB_DATA
- ACPI_SMB_HC_CLASS
- ACPI_SMB_HC_DEVICE_NAME
- ACPI_SMB_PROTOCOL
- ACPI_SMB_STATUS
- ACPI_SORT_ASCENDING
- ACPI_SORT_DESCENDING
- ACPI_SPACE_MEM
- ACPI_SPARSE_TRANSLATION
- ACPI_SPCR_DO_NOT_DISABLE
- ACPI_SPECIFIC_NOTIFY_MAX
- ACPI_SPI_3WIRE_MODE
- ACPI_SPI_4WIRE_MODE
- ACPI_SPI_ACTIVE_HIGH
- ACPI_SPI_ACTIVE_LOW
- ACPI_SPI_FIRST_PHASE
- ACPI_SPI_SECOND_PHASE
- ACPI_SPI_START_HIGH
- ACPI_SPI_START_LOW
- ACPI_SPLC_METHOD
- ACPI_SPLC_WIFI_DATA_SIZE
- ACPI_SPMI_BLOCK_TRANSFER
- ACPI_SPMI_KEYBOARD
- ACPI_SPMI_NOT_USED
- ACPI_SPMI_RESERVED
- ACPI_SPMI_SMBUS
- ACPI_SPMI_SMI
- ACPI_SRAT_CPU_ENABLED
- ACPI_SRAT_CPU_USE_AFFINITY
- ACPI_SRAT_GENERIC_AFFINITY_ENABLED
- ACPI_SRAT_GICC_ENABLED
- ACPI_SRAT_MEM_ENABLED
- ACPI_SRAT_MEM_HOT_PLUGGABLE
- ACPI_SRAT_MEM_NON_VOLATILE
- ACPI_SRAT_TYPE_CPU_AFFINITY
- ACPI_SRAT_TYPE_GENERIC_AFFINITY
- ACPI_SRAT_TYPE_GICC_AFFINITY
- ACPI_SRAT_TYPE_GIC_ITS_AFFINITY
- ACPI_SRAT_TYPE_MEMORY_AFFINITY
- ACPI_SRAT_TYPE_RESERVED
- ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY
- ACPI_SST_INDICATOR_OFF
- ACPI_SST_SLEEPING
- ACPI_SST_SLEEP_CONTEXT
- ACPI_SST_WAKING
- ACPI_SST_WORKING
- ACPI_STATE_C0
- ACPI_STATE_C1
- ACPI_STATE_C2
- ACPI_STATE_C3
- ACPI_STATE_CIR_BIT
- ACPI_STATE_COMMON
- ACPI_STATE_D0
- ACPI_STATE_D1
- ACPI_STATE_D2
- ACPI_STATE_D3
- ACPI_STATE_D3_COLD
- ACPI_STATE_D3_HOT
- ACPI_STATE_S0
- ACPI_STATE_S1
- ACPI_STATE_S2
- ACPI_STATE_S3
- ACPI_STATE_S4
- ACPI_STATE_S5
- ACPI_STATE_UNKNOWN
- ACPI_STA_ALL
- ACPI_STA_BATTERY_PRESENT
- ACPI_STA_DEFAULT
- ACPI_STA_DEVICE_ENABLED
- ACPI_STA_DEVICE_FUNCTIONING
- ACPI_STA_DEVICE_OK
- ACPI_STA_DEVICE_PRESENT
- ACPI_STA_DEVICE_UI
- ACPI_STRUCT_INIT
- ACPI_SUBSYSTEM_INITIALIZE
- ACPI_SUBTABLE_COMMON
- ACPI_SUBTABLE_HMAT
- ACPI_SUB_DECODE
- ACPI_SUB_OPTIMAL_CONFIGURATION
- ACPI_SUB_PTR
- ACPI_SUCCESS
- ACPI_SW_PATROL_SCRUB_EXPOSED
- ACPI_SYSTEM_COMPONENT
- ACPI_SYSTEM_HANDLER_LIST
- ACPI_SYSTEM_HID
- ACPI_SYSTEM_NOTIFY
- ACPI_SYSTEM_XFACE
- ACPI_SYS_MODES_MASK
- ACPI_SYS_MODE_ACPI
- ACPI_SYS_MODE_LEGACY
- ACPI_SYS_MODE_UNKNOWN
- ACPI_S_STATES_MAX
- ACPI_S_STATE_COUNT
- ACPI_TABLE
- ACPI_TABLES
- ACPI_TABLE_EVENT_INSTALL
- ACPI_TABLE_EVENT_LOAD
- ACPI_TABLE_EVENT_UNINSTALL
- ACPI_TABLE_EVENT_UNLOAD
- ACPI_TABLE_EXCEPTION
- ACPI_TABLE_GUID
- ACPI_TABLE_ID_LEN
- ACPI_TABLE_IS_LOADED
- ACPI_TABLE_IS_VERIFIED
- ACPI_TABLE_ORIGIN_EXTERNAL_VIRTUAL
- ACPI_TABLE_ORIGIN_INTERNAL_PHYSICAL
- ACPI_TABLE_ORIGIN_INTERNAL_VIRTUAL
- ACPI_TABLE_ORIGIN_MASK
- ACPI_TABLE_UPGRADE_MAX_PHYS
- ACPI_TAD_AC_S4_WAKE
- ACPI_TAD_AC_S5_WAKE
- ACPI_TAD_AC_TIMER
- ACPI_TAD_AC_WAKE
- ACPI_TAD_DC_S4_WAKE
- ACPI_TAD_DC_S5_WAKE
- ACPI_TAD_DC_TIMER
- ACPI_TAD_DC_WAKE
- ACPI_TAD_RT
- ACPI_TAD_RT_IN_MS
- ACPI_TAD_S4_S5__GWS
- ACPI_TAD_WAKE_DISABLED
- ACPI_TCPA_ADDRESS_VALID
- ACPI_TCPA_BUS_PNP
- ACPI_TCPA_CLIENT_TABLE
- ACPI_TCPA_GLOBAL_INTERRUPT
- ACPI_TCPA_INTERRUPT_MODE
- ACPI_TCPA_INTERRUPT_POLARITY
- ACPI_TCPA_PCI_DEVICE
- ACPI_TCPA_SCI_VIA_GPE
- ACPI_TCPA_SERVER_TABLE
- ACPI_TCPA_SIG
- ACPI_THERMAL_CLASS
- ACPI_THERMAL_COMPONENT
- ACPI_THERMAL_DEVICE_NAME
- ACPI_THERMAL_GET_ART
- ACPI_THERMAL_GET_ART_COUNT
- ACPI_THERMAL_GET_ART_LEN
- ACPI_THERMAL_GET_TRT
- ACPI_THERMAL_GET_TRT_COUNT
- ACPI_THERMAL_GET_TRT_LEN
- ACPI_THERMAL_HID
- ACPI_THERMAL_MAGIC
- ACPI_THERMAL_MAX_ACTIVE
- ACPI_THERMAL_MAX_LIMIT_STR_LEN
- ACPI_THERMAL_MODE_ACTIVE
- ACPI_THERMAL_NOTIFY_CRITICAL
- ACPI_THERMAL_NOTIFY_DEVICES
- ACPI_THERMAL_NOTIFY_HOT
- ACPI_THERMAL_NOTIFY_TEMPERATURE
- ACPI_THERMAL_NOTIFY_THRESHOLDS
- ACPI_THERMAL_TRIPS_EXCEPTION
- ACPI_TIME_AFTER
- ACPI_TOOLS
- ACPI_TOTAL_TYPES
- ACPI_TO_INTEGER
- ACPI_TO_POINTER
- ACPI_TO_RAW
- ACPI_TPM23_ACPI_START_METHOD
- ACPI_TPM2_COMMAND_BUFFER
- ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC
- ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD
- ACPI_TPM2_IDLE_SUPPORT
- ACPI_TPM2_INTERRUPT_SUPPORT
- ACPI_TPM2_MEMORY_MAPPED
- ACPI_TPM2_NOT_ALLOWED
- ACPI_TPM2_RESERVED
- ACPI_TPM2_RESERVED1
- ACPI_TPM2_RESERVED10
- ACPI_TPM2_RESERVED3
- ACPI_TPM2_RESERVED4
- ACPI_TPM2_RESERVED5
- ACPI_TPM2_RESERVED9
- ACPI_TPM2_START_METHOD
- ACPI_TRACE_AML_METHOD
- ACPI_TRACE_AML_OPCODE
- ACPI_TRACE_AML_REGION
- ACPI_TRACE_ENABLED
- ACPI_TRACE_ENTRY
- ACPI_TRACE_EXIT
- ACPI_TRACE_LAYER_ALL
- ACPI_TRACE_LAYER_DEFAULT
- ACPI_TRACE_LEVEL_ALL
- ACPI_TRACE_LEVEL_DEFAULT
- ACPI_TRACE_ONESHOT
- ACPI_TRACE_OPCODE
- ACPI_TRACE_POINT
- ACPI_TRANSFER_16
- ACPI_TRANSFER_8
- ACPI_TRANSFER_8_16
- ACPI_TRIPS_ACTIVE
- ACPI_TRIPS_CRITICAL
- ACPI_TRIPS_DEVICES
- ACPI_TRIPS_HOT
- ACPI_TRIPS_INIT
- ACPI_TRIPS_PASSIVE
- ACPI_TRIPS_REFRESH_DEVICES
- ACPI_TRIPS_REFRESH_THRESHOLDS
- ACPI_TSD_REV0_ENTRIES
- ACPI_TSD_REV0_REVISION
- ACPI_TYPE_A
- ACPI_TYPE_ANY
- ACPI_TYPE_B
- ACPI_TYPE_BUFFER
- ACPI_TYPE_BUFFER_FIELD
- ACPI_TYPE_DDB_HANDLE
- ACPI_TYPE_DEBUG_OBJECT
- ACPI_TYPE_DEVICE
- ACPI_TYPE_EVENT
- ACPI_TYPE_EXTERNAL_MAX
- ACPI_TYPE_F
- ACPI_TYPE_FIELD_UNIT
- ACPI_TYPE_INTEGER
- ACPI_TYPE_INVALID
- ACPI_TYPE_LOCAL_ADDRESS_HANDLER
- ACPI_TYPE_LOCAL_ALIAS
- ACPI_TYPE_LOCAL_BANK_FIELD
- ACPI_TYPE_LOCAL_DATA
- ACPI_TYPE_LOCAL_EXTRA
- ACPI_TYPE_LOCAL_INDEX_FIELD
- ACPI_TYPE_LOCAL_MAX
- ACPI_TYPE_LOCAL_METHOD_ALIAS
- ACPI_TYPE_LOCAL_NOTIFY
- ACPI_TYPE_LOCAL_REFERENCE
- ACPI_TYPE_LOCAL_REGION_FIELD
- ACPI_TYPE_LOCAL_RESOURCE
- ACPI_TYPE_LOCAL_RESOURCE_FIELD
- ACPI_TYPE_LOCAL_SCOPE
- ACPI_TYPE_METHOD
- ACPI_TYPE_MUTEX
- ACPI_TYPE_NOT_FOUND
- ACPI_TYPE_NS_NODE_MAX
- ACPI_TYPE_PACKAGE
- ACPI_TYPE_POWER
- ACPI_TYPE_PROCESSOR
- ACPI_TYPE_REGION
- ACPI_TYPE_STRING
- ACPI_TYPE_THERMAL
- ACPI_UART_1P5_STOP_BITS
- ACPI_UART_1_STOP_BIT
- ACPI_UART_2_STOP_BITS
- ACPI_UART_5_DATA_BITS
- ACPI_UART_6_DATA_BITS
- ACPI_UART_7_DATA_BITS
- ACPI_UART_8_DATA_BITS
- ACPI_UART_9_DATA_BITS
- ACPI_UART_BIG_ENDIAN
- ACPI_UART_CARRIER_DETECT
- ACPI_UART_CLEAR_TO_SEND
- ACPI_UART_DATA_SET_READY
- ACPI_UART_DATA_TERMINAL_READY
- ACPI_UART_FLOW_CONTROL_HW
- ACPI_UART_FLOW_CONTROL_NONE
- ACPI_UART_FLOW_CONTROL_XON_XOFF
- ACPI_UART_LITTLE_ENDIAN
- ACPI_UART_NO_STOP_BITS
- ACPI_UART_PARITY_EVEN
- ACPI_UART_PARITY_MARK
- ACPI_UART_PARITY_NONE
- ACPI_UART_PARITY_ODD
- ACPI_UART_PARITY_SPACE
- ACPI_UART_REQUEST_TO_SEND
- ACPI_UART_RING_INDICATOR
- ACPI_UINT16_MAX
- ACPI_UINT32_MAX
- ACPI_UINT64_MAX
- ACPI_UINT8_MAX
- ACPI_UNKNOWN_NAME
- ACPI_UNUSED_VAR
- ACPI_USAGE_HEADER
- ACPI_USAGE_TEXT
- ACPI_USEC_PER_MSEC
- ACPI_USEC_PER_SEC
- ACPI_USER_REGION_BEGIN
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_acquire_object
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_acquire_raw_lock
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_allocate
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_allocate_zeroed
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_close_directory
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_create_lock
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_create_raw_lock
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_delete_raw_lock
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_free
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_next_filename
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_table_by_address
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_table_by_index
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_table_by_name
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_thread_id
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_initialize
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_initialize_debugger
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_open_directory
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_readable
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_redirect_output
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_release_raw_lock
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_terminate
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_terminate_debugger
- ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_writable
- ACPI_USE_DO_WHILE_0
- ACPI_USE_GPE_POLLING
- ACPI_USE_LOCAL_CACHE
- ACPI_USE_NATIVE_DIVIDE
- ACPI_USE_NATIVE_MATH64
- ACPI_USE_NATIVE_MEMORY_MAPPING
- ACPI_USE_NATIVE_RSDP_POINTER
- ACPI_USE_STANDARD_HEADERS
- ACPI_USE_SYSTEM_CLIBRARY
- ACPI_USE_SYSTEM_INTTYPES
- ACPI_UTILITIES
- ACPI_UUID_LENGTH
- ACPI_VALIDATE_RSDP_SIG
- ACPI_VALID_ADR
- ACPI_VALID_CID
- ACPI_VALID_CLS
- ACPI_VALID_HID
- ACPI_VALID_SXDS
- ACPI_VALID_SXWS
- ACPI_VALID_UID
- ACPI_VARIABLE_LENGTH
- ACPI_VAR_ARGS
- ACPI_VENDOR_SPECIFIC_MASK
- ACPI_VENDOR_SPECIFIC_SHIFT
- ACPI_VENDOR_STRINGS
- ACPI_VIDEO_AC_LEVEL
- ACPI_VIDEO_BACKLIGHT
- ACPI_VIDEO_BACKLIGHT_DMI_VENDOR
- ACPI_VIDEO_BACKLIGHT_DMI_VIDEO
- ACPI_VIDEO_BACKLIGHT_FORCE_VENDOR
- ACPI_VIDEO_BACKLIGHT_FORCE_VIDEO
- ACPI_VIDEO_BATTERY_LEVEL
- ACPI_VIDEO_BUS_NAME
- ACPI_VIDEO_CLASS
- ACPI_VIDEO_COMPONENT
- ACPI_VIDEO_DEVICE_NAME
- ACPI_VIDEO_DEVICE_POSTING
- ACPI_VIDEO_DISPLAY_CRT
- ACPI_VIDEO_DISPLAY_DVI
- ACPI_VIDEO_DISPLAY_LCD
- ACPI_VIDEO_DISPLAY_LEGACY_MONITOR
- ACPI_VIDEO_DISPLAY_LEGACY_PANEL
- ACPI_VIDEO_DISPLAY_LEGACY_TV
- ACPI_VIDEO_DISPLAY_TV
- ACPI_VIDEO_FIRST_LEVEL
- ACPI_VIDEO_HID
- ACPI_VIDEO_NOTIFY_CYCLE
- ACPI_VIDEO_NOTIFY_CYCLE_BRIGHTNESS
- ACPI_VIDEO_NOTIFY_DEC_BRIGHTNESS
- ACPI_VIDEO_NOTIFY_DISPLAY_OFF
- ACPI_VIDEO_NOTIFY_INC_BRIGHTNESS
- ACPI_VIDEO_NOTIFY_NEXT_OUTPUT
- ACPI_VIDEO_NOTIFY_PREV_OUTPUT
- ACPI_VIDEO_NOTIFY_PROBE
- ACPI_VIDEO_NOTIFY_SWITCH
- ACPI_VIDEO_NOTIFY_ZERO_BRIGHTNESS
- ACPI_VIDEO_OUTPUT_SWITCHING
- ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VENDOR
- ACPI_VIDEO_OUTPUT_SWITCHING_DMI_VIDEO
- ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VENDOR
- ACPI_VIDEO_OUTPUT_SWITCHING_FORCE_VIDEO
- ACPI_VIDEO_ROM_AVAILABLE
- ACPI_VOLTAGE_EN
- ACPI_VPRINTF_BUFFER_SIZE
- ACPI_WAET_RTC_NO_ACK
- ACPI_WAET_TIMER_ONE_READ
- ACPI_WAIT_FOREVER
- ACPI_WAKE_CAPABLE
- ACPI_WAKE_EN_CIR_BIT
- ACPI_WALK_METHOD
- ACPI_WALK_METHOD_RESTART
- ACPI_WALK_NON_METHOD
- ACPI_WALK_OPERANDS
- ACPI_WARNING
- ACPI_WARN_ALWAYS
- ACPI_WARN_PREDEFINED
- ACPI_WDAT_ACTION_RESERVED
- ACPI_WDAT_ENABLED
- ACPI_WDAT_GET_COUNTDOWN
- ACPI_WDAT_GET_CURRENT_COUNTDOWN
- ACPI_WDAT_GET_REBOOT
- ACPI_WDAT_GET_RUNNING_STATE
- ACPI_WDAT_GET_SHUTDOWN
- ACPI_WDAT_GET_STATUS
- ACPI_WDAT_GET_STOPPED_STATE
- ACPI_WDAT_INSTRUCTION_RESERVED
- ACPI_WDAT_PRESERVE_REGISTER
- ACPI_WDAT_READ_COUNTDOWN
- ACPI_WDAT_READ_VALUE
- ACPI_WDAT_RESET
- ACPI_WDAT_SET_COUNTDOWN
- ACPI_WDAT_SET_REBOOT
- ACPI_WDAT_SET_RUNNING_STATE
- ACPI_WDAT_SET_SHUTDOWN
- ACPI_WDAT_SET_STATUS
- ACPI_WDAT_SET_STOPPED_STATE
- ACPI_WDAT_STOPPED
- ACPI_WDAT_WRITE_COUNTDOWN
- ACPI_WDAT_WRITE_VALUE
- ACPI_WDDT_ACTIVE
- ACPI_WDDT_ALERT_SUPPORT
- ACPI_WDDT_AUTO_RESET
- ACPI_WDDT_AVAILABLE
- ACPI_WDDT_POWER_FAIL
- ACPI_WDDT_TCO_OS_OWNED
- ACPI_WDDT_UNKNOWN_RESET
- ACPI_WDDT_USER_RESET
- ACPI_WDDT_WDT_RESET
- ACPI_WGDS_METHOD
- ACPI_WGDS_NUM_BANDS
- ACPI_WGDS_TABLE_SIZE
- ACPI_WGDS_WIFI_DATA_SIZE
- ACPI_WIDTH
- ACPI_WIFI_DOMAIN
- ACPI_WMI_EVENT
- ACPI_WMI_EXPENSIVE
- ACPI_WMI_METHOD
- ACPI_WMI_STRING
- ACPI_WRDD_METHOD
- ACPI_WRDD_WIFI_DATA_SIZE
- ACPI_WRDS_METHOD
- ACPI_WRDS_WIFI_DATA_SIZE
- ACPI_WRITE
- ACPI_WRITE_COMBINING_MEMORY
- ACPI_WSMT_COMM_BUFFER_NESTED_PTR_PROTECTION
- ACPI_WSMT_FIXED_COMM_BUFFERS
- ACPI_WSMT_SYSTEM_RESOURCE_PROTECTION
- ACPI_XSDT_ENTRY_SIZE
- ACPI_X_SLEEP_ENABLE
- ACPI_X_SLEEP_TYPE_MASK
- ACPI_X_SLEEP_TYPE_POSITION
- ACPI_X_WAKE_STATUS
- ACPU
- ACPU_DFS_CUR_FREQ
- ACPU_DFS_FLAG
- ACPU_DFS_FREQ_LMT
- ACPU_DFS_FREQ_MAX
- ACPU_DFS_FREQ_REQ
- ACPU_DFS_LOCK_FLAG
- ACPU_FULL
- ACPU_HALF
- ACP_2_2_D_H
- ACP_2_2_ENUM_H
- ACP_2_2_SH_MASK_H
- ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK
- ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT
- ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK
- ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK
- ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK
- ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK
- ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK
- ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT
- ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT
- ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK
- ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT
- ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK
- ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT
- ACP_BASE__INST0_SEG0
- ACP_BASE__INST0_SEG1
- ACP_BASE__INST0_SEG2
- ACP_BASE__INST0_SEG3
- ACP_BASE__INST0_SEG4
- ACP_BASE__INST1_SEG0
- ACP_BASE__INST1_SEG1
- ACP_BASE__INST1_SEG2
- ACP_BASE__INST1_SEG3
- ACP_BASE__INST1_SEG4
- ACP_BASE__INST2_SEG0
- ACP_BASE__INST2_SEG1
- ACP_BASE__INST2_SEG2
- ACP_BASE__INST2_SEG3
- ACP_BASE__INST2_SEG4
- ACP_BASE__INST3_SEG0
- ACP_BASE__INST3_SEG1
- ACP_BASE__INST3_SEG2
- ACP_BASE__INST3_SEG3
- ACP_BASE__INST3_SEG4
- ACP_BASE__INST4_SEG0
- ACP_BASE__INST4_SEG1
- ACP_BASE__INST4_SEG2
- ACP_BASE__INST4_SEG3
- ACP_BASE__INST4_SEG4
- ACP_BASE__INST5_SEG0
- ACP_BASE__INST5_SEG1
- ACP_BASE__INST5_SEG2
- ACP_BASE__INST5_SEG3
- ACP_BASE__INST5_SEG4
- ACP_BASE__INST6_SEG0
- ACP_BASE__INST6_SEG1
- ACP_BASE__INST6_SEG2
- ACP_BASE__INST6_SEG3
- ACP_BASE__INST6_SEG4
- ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK
- ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT
- ACP_BT_COMP1_REG_OFFSET
- ACP_BT_COMP2_REG_OFFSET
- ACP_BT_PLAY_REGS_END
- ACP_BT_PLAY_REGS_START
- ACP_BT_UART_PAD_SELECT_MASK
- ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK
- ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT
- ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK
- ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT
- ACP_CAPTURE_PTE_OFFSET
- ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK
- ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT
- ACP_CLOCK_EN_TIME_OUT_VALUE
- ACP_CONFIG__ACP_RDREQ_URG_MASK
- ACP_CONFIG__ACP_RDREQ_URG__SHIFT
- ACP_CONFIG__ACP_REQ_TRAN_MASK
- ACP_CONFIG__ACP_REQ_TRAN__SHIFT
- ACP_CONTROL__ClkEn_MASK
- ACP_CONTROL__ClkEn__SHIFT
- ACP_CONTROL__JtagEn_MASK
- ACP_CONTROL__JtagEn__SHIFT
- ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK
- ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT
- ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK
- ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT
- ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK
- ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT
- ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK
- ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT
- ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK
- ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT
- ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK
- ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT
- ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK
- ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT
- ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK
- ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT
- ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK
- ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT
- ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK
- ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT
- ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK
- ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT
- ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK
- ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT
- ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK
- ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT
- ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK
- ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT
- ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK
- ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT
- ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK
- ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT
- ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK
- ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT
- ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK
- ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT
- ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK
- ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT
- ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK
- ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT
- ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK
- ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK
- ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK
- ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT
- ACP_DAGB_GRP_SRAM_BASE_ADDRESS
- ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK
- ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK
- ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK
- ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT
- ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK
- ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT
- ACP_DEVS
- ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM
- ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM
- ACP_DMA_ATTR_FORCE_SIZE
- ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION
- ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC
- ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK
- ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT
- ACP_DMA_CH_STS__DMAChSts_MASK
- ACP_DMA_CH_STS__DMAChSts__SHIFT
- ACP_DMA_CNTL_0__Circular_DMA_En_MASK
- ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_0__DMAChIOCEn_MASK
- ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_0__DMAChRst_MASK
- ACP_DMA_CNTL_0__DMAChRst__SHIFT
- ACP_DMA_CNTL_0__DMAChRun_MASK
- ACP_DMA_CNTL_0__DMAChRun__SHIFT
- ACP_DMA_CNTL_10__Circular_DMA_En_MASK
- ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_10__DMAChIOCEn_MASK
- ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_10__DMAChRst_MASK
- ACP_DMA_CNTL_10__DMAChRst__SHIFT
- ACP_DMA_CNTL_10__DMAChRun_MASK
- ACP_DMA_CNTL_10__DMAChRun__SHIFT
- ACP_DMA_CNTL_11__Circular_DMA_En_MASK
- ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_11__DMAChIOCEn_MASK
- ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_11__DMAChRst_MASK
- ACP_DMA_CNTL_11__DMAChRst__SHIFT
- ACP_DMA_CNTL_11__DMAChRun_MASK
- ACP_DMA_CNTL_11__DMAChRun__SHIFT
- ACP_DMA_CNTL_12__Circular_DMA_En_MASK
- ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_12__DMAChIOCEn_MASK
- ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_12__DMAChRst_MASK
- ACP_DMA_CNTL_12__DMAChRst__SHIFT
- ACP_DMA_CNTL_12__DMAChRun_MASK
- ACP_DMA_CNTL_12__DMAChRun__SHIFT
- ACP_DMA_CNTL_13__Circular_DMA_En_MASK
- ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_13__DMAChIOCEn_MASK
- ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_13__DMAChRst_MASK
- ACP_DMA_CNTL_13__DMAChRst__SHIFT
- ACP_DMA_CNTL_13__DMAChRun_MASK
- ACP_DMA_CNTL_13__DMAChRun__SHIFT
- ACP_DMA_CNTL_14__Circular_DMA_En_MASK
- ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_14__DMAChIOCEn_MASK
- ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_14__DMAChRst_MASK
- ACP_DMA_CNTL_14__DMAChRst__SHIFT
- ACP_DMA_CNTL_14__DMAChRun_MASK
- ACP_DMA_CNTL_14__DMAChRun__SHIFT
- ACP_DMA_CNTL_15__Circular_DMA_En_MASK
- ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_15__DMAChIOCEn_MASK
- ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_15__DMAChRst_MASK
- ACP_DMA_CNTL_15__DMAChRst__SHIFT
- ACP_DMA_CNTL_15__DMAChRun_MASK
- ACP_DMA_CNTL_15__DMAChRun__SHIFT
- ACP_DMA_CNTL_1__Circular_DMA_En_MASK
- ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_1__DMAChIOCEn_MASK
- ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_1__DMAChRst_MASK
- ACP_DMA_CNTL_1__DMAChRst__SHIFT
- ACP_DMA_CNTL_1__DMAChRun_MASK
- ACP_DMA_CNTL_1__DMAChRun__SHIFT
- ACP_DMA_CNTL_2__Circular_DMA_En_MASK
- ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_2__DMAChIOCEn_MASK
- ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_2__DMAChRst_MASK
- ACP_DMA_CNTL_2__DMAChRst__SHIFT
- ACP_DMA_CNTL_2__DMAChRun_MASK
- ACP_DMA_CNTL_2__DMAChRun__SHIFT
- ACP_DMA_CNTL_3__Circular_DMA_En_MASK
- ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_3__DMAChIOCEn_MASK
- ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_3__DMAChRst_MASK
- ACP_DMA_CNTL_3__DMAChRst__SHIFT
- ACP_DMA_CNTL_3__DMAChRun_MASK
- ACP_DMA_CNTL_3__DMAChRun__SHIFT
- ACP_DMA_CNTL_4__Circular_DMA_En_MASK
- ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_4__DMAChIOCEn_MASK
- ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_4__DMAChRst_MASK
- ACP_DMA_CNTL_4__DMAChRst__SHIFT
- ACP_DMA_CNTL_4__DMAChRun_MASK
- ACP_DMA_CNTL_4__DMAChRun__SHIFT
- ACP_DMA_CNTL_5__Circular_DMA_En_MASK
- ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_5__DMAChIOCEn_MASK
- ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_5__DMAChRst_MASK
- ACP_DMA_CNTL_5__DMAChRst__SHIFT
- ACP_DMA_CNTL_5__DMAChRun_MASK
- ACP_DMA_CNTL_5__DMAChRun__SHIFT
- ACP_DMA_CNTL_6__Circular_DMA_En_MASK
- ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_6__DMAChIOCEn_MASK
- ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_6__DMAChRst_MASK
- ACP_DMA_CNTL_6__DMAChRst__SHIFT
- ACP_DMA_CNTL_6__DMAChRun_MASK
- ACP_DMA_CNTL_6__DMAChRun__SHIFT
- ACP_DMA_CNTL_7__Circular_DMA_En_MASK
- ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_7__DMAChIOCEn_MASK
- ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_7__DMAChRst_MASK
- ACP_DMA_CNTL_7__DMAChRst__SHIFT
- ACP_DMA_CNTL_7__DMAChRun_MASK
- ACP_DMA_CNTL_7__DMAChRun__SHIFT
- ACP_DMA_CNTL_8__Circular_DMA_En_MASK
- ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_8__DMAChIOCEn_MASK
- ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_8__DMAChRst_MASK
- ACP_DMA_CNTL_8__DMAChRst__SHIFT
- ACP_DMA_CNTL_8__DMAChRun_MASK
- ACP_DMA_CNTL_8__DMAChRun__SHIFT
- ACP_DMA_CNTL_9__Circular_DMA_En_MASK
- ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT
- ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK
- ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT
- ACP_DMA_CNTL_9__DMAChIOCEn_MASK
- ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT
- ACP_DMA_CNTL_9__DMAChRst_MASK
- ACP_DMA_CNTL_9__DMAChRst__SHIFT
- ACP_DMA_CNTL_9__DMAChRun_MASK
- ACP_DMA_CNTL_9__DMAChRun__SHIFT
- ACP_DMA_COMPLETE_TIME_OUT_VALUE
- ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK
- ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT
- ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT
- ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK
- ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT
- ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK
- ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT
- ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK
- ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT
- ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK
- ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT
- ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK
- ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT
- ACP_DMA_ERR_STS_0__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_0__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_10__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_10__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_11__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_11__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_12__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_12__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_13__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_13__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_14__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_14__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_15__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_15__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_1__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_1__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_2__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_2__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_3__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_3__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_4__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_4__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_5__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_5__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_6__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_6__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_7__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_7__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_8__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_8__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT
- ACP_DMA_ERR_STS_9__DMAChErrCode_MASK
- ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT
- ACP_DMA_ERR_STS_9__DMAChTermErr_MASK
- ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT
- ACP_DMA_PRIORITY_LEVEL_FORCESIZE
- ACP_DMA_PRIORITY_LEVEL_HIGH
- ACP_DMA_PRIORITY_LEVEL_NORMAL
- ACP_DMA_PRIO_0__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_10__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_11__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_12__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_13__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_14__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_15__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_1__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_2__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_3__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_4__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_5__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_6__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_7__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_8__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT
- ACP_DMA_PRIO_9__DMAChPrioLvl_MASK
- ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT
- ACP_DMA_REGS_END
- ACP_DMA_RESET_TIME
- ACP_DPM_MASK
- ACP_DSP0_CACHE_OFFSET0__Offset_MASK
- ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET1__Offset_MASK
- ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET2__Offset_MASK
- ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET3__Offset_MASK
- ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET4__Offset_MASK
- ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET5__Offset_MASK
- ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET6__Offset_MASK
- ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET7__Offset_MASK
- ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_OFFSET8__Offset_MASK
- ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT
- ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK
- ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT
- ACP_DSP0_CACHE_SIZE0__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE0__Size_MASK
- ACP_DSP0_CACHE_SIZE0__Size__SHIFT
- ACP_DSP0_CACHE_SIZE1__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE1__Size_MASK
- ACP_DSP0_CACHE_SIZE1__Size__SHIFT
- ACP_DSP0_CACHE_SIZE2__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE2__Size_MASK
- ACP_DSP0_CACHE_SIZE2__Size__SHIFT
- ACP_DSP0_CACHE_SIZE3__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE3__Size_MASK
- ACP_DSP0_CACHE_SIZE3__Size__SHIFT
- ACP_DSP0_CACHE_SIZE4__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE4__Size_MASK
- ACP_DSP0_CACHE_SIZE4__Size__SHIFT
- ACP_DSP0_CACHE_SIZE5__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE5__Size_MASK
- ACP_DSP0_CACHE_SIZE5__Size__SHIFT
- ACP_DSP0_CACHE_SIZE6__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE6__Size_MASK
- ACP_DSP0_CACHE_SIZE6__Size__SHIFT
- ACP_DSP0_CACHE_SIZE7__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE7__Size_MASK
- ACP_DSP0_CACHE_SIZE7__Size__SHIFT
- ACP_DSP0_CACHE_SIZE8__PageEnable_MASK
- ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT
- ACP_DSP0_CACHE_SIZE8__Size_MASK
- ACP_DSP0_CACHE_SIZE8__Size__SHIFT
- ACP_DSP0_CLKRST_CNTL__ClkEn_MASK
- ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT
- ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK
- ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT
- ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK
- ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT
- ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK
- ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT
- ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK
- ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT
- ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK
- ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT
- ACP_DSP0_CS_STATE__DSP0_CS_state_MASK
- ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT
- ACP_DSP0_DEBUG_PC__DebugPC_MASK
- ACP_DSP0_DEBUG_PC__DebugPC__SHIFT
- ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK
- ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT
- ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK
- ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT
- ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK
- ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT
- ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK
- ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT
- ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK
- ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT
- ACP_DSP0_INTR_CNTL__ACPErrMask_MASK
- ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT
- ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK
- ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT
- ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK
- ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT
- ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK
- ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT
- ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK
- ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT
- ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK
- ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT
- ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK
- ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT
- ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK
- ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT
- ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK
- ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT
- ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK
- ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT
- ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK
- ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT
- ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK
- ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT
- ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK
- ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT
- ACP_DSP0_INTR_STAT__ACPErrAck_MASK
- ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT
- ACP_DSP0_INTR_STAT__ACPErrStat_MASK
- ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT
- ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK
- ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT
- ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK
- ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT
- ACP_DSP0_INTR_STAT__DMAIOCAck_MASK
- ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT
- ACP_DSP0_INTR_STAT__DMAIOCStat_MASK
- ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT
- ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK
- ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT
- ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK
- ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT
- ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK
- ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT
- ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK
- ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT
- ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK
- ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT
- ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK
- ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT
- ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK
- ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT
- ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK
- ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT
- ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK
- ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT
- ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK
- ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT
- ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK
- ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT
- ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK
- ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT
- ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK
- ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT
- ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK
- ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT
- ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK
- ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT
- ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK
- ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT
- ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK
- ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT
- ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK
- ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT
- ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK
- ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT
- ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK
- ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT
- ACP_DSP0_NMI_SEL__NMISel_MASK
- ACP_DSP0_NMI_SEL__NMISel__SHIFT
- ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK
- ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT
- ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK
- ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT
- ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK
- ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP0_NONCACHE_SIZE0__Size_MASK
- ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT
- ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK
- ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP0_NONCACHE_SIZE1__Size_MASK
- ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT
- ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK
- ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT
- ACP_DSP0_RUNSTALL__RunStallCntl_MASK
- ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT
- ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK
- ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT
- ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK
- ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT
- ACP_DSP0_TIMER__ACP_DSP0_timer_MASK
- ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT
- ACP_DSP0_VECT_SEL__StaticVectorSel_MASK
- ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT
- ACP_DSP0_WAIT_MODE__WaitMode_MASK
- ACP_DSP0_WAIT_MODE__WaitMode__SHIFT
- ACP_DSP1_CACHE_OFFSET0__Offset_MASK
- ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET1__Offset_MASK
- ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET2__Offset_MASK
- ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET3__Offset_MASK
- ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET4__Offset_MASK
- ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET5__Offset_MASK
- ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET6__Offset_MASK
- ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET7__Offset_MASK
- ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_OFFSET8__Offset_MASK
- ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT
- ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK
- ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT
- ACP_DSP1_CACHE_SIZE0__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE0__Size_MASK
- ACP_DSP1_CACHE_SIZE0__Size__SHIFT
- ACP_DSP1_CACHE_SIZE1__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE1__Size_MASK
- ACP_DSP1_CACHE_SIZE1__Size__SHIFT
- ACP_DSP1_CACHE_SIZE2__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE2__Size_MASK
- ACP_DSP1_CACHE_SIZE2__Size__SHIFT
- ACP_DSP1_CACHE_SIZE3__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE3__Size_MASK
- ACP_DSP1_CACHE_SIZE3__Size__SHIFT
- ACP_DSP1_CACHE_SIZE4__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE4__Size_MASK
- ACP_DSP1_CACHE_SIZE4__Size__SHIFT
- ACP_DSP1_CACHE_SIZE5__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE5__Size_MASK
- ACP_DSP1_CACHE_SIZE5__Size__SHIFT
- ACP_DSP1_CACHE_SIZE6__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE6__Size_MASK
- ACP_DSP1_CACHE_SIZE6__Size__SHIFT
- ACP_DSP1_CACHE_SIZE7__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE7__Size_MASK
- ACP_DSP1_CACHE_SIZE7__Size__SHIFT
- ACP_DSP1_CACHE_SIZE8__PageEnable_MASK
- ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT
- ACP_DSP1_CACHE_SIZE8__Size_MASK
- ACP_DSP1_CACHE_SIZE8__Size__SHIFT
- ACP_DSP1_CLKRST_CNTL__ClkEn_MASK
- ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT
- ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK
- ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT
- ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK
- ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT
- ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK
- ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT
- ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK
- ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT
- ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK
- ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT
- ACP_DSP1_CS_STATE__DSP1_CS_state_MASK
- ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT
- ACP_DSP1_DEBUG_PC__DebugPC_MASK
- ACP_DSP1_DEBUG_PC__DebugPC__SHIFT
- ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK
- ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT
- ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK
- ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT
- ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK
- ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT
- ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK
- ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT
- ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK
- ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT
- ACP_DSP1_INTR_CNTL__ACPErrMask_MASK
- ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT
- ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK
- ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT
- ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK
- ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT
- ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK
- ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT
- ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK
- ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT
- ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK
- ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT
- ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK
- ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT
- ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK
- ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT
- ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK
- ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT
- ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK
- ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT
- ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK
- ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT
- ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK
- ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT
- ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK
- ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT
- ACP_DSP1_INTR_STAT__ACPErrAck_MASK
- ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT
- ACP_DSP1_INTR_STAT__ACPErrStat_MASK
- ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT
- ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK
- ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT
- ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK
- ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT
- ACP_DSP1_INTR_STAT__DMAIOCAck_MASK
- ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT
- ACP_DSP1_INTR_STAT__DMAIOCStat_MASK
- ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT
- ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK
- ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT
- ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK
- ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT
- ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK
- ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT
- ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK
- ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT
- ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK
- ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT
- ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK
- ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT
- ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK
- ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT
- ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK
- ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT
- ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK
- ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT
- ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK
- ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT
- ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK
- ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT
- ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK
- ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT
- ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK
- ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT
- ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK
- ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT
- ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK
- ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT
- ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK
- ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT
- ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK
- ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT
- ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK
- ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT
- ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK
- ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT
- ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK
- ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT
- ACP_DSP1_NMI_SEL__NMISel_MASK
- ACP_DSP1_NMI_SEL__NMISel__SHIFT
- ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK
- ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT
- ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK
- ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT
- ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK
- ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP1_NONCACHE_SIZE0__Size_MASK
- ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT
- ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK
- ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP1_NONCACHE_SIZE1__Size_MASK
- ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT
- ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK
- ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT
- ACP_DSP1_RUNSTALL__RunStallCntl_MASK
- ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT
- ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK
- ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT
- ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK
- ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT
- ACP_DSP1_TIMER__ACP_DSP1_timer_MASK
- ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT
- ACP_DSP1_VECT_SEL__StaticVectorSel_MASK
- ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT
- ACP_DSP1_WAIT_MODE__WaitMode_MASK
- ACP_DSP1_WAIT_MODE__WaitMode__SHIFT
- ACP_DSP2_CACHE_OFFSET0__Offset_MASK
- ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET1__Offset_MASK
- ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET2__Offset_MASK
- ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET3__Offset_MASK
- ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET4__Offset_MASK
- ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET5__Offset_MASK
- ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET6__Offset_MASK
- ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET7__Offset_MASK
- ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_OFFSET8__Offset_MASK
- ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT
- ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK
- ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT
- ACP_DSP2_CACHE_SIZE0__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE0__Size_MASK
- ACP_DSP2_CACHE_SIZE0__Size__SHIFT
- ACP_DSP2_CACHE_SIZE1__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE1__Size_MASK
- ACP_DSP2_CACHE_SIZE1__Size__SHIFT
- ACP_DSP2_CACHE_SIZE2__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE2__Size_MASK
- ACP_DSP2_CACHE_SIZE2__Size__SHIFT
- ACP_DSP2_CACHE_SIZE3__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE3__Size_MASK
- ACP_DSP2_CACHE_SIZE3__Size__SHIFT
- ACP_DSP2_CACHE_SIZE4__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE4__Size_MASK
- ACP_DSP2_CACHE_SIZE4__Size__SHIFT
- ACP_DSP2_CACHE_SIZE5__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE5__Size_MASK
- ACP_DSP2_CACHE_SIZE5__Size__SHIFT
- ACP_DSP2_CACHE_SIZE6__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE6__Size_MASK
- ACP_DSP2_CACHE_SIZE6__Size__SHIFT
- ACP_DSP2_CACHE_SIZE7__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE7__Size_MASK
- ACP_DSP2_CACHE_SIZE7__Size__SHIFT
- ACP_DSP2_CACHE_SIZE8__PageEnable_MASK
- ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT
- ACP_DSP2_CACHE_SIZE8__Size_MASK
- ACP_DSP2_CACHE_SIZE8__Size__SHIFT
- ACP_DSP2_CLKRST_CNTL__ClkEn_MASK
- ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT
- ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK
- ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT
- ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK
- ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT
- ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK
- ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT
- ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK
- ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT
- ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK
- ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT
- ACP_DSP2_CS_STATE__DSP2_CS_state_MASK
- ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT
- ACP_DSP2_DEBUG_PC__DebugPC_MASK
- ACP_DSP2_DEBUG_PC__DebugPC__SHIFT
- ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK
- ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT
- ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK
- ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT
- ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK
- ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT
- ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK
- ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT
- ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK
- ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT
- ACP_DSP2_INTR_CNTL__ACPErrMask_MASK
- ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT
- ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK
- ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT
- ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK
- ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT
- ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK
- ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT
- ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK
- ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT
- ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK
- ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT
- ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK
- ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT
- ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK
- ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT
- ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK
- ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT
- ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK
- ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT
- ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK
- ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT
- ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK
- ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT
- ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK
- ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT
- ACP_DSP2_INTR_STAT__ACPErrAck_MASK
- ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT
- ACP_DSP2_INTR_STAT__ACPErrStat_MASK
- ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT
- ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK
- ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT
- ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK
- ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT
- ACP_DSP2_INTR_STAT__DMAIOCAck_MASK
- ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT
- ACP_DSP2_INTR_STAT__DMAIOCStat_MASK
- ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT
- ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK
- ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT
- ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK
- ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT
- ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK
- ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT
- ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK
- ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT
- ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK
- ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT
- ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK
- ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT
- ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK
- ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT
- ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK
- ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT
- ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK
- ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT
- ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK
- ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT
- ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK
- ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT
- ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK
- ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT
- ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK
- ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT
- ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK
- ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT
- ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK
- ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT
- ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK
- ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT
- ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK
- ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT
- ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK
- ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT
- ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK
- ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT
- ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK
- ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT
- ACP_DSP2_NMI_SEL__NMISel_MASK
- ACP_DSP2_NMI_SEL__NMISel__SHIFT
- ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK
- ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT
- ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK
- ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT
- ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK
- ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT
- ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK
- ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT
- ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK
- ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT
- ACP_DSP2_NONCACHE_SIZE0__Size_MASK
- ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT
- ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK
- ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT
- ACP_DSP2_NONCACHE_SIZE1__Size_MASK
- ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT
- ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK
- ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT
- ACP_DSP2_RUNSTALL__RunStallCntl_MASK
- ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT
- ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK
- ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT
- ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK
- ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT
- ACP_DSP2_TIMER__ACP_DSP2_timer_MASK
- ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT
- ACP_DSP2_VECT_SEL__StaticVectorSel_MASK
- ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT
- ACP_DSP2_WAIT_MODE__WaitMode_MASK
- ACP_DSP2_WAIT_MODE__WaitMode__SHIFT
- ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK
- ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT
- ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK
- ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK
- ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK
- ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK
- ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK
- ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT
- ACP_EN
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK
- ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT
- ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK
- ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT
- ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK
- ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT
- ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK
- ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT
- ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK
- ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT
- ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK
- ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT
- ACP_ERROR_SOURCE_STS__DAGBErr_MASK
- ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT
- ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK
- ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK
- ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT
- ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK
- ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT
- ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK
- ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT
- ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK
- ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT
- ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK
- ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT
- ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK
- ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT
- ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK
- ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK
- ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK
- ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK
- ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK
- ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK
- ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK
- ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK
- ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK
- ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK
- ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT
- ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK
- ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT
- ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK
- ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT
- ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK
- ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK
- ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK
- ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK
- ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK
- ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK
- ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK
- ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK
- ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK
- ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK
- ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK
- ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK
- ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK
- ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK
- ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK
- ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK
- ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK
- ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK
- ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK
- ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK
- ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK
- ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT
- ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK
- ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT
- ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK
- ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK
- ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK
- ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK
- ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK
- ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK
- ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK
- ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK
- ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK
- ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT
- ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK
- ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT
- ACP_FW_STATUS__RUN_MASK
- ACP_FW_STATUS__RUN__SHIFT
- ACP_GARLIC_CNTL_DEFAULT
- ACP_HWID
- ACP_I2SBT_CCR__I2SBT_SCLKG_MASK
- ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT
- ACP_I2SBT_CCR__I2SBT_WSS_MASK
- ACP_I2SBT_CCR__I2SBT_WSS__SHIFT
- ACP_I2SBT_CER__I2SBT_CLKEN_MASK
- ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK
- ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK
- ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT
- ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK
- ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT
- ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK
- ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT
- ACP_I2SBT_IER__I2SBT_IEN_MASK
- ACP_I2SBT_IER__I2SBT_IEN__SHIFT
- ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK
- ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT
- ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK
- ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT
- ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK
- ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT
- ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK
- ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT
- ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK
- ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT
- ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK
- ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT
- ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK
- ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT
- ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK
- ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT
- ACP_I2SBT_IRER__I2SBT_RXEN_MASK
- ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT
- ACP_I2SBT_ISR0__I2SBT_RXDA_MASK
- ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT
- ACP_I2SBT_ISR0__I2SBT_RXFO_MASK
- ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT
- ACP_I2SBT_ISR0__I2SBT_TXFE_MASK
- ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT
- ACP_I2SBT_ISR0__I2SBT_TXFO_MASK
- ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT
- ACP_I2SBT_ISR1__I2SBT_RXDA_MASK
- ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT
- ACP_I2SBT_ISR1__I2SBT_RXFO_MASK
- ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT
- ACP_I2SBT_ISR1__I2SBT_TXFE_MASK
- ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT
- ACP_I2SBT_ISR1__I2SBT_TXFO_MASK
- ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT
- ACP_I2SBT_ITER__I2SBT_TXEN_MASK
- ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT
- ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK
- ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT
- ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK
- ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT
- ACP_I2SBT_RCR0__I2SBT_WLEN_MASK
- ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT
- ACP_I2SBT_RCR1__I2SBT_WLEN_MASK
- ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT
- ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK
- ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT
- ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK
- ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT
- ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK
- ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT
- ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK
- ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT
- ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK
- ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT
- ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK
- ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT
- ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK
- ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT
- ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK
- ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT
- ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK
- ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT
- ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK
- ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT
- ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK
- ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT
- ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK
- ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT
- ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK
- ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT
- ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK
- ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT
- ACP_I2SBT_TCR0__I2SBT_WLEN_MASK
- ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT
- ACP_I2SBT_TCR1__I2SBT_WLEN_MASK
- ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT
- ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK
- ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT
- ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK
- ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT
- ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK
- ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT
- ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK
- ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT
- ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK
- ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT
- ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK
- ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT
- ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK
- ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT
- ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK
- ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT
- ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK
- ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT
- ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK
- ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT
- ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK
- ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT
- ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK
- ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT
- ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK
- ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK
- ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK
- ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT
- ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK
- ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT
- ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK
- ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT
- ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK
- ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT
- ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK
- ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT
- ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK
- ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT
- ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK
- ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT
- ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK
- ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT
- ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK
- ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT
- ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK
- ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT
- ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK
- ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT
- ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK
- ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT
- ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK
- ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT
- ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK
- ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT
- ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK
- ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT
- ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK
- ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT
- ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK
- ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT
- ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK
- ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT
- ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK
- ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT
- ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK
- ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT
- ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK
- ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT
- ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK
- ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT
- ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK
- ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT
- ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK
- ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT
- ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK
- ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT
- ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK
- ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT
- ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK
- ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT
- ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK
- ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT
- ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK
- ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT
- ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK
- ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT
- ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK
- ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT
- ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK
- ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT
- ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK
- ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT
- ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK
- ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT
- ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK
- ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT
- ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK
- ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT
- ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK
- ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT
- ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK
- ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT
- ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK
- ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT
- ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK
- ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT
- ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK
- ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT
- ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK
- ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT
- ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK
- ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT
- ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK
- ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT
- ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK
- ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT
- ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK
- ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT
- ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK
- ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT
- ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK
- ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT
- ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK
- ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT
- ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK
- ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT
- ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK
- ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT
- ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK
- ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT
- ACP_I2SSP_CCR__I2SSP_SCLKG_MASK
- ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT
- ACP_I2SSP_CCR__I2SSP_WSS_MASK
- ACP_I2SSP_CCR__I2SSP_WSS__SHIFT
- ACP_I2SSP_CER__I2SSP_CLKEN_MASK
- ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK
- ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK
- ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT
- ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK
- ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT
- ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK
- ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT
- ACP_I2SSP_IER__I2SSP_IEN_MASK
- ACP_I2SSP_IER__I2SSP_IEN__SHIFT
- ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK
- ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT
- ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK
- ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT
- ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK
- ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT
- ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK
- ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT
- ACP_I2SSP_IRER__I2SSP_RXEN_MASK
- ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT
- ACP_I2SSP_ISR0__I2SSP_RXDA_MASK
- ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT
- ACP_I2SSP_ISR0__I2SSP_RXFO_MASK
- ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT
- ACP_I2SSP_ISR0__I2SSP_TXFE_MASK
- ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT
- ACP_I2SSP_ISR0__I2SSP_TXFO_MASK
- ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT
- ACP_I2SSP_ITER__I2SSP_TXEN_MASK
- ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT
- ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK
- ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT
- ACP_I2SSP_RCR0__I2SSP_WLEN_MASK
- ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT
- ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK
- ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT
- ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK
- ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT
- ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK
- ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT
- ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK
- ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT
- ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK
- ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT
- ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK
- ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT
- ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK
- ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT
- ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK
- ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT
- ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK
- ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT
- ACP_I2SSP_TCR0__I2SSP_WLEN_MASK
- ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT
- ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK
- ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT
- ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK
- ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT
- ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK
- ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT
- ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK
- ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT
- ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK
- ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT
- ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK
- ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT
- ACP_I2S_BT_16BIT_RESOLUTION_EN
- ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK
- ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT
- ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK
- ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT
- ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK
- ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT
- ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK
- ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT
- ACP_I2S_CAP_REGS_END
- ACP_I2S_CAP_REGS_START
- ACP_I2S_COMP1_CAP_REG_OFFSET
- ACP_I2S_COMP1_PLAY_REG_OFFSET
- ACP_I2S_COMP2_CAP_REG_OFFSET
- ACP_I2S_COMP2_PLAY_REG_OFFSET
- ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK
- ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT
- ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK
- ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT
- ACP_I2S_MIC_16BIT_RESOLUTION_EN
- ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK
- ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT
- ACP_I2S_PLAY_REGS_END
- ACP_I2S_PLAY_REGS_START
- ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK
- ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT
- ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK
- ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT
- ACP_I2S_SP_16BIT_RESOLUTION_EN
- ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK
- ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT
- ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK
- ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT
- ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
- ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS
- ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK
- ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT
- ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK
- ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT
- ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK
- ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT
- ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK
- ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT
- ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK
- ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT
- ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK
- ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT
- ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK
- ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT
- ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK
- ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT
- ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK
- ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT
- ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK
- ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT
- ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK
- ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT
- ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK
- ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT
- ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK
- ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT
- ACP_MODE_AZ
- ACP_MODE_I2S
- ACP_ONION_CNTL_DEFAULT
- ACP_PAGE_SIZE_4K_ENABLE
- ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK
- ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT
- ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK
- ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT
- ACP_PGFSM_CONFIG_REG__P1_Select_MASK
- ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT
- ACP_PGFSM_CONFIG_REG__P2_Select_MASK
- ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT
- ACP_PGFSM_CONFIG_REG__Power_Down_MASK
- ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT
- ACP_PGFSM_CONFIG_REG__Power_Up_MASK
- ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT
- ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK
- ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT
- ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK
- ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT
- ACP_PGFSM_CONFIG_REG__Rd_MASK
- ACP_PGFSM_CONFIG_REG__Rd__SHIFT
- ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK
- ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT
- ACP_PGFSM_CONFIG_REG__SRBM_override_MASK
- ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT
- ACP_PGFSM_CONFIG_REG__Short_Format_MASK
- ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT
- ACP_PGFSM_CONFIG_REG__Wr_MASK
- ACP_PGFSM_CONFIG_REG__Wr__SHIFT
- ACP_PGFSM_READ_REG_0__Read_value_MASK
- ACP_PGFSM_READ_REG_0__Read_value__SHIFT
- ACP_PGFSM_READ_REG_1__Read_value_MASK
- ACP_PGFSM_READ_REG_1__Read_value__SHIFT
- ACP_PGFSM_READ_REG_2__Read_value_MASK
- ACP_PGFSM_READ_REG_2__Read_value__SHIFT
- ACP_PGFSM_READ_REG_3__Read_value_MASK
- ACP_PGFSM_READ_REG_3__Read_value__SHIFT
- ACP_PGFSM_READ_REG_4__Read_value_MASK
- ACP_PGFSM_READ_REG_4__Read_value__SHIFT
- ACP_PGFSM_READ_REG_5__Read_value_MASK
- ACP_PGFSM_READ_REG_5__Read_value__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT
- ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK
- ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT
- ACP_PGFSM_WRITE_REG__Write_value_MASK
- ACP_PGFSM_WRITE_REG__Write_value__SHIFT
- ACP_PHYSICAL_BASE
- ACP_PLAYBACK_PTE_OFFSET
- ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK
- ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT
- ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK
- ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT
- ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK
- ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT
- ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK
- ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT
- ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK
- ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT
- ACP_SEMA_CMD__ATC_MASK
- ACP_SEMA_CMD__ATC__SHIFT
- ACP_SEMA_CMD__REQ_CMD_MASK
- ACP_SEMA_CMD__REQ_CMD__SHIFT
- ACP_SEMA_CMD__VMID_EN_MASK
- ACP_SEMA_CMD__VMID_EN__SHIFT
- ACP_SEMA_CMD__VMID_MASK
- ACP_SEMA_CMD__VMID__SHIFT
- ACP_SEMA_CMD__WR_PHASE_MASK
- ACP_SEMA_CMD__WR_PHASE__SHIFT
- ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK
- ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT
- ACP_SEMA_STS__REQ_RESP_AVAIL_MASK
- ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT
- ACP_SEMA_STS__REQ_STS_MASK
- ACP_SEMA_STS__REQ_STS__SHIFT
- ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK
- ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT
- ACP_SOFT_RESET_DONE_TIME_OUT_VALUE
- ACP_SOFT_RESET__ExternalSoftResetMode_MASK
- ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT
- ACP_SOFT_RESET__InternalSoftResetMode_MASK
- ACP_SOFT_RESET__InternalSoftResetMode__SHIFT
- ACP_SOFT_RESET__SoftResetAudDone_MASK
- ACP_SOFT_RESET__SoftResetAudDone__SHIFT
- ACP_SOFT_RESET__SoftResetAud_MASK
- ACP_SOFT_RESET__SoftResetAud__SHIFT
- ACP_SOFT_RESET__SoftResetDMADone_MASK
- ACP_SOFT_RESET__SoftResetDMADone__SHIFT
- ACP_SOFT_RESET__SoftResetDMA_MASK
- ACP_SOFT_RESET__SoftResetDMA__SHIFT
- ACP_SRAM_BANK_1_ADDRESS
- ACP_SRAM_BANK_2_ADDRESS
- ACP_SRAM_BANK_3_ADDRESS
- ACP_SRAM_BANK_4_ADDRESS
- ACP_SRAM_BANK_5_ADDRESS
- ACP_SRAM_BASE_ADDRESS
- ACP_SRAM_PTE_OFFSET
- ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK
- ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT
- ACP_SRBM_Client_RDDATA__ReadData_MASK
- ACP_SRBM_Client_RDDATA__ReadData__SHIFT
- ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK
- ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT
- ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK
- ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT
- ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK
- ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT
- ACP_SRC_ID
- ACP_STATUS__ACPRefClkSpd_MASK
- ACP_STATUS__ACPRefClkSpd__SHIFT
- ACP_STATUS__ClkOn_MASK
- ACP_STATUS__ClkOn__SHIFT
- ACP_STATUS__MCStutterLastEdge_MASK
- ACP_STATUS__MCStutterLastEdge__SHIFT
- ACP_STATUS__SMUStutterLastEdge_MASK
- ACP_STATUS__SMUStutterLastEdge__SHIFT
- ACP_ST_BT_CAPTURE_PTE_OFFSET
- ACP_ST_BT_PLAYBACK_PTE_OFFSET
- ACP_ST_CAPTURE_PTE_OFFSET
- ACP_ST_PLAYBACK_PTE_OFFSET
- ACP_TILE_DSP0
- ACP_TILE_DSP0_MASK
- ACP_TILE_DSP1
- ACP_TILE_DSP1_MASK
- ACP_TILE_DSP2
- ACP_TILE_DSP2_MASK
- ACP_TILE_OFF_MASK
- ACP_TILE_OFF_RETAIN_REG_MASK
- ACP_TILE_ON_MASK
- ACP_TILE_ON_RETAIN_REG_MASK
- ACP_TILE_P1
- ACP_TILE_P1_MASK
- ACP_TILE_P2
- ACP_TILE_P2_MASK
- ACP_TIMEOUT_LOOP
- ACP_TIMER_CNTL__ACP_Timer_control_MASK
- ACP_TIMER_CNTL__ACP_Timer_control__SHIFT
- ACP_TIMER__ACP_Timer_count_MASK
- ACP_TIMER__ACP_Timer_count__SHIFT
- ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM
- ACP_TO_I2S_DMA_CH_NUM
- ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM
- ACP_TO_SYSRAM_CH_NUM
- ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK
- ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT
- ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK
- ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT
- ACQ_CNTL_1
- ACQ_CNTL_2
- ACQ_CNTL_3
- ACQ_CTL
- ACQ_CTRL_REG_1
- ACQ_CTRL_REG_2
- ACQ_DELAY
- ACQ_MODE_EVEN
- ACQ_MODE_NEXT
- ACQ_MODE_ODD
- ACQ_STATUS_REG
- ACR
- ACR0_MODE
- ACR122U_PRODUCT_ID
- ACR1_MODE
- ACR2_MODE
- ACR3_MODE
- ACRC
- ACRC32
- ACRDIV
- ACREGACC
- ACREGACC_CODECID_SHIFT
- ACREGACC_DAT_SHIFT
- ACREGACC_READ
- ACREGACC_REG_SHIFT
- ACREGACC_WRITE
- ACREVID
- ACRPRESC
- ACRYPTO_MODE_CBC
- ACRYPTO_MODE_CFB
- ACRYPTO_MODE_ECB
- ACRYPTO_MODE_OFB
- ACRYPTO_OP_DECRYPT
- ACRYPTO_OP_ENCRYPT
- ACRYPTO_OP_HMAC
- ACRYPTO_OP_RNG
- ACRYPTO_TYPE_3DES
- ACRYPTO_TYPE_AES_128
- ACRYPTO_TYPE_AES_192
- ACRYPTO_TYPE_AES_256
- ACRYPTO_TYPE_DES
- ACR_32
- ACR_44
- ACR_48
- ACR_ADMSK
- ACR_ANY
- ACR_ASIZE_MASK
- ACR_BA
- ACR_BASE_POS
- ACR_BAUD0
- ACR_BAUD1
- ACR_BRG_SET1
- ACR_BRG_SET2
- ACR_BWE
- ACR_CClk16
- ACR_CDIS
- ACR_CENB
- ACR_CExt
- ACR_CM
- ACR_CMD_BOOTSTRAP_FALCON
- ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO
- ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES
- ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS
- ACR_CMD_INIT_WPR_REGION
- ACR_CM_CB
- ACR_CM_CP
- ACR_CM_IMPRE
- ACR_CM_OFF_IMP
- ACR_CM_OFF_PRE
- ACR_CM_PRE
- ACR_CM_WT
- ACR_CT_Mask
- ACR_CTxCA
- ACR_CTxCB
- ACR_DELTA_IP0_IRQ_EN
- ACR_DELTA_IP1_IRQ_EN
- ACR_DELTA_IP2_IRQ_EN
- ACR_DELTA_IP3_IRQ_EN
- ACR_DMARX16
- ACR_DMARX20
- ACR_DMATX16
- ACR_DMATX20
- ACR_ENABLE
- ACR_EW_MASK
- ACR_MASK_POS
- ACR_MDF0
- ACR_MDF1
- ACR_MODE
- ACR_NONE
- ACR_R352_MAX_APPS
- ACR_RAM_2WORD
- ACR_RAM_4BYTE
- ACR_RAM_NONE
- ACR_RAR
- ACR_RDE
- ACR_RDS
- ACR_SIZE
- ACR_SP
- ACR_SS_MASK
- ACR_SUBPACK_CTS
- ACR_SUBPACK_N
- ACR_SUPER
- ACR_TAM_2WORD
- ACR_TAM_4BYTE
- ACR_TAM_NONE
- ACR_TAR
- ACR_TClk
- ACR_TClk16
- ACR_TDE
- ACR_TDS
- ACR_TExt
- ACR_TExt16
- ACR_TIMER_MODE
- ACR_TX12ATOM
- ACR_USER
- ACR_WPROTECT
- ACSAD2_SI_MASK
- ACSAD2_SI_SHIFT
- ACSAD_SI_MASK
- ACSAD_SI_SHIFT
- ACSDA2_SD_MASK
- ACSDA2_SD_SHIFT
- ACSDA_SD_MASK
- ACSDA_SD_SHIFT
- ACSDIS
- ACSI_MAJOR
- ACSR
- ACSR_PIN_PRIO_SELECT
- ACSTREAM_FRONT
- ACSTREAM_LFE
- ACSTREAM_SURROUND
- ACSTS2_CRDY
- ACSTS2_VSTS
- ACSTS_CRDY
- ACSTS_VSTS
- ACSTS_WKUP
- ACS_ABO_BITPOS
- ACS_ACNO
- ACS_CODE
- ACS_DARROW
- ACS_HLINE
- ACS_LLCORNER
- ACS_LRCORNER
- ACS_LTEE
- ACS_RTEE
- ACS_UARROW
- ACS_ULCORNER
- ACS_URCORNER
- ACS_VENDOR_ID
- ACS_VLINE
- ACT
- ACT8600
- ACT8600_APCH0
- ACT8600_APCH1
- ACT8600_APCH2
- ACT8600_APCH_CHG_ACIN
- ACT8600_APCH_CHG_USB
- ACT8600_APCH_CSTATE0
- ACT8600_APCH_CSTATE1
- ACT8600_APCH_STAT
- ACT8600_DCDC1_CTRL
- ACT8600_DCDC1_VSET
- ACT8600_DCDC2_CTRL
- ACT8600_DCDC2_VSET
- ACT8600_DCDC3_CTRL
- ACT8600_DCDC3_VSET
- ACT8600_ID_DCDC1
- ACT8600_ID_DCDC2
- ACT8600_ID_DCDC3
- ACT8600_ID_LDO10
- ACT8600_ID_LDO5
- ACT8600_ID_LDO6
- ACT8600_ID_LDO7
- ACT8600_ID_LDO8
- ACT8600_ID_LDO9
- ACT8600_ID_SUDCDC4
- ACT8600_LDO10_ENA
- ACT8600_LDO5_CTRL
- ACT8600_LDO5_VSET
- ACT8600_LDO6_CTRL
- ACT8600_LDO6_VSET
- ACT8600_LDO7_CTRL
- ACT8600_LDO7_VSET
- ACT8600_LDO8_CTRL
- ACT8600_LDO8_VSET
- ACT8600_LDO910_CTRL
- ACT8600_OTG0
- ACT8600_OTG1
- ACT8600_SUDCDC4_CTRL
- ACT8600_SUDCDC4_VSET
- ACT8600_SUDCDC_VOLTAGE_NUM
- ACT8600_SUDCDC_VSEL_MASK
- ACT8600_SYS_CTRL
- ACT8600_SYS_MODE
- ACT8846
- ACT8846_GLB_OFF_CTRL
- ACT8846_ID_REG1
- ACT8846_ID_REG10
- ACT8846_ID_REG11
- ACT8846_ID_REG12
- ACT8846_ID_REG2
- ACT8846_ID_REG3
- ACT8846_ID_REG4
- ACT8846_ID_REG5
- ACT8846_ID_REG6
- ACT8846_ID_REG7
- ACT8846_ID_REG8
- ACT8846_ID_REG9
- ACT8846_OFF_SYSMASK
- ACT8846_REG10_CTRL
- ACT8846_REG10_VSET
- ACT8846_REG11_CTRL
- ACT8846_REG11_VSET
- ACT8846_REG12_CTRL
- ACT8846_REG12_VSET
- ACT8846_REG13_CTRL
- ACT8846_REG1_CTRL
- ACT8846_REG1_VSET
- ACT8846_REG2_CTRL
- ACT8846_REG2_VSET0
- ACT8846_REG2_VSET1
- ACT8846_REG3_CTRL
- ACT8846_REG3_VSET0
- ACT8846_REG3_VSET1
- ACT8846_REG4_CTRL
- ACT8846_REG4_VSET0
- ACT8846_REG4_VSET1
- ACT8846_REG5_CTRL
- ACT8846_REG5_VSET
- ACT8846_REG6_CTRL
- ACT8846_REG6_VSET
- ACT8846_REG7_CTRL
- ACT8846_REG7_VSET
- ACT8846_REG8_CTRL
- ACT8846_REG8_VSET
- ACT8846_REG9_CTRL
- ACT8846_REG9_VSET
- ACT8846_REG_NUM
- ACT8846_SYS0
- ACT8846_SYS1
- ACT8865
- ACT8865_DCDC1_CTRL
- ACT8865_DCDC1_SUS
- ACT8865_DCDC1_VSET1
- ACT8865_DCDC1_VSET2
- ACT8865_DCDC2_CTRL
- ACT8865_DCDC2_SUS
- ACT8865_DCDC2_VSET1
- ACT8865_DCDC2_VSET2
- ACT8865_DCDC3_CTRL
- ACT8865_DCDC3_SUS
- ACT8865_DCDC3_VSET1
- ACT8865_DCDC3_VSET2
- ACT8865_DIS
- ACT8865_ENA
- ACT8865_ID_DCDC1
- ACT8865_ID_DCDC2
- ACT8865_ID_DCDC3
- ACT8865_ID_LDO1
- ACT8865_ID_LDO2
- ACT8865_ID_LDO3
- ACT8865_ID_LDO4
- ACT8865_LDO1_CTRL
- ACT8865_LDO1_SUS
- ACT8865_LDO1_VSET
- ACT8865_LDO2_CTRL
- ACT8865_LDO2_SUS
- ACT8865_LDO2_VSET
- ACT8865_LDO3_CTRL
- ACT8865_LDO3_SUS
- ACT8865_LDO3_VSET
- ACT8865_LDO4_CTRL
- ACT8865_LDO4_SUS
- ACT8865_LDO4_VSET
- ACT8865_MSTROFF
- ACT8865_REGULATOR_MODE_FIXED
- ACT8865_REGULATOR_MODE_LOWPOWER
- ACT8865_REGULATOR_MODE_NORMAL
- ACT8865_REG_NUM
- ACT8865_SYS_CTRL
- ACT8865_SYS_MODE
- ACT8865_SYS_UNLK_REGS
- ACT8865_VOLTAGE_NUM
- ACT8865_VSEL_MASK
- ACT88xx_LDO
- ACT88xx_REG
- ACT88xx_REG_
- ACT8945A_APCH_CFG
- ACT8945A_APCH_CTRL
- ACT8945A_APCH_STATE
- ACT8945A_APCH_STATUS
- ACT8945A_DCDC1_CTRL
- ACT8945A_DCDC1_SUS
- ACT8945A_DCDC1_VSET1
- ACT8945A_DCDC1_VSET2
- ACT8945A_DCDC2_CTRL
- ACT8945A_DCDC2_SUS
- ACT8945A_DCDC2_VSET1
- ACT8945A_DCDC2_VSET2
- ACT8945A_DCDC3_CTRL
- ACT8945A_DCDC3_SUS
- ACT8945A_DCDC3_VSET1
- ACT8945A_DCDC3_VSET2
- ACT8945A_ENA
- ACT8945A_ID_DCDC1
- ACT8945A_ID_DCDC2
- ACT8945A_ID_DCDC3
- ACT8945A_ID_LDO1
- ACT8945A_ID_LDO2
- ACT8945A_ID_LDO3
- ACT8945A_ID_LDO4
- ACT8945A_ID_MAX
- ACT8945A_LDO1_CTRL
- ACT8945A_LDO1_SUS
- ACT8945A_LDO1_VSET
- ACT8945A_LDO2_CTRL
- ACT8945A_LDO2_SUS
- ACT8945A_LDO2_VSET
- ACT8945A_LDO3_CTRL
- ACT8945A_LDO3_SUS
- ACT8945A_LDO3_VSET
- ACT8945A_LDO4_CTRL
- ACT8945A_LDO4_SUS
- ACT8945A_LDO4_VSET
- ACT8945A_REGULATOR_MODE_FIXED
- ACT8945A_REGULATOR_MODE_LOWPOWER
- ACT8945A_REGULATOR_MODE_NORMAL
- ACT8945A_SYS_CTRL
- ACT8945A_SYS_MODE
- ACT8945A_SYS_UNLK_REGS
- ACT8945A_VOLTAGE_NUM
- ACT8945A_VSEL_MASK
- ACT89xx_REG
- ACTAG_MASK
- ACTEL_VID
- ACTHD
- ACTHD_I965
- ACTION
- ACTIONS
- ACTIONS_DONE
- ACTION_BOOT_THREAD
- ACTION_CACHE_LINE_SIZE
- ACTION_CAT_ID
- ACTION_CLR_IPI
- ACTION_CPY
- ACTION_DELAY
- ACTION_DELAYED_RETRY
- ACTION_ENUM
- ACTION_FAIL
- ACTION_FLAGS
- ACTION_FRAME
- ACTION_GET
- ACTION_HALFOFF
- ACTION_IDENTIFY
- ACTION_LEN
- ACTION_LIST
- ACTION_MASK
- ACTION_MGMT_FTYPE
- ACTION_NMI
- ACTION_NONE
- ACTION_ONLY
- ACTION_OOBOFF
- ACTION_PRGPAGE
- ACTION_PUT
- ACTION_READ_STATUS
- ACTION_REENABLE
- ACTION_REMARKS
- ACTION_REPREP
- ACTION_RESET
- ACTION_RETRY
- ACTION_RUN_SCRIPT
- ACTION_SAVE
- ACTION_SCI
- ACTION_SECERASE
- ACTION_SELECT_0
- ACTION_SELECT_1
- ACTION_SELECT_2
- ACTION_SELECT_3
- ACTION_SELECT_4
- ACTION_SELECT_5
- ACTION_SELECT_6
- ACTION_SELECT_7
- ACTION_SEND_COMMAND
- ACTION_SERIAL
- ACTION_SET_IPI
- ACTION_SMI
- ACTION_SNAPSHOT
- ACTION_SOFT_RESET
- ACTION_SUBTYPE_ID
- ACTION_TRACE
- ACTION_WAIT_EVENT
- ACTION_ZEROOFF
- ACTISENSE_D9AC_PID
- ACTISENSE_D9AD_PID
- ACTISENSE_D9AE_PID
- ACTISENSE_D9AF_PID
- ACTISENSE_NDC_PID
- ACTISENSE_NGT_PID
- ACTISENSE_NGW_PID
- ACTISENSE_USG_PID
- ACTIVATE
- ACTIVATE_INDEX
- ACTIVATE_MSG
- ACTIVE
- ACTIVEDATA_TO_BLON_DELAY_SHIFT
- ACTIVEFILTERCOUNTS_F
- ACTIVEFILTERCOUNTS_S
- ACTIVEFILTERCOUNTS_V
- ACTIVEIRQ_MASK
- ACTIVE_33V
- ACTIVE_ACTIVATE_CODEC
- ACTIVE_ASPECT_RATE_14_9
- ACTIVE_ASPECT_RATE_16_9
- ACTIVE_ASPECT_RATE_4_3
- ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME
- ACTIVE_BIT
- ACTIVE_CACHELINE_MAX_OVERLAP
- ACTIVE_CTX_STATUS
- ACTIVE_DBL
- ACTIVE_DISPLAYS
- ACTIVE_ERASED_DET
- ACTIVE_FORMAT_ASPECT_RATIO_14_9
- ACTIVE_FORMAT_ASPECT_RATIO_16_9
- ACTIVE_FORMAT_ASPECT_RATIO_4_3
- ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE
- ACTIVE_FORMAT_NO_DATA
- ACTIVE_FORMAT_VALID
- ACTIVE_HIGH
- ACTIVE_IDX
- ACTIVE_LEVEL_BOTH
- ACTIVE_LEVEL_HIGH
- ACTIVE_LEVEL_LOW
- ACTIVE_LEVEL_MASK
- ACTIVE_LEVEL_OFF
- ACTIVE_LOW
- ACTIVE_MODE
- ACTIVE_NEG
- ACTIVE_NEGATION
- ACTIVE_NEGPLUS
- ACTIVE_NODE_FRACTION
- ACTIVE_PROFILE_TYPE
- ACTIVE_SCAN
- ACTIVE_SCAN_CTRL_FLAGS
- ACTIVE_TCS
- ACTIVE_TCS_BMAP
- ACTIVE_TCS_BMAP_4PORT_K2
- ACTIVITY
- ACTIVITY_BIT_POS
- ACTIVITY_JOGGING
- ACTIVITY_MASK
- ACTIVITY_REST
- ACTIVITY_RUNNING
- ACTIVITY_TIMER
- ACTIVITY_UNKNOWN
- ACTIVITY_WALKING
- ACTL2_RAMOVRLY
- ACTL2_SLEEP
- ACTLR
- ACTLR_EL1
- ACTL_ARB
- ACTL_CLRFIRQ
- ACTL_DMA_MODE_BIT
- ACTL_DMA_MODE_VAL_DMA_MODE_0
- ACTL_DMA_MODE_VAL_DMA_MODE_1
- ACTL_FIFOEN
- ACTL_FIFOWR
- ACTL_FIRQ
- ACTL_IRQEN
- ACTL_PAREN
- ACTL_RESET
- ACTL_SCE_BIT
- ACTMON_ABOVE_WMARK_WINDOW
- ACTMON_AVERAGE_WINDOW_LOG2
- ACTMON_BELOW_WMARK_WINDOW
- ACTMON_BOOST_FREQ_STEP
- ACTMON_COUNT_WEIGHT
- ACTMON_DEFAULT_AVG_BAND
- ACTMON_DEV_AVG_COUNT
- ACTMON_DEV_AVG_LOWER_WMARK
- ACTMON_DEV_AVG_UPPER_WMARK
- ACTMON_DEV_COUNT_WEIGHT
- ACTMON_DEV_CTRL
- ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN
- ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN
- ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN
- ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT
- ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN
- ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT
- ACTMON_DEV_CTRL_ENB
- ACTMON_DEV_CTRL_ENB_PERIODIC
- ACTMON_DEV_CTRL_K_VAL_SHIFT
- ACTMON_DEV_INIT_AVG
- ACTMON_DEV_INTR_CONSECUTIVE_LOWER
- ACTMON_DEV_INTR_CONSECUTIVE_UPPER
- ACTMON_DEV_INTR_STATUS
- ACTMON_DEV_LOWER_WMARK
- ACTMON_DEV_UPPER_WMARK
- ACTMON_GLB_PERIOD_CTRL
- ACTMON_GLB_STATUS
- ACTMON_INTR_STATUS_CLEAR
- ACTMON_SAMPLING_PERIOD
- ACTO
- ACTON_SPECTRAPRO_PID
- ACTON_VID
- ACTS_ASC0_ACT
- ACTS_ASC1_ACT
- ACTS_I2C_ACT
- ACTS_P0
- ACTS_P1
- ACTS_P2
- ACTS_P3
- ACTS_P4
- ACTS_PADCTRL0
- ACTS_PADCTRL1
- ACTS_PADCTRL2
- ACTS_PADCTRL3
- ACTS_PADCTRL4
- ACTS_SSC0
- ACTTAG_MASK
- ACTUALLY_THROTTLED
- ACTUAL_FREQ
- ACTUAL_NR_IRQS
- ACTUAL_RAM_BASE
- ACTUAL_REASS_RAM_BASE
- ACTUAL_SEG_RAM_BASE
- ACT_ABORTACCEPT
- ACT_ABORTCID
- ACT_ABORTDIAL
- ACT_ABORTHUP
- ACT_ACCEPT
- ACT_ACCEPTED
- ACT_ACDC
- ACT_ADDBAREQ
- ACT_ADDBARSP
- ACT_ADDTSREQ
- ACT_ADDTSRSP
- ACT_BPF_NAME_LEN
- ACT_CATEGORY
- ACT_CAT_BA
- ACT_CAT_DLS
- ACT_CAT_HT
- ACT_CAT_QOS
- ACT_CAT_VENDOR
- ACT_CAT_WMM
- ACT_CID
- ACT_CMD
- ACT_CMODESET
- ACT_CONFIGMODE
- ACT_CONNECT
- ACT_CONNTIMEOUT
- ACT_CTRL_ACT_TRIG
- ACT_CTRL_OPCODE_ACTIVATE
- ACT_CTRL_OPCODE_DEACTIVATE
- ACT_CTRL_OPCODE_SHIFT
- ACT_DEBUG
- ACT_DELBA
- ACT_DELTS
- ACT_DIAL
- ACT_DIALING
- ACT_DISCONNECT
- ACT_DLE0
- ACT_DLE1
- ACT_ERROR
- ACT_ESTAB
- ACT_FAILCID
- ACT_FAILCMODE
- ACT_FAILDLE0
- ACT_FAILDLE1
- ACT_FAILINIT
- ACT_FAILSDOWN
- ACT_FAILUMODE
- ACT_FAILVER
- ACT_FAKEDLE0
- ACT_FAKEHUP
- ACT_FAKESDOWN
- ACT_GETSTRING
- ACT_GOTVER
- ACT_HUP
- ACT_HUPMODEM
- ACT_ICALL
- ACT_IF_LOCK
- ACT_IF_VER
- ACT_INACT_CTL
- ACT_INIT
- ACT_MPLS_BOS_NOT_SET
- ACT_MPLS_LABEL_NOT_SET
- ACT_MPLS_TC_NOT_SET
- ACT_MPLS_TTL_DEFAULT
- ACT_NOTHING
- ACT_NOTIFY_BC_DOWN
- ACT_NOTIFY_BC_UP
- ACT_OFLD_CONN
- ACT_OPEN_REQ
- ACT_OPEN_RETRY_COUNT
- ACT_OPEN_RPL
- ACT_PLL_STATUS
- ACT_POL_RAM
- ACT_PROC_CIDMODE
- ACT_PUBLIC_BSSCOEXIST
- ACT_PUBLIC_DSE_DEENABLE
- ACT_PUBLIC_DSE_ENABLE
- ACT_PUBLIC_DSE_MSR_REQ
- ACT_PUBLIC_DSE_MSR_RPRT
- ACT_PUBLIC_DSE_PWR_CONSTRAINT
- ACT_PUBLIC_DSE_REG_LOCATION
- ACT_PUBLIC_EXT_CHL_SWITCH
- ACT_PUBLIC_GAS_COMEBACK_REQ
- ACT_PUBLIC_GAS_COMEBACK_RSP
- ACT_PUBLIC_GAS_INITIAL_REQ
- ACT_PUBLIC_GAS_INITIAL_RSP
- ACT_PUBLIC_LOCATION_TRACK
- ACT_PUBLIC_MAX
- ACT_PUBLIC_MP
- ACT_PUBLIC_TDLS_DISCOVERY_RSP
- ACT_PUBLIC_VENDOR
- ACT_P_CREATED
- ACT_P_DELETED
- ACT_REG
- ACT_REMOTEHUP
- ACT_REMOTEREJECT
- ACT_RETRY_INUSE
- ACT_RETRY_NOMEM
- ACT_RING
- ACT_SCHEDULE
- ACT_SDOWN
- ACT_SETDLE0
- ACT_SETDLE1
- ACT_SETVER
- ACT_SHUTDOWN
- ACT_START
- ACT_STOP
- ACT_TAP_STATUS
- ACT_TDLS_CONFIG
- ACT_TDLS_CREATE
- ACT_TDLS_CS_ENABLE_CONFIG
- ACT_TDLS_CS_INIT
- ACT_TDLS_CS_PARAMS
- ACT_TDLS_CS_STOP
- ACT_TDLS_DELETE
- ACT_TEST
- ACT_TIMEOUT
- ACT_UMODESET
- ACT_WARN
- ACT_X_EN
- ACT_X_SRC
- ACT_Y_EN
- ACT_Y_SRC
- ACT_ZCAU
- ACT_Z_EN
- ACT_Z_SRC
- ACTdeassert
- ACX
- ACX_ACI_OPTION_CFG
- ACX_AC_CFG
- ACX_AID
- ACX_ANTENNA_DIVERSITY_CFG
- ACX_AP_SLEEP_CFG
- ACX_ARP_FILTER_ARP_FILTERING
- ACX_ARP_FILTER_AUTO_ARP
- ACX_ARP_IP_FILTER
- ACX_AUTO_RX_STREAMING
- ACX_AVERAGE_RSSI
- ACX_BA_SESSION_INIT_POLICY
- ACX_BA_SESSION_RX_SETUP
- ACX_BCN_DTIM_OPTIONS
- ACX_BEACON_FILTER_OPT
- ACX_BEACON_FILTER_TABLE
- ACX_BET_ENABLE
- ACX_BSS_IN_PS
- ACX_BURST_MODE
- ACX_CCA_THRESHOLD
- ACX_CFG
- ACX_CLEAR_STATISTICS
- ACX_COEX_ACTIVITY
- ACX_CONFIG_HANGOVER
- ACX_CONFIG_PS
- ACX_CONFIG_PS_WMM
- ACX_CONN_MONIT_DISABLE_VALUE
- ACX_CONN_MONIT_PARAMS
- ACX_CONS_TX_FAILURE
- ACX_CONT_WIND_CFG_REG
- ACX_CONT_WIND_MAX
- ACX_CONT_WIND_MIN_MASK
- ACX_CSUM_CONFIG
- ACX_CTS_PROTECTION
- ACX_DATA_PATH_PARAMS
- ACX_DATA_PATH_RESP_PARAMS
- ACX_DISABLE_BROADCASTS
- ACX_DTIM_PERIOD
- ACX_DYNAMIC_TRACES_CFG
- ACX_EEPROMLESS_IND_REG
- ACX_EE_ADDR_REG
- ACX_EE_CFG
- ACX_EE_CTL_REG
- ACX_EE_DATA_REG
- ACX_ENABLE_RX_DATA_FILTER
- ACX_ERROR_CNT
- ACX_EVENT_MBOX_MASK
- ACX_FEATURE_CFG
- ACX_FM_COEX_CFG
- ACX_FRAG_CFG
- ACX_FW_GEN_FRAME_RATES
- ACX_FW_REV
- ACX_GEN_FW_CMD
- ACX_GET_DATA_FILTER_STATISTICS
- ACX_GET_RATE_MGMT_PARAMS
- ACX_GPIO_CFG
- ACX_GPIO_OUT_REG
- ACX_GPIO_SET
- ACX_HDK_VERSION
- ACX_HOST_IF_CFG_BITMAP
- ACX_HT_BSS_OPERATION
- ACX_IBSS_FILTER
- ACX_INTERRUPT_NOTIFY
- ACX_IPV4_ADDR_SIZE
- ACX_IPV4_VERSION
- ACX_IPV6_VERSION
- ACX_KEEP_ALIVE_MODE
- ACX_KEEP_ALIVE_NO_TX
- ACX_KEEP_ALIVE_PERIOD_ONLY
- ACX_KEEP_ALIVE_TPL_INVALID
- ACX_KEEP_ALIVE_TPL_VALID
- ACX_LOW_RSSI
- ACX_LOW_SNR
- ACX_MAX_GPIO_LINES
- ACX_MAX_RATE_CLASSES
- ACX_MAX_TX_FAILURE
- ACX_MC_ADDRESS_GROUP_MAX
- ACX_MC_ADDRESS_GROUP_MAX_LEN
- ACX_MEDIUM_USAGE
- ACX_MEM_CFG
- ACX_MEM_MAP
- ACX_MISC_CFG
- ACX_MISSED_BEACONS_SPREAD
- ACX_NOISE_HIST
- ACX_NS_IPV6_FILTER
- ACX_PD_THRESHOLD
- ACX_PEER_CAP
- ACX_PEER_HT_CAP
- ACX_PEER_HT_OPERATION_MODE_CFG
- ACX_PM_CFG
- ACX_PM_CONFIG
- ACX_POWER_LEVEL_TABLE
- ACX_PREAMBLE_LONG
- ACX_PREAMBLE_SHORT
- ACX_PREAMBLE_TYPE
- ACX_PROTECTION_CFG
- ACX_PS_RX_STREAMING
- ACX_PWR_CONSUMPTION_STATISTICS
- ACX_QUEUE_HEAD
- ACX_RADIO_PARAM
- ACX_RATE_MASK_UNSPECIFIED
- ACX_RATE_MGMT_ALL_PARAMS
- ACX_RATE_MGMT_NUM_OF_RATES
- ACX_RATE_POLICY
- ACX_RATE_RETRY_LIMIT
- ACX_REG_ECPU_CONTROL
- ACX_REG_EEPROM_START_BIT
- ACX_REG_EE_START
- ACX_REG_HINT_MASK_CLR
- ACX_REG_HINT_MASK_SET
- ACX_REG_INTERRUPT_ACK
- ACX_REG_INTERRUPT_CLEAR
- ACX_REG_INTERRUPT_MASK
- ACX_REG_INTERRUPT_NO_CLEAR
- ACX_REG_INTERRUPT_TRIG
- ACX_REG_INTERRUPT_TRIG_H
- ACX_REG_SLV_SOFT_RESET
- ACX_REG_TABLE_LEN
- ACX_ROAMING_STATISTICS_TBL
- ACX_RSSI_SNR_TRIGGER
- ACX_RSSI_SNR_WEIGHTS
- ACX_RX_BA_FILTER
- ACX_RX_CFG
- ACX_RX_CONFIG_OPT
- ACX_RX_DESC_DEF
- ACX_RX_DESC_MAX
- ACX_RX_DESC_MIN
- ACX_SERVICE_PERIOD_TIMEOUT
- ACX_SET_DCO_ITRIM_PARAMS
- ACX_SET_KEEP_ALIVE_CONFIG
- ACX_SET_RATE_ADAPT_PARAMS
- ACX_SET_RATE_MGMT_PARAMS
- ACX_SET_RX_DATA_FILTER
- ACX_SG_CFG
- ACX_SG_ENABLE
- ACX_SIM_CONFIG
- ACX_SLEEP_AUTH
- ACX_SLOT
- ACX_SLV_SOFT_RESET_BIT
- ACX_STATISTICS
- ACX_TID_CFG
- ACX_TIME_SYNC_CFG
- ACX_TSF_INFO
- ACX_TX_CONFIG_OPT
- ACX_TX_DESC_DEF
- ACX_TX_DESC_MAX
- ACX_TX_DESC_MIN
- ACX_TX_QUEUE_CFG
- ACX_UPDATE_INCONNECTION_STA_LIST
- ACX_WAKE_UP_CONDITIONS
- ACX_WR_TBTT_AND_DTIM
- AC_AFG_BEEP_GEN
- AC_AFG_IN_DELAY
- AC_AFG_OUT_DELAY
- AC_AMPCAP_MIN_MUTE
- AC_AMPCAP_MUTE
- AC_AMPCAP_MUTE_SHIFT
- AC_AMPCAP_NUM_STEPS
- AC_AMPCAP_NUM_STEPS_SHIFT
- AC_AMPCAP_OFFSET
- AC_AMPCAP_OFFSET_SHIFT
- AC_AMPCAP_STEP_SIZE
- AC_AMPCAP_STEP_SIZE_SHIFT
- AC_AMP_FAKE_MUTE
- AC_AMP_GAIN
- AC_AMP_GET_INDEX
- AC_AMP_GET_INPUT
- AC_AMP_GET_LEFT
- AC_AMP_GET_OUTPUT
- AC_AMP_GET_RIGHT
- AC_AMP_MUTE
- AC_AMP_SET_INDEX
- AC_AMP_SET_INDEX_SHIFT
- AC_AMP_SET_INPUT
- AC_AMP_SET_LEFT
- AC_AMP_SET_OUTPUT
- AC_AMP_SET_RIGHT
- AC_ASYNC_ERR
- AC_ASYNC_VA
- AC_BCAST
- AC_BE
- AC_BK
- AC_BOOT_SCC
- AC_BUS_ERROR
- AC_BUS_RESET
- AC_CACHEDDATA
- AC_CACHETAGS
- AC_CHG
- AC_CLIST_LENGTH
- AC_CLIST_LONG
- AC_CONTEXT
- AC_CONV_CHANNEL
- AC_CONV_STREAM
- AC_CONV_STREAM_SHIFT
- AC_CPCTRL_CES
- AC_CPCTRL_READY
- AC_CPCTRL_STATE
- AC_CPCTRL_SUBTAG
- AC_CVTMAP_CHAN
- AC_CVTMAP_HDMI_SLOT
- AC_DC_SW
- AC_DEFCFG_ASSOC_SHIFT
- AC_DEFCFG_COLOR
- AC_DEFCFG_COLOR_SHIFT
- AC_DEFCFG_CONN_TYPE
- AC_DEFCFG_CONN_TYPE_SHIFT
- AC_DEFCFG_DEF_ASSOC
- AC_DEFCFG_DEVICE
- AC_DEFCFG_DEVICE_SHIFT
- AC_DEFCFG_LOCATION
- AC_DEFCFG_LOCATION_SHIFT
- AC_DEFCFG_MISC
- AC_DEFCFG_MISC_NO_PRESENCE
- AC_DEFCFG_MISC_SHIFT
- AC_DEFCFG_PORT_CONN
- AC_DEFCFG_PORT_CONN_SHIFT
- AC_DEFCFG_SEQUENCE
- AC_DEV_LIST_LEN_MASK
- AC_DE_ELDV
- AC_DE_IA
- AC_DE_PD
- AC_DIG1_COPYRIGHT
- AC_DIG1_EMPHASIS
- AC_DIG1_ENABLE
- AC_DIG1_LEVEL
- AC_DIG1_NONAUDIO
- AC_DIG1_PROFESSIONAL
- AC_DIG1_V
- AC_DIG1_VCFG
- AC_DIG2_CC
- AC_DIG3_ICT
- AC_DIG3_KAE
- AC_DIPIDX_BYTE_IDX
- AC_DIPIDX_PACK_IDX
- AC_DIPSIZE_ELD_BUF
- AC_DIPSIZE_PACK_IDX
- AC_DIPXMIT_BEST
- AC_DIPXMIT_DISABLE
- AC_DIPXMIT_MASK
- AC_DIPXMIT_ONCE
- AC_EAPDBTL_BALANCED
- AC_EAPDBTL_EAPD
- AC_EAPDBTL_LR_SWAP
- AC_ELDD_ELD_DATA
- AC_ELDD_ELD_VALID
- AC_ERR_ATA_BUS
- AC_ERR_DEV
- AC_ERR_HOST_BUS
- AC_ERR_HSM
- AC_ERR_INVALID
- AC_ERR_MEDIA
- AC_ERR_NCQ
- AC_ERR_NODEV_HINT
- AC_ERR_OTHER
- AC_ERR_SYSTEM
- AC_ERR_TIMEOUT
- AC_FGT_TYPE
- AC_FGT_TYPE_SHIFT
- AC_FGT_UNSOL_CAP
- AC_FMT_BASE_44K
- AC_FMT_BASE_48K
- AC_FMT_BASE_SHIFT
- AC_FMT_BITS_16
- AC_FMT_BITS_20
- AC_FMT_BITS_24
- AC_FMT_BITS_32
- AC_FMT_BITS_8
- AC_FMT_BITS_MASK
- AC_FMT_BITS_SHIFT
- AC_FMT_CHAN_MASK
- AC_FMT_CHAN_SHIFT
- AC_FMT_DIV_MASK
- AC_FMT_DIV_SHIFT
- AC_FMT_MULT_MASK
- AC_FMT_MULT_SHIFT
- AC_FMT_TYPE_NON_PCM
- AC_FMT_TYPE_PCM
- AC_FMT_TYPE_SHIFT
- AC_FOUND_DEVICE
- AC_G
- AC_GETDEV_CHANGED
- AC_GPIO_IO_COUNT
- AC_GPIO_I_COUNT
- AC_GPIO_I_COUNT_SHIFT
- AC_GPIO_O_COUNT
- AC_GPIO_O_COUNT_SHIFT
- AC_GPIO_UNSOLICITED
- AC_GPIO_WAKE
- AC_GR
- AC_GROUP
- AC_GRP_AUDIO_FUNCTION
- AC_GRP_MODEM_FUNCTION
- AC_IDPROM
- AC_INQ_CHANGED
- AC_JACK_AUX
- AC_JACK_CD
- AC_JACK_COLOR_BLACK
- AC_JACK_COLOR_BLUE
- AC_JACK_COLOR_GREEN
- AC_JACK_COLOR_GREY
- AC_JACK_COLOR_ORANGE
- AC_JACK_COLOR_OTHER
- AC_JACK_COLOR_PINK
- AC_JACK_COLOR_PURPLE
- AC_JACK_COLOR_RED
- AC_JACK_COLOR_UNKNOWN
- AC_JACK_COLOR_WHITE
- AC_JACK_COLOR_YELLOW
- AC_JACK_CONN_1_4
- AC_JACK_CONN_1_8
- AC_JACK_CONN_ATAPI
- AC_JACK_CONN_COMB
- AC_JACK_CONN_DIN
- AC_JACK_CONN_OPTICAL
- AC_JACK_CONN_OTHER
- AC_JACK_CONN_OTHER_ANALOG
- AC_JACK_CONN_OTHER_DIGITAL
- AC_JACK_CONN_RCA
- AC_JACK_CONN_RJ11
- AC_JACK_CONN_UNKNOWN
- AC_JACK_CONN_XLR
- AC_JACK_DIG_OTHER_IN
- AC_JACK_DIG_OTHER_OUT
- AC_JACK_HP_OUT
- AC_JACK_LINE_IN
- AC_JACK_LINE_OUT
- AC_JACK_LOC_ATAPI
- AC_JACK_LOC_BOTTOM
- AC_JACK_LOC_DRIVE_BAY
- AC_JACK_LOC_EXTERNAL
- AC_JACK_LOC_FRONT
- AC_JACK_LOC_HDMI
- AC_JACK_LOC_INTERNAL
- AC_JACK_LOC_LEFT
- AC_JACK_LOC_MOBILE_IN
- AC_JACK_LOC_MOBILE_OUT
- AC_JACK_LOC_NONE
- AC_JACK_LOC_OTHER
- AC_JACK_LOC_REAR
- AC_JACK_LOC_REAR_PANEL
- AC_JACK_LOC_RIGHT
- AC_JACK_LOC_RISER
- AC_JACK_LOC_SEPARATE
- AC_JACK_LOC_TOP
- AC_JACK_MIC_IN
- AC_JACK_MODEM_HAND_SIDE
- AC_JACK_MODEM_LINE_SIDE
- AC_JACK_OTHER
- AC_JACK_PORT_BOTH
- AC_JACK_PORT_COMPLEX
- AC_JACK_PORT_FIXED
- AC_JACK_PORT_NONE
- AC_JACK_SPDIF_IN
- AC_JACK_SPDIF_OUT
- AC_JACK_SPEAKER
- AC_JACK_TELEPHONY
- AC_KNBCAP_DELTA
- AC_KNBCAP_NUM_STEPS
- AC_LEDS
- AC_LOST_DEVICE
- AC_LPCMCAP_192K_20BIT
- AC_LPCMCAP_192K_24BIT
- AC_LPCMCAP_192K_CP_CHNS
- AC_LPCMCAP_192K_NO_CHNS
- AC_LPCMCAP_44K
- AC_LPCMCAP_44K_MS
- AC_LPCMCAP_48K_20BIT
- AC_LPCMCAP_48K_24BIT
- AC_LPCMCAP_48K_CP_CHNS
- AC_LPCMCAP_48K_NO_CHNS
- AC_LPCMCAP_96K_20BIT
- AC_LPCMCAP_96K_24BIT
- AC_LPCMCAP_96K_CP_CHNS
- AC_LPCMCAP_96K_NO_CHNS
- AC_MAX
- AC_MAX_DEV_LIST_LEN
- AC_MINOR
- AC_MODE_MCS7_RIX
- AC_MODE_MCS8_RIX
- AC_MODE_MCS9_RIX
- AC_M_AFAR
- AC_M_AFSR
- AC_M_CTPR
- AC_M_CXR
- AC_M_DAPTP
- AC_M_DAPTP1
- AC_M_IAPTP
- AC_M_IAPTP1
- AC_M_ITR
- AC_M_PCR
- AC_M_RESET
- AC_M_RPR
- AC_M_RPR1
- AC_M_SFAR
- AC_M_SFARX
- AC_M_SFSR
- AC_M_SFSRX
- AC_M_TRCR
- AC_M_TSUTRCR
- AC_NA
- AC_NODE_ROOT
- AC_NUM
- AC_PAGEMAP
- AC_PARAMS_MAX_TSID
- AC_PARAM_AIFS_OFFSET
- AC_PARAM_AIFS_SHIFT
- AC_PARAM_ECW_MAX_OFFSET
- AC_PARAM_ECW_MAX_SHIFT
- AC_PARAM_ECW_MIN_OFFSET
- AC_PARAM_ECW_MIN_SHIFT
- AC_PARAM_TXOP_LIMIT_OFFSET
- AC_PARAM_TXOP_LIMIT_SHIFT
- AC_PARAM_TXOP_OFFSET
- AC_PAR_AMP_IN_CAP
- AC_PAR_AMP_OUT_CAP
- AC_PAR_AUDIO_FG_CAP
- AC_PAR_AUDIO_WIDGET_CAP
- AC_PAR_CONNLIST_LEN
- AC_PAR_DEVLIST_LEN
- AC_PAR_FUNCTION_TYPE
- AC_PAR_GPIO_CAP
- AC_PAR_HDMI_LPCM_CAP
- AC_PAR_NODE_COUNT
- AC_PAR_PCM
- AC_PAR_PCM_RATE_BITS
- AC_PAR_PIN_CAP
- AC_PAR_POWER_STATE
- AC_PAR_PROC_CAP
- AC_PAR_REV_ID
- AC_PAR_STREAM
- AC_PAR_SUBSYSTEM_ID
- AC_PAR_VENDOR_ID
- AC_PAR_VOL_KNB_CAP
- AC_PATH_DEREGISTERED
- AC_PATH_REGISTERED
- AC_PCAP_BENIGN
- AC_PCAP_NUM_COEF
- AC_PCAP_NUM_COEF_SHIFT
- AC_PINCAP_BALANCE
- AC_PINCAP_DP
- AC_PINCAP_EAPD
- AC_PINCAP_HBR
- AC_PINCAP_HDMI
- AC_PINCAP_HP_DRV
- AC_PINCAP_IMP_SENSE
- AC_PINCAP_IN
- AC_PINCAP_LR_SWAP
- AC_PINCAP_OUT
- AC_PINCAP_PRES_DETECT
- AC_PINCAP_TRIG_REQ
- AC_PINCAP_VREF
- AC_PINCAP_VREF_100
- AC_PINCAP_VREF_50
- AC_PINCAP_VREF_80
- AC_PINCAP_VREF_GRD
- AC_PINCAP_VREF_HIZ
- AC_PINCAP_VREF_SHIFT
- AC_PINCTL_EPT
- AC_PINCTL_EPT_HBR
- AC_PINCTL_EPT_NATIVE
- AC_PINCTL_HP_EN
- AC_PINCTL_IN_EN
- AC_PINCTL_OUT_EN
- AC_PINCTL_VREFEN
- AC_PINCTL_VREF_100
- AC_PINCTL_VREF_50
- AC_PINCTL_VREF_80
- AC_PINCTL_VREF_GRD
- AC_PINCTL_VREF_HIZ
- AC_PINSENSE_ELDV
- AC_PINSENSE_IMPEDANCE_MASK
- AC_PINSENSE_PRESENCE
- AC_PWRST_ACTUAL
- AC_PWRST_ACTUAL_SHIFT
- AC_PWRST_CLKSTOP
- AC_PWRST_CLK_STOP_OK
- AC_PWRST_D0
- AC_PWRST_D0SUP
- AC_PWRST_D1
- AC_PWRST_D1SUP
- AC_PWRST_D2
- AC_PWRST_D2SUP
- AC_PWRST_D3
- AC_PWRST_D3COLDSUP
- AC_PWRST_D3SUP
- AC_PWRST_EPSS
- AC_PWRST_ERROR
- AC_PWRST_S3D3COLDSUP
- AC_PWRST_SETTING
- AC_PWRST_SETTING_RESET
- AC_PW_CONN
- AC_READ
- AC_S
- AC_SCSI_AEN
- AC_SDI_SELECT
- AC_SEGMAP
- AC_SENABLE
- AC_SENT_BDR
- AC_SETCLR
- AC_STATUS_BREAK
- AC_STATUS_CHANGED
- AC_STATUS_CONTINUE
- AC_STATUS_FOUND
- AC_SUPFMT_AC3
- AC_SUPFMT_FLOAT32
- AC_SUPFMT_PCM
- AC_SUPPCM_BITS_16
- AC_SUPPCM_BITS_20
- AC_SUPPCM_BITS_24
- AC_SUPPCM_BITS_32
- AC_SUPPCM_BITS_8
- AC_SUPPCM_RATES
- AC_SYNC_ERR
- AC_SYNC_VA
- AC_TEST_OFF
- AC_TEST_ON
- AC_TRANSFER_NEG
- AC_TXOP_CSR0
- AC_TXOP_CSR0_AC0_TX_OP
- AC_TXOP_CSR0_AC1_TX_OP
- AC_TXOP_CSR1
- AC_TXOP_CSR1_AC2_TX_OP
- AC_TXOP_CSR1_AC3_TX_OP
- AC_UARTBRK
- AC_UDVMA_ENB
- AC_UDVMA_MAP
- AC_UNSOL_ENABLED
- AC_UNSOL_RESEL
- AC_UNSOL_RES_CP_READY
- AC_UNSOL_RES_CP_STATE
- AC_UNSOL_RES_DE
- AC_UNSOL_RES_DE_SHIFT
- AC_UNSOL_RES_ELDV
- AC_UNSOL_RES_IA
- AC_UNSOL_RES_PD
- AC_UNSOL_RES_SUBTAG
- AC_UNSOL_RES_SUBTAG_SHIFT
- AC_UNSOL_RES_TAG
- AC_UNSOL_RES_TAG_SHIFT
- AC_UNSOL_TAG
- AC_USRSP_EN
- AC_VECTOR
- AC_VERB_GET_AMP_GAIN_MUTE
- AC_VERB_GET_BEEP_CONTROL
- AC_VERB_GET_COEF_INDEX
- AC_VERB_GET_CONFIG_DEFAULT
- AC_VERB_GET_CONNECT_LIST
- AC_VERB_GET_CONNECT_SEL
- AC_VERB_GET_CONV
- AC_VERB_GET_CVT_CHAN_COUNT
- AC_VERB_GET_DEVICE_LIST
- AC_VERB_GET_DEVICE_SEL
- AC_VERB_GET_DIGI_CONVERT_1
- AC_VERB_GET_DIGI_CONVERT_2
- AC_VERB_GET_EAPD_BTLENABLE
- AC_VERB_GET_GPIO_DATA
- AC_VERB_GET_GPIO_DIRECTION
- AC_VERB_GET_GPIO_MASK
- AC_VERB_GET_GPIO_STICKY_MASK
- AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK
- AC_VERB_GET_GPIO_WAKE_MASK
- AC_VERB_GET_HDMI_CHAN_SLOT
- AC_VERB_GET_HDMI_CP_CTRL
- AC_VERB_GET_HDMI_DIP_DATA
- AC_VERB_GET_HDMI_DIP_INDEX
- AC_VERB_GET_HDMI_DIP_SIZE
- AC_VERB_GET_HDMI_DIP_XMIT
- AC_VERB_GET_HDMI_ELDD
- AC_VERB_GET_PIN_SENSE
- AC_VERB_GET_PIN_WIDGET_CONTROL
- AC_VERB_GET_POWER_STATE
- AC_VERB_GET_PROC_COEF
- AC_VERB_GET_PROC_STATE
- AC_VERB_GET_SDI_SELECT
- AC_VERB_GET_STREAM_FORMAT
- AC_VERB_GET_STRIPE_CONTROL
- AC_VERB_GET_SUBSYSTEM_ID
- AC_VERB_GET_UNSOLICITED_RESPONSE
- AC_VERB_GET_VOLUME_KNOB_CONTROL
- AC_VERB_IDT_GET_POWER_MAP
- AC_VERB_IDT_SET_POWER_MAP
- AC_VERB_PARAMETERS
- AC_VERB_SET_AMP_GAIN_MUTE
- AC_VERB_SET_BEEP_CONTROL
- AC_VERB_SET_CHANNEL_STREAMID
- AC_VERB_SET_CODEC_RESET
- AC_VERB_SET_COEF_INDEX
- AC_VERB_SET_CONFIG_DEFAULT_BYTES_0
- AC_VERB_SET_CONFIG_DEFAULT_BYTES_1
- AC_VERB_SET_CONFIG_DEFAULT_BYTES_2
- AC_VERB_SET_CONFIG_DEFAULT_BYTES_3
- AC_VERB_SET_CONNECT_SEL
- AC_VERB_SET_CVT_CHAN_COUNT
- AC_VERB_SET_DEVICE_SEL
- AC_VERB_SET_DIGI_CONVERT_1
- AC_VERB_SET_DIGI_CONVERT_2
- AC_VERB_SET_DIGI_CONVERT_3
- AC_VERB_SET_EAPD
- AC_VERB_SET_EAPD_BTLENABLE
- AC_VERB_SET_GPIO_DATA
- AC_VERB_SET_GPIO_DIRECTION
- AC_VERB_SET_GPIO_MASK
- AC_VERB_SET_GPIO_STICKY_MASK
- AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK
- AC_VERB_SET_GPIO_WAKE_MASK
- AC_VERB_SET_HDMI_CHAN_SLOT
- AC_VERB_SET_HDMI_CP_CTRL
- AC_VERB_SET_HDMI_DIP_DATA
- AC_VERB_SET_HDMI_DIP_INDEX
- AC_VERB_SET_HDMI_DIP_XMIT
- AC_VERB_SET_PIN_SENSE
- AC_VERB_SET_PIN_WIDGET_CONTROL
- AC_VERB_SET_POWER_STATE
- AC_VERB_SET_PROC_COEF
- AC_VERB_SET_PROC_STATE
- AC_VERB_SET_SDI_SELECT
- AC_VERB_SET_STREAM_FORMAT
- AC_VERB_SET_STRIPE_CONTROL
- AC_VERB_SET_UNSOLICITED_ENABLE
- AC_VERB_SET_VOLUME_KNOB_CONTROL
- AC_VI
- AC_VME_VECTOR
- AC_VO
- AC_WCAP_AMP_OVRD
- AC_WCAP_CHAN_CNT_EXT
- AC_WCAP_CONN_LIST
- AC_WCAP_CP_CAPS
- AC_WCAP_DELAY
- AC_WCAP_DELAY_SHIFT
- AC_WCAP_DIGITAL
- AC_WCAP_FORMAT_OVRD
- AC_WCAP_IN_AMP
- AC_WCAP_LR_SWAP
- AC_WCAP_OUT_AMP
- AC_WCAP_POWER
- AC_WCAP_PROC_WID
- AC_WCAP_STEREO
- AC_WCAP_STRIPE
- AC_WCAP_TYPE
- AC_WCAP_TYPE_SHIFT
- AC_WCAP_UNSOL_CAP
- AC_WID_AUD_IN
- AC_WID_AUD_MIX
- AC_WID_AUD_OUT
- AC_WID_AUD_SEL
- AC_WID_BEEP
- AC_WID_PIN
- AC_WID_POWER
- AC_WID_VENDOR
- AC_WID_VOL_KNB
- AC_WRITE
- AC_XRI
- AC_param
- ACrYCb16161616_10LSB
- ACrYCb16161616_10MSB
- ACrYCb16161616_12LSB
- ACrYCb16161616_12MSB
- ACrYCb2101010
- ACrYCb8888
- AD10
- AD11
- AD12
- AD14
- AD15
- AD16
- AD1816A_3D_PHAT_CTRL
- AD1816A_ADC_PGA
- AD1816A_ADC_SOURCE_SEL
- AD1816A_CAPTURE_BASE_COUNT
- AD1816A_CAPTURE_CONFIG
- AD1816A_CAPTURE_CURR_COUNT
- AD1816A_CAPTURE_ENABLE
- AD1816A_CAPTURE_IRQ_ENABLE
- AD1816A_CAPTURE_IRQ_PENDING
- AD1816A_CAPTURE_NOT_EQUAL
- AD1816A_CAPTURE_PIO
- AD1816A_CAPTURE_SAMPLE_RATE
- AD1816A_CD_GAIN_ATT
- AD1816A_CHIP_CONFIG
- AD1816A_CHIP_STATUS
- AD1816A_DOUBLE
- AD1816A_DOUBLE_TLV
- AD1816A_DSP_CONFIG
- AD1816A_DSP_MAILBOX_0
- AD1816A_DSP_MAILBOX_1
- AD1816A_EXTERNAL_CTRL
- AD1816A_FMT_ALAW_8
- AD1816A_FMT_ALL
- AD1816A_FMT_LINEAR_16_BIG
- AD1816A_FMT_LINEAR_16_LIT
- AD1816A_FMT_LINEAR_8
- AD1816A_FMT_STEREO
- AD1816A_FMT_ULAW_8
- AD1816A_FM_ATT
- AD1816A_FM_SAMPLE_RATE
- AD1816A_HW_AD1815
- AD1816A_HW_AD1816A
- AD1816A_HW_AD18MAX10
- AD1816A_HW_AUTO
- AD1816A_HW_VOL_BUT
- AD1816A_I2S_0_ATT
- AD1816A_I2S_0_SAMPLE_RATE
- AD1816A_I2S_1_ATT
- AD1816A_I2S_1_SAMPLE_RATE
- AD1816A_INDIR_ADDR
- AD1816A_INDIR_DATA_HIGH
- AD1816A_INDIR_DATA_LOW
- AD1816A_INTERRUPT_ENABLE
- AD1816A_INTERRUPT_STATUS
- AD1816A_JOYSTICK_CTRL
- AD1816A_JOYSTICK_RAW_DATA
- AD1816A_JOY_POS_DATA_HIGH
- AD1816A_JOY_POS_DATA_LOW
- AD1816A_LINE_GAIN_ATT
- AD1816A_LOW_BYTE_TMP
- AD1816A_MASTER_ATT
- AD1816A_MIC_GAIN_ATT
- AD1816A_MODE_CAPTURE
- AD1816A_MODE_OPEN
- AD1816A_MODE_PLAYBACK
- AD1816A_MODE_TIMER
- AD1816A_PHONE_IN_GAIN_ATT
- AD1816A_PHONE_OUT_ATT
- AD1816A_PIO_DATA
- AD1816A_PIO_DEBUG
- AD1816A_PIO_STATUS
- AD1816A_PLAYBACK_BASE_COUNT
- AD1816A_PLAYBACK_CONFIG
- AD1816A_PLAYBACK_CURR_COUNT
- AD1816A_PLAYBACK_ENABLE
- AD1816A_PLAYBACK_IRQ_ENABLE
- AD1816A_PLAYBACK_IRQ_PENDING
- AD1816A_PLAYBACK_PIO
- AD1816A_PLAYBACK_SAMPLE_RATE
- AD1816A_POWERDOWN_CTRL
- AD1816A_PROGRAM_CLOCK_RATE
- AD1816A_READY
- AD1816A_REG
- AD1816A_RESERVED_10
- AD1816A_RESERVED_11
- AD1816A_RESERVED_37
- AD1816A_RESERVED_40
- AD1816A_RESERVED_46
- AD1816A_RESERVED_7
- AD1816A_SINGLE
- AD1816A_SINGLE_TLV
- AD1816A_SRC_CD
- AD1816A_SRC_LINE
- AD1816A_SRC_MASK
- AD1816A_SRC_MIC
- AD1816A_SRC_MONO
- AD1816A_SRC_OUT
- AD1816A_SRC_PHONE_IN
- AD1816A_SRC_SYNTH
- AD1816A_SRC_VIDEO
- AD1816A_SYNTH_GAIN_ATT
- AD1816A_TIMER_BASE_COUNT
- AD1816A_TIMER_CTRL
- AD1816A_TIMER_CURR_COUNT
- AD1816A_TIMER_ENABLE
- AD1816A_TIMER_IRQ_ENABLE
- AD1816A_TIMER_IRQ_PENDING
- AD1816A_VERSION_ID
- AD1816A_VID_GAIN_ATT
- AD1816A_VOICE_ATT
- AD1816A_WSS_ENABLE
- AD1835
- AD1836
- AD1836_ADC_AUX
- AD1836_ADC_CTRL1
- AD1836_ADC_CTRL2
- AD1836_ADC_CTRL3
- AD1836_ADC_HIGHPASS_FILTER
- AD1836_ADC_POWERDOWN
- AD1836_ADC_SERFMT_MASK
- AD1836_ADC_SERFMT_PCK128
- AD1836_ADC_SERFMT_PCK256
- AD1836_ADC_SWITCH
- AD1836_ADC_WORD_LEN_MASK
- AD1836_ADC_WORD_OFFSET
- AD1836_DAC_CTRL1
- AD1836_DAC_CTRL2
- AD1836_DAC_L_VOL
- AD1836_DAC_POWERDOWN
- AD1836_DAC_R_VOL
- AD1836_DAC_SERFMT_MASK
- AD1836_DAC_SERFMT_PCK128
- AD1836_DAC_SERFMT_PCK256
- AD1836_DAC_SWITCH
- AD1836_DAC_VOLUME
- AD1836_DAC_WORD_LEN_MASK
- AD1836_DAC_WORD_LEN_OFFSET
- AD1836_MUTE_LEFT
- AD1836_MUTE_RIGHT
- AD1836_NUM_REGS
- AD1836_WORD_LEN_16
- AD1836_WORD_LEN_20
- AD1836_WORD_LEN_24
- AD1838
- AD183X_DAI
- AD1843_GAIN_LINE
- AD1843_GAIN_LINE_2
- AD1843_GAIN_MIC
- AD1843_GAIN_PCM_0
- AD1843_GAIN_PCM_1
- AD1843_GAIN_RECLEV
- AD1843_GAIN_SIZE
- AD1845_AF1_MIC_LEFT
- AD1845_AF2_MIC_RIGHT
- AD1845_CLOCK
- AD1845_LWR_FREQ_SEL
- AD1845_PWR_DOWN
- AD1845_UPR_FREQ_SEL
- AD1848_THINKPAD_CS4248_ENABLE_BIT
- AD1848_THINKPAD_CTL_PORT1
- AD1848_THINKPAD_CTL_PORT2
- AD1884_FIXUP_AMP_OVERRIDE
- AD1884_FIXUP_DMIC_COEF
- AD1884_FIXUP_HP_EAPD
- AD1884_FIXUP_HP_TOUCHSMART
- AD1884_FIXUP_THINKPAD
- AD1889_DRVVER
- AD18XX_PCM_BITS
- AD18XX_PCM_VOLUME
- AD19
- AD1933
- AD1934
- AD193X
- AD193X_16_CHANNELS
- AD193X_2_CHANNELS
- AD193X_4_CHANNELS
- AD193X_8_CHANNELS
- AD193X_ADCL1_MUTE
- AD193X_ADCL2_MUTE
- AD193X_ADCR1_MUTE
- AD193X_ADCR2_MUTE
- AD193X_ADC_BCLK_INV
- AD193X_ADC_BCLK_MASTER
- AD193X_ADC_CHAN_MASK
- AD193X_ADC_CHAN_SHFT
- AD193X_ADC_CTRL0
- AD193X_ADC_CTRL1
- AD193X_ADC_CTRL2
- AD193X_ADC_FMT_MASK
- AD193X_ADC_HIGHPASS_FILTER
- AD193X_ADC_LCR_MASTER
- AD193X_ADC_LEFT_HIGH
- AD193X_ADC_POWERDOWN
- AD193X_ADC_SERFMT_AUX
- AD193X_ADC_SERFMT_MASK
- AD193X_ADC_SERFMT_STEREO
- AD193X_ADC_SERFMT_TDM
- AD193X_ADC_WORD_LEN_MASK
- AD193X_DACL1_MUTE
- AD193X_DACL2_MUTE
- AD193X_DACL3_MUTE
- AD193X_DACL4_MUTE
- AD193X_DACR1_MUTE
- AD193X_DACR2_MUTE
- AD193X_DACR3_MUTE
- AD193X_DACR4_MUTE
- AD193X_DAC_BCLK_INV
- AD193X_DAC_BCLK_MASTER
- AD193X_DAC_CHAN_MASK
- AD193X_DAC_CHAN_SHFT
- AD193X_DAC_CHNL_MUTE
- AD193X_DAC_CTRL0
- AD193X_DAC_CTRL1
- AD193X_DAC_CTRL2
- AD193X_DAC_FMT_MASK
- AD193X_DAC_L1_VOL
- AD193X_DAC_L2_VOL
- AD193X_DAC_L3_VOL
- AD193X_DAC_L4_VOL
- AD193X_DAC_LCR_MASTER
- AD193X_DAC_LEFT_HIGH
- AD193X_DAC_MASTER_MUTE
- AD193X_DAC_POWERDOWN
- AD193X_DAC_R1_VOL
- AD193X_DAC_R2_VOL
- AD193X_DAC_R3_VOL
- AD193X_DAC_R4_VOL
- AD193X_DAC_SERFMT_MASK
- AD193X_DAC_SERFMT_STEREO
- AD193X_DAC_SERFMT_TDM
- AD193X_DAC_WORD_LEN_MASK
- AD193X_DAC_WORD_LEN_SHFT
- AD193X_NUM_REGS
- AD193X_PLL_CLK_CTRL0
- AD193X_PLL_CLK_CTRL1
- AD193X_PLL_CLK_SRC_MCLK
- AD193X_PLL_CLK_SRC_PLL
- AD193X_PLL_DAC_SRC_MCLK
- AD193X_PLL_DAC_SRC_PLL
- AD193X_PLL_INPUT_256
- AD193X_PLL_INPUT_384
- AD193X_PLL_INPUT_512
- AD193X_PLL_INPUT_768
- AD193X_PLL_INPUT_MASK
- AD193X_PLL_POWERDOWN
- AD193X_PLL_SRC_MASK
- AD193X_SYSCLK_MCLK
- AD193X_SYSCLK_PLL
- AD1980_VENDOR_ID
- AD1980_VENDOR_MASK
- AD1981_FIXUP_AMP_OVERRIDE
- AD1981_FIXUP_HP_EAPD
- AD1986A_FIXUP_3STACK
- AD1986A_FIXUP_EAPD
- AD1986A_FIXUP_EAPD_MIX_IN
- AD1986A_FIXUP_EASYNOTE
- AD1986A_FIXUP_INV_JACK_DETECT
- AD1986A_FIXUP_LAPTOP
- AD1986A_FIXUP_LAPTOP_IMIC
- AD1986A_FIXUP_SAMSUNG
- AD1986A_FIXUP_ULTRA
- AD1988_FIXUP_6STACK_DIG
- AD1D0ER
- AD1D0SR
- AD1R
- AD20
- AD22
- AD23
- AD24
- AD25
- AD26
- AD2D0ER
- AD2D0SR
- AD2D1ER
- AD2D1SR
- AD2R
- AD2S1200_HZ
- AD2S1200_TSCLK
- AD2S1210_A0
- AD2S1210_A1
- AD2S1210_DEF_CONTROL
- AD2S1210_DEF_EXCIT
- AD2S1210_ENABLE_HYSTERESIS
- AD2S1210_MAX_CLKIN
- AD2S1210_MAX_EXCIT
- AD2S1210_MAX_FCW
- AD2S1210_MIN_CLKIN
- AD2S1210_MIN_EXCIT
- AD2S1210_MIN_FCW
- AD2S1210_MSB_IS_HIGH
- AD2S1210_MSB_IS_LOW
- AD2S1210_PHASE_LOCK_RANGE_44
- AD2S1210_REG_CONTROL
- AD2S1210_REG_DOS_MIS_THRD
- AD2S1210_REG_DOS_OVR_THRD
- AD2S1210_REG_DOS_RST_MAX_THRD
- AD2S1210_REG_DOS_RST_MIN_THRD
- AD2S1210_REG_EXCIT_FREQ
- AD2S1210_REG_FAULT
- AD2S1210_REG_LOS_THRD
- AD2S1210_REG_LOT_HIGH_THRD
- AD2S1210_REG_LOT_LOW_THRD
- AD2S1210_REG_POSITION
- AD2S1210_REG_SOFT_RESET
- AD2S1210_REG_VELOCITY
- AD2S1210_RES0
- AD2S1210_RES1
- AD2S1210_SAMPLE
- AD2S1210_SET_ENRES0
- AD2S1210_SET_ENRES1
- AD2S1210_SET_RES0
- AD2S1210_SET_RES1
- AD2S1210_SET_RESOLUTION
- AD2S90_MAX_SPI_FREQ_HZ
- AD3ER
- AD3R
- AD3SR
- AD5064_ADDR
- AD5064_ADDR_ALL_DAC
- AD5064_CHANNEL
- AD5064_CMD
- AD5064_CMD_CLEAR
- AD5064_CMD_CONFIG
- AD5064_CMD_CONFIG_V2
- AD5064_CMD_LDAC_MASK
- AD5064_CMD_POWERDOWN_DAC
- AD5064_CMD_RESET
- AD5064_CMD_RESET_V2
- AD5064_CMD_UPDATE_DAC_N
- AD5064_CMD_WRITE_INPUT_N
- AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL
- AD5064_CMD_WRITE_INPUT_N_UPDATE_N
- AD5064_CONFIG_DAISY_CHAIN_ENABLE
- AD5064_CONFIG_INT_VREF_ENABLE
- AD5064_LDAC_PWRDN_100K
- AD5064_LDAC_PWRDN_1K
- AD5064_LDAC_PWRDN_3STATE
- AD5064_LDAC_PWRDN_NONE
- AD5064_MAX_DAC_CHANNELS
- AD5064_MAX_VREFS
- AD5064_REGMAP_ADI
- AD5064_REGMAP_ADI2
- AD5064_REGMAP_LTC
- AD5160_ID
- AD5161_ID
- AD5162_ID
- AD5165_ID
- AD5170_ID
- AD5171_ID
- AD5172_ID
- AD5173_ID
- AD5200_ID
- AD5201_ID
- AD5203_ID
- AD5204_ID
- AD5206_ID
- AD5207_ID
- AD5231_ID
- AD5232_ID
- AD5233_ID
- AD5235_ID
- AD5241_ID
- AD5242_ID
- AD5243_ID
- AD5245_ID
- AD5246_ID
- AD5247_ID
- AD5248_ID
- AD5251_ID
- AD5252_ID
- AD5253_ID
- AD5254_ID
- AD5255_ID
- AD5258_ID
- AD5259_ID
- AD5260_ID
- AD5262_ID
- AD5263_ID
- AD5270_ID
- AD5271_ID
- AD5272_020
- AD5272_050
- AD5272_100
- AD5272_CTL
- AD5272_ID
- AD5272_RDAC_RD
- AD5272_RDAC_WR
- AD5272_RDAC_WR_EN
- AD5272_RESET
- AD5273_ID
- AD5274_020
- AD5274_100
- AD5274_ID
- AD5280_ID
- AD5282_ID
- AD5290_ID
- AD5291_ID
- AD5292_ID
- AD5293_ID
- AD5310_CMD
- AD5310_REF_BIT_MSK
- AD5310_REGMAP
- AD5360_ADDR
- AD5360_CHANNEL
- AD5360_CHAN_ADDR
- AD5360_CMD
- AD5360_CMD_SPECIAL_FUNCTION
- AD5360_CMD_WRITE_DATA
- AD5360_CMD_WRITE_GAIN
- AD5360_CMD_WRITE_OFFSET
- AD5360_READBACK_ADDR
- AD5360_READBACK_GAIN
- AD5360_READBACK_OFFSET
- AD5360_READBACK_SF
- AD5360_READBACK_TYPE
- AD5360_READBACK_X1A
- AD5360_READBACK_X1B
- AD5360_REG_SF_CTRL
- AD5360_REG_SF_NOP
- AD5360_REG_SF_OFS
- AD5360_REG_SF_READBACK
- AD5360_SF_CTRL_PWR_DOWN
- AD5380_CHANNEL
- AD5380_CTRL_INT_VREF_2V5
- AD5380_CTRL_INT_VREF_EN
- AD5380_CTRL_PWR_DOWN_MODE_OFFSET
- AD5380_REG_DATA
- AD5380_REG_GAIN
- AD5380_REG_OFFSET
- AD5380_REG_SF_CTRL
- AD5380_REG_SF_PWR_DOWN
- AD5380_REG_SF_PWR_UP
- AD5398_CURRENT_EN_MASK
- AD5421_CTRL_ADC_ENABLE
- AD5421_CTRL_ADC_SOURCE_TEMP
- AD5421_CTRL_AUTO_FAULT_READBACK
- AD5421_CTRL_MIN_CURRENT
- AD5421_CTRL_PWR_DOWN_INT_VREF
- AD5421_CTRL_WATCHDOG_DISABLE
- AD5421_CURRENT_RANGE_3mA2_24mA
- AD5421_CURRENT_RANGE_3mA8_21mA
- AD5421_CURRENT_RANGE_4mA_20mA
- AD5421_FAULT_OVER_CURRENT
- AD5421_FAULT_PEC
- AD5421_FAULT_SPI
- AD5421_FAULT_TEMP_OVER_100
- AD5421_FAULT_TEMP_OVER_140
- AD5421_FAULT_TRIGGER_IRQ
- AD5421_FAULT_UNDER_CURRENT
- AD5421_FAULT_UNDER_VOLTAGE_12V
- AD5421_FAULT_UNDER_VOLTAGE_6V
- AD5421_REG_CTRL
- AD5421_REG_DAC_DATA
- AD5421_REG_FAULT
- AD5421_REG_FORCE_ALARM_CURRENT
- AD5421_REG_GAIN
- AD5421_REG_LOAD_DAC
- AD5421_REG_NOOP
- AD5421_REG_OFFSET
- AD5421_REG_RESET
- AD5421_REG_START_CONVERSION
- AD5446_CHANNEL
- AD5446_CHANNEL_POWERDOWN
- AD5449_CHANNEL
- AD5449_CMD_CTRL
- AD5449_CMD_LOAD
- AD5449_CMD_LOAD_AND_UPDATE
- AD5449_CMD_NOOP
- AD5449_CMD_READ
- AD5449_CTRL_DAISY_CHAIN
- AD5449_CTRL_HCLR_TO_MIDSCALE
- AD5449_CTRL_SAMPLE_RISING
- AD5449_CTRL_SDO_OFFSET
- AD5449_MAX_CHANNELS
- AD5449_MAX_VREFS
- AD5449_SDO_DISABLED
- AD5449_SDO_DRIVE_FULL
- AD5449_SDO_DRIVE_WEAK
- AD5449_SDO_OPEN_DRAIN
- AD5504_ADDR
- AD5504_ADDR_ALL_DAC
- AD5504_ADDR_CTRL
- AD5504_ADDR_DAC
- AD5504_ADDR_NOOP
- AD5504_CHANNEL
- AD5504_CMD_READ
- AD5504_CMD_WRITE
- AD5504_DAC_PWR
- AD5504_DAC_PWRDN_20K
- AD5504_DAC_PWRDN_3STATE
- AD5504_DAC_PWRDWN_MODE
- AD5504_RES_MASK
- AD5592R_GPIO_READBACK_EN
- AD5592R_LDAC_READBACK_EN
- AD5592R_REG_ADC_EN
- AD5592R_REG_ADC_SEQ
- AD5592R_REG_CTRL
- AD5592R_REG_CTRL_ADC_RANGE
- AD5592R_REG_CTRL_DAC_RANGE
- AD5592R_REG_DAC_EN
- AD5592R_REG_DAC_READBACK
- AD5592R_REG_GPIO_IN_EN
- AD5592R_REG_GPIO_OUT_EN
- AD5592R_REG_GPIO_SET
- AD5592R_REG_LDAC
- AD5592R_REG_NOOP
- AD5592R_REG_OPEN_DRAIN
- AD5592R_REG_PD
- AD5592R_REG_PD_EN_REF
- AD5592R_REG_PULLDOWN
- AD5592R_REG_RESET
- AD5592R_REG_TRISTATE
- AD5593R_MODE_ADC_READBACK
- AD5593R_MODE_CONF
- AD5593R_MODE_DAC_READBACK
- AD5593R_MODE_DAC_WRITE
- AD5593R_MODE_GPIO_READBACK
- AD5593R_MODE_REG_READBACK
- AD5624R_ADDR_ALL_DAC
- AD5624R_ADDR_DAC0
- AD5624R_ADDR_DAC1
- AD5624R_ADDR_DAC2
- AD5624R_ADDR_DAC3
- AD5624R_CHANNEL
- AD5624R_CMD_INTERNAL_REFER_SETUP
- AD5624R_CMD_LDAC_SETUP
- AD5624R_CMD_POWERDOWN_DAC
- AD5624R_CMD_RESET
- AD5624R_CMD_UPDATE_DAC_N
- AD5624R_CMD_WRITE_INPUT_N
- AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL
- AD5624R_CMD_WRITE_INPUT_N_UPDATE_N
- AD5624R_DAC_CHANNELS
- AD5624R_LDAC_PWRDN_100K
- AD5624R_LDAC_PWRDN_1K
- AD5624R_LDAC_PWRDN_3STATE
- AD5624R_LDAC_PWRDN_NONE
- AD5683_DATA
- AD5683_REF_BIT_MSK
- AD5683_REGMAP
- AD5686_ADDR
- AD5686_ADDR_ALL_DAC
- AD5686_ADDR_DAC
- AD5686_CMD
- AD5686_CMD_CONTROL_REG
- AD5686_CMD_DAISY_CHAIN_ENABLE
- AD5686_CMD_INTERNAL_REFER_SETUP
- AD5686_CMD_LDAC_MASK
- AD5686_CMD_NOOP
- AD5686_CMD_POWERDOWN_DAC
- AD5686_CMD_READBACK_ENABLE
- AD5686_CMD_READBACK_ENABLE_V2
- AD5686_CMD_RESET
- AD5686_CMD_UPDATE_DAC_N
- AD5686_CMD_WRITE_INPUT_N
- AD5686_CMD_WRITE_INPUT_N_UPDATE_N
- AD5686_LDAC_PWRDN_100K
- AD5686_LDAC_PWRDN_1K
- AD5686_LDAC_PWRDN_3STATE
- AD5686_LDAC_PWRDN_NONE
- AD5686_REGMAP
- AD5693_REF_BIT_MSK
- AD5693_REGMAP
- AD5755_ADDR
- AD5755_CHANNEL
- AD5755_CTRL_REG_DAC
- AD5755_CTRL_REG_DC_DC
- AD5755_CTRL_REG_MAIN
- AD5755_CTRL_REG_SLEW
- AD5755_CTRL_REG_SW
- AD5755_DAC_CLR_EN
- AD5755_DAC_DC_DC_EN
- AD5755_DAC_INT_CURRENT_SENSE_RESISTOR
- AD5755_DAC_INT_EN
- AD5755_DAC_OUT_EN
- AD5755_DAC_VOLTAGE_OVERRANGE_EN
- AD5755_DC_DC_FREQ_250kHZ
- AD5755_DC_DC_FREQ_410kHZ
- AD5755_DC_DC_FREQ_650kHZ
- AD5755_DC_DC_FREQ_SHIFT
- AD5755_DC_DC_MAXV
- AD5755_DC_DC_MAXV_23V
- AD5755_DC_DC_MAXV_24V5
- AD5755_DC_DC_MAXV_27V
- AD5755_DC_DC_MAXV_29V5
- AD5755_DC_DC_PHASE_90_DEGREE
- AD5755_DC_DC_PHASE_ALL_SAME_EDGE
- AD5755_DC_DC_PHASE_A_B_SAME_EDGE_C_D_OPP_EDGE
- AD5755_DC_DC_PHASE_A_C_SAME_EDGE_B_D_OPP_EDGE
- AD5755_DC_DC_PHASE_SHIFT
- AD5755_DEFAULT_DAC_PDATA
- AD5755_EXT_DC_DC_COMP_RES
- AD5755_MODE_CURRENT_0mA_20mA
- AD5755_MODE_CURRENT_0mA_24mA
- AD5755_MODE_CURRENT_4mA_20mA
- AD5755_MODE_VOLTAGE_0V_10V
- AD5755_MODE_VOLTAGE_0V_5V
- AD5755_MODE_VOLTAGE_PLUSMINUS_10V
- AD5755_MODE_VOLTAGE_PLUSMINUS_5V
- AD5755_NOOP
- AD5755_NUM_CHANNELS
- AD5755_READ_FLAG
- AD5755_READ_REG_CLEAR
- AD5755_READ_REG_CTRL
- AD5755_READ_REG_DATA
- AD5755_READ_REG_DC_DC
- AD5755_READ_REG_GAIN
- AD5755_READ_REG_MAIN
- AD5755_READ_REG_OFFSET
- AD5755_READ_REG_SLEW
- AD5755_READ_REG_STATUS
- AD5755_SLEW_ENABLE
- AD5755_SLEW_RATE_0_5
- AD5755_SLEW_RATE_125
- AD5755_SLEW_RATE_16
- AD5755_SLEW_RATE_16k
- AD5755_SLEW_RATE_1k
- AD5755_SLEW_RATE_250
- AD5755_SLEW_RATE_2k
- AD5755_SLEW_RATE_32
- AD5755_SLEW_RATE_32k
- AD5755_SLEW_RATE_4
- AD5755_SLEW_RATE_4k
- AD5755_SLEW_RATE_500
- AD5755_SLEW_RATE_64
- AD5755_SLEW_RATE_64k
- AD5755_SLEW_RATE_8
- AD5755_SLEW_RATE_8k
- AD5755_SLEW_RATE_SHIFT
- AD5755_SLEW_STEP_SIZE_1
- AD5755_SLEW_STEP_SIZE_128
- AD5755_SLEW_STEP_SIZE_16
- AD5755_SLEW_STEP_SIZE_2
- AD5755_SLEW_STEP_SIZE_256
- AD5755_SLEW_STEP_SIZE_32
- AD5755_SLEW_STEP_SIZE_4
- AD5755_SLEW_STEP_SIZE_64
- AD5755_SLEW_STEP_SIZE_8
- AD5755_SLEW_STEP_SIZE_SHIFT
- AD5755_WRITE_REG_CTRL
- AD5755_WRITE_REG_DATA
- AD5755_WRITE_REG_GAIN
- AD5755_WRITE_REG_OFFSET
- AD5758_ADC_CONFIG
- AD5758_ADC_CONFIG_PPC_BUF_EN
- AD5758_ADC_CONFIG_PPC_BUF_MSK
- AD5758_ANALOG_DIAG_RESULTS
- AD5758_CAL_MEM_UNREFRESHED_MSK
- AD5758_CHIP_ID
- AD5758_CLEAR_CODE
- AD5758_DAC_CHAN
- AD5758_DAC_CONFIG
- AD5758_DAC_CONFIG_INT_EN_MODE
- AD5758_DAC_CONFIG_INT_EN_MSK
- AD5758_DAC_CONFIG_OUT_EN_MODE
- AD5758_DAC_CONFIG_OUT_EN_MSK
- AD5758_DAC_CONFIG_RANGE_MODE
- AD5758_DAC_CONFIG_RANGE_MSK
- AD5758_DAC_CONFIG_SR_CLOCK_MODE
- AD5758_DAC_CONFIG_SR_CLOCK_MSK
- AD5758_DAC_CONFIG_SR_EN_MODE
- AD5758_DAC_CONFIG_SR_EN_MSK
- AD5758_DAC_CONFIG_SR_STEP_MODE
- AD5758_DAC_CONFIG_SR_STEP_MSK
- AD5758_DAC_INPUT
- AD5758_DAC_OUTPUT
- AD5758_DCDC_CONFIG1
- AD5758_DCDC_CONFIG1_DCDC_MODE_MODE
- AD5758_DCDC_CONFIG1_DCDC_MODE_MSK
- AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE
- AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK
- AD5758_DCDC_CONFIG2
- AD5758_DCDC_CONFIG2_BUSY_3WI_MSK
- AD5758_DCDC_CONFIG2_ILIMIT_MODE
- AD5758_DCDC_CONFIG2_ILIMIT_MSK
- AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK
- AD5758_DCDC_MODE_DPC_CURRENT
- AD5758_DCDC_MODE_DPC_VOLTAGE
- AD5758_DCDC_MODE_POWER_OFF
- AD5758_DCDC_MODE_PPC_CURRENT
- AD5758_DEVICE_ID_0
- AD5758_DEVICE_ID_1
- AD5758_DEVICE_ID_2
- AD5758_DEVICE_ID_3
- AD5758_DIGITAL_DIAG_CONFIG
- AD5758_DIGITAL_DIAG_RESULTS
- AD5758_FAULT_PIN_CONFIG
- AD5758_FREQ_MONITOR
- AD5758_FULL_SCALE_MICRO
- AD5758_GP_CONFIG1
- AD5758_GP_CONFIG2
- AD5758_KEY
- AD5758_KEY_CODE_CALIB_MEM_REFRESH
- AD5758_KEY_CODE_RESET_1
- AD5758_KEY_CODE_RESET_2
- AD5758_KEY_CODE_RESET_WDT
- AD5758_KEY_CODE_SINGLE_ADC_CONV
- AD5758_NOP
- AD5758_RANGE_0V_10V
- AD5758_RANGE_0V_5V
- AD5758_RANGE_0mA_20mA
- AD5758_RANGE_0mA_24mA
- AD5758_RANGE_4mA_24mA
- AD5758_RANGE_MINUS_1mA_PLUS_22mA
- AD5758_RANGE_PLUSMINUS_10V
- AD5758_RANGE_PLUSMINUS_20mA
- AD5758_RANGE_PLUSMINUS_24mA
- AD5758_RANGE_PLUSMINUS_5V
- AD5758_STATUS
- AD5758_SW_LDAC
- AD5758_TWO_STAGE_READBACK_SELECT
- AD5758_USER_GAIN
- AD5758_USER_OFFSET
- AD5758_WDT_CONFIG
- AD5758_WR_FLAG_MSK
- AD5761_ADDR
- AD5761_ADDR_CTRL_READ_REG
- AD5761_ADDR_CTRL_WRITE_REG
- AD5761_ADDR_DAC_READ
- AD5761_ADDR_DAC_WRITE
- AD5761_ADDR_NOOP
- AD5761_ADDR_SW_DATA_RESET
- AD5761_ADDR_SW_FULL_RESET
- AD5761_CHAN
- AD5761_CTRL_ETS
- AD5761_CTRL_LINCOMP
- AD5761_CTRL_USE_INTVREF
- AD5761_VOLTAGE_RANGE_0V_10V
- AD5761_VOLTAGE_RANGE_0V_16V
- AD5761_VOLTAGE_RANGE_0V_20V
- AD5761_VOLTAGE_RANGE_0V_5V
- AD5761_VOLTAGE_RANGE_M10V_10V
- AD5761_VOLTAGE_RANGE_M2V5_7V5
- AD5761_VOLTAGE_RANGE_M3V_3V
- AD5761_VOLTAGE_RANGE_M5V_5V
- AD5764_CHANNEL
- AD5764_NUM_CHANNELS
- AD5764_REG_COARSE_GAIN
- AD5764_REG_DATA
- AD5764_REG_FINE_GAIN
- AD5764_REG_OFFSET
- AD5764_REG_SF_CLEAR
- AD5764_REG_SF_CONFIG
- AD5764_REG_SF_LOAD
- AD5764_REG_SF_NOP
- AD5780_LINCOMP_0_10
- AD5780_LINCOMP_10_20
- AD5791_ADDR
- AD5791_ADDR_CLRCODE
- AD5791_ADDR_CTRL
- AD5791_ADDR_DAC0
- AD5791_ADDR_NOOP
- AD5791_ADDR_SW_CTRL
- AD5791_CHAN
- AD5791_CMD_READ
- AD5791_CMD_WRITE
- AD5791_CTRL_BIN2SC
- AD5791_CTRL_DACTRI
- AD5791_CTRL_OPGND
- AD5791_CTRL_RBUF
- AD5791_CTRL_SDODIS
- AD5791_DAC_MASK
- AD5791_DAC_PWRDN_3STATE
- AD5791_DAC_PWRDN_6K
- AD5791_LINCOMP_0_10
- AD5791_LINCOMP_10_12
- AD5791_LINCOMP_12_16
- AD5791_LINCOMP_16_19
- AD5791_LINCOMP_19_20
- AD5791_SWCTRL_CLR
- AD5791_SWCTRL_LDAC
- AD5791_SWCTRL_RESET
- AD5820_DAC_SHIFT
- AD5820_NAME
- AD5820_POWER_DOWN
- AD5820_RAMP_MODE_64_16
- AD5820_RAMP_MODE_LINEAR
- AD5868_CHANNEL
- AD5933_CHANNEL
- AD5933_CTRL_EXT_SYSCLK
- AD5933_CTRL_INC_FREQ
- AD5933_CTRL_INIT_START_FREQ
- AD5933_CTRL_INT_SYSCLK
- AD5933_CTRL_MEASURE_TEMP
- AD5933_CTRL_PGA_GAIN_1
- AD5933_CTRL_PGA_GAIN_5
- AD5933_CTRL_POWER_DOWN
- AD5933_CTRL_RANGE
- AD5933_CTRL_RANGE_1000mVpp
- AD5933_CTRL_RANGE_2000mVpp
- AD5933_CTRL_RANGE_200mVpp
- AD5933_CTRL_RANGE_400mVpp
- AD5933_CTRL_REPEAT_FREQ
- AD5933_CTRL_RESET
- AD5933_CTRL_STANDBY
- AD5933_CTRL_START_SWEEP
- AD5933_FREQ_POINTS
- AD5933_I2C_ADDR_POINTER
- AD5933_I2C_BLOCK_READ
- AD5933_I2C_BLOCK_WRITE
- AD5933_INIT_EXCITATION_TIME_ms
- AD5933_INT_OSC_FREQ_Hz
- AD5933_IN_PGA_GAIN
- AD5933_IN_PGA_GAIN_AVAIL
- AD5933_MAX_OUTPUT_FREQ_Hz
- AD5933_MAX_RETRIES
- AD5933_OUT_RANGE
- AD5933_OUT_RANGE_AVAIL
- AD5933_OUT_SETTLING_CYCLES
- AD5933_POLL_TIME_ms
- AD5933_REG_CONTROL_HB
- AD5933_REG_CONTROL_LB
- AD5933_REG_FREQ_INC
- AD5933_REG_FREQ_START
- AD5933_REG_IMAG_DATA
- AD5933_REG_INC_NUM
- AD5933_REG_REAL_DATA
- AD5933_REG_SETTLING_CYCLES
- AD5933_REG_STATUS
- AD5933_REG_TEMP_DATA
- AD5933_STAT_DATA_VALID
- AD5933_STAT_SWEEP_DONE
- AD5933_STAT_TEMP_VALID
- AD7
- AD7091R_CHAN
- AD7124_ADC_CONTROL
- AD7124_ADC_CTRL_MODE
- AD7124_ADC_CTRL_MODE_MSK
- AD7124_ADC_CTRL_PWR
- AD7124_ADC_CTRL_PWR_MSK
- AD7124_ADC_CTRL_REF_EN
- AD7124_ADC_CTRL_REF_EN_MSK
- AD7124_AVDD_REF
- AD7124_CHANNEL
- AD7124_CHANNEL_AINM
- AD7124_CHANNEL_AINM_MSK
- AD7124_CHANNEL_AINP
- AD7124_CHANNEL_AINP_MSK
- AD7124_CHANNEL_EN
- AD7124_CHANNEL_EN_MSK
- AD7124_CHANNEL_SETUP
- AD7124_CHANNEL_SETUP_MSK
- AD7124_COMMS
- AD7124_CONFIG
- AD7124_CONFIG_BIPOLAR
- AD7124_CONFIG_BIPOLAR_MSK
- AD7124_CONFIG_IN_BUFF
- AD7124_CONFIG_IN_BUFF_MSK
- AD7124_CONFIG_PGA
- AD7124_CONFIG_PGA_MSK
- AD7124_CONFIG_REF_SEL
- AD7124_CONFIG_REF_SEL_MSK
- AD7124_DATA
- AD7124_ERROR
- AD7124_ERROR_EN
- AD7124_FILTER
- AD7124_FILTER_FS
- AD7124_FILTER_FS_MSK
- AD7124_FULL_POWER
- AD7124_GAIN
- AD7124_ID
- AD7124_INT_REF
- AD7124_IO_CONTROL_1
- AD7124_IO_CONTROL_2
- AD7124_LOW_POWER
- AD7124_MCLK_COUNT
- AD7124_MID_POWER
- AD7124_OFFSET
- AD7124_REFIN1
- AD7124_REFIN2
- AD7124_STATUS
- AD7124_STATUS_POR_FLAG_MSK
- AD7142_PARTID
- AD7143_PARTID
- AD7147_PARTID
- AD7148_PARTID
- AD714X_AMB_COMP_CTRL0_REG
- AD714X_PARTID_REG
- AD714X_PWR_CTRL
- AD714X_STAGECFG_REG
- AD714X_STG_CAL_EN_REG
- AD714X_SYSCFG_REG
- AD714x_SPI_CMD_PREFIX
- AD714x_SPI_READ
- AD7150_CAPACITANCE_CHAN
- AD7150_CFG
- AD7150_CFG_FIX
- AD7150_CH1_AVG_HIGH
- AD7150_CH1_CAPDAC
- AD7150_CH1_DATA_HIGH
- AD7150_CH1_SENSITIVITY
- AD7150_CH1_SETUP
- AD7150_CH1_THR_HOLD_H
- AD7150_CH1_TIMEOUT
- AD7150_CH2_AVG_HIGH
- AD7150_CH2_CAPDAC
- AD7150_CH2_DATA_HIGH
- AD7150_CH2_SENSITIVITY
- AD7150_CH2_SETUP
- AD7150_CH2_THR_HOLD_H
- AD7150_CH2_TIMEOUT
- AD7150_ID
- AD7150_PD_TIMER
- AD7150_SN0
- AD7150_SN1
- AD7150_SN2
- AD7150_SN3
- AD7150_STATUS
- AD7150_STATUS_OUT1
- AD7150_STATUS_OUT2
- AD7150_THRESHTYPE_MSK
- AD7150_TIMEOUT
- AD7170_CHANNEL
- AD7170_ID
- AD7170_PATTERN_GOOD
- AD7170_PATTERN_MASK
- AD7171_ID
- AD7192_CH_AIN1
- AD7192_CH_AIN1P_AIN2M
- AD7192_CH_AIN2
- AD7192_CH_AIN2P_AIN2M
- AD7192_CH_AIN3
- AD7192_CH_AIN3P_AIN4M
- AD7192_CH_AIN4
- AD7192_CH_TEMP
- AD7192_CLK_EXT_MCLK1_2
- AD7192_CLK_EXT_MCLK2
- AD7192_CLK_INT
- AD7192_CLK_INT_CO
- AD7192_COMM_ADDR
- AD7192_COMM_CREAD
- AD7192_COMM_READ
- AD7192_COMM_WEN
- AD7192_COMM_WRITE
- AD7192_CONF_BUF
- AD7192_CONF_BURN
- AD7192_CONF_CHAN
- AD7192_CONF_CHAN_MASK
- AD7192_CONF_CHOP
- AD7192_CONF_GAIN
- AD7192_CONF_REFDET
- AD7192_CONF_REFSEL
- AD7192_CONF_UNIPOLAR
- AD7192_EXT_FREQ_MHZ_MAX
- AD7192_EXT_FREQ_MHZ_MIN
- AD7192_GPOCON_BPDSW
- AD7192_GPOCON_GP10EN
- AD7192_GPOCON_GP32EN
- AD7192_GPOCON_P0DAT
- AD7192_GPOCON_P1DAT
- AD7192_GPOCON_P2DAT
- AD7192_GPOCON_P3DAT
- AD7192_ID_MASK
- AD7192_INT_FREQ_MHZ
- AD7192_MODE_ACX
- AD7192_MODE_CAL_INT_FULL
- AD7192_MODE_CAL_INT_ZERO
- AD7192_MODE_CAL_SYS_FULL
- AD7192_MODE_CAL_SYS_ZERO
- AD7192_MODE_CLKDIV
- AD7192_MODE_CLKSRC
- AD7192_MODE_CONT
- AD7192_MODE_DAT_STA
- AD7192_MODE_ENPAR
- AD7192_MODE_IDLE
- AD7192_MODE_PWRDN
- AD7192_MODE_RATE
- AD7192_MODE_REJ60
- AD7192_MODE_SCYCLE
- AD7192_MODE_SEL
- AD7192_MODE_SEL_MASK
- AD7192_MODE_SINC3
- AD7192_MODE_SINGLE
- AD7192_NO_SYNC_FILTER
- AD7192_REG_COMM
- AD7192_REG_CONF
- AD7192_REG_DATA
- AD7192_REG_FULLSALE
- AD7192_REG_GPOCON
- AD7192_REG_ID
- AD7192_REG_MODE
- AD7192_REG_OFFSET
- AD7192_REG_STAT
- AD7192_STAT_CH1
- AD7192_STAT_CH2
- AD7192_STAT_CH3
- AD7192_STAT_ERR
- AD7192_STAT_NOREF
- AD7192_STAT_PARITY
- AD7192_STAT_RDY
- AD7192_SYNC3_FILTER
- AD7192_SYNC4_FILTER
- AD7193_CH_AIN1
- AD7193_CH_AIN1P_AIN2M
- AD7193_CH_AIN2
- AD7193_CH_AIN2P_AIN2M
- AD7193_CH_AIN3
- AD7193_CH_AIN3P_AIN4M
- AD7193_CH_AIN4
- AD7193_CH_AIN5
- AD7193_CH_AIN5P_AIN6M
- AD7193_CH_AIN6
- AD7193_CH_AIN7
- AD7193_CH_AIN7P_AIN8M
- AD7193_CH_AIN8
- AD7193_CH_AINCOM
- AD7193_CH_TEMP
- AD7266_CHAN
- AD7266_CHAN_DIFF
- AD7266_CHAN_INFO_INDEX
- AD7266_DECLARE_DIFF_CHANNELS
- AD7266_DECLARE_DIFF_CHANNELS_FIXED
- AD7266_DECLARE_SINGLE_ENDED_CHANNELS
- AD7266_DECLARE_SINGLE_ENDED_CHANNELS_FIXED
- AD7266_MODE_DIFF
- AD7266_MODE_PSEUDO_DIFF
- AD7266_MODE_SINGLE_ENDED
- AD7266_RANGE_2VREF
- AD7266_RANGE_VREF
- AD7280A_ACQ_TIME_1200ns
- AD7280A_ACQ_TIME_1600ns
- AD7280A_ACQ_TIME_400ns
- AD7280A_ACQ_TIME_800ns
- AD7280A_ALERT
- AD7280A_ALERT_GEN_STATIC_HIGH
- AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN
- AD7280A_ALERT_REMOVE_AUX4_AUX5
- AD7280A_ALERT_REMOVE_AUX5
- AD7280A_ALERT_REMOVE_VIN4_VIN5
- AD7280A_ALERT_REMOVE_VIN5
- AD7280A_ALL_CELLS
- AD7280A_AUX_ADC_1
- AD7280A_AUX_ADC_2
- AD7280A_AUX_ADC_3
- AD7280A_AUX_ADC_4
- AD7280A_AUX_ADC_5
- AD7280A_AUX_ADC_6
- AD7280A_AUX_ADC_OVERVOLTAGE
- AD7280A_AUX_ADC_UNDERVOLTAGE
- AD7280A_BITS
- AD7280A_CALC_TEMP_CHAN_NUM
- AD7280A_CALC_VOLTAGE_CHAN_NUM
- AD7280A_CB1_TIMER
- AD7280A_CB2_TIMER
- AD7280A_CB3_TIMER
- AD7280A_CB4_TIMER
- AD7280A_CB5_TIMER
- AD7280A_CB6_TIMER
- AD7280A_CELLS_PER_DEV
- AD7280A_CELL_BALANCE
- AD7280A_CELL_OVERVOLTAGE
- AD7280A_CELL_UNDERVOLTAGE
- AD7280A_CELL_VOLTAGE_1
- AD7280A_CELL_VOLTAGE_2
- AD7280A_CELL_VOLTAGE_3
- AD7280A_CELL_VOLTAGE_4
- AD7280A_CELL_VOLTAGE_5
- AD7280A_CELL_VOLTAGE_6
- AD7280A_CNVST_CONTROL
- AD7280A_CONTROL_HB
- AD7280A_CONTROL_LB
- AD7280A_CONV_AVG_2
- AD7280A_CONV_AVG_4
- AD7280A_CONV_AVG_8
- AD7280A_CONV_AVG_DIS
- AD7280A_CTRL_HB_CONV_AVG
- AD7280A_CTRL_HB_CONV_AVG_2
- AD7280A_CTRL_HB_CONV_AVG_4
- AD7280A_CTRL_HB_CONV_AVG_8
- AD7280A_CTRL_HB_CONV_AVG_DIS
- AD7280A_CTRL_HB_CONV_INPUT_6CELL
- AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4
- AD7280A_CTRL_HB_CONV_INPUT_ALL
- AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST
- AD7280A_CTRL_HB_CONV_RES_READ_6CELL
- AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4
- AD7280A_CTRL_HB_CONV_RES_READ_ALL
- AD7280A_CTRL_HB_CONV_RES_READ_NO
- AD7280A_CTRL_HB_CONV_START_CNVST
- AD7280A_CTRL_HB_CONV_START_CS
- AD7280A_CTRL_HB_PWRDN_SW
- AD7280A_CTRL_LB_ACQ_TIME
- AD7280A_CTRL_LB_ACQ_TIME_1200ns
- AD7280A_CTRL_LB_ACQ_TIME_1600ns
- AD7280A_CTRL_LB_ACQ_TIME_400ns
- AD7280A_CTRL_LB_ACQ_TIME_800ns
- AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN
- AD7280A_CTRL_LB_INC_DEV_ADDR
- AD7280A_CTRL_LB_LOCK_DEV_ADDR
- AD7280A_CTRL_LB_MUST_SET
- AD7280A_CTRL_LB_SWRST
- AD7280A_CTRL_LB_THERMISTOR_EN
- AD7280A_DEVADDR_ALL
- AD7280A_DEVADDR_MASTER
- AD7280A_MAX_CHAIN
- AD7280A_MAX_SPI_CLK_HZ
- AD7280A_NUM_CH
- AD7280A_PD_TIMER
- AD7280A_READ
- AD7280A_READ_TXVAL
- AD7280A_SELF_TEST
- AD7291_ALERT_CLEAR
- AD7291_ALERT_POLARITY
- AD7291_AUTOCYCLE
- AD7291_BITS
- AD7291_COMMAND
- AD7291_DATA_HIGH
- AD7291_DATA_LOW
- AD7291_EXT_REF
- AD7291_HYST
- AD7291_NOISE_DELAY
- AD7291_RESET
- AD7291_T_ALERT_STATUS
- AD7291_T_AVERAGE
- AD7291_T_AVG_HIGH
- AD7291_T_AVG_LOW
- AD7291_T_HIGH
- AD7291_T_LOW
- AD7291_T_SENSE
- AD7291_T_SENSE_MASK
- AD7291_VALUE_MASK
- AD7291_VOLTAGE
- AD7291_VOLTAGE_ALERT_STATUS
- AD7291_VOLTAGE_CHAN
- AD7291_VOLTAGE_LIMIT_COUNT
- AD7291_VOLTAGE_MASK
- AD7291_VOLTAGE_OFFSET
- AD7291_V_HIGH
- AD7291_V_LOW
- AD7298_CH
- AD7298_CH_TEMP
- AD7298_EXTREF
- AD7298_INTREF_mV
- AD7298_MAX_CHAN
- AD7298_PDD
- AD7298_REPEAT
- AD7298_TAVG
- AD7298_TSENSE
- AD7298_V_CHAN
- AD7298_WRITE
- AD7303_CFG_ADDR_OFFSET
- AD7303_CFG_EXTERNAL_VREF
- AD7303_CFG_POWER_DOWN
- AD7303_CHANNEL
- AD7303_CMD_UPDATE_DAC
- AD7310_COMMAND
- AD7314_TEMP_MASK
- AD7314_TEMP_SHIFT
- AD7376_ID
- AD7414_REG_CONF
- AD7414_REG_TEMP
- AD7414_REG_T_HIGH
- AD7414_REG_T_LOW
- AD7418_CH_TEMP
- AD7418_REG_ADC
- AD7418_REG_ADC_CH
- AD7418_REG_CONF
- AD7418_REG_CONF2
- AD7418_REG_TEMP_HYST
- AD7418_REG_TEMP_IN
- AD7418_REG_TEMP_OS
- AD7466_EXCLVL_0
- AD7466_EXCLVL_1
- AD7466_EXCLVL_2
- AD7466_EXCLVL_3
- AD7476_CHAN
- AD7605_CHANNEL
- AD7606_CHANNEL
- AD7606_CONFIGURATION_REGISTER
- AD7606_OS_MODE
- AD7606_PM_OPS
- AD7606_RANGE_CH_ADDR
- AD7606_RANGE_CH_MODE
- AD7606_RANGE_CH_MSK
- AD7606_SINGLE_DOUT
- AD760X_CHANNEL
- AD7616_BURST_MODE
- AD7616_CHANNEL
- AD7616_CONFIGURATION_REGISTER
- AD7616_OS_MASK
- AD7616_RANGE_CH_ADDR
- AD7616_RANGE_CH_A_ADDR_OFF
- AD7616_RANGE_CH_B_ADDR_OFF
- AD7616_RANGE_CH_MODE
- AD7616_RANGE_CH_MSK
- AD7616_SEQEN_MODE
- AD7746_CAPDAC_DACEN
- AD7746_CAPDAC_DACP
- AD7746_CAPSETUP_CACHOP
- AD7746_CAPSETUP_CAPDIFF
- AD7746_CAPSETUP_CAPEN
- AD7746_CAPSETUP_CIN2
- AD7746_CONF_CAPFS_MASK
- AD7746_CONF_CAPFS_SHIFT
- AD7746_CONF_MODE_CONT_CONV
- AD7746_CONF_MODE_GAIN_CAL
- AD7746_CONF_MODE_IDLE
- AD7746_CONF_MODE_OFFS_CAL
- AD7746_CONF_MODE_PWRDN
- AD7746_CONF_MODE_SINGLE_CONV
- AD7746_CONF_VTFS_MASK
- AD7746_CONF_VTFS_SHIFT
- AD7746_EXCSETUP_CLKCTRL
- AD7746_EXCSETUP_EXCA
- AD7746_EXCSETUP_EXCB
- AD7746_EXCSETUP_EXCLVL
- AD7746_EXCSETUP_EXCON
- AD7746_EXCSETUP_NEXCA
- AD7746_EXCSETUP_NEXCB
- AD7746_REG_CAPDACA
- AD7746_REG_CAPDACB
- AD7746_REG_CAP_DATA_HIGH
- AD7746_REG_CAP_GAINH
- AD7746_REG_CAP_OFFH
- AD7746_REG_CAP_SETUP
- AD7746_REG_CFG
- AD7746_REG_EXC_SETUP
- AD7746_REG_STATUS
- AD7746_REG_VOLT_GAINH
- AD7746_REG_VT_DATA_HIGH
- AD7746_REG_VT_SETUP
- AD7746_STATUS_EXCERR
- AD7746_STATUS_RDY
- AD7746_STATUS_RDYCAP
- AD7746_STATUS_RDYVT
- AD7746_VTSETUP_EXTREF
- AD7746_VTSETUP_VTCHOP
- AD7746_VTSETUP_VTEN
- AD7746_VTSETUP_VTMD_EXT_TEMP
- AD7746_VTSETUP_VTMD_EXT_VIN
- AD7746_VTSETUP_VTMD_INT_TEMP
- AD7746_VTSETUP_VTMD_VDD_MON
- AD7746_VTSETUP_VTSHORT
- AD7766_NUM_SUPPLIES
- AD7766_SUPPLY_AVDD
- AD7766_SUPPLY_DVDD
- AD7766_SUPPLY_VREF
- AD7768_CONTINUOUS
- AD7768_CONV_MODE
- AD7768_CONV_MODE_MSK
- AD7768_DEC_RATE_1024
- AD7768_DEC_RATE_128
- AD7768_DEC_RATE_16
- AD7768_DEC_RATE_256
- AD7768_DEC_RATE_32
- AD7768_DEC_RATE_512
- AD7768_DEC_RATE_64
- AD7768_DEC_RATE_8
- AD7768_DIG_FIL_DEC_MSK
- AD7768_DIG_FIL_DEC_RATE
- AD7768_DIG_FIL_FIL
- AD7768_DIG_FIL_FIL_MSK
- AD7768_ECO_MODE
- AD7768_FAST_MODE
- AD7768_MCLK_DIV_16
- AD7768_MCLK_DIV_2
- AD7768_MCLK_DIV_4
- AD7768_MCLK_DIV_8
- AD7768_MED_MODE
- AD7768_ONE_SHOT
- AD7768_PERIODIC
- AD7768_PWR_MCLK_DIV
- AD7768_PWR_MCLK_DIV_MSK
- AD7768_PWR_PWRMODE
- AD7768_PWR_PWRMODE_MSK
- AD7768_RD_FLAG_MSK
- AD7768_REG_ADC_DATA
- AD7768_REG_ADC_DIAG_ENABLE
- AD7768_REG_ADC_DIAG_STATUS
- AD7768_REG_ANALOG
- AD7768_REG_ANALOG2
- AD7768_REG_CHIP_GRADE
- AD7768_REG_CHIP_TYPE
- AD7768_REG_CONVERSION
- AD7768_REG_DIGITAL_FILTER
- AD7768_REG_DIG_DIAG_ENABLE
- AD7768_REG_DIG_DIAG_STATUS
- AD7768_REG_DUTY_CYCLE_RATIO
- AD7768_REG_GAIN_HI
- AD7768_REG_GAIN_LO
- AD7768_REG_GAIN_MID
- AD7768_REG_GPIO_CONTROL
- AD7768_REG_GPIO_READ
- AD7768_REG_GPIO_WRITE
- AD7768_REG_INTERFACE_FORMAT
- AD7768_REG_MASTER_STATUS
- AD7768_REG_MCLK_COUNTER
- AD7768_REG_OFFSET_HI
- AD7768_REG_OFFSET_LO
- AD7768_REG_OFFSET_MID
- AD7768_REG_POWER_CLOCK
- AD7768_REG_PROD_ID_H
- AD7768_REG_PROD_ID_L
- AD7768_REG_SCRATCH_PAD
- AD7768_REG_SINC3_DEC_RATE_LSB
- AD7768_REG_SINC3_DEC_RATE_MSB
- AD7768_REG_SPI_DIAG_ENABLE
- AD7768_REG_SPI_DIAG_STATUS
- AD7768_REG_SYNC_RESET
- AD7768_REG_VENDOR_H
- AD7768_REG_VENDOR_L
- AD7768_SINGLE
- AD7768_STANDBY
- AD7768_WR_FLAG_MSK
- AD7780_CHANNEL
- AD7780_ERR
- AD7780_FILTER
- AD7780_FILTER_MIDPOINT
- AD7780_GAIN
- AD7780_GAIN_MIDPOINT
- AD7780_ID
- AD7780_ID0
- AD7780_ID1
- AD7780_ID_MASK
- AD7780_PATTERN_GOOD
- AD7780_PATTERN_MASK
- AD7780_RDY
- AD7781_ID
- AD7785_ID
- AD7787
- AD7788
- AD7789
- AD7790
- AD7791
- AD7791_CH_AIN1N_AIN1N
- AD7791_CH_AIN1P_AIN1N
- AD7791_CH_AIN2
- AD7791_CH_AVDD_MONITOR
- AD7791_FILTER_CLK_DIV_1
- AD7791_FILTER_CLK_DIV_2
- AD7791_FILTER_CLK_DIV_4
- AD7791_FILTER_CLK_DIV_8
- AD7791_FILTER_CLK_MASK
- AD7791_FILTER_RATE_100
- AD7791_FILTER_RATE_120
- AD7791_FILTER_RATE_13_3
- AD7791_FILTER_RATE_16_6
- AD7791_FILTER_RATE_16_7
- AD7791_FILTER_RATE_20
- AD7791_FILTER_RATE_33_3
- AD7791_FILTER_RATE_9_5
- AD7791_FILTER_RATE_MASK
- AD7791_FLAG_HAS_BUFFER
- AD7791_FLAG_HAS_BURNOUT
- AD7791_FLAG_HAS_FILTER
- AD7791_FLAG_HAS_UNIPOLAR
- AD7791_MODE_BUFFER
- AD7791_MODE_BURNOUT
- AD7791_MODE_CONTINUOUS
- AD7791_MODE_POWERDOWN
- AD7791_MODE_SEL
- AD7791_MODE_SEL_MASK
- AD7791_MODE_SINGLE
- AD7791_MODE_UNIPOLAR
- AD7791_REG_COMM
- AD7791_REG_DATA
- AD7791_REG_FILTER
- AD7791_REG_MODE
- AD7791_REG_STATUS
- AD7792_ID
- AD7793_BIAS_VOLTAGE_AIN1
- AD7793_BIAS_VOLTAGE_AIN2
- AD7793_BIAS_VOLTAGE_AIN3
- AD7793_BIAS_VOLTAGE_DISABLED
- AD7793_CH_AIN1M_AIN1M
- AD7793_CH_AIN1P_AIN1M
- AD7793_CH_AIN2P_AIN2M
- AD7793_CH_AIN3P_AIN3M
- AD7793_CH_AVDD_MONITOR
- AD7793_CH_TEMP
- AD7793_CLK_EXT
- AD7793_CLK_EXT_DIV2
- AD7793_CLK_INT
- AD7793_CLK_INT_CO
- AD7793_CLK_SRC_EXT
- AD7793_CLK_SRC_EXT_DIV2
- AD7793_CLK_SRC_INT
- AD7793_CLK_SRC_INT_CO
- AD7793_COMM_ADDR
- AD7793_COMM_CREAD
- AD7793_COMM_READ
- AD7793_COMM_WEN
- AD7793_COMM_WRITE
- AD7793_CONF_BOOST
- AD7793_CONF_BO_EN
- AD7793_CONF_BUF
- AD7793_CONF_CHAN
- AD7793_CONF_CHAN_MASK
- AD7793_CONF_GAIN
- AD7793_CONF_REFSEL
- AD7793_CONF_UNIPOLAR
- AD7793_CONF_VBIAS
- AD7793_FLAG_HAS_BUFFER
- AD7793_FLAG_HAS_CLKSEL
- AD7793_FLAG_HAS_GAIN
- AD7793_FLAG_HAS_REFSEL
- AD7793_FLAG_HAS_VBIAS
- AD7793_HAS_EXITATION_CURRENT
- AD7793_ID
- AD7793_ID_MASK
- AD7793_IEXEC1_IEXEC2_IOUT1
- AD7793_IEXEC1_IEXEC2_IOUT2
- AD7793_IEXEC1_IOUT1_IEXEC2_IOUT2
- AD7793_IEXEC1_IOUT2_IEXEC2_IOUT1
- AD7793_IO_IEXC1_IEXC2_IOUT1
- AD7793_IO_IEXC1_IEXC2_IOUT2
- AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2
- AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1
- AD7793_IO_IXCEN_10uA
- AD7793_IO_IXCEN_1mA
- AD7793_IO_IXCEN_210uA
- AD7793_IX_10uA
- AD7793_IX_1mA
- AD7793_IX_210uA
- AD7793_IX_DISABLED
- AD7793_MODE_CAL_INT_FULL
- AD7793_MODE_CAL_INT_ZERO
- AD7793_MODE_CAL_SYS_FULL
- AD7793_MODE_CAL_SYS_ZERO
- AD7793_MODE_CLKSRC
- AD7793_MODE_CONT
- AD7793_MODE_IDLE
- AD7793_MODE_PWRDN
- AD7793_MODE_RATE
- AD7793_MODE_SEL
- AD7793_MODE_SEL_MASK
- AD7793_MODE_SINGLE
- AD7793_REFSEL_INTERNAL
- AD7793_REFSEL_REFIN1
- AD7793_REFSEL_REFIN2
- AD7793_REG_COMM
- AD7793_REG_CONF
- AD7793_REG_DATA
- AD7793_REG_FULLSALE
- AD7793_REG_ID
- AD7793_REG_IO
- AD7793_REG_MODE
- AD7793_REG_OFFSET
- AD7793_REG_STAT
- AD7793_STAT_CH1
- AD7793_STAT_CH2
- AD7793_STAT_CH3
- AD7793_STAT_ERR
- AD7793_STAT_RDY
- AD7794_ID
- AD7795_CH_AIN1M_AIN1M
- AD7795_CH_AIN4P_AIN4M
- AD7795_CH_AIN5P_AIN5M
- AD7795_CH_AIN6P_AIN6M
- AD7795_ID
- AD7796_ID
- AD7797_ID
- AD7798_ID
- AD7799_ID
- AD7816_BOUND_VALUE_BASE
- AD7816_BOUND_VALUE_MAX
- AD7816_BOUND_VALUE_MIN
- AD7816_CS_MASK
- AD7816_CS_MAX
- AD7816_FULL
- AD7816_PD
- AD7816_TEMP_FLOAT_MASK
- AD7816_TEMP_FLOAT_OFFSET
- AD7816_VALUE_OFFSET
- AD7877_ACQ
- AD7877_AVG
- AD7877_CHANADD
- AD7877_DAC_CONF
- AD7877_DFR
- AD7877_EXTW_GPIO_3_CONF
- AD7877_EXTW_GPIO_DATA
- AD7877_FCD
- AD7877_MM_SEQUENCE
- AD7877_MODE_NOC
- AD7877_MODE_SCC
- AD7877_MODE_SEQ0
- AD7877_MODE_SEQ1
- AD7877_NR_SENSE
- AD7877_PM
- AD7877_POL
- AD7877_READADD
- AD7877_READ_CHAN
- AD7877_REF
- AD7877_REG_ALERT
- AD7877_REG_AUX1HIGH
- AD7877_REG_AUX1LOW
- AD7877_REG_BAT1HIGH
- AD7877_REG_BAT1LOW
- AD7877_REG_BAT2HIGH
- AD7877_REG_BAT2LOW
- AD7877_REG_CTRL1
- AD7877_REG_CTRL2
- AD7877_REG_DAC
- AD7877_REG_EXTWRITE
- AD7877_REG_GPIOCTRL1
- AD7877_REG_GPIOCTRL2
- AD7877_REG_GPIODATA
- AD7877_REG_NONE1
- AD7877_REG_NONE2
- AD7877_REG_NONE3
- AD7877_REG_SEQ0
- AD7877_REG_SEQ1
- AD7877_REG_TEMP1HIGH
- AD7877_REG_TEMP1LOW
- AD7877_REG_XPLUS
- AD7877_REG_YPLUS
- AD7877_REG_Z1
- AD7877_REG_Z2
- AD7877_REG_ZEROS
- AD7877_REG_aux1
- AD7877_REG_aux2
- AD7877_REG_aux3
- AD7877_REG_bat1
- AD7877_REG_bat2
- AD7877_REG_temp1
- AD7877_REG_temp2
- AD7877_SEQ_AUX1
- AD7877_SEQ_AUX1_BIT
- AD7877_SEQ_AUX2
- AD7877_SEQ_AUX2_BIT
- AD7877_SEQ_AUX3
- AD7877_SEQ_AUX3_BIT
- AD7877_SEQ_BAT1
- AD7877_SEQ_BAT1_BIT
- AD7877_SEQ_BAT2
- AD7877_SEQ_BAT2_BIT
- AD7877_SEQ_TEMP1
- AD7877_SEQ_TEMP1_BIT
- AD7877_SEQ_TEMP2
- AD7877_SEQ_TEMP2_BIT
- AD7877_SEQ_XPLUS_BIT
- AD7877_SEQ_XPOS
- AD7877_SEQ_YPLUS_BIT
- AD7877_SEQ_YPOS
- AD7877_SEQ_Z1
- AD7877_SEQ_Z1_BIT
- AD7877_SEQ_Z2
- AD7877_SEQ_Z2_BIT
- AD7877_SER
- AD7877_TMR
- AD7877_WRITEADD
- AD7879_ACQ
- AD7879_AUXHIGH_BIT
- AD7879_AUXLOW_BIT
- AD7879_AUXVBATMASK_BIT
- AD7879_AUX_BIT
- AD7879_AVG
- AD7879_CMD_MAGIC
- AD7879_CMD_READ
- AD7879_DEVID
- AD7879_DFR
- AD7879_FCD
- AD7879_GPIOALERTMASK_BIT
- AD7879_GPIODIR
- AD7879_GPIOPOL
- AD7879_GPIO_DATA
- AD7879_GPIO_EN
- AD7879_INTMODE_BIT
- AD7879_MFS
- AD7879_MODE_INT
- AD7879_MODE_NOC
- AD7879_MODE_SCC
- AD7879_MODE_SEQ0
- AD7879_MODE_SEQ1
- AD7879_NR_SENSE
- AD7879_PM
- AD7879_PM_DYN
- AD7879_PM_FULLON
- AD7879_PM_SHUTDOWN
- AD7879_REG_AUX1HIGH
- AD7879_REG_AUX1LOW
- AD7879_REG_AUXVBAT
- AD7879_REG_CTRL1
- AD7879_REG_CTRL2
- AD7879_REG_CTRL3
- AD7879_REG_REVID
- AD7879_REG_TEMP
- AD7879_REG_TEMP1HIGH
- AD7879_REG_TEMP1LOW
- AD7879_REG_XPLUS
- AD7879_REG_YPLUS
- AD7879_REG_Z1
- AD7879_REG_Z2
- AD7879_REG_ZEROS
- AD7879_RESET
- AD7879_SEQ_XPOS
- AD7879_SEQ_YPOS
- AD7879_SEQ_Z1
- AD7879_SEQ_Z2
- AD7879_SER
- AD7879_TEMPHIGH_BIT
- AD7879_TEMPLOW_BIT
- AD7879_TEMPMASK_BIT
- AD7879_TEMP_BIT
- AD7879_TMR
- AD7879_VBAT_BIT
- AD7879_XPLUS_BIT
- AD7879_YPLUS_BIT
- AD7879_Z1_BIT
- AD7879_Z2_BIT
- AD7887_CH0
- AD7887_CH0_CH1
- AD7887_CH1
- AD7887_CH_AIN0
- AD7887_CH_AIN1
- AD7887_DUAL
- AD7887_PM_MODE1
- AD7887_PM_MODE2
- AD7887_PM_MODE3
- AD7887_PM_MODE4
- AD7887_REF_DIS
- AD7904
- AD7914
- AD7923_CHANNEL_0
- AD7923_CHANNEL_1
- AD7923_CHANNEL_2
- AD7923_CHANNEL_3
- AD7923_CHANNEL_WRITE
- AD7923_CODING
- AD7923_MAX_CHAN
- AD7923_PM_MODE_AS
- AD7923_PM_MODE_FS
- AD7923_PM_MODE_OPS
- AD7923_PM_MODE_WRITE
- AD7923_RANGE
- AD7923_SEQUENCE_OFF
- AD7923_SEQUENCE_ON
- AD7923_SEQUENCE_PROTECT
- AD7923_SEQUENCE_WRITE
- AD7923_SHIFT_REGISTER
- AD7923_V_CHAN
- AD7923_WRITE_CR
- AD7924
- AD7940_CHAN
- AD7949_ADC_CHANNEL
- AD7949_CFG_READ_BACK
- AD7949_CFG_REG_SIZE_BITS
- AD7949_MASK_CHANNEL_SEL
- AD7949_MASK_TOTAL
- AD7949_OFFSET_CHANNEL_SEL
- AD7991_BIT_TRIAL_DELAY
- AD7991_FLTR
- AD7991_REF_SEL
- AD7991_SAMPLE_DELAY
- AD7997_8_READ_SEQUENCE
- AD7997_8_READ_SINGLE
- AD7998_ALERT_EN
- AD7998_ALERT_STAT_CLEAR
- AD7998_ALERT_STAT_REG
- AD7998_BUSY_ALERT
- AD7998_BUSY_ALERT_POL
- AD7998_CONF_REG
- AD7998_CONV_RES_REG
- AD7998_CYCLE_TMR_REG
- AD7998_CYC_DIS
- AD7998_CYC_MASK
- AD7998_CYC_TCONF_1024
- AD7998_CYC_TCONF_128
- AD7998_CYC_TCONF_2048
- AD7998_CYC_TCONF_256
- AD7998_CYC_TCONF_32
- AD7998_CYC_TCONF_512
- AD7998_CYC_TCONF_64
- AD7998_DATAHIGH_REG
- AD7998_DATALOW_REG
- AD7998_FLTR
- AD7998_HYST_REG
- AD799X_CHANNEL
- AD799X_CHANNEL_SHIFT
- AD799X_CHANNEL_WITH_EVENTS
- AD8
- AD8366_CHAN
- AD8400_ID
- AD8402_ID
- AD8403_ID
- AD8801_CFG_ADDR_OFFSET
- AD8801_CHANNEL
- AD9
- AD9389B_EDID_DETECT
- AD9389B_H
- AD9389B_MONITOR_DETECT
- AD9389B_TMDS_PLL_GEAR_AUTOMATIC
- AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC
- AD9523_ADDR
- AD9523_CHANNEL_CLOCK_DIST
- AD9523_CLK_DIST_DIV
- AD9523_CLK_DIST_DIV_PHASE
- AD9523_CLK_DIST_DIV_PHASE_REV
- AD9523_CLK_DIST_DIV_REV
- AD9523_CLK_DIST_DRIVER_MODE
- AD9523_CLK_DIST_IGNORE_SYNC_EN
- AD9523_CLK_DIST_INV_DIV_OUTPUT_EN
- AD9523_CLK_DIST_LOW_PWR_MODE_EN
- AD9523_CLK_DIST_PWR_DOWN_EN
- AD9523_CNT
- AD9523_EEPROM
- AD9523_EEPROM_CTRL1
- AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS
- AD9523_EEPROM_CTRL1_SOFT_EEPROM
- AD9523_EEPROM_CTRL2
- AD9523_EEPROM_CTRL2_REG2EEPROM
- AD9523_EEPROM_CUSTOMER_VERSION_ID
- AD9523_EEPROM_DATA_XFER_IN_PROGRESS
- AD9523_EEPROM_DATA_XFER_STATUS
- AD9523_EEPROM_ERROR_READBACK
- AD9523_EEPROM_ERROR_READBACK_FAIL
- AD9523_IO_UPDATE
- AD9523_IO_UPDATE_EN
- AD9523_NUM_CHAN
- AD9523_NUM_CHAN_ALT_CLK_SRC
- AD9523_NUM_CLK_SRC
- AD9523_PART_REGISTER
- AD9523_PLL1_BACKLASH_PW_HIGH
- AD9523_PLL1_BACKLASH_PW_LOW
- AD9523_PLL1_BACKLASH_PW_MAX
- AD9523_PLL1_BACKLASH_PW_MIN
- AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN
- AD9523_PLL1_BYPASS_REFA_DIV
- AD9523_PLL1_BYPASS_REFB_DIV
- AD9523_PLL1_BYPASS_REF_TEST_DIV_EN
- AD9523_PLL1_CHARGE_PUMP_CTRL
- AD9523_PLL1_CHARGE_PUMP_CURRENT_nA
- AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL
- AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN
- AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP
- AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE
- AD9523_PLL1_CHARGE_PUMP_TRISTATE
- AD9523_PLL1_FEEDBACK_DIVIDER
- AD9523_PLL1_INPUT_RECEIVERS_CTRL
- AD9523_PLL1_LOOP_FILTER_CTRL
- AD9523_PLL1_LOOP_FILTER_RZERO
- AD9523_PLL1_MISC_CTRL
- AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN
- AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN
- AD9523_PLL1_OSC_IN_DIFF_EN
- AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN
- AD9523_PLL1_OUTPUT_CHANNEL_CTRL
- AD9523_PLL1_OUTPUT_CTRL
- AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN
- AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2
- AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2
- AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2
- AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0
- AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1
- AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2
- AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3
- AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK
- AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1
- AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16
- AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2
- AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4
- AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8
- AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2
- AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2
- AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2
- AD9523_PLL1_REFA_CMOS_NEG_INP_EN
- AD9523_PLL1_REFA_DIFF_RCV_EN
- AD9523_PLL1_REFA_RCV_EN
- AD9523_PLL1_REFA_REFB_PWR_CTRL_EN
- AD9523_PLL1_REFB_CMOS_NEG_INP_EN
- AD9523_PLL1_REFB_DIFF_RCV_EN
- AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN
- AD9523_PLL1_REFB_RCV_EN
- AD9523_PLL1_REF_A_DIVIDER
- AD9523_PLL1_REF_B_DIVIDER
- AD9523_PLL1_REF_CTRL
- AD9523_PLL1_REF_MODE
- AD9523_PLL1_REF_TEST_DIVIDER
- AD9523_PLL1_REF_TEST_RCV_EN
- AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN
- AD9523_PLL1_ZD_IN_DIFF_EN
- AD9523_PLL1_ZERO_DELAY_MODE_EXT
- AD9523_PLL1_ZERO_DELAY_MODE_INT
- AD9523_PLL2_BACKLASH_CTRL_EN
- AD9523_PLL2_BACKLASH_PW_HIGH
- AD9523_PLL2_BACKLASH_PW_LOW
- AD9523_PLL2_BACKLASH_PW_MAX
- AD9523_PLL2_BACKLASH_PW_MIN
- AD9523_PLL2_CHARGE_PUMP
- AD9523_PLL2_CHARGE_PUMP_CURRENT_nA
- AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL
- AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN
- AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP
- AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE
- AD9523_PLL2_CTRL
- AD9523_PLL2_FB_NDIV
- AD9523_PLL2_FB_NDIV_A_CNT
- AD9523_PLL2_FB_NDIV_B_CNT
- AD9523_PLL2_FEEDBACK_DIVIDER_AB
- AD9523_PLL2_FORCE_REFERENCE_VALID
- AD9523_PLL2_FORCE_RELEASE_SYNC
- AD9523_PLL2_FORCE_VCO_MIDSCALE
- AD9523_PLL2_FREQ_DOUBLER_EN
- AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN
- AD9523_PLL2_LOOP_FILTER_CPOLE1
- AD9523_PLL2_LOOP_FILTER_CTRL
- AD9523_PLL2_LOOP_FILTER_RPOLE2
- AD9523_PLL2_LOOP_FILTER_RZERO
- AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN
- AD9523_PLL2_R2_DIVIDER
- AD9523_PLL2_R2_DIVIDER_VAL
- AD9523_PLL2_VCO_CALIBRATE
- AD9523_PLL2_VCO_CTRL
- AD9523_PLL2_VCO_DIVIDER
- AD9523_PLL2_VCO_DIV_M1
- AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN
- AD9523_PLL2_VCO_DIV_M2
- AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN
- AD9523_POWER_DOWN_CTRL
- AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN
- AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN
- AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN
- AD9523_R1B
- AD9523_R2B
- AD9523_R3B
- AD9523_READ
- AD9523_READBACK_0
- AD9523_READBACK_0_STAT_PLL1_LD
- AD9523_READBACK_0_STAT_PLL2_FB_CLK
- AD9523_READBACK_0_STAT_PLL2_LD
- AD9523_READBACK_0_STAT_PLL2_REF_CLK
- AD9523_READBACK_0_STAT_REFA
- AD9523_READBACK_0_STAT_REFB
- AD9523_READBACK_0_STAT_REF_TEST
- AD9523_READBACK_0_STAT_VCXO
- AD9523_READBACK_1
- AD9523_READBACK_1_AUTOMODE_SEL_REFB
- AD9523_READBACK_1_HOLDOVER_ACTIVE
- AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS
- AD9523_READBACK_CTRL
- AD9523_READBACK_CTRL_READ_BUFFERED
- AD9523_SERIAL_PORT_CONFIG
- AD9523_SER_CONF_SDO_ACTIVE
- AD9523_SER_CONF_SOFT_RESET
- AD9523_STATUS_MONITOR_01_PLL12_LOCKED
- AD9523_STATUS_SIGNALS
- AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL
- AD9523_STAT_PLL1_LD
- AD9523_STAT_PLL2_FB_CLK
- AD9523_STAT_PLL2_LD
- AD9523_STAT_PLL2_REF_CLK
- AD9523_STAT_REFA
- AD9523_STAT_REFB
- AD9523_STAT_REF_TEST
- AD9523_STAT_VCXO
- AD9523_SYNC
- AD9523_TRANSF_LEN
- AD9523_VCO1
- AD9523_VCO2
- AD9523_VCXO
- AD9523_VERSION_REGISTER
- AD9523_WRITE
- AD9832_CLR
- AD9832_CMD_FPSELECT
- AD9832_CMD_FRE16BITSW
- AD9832_CMD_FRE8BITSW
- AD9832_CMD_PHA16BITSW
- AD9832_CMD_PHA8BITSW
- AD9832_CMD_SLEEPRESCLR
- AD9832_CMD_SYNCSELSRC
- AD9832_FREQ
- AD9832_FREQ0HL
- AD9832_FREQ0HM
- AD9832_FREQ0LL
- AD9832_FREQ0LM
- AD9832_FREQ1HL
- AD9832_FREQ1HM
- AD9832_FREQ1LL
- AD9832_FREQ1LM
- AD9832_FREQ_BITS
- AD9832_FREQ_SYM
- AD9832_OUTPUT_EN
- AD9832_PHASE
- AD9832_PHASE0H
- AD9832_PHASE0L
- AD9832_PHASE1H
- AD9832_PHASE1L
- AD9832_PHASE2H
- AD9832_PHASE2L
- AD9832_PHASE3H
- AD9832_PHASE3L
- AD9832_PHASE_BITS
- AD9832_PHASE_SYM
- AD9832_PINCTRL_EN
- AD9832_RESET
- AD9832_SELSRC
- AD9832_SLEEP
- AD9832_SYNC
- AD9834_B28
- AD9834_DIV2
- AD9834_FREQ_BITS
- AD9834_FSEL
- AD9834_HLB
- AD9834_MODE
- AD9834_OPBITEN
- AD9834_PHASE_BITS
- AD9834_PIN_SW
- AD9834_PSEL
- AD9834_REG_CMD
- AD9834_REG_FREQ0
- AD9834_REG_FREQ1
- AD9834_REG_PHASE0
- AD9834_REG_PHASE1
- AD9834_RESET
- AD9834_SIGN_PIB
- AD9834_SLEEP1
- AD9834_SLEEP12
- ADAC1ODC
- ADAC1ODC_ADAC_RAMPCLT_MASK
- ADAC1ODC_ADAC_RAMPCLT_NORMAL
- ADAC1ODC_ADAC_RAMPCLT_REDUCE
- ADAC1ODC_HP_DIS_RES_MASK
- ADAC1ODC_HP_DIS_RES_OFF
- ADAC1ODC_HP_DIS_RES_ON
- ADACSEQ1
- ADACSEQ1_MMUTE
- ADACSEQ2
- ADACSEQ2_ADACIN_FIX
- ADAP2RAIDDEV
- ADAPTER_ADDRESS
- ADAPTER_CGA
- ADAPTER_CNF_OFFSET
- ADAPTER_CNTL_EN
- ADAPTER_ECC_EN
- ADAPTER_EGA
- ADAPTER_EOI_TX_ON
- ADAPTER_ID
- ADAPTER_ID_W
- ADAPTER_ID_W__SUBSYSTEM_ID_MASK
- ADAPTER_ID_W__SUBSYSTEM_ID__MASK
- ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
- ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
- ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK
- ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
- ADAPTER_ID__SUBSYSTEM_ID_MASK
- ADAPTER_ID__SUBSYSTEM_ID__MASK
- ADAPTER_ID__SUBSYSTEM_ID__SHIFT
- ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
- ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK
- ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
- ADAPTER_INIT_STRUCT_REVISION
- ADAPTER_INIT_STRUCT_REVISION_4
- ADAPTER_INIT_STRUCT_REVISION_6
- ADAPTER_INIT_STRUCT_REVISION_7
- ADAPTER_INIT_STRUCT_REVISION_8
- ADAPTER_INIT_TOV
- ADAPTER_LED_ON
- ADAPTER_MAD
- ADAPTER_NOT_SAME
- ADAPTER_PROBLEM
- ADAPTER_RESET_TOV
- ADAPTER_ROM
- ADAPTER_SCSI_ID
- ADAPTER_SET_WRB_TYPE
- ADAPTER_STATE_FAILED
- ADAPTER_STATE_FAULTED
- ADAPTER_STATE_GOING_DOWN
- ADAPTER_STATE_HOLD
- ADAPTER_STATE_INITIALIZING
- ADAPTER_STATE_INIT_FAILED
- ADAPTER_STATE_LINK_DOWN
- ADAPTER_STATE_OPERATIONAL
- ADAPTER_STATE_READY
- ADAPTER_STATE_RESET
- ADAPTER_STATE_UP
- ADAPTER_STATUS_MC_DRAM_READY
- ADAPTER_STATUS_MC_QUEUES_READY
- ADAPTER_STATUS_M_PLL_LOCK
- ADAPTER_STATUS_PFC_READY
- ADAPTER_STATUS_PIC_QUIESCENT
- ADAPTER_STATUS_P_PLL_LOCK
- ADAPTER_STATUS_RC_PRC_QUIESCENT
- ADAPTER_STATUS_RDMA_READY
- ADAPTER_STATUS_RIC_RUNNING
- ADAPTER_STATUS_RMAC_LOCAL_FAULT
- ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
- ADAPTER_STATUS_RMAC_PCC_IDLE
- ADAPTER_STATUS_RMAC_REMOTE_FAULT
- ADAPTER_STATUS_TDMA_READY
- ADAPTER_STATUS_TMAC_BUF_EMPTY
- ADAPTER_TID
- ADAPTER_TYPE
- ADAPTER_UDPI
- ADAPTER_V1
- ADAPTER_V2
- ADAPTER_VGA
- ADAPTER_WAIT_INT
- ADAPTIVE_KEY_MODE
- ADAPTIVITY_VERSION
- ADAPT_FIELD
- ADAPT_SCALE_BASE
- ADAPT_SCALE_NPAGES
- ADAPT_SCALE_SHIFT
- ADAPT_SUCCESS
- ADAP_EXT_FLAG
- ADAP_HIGH_CMD_ENTRIES
- ADAP_HIGH_RESP_ENTRIES
- ADAP_INIT
- ADAP_NORM_CMD_ENTRIES
- ADAP_NORM_RESP_ENTRIES
- ADAP_READ_AHEAD
- ADAP_SLEEP
- ADAP_STREAMING
- ADATA_IN
- ADATA_OUT
- ADAT_IN
- ADAT_OUT
- ADAT_USER_DATA_MASK
- ADAT_USER_DATA_NO_DATA
- ADAU1361
- ADAU1373_3D_CTRL1
- ADAU1373_3D_CTRL2
- ADAU1373_ADC_CTRL
- ADAU1373_ADC_CTRL_PEAK_DETECT
- ADAU1373_ADC_CTRL_RESET
- ADAU1373_ADC_CTRL_RESET_FORCE
- ADAU1373_ADC_DAC_STATUS
- ADAU1373_ADC_GAIN
- ADAU1373_ADC_RECL_VOL
- ADAU1373_ADC_RECR_VOL
- ADAU1373_AINL_CTRL
- ADAU1373_AINR_CTRL
- ADAU1373_BASS1
- ADAU1373_BASS2
- ADAU1373_BCLKDIV
- ADAU1373_BCLKDIV_128
- ADAU1373_BCLKDIV_256
- ADAU1373_BCLKDIV_32
- ADAU1373_BCLKDIV_64
- ADAU1373_BCLKDIV_BCLK_MASK
- ADAU1373_BCLKDIV_SOURCE
- ADAU1373_BCLKDIV_SR_MASK
- ADAU1373_CLK_SRC_DIV
- ADAU1373_CLK_SRC_PLL1
- ADAU1373_CLK_SRC_PLL2
- ADAU1373_DAC1_PBL_VOL
- ADAU1373_DAC1_PBR_VOL
- ADAU1373_DAC2_PBL_VOL
- ADAU1373_DAC2_PBR_VOL
- ADAU1373_DAI
- ADAU1373_DAI_FORMAT_DSP
- ADAU1373_DAI_FORMAT_I2S
- ADAU1373_DAI_FORMAT_LEFT_J
- ADAU1373_DAI_FORMAT_RIGHT_J
- ADAU1373_DAI_INVERT_BCLK
- ADAU1373_DAI_INVERT_LRCLK
- ADAU1373_DAI_MASTER
- ADAU1373_DAI_PBL_VOL
- ADAU1373_DAI_PBR_VOL
- ADAU1373_DAI_RECL_VOL
- ADAU1373_DAI_RECR_VOL
- ADAU1373_DAI_WLEN_16
- ADAU1373_DAI_WLEN_20
- ADAU1373_DAI_WLEN_24
- ADAU1373_DAI_WLEN_32
- ADAU1373_DAI_WLEN_MASK
- ADAU1373_DEEMP_CTRL
- ADAU1373_DIGEN
- ADAU1373_DIGMICCTRL
- ADAU1373_DIN_MIX_CTRL
- ADAU1373_DMIC_RECL_VOL
- ADAU1373_DMIC_RECR_VOL
- ADAU1373_DOUT_MIX_CTRL
- ADAU1373_DPLL_CTRL
- ADAU1373_DRC
- ADAU1373_DRC_SIZE
- ADAU1373_EP_CTRL
- ADAU1373_EP_CTRL_MICBIAS1_OFFSET
- ADAU1373_EP_CTRL_MICBIAS2_OFFSET
- ADAU1373_EP_MIX
- ADAU1373_FDSP_SEL1
- ADAU1373_FDSP_SEL2
- ADAU1373_FDSP_SEL3
- ADAU1373_FDSP_SEL4
- ADAU1373_FORMATS
- ADAU1373_HEADDECT
- ADAU1373_HPF_CTRL
- ADAU1373_HP_CTRL
- ADAU1373_HP_CTRL2
- ADAU1373_INPUT_MODE
- ADAU1373_LADC_MIXER
- ADAU1373_LHP_MIX
- ADAU1373_LHP_OUT
- ADAU1373_LLINE1_MIX
- ADAU1373_LLINE2_MIX
- ADAU1373_LLINE_OUT
- ADAU1373_LSPK_MIX
- ADAU1373_LSPK_OUT
- ADAU1373_LS_CTRL
- ADAU1373_MICBIAS_1_8V
- ADAU1373_MICBIAS_2_2V
- ADAU1373_MICBIAS_2_6V
- ADAU1373_MICBIAS_2_9V
- ADAU1373_MICBIAS_CTRL1
- ADAU1373_MICBIAS_CTRL2
- ADAU1373_OUTPUT_CTRL
- ADAU1373_OUTPUT_CTRL_LDIFF
- ADAU1373_OUTPUT_CTRL_LNFBEN
- ADAU1373_PLL1
- ADAU1373_PLL2
- ADAU1373_PLL_CTRL1
- ADAU1373_PLL_CTRL2
- ADAU1373_PLL_CTRL3
- ADAU1373_PLL_CTRL4
- ADAU1373_PLL_CTRL5
- ADAU1373_PLL_CTRL6
- ADAU1373_PLL_CTRL6_DPLL_BYPASS
- ADAU1373_PLL_CTRL6_PLL_EN
- ADAU1373_PLL_SRC_BCLK1
- ADAU1373_PLL_SRC_BCLK2
- ADAU1373_PLL_SRC_BCLK3
- ADAU1373_PLL_SRC_GPIO1
- ADAU1373_PLL_SRC_GPIO2
- ADAU1373_PLL_SRC_GPIO3
- ADAU1373_PLL_SRC_GPIO4
- ADAU1373_PLL_SRC_LRCLK1
- ADAU1373_PLL_SRC_LRCLK2
- ADAU1373_PLL_SRC_LRCLK3
- ADAU1373_PLL_SRC_MCLK1
- ADAU1373_PLL_SRC_MCLK2
- ADAU1373_PWDN_CTRL1
- ADAU1373_PWDN_CTRL2
- ADAU1373_PWDN_CTRL3
- ADAU1373_PWDN_CTRL3_PWR_EN
- ADAU1373_RADC_MIXER
- ADAU1373_RHP_MIX
- ADAU1373_RHP_OUT
- ADAU1373_RLINE1_MIX
- ADAU1373_RLINE2_MIX
- ADAU1373_RLINE_OUT
- ADAU1373_RSPK_MIX
- ADAU1373_RSPK_OUT
- ADAU1373_SOFT_RESET
- ADAU1373_SRC_DAI_CTRL
- ADAU1373_SRC_RATIOA
- ADAU1373_SRC_RATIOB
- ADAU1373_VOL_GAIN1
- ADAU1373_VOL_GAIN2
- ADAU1373_VOL_GAIN3
- ADAU1381
- ADAU1381_FIRMWARE
- ADAU1701_AUXNPOW
- ADAU1701_AUXNPOW_VBPD
- ADAU1701_AUXNPOW_VRPD
- ADAU1701_CLK_SRC_MCLK
- ADAU1701_CLK_SRC_OSC
- ADAU1701_DACSET
- ADAU1701_DACSET_DACINIT
- ADAU1701_DSPCTRL
- ADAU1701_DSPCTRL_ADM
- ADAU1701_DSPCTRL_CR
- ADAU1701_DSPCTRL_DAM
- ADAU1701_DSPCTRL_IST
- ADAU1701_DSPCTRL_SR_192
- ADAU1701_DSPCTRL_SR_48
- ADAU1701_DSPCTRL_SR_96
- ADAU1701_DSPCTRL_SR_MASK
- ADAU1701_FIRMWARE
- ADAU1701_FORMATS
- ADAU1701_MAX_REGISTER
- ADAU1701_OSCIPOW
- ADAU1701_OSCIPOW_OPD
- ADAU1701_PINCONF_0
- ADAU1701_PINCONF_1
- ADAU1701_RATES
- ADAU1701_SAFELOAD_ADDR
- ADAU1701_SAFELOAD_DATA
- ADAU1701_SERICTL
- ADAU1701_SERICTL_I2S
- ADAU1701_SERICTL_INV_BCLK
- ADAU1701_SERICTL_INV_LRCLK
- ADAU1701_SERICTL_LEFTJ
- ADAU1701_SERICTL_MODE_MASK
- ADAU1701_SERICTL_RIGHTJ_16
- ADAU1701_SERICTL_RIGHTJ_18
- ADAU1701_SERICTL_RIGHTJ_20
- ADAU1701_SERICTL_RIGHTJ_24
- ADAU1701_SERICTL_TDM
- ADAU1701_SEROCTL
- ADAU1701_SEROCTL_INV_BCLK
- ADAU1701_SEROCTL_INV_LRCLK
- ADAU1701_SEROCTL_MASTER
- ADAU1701_SEROCTL_MSB_DEALY0
- ADAU1701_SEROCTL_MSB_DEALY1
- ADAU1701_SEROCTL_MSB_DEALY12
- ADAU1701_SEROCTL_MSB_DEALY16
- ADAU1701_SEROCTL_MSB_DEALY8
- ADAU1701_SEROCTL_MSB_DEALY_MASK
- ADAU1701_SEROCTL_OBF16
- ADAU1701_SEROCTL_OBF2
- ADAU1701_SEROCTL_OBF4
- ADAU1701_SEROCTL_OBF8
- ADAU1701_SEROCTL_OBF_MASK
- ADAU1701_SEROCTL_OLF1024
- ADAU1701_SEROCTL_OLF256
- ADAU1701_SEROCTL_OLF512
- ADAU1701_SEROCTL_OLF_MASK
- ADAU1701_SEROCTL_WORD_LEN_16
- ADAU1701_SEROCTL_WORD_LEN_20
- ADAU1701_SEROCTL_WORD_LEN_24
- ADAU1701_SEROCTL_WORD_LEN_MASK
- ADAU1707_CLKDIV_UNSET
- ADAU1761
- ADAU1761_CLK_ENABLE0
- ADAU1761_CLK_ENABLE1
- ADAU1761_DEJITTER
- ADAU1761_DIFF_INPUT_VOL_LDEN
- ADAU1761_DIGMIC_JACKDETECT
- ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW
- ADAU1761_DIGMIC_JACKDETECT_DIGMIC
- ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC
- ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT
- ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE
- ADAU1761_FIRMWARE
- ADAU1761_FORMATS
- ADAU1761_JACKDETECT_DEBOUNCE_10MS
- ADAU1761_JACKDETECT_DEBOUNCE_20MS
- ADAU1761_JACKDETECT_DEBOUNCE_40MS
- ADAU1761_JACKDETECT_DEBOUNCE_5MS
- ADAU1761_JACK_DETECT_PIN
- ADAU1761_LEFT_DIFF_INPUT_VOL
- ADAU1761_OUTPUT_MODE_HEADPHONE
- ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS
- ADAU1761_OUTPUT_MODE_LINE
- ADAU1761_PLAY_HP_LEFT_VOL
- ADAU1761_PLAY_HP_RIGHT_VOL
- ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP
- ADAU1761_PLAY_LINE_LEFT_VOL
- ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP
- ADAU1761_PLAY_LINE_RIGHT_VOL
- ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP
- ADAU1761_PLAY_LR_MIXER_LEFT
- ADAU1761_PLAY_LR_MIXER_RIGHT
- ADAU1761_PLAY_MIXER_LEFT0
- ADAU1761_PLAY_MIXER_LEFT1
- ADAU1761_PLAY_MIXER_MONO
- ADAU1761_PLAY_MIXER_RIGHT0
- ADAU1761_PLAY_MIXER_RIGHT1
- ADAU1761_PLAY_MONO_OUTPUT_VOL
- ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP
- ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE
- ADAU1761_POP_CLICK_SUPPRESS
- ADAU1761_REC_MIXER_LEFT0
- ADAU1761_REC_MIXER_LEFT1
- ADAU1761_REC_MIXER_RIGHT0
- ADAU1761_REC_MIXER_RIGHT1
- ADAU1761_RIGHT_DIFF_INPUT_VOL
- ADAU1781
- ADAU1781_BEEP_ZC
- ADAU1781_DEJITTER
- ADAU1781_DIG_PWDN0
- ADAU1781_DIG_PWDN1
- ADAU1781_DMIC_BEEP_CTRL
- ADAU1781_FIRMWARE
- ADAU1781_FORMATS
- ADAU1781_INPUT_DIFFERNTIAL
- ADAU1781_LEFT_LINEOUT
- ADAU1781_LEFT_PGA
- ADAU1781_LEFT_PLAYBACK_MIXER
- ADAU1781_MONO_PLAYBACK_MIXER
- ADAU1781_RIGHT_LINEOUT
- ADAU1781_RIGHT_PGA
- ADAU1781_RIGHT_PLAYBACK_MIXER
- ADAU1781_SPEAKER
- ADAU17X1_ADC_CONTROL
- ADAU17X1_CLK_SRC_MCLK
- ADAU17X1_CLK_SRC_PLL
- ADAU17X1_CLK_SRC_PLL_AUTO
- ADAU17X1_CLOCK_CONTROL
- ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL
- ADAU17X1_CLOCK_CONTROL_INFREQ_MASK
- ADAU17X1_CLOCK_CONTROL_SYSCLK_EN
- ADAU17X1_CONTROL_PORT_PAD0
- ADAU17X1_CONTROL_PORT_PAD1
- ADAU17X1_CONVERTER0
- ADAU17X1_CONVERTER0_ADOSR
- ADAU17X1_CONVERTER0_CONVSR_MASK
- ADAU17X1_CONVERTER0_DAC_PAIR
- ADAU17X1_CONVERTER0_DAC_PAIR_MASK
- ADAU17X1_CONVERTER1
- ADAU17X1_CONVERTER1_ADC_PAIR
- ADAU17X1_CONVERTER1_ADC_PAIR_MASK
- ADAU17X1_DAC_CONTROL0
- ADAU17X1_DAC_CONTROL1
- ADAU17X1_DAC_CONTROL2
- ADAU17X1_DSP_ENABLE
- ADAU17X1_DSP_RUN
- ADAU17X1_DSP_SAMPLING_RATE
- ADAU17X1_LEFT_INPUT_DIGITAL_VOL
- ADAU17X1_MICBIAS
- ADAU17X1_MICBIAS_0_65_AVDD
- ADAU17X1_MICBIAS_0_90_AVDD
- ADAU17X1_PLAY_POWER_MGMT
- ADAU17X1_PLL
- ADAU17X1_PLL_CONTROL
- ADAU17X1_PLL_SRC_MCLK
- ADAU17X1_REC_POWER_MGMT
- ADAU17X1_RIGHT_INPUT_DIGITAL_VOL
- ADAU17X1_SAFELOAD_DATA
- ADAU17X1_SAFELOAD_DATA_SIZE
- ADAU17X1_SAFELOAD_TARGET_ADDRESS
- ADAU17X1_SAFELOAD_TRIGGER
- ADAU17X1_SERIAL_INPUT_ROUTE
- ADAU17X1_SERIAL_OUTPUT_ROUTE
- ADAU17X1_SERIAL_PORT0
- ADAU17X1_SERIAL_PORT0_BCLK_POL
- ADAU17X1_SERIAL_PORT0_LRCLK_POL
- ADAU17X1_SERIAL_PORT0_MASTER
- ADAU17X1_SERIAL_PORT0_PULSE_MODE
- ADAU17X1_SERIAL_PORT0_STEREO
- ADAU17X1_SERIAL_PORT0_TDM4
- ADAU17X1_SERIAL_PORT0_TDM8
- ADAU17X1_SERIAL_PORT0_TDM_MASK
- ADAU17X1_SERIAL_PORT1
- ADAU17X1_SERIAL_PORT1_BCLK128
- ADAU17X1_SERIAL_PORT1_BCLK256
- ADAU17X1_SERIAL_PORT1_BCLK32
- ADAU17X1_SERIAL_PORT1_BCLK48
- ADAU17X1_SERIAL_PORT1_BCLK64
- ADAU17X1_SERIAL_PORT1_BCLK_MASK
- ADAU17X1_SERIAL_PORT1_DELAY0
- ADAU17X1_SERIAL_PORT1_DELAY1
- ADAU17X1_SERIAL_PORT1_DELAY16
- ADAU17X1_SERIAL_PORT1_DELAY8
- ADAU17X1_SERIAL_PORT1_DELAY_MASK
- ADAU17X1_SERIAL_PORT_PAD
- ADAU17X1_SERIAL_SAMPLING_RATE
- ADAU17X1_WORD_SIZE
- ADAU1977
- ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE
- ADAU1977_BLOCK_POWER_SAI_LDO_EN
- ADAU1977_BLOCK_POWER_SAI_LR_POL
- ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET
- ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET
- ADAU1977_DC_SUB_SWITCH
- ADAU1977_HPF_SWITCH
- ADAU1977_MICBIAS_5V0
- ADAU1977_MICBIAS_5V5
- ADAU1977_MICBIAS_6V0
- ADAU1977_MICBIAS_6V5
- ADAU1977_MICBIAS_7V0
- ADAU1977_MICBIAS_7V5
- ADAU1977_MICBIAS_8V0
- ADAU1977_MICBIAS_8V5
- ADAU1977_MICBIAS_9V0
- ADAU1977_MICBIAS_MB_VOLTS_MASK
- ADAU1977_MICBIAS_MB_VOLTS_OFFSET
- ADAU1977_MISC_CONTROL_DC_CAL
- ADAU1977_MISC_CONTROL_MMUTE
- ADAU1977_MISC_CONTROL_SUM_MODE_1CH
- ADAU1977_MISC_CONTROL_SUM_MODE_2CH
- ADAU1977_MISC_CONTROL_SUM_MODE_4CH
- ADAU1977_MISC_CONTROL_SUM_MODE_MASK
- ADAU1977_PLL_CLK_S
- ADAU1977_PLL_MCS_MASK
- ADAU1977_POWER_PWUP
- ADAU1977_POWER_RESET
- ADAU1977_RATE_CONSTRAINT_MASK_32000
- ADAU1977_RATE_CONSTRAINT_MASK_44100
- ADAU1977_RATE_CONSTRAINT_MASK_48000
- ADAU1977_RATE_CONSTRAINT_MASK_LRCLK
- ADAU1977_REG_ADC_CLIP
- ADAU1977_REG_ADJUST1
- ADAU1977_REG_ADJUST2
- ADAU1977_REG_BLOCK_POWER_SAI
- ADAU1977_REG_BOOST
- ADAU1977_REG_CMAP12
- ADAU1977_REG_CMAP34
- ADAU1977_REG_DC_HPF_CAL
- ADAU1977_REG_DIAG_CONTROL
- ADAU1977_REG_DIAG_IRQ1
- ADAU1977_REG_DIAG_IRQ2
- ADAU1977_REG_MICBIAS
- ADAU1977_REG_MISC_CONTROL
- ADAU1977_REG_PLL
- ADAU1977_REG_POST_ADC_GAIN
- ADAU1977_REG_POWER
- ADAU1977_REG_SAI_CTRL0
- ADAU1977_REG_SAI_CTRL1
- ADAU1977_REG_SAI_OVERTEMP
- ADAU1977_REG_STATUS
- ADAU1977_SAI_CTRL0_FMT_I2S
- ADAU1977_SAI_CTRL0_FMT_LJ
- ADAU1977_SAI_CTRL0_FMT_MASK
- ADAU1977_SAI_CTRL0_FMT_RJ_16BIT
- ADAU1977_SAI_CTRL0_FMT_RJ_24BIT
- ADAU1977_SAI_CTRL0_FS_128000_192000
- ADAU1977_SAI_CTRL0_FS_16000_24000
- ADAU1977_SAI_CTRL0_FS_32000_48000
- ADAU1977_SAI_CTRL0_FS_64000_96000
- ADAU1977_SAI_CTRL0_FS_8000_12000
- ADAU1977_SAI_CTRL0_FS_MASK
- ADAU1977_SAI_CTRL0_SAI_I2S
- ADAU1977_SAI_CTRL0_SAI_MASK
- ADAU1977_SAI_CTRL0_SAI_TDM_16
- ADAU1977_SAI_CTRL0_SAI_TDM_2
- ADAU1977_SAI_CTRL0_SAI_TDM_4
- ADAU1977_SAI_CTRL0_SAI_TDM_8
- ADAU1977_SAI_CTRL1_BCLKRATE_16
- ADAU1977_SAI_CTRL1_BCLKRATE_32
- ADAU1977_SAI_CTRL1_BCLKRATE_MASK
- ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT
- ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT
- ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK
- ADAU1977_SAI_CTRL1_LRCLK_PULSE
- ADAU1977_SAI_CTRL1_MASTER
- ADAU1977_SAI_CTRL1_MSB
- ADAU1977_SAI_CTRL1_SLOT_WIDTH_16
- ADAU1977_SAI_CTRL1_SLOT_WIDTH_24
- ADAU1977_SAI_CTRL1_SLOT_WIDTH_32
- ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK
- ADAU1977_SAI_OVERTEMP_DRV_C
- ADAU1977_SAI_OVERTEMP_DRV_HIZ
- ADAU1977_SYSCLK
- ADAU1977_SYSCLK_SRC_LRCLK
- ADAU1977_SYSCLK_SRC_MCLK
- ADAU1977_VOLUME
- ADAU1978
- ADAU1979
- ADAV80X_ADC_CTRL1
- ADAV80X_ADC_CTRL1_MODULATOR_128FS
- ADAV80X_ADC_CTRL1_MODULATOR_64FS
- ADAV80X_ADC_CTRL1_MODULATOR_MASK
- ADAV80X_ADC_CTRL2
- ADAV80X_ADC_L_VOL
- ADAV80X_ADC_R_VOL
- ADAV80X_AUX_IN_CTRL
- ADAV80X_AUX_OUT_CTRL
- ADAV80X_CAPTRUE_WORD_LEN18
- ADAV80X_CAPTURE_MODE_I2S
- ADAV80X_CAPTURE_MODE_LEFT_J
- ADAV80X_CAPTURE_MODE_MASK
- ADAV80X_CAPTURE_MODE_MASTER
- ADAV80X_CAPTURE_MODE_RIGHT_J
- ADAV80X_CAPTURE_RATES
- ADAV80X_CAPTURE_WORD_LEN16
- ADAV80X_CAPTURE_WORD_LEN20
- ADAV80X_CAPTURE_WORD_LEN24
- ADAV80X_CAPTURE_WORD_LEN_MASK
- ADAV80X_CLK_MCLKI
- ADAV80X_CLK_PLL1
- ADAV80X_CLK_PLL2
- ADAV80X_CLK_SYSCLK1
- ADAV80X_CLK_SYSCLK2
- ADAV80X_CLK_SYSCLK3
- ADAV80X_CLK_XIN
- ADAV80X_CLK_XTAL
- ADAV80X_DAC_CTRL1
- ADAV80X_DAC_CTRL1_PD
- ADAV80X_DAC_CTRL2
- ADAV80X_DAC_CTRL2_DEEMPH_32
- ADAV80X_DAC_CTRL2_DEEMPH_44
- ADAV80X_DAC_CTRL2_DEEMPH_48
- ADAV80X_DAC_CTRL2_DEEMPH_MASK
- ADAV80X_DAC_CTRL2_DEEMPH_NONE
- ADAV80X_DAC_CTRL2_DIV1
- ADAV80X_DAC_CTRL2_DIV1_5
- ADAV80X_DAC_CTRL2_DIV2
- ADAV80X_DAC_CTRL2_DIV3
- ADAV80X_DAC_CTRL2_DIV_MASK
- ADAV80X_DAC_CTRL2_INTERPOL_128FS
- ADAV80X_DAC_CTRL2_INTERPOL_256FS
- ADAV80X_DAC_CTRL2_INTERPOL_64FS
- ADAV80X_DAC_CTRL2_INTERPOL_MASK
- ADAV80X_DAC_CTRL3
- ADAV80X_DAC_L_VOL
- ADAV80X_DAC_R_VOL
- ADAV80X_DPATH_CTRL1
- ADAV80X_DPATH_CTRL2
- ADAV80X_FORMATS
- ADAV80X_ICLK_CTRL1
- ADAV80X_ICLK_CTRL1_ADC_SRC
- ADAV80X_ICLK_CTRL1_DAC_SRC
- ADAV80X_ICLK_CTRL1_ICLK2_SRC
- ADAV80X_ICLK_CTRL2
- ADAV80X_ICLK_CTRL2_ICLK1_SRC
- ADAV80X_MUX
- ADAV80X_MUX_ENUM_DECL
- ADAV80X_PGA_L_VOL
- ADAV80X_PGA_R_VOL
- ADAV80X_PLAYBACK_CTRL
- ADAV80X_PLAYBACK_MODE_I2S
- ADAV80X_PLAYBACK_MODE_LEFT_J
- ADAV80X_PLAYBACK_MODE_MASK
- ADAV80X_PLAYBACK_MODE_MASTER
- ADAV80X_PLAYBACK_MODE_RIGHT_J_16
- ADAV80X_PLAYBACK_MODE_RIGHT_J_18
- ADAV80X_PLAYBACK_MODE_RIGHT_J_20
- ADAV80X_PLAYBACK_MODE_RIGHT_J_24
- ADAV80X_PLAYBACK_RATES
- ADAV80X_PLL1
- ADAV80X_PLL2
- ADAV80X_PLL_CLK_SRC
- ADAV80X_PLL_CLK_SRC_PLL_MASK
- ADAV80X_PLL_CLK_SRC_PLL_MCLKI
- ADAV80X_PLL_CLK_SRC_PLL_XIN
- ADAV80X_PLL_CTRL1
- ADAV80X_PLL_CTRL1_PLLDIV
- ADAV80X_PLL_CTRL1_PLLPD
- ADAV80X_PLL_CTRL1_XTLPD
- ADAV80X_PLL_CTRL2
- ADAV80X_PLL_CTRL2_DOUB
- ADAV80X_PLL_CTRL2_FIELD
- ADAV80X_PLL_CTRL2_FS_32
- ADAV80X_PLL_CTRL2_FS_44
- ADAV80X_PLL_CTRL2_FS_48
- ADAV80X_PLL_CTRL2_PLL_MASK
- ADAV80X_PLL_CTRL2_SEL
- ADAV80X_PLL_OUTE
- ADAV80X_PLL_OUTE_SYSCLKPD
- ADAV80X_PLL_SRC_MCLKI
- ADAV80X_PLL_SRC_XIN
- ADAV80X_PLL_SRC_XTAL
- ADAV80X_REC_CTRL
- ADBMOUSE_EXTENDED
- ADBMOUSE_MACALLY2
- ADBMOUSE_MICROSPEED
- ADBMOUSE_MS_A3
- ADBMOUSE_STANDARD_100
- ADBMOUSE_STANDARD_200
- ADBMOUSE_TRACKBALL
- ADBMOUSE_TRACKBALLPRO
- ADBMOUSE_TRACKPAD
- ADBMOUSE_TURBOMOUSE5
- ADBREQ_NOSEND
- ADBREQ_REPLY
- ADBREQ_SYNC
- ADBRamLink
- ADB_A3DIN
- ADB_A3DOUT
- ADB_ADDR
- ADB_BUSRESET
- ADB_CHAN
- ADB_CODECIN
- ADB_CODECOUT
- ADB_DMA
- ADB_DONGLE
- ADB_EQIN
- ADB_EQOUT
- ADB_FIFO_EN
- ADB_FIFO_EN_SHIFT
- ADB_FLUSH
- ADB_IOP
- ADB_IOP_AUTOPOLL
- ADB_IOP_EXISTS
- ADB_IOP_EXPLICIT
- ADB_IOP_FLUSH
- ADB_IOP_INT
- ADB_IOP_LISTEN
- ADB_IOP_POLL
- ADB_IOP_RESET
- ADB_IOP_SRQ
- ADB_IOP_TALK
- ADB_IOP_TIMEOUT
- ADB_IOP_UNINT
- ADB_KEYBOARD
- ADB_KEYBOARD_ANSI
- ADB_KEYBOARD_ISO
- ADB_KEYBOARD_JIS
- ADB_KEYBOARD_UNKNOWN
- ADB_KEY_CAPSLOCK
- ADB_KEY_CMD
- ADB_KEY_DEL
- ADB_KEY_FN
- ADB_KEY_FWDEL
- ADB_KEY_POWER
- ADB_KEY_POWER_OLD
- ADB_MAJOR
- ADB_MASK
- ADB_MISC
- ADB_MIXIN
- ADB_MIXOUT
- ADB_MODEM
- ADB_MOUSE
- ADB_MSG_POST_RESET
- ADB_MSG_POWERDOWN
- ADB_MSG_PRE_RESET
- ADB_PACKET
- ADB_QUERY
- ADB_QUERY_GETDEVINFO
- ADB_READREG
- ADB_RET_OK
- ADB_RET_TIMEOUT
- ADB_RST
- ADB_SHIFT
- ADB_SPDIFIN
- ADB_SPDIFOUT
- ADB_SPORTIN
- ADB_SPORTOUT
- ADB_SRCIN
- ADB_SRCOUT
- ADB_SUBBUF_MASK
- ADB_SUBBUF_SHIFT
- ADB_TABLET
- ADB_WRITEREG
- ADB_WTOUT
- ADB_XTALKIN
- ADB_XTALKOUT
- ADC
- ADC0
- ADC081C
- ADC081C_NUM_CHANNELS
- ADC081S_CHAN
- ADC0832_VOLTAGE_CHANNEL
- ADC0832_VOLTAGE_CHANNEL_DIFF
- ADC084S021_DRIVER_NAME
- ADC084S021_VOLTAGE_CHANNEL
- ADC1
- ADC101C
- ADC108S102_BITS
- ADC108S102_CMD
- ADC108S102_MAX_CHANNELS
- ADC108S102_RES_DATA
- ADC108S102_VA_MV_ACPI_DEFAULT
- ADC108S102_V_CHAN
- ADC12
- ADC12138_MODE_ACQUISITION_TIME_10
- ADC12138_MODE_ACQUISITION_TIME_18
- ADC12138_MODE_ACQUISITION_TIME_34
- ADC12138_MODE_ACQUISITION_TIME_6
- ADC12138_MODE_AUTO_CAL
- ADC12138_MODE_READ_STATUS
- ADC12138_STATUS_CAL
- ADC12138_VOLTAGE_CHANNEL
- ADC12138_VOLTAGE_CHANNEL_DIFF
- ADC121C
- ADC128_ATTR_NUM_VOLT
- ADC128_REG_ALARM
- ADC128_REG_BUSY_STATUS
- ADC128_REG_CONFIG
- ADC128_REG_CONFIG_ADV
- ADC128_REG_CONV_RATE
- ADC128_REG_DEV_ID
- ADC128_REG_IN
- ADC128_REG_IN_MAX
- ADC128_REG_IN_MIN
- ADC128_REG_MAN_ID
- ADC128_REG_MASK
- ADC128_REG_ONESHOT
- ADC128_REG_SHUTDOWN
- ADC128_REG_TEMP
- ADC128_REG_TEMP_HYST
- ADC128_REG_TEMP_MAX
- ADC128_VOLTAGE_CHANNEL
- ADC12_CK
- ADC12_K
- ADC12_R
- ADC2_CLAMP_VOLTAGE
- ADC2_CLAMP_VOLTAGE_MASK
- ADC2_REG
- ADC3_CK
- ADC5_1P25VREF
- ADC5_ABSOLUTE_CAL
- ADC5_AMUX_THM1
- ADC5_AMUX_THM1_100K_PU
- ADC5_AMUX_THM1_30K_PU
- ADC5_AMUX_THM1_400K_PU
- ADC5_AMUX_THM2
- ADC5_AMUX_THM2_100K_PU
- ADC5_AMUX_THM2_30K_PU
- ADC5_AMUX_THM2_400K_PU
- ADC5_AMUX_THM3
- ADC5_AMUX_THM3_100K_PU
- ADC5_AMUX_THM3_30K_PU
- ADC5_AMUX_THM3_400K_PU
- ADC5_AMUX_THM4
- ADC5_AMUX_THM4_100K_PU
- ADC5_AMUX_THM4_30K_PU
- ADC5_AMUX_THM4_400K_PU
- ADC5_AMUX_THM5
- ADC5_AMUX_THM5_100K_PU
- ADC5_AMUX_THM5_30K_PU
- ADC5_AMUX_THM5_400K_PU
- ADC5_AVG_SAMPLES_MAX
- ADC5_BAT_ID
- ADC5_BAT_ID_100K_PU
- ADC5_BAT_ID_30K_PU
- ADC5_BAT_ID_400K_PU
- ADC5_BAT_THERM
- ADC5_BAT_THERM_100K_PU
- ADC5_BAT_THERM_30K_PU
- ADC5_BAT_THERM_400K_PU
- ADC5_CHAN
- ADC5_CHAN_TEMP
- ADC5_CHAN_VOLT
- ADC5_CHG_TEMP
- ADC5_CONV_TIMEOUT
- ADC5_CONV_TIME_MAX_US
- ADC5_CONV_TIME_MIN_US
- ADC5_CONV_TIME_RETRY
- ADC5_CUR_REPLICA_VDS
- ADC5_CUR_SENS_BATFET_VDS_OFFSET
- ADC5_CUR_SENS_REPLICA_VDS_OFFSET
- ADC5_DECIMATION_DEFAULT
- ADC5_DECIMATION_LONG
- ADC5_DECIMATION_MEDIUM
- ADC5_DECIMATION_SAMPLES_MAX
- ADC5_DECIMATION_SHORT
- ADC5_DEF_VBAT_PRESCALING
- ADC5_DIE_TEMP
- ADC5_EXT_ISENSE_VBAT_IDATA
- ADC5_EXT_ISENSE_VBAT_VDATA
- ADC5_EXT_SENS_OFFSET
- ADC5_FULL_SCALE_CODE
- ADC5_GPIO1
- ADC5_GPIO1_100K_PU
- ADC5_GPIO1_30K_PU
- ADC5_GPIO1_400K_PU
- ADC5_GPIO1_DIV3
- ADC5_GPIO2
- ADC5_GPIO2_100K_PU
- ADC5_GPIO2_30K_PU
- ADC5_GPIO2_400K_PU
- ADC5_GPIO2_DIV3
- ADC5_GPIO3
- ADC5_GPIO3_100K_PU
- ADC5_GPIO3_30K_PU
- ADC5_GPIO3_400K_PU
- ADC5_GPIO3_DIV3
- ADC5_GPIO4
- ADC5_GPIO4_100K_PU
- ADC5_GPIO4_30K_PU
- ADC5_GPIO4_400K_PU
- ADC5_GPIO4_DIV3
- ADC5_GPIO5
- ADC5_GPIO5_100K_PU
- ADC5_GPIO5_30K_PU
- ADC5_GPIO5_400K_PU
- ADC5_GPIO5_DIV3
- ADC5_GPIO6
- ADC5_GPIO6_100K_PU
- ADC5_GPIO6_30K_PU
- ADC5_GPIO6_400K_PU
- ADC5_GPIO6_DIV3
- ADC5_GPIO7
- ADC5_GPIO7_100K_PU
- ADC5_GPIO7_30K_PU
- ADC5_GPIO7_400K_PU
- ADC5_GPIO7_DIV3
- ADC5_HW_SETTLE_DIFF_MAJOR
- ADC5_HW_SETTLE_DIFF_MINOR
- ADC5_INT_EXT_ISENSE
- ADC5_INT_EXT_ISENSE_VBAT_IDATA
- ADC5_INT_EXT_ISENSE_VBAT_VDATA
- ADC5_MAX_CHANNEL
- ADC5_MID_CHG_DIV6
- ADC5_NEW_CAL
- ADC5_NO_CAL
- ADC5_OFF
- ADC5_PARALLEL_ISENSE
- ADC5_PARALLEL_ISENSE_VBAT_IDATA
- ADC5_PARALLEL_ISENSE_VBAT_VDATA
- ADC5_RATIOMETRIC_CAL
- ADC5_REF_GND
- ADC5_SBUx
- ADC5_SBUx_100K_PU
- ADC5_SBUx_30K_PU
- ADC5_SBUx_400K_PU
- ADC5_SBUx_DIV3
- ADC5_TIMER_CAL
- ADC5_USB_IN_I
- ADC5_USB_IN_V_16
- ADC5_USR_CH_SEL_CTL
- ADC5_USR_CONV_REQ
- ADC5_USR_CONV_REQ_REQ
- ADC5_USR_DATA0
- ADC5_USR_DATA1
- ADC5_USR_DATA_CHECK
- ADC5_USR_DELAY_CTL
- ADC5_USR_DIG_PARAM
- ADC5_USR_DIG_PARAM_CAL_SEL
- ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT
- ADC5_USR_DIG_PARAM_CAL_VAL
- ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT
- ADC5_USR_DIG_PARAM_DEC_RATIO_SEL
- ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT
- ADC5_USR_EN_CTL1
- ADC5_USR_EN_CTL1_ADC_EN
- ADC5_USR_FAST_AVG_CTL
- ADC5_USR_FAST_AVG_CTL_EN
- ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK
- ADC5_USR_HW_SETTLE_DELAY_MASK
- ADC5_USR_IBAT_DATA0
- ADC5_USR_IBAT_DATA1
- ADC5_USR_IBAT_MEAS
- ADC5_USR_IBAT_MEAS_SUPPORTED
- ADC5_USR_REVISION1
- ADC5_USR_STATUS1
- ADC5_USR_STATUS1_EOC
- ADC5_USR_STATUS1_REQ_STS
- ADC5_USR_STATUS1_REQ_STS_EOC_MASK
- ADC5_USR_STATUS2
- ADC5_USR_STATUS2_CONV_SEQ_MASK
- ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT
- ADC5_VBAT_SNS
- ADC5_VCOIN
- ADC5_VPH_PWR
- ADC5_VREF_VADC
- ADC5_VREF_VADC5_DIV_3
- ADC5_XO_THERM
- ADC5_XO_THERM_100K_PU
- ADC5_XO_THERM_30K_PU
- ADC5_XO_THERM_400K_PU
- ADCBA
- ADCBA_MASK
- ADCBS
- ADCBS_BUFSIZE_1024
- ADCBS_BUFSIZE_10240
- ADCBS_BUFSIZE_12288
- ADCBS_BUFSIZE_1280
- ADCBS_BUFSIZE_14366
- ADCBS_BUFSIZE_1536
- ADCBS_BUFSIZE_16384
- ADCBS_BUFSIZE_1792
- ADCBS_BUFSIZE_2048
- ADCBS_BUFSIZE_20480
- ADCBS_BUFSIZE_24576
- ADCBS_BUFSIZE_2560
- ADCBS_BUFSIZE_28672
- ADCBS_BUFSIZE_3072
- ADCBS_BUFSIZE_32768
- ADCBS_BUFSIZE_3584
- ADCBS_BUFSIZE_384
- ADCBS_BUFSIZE_4096
- ADCBS_BUFSIZE_40960
- ADCBS_BUFSIZE_448
- ADCBS_BUFSIZE_49152
- ADCBS_BUFSIZE_512
- ADCBS_BUFSIZE_5120
- ADCBS_BUFSIZE_57344
- ADCBS_BUFSIZE_6144
- ADCBS_BUFSIZE_640
- ADCBS_BUFSIZE_65536
- ADCBS_BUFSIZE_7168
- ADCBS_BUFSIZE_768
- ADCBS_BUFSIZE_8192
- ADCBS_BUFSIZE_896
- ADCBS_BUFSIZE_NONE
- ADCCR
- ADCCR_LCHANENABLE
- ADCCR_RCHANENABLE
- ADCCR_SAMPLERATE_11
- ADCCR_SAMPLERATE_16
- ADCCR_SAMPLERATE_22
- ADCCR_SAMPLERATE_24
- ADCCR_SAMPLERATE_32
- ADCCR_SAMPLERATE_44
- ADCCR_SAMPLERATE_48
- ADCCR_SAMPLERATE_8
- ADCCR_SAMPLERATE_MASK
- ADCFSM_STEPID
- ADCIDX
- ADCIDX_IDX
- ADCIDX_MASK
- ADCLEAR_R
- ADCR
- ADCSET1_T
- ADCSET1_T_REFSEL_1V
- ADCSET1_T_REFSEL_1_5V
- ADCSET1_T_REFSEL_2V
- ADCSET1_T_REFSEL_MASK
- ADCSR
- ADCSRC
- ADCSR_ADF
- ADCSR_ADIE
- ADCSR_ADST
- ADCSR_CH_MASK
- ADCSR_CKS
- ADCSR_MULTI
- ADC_0dB
- ADC_12BIT_MODE
- ADC_12V_CURRENT_SCALE
- ADC_ACTIVE_BIT
- ADC_ADI
- ADC_ADI0
- ADC_ADI1
- ADC_AIEN
- ADC_ALC_CTRL1
- ADC_ALC_CTRL2
- ADC_ALC_CTRL3
- ADC_AMUX_PREMUX_SHIFT
- ADC_AMUX_SEL_SHIFT
- ADC_ANALOG_GATE_BITS
- ADC_ARB_BTM_AMUX_CNTRL
- ADC_ARB_BTM_ANA_PARAM
- ADC_ARB_BTM_BAT_COOL_THR0
- ADC_ARB_BTM_BAT_COOL_THR1
- ADC_ARB_BTM_BAT_WARM_THR0
- ADC_ARB_BTM_BAT_WARM_THR1
- ADC_ARB_BTM_CNTRL1
- ADC_ARB_BTM_CNTRL1_EN_BTM
- ADC_ARB_BTM_CNTRL1_EOC
- ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL1
- ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL2
- ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL3
- ADC_ARB_BTM_CNTRL1_MEAS_INTERVAL4
- ADC_ARB_BTM_CNTRL1_REQ
- ADC_ARB_BTM_CNTRL1_SEL_OP_MODE
- ADC_ARB_BTM_CNTRL2
- ADC_ARB_BTM_DATA0
- ADC_ARB_BTM_DATA1
- ADC_ARB_BTM_DIG_PARAM
- ADC_ARB_BTM_RSV
- ADC_ARB_USRP_AMUX_CNTRL
- ADC_ARB_USRP_AMUX_CNTRL_CHAN_MASK
- ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX0
- ADC_ARB_USRP_AMUX_CNTRL_PRESCALEMUX1
- ADC_ARB_USRP_AMUX_CNTRL_RSV0
- ADC_ARB_USRP_AMUX_CNTRL_RSV1
- ADC_ARB_USRP_AMUX_CNTRL_SEL0
- ADC_ARB_USRP_AMUX_CNTRL_SEL1
- ADC_ARB_USRP_AMUX_CNTRL_SEL2
- ADC_ARB_USRP_AMUX_CNTRL_SEL3
- ADC_ARB_USRP_ANA_PARAM
- ADC_ARB_USRP_ANA_PARAM_DIS
- ADC_ARB_USRP_ANA_PARAM_EN
- ADC_ARB_USRP_CNTRL
- ADC_ARB_USRP_CNTRL_EN_ARB
- ADC_ARB_USRP_CNTRL_EOC
- ADC_ARB_USRP_CNTRL_REQ
- ADC_ARB_USRP_CNTRL_RSV1
- ADC_ARB_USRP_CNTRL_RSV2
- ADC_ARB_USRP_CNTRL_RSV3
- ADC_ARB_USRP_CNTRL_RSV4
- ADC_ARB_USRP_CNTRL_RSV5
- ADC_ARB_USRP_DATA0
- ADC_ARB_USRP_DATA1
- ADC_ARB_USRP_DIG_PARAM
- ADC_ARB_USRP_DIG_PARAM_CLK_RATE0
- ADC_ARB_USRP_DIG_PARAM_CLK_RATE1
- ADC_ARB_USRP_DIG_PARAM_DEC_RATE0
- ADC_ARB_USRP_DIG_PARAM_DEC_RATE1
- ADC_ARB_USRP_DIG_PARAM_EN
- ADC_ARB_USRP_DIG_PARAM_EOC
- ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT0
- ADC_ARB_USRP_DIG_PARAM_SEL_SHIFT1
- ADC_ARB_USRP_RSV
- ADC_ARB_USRP_RSV_DTEST0
- ADC_ARB_USRP_RSV_DTEST1
- ADC_ARB_USRP_RSV_IP_SEL0
- ADC_ARB_USRP_RSV_IP_SEL1
- ADC_ARB_USRP_RSV_IP_SEL2
- ADC_ARB_USRP_RSV_OP
- ADC_ARB_USRP_RSV_RST
- ADC_ARB_USRP_RSV_TRM
- ADC_ATTEN_ADCL
- ADC_ATTEN_ADCR
- ADC_AUX
- ADC_AUX1
- ADC_AUX2
- ADC_AVGE
- ADC_AVGS_MASK
- ADC_AVGS_SHIFT
- ADC_BUFFER_CLEAR_REG
- ADC_CAL
- ADC_CALF
- ADC_CAL_ATEST_CH1
- ADC_CAL_ATEST_CH2
- ADC_CAL_ATEST_CH3
- ADC_CELL
- ADC_CHANLS_MAX
- ADC_CHANNEL
- ADC_CHANNEL_BACKUP
- ADC_CHANNEL_BATTERY
- ADC_CHANNEL_CHARGE
- ADC_CHANNEL_TS_X
- ADC_CHANNEL_TS_Y
- ADC_CHAN_SELECT
- ADC_CHNL_START_ADDR
- ADC_CH_ACCDET2_MAX
- ADC_CH_ACCDET2_MIN
- ADC_CH_BKBAT_MAX
- ADC_CH_BKBAT_MIN
- ADC_CH_BTEMP_MAX
- ADC_CH_BTEMP_MIN
- ADC_CH_CHG_I_MAX
- ADC_CH_CHG_I_MIN
- ADC_CH_CHG_V_MAX
- ADC_CH_CHG_V_MIN
- ADC_CH_DIETEMP_MAX
- ADC_CH_DIETEMP_MIN
- ADC_CH_IBAT_MAX
- ADC_CH_IBAT_MAX_V
- ADC_CH_IBAT_MIN
- ADC_CH_IBAT_MIN_V
- ADC_CH_MAIN_MAX
- ADC_CH_MAIN_MIN
- ADC_CH_VBAT_MAX
- ADC_CH_VBAT_MIN
- ADC_CH_VBUS_MAX
- ADC_CH_VBUS_MIN
- ADC_CLK
- ADC_CLK_DIV
- ADC_CLK_DIV_8
- ADC_CLK_DIV_MASK
- ADC_CLK_ENB
- ADC_CLK_SEL
- ADC_COMMON_BIT
- ADC_COMPLETE_INT_DISABLE
- ADC_COM_BIAS1
- ADC_COM_BIAS2
- ADC_COM_BIAS3
- ADC_COM_INT5_STAB_REF
- ADC_COM_QUANT
- ADC_CONTROL0_REG
- ADC_CONTROL1_REG
- ADC_CONVERT_REG
- ADC_CONV_DISABLE
- ADC_CONV_MODE_MASK
- ADC_CONV_START
- ADC_CON_EN_START
- ADC_CON_EN_START_MASK
- ADC_COUNT_LOWER_REG
- ADC_COUNT_UPPER_REG
- ADC_CPU_CURRENT_SCALE
- ADC_CPU_VOLTAGE_SCALE
- ADC_CTL_0
- ADC_CTL_1
- ADC_CTRL
- ADC_CTRL_DAC1_CH1
- ADC_CTRL_DAC1_CH2
- ADC_CTRL_DAC1_CH3
- ADC_CTRL_DAC23_CH1
- ADC_CTRL_DAC23_CH2
- ADC_CTRL_DAC23_CH3
- ADC_DATA
- ADC_DATA_START_ADDR
- ADC_DATX_MASK
- ADC_DATX_PRESSED
- ADC_DATY_MASK
- ADC_DCSERVO_DEM_CH1
- ADC_DCSERVO_DEM_CH2
- ADC_DCSERVO_DEM_CH3
- ADC_DC_CAL
- ADC_DEBOUNCE_TIME_0_5MS
- ADC_DEBOUNCE_TIME_10MS
- ADC_DEBOUNCE_TIME_25MS
- ADC_DEBOUNCE_TIME_38_62MS
- ADC_DEBOUNCE_TIME_5MS
- ADC_DECREMENT
- ADC_DELAY_INTERVAL_LOWER_REG
- ADC_DELAY_INTERVAL_UPPER_REG
- ADC_DIG_PARAM_DEC_SHIFT
- ADC_DITHER_BIT
- ADC_DIV_DEFAULT
- ADC_DIV_MASK
- ADC_DMA_DISABLE_BIT
- ADC_DMA_EN
- ADC_DONE_BIT
- ADC_EN
- ADC_ENABLE_BIT
- ADC_EXT_CONV_FALLING_BIT
- ADC_EXT_GATE_BITS
- ADC_FB_FRCRST_CH1
- ADC_FB_FRCRST_CH2
- ADC_FB_FRCRST_CH3
- ADC_FIFO_CLEAR_REG
- ADC_FIFO_REG
- ADC_FIRST_DLY
- ADC_FIRST_DLY_MODE
- ADC_FRAC_BITS
- ADC_GAIN_CAL
- ADC_GAIN_MASK
- ADC_GATE_LEVEL_BIT
- ADC_GATE_POLARITY_BIT
- ADC_GATE_SRC_MASK
- ADC_HARDWARE_TRIGGER
- ADC_HI_CHANNEL_4020_MASK
- ADC_HPF_DISABLE
- ADC_HW
- ADC_I2C_ADDR
- ADC_IFC_CTRL
- ADC_INCREMENT
- ADC_INPUT_BTEMP
- ADC_INPUT_CH1
- ADC_INPUT_CH2
- ADC_INPUT_CH3
- ADC_INPUT_CLK_MASK
- ADC_INPUT_IBAT
- ADC_INPUT_VBAT
- ADC_INPUT_VMAIN
- ADC_INT
- ADC_INTR_EOC_BITS
- ADC_INTR_EOSCAN_BITS
- ADC_INTR_EOSEQ_BITS
- ADC_INTR_PENDING_BIT
- ADC_INTR_QFULL_BITS
- ADC_INTR_SRC_MASK
- ADC_IPG_CLK
- ADC_LEFT
- ADC_LIMIT_CTRL
- ADC_LINEIN
- ADC_LOOP_MAX
- ADC_LO_CHANNEL_4020_MASK
- ADC_MASTER
- ADC_MAX
- ADC_MAX_LOW_MEASUREMENT_MV
- ADC_MICIN
- ADC_MIN
- ADC_MODE_MASK
- ADC_MOD_LEFT
- ADC_MOD_RIGHT
- ADC_MUTE
- ADC_MUTE_MASK
- ADC_MUX
- ADC_MUX_0
- ADC_MUX_1
- ADC_MUX_2
- ADC_MUX_3
- ADC_MUX_AIN0
- ADC_MUX_AUX
- ADC_MUX_IDLE
- ADC_MUX_IDLE1
- ADC_MUX_LINEIN
- ADC_MUX_MASK
- ADC_MUX_MIC
- ADC_MUX_PHONE
- ADC_MUX_PREAMPLIFIER
- ADC_NOISE_CTRL
- ADC_NOM_CHG_DETECT_1A
- ADC_NOM_CHG_DETECT_USB
- ADC_NONE
- ADC_NTF_PRECLMP_EN_CH1
- ADC_NTF_PRECLMP_EN_CH2
- ADC_NTF_PRECLMP_EN_CH3
- ADC_ON_12BIT
- ADC_ON_DIBTX
- ADC_OSR
- ADC_OVERRUN_BIT
- ADC_OVR
- ADC_POWER
- ADC_POWER_EVENT
- ADC_PWRDN_CLAMP_CH1
- ADC_PWRDN_CLAMP_CH2
- ADC_PWRDN_CLAMP_CH3
- ADC_QGAIN_RES_TRM_CH1
- ADC_QGAIN_RES_TRM_CH2
- ADC_QGAIN_RES_TRM_CH3
- ADC_QUEUE_CLEAR_REG
- ADC_QUEUE_CONFIG_BIT
- ADC_QUEUE_FIFO_REG
- ADC_QUEUE_HIGH_REG
- ADC_QUEUE_LOAD_REG
- ADC_READ_PNTR_REG
- ADC_RES
- ADC_RESOLUTION
- ADC_RIGHT
- ADC_RSV_IP_SEL_SHIFT
- ADC_RUNNING
- ADC_S3C2410_CON_SELMUX
- ADC_S3C2410_DATX_MASK
- ADC_S3C2410_MUX
- ADC_S3C2410_MUX_TS
- ADC_S3C2410_TSC_AUTO_PST
- ADC_S3C2410_TSC_PULL_UP_DISABLE
- ADC_S3C2410_TSC_XM_SEN
- ADC_S3C2410_TSC_XP_SEN
- ADC_S3C2410_TSC_XY_PST
- ADC_S3C2410_TSC_YM_SEN
- ADC_S3C2410_TSC_YP_SEN
- ADC_S3C2416_CON_RES_SEL
- ADC_S3C2443_TSC_UD_SEN
- ADC_SAMPLE_COUNTER_EN_BIT
- ADC_SAMPLE_INTERVAL_LOWER_REG
- ADC_SAMPLE_INTERVAL_UPPER_REG
- ADC_SAMPLE_MODE_MASK
- ADC_SAMPLE_TIME_CONF_REG
- ADC_SE_DIFF_BIT
- ADC_SHORT_SAMPLE_MODE
- ADC_SHUT
- ADC_SOC_PRECLMP_TERM_CH1
- ADC_SOC_PRECLMP_TERM_CH2
- ADC_SOC_PRECLMP_TERM_CH3
- ADC_SOFT_GATE_BITS
- ADC_SOURCE_LEFT_PSG
- ADC_SOURCE_RIGHT_PSG
- ADC_SRC_4020_MASK
- ADC_START_CONVERT_REG
- ADC_START_REG
- ADC_START_TRIG_ANALOG_BITS
- ADC_START_TRIG_EXT_BITS
- ADC_START_TRIG_FALLING_BIT
- ADC_START_TRIG_MASK
- ADC_START_TRIG_SOFT_BITS
- ADC_STATUS2_CH1
- ADC_STATUS2_CH2
- ADC_STATUS2_CH3
- ADC_STATUS_CH1
- ADC_STATUS_CH2
- ADC_STATUS_CH3
- ADC_STEP_MV
- ADC_STOP_BIT
- ADC_SW
- ADC_SW_CONV
- ADC_SW_GATE_BIT
- ADC_TARGET
- ADC_TIMEOUT
- ADC_TIMEOUT_DISABLE
- ADC_TO_CURR
- ADC_TO_MV
- ADC_TRANWIN_MASK
- ADC_TSC_AUTOPST
- ADC_TSC_WAIT4INT
- ADC_V1_CLRINTPNDNUP
- ADC_V1_CON
- ADC_V1_CON_PRSCEN
- ADC_V1_CON_PRSCLV
- ADC_V1_CON_RES
- ADC_V1_CON_STANDBY
- ADC_V1_DATX
- ADC_V1_DATY
- ADC_V1_DLY
- ADC_V1_INTCLR
- ADC_V1_MUX
- ADC_V1_TSC
- ADC_V1_UPDN
- ADC_V2_CON1
- ADC_V2_CON1_SOFT_RESET
- ADC_V2_CON2
- ADC_V2_CON2_ACH_MASK
- ADC_V2_CON2_ACH_SEL
- ADC_V2_CON2_C_TIME
- ADC_V2_CON2_ESEL
- ADC_V2_CON2_HIGHF
- ADC_V2_CON2_OSEL
- ADC_V2_INT_EN
- ADC_V2_INT_ST
- ADC_V2_STAT
- ADC_V2_VER
- ADC_VAL0C
- ADC_VAL20C
- ADC_VAL40C
- ADC_VAL60C
- ADC_VALUE_HIGH
- ADC_VALUE_LOW
- ADC_VIDEO
- ADC_WAIT
- ADC_WAIT_DEFAULT
- ADC_WRITE_PNTR_REG
- ADC_ZERODB
- ADCxx1C_CHAN
- ADCxx1C_MODEL
- ADD
- ADD128
- ADD3
- ADD48
- ADDA_AFE_ON_MASK
- ADDA_AFE_ON_MASK_SFT
- ADDA_AFE_ON_SFT
- ADDA_AUD_PAD_TOP_MON1_MASK
- ADDA_AUD_PAD_TOP_MON1_MASK_SFT
- ADDA_AUD_PAD_TOP_MON1_SFT
- ADDA_AUD_PAD_TOP_MON_MASK
- ADDA_AUD_PAD_TOP_MON_MASK_SFT
- ADDA_AUD_PAD_TOP_MON_SFT
- ADDA_PR
- ADDA_PR_ADDR_MASK
- ADDA_PR_ADDR_SHIFT
- ADDA_PR_DATA_IN_MASK
- ADDA_PR_DATA_IN_SHIFT
- ADDA_PR_DATA_OUT_MASK
- ADDA_PR_DATA_OUT_SHIFT
- ADDA_PR_RESET
- ADDA_PR_WRITE
- ADDBA_RESP_INTERVAL
- ADDBA_RSP_STATUS_ACCEPT
- ADDBA_Req_Report_parm
- ADDBA_STATUS_INVALID_PARAM
- ADDBA_STATUS_REFUSED
- ADDBA_STATUS_SUCCESS
- ADDBA_TO
- ADDBA_request
- ADDBPTR
- ADDC
- ADDC32
- ADDCTL
- ADDIS_R2_R12
- ADDITIONAL_ENTRIES
- ADDITIONAL_TRANSACTION_OPPORTUNITIES
- ADDIU
- ADDI_R2_R2
- ADDI_TCW_CTRL_CASCADE
- ADDI_TCW_CTRL_CNTR_ENA
- ADDI_TCW_CTRL_CNT_UP
- ADDI_TCW_CTRL_ENA
- ADDI_TCW_CTRL_EXT_CLK
- ADDI_TCW_CTRL_EXT_CLK_MASK
- ADDI_TCW_CTRL_EXT_CLK_STATUS
- ADDI_TCW_CTRL_EXT_GATE
- ADDI_TCW_CTRL_EXT_GATE_MASK
- ADDI_TCW_CTRL_EXT_TRIG
- ADDI_TCW_CTRL_EXT_TRIG_MASK
- ADDI_TCW_CTRL_GATE
- ADDI_TCW_CTRL_IRQ_ENA
- ADDI_TCW_CTRL_MODE
- ADDI_TCW_CTRL_MODE_MASK
- ADDI_TCW_CTRL_OUT
- ADDI_TCW_CTRL_OUT_MASK
- ADDI_TCW_CTRL_REG
- ADDI_TCW_CTRL_RESET_ENA
- ADDI_TCW_CTRL_TIMER_ENA
- ADDI_TCW_CTRL_TRIG
- ADDI_TCW_CTRL_WARN_ENA
- ADDI_TCW_IRQ
- ADDI_TCW_IRQ_REG
- ADDI_TCW_RELOAD_REG
- ADDI_TCW_STATUS_HARDWARE_TRIG
- ADDI_TCW_STATUS_OVERFLOW
- ADDI_TCW_STATUS_REG
- ADDI_TCW_STATUS_SOFT_CLR
- ADDI_TCW_STATUS_SOFT_TRIG
- ADDI_TCW_SYNC_CTR_DIS
- ADDI_TCW_SYNC_CTR_ENA
- ADDI_TCW_SYNC_CTR_TRIG
- ADDI_TCW_SYNC_REG
- ADDI_TCW_SYNC_TIMER_DIS
- ADDI_TCW_SYNC_TIMER_ENA
- ADDI_TCW_SYNC_TIMER_TRIG
- ADDI_TCW_SYNC_WDOG_DIS
- ADDI_TCW_SYNC_WDOG_ENA
- ADDI_TCW_SYNC_WDOG_TRIG
- ADDI_TCW_TIMEBASE_REG
- ADDI_TCW_VAL_REG
- ADDI_TCW_WARN_TIMEBASE_REG
- ADDI_TCW_WARN_TIMEVAL_REG
- ADDL_SEL_TIMEOUT
- ADDMSGI
- ADDMSGO
- ADDON_EN
- ADDPART_FLAG_NONE
- ADDPART_FLAG_RAID
- ADDPART_FLAG_WHOLEDISK
- ADDR
- ADDR0
- ADDR0_REG
- ADDR1
- ADDR1_REG
- ADDR2
- ADDR2BASE
- ADDR2PORT
- ADDR2_REG
- ADDRAH
- ADDRAL
- ADDRBH
- ADDRBL
- ADDRCH
- ADDRCHG
- ADDRCL
- ADDRCNTR_SEC
- ADDRCNTR_SEC_SHIFT
- ADDRCONF_NOTIFY_PRIORITY
- ADDRCONF_TIMER_FUZZ
- ADDRCONF_TIMER_FUZZ_MAX
- ADDRCONF_TIMER_FUZZ_MINUS
- ADDRDH
- ADDRDL
- ADDRESS
- ADDRESS_COUNT
- ADDRESS_ERROR
- ADDRESS_GROUP_MAX_LEN
- ADDRESS_IRQ
- ADDRESS_LEN
- ADDRESS_MAPPING
- ADDRESS_MASK
- ADDRESS_MSK
- ADDRESS_NAME_LEN
- ADDRESS_S
- ADDRESS_SHIFT
- ADDRESS_STATE
- ADDRESS_U1_DEVICE_TYP
- ADDRESS_U1_DEV_CTRL_1
- ADDRESS_U1_NUM_SENS_X
- ADDRESS_U1_NUM_SENS_Y
- ADDRESS_U1_PAD_BTN
- ADDRESS_U1_PITCH_SENS_X
- ADDRESS_U1_PITCH_SENS_Y
- ADDRESS_U1_RESO_DWN_ABS
- ADDRESS_U1_SP_BTN
- ADDRESS_V
- ADDRESS_WATCH_CNTL_OFFSET
- ADDRESS_WATCH_REG_ADDHIGH_MASK
- ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION
- ADDRESS_WATCH_REG_ADDLOW_SHIFT
- ADDRESS_WATCH_REG_ADDR_HI
- ADDRESS_WATCH_REG_ADDR_LO
- ADDRESS_WATCH_REG_CNTL
- ADDRESS_WATCH_REG_CNTL_ATC_BIT
- ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK
- ADDRESS_WATCH_REG_MAX
- ADDRH
- ADDRL
- ADDRLABEL
- ADDRLEN
- ADDRMASK
- ADDROFF
- ADDRQ_STAT
- ADDRS
- ADDRS_DEMOD
- ADDRS_PER_BLOCK
- ADDRS_PER_INODE
- ADDRS_PER_PAGE
- ADDRS_RADIO
- ADDRS_TV
- ADDRS_TV_WITH_DEMOD
- ADDRWIN_MAP_DST_DDR
- ADDRWIN_MAP_DST_LIO
- ADDRWIN_MAP_DST_PCI
- ADDRWIN_WIN0
- ADDRWIN_WIN1
- ADDRWIN_WIN2
- ADDRWIN_WIN3
- ADDR_1G_MASK
- ADDR_2M_MASK
- ADDR_4K_MASK
- ADDR_4MB_MASK
- ADDR_64BITS
- ADDR_64K_MASK
- ADDR_ANY
- ADDR_AT_SCU_SPACE
- ADDR_B1A6_STREAM_CTRL
- ADDR_B600_VOLTAGE_13V
- ADDR_B601_VOLTAGE_18V
- ADDR_B880_READ_REMOTE
- ADDR_BANK_MASK
- ADDR_BANK_SHIFT
- ADDR_BCAST
- ADDR_BMP_AP
- ADDR_BMP_BSSID
- ADDR_BMP_BSS_IDX_MASK
- ADDR_BMP_BSS_IDX_SHIFT
- ADDR_BMP_RA
- ADDR_BMP_RESERVED1
- ADDR_BMP_RESERVED2
- ADDR_BMP_RESERVED3
- ADDR_BMP_STA
- ADDR_BMP_TA
- ADDR_BNDRY
- ADDR_CHECK_FREQUENCY
- ADDR_CH_DIS
- ADDR_CLI_IDX
- ADDR_COLUMN
- ADDR_COLUMN_PAGE
- ADDR_COL_MASK
- ADDR_COMPAT_LAYOUT
- ADDR_CONFIG_16_BANK
- ADDR_CONFIG_16_PIPE
- ADDR_CONFIG_1KB_ROW
- ADDR_CONFIG_1_BANK
- ADDR_CONFIG_1_GPU
- ADDR_CONFIG_1_LOWER_PIPES
- ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS
- ADDR_CONFIG_1_PIPE
- ADDR_CONFIG_1_RB_PER_SHADER_ENGINE
- ADDR_CONFIG_1_SHADER_ENGINE
- ADDR_CONFIG_2KB_ROW
- ADDR_CONFIG_2_BANK
- ADDR_CONFIG_2_GPU
- ADDR_CONFIG_2_LOWER_PIPES
- ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS
- ADDR_CONFIG_2_PIPE
- ADDR_CONFIG_2_RB_PER_SHADER_ENGINE
- ADDR_CONFIG_2_SHADER_ENGINE
- ADDR_CONFIG_32_PIPE
- ADDR_CONFIG_4KB_ROW
- ADDR_CONFIG_4_BANK
- ADDR_CONFIG_4_GPU
- ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS
- ADDR_CONFIG_4_PIPE
- ADDR_CONFIG_4_RB_PER_SHADER_ENGINE
- ADDR_CONFIG_4_SHADER_ENGINE
- ADDR_CONFIG_64_PIPE
- ADDR_CONFIG_8_BANK
- ADDR_CONFIG_8_GPU
- ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS
- ADDR_CONFIG_8_PIPE
- ADDR_CONFIG_8_SHADER_ENGINE
- ADDR_CONFIG_BANK_INTERLEAVE_1
- ADDR_CONFIG_BANK_INTERLEAVE_2
- ADDR_CONFIG_BANK_INTERLEAVE_4
- ADDR_CONFIG_BANK_INTERLEAVE_8
- ADDR_CONFIG_DISABLE_SE
- ADDR_CONFIG_ENABLE_SE
- ADDR_CONFIG_GPU_TILE_128
- ADDR_CONFIG_GPU_TILE_16
- ADDR_CONFIG_GPU_TILE_32
- ADDR_CONFIG_GPU_TILE_64
- ADDR_CONFIG_PIPE_INTERLEAVE_1KB
- ADDR_CONFIG_PIPE_INTERLEAVE_256B
- ADDR_CONFIG_PIPE_INTERLEAVE_2KB
- ADDR_CONFIG_PIPE_INTERLEAVE_512B
- ADDR_CONFIG_SE_TILE_16
- ADDR_CONFIG_SE_TILE_32
- ADDR_DEV
- ADDR_DIRECT
- ADDR_DMEM
- ADDR_DVD0
- ADDR_DVD1
- ADDR_EMPTY
- ADDR_ERAL
- ADDR_ERROR
- ADDR_ERR_EVEN
- ADDR_ERR_ODD
- ADDR_EWDS
- ADDR_EWEN
- ADDR_EXTENT
- ADDR_FAMILY_IPV4
- ADDR_FAMILY_IPV6
- ADDR_FAMILY_NONE
- ADDR_FETCH_TYPE
- ADDR_FILTX
- ADDR_FILTX_FB_ADDRHI
- ADDR_FILTX_FB_TYPE
- ADDR_FILTX_FB_VALID
- ADDR_FILTX_SB_ADDRLO
- ADDR_FIX_1
- ADDR_FIX_2
- ADDR_FIX_3
- ADDR_FIX_4
- ADDR_FIX_5
- ADDR_GEN_128MB
- ADDR_GEN_1GB
- ADDR_GEN_256MB
- ADDR_GEN_512MB
- ADDR_H
- ADDR_HI
- ADDR_HOLD
- ADDR_IMEM
- ADDR_INC_DISABLE
- ADDR_INDIRECT
- ADDR_INV_ABORT_ALU
- ADDR_IN_4BYTES
- ADDR_IN_RANGE
- ADDR_IN_WINDOW1
- ADDR_L
- ADDR_LEN
- ADDR_LE_DEV_PUBLIC
- ADDR_LE_DEV_RANDOM
- ADDR_LIMIT_32BIT
- ADDR_LIMIT_3GB
- ADDR_LO
- ADDR_MAP_MASK
- ADDR_MARK_128TB
- ADDR_MARK_256TB
- ADDR_MASK
- ADDR_MCAST
- ADDR_NEW
- ADDR_NO_RANDOMIZE
- ADDR_NUM_BANKS_BC_BANKS_1
- ADDR_NUM_BANKS_BC_BANKS_16
- ADDR_NUM_BANKS_BC_BANKS_2
- ADDR_NUM_BANKS_BC_BANKS_4
- ADDR_NUM_BANKS_BC_BANKS_8
- ADDR_NUM_PIPES_BC_P16
- ADDR_NUM_PIPES_BC_P8
- ADDR_OFFSET
- ADDR_OF_256B_BLOCK
- ADDR_OF_8KB_BLOCK
- ADDR_ONLY
- ADDR_PAGE
- ADDR_PORT
- ADDR_RANGE_MIRRORING
- ADDR_REG1
- ADDR_REG2
- ADDR_REG_OFFSET
- ADDR_ROW_MASK
- ADDR_ROW_SHIFT
- ADDR_RST
- ADDR_SETUP_PROT
- ADDR_SHIFT
- ADDR_SIZE_PREFIX
- ADDR_SRV_IDX
- ADDR_STA0_DVD
- ADDR_STR_COUNT
- ADDR_STR_COUNT_LOG
- ADDR_STR_COUNT_MASK
- ADDR_SURF_16_BANK
- ADDR_SURF_2_BANK
- ADDR_SURF_4_BANK
- ADDR_SURF_8_BANK
- ADDR_SURF_BANK_HEIGHT_1
- ADDR_SURF_BANK_HEIGHT_2
- ADDR_SURF_BANK_HEIGHT_4
- ADDR_SURF_BANK_HEIGHT_8
- ADDR_SURF_BANK_WH_1
- ADDR_SURF_BANK_WH_2
- ADDR_SURF_BANK_WH_4
- ADDR_SURF_BANK_WH_8
- ADDR_SURF_BANK_WIDTH_1
- ADDR_SURF_BANK_WIDTH_2
- ADDR_SURF_BANK_WIDTH_4
- ADDR_SURF_BANK_WIDTH_8
- ADDR_SURF_DEPTH_MICRO_TILING
- ADDR_SURF_DISPLAY_MICRO_TILING
- ADDR_SURF_MACRO_ASPECT_1
- ADDR_SURF_MACRO_ASPECT_2
- ADDR_SURF_MACRO_ASPECT_4
- ADDR_SURF_MACRO_ASPECT_8
- ADDR_SURF_MACRO_TILE_ASPECT_1
- ADDR_SURF_MACRO_TILE_ASPECT_2
- ADDR_SURF_MACRO_TILE_ASPECT_4
- ADDR_SURF_MACRO_TILE_ASPECT_8
- ADDR_SURF_MICRO_TILING_DISPLAY
- ADDR_SURF_MICRO_TILING_NON_DISPLAY
- ADDR_SURF_P16
- ADDR_SURF_P16_32x32_16x16
- ADDR_SURF_P16_32x32_8x16
- ADDR_SURF_P2
- ADDR_SURF_P2_RESERVED0
- ADDR_SURF_P2_RESERVED1
- ADDR_SURF_P2_RESERVED2
- ADDR_SURF_P4_16x16
- ADDR_SURF_P4_16x32
- ADDR_SURF_P4_32x32
- ADDR_SURF_P4_8x16
- ADDR_SURF_P8_16x16_8x16
- ADDR_SURF_P8_16x32_16x16
- ADDR_SURF_P8_16x32_8x16
- ADDR_SURF_P8_32x32_16x16
- ADDR_SURF_P8_32x32_16x32
- ADDR_SURF_P8_32x32_8x16
- ADDR_SURF_P8_32x64_32x32
- ADDR_SURF_P8_RESERVED0
- ADDR_SURF_ROTATED_MICRO_TILING
- ADDR_SURF_SAMPLE_SPLIT_1
- ADDR_SURF_SAMPLE_SPLIT_2
- ADDR_SURF_SAMPLE_SPLIT_4
- ADDR_SURF_SAMPLE_SPLIT_8
- ADDR_SURF_THICK_MICRO_TILING
- ADDR_SURF_THIN_MICRO_TILING
- ADDR_SURF_TILE_SPLIT_128B
- ADDR_SURF_TILE_SPLIT_1KB
- ADDR_SURF_TILE_SPLIT_256B
- ADDR_SURF_TILE_SPLIT_2KB
- ADDR_SURF_TILE_SPLIT_4KB
- ADDR_SURF_TILE_SPLIT_512B
- ADDR_SURF_TILE_SPLIT_64B
- ADDR_SWITCH_HINT
- ADDR_TO_FLASH_U2
- ADDR_TO_FLASH_U3
- ADDR_TO_REGION
- ADDR_TRAP_SPACING
- ADDR_TYPE_EXPECTED_LOCAL
- ADDR_TYPE_EXPECTED_REMOTE
- ADDR_TYPE_LOCAL
- ADDR_TYPE_MCAST
- ADDR_TYPE_REMOTE
- ADDR_UCAST
- ADDR_UNALIGNED_BITS
- ADDR_UNSET
- ADDR_VALID
- ADDSEL1_MASK
- ADDSEL1_REGEN
- ADDVFH
- ADDVFL
- ADD_64
- ADD_64_LE
- ADD_64_LE16
- ADD_ADDR
- ADD_ADDR_ENABLE
- ADD_ADDR_HI_MASK
- ADD_ADDR_INCR
- ADD_BATCHCMD
- ADD_CACHE_INFO
- ADD_COMM_TALLIES
- ADD_CONFIG_TERM
- ADD_COUNTER
- ADD_CPY_FLAG
- ADD_CTLS
- ADD_DELTA_TSF
- ADD_DMI_ATTR
- ADD_DT_NODE
- ADD_ENTROPY_ASYNC
- ADD_ENTROPY_GET_RESULT
- ADD_ENTROPY_RESET_ASYNC
- ADD_EP
- ADD_EVENT_FIELD
- ADD_EVSEL_CONFIG
- ADD_EXTEND_64
- ADD_FCS_BIT
- ADD_FIELD
- ADD_FILE
- ADD_FO1_DISABLE_GPIO_LED_CTRL
- ADD_FO1_ENABLE_PUREX_IOCB
- ADD_FO2_ENABLE_SEL_CLS2
- ADD_FO3_NO_ABT_ON_LINK_DOWN
- ADD_FO_COUNT
- ADD_HOTPLUG_VAR
- ADD_ID
- ADD_ID_MASK
- ADD_IF_GE
- ADD_INDEX_LOG
- ADD_LEN
- ADD_LER
- ADD_LIMITED
- ADD_LLI
- ADD_MANAGED_RESOURCE
- ADD_MASK
- ADD_MULTICAST
- ADD_MULTIPLE_PRIO
- ADD_NEW_DISK
- ADD_NOT_SUPPORTED
- ADD_NS
- ADD_ONE_WITH_WRAP_AROUND
- ADD_PERF_COUNTER
- ADD_PORT
- ADD_PREQ
- ADD_PRIO
- ADD_RATE_INIT
- ADD_ROCKCHIP_SUB_DRIVER
- ADD_ROUND
- ADD_SHIFT
- ADD_SIG
- ADD_SLOT_ATTR_NAME
- ADD_SM
- ADD_STA
- ADD_STAT64
- ADD_STATS_64
- ADD_STATUS
- ADD_STATUS_FW_NOT_SUPPORTED
- ADD_STATUS_INVALID_REQUEST
- ADD_STATUS_OPERATION_ALREADY_ACTIVE
- ADD_STA_IMMEDIATE_BA_FAILURE
- ADD_STA_KEY
- ADD_STA_MODIFY_NON_EXISTING_STA
- ADD_STA_MODIFY_NON_EXIST_STA
- ADD_STA_NO_BLOCK_ACK_RESOURCE
- ADD_STA_NO_ROOM_IN_TABLE
- ADD_STA_NO_ROOM_IN_TBL
- ADD_STA_STATIONS_OVERLOAD
- ADD_STA_STATS
- ADD_STA_SUCCESS
- ADD_STA_SUCCESS_MSK
- ADD_TEXT
- ADD_TO_MCG
- ADD_TO_MLQUEUE
- ADD_UVERBS_ATTRIBUTES_SIMPLE
- ADD_UVERBS_METHODS
- ADD_VLAN_CMD
- ADE0_QOSGENERATOR_EXTCONTROL
- ADE0_QOSGENERATOR_MODE
- ADE1_QOSGENERATOR_EXTCONTROL
- ADE1_QOSGENERATOR_MODE
- ADE7854_ACCMODE
- ADE7854_AFVARGAIN
- ADE7854_AFVARHR
- ADE7854_AFVAROS
- ADE7854_AFWATTHR
- ADE7854_AFWATTOS
- ADE7854_AFWGAIN
- ADE7854_AIGAIN
- ADE7854_AIRMS
- ADE7854_AIRMSOS
- ADE7854_ANGLE0
- ADE7854_ANGLE1
- ADE7854_ANGLE2
- ADE7854_APHCAL
- ADE7854_APNOLOAD
- ADE7854_AVA
- ADE7854_AVAGAIN
- ADE7854_AVAHR
- ADE7854_AVARGAIN
- ADE7854_AVARHR
- ADE7854_AVAROS
- ADE7854_AVGAIN
- ADE7854_AVRMS
- ADE7854_AVRMSOS
- ADE7854_AWATT
- ADE7854_AWATTHR
- ADE7854_AWATTOS
- ADE7854_AWGAIN
- ADE7854_BFVARGAIN
- ADE7854_BFVARHR
- ADE7854_BFVAROS
- ADE7854_BFWATTHR
- ADE7854_BFWATTOS
- ADE7854_BFWGAIN
- ADE7854_BIGAIN
- ADE7854_BIRMS
- ADE7854_BIRMSOS
- ADE7854_BPHCAL
- ADE7854_BVA
- ADE7854_BVAGAIN
- ADE7854_BVAHR
- ADE7854_BVARGAIN
- ADE7854_BVARHR
- ADE7854_BVAROS
- ADE7854_BVGAIN
- ADE7854_BVRMS
- ADE7854_BVRMSOS
- ADE7854_BWATT
- ADE7854_BWATTHR
- ADE7854_BWATTOS
- ADE7854_BWGAIN
- ADE7854_CF1DEN
- ADE7854_CF2DEN
- ADE7854_CF3DEN
- ADE7854_CFCYC
- ADE7854_CFMODE
- ADE7854_CFVARGAIN
- ADE7854_CFVARHR
- ADE7854_CFVAROS
- ADE7854_CFWATTHR
- ADE7854_CFWATTOS
- ADE7854_CFWGAIN
- ADE7854_CHECKSUM
- ADE7854_CIGAIN
- ADE7854_CIRMS
- ADE7854_CIRMSOS
- ADE7854_COMPMODE
- ADE7854_CONFIG
- ADE7854_CONFIG2
- ADE7854_CPHCAL
- ADE7854_CVA
- ADE7854_CVAGAIN
- ADE7854_CVAHR
- ADE7854_CVARGAIN
- ADE7854_CVARHR
- ADE7854_CVAROS
- ADE7854_CVGAIN
- ADE7854_CVRMS
- ADE7854_CVRMSOS
- ADE7854_CWATT
- ADE7854_CWATTHR
- ADE7854_CWATTOS
- ADE7854_CWGAIN
- ADE7854_DICOEFF
- ADE7854_GAIN
- ADE7854_HPFDIS
- ADE7854_HSDC_CFG
- ADE7854_IAWV
- ADE7854_IBWV
- ADE7854_ICWV
- ADE7854_IPEAK
- ADE7854_ISUM
- ADE7854_ISUMLVL
- ADE7854_LCYCMODE
- ADE7854_LINECYC
- ADE7854_MASK0
- ADE7854_MASK1
- ADE7854_MAX_RX
- ADE7854_MAX_TX
- ADE7854_MMODE
- ADE7854_NIGAIN
- ADE7854_NIRMS
- ADE7854_NIRMSOS
- ADE7854_OILVL
- ADE7854_OVLVL
- ADE7854_PEAKCYC
- ADE7854_PERIOD
- ADE7854_PHNOLOAD
- ADE7854_PHSIGN
- ADE7854_PHSTATUS
- ADE7854_READ_REG
- ADE7854_RSV
- ADE7854_RUN
- ADE7854_SAGCYC
- ADE7854_SAGLVL
- ADE7854_SPI_BURST
- ADE7854_SPI_FAST
- ADE7854_SPI_SLOW
- ADE7854_STARTUP_DELAY
- ADE7854_STATUS0
- ADE7854_STATUS1
- ADE7854_VANOLOAD
- ADE7854_VARNOLOAD
- ADE7854_VARTHR0
- ADE7854_VARTHR1
- ADE7854_VATHR0
- ADE7854_VATHR1
- ADE7854_VAWV
- ADE7854_VBWV
- ADE7854_VCWV
- ADE7854_VLEVEL
- ADE7854_VNOM
- ADE7854_VPEAK
- ADE7854_WRITE_REG
- ADE7854_WTHR0
- ADE7854_WTHR1
- ADE7854_ZXTOUT
- ADE_ABGR_8888
- ADE_ALP_GLOBAL
- ADE_ALP_MUL_COEFF_0
- ADE_ALP_MUL_COEFF_1
- ADE_ALP_MUL_COEFF_2
- ADE_ALP_MUL_COEFF_3
- ADE_ALP_PIXEL
- ADE_ALP_PIXEL_AND_GLB
- ADE_ARGB_8888
- ADE_BGRA_8888
- ADE_BGR_565
- ADE_BGR_888
- ADE_CH1
- ADE_CH_NUM
- ADE_CLIP_DISABLE
- ADE_CLIP_SIZE0
- ADE_CLIP_SIZE1
- ADE_CTRAN1
- ADE_CTRAN2
- ADE_CTRAN3
- ADE_CTRAN4
- ADE_CTRAN5
- ADE_CTRAN6
- ADE_CTRAN_DIS
- ADE_CTRAN_IMAGE_SIZE
- ADE_CTRAN_NUM
- ADE_CTRL
- ADE_CTRL1
- ADE_DEBUG
- ADE_DISABLE
- ADE_DISP_SRC_CFG
- ADE_EN
- ADE_ENABLE
- ADE_FORMAT_UNSUPPORT
- ADE_OVLY1
- ADE_OVLY1_TRANS_CFG
- ADE_OVLY2
- ADE_OVLY3
- ADE_OVLYX_CTL
- ADE_OVLY_CH_CTL
- ADE_OVLY_CH_XY0
- ADE_OVLY_CH_XY1
- ADE_OVLY_CTL
- ADE_OVLY_NUM
- ADE_OVLY_OUTPUT_SIZE
- ADE_RELOAD_DIS
- ADE_RGBA_8888
- ADE_RGB_565
- ADE_RGB_888
- ADE_SCL1
- ADE_SCL2
- ADE_SCL3
- ADE_SCL_NUM
- ADE_SOFT_RST_SEL
- ADE_XBGR_8888
- ADE_XRGB_8888
- ADF
- ADF4350_FREQ
- ADF4350_FREQ_REFIN
- ADF4350_FREQ_RESOLUTION
- ADF4350_MAX_BANDSEL_CLK
- ADF4350_MAX_FREQ_45_PRESC
- ADF4350_MAX_FREQ_PFD
- ADF4350_MAX_FREQ_REFIN
- ADF4350_MAX_MODULUS
- ADF4350_MAX_OUT_FREQ
- ADF4350_MAX_R_CNT
- ADF4350_MIN_OUT_FREQ
- ADF4350_MIN_VCO_FREQ
- ADF4350_MUXOUT_ANALOG_LOCK_DETECT
- ADF4350_MUXOUT_DIGITAL_LOCK_DETECT
- ADF4350_MUXOUT_DVDD
- ADF4350_MUXOUT_GND
- ADF4350_MUXOUT_N_DIV_OUT
- ADF4350_MUXOUT_R_DIV_OUT
- ADF4350_MUXOUT_THREESTATE
- ADF4350_PWRDOWN
- ADF4350_REG0
- ADF4350_REG0_FRACT
- ADF4350_REG0_INT
- ADF4350_REG1
- ADF4350_REG1_MOD
- ADF4350_REG1_PHASE
- ADF4350_REG1_PRESCALER
- ADF4350_REG2
- ADF4350_REG2_10BIT_R_CNT
- ADF4350_REG2_CHARGE_PUMP_CURR_uA
- ADF4350_REG2_COUNTER_RESET_EN
- ADF4350_REG2_CP_THREESTATE_EN
- ADF4350_REG2_DOUBLE_BUFF_EN
- ADF4350_REG2_LDF_FRACT_N
- ADF4350_REG2_LDF_INT_N
- ADF4350_REG2_LDP_10ns
- ADF4350_REG2_LDP_6ns
- ADF4350_REG2_MUXOUT
- ADF4350_REG2_NOISE_MODE
- ADF4350_REG2_PD_POLARITY_POS
- ADF4350_REG2_POWER_DOWN_EN
- ADF4350_REG2_RDIV2_EN
- ADF4350_REG2_RMULT2_EN
- ADF4350_REG3
- ADF4350_REG3_12BIT_CLKDIV
- ADF4350_REG3_12BIT_CLKDIV_MODE
- ADF4350_REG3_12BIT_CSR_EN
- ADF4350_REG4
- ADF4350_REG4_8BIT_BAND_SEL_CLKDIV
- ADF4350_REG4_AUX_OUTPUT_DIV
- ADF4350_REG4_AUX_OUTPUT_EN
- ADF4350_REG4_AUX_OUTPUT_FUND
- ADF4350_REG4_AUX_OUTPUT_PWR
- ADF4350_REG4_FEEDBACK_DIVIDED
- ADF4350_REG4_FEEDBACK_FUND
- ADF4350_REG4_MUTE_TILL_LOCK_EN
- ADF4350_REG4_OUTPUT_PWR
- ADF4350_REG4_RF_DIV_SEL
- ADF4350_REG4_RF_OUT_EN
- ADF4350_REG4_VCO_PWRDOWN_EN
- ADF4350_REG5
- ADF4350_REG5_LD_PIN_MODE_DIGITAL
- ADF4350_REG5_LD_PIN_MODE_HIGH
- ADF4350_REG5_LD_PIN_MODE_LOW
- ADF4351_MIN_OUT_FREQ
- ADF4351_REG3_ANTI_BACKLASH_3ns_EN
- ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH
- ADF4351_REG3_CHARGE_CANCELLATION_EN
- ADF4371
- ADF4371_ADDR_ASC
- ADF4371_ADDR_ASC_MSK
- ADF4371_ADDR_ASC_R
- ADF4371_ADDR_ASC_R_MSK
- ADF4371_CHANNEL
- ADF4371_CHANNEL_NAME
- ADF4371_CHECK_RANGE
- ADF4371_CH_RF16
- ADF4371_CH_RF32
- ADF4371_CH_RF8
- ADF4371_CH_RFAUX8
- ADF4371_FRAC1WORD
- ADF4371_FRAC1WORD_MSK
- ADF4371_FRAC2WORD_H
- ADF4371_FRAC2WORD_H_MSK
- ADF4371_FRAC2WORD_L
- ADF4371_FRAC2WORD_L_MSK
- ADF4371_FREQ
- ADF4371_MAX_FREQ_PFD
- ADF4371_MAX_FREQ_REFIN
- ADF4371_MAX_MODULUS2
- ADF4371_MAX_OUT_RF16_FREQ
- ADF4371_MAX_OUT_RF32_FREQ
- ADF4371_MAX_OUT_RF8_FREQ
- ADF4371_MAX_VCO_FREQ
- ADF4371_MIN_OUT_RF16_FREQ
- ADF4371_MIN_OUT_RF32_FREQ
- ADF4371_MIN_OUT_RF8_FREQ
- ADF4371_MIN_VCO_FREQ
- ADF4371_MOD2WORD
- ADF4371_MOD2WORD_MSK
- ADF4371_MODULUS1
- ADF4371_MUTE_LD
- ADF4371_MUTE_LD_MSK
- ADF4371_POWER_DOWN
- ADF4371_REG
- ADF4371_RESET_CMD
- ADF4371_RF_DIV_SEL
- ADF4371_RF_DIV_SEL_MSK
- ADF4371_TIMEOUT
- ADF4371_TIMEOUT_MSK
- ADF4371_VCO_ALC_TOUT
- ADF4371_VCO_ALC_TOUT_MSK
- ADF4372
- ADF7242_REPORT_CSMA_CA_STAT
- ADFIFO_R
- ADFSDM_K
- ADFSR
- ADFS_BAD_FRAG
- ADFS_DEFAULT_OTHER_MASK
- ADFS_DEFAULT_OWNER_MASK
- ADFS_DIR_F_H
- ADFS_DISCRECORD
- ADFS_DR_OFFSET
- ADFS_DR_SIZE
- ADFS_DR_SIZE_BITS
- ADFS_FILETYPE_NONE
- ADFS_FPLUS_NAME_LEN
- ADFS_FREE_FRAG
- ADFS_F_NAME_LEN
- ADFS_I
- ADFS_MAX_NAME_LEN
- ADFS_NDA_DIRECTORY
- ADFS_NDA_EXECUTE
- ADFS_NDA_LOCKED
- ADFS_NDA_OWNER_READ
- ADFS_NDA_OWNER_WRITE
- ADFS_NDA_PUBLIC_READ
- ADFS_NDA_PUBLIC_WRITE
- ADFS_NEWDIR_SIZE
- ADFS_NUM_DIR_ENTRIES
- ADFS_ROOT_FRAG
- ADFS_SB
- ADFS_SB_FLAGS
- ADFS_SUPER_MAGIC
- ADFWOPT_AUTOCONN_DISABLE
- ADFWOPT_SERIALIZE_TASK_MGMT
- ADF_2001
- ADF_2012A
- ADF_ACCEL_CAPABILITIES_AUTHENTICATION
- ADF_ACCEL_CAPABILITIES_CIPHER
- ADF_ACCEL_CAPABILITIES_COMPRESSION
- ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC
- ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC
- ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION
- ADF_ACCEL_CAPABILITIES_NULL
- ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER
- ADF_ACCEL_DEVICES_H_
- ADF_ACCEL_SEC
- ADF_ACCEL_STR
- ADF_ADMINMSG_LEN
- ADF_ALL
- ADF_ALL_2000
- ADF_ALL_CACHE
- ADF_ALL_EATA
- ADF_ALL_MASTER
- ADF_ALL_PLUS
- ADF_ALL_SC3
- ADF_ALL_SC4
- ADF_ALL_SC5
- ADF_ARB_NUM
- ADF_ARB_OFFSET
- ADF_ARB_REG_SIZE
- ADF_ARB_REG_SLOT
- ADF_ARB_RINGSRVARBEN_OFFSET
- ADF_ARB_RO_EN_OFFSET
- ADF_ARB_WQCFG_OFFSET
- ADF_ARB_WRK_2_SER_MAP_OFFSET
- ADF_ARB_WTR_OFFSET
- ADF_ARB_WTR_SIZE
- ADF_BANK_INT_FLAG_CLEAR_MASK
- ADF_BANK_INT_SRC_SEL_MASK_0
- ADF_BANK_INT_SRC_SEL_MASK_X
- ADF_BUILD_VERSION
- ADF_BYTES_TO_MSG_SIZE
- ADF_C3XXXIOV_ACCELENGINES_MASK
- ADF_C3XXXIOV_ACCELERATORS_MASK
- ADF_C3XXXIOV_ETR_BAR
- ADF_C3XXXIOV_ETR_MAX_BANKS
- ADF_C3XXXIOV_MAX_ACCELENGINES
- ADF_C3XXXIOV_MAX_ACCELERATORS
- ADF_C3XXXIOV_PCI_DEVICE_ID
- ADF_C3XXXIOV_PF2VF_OFFSET
- ADF_C3XXXIOV_PMISC_BAR
- ADF_C3XXXIOV_RX_RINGS_OFFSET
- ADF_C3XXXIOV_TX_RINGS_MASK
- ADF_C3XXXIOV_VINTMSK_OFFSET
- ADF_C3XXXVF_DEVICE_NAME
- ADF_C3XXXVF_HW_DATA_H_
- ADF_C3XXX_ACCELENGINES_MASK
- ADF_C3XXX_ACCELERATORS_MASK
- ADF_C3XXX_ACCELERATORS_REG_OFFSET
- ADF_C3XXX_AE_CTX_ENABLES
- ADF_C3XXX_AE_MISC_CONTROL
- ADF_C3XXX_CERRSSMSH
- ADF_C3XXX_DEVICE_NAME
- ADF_C3XXX_ENABLE_AE_ECC_ERR
- ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR
- ADF_C3XXX_ERRSSMSH_EN
- ADF_C3XXX_ETR_BAR
- ADF_C3XXX_ETR_MAX_BANKS
- ADF_C3XXX_FW
- ADF_C3XXX_HW_DATA_H_
- ADF_C3XXX_MAX_ACCELENGINES
- ADF_C3XXX_MAX_ACCELERATORS
- ADF_C3XXX_MMP
- ADF_C3XXX_PCI_DEVICE_ID
- ADF_C3XXX_PF2VF_OFFSET
- ADF_C3XXX_PMISC_BAR
- ADF_C3XXX_RX_RINGS_OFFSET
- ADF_C3XXX_SMIA0_MASK
- ADF_C3XXX_SMIA1_MASK
- ADF_C3XXX_SMIAPF0_MASK_OFFSET
- ADF_C3XXX_SMIAPF1_MASK_OFFSET
- ADF_C3XXX_TX_RINGS_MASK
- ADF_C3XXX_UERRSSMSH
- ADF_C3XXX_VINTMSK_OFFSET
- ADF_C62XIOV_ACCELENGINES_MASK
- ADF_C62XIOV_ACCELERATORS_MASK
- ADF_C62XIOV_ETR_BAR
- ADF_C62XIOV_ETR_MAX_BANKS
- ADF_C62XIOV_MAX_ACCELENGINES
- ADF_C62XIOV_MAX_ACCELERATORS
- ADF_C62XIOV_PCI_DEVICE_ID
- ADF_C62XIOV_PF2VF_OFFSET
- ADF_C62XIOV_PMISC_BAR
- ADF_C62XIOV_RX_RINGS_OFFSET
- ADF_C62XIOV_TX_RINGS_MASK
- ADF_C62XIOV_VINTMSK_OFFSET
- ADF_C62XVF_DEVICE_NAME
- ADF_C62XVF_HW_DATA_H_
- ADF_C62X_ACCELENGINES_MASK
- ADF_C62X_ACCELERATORS_MASK
- ADF_C62X_ACCELERATORS_REG_OFFSET
- ADF_C62X_AE_CTX_ENABLES
- ADF_C62X_AE_MISC_CONTROL
- ADF_C62X_CERRSSMSH
- ADF_C62X_DEVICE_NAME
- ADF_C62X_ENABLE_AE_ECC_ERR
- ADF_C62X_ENABLE_AE_ECC_PARITY_CORR
- ADF_C62X_ERRSSMSH_EN
- ADF_C62X_ETR_BAR
- ADF_C62X_ETR_MAX_BANKS
- ADF_C62X_FW
- ADF_C62X_HW_DATA_H_
- ADF_C62X_MAX_ACCELENGINES
- ADF_C62X_MAX_ACCELERATORS
- ADF_C62X_MMP
- ADF_C62X_PCI_DEVICE_ID
- ADF_C62X_PF2VF_OFFSET
- ADF_C62X_PMISC_BAR
- ADF_C62X_RX_RINGS_OFFSET
- ADF_C62X_SMIA0_MASK
- ADF_C62X_SMIA1_MASK
- ADF_C62X_SMIAPF0_MASK_OFFSET
- ADF_C62X_SMIAPF1_MASK_OFFSET
- ADF_C62X_SRAM_BAR
- ADF_C62X_TX_RINGS_MASK
- ADF_C62X_UERRSSMSH
- ADF_C62X_VINTMSK_OFFSET
- ADF_CFG_AFFINITY_WHATEVER
- ADF_CFG_ALL_DEVICES
- ADF_CFG_BASE_DEC
- ADF_CFG_BASE_HEX
- ADF_CFG_COMMON_H_
- ADF_CFG_H_
- ADF_CFG_MAX_KEY_LEN_IN_BYTES
- ADF_CFG_MAX_SECTION_LEN_IN_BYTES
- ADF_CFG_MAX_STR_LEN
- ADF_CFG_MAX_VAL_LEN_IN_BYTES
- ADF_CFG_NO_DEVICE
- ADF_CFG_STRINGS_H_
- ADF_CFG_USER_H_
- ADF_COALESCING_DEF_TIME
- ADF_COALESCING_MAX_TIME
- ADF_COALESCING_MIN_TIME
- ADF_CODE
- ADF_CSR_RD
- ADF_CSR_WR
- ADF_CTL_IOC_MAGIC
- ADF_CY
- ADF_DC
- ADF_DEC
- ADF_DEFAULT_RING_SIZE
- ADF_DEVICE_FUSECTL_MASK
- ADF_DEVICE_FUSECTL_OFFSET
- ADF_DEVICE_LEGFUSE_OFFSET
- ADF_DEVICE_NAME_LENGTH
- ADF_DEVICE_NAME_PREFIX
- ADF_DEVS_ARRAY_SIZE
- ADF_DEV_RESET_ASYNC
- ADF_DEV_RESET_SYNC
- ADF_DH895XCCIOV_ACCELENGINES_MASK
- ADF_DH895XCCIOV_ACCELERATORS_MASK
- ADF_DH895XCCIOV_ETR_BAR
- ADF_DH895XCCIOV_ETR_MAX_BANKS
- ADF_DH895XCCIOV_MAX_ACCELENGINES
- ADF_DH895XCCIOV_MAX_ACCELERATORS
- ADF_DH895XCCIOV_PCI_DEVICE_ID
- ADF_DH895XCCIOV_PF2VF_OFFSET
- ADF_DH895XCCIOV_PMISC_BAR
- ADF_DH895XCCIOV_RX_RINGS_OFFSET
- ADF_DH895XCCIOV_TX_RINGS_MASK
- ADF_DH895XCCIOV_VINTMSK_OFFSET
- ADF_DH895XCCVF_DEVICE_NAME
- ADF_DH895XCC_ACCELENGINES_MASK
- ADF_DH895XCC_ACCELERATORS_MASK
- ADF_DH895XCC_ACCELERATORS_REG_OFFSET
- ADF_DH895XCC_ADMINMSGLR_OFFSET
- ADF_DH895XCC_ADMINMSGUR_OFFSET
- ADF_DH895XCC_AE_CTX_ENABLES
- ADF_DH895XCC_AE_MISC_CONTROL
- ADF_DH895XCC_CERRSSMSH
- ADF_DH895XCC_DEVICE_NAME
- ADF_DH895XCC_ENABLE_AE_ECC_ERR
- ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR
- ADF_DH895XCC_EP_OFFSET
- ADF_DH895XCC_ERRMSK3
- ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK
- ADF_DH895XCC_ERRMSK5
- ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK
- ADF_DH895XCC_ERRSSMSH_EN
- ADF_DH895XCC_ETR_BAR
- ADF_DH895XCC_ETR_MAX_BANKS
- ADF_DH895XCC_FUSECTL_SKU_1
- ADF_DH895XCC_FUSECTL_SKU_2
- ADF_DH895XCC_FUSECTL_SKU_3
- ADF_DH895XCC_FUSECTL_SKU_4
- ADF_DH895XCC_FUSECTL_SKU_MASK
- ADF_DH895XCC_FUSECTL_SKU_SHIFT
- ADF_DH895XCC_FW
- ADF_DH895XCC_MAILBOX_BASE_OFFSET
- ADF_DH895XCC_MAILBOX_STRIDE
- ADF_DH895XCC_MAX_ACCELENGINES
- ADF_DH895XCC_MAX_ACCELERATORS
- ADF_DH895XCC_MMP
- ADF_DH895XCC_PCI_DEVICE_ID
- ADF_DH895XCC_PF2VF_OFFSET
- ADF_DH895XCC_PMISC_BAR
- ADF_DH895XCC_RX_RINGS_OFFSET
- ADF_DH895XCC_SMIA0_MASK
- ADF_DH895XCC_SMIA1_MASK
- ADF_DH895XCC_SMIAPF0_MASK_OFFSET
- ADF_DH895XCC_SMIAPF1_MASK_OFFSET
- ADF_DH895XCC_SRAM_BAR
- ADF_DH895XCC_TX_RINGS_MASK
- ADF_DH895XCC_UERRSSMSH
- ADF_DH895XCC_VINTMSK_OFFSET
- ADF_DH895XVF_HW_DATA_H_
- ADF_DH895x_HW_DATA_H_
- ADF_DRV_H
- ADF_DRV_VERSION
- ADF_ERRSOU3
- ADF_ERRSOU5
- ADF_ETRMGR_BANK
- ADF_ETRMGR_COALESCE_TIMER
- ADF_ETRMGR_COALESCE_TIMER_FORMAT
- ADF_ETRMGR_COALESCING_ENABLED
- ADF_ETRMGR_COALESCING_ENABLED_FORMAT
- ADF_ETRMGR_COALESCING_MSG_ENABLED
- ADF_ETRMGR_COALESCING_MSG_ENABLED_FORMAT
- ADF_ETRMGR_CORE_AFFINITY
- ADF_ETRMGR_CORE_AFFINITY_FORMAT
- ADF_ETR_MAX_RINGS_PER_BANK
- ADF_EVENT_INIT
- ADF_EVENT_RESTARTED
- ADF_EVENT_RESTARTING
- ADF_EVENT_SHUTDOWN
- ADF_EVENT_START
- ADF_EVENT_STOP
- ADF_GENERAL_SEC
- ADF_HEX
- ADF_IOV_MSG_ACK_DELAY
- ADF_IOV_MSG_ACK_MAX_RETRY
- ADF_IOV_MSG_COLLISION_DETECT_DELAY
- ADF_IOV_MSG_MAX_RETRIES
- ADF_IOV_MSG_RESP_TIMEOUT
- ADF_IOV_MSG_RETRY_DELAY
- ADF_KERNEL_SEC
- ADF_MAJOR_VERSION
- ADF_MAX_DEVICES
- ADF_MAX_INFLIGHTS
- ADF_MAX_MSG_SIZE
- ADF_MAX_MSIX_VECTOR_NAME
- ADF_MAX_RING_SIZE
- ADF_MINOR_VERSION
- ADF_MIN_MSG_SIZE
- ADF_MIN_RING_SIZE
- ADF_MSG_SIZE_128
- ADF_MSG_SIZE_32
- ADF_MSG_SIZE_64
- ADF_MSG_SIZE_TO_BYTES
- ADF_NUM_CY
- ADF_NUM_DC
- ADF_PCI_MAX_BARS
- ADF_PF2VF_INT
- ADF_PF2VF_IN_USE_BY_PF
- ADF_PF2VF_IN_USE_BY_PF_MASK
- ADF_PF2VF_MAJORVERSION_SHIFT
- ADF_PF2VF_MINORVERSION_SHIFT
- ADF_PF2VF_MSGORIGIN_SYSTEM
- ADF_PF2VF_MSGTYPE_MASK
- ADF_PF2VF_MSGTYPE_RESTARTING
- ADF_PF2VF_MSGTYPE_SHIFT
- ADF_PF2VF_MSGTYPE_VERSION_RESP
- ADF_PF2VF_MSG_H
- ADF_PF2VF_VERSION_RESP_RESULT_MASK
- ADF_PF2VF_VERSION_RESP_RESULT_SHIFT
- ADF_PF2VF_VERSION_RESP_VERS_MASK
- ADF_PF2VF_VERSION_RESP_VERS_SHIFT
- ADF_PF2VF_VF_COMPATIBLE
- ADF_PF2VF_VF_COMPAT_UNKNOWN
- ADF_PF2VF_VF_INCOMPATIBLE
- ADF_PFVF_COMPATIBILITY_VERSION
- ADF_PLUS_EISA
- ADF_PLUS_ISA
- ADF_RING_ASYM_RX
- ADF_RING_ASYM_SIZE
- ADF_RING_ASYM_TX
- ADF_RING_BANK_NUM
- ADF_RING_BUNDLE_SIZE
- ADF_RING_CONFIG_NEAR_EMPTY_WM
- ADF_RING_CONFIG_NEAR_FULL_WM
- ADF_RING_CSR_E_STAT
- ADF_RING_CSR_INT_COL_CTL
- ADF_RING_CSR_INT_COL_CTL_ENABLE
- ADF_RING_CSR_INT_COL_EN
- ADF_RING_CSR_INT_FLAG
- ADF_RING_CSR_INT_FLAG_AND_COL
- ADF_RING_CSR_INT_SRCSEL
- ADF_RING_CSR_INT_SRCSEL_2
- ADF_RING_CSR_RING_CONFIG
- ADF_RING_CSR_RING_HEAD
- ADF_RING_CSR_RING_LBASE
- ADF_RING_CSR_RING_TAIL
- ADF_RING_CSR_RING_UBASE
- ADF_RING_DC_RX
- ADF_RING_DC_SIZE
- ADF_RING_DC_TX
- ADF_RING_EMPTY_SIG
- ADF_RING_NEAR_WATERMARK_0
- ADF_RING_NEAR_WATERMARK_512
- ADF_RING_SIZE_128
- ADF_RING_SIZE_16K
- ADF_RING_SIZE_256
- ADF_RING_SIZE_4K
- ADF_RING_SIZE_4M
- ADF_RING_SIZE_512
- ADF_RING_SIZE_BYTES_MIN
- ADF_RING_SIZE_IN_BYTES_TO_SIZE
- ADF_RING_SIZE_MODULO
- ADF_RING_SYM_RX
- ADF_RING_SYM_SIZE
- ADF_RING_SYM_TX
- ADF_SC3_EISA
- ADF_SC3_ISA
- ADF_SC3_PCI
- ADF_SC4_EISA
- ADF_SC4_ISA
- ADF_SC4_PCI
- ADF_SC5_PCI
- ADF_SIZE_TO_POW
- ADF_SIZE_TO_RING_SIZE_IN_BYTES
- ADF_STATUS_AE_INITIALISED
- ADF_STATUS_AE_STARTED
- ADF_STATUS_AE_UCODE_LOADED
- ADF_STATUS_CONFIGURED
- ADF_STATUS_IRQ_ALLOCATED
- ADF_STATUS_PF_RUNNING
- ADF_STATUS_RESTARTING
- ADF_STATUS_STARTED
- ADF_STATUS_STARTING
- ADF_STR
- ADF_SYSTEM_DEVICE
- ADF_TRANSPORT_ACCESS_MACROS_H
- ADF_TRANSPORT_H
- ADF_TRANSPORT_INTRN_H
- ADF_VF2PF_COMPAT_VER_REQ_SHIFT
- ADF_VF2PF_INT
- ADF_VF2PF_IN_USE_BY_VF
- ADF_VF2PF_IN_USE_BY_VF_MASK
- ADF_VF2PF_MSGORIGIN_SYSTEM
- ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ
- ADF_VF2PF_MSGTYPE_INIT
- ADF_VF2PF_MSGTYPE_MASK
- ADF_VF2PF_MSGTYPE_SHIFT
- ADF_VF2PF_MSGTYPE_SHUTDOWN
- ADF_VF2PF_MSGTYPE_VERSION_REQ
- ADF_VINTSOU_BUN
- ADF_VINTSOU_OFFSET
- ADF_VINTSOU_PF2VF
- ADG792A_DISABLE
- ADG792A_DISABLE_ALL
- ADG792A_LDSW
- ADG792A_MUX
- ADG792A_MUX_ALL
- ADG792A_RESETB
- ADGS1408
- ADGS1408_DISABLE
- ADGS1408_MUX
- ADGS1408_REG_READ
- ADGS1408_SW_DATA
- ADGS1409
- ADH5
- ADH6
- ADHOC
- ADHOCMODE
- ADHOC_COALESCED
- ADHOC_CREATOR
- ADHOC_IDLE
- ADHOC_JOINED
- ADHOC_MODE
- ADHOC_NETWORK
- ADHOC_STARTED
- ADI930
- ADI930_FIRMWARE
- ADI930_PID_PREFIRM
- ADI930_PID_PSTFIRM
- ADICHS0_B_MARK
- ADICHS0_MARK
- ADICHS1_B_MARK
- ADICHS1_MARK
- ADICHS2_B_MARK
- ADICHS2_MARK
- ADICLK_B_MARK
- ADICLK_MARK
- ADICS_B_SAMP_B_MARK
- ADICS_SAMP_B_MARK
- ADICS_SAMP_MARK
- ADIDATA_B_MARK
- ADIDATA_MARK
- ADIN1300_AUTO_MDI_EN
- ADIN1300_CLOCK_STOP_REG
- ADIN1300_DOWNSPEEDS_EN
- ADIN1300_DOWNSPEED_AN_100_EN
- ADIN1300_DOWNSPEED_AN_10_EN
- ADIN1300_DOWNSPEED_RETRIES_MSK
- ADIN1300_EEE_ADV_REG
- ADIN1300_EEE_CAP_REG
- ADIN1300_EEE_LPABLE_REG
- ADIN1300_GE_RGMII_CFG_REG
- ADIN1300_GE_RGMII_EN
- ADIN1300_GE_RGMII_GTX_MSK
- ADIN1300_GE_RGMII_GTX_SEL
- ADIN1300_GE_RGMII_RXID_EN
- ADIN1300_GE_RGMII_RX_MSK
- ADIN1300_GE_RGMII_RX_SEL
- ADIN1300_GE_RGMII_TXID_EN
- ADIN1300_GE_RMII_CFG_REG
- ADIN1300_GE_RMII_EN
- ADIN1300_GE_RMII_FIFO_DEPTH_MSK
- ADIN1300_GE_RMII_FIFO_DEPTH_SEL
- ADIN1300_GE_SOFT_RESET
- ADIN1300_GE_SOFT_RESET_REG
- ADIN1300_GROUP_MDIO_EN
- ADIN1300_INT_ANEG_PAGE_RX_EN
- ADIN1300_INT_ANEG_STAT_CHNG_EN
- ADIN1300_INT_HW_IRQ_EN
- ADIN1300_INT_IDLE_ERR_CNT_EN
- ADIN1300_INT_LINK_STAT_CHNG_EN
- ADIN1300_INT_MAC_FIFO_OU_EN
- ADIN1300_INT_MASK_EN
- ADIN1300_INT_MASK_REG
- ADIN1300_INT_MDIO_SYNC_EN
- ADIN1300_INT_RX_STAT_CHNG_EN
- ADIN1300_INT_SPEED_CHNG_EN
- ADIN1300_INT_STATUS_REG
- ADIN1300_LINKING_EN
- ADIN1300_LPI_WAKE_ERR_CNT_REG
- ADIN1300_MAN_MDIX_EN
- ADIN1300_MII_EXT_REG_DATA
- ADIN1300_MII_EXT_REG_PTR
- ADIN1300_NRG_PD_EN
- ADIN1300_NRG_PD_STATUS
- ADIN1300_NRG_PD_TX_EN
- ADIN1300_PAIR_01_SWAP
- ADIN1300_PHY_CTRL1
- ADIN1300_PHY_CTRL2
- ADIN1300_PHY_CTRL3
- ADIN1300_PHY_CTRL_STATUS2
- ADIN1300_PHY_STATUS1
- ADIN1300_RGMII_1_60_NS
- ADIN1300_RGMII_1_80_NS
- ADIN1300_RGMII_2_00_NS
- ADIN1300_RGMII_2_20_NS
- ADIN1300_RGMII_2_40_NS
- ADIN1300_RMII_12_BITS
- ADIN1300_RMII_16_BITS
- ADIN1300_RMII_20_BITS
- ADIN1300_RMII_24_BITS
- ADIN1300_RMII_4_BITS
- ADIN1300_RMII_8_BITS
- ADIN1300_RX_ERR_CNT
- ADIS16080_DIN_AIN1
- ADIS16080_DIN_AIN2
- ADIS16080_DIN_GYRO
- ADIS16080_DIN_TEMP
- ADIS16080_DIN_WRITE
- ADIS16130_CON
- ADIS16130_CON_RD
- ADIS16130_IOP
- ADIS16130_IOP_ALL_RDY
- ADIS16130_IOP_SYNC
- ADIS16130_MODE
- ADIS16130_MODE_24BIT
- ADIS16130_RATECONV
- ADIS16130_RATECS
- ADIS16130_RATECS_EN
- ADIS16130_RATEDATA
- ADIS16130_TEMPCONV
- ADIS16130_TEMPCS
- ADIS16130_TEMPCS_EN
- ADIS16130_TEMPDATA
- ADIS16136_DIAG_STAT_FLASH_CHKSUM_FAIL
- ADIS16136_DIAG_STAT_FLASH_UPDATE_FAIL
- ADIS16136_DIAG_STAT_SELF_TEST_FAIL
- ADIS16136_DIAG_STAT_SPI_FAIL
- ADIS16136_MSC_CTRL_MEMORY_TEST
- ADIS16136_MSC_CTRL_SELF_TEST
- ADIS16136_REG_ALM_CTRL
- ADIS16136_REG_ALM_MAG1
- ADIS16136_REG_ALM_MAG2
- ADIS16136_REG_ALM_SAMPL1
- ADIS16136_REG_ALM_SAMPL2
- ADIS16136_REG_AVG_CNT
- ADIS16136_REG_DEC_RATE
- ADIS16136_REG_DIAG_STAT
- ADIS16136_REG_FLASH_CNT
- ADIS16136_REG_GLOB_CMD
- ADIS16136_REG_GPIO_CTRL
- ADIS16136_REG_GYRO_OFF
- ADIS16136_REG_GYRO_OFF2
- ADIS16136_REG_GYRO_OUT
- ADIS16136_REG_GYRO_OUT2
- ADIS16136_REG_LOT1
- ADIS16136_REG_LOT2
- ADIS16136_REG_LOT3
- ADIS16136_REG_MSC_CTRL
- ADIS16136_REG_PROD_ID
- ADIS16136_REG_SERIAL_NUM
- ADIS16136_REG_SLP_CTRL
- ADIS16136_REG_SMPL_PRD
- ADIS16136_REG_TEMP_OUT
- ADIS16136_SCAN_GYRO
- ADIS16136_SCAN_TEMP
- ADIS16201_ALM_CTRL_REG
- ADIS16201_ALM_MAG1_REG
- ADIS16201_ALM_MAG2_REG
- ADIS16201_ALM_SMPL1_REG
- ADIS16201_ALM_SMPL2_REG
- ADIS16201_AUX_ADC_REG
- ADIS16201_AUX_DAC_REG
- ADIS16201_AVG_CNT_REG
- ADIS16201_DIAG_STAT_ALARM1
- ADIS16201_DIAG_STAT_ALARM2
- ADIS16201_DIAG_STAT_FLASH_UPT_FAIL_BIT
- ADIS16201_DIAG_STAT_POWER_HIGH_BIT
- ADIS16201_DIAG_STAT_POWER_LOW_BIT
- ADIS16201_DIAG_STAT_REG
- ADIS16201_DIAG_STAT_SPI_FAIL_BIT
- ADIS16201_ERROR_ACTIVE
- ADIS16201_FLASH_CNT
- ADIS16201_GLOB_CMD_FACTORY_RESET
- ADIS16201_GLOB_CMD_REG
- ADIS16201_GLOB_CMD_SW_RESET
- ADIS16201_GPIO_CTRL_REG
- ADIS16201_MSC_CTRL_ACTIVE_DATA_RDY_HIGH
- ADIS16201_MSC_CTRL_DATA_RDY_DIO1
- ADIS16201_MSC_CTRL_DATA_RDY_EN
- ADIS16201_MSC_CTRL_REG
- ADIS16201_MSC_CTRL_SELF_TEST_EN
- ADIS16201_SCAN_ACC_X
- ADIS16201_SCAN_ACC_Y
- ADIS16201_SCAN_AUX_ADC
- ADIS16201_SCAN_INCLI_X
- ADIS16201_SCAN_INCLI_Y
- ADIS16201_SCAN_SUPPLY
- ADIS16201_SCAN_TEMP
- ADIS16201_SLP_CNT_REG
- ADIS16201_SMPL_PRD_REG
- ADIS16201_STARTUP_DELAY_MS
- ADIS16201_SUPPLY_OUT_REG
- ADIS16201_TEMP_OUT_REG
- ADIS16201_XACCL_OFFS_REG
- ADIS16201_XACCL_OUT_REG
- ADIS16201_XACCL_SCALE_REG
- ADIS16201_XINCL_OFFS_REG
- ADIS16201_XINCL_OUT_REG
- ADIS16201_XINCL_SCALE_REG
- ADIS16201_YACCL_OFFS_REG
- ADIS16201_YACCL_OUT_REG
- ADIS16201_YACCL_SCALE_REG
- ADIS16201_YINCL_OFFS_REG
- ADIS16201_YINCL_OUT_REG
- ADIS16201_YINCL_SCALE_REG
- ADIS16203_ALM_CTRL
- ADIS16203_ALM_MAG1
- ADIS16203_ALM_MAG2
- ADIS16203_ALM_SMPL1
- ADIS16203_ALM_SMPL2
- ADIS16203_AUX_ADC
- ADIS16203_AUX_DAC
- ADIS16203_AVG_CNT
- ADIS16203_DIAG_STAT
- ADIS16203_DIAG_STAT_ALARM1
- ADIS16203_DIAG_STAT_ALARM2
- ADIS16203_DIAG_STAT_FLASH_UPT_BIT
- ADIS16203_DIAG_STAT_POWER_HIGH_BIT
- ADIS16203_DIAG_STAT_POWER_LOW_BIT
- ADIS16203_DIAG_STAT_SELFTEST_FAIL_BIT
- ADIS16203_DIAG_STAT_SPI_FAIL_BIT
- ADIS16203_ERROR_ACTIVE
- ADIS16203_FLASH_CNT
- ADIS16203_GLOB_CMD
- ADIS16203_GLOB_CMD_CLEAR_STAT
- ADIS16203_GLOB_CMD_FACTORY_CAL
- ADIS16203_GLOB_CMD_SW_RESET
- ADIS16203_GPIO_CTRL
- ADIS16203_INCL_NULL
- ADIS16203_MSC_CTRL
- ADIS16203_MSC_CTRL_ACTIVE_HIGH
- ADIS16203_MSC_CTRL_DATA_RDY_DIO1
- ADIS16203_MSC_CTRL_DATA_RDY_EN
- ADIS16203_MSC_CTRL_PWRUP_SELF_TEST
- ADIS16203_MSC_CTRL_REVERSE_ROT_EN
- ADIS16203_MSC_CTRL_SELF_TEST_EN
- ADIS16203_SCAN_AUX_ADC
- ADIS16203_SCAN_INCLI_X
- ADIS16203_SCAN_INCLI_Y
- ADIS16203_SCAN_SUPPLY
- ADIS16203_SCAN_TEMP
- ADIS16203_SLP_CNT
- ADIS16203_SMPL_PRD
- ADIS16203_STARTUP_DELAY
- ADIS16203_SUPPLY_OUT
- ADIS16203_TEMP_OUT
- ADIS16203_XINCL_OUT
- ADIS16203_YINCL_OUT
- ADIS16209_ALM_CTRL_REG
- ADIS16209_ALM_MAG1_REG
- ADIS16209_ALM_MAG2_REG
- ADIS16209_ALM_SMPL1_REG
- ADIS16209_ALM_SMPL2_REG
- ADIS16209_AUX_ADC_REG
- ADIS16209_AUX_DAC_REG
- ADIS16209_AVG_CNT_REG
- ADIS16209_CMD_CLEAR_STAT
- ADIS16209_CMD_FACTORY_CAL
- ADIS16209_CMD_REG
- ADIS16209_CMD_SW_RESET
- ADIS16209_ERROR_ACTIVE
- ADIS16209_FLASH_CNT_REG
- ADIS16209_GPIO_CTRL_REG
- ADIS16209_MSC_CTRL_ACTIVE_HIGH
- ADIS16209_MSC_CTRL_DATA_RDY_DIO2
- ADIS16209_MSC_CTRL_DATA_RDY_EN
- ADIS16209_MSC_CTRL_PWRUP_SELF_TEST
- ADIS16209_MSC_CTRL_REG
- ADIS16209_MSC_CTRL_SELF_TEST_EN
- ADIS16209_ROT_NULL_REG
- ADIS16209_ROT_OUT_REG
- ADIS16209_SCAN_ACC_X
- ADIS16209_SCAN_ACC_Y
- ADIS16209_SCAN_AUX_ADC
- ADIS16209_SCAN_INCLI_X
- ADIS16209_SCAN_INCLI_Y
- ADIS16209_SCAN_ROT
- ADIS16209_SCAN_SUPPLY
- ADIS16209_SCAN_TEMP
- ADIS16209_SLP_CNT_REG
- ADIS16209_SMPL_PRD_REG
- ADIS16209_STARTUP_DELAY_MS
- ADIS16209_STAT_ALARM1
- ADIS16209_STAT_ALARM2
- ADIS16209_STAT_FLASH_UPT_FAIL_BIT
- ADIS16209_STAT_POWER_HIGH_BIT
- ADIS16209_STAT_POWER_LOW_BIT
- ADIS16209_STAT_REG
- ADIS16209_STAT_SELFTEST_FAIL_BIT
- ADIS16209_STAT_SPI_FAIL_BIT
- ADIS16209_SUPPLY_OUT_REG
- ADIS16209_TEMP_OUT_REG
- ADIS16209_XACCL_NULL_REG
- ADIS16209_XACCL_OUT_REG
- ADIS16209_XINCL_NULL_REG
- ADIS16209_XINCL_OUT_REG
- ADIS16209_YACCL_NULL_REG
- ADIS16209_YACCL_OUT_REG
- ADIS16209_YINCL_NULL_REG
- ADIS16209_YINCL_OUT_REG
- ADIS16240_ALM_CTRL
- ADIS16240_ALM_MAG1
- ADIS16240_ALM_MAG2
- ADIS16240_AUX_ADC
- ADIS16240_CAPT_BUF1
- ADIS16240_CAPT_BUF2
- ADIS16240_CAPT_CTRL
- ADIS16240_CAPT_PNTR
- ADIS16240_CHK_SUM
- ADIS16240_CLK_DATE
- ADIS16240_CLK_TIME
- ADIS16240_CLK_YEAR
- ADIS16240_DIAG_STAT
- ADIS16240_DIAG_STAT_ALARM1
- ADIS16240_DIAG_STAT_ALARM2
- ADIS16240_DIAG_STAT_CHKSUM
- ADIS16240_DIAG_STAT_CPT_BUF_FUL
- ADIS16240_DIAG_STAT_FLASH_UPT_BIT
- ADIS16240_DIAG_STAT_POWER_HIGH_BIT
- ADIS16240_DIAG_STAT_POWER_LOW_BIT
- ADIS16240_DIAG_STAT_PWRON_BUSY
- ADIS16240_DIAG_STAT_PWRON_FAIL_BIT
- ADIS16240_DIAG_STAT_SPI_FAIL_BIT
- ADIS16240_ERROR_ACTIVE
- ADIS16240_EVNT_CNTR
- ADIS16240_FLASH_CNT
- ADIS16240_GLOB_CMD
- ADIS16240_GLOB_CMD_RESUME
- ADIS16240_GLOB_CMD_STANDBY
- ADIS16240_GLOB_CMD_SW_RESET
- ADIS16240_GPIO_CTRL
- ADIS16240_MSC_CTRL
- ADIS16240_MSC_CTRL_ACTIVE_HIGH
- ADIS16240_MSC_CTRL_DATA_RDY_DIO2
- ADIS16240_MSC_CTRL_DATA_RDY_EN
- ADIS16240_MSC_CTRL_SELF_TEST_EN
- ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN
- ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN
- ADIS16240_SCAN_ACC_X
- ADIS16240_SCAN_ACC_Y
- ADIS16240_SCAN_ACC_Z
- ADIS16240_SCAN_AUX_ADC
- ADIS16240_SCAN_SUPPLY
- ADIS16240_SCAN_TEMP
- ADIS16240_SMPL_PRD
- ADIS16240_STARTUP_DELAY
- ADIS16240_SUPPLY_OUT
- ADIS16240_TEMP_OUT
- ADIS16240_WAKE_DATE
- ADIS16240_WAKE_TIME
- ADIS16240_XACCL_OFF
- ADIS16240_XACCL_OUT
- ADIS16240_XPEAK_OUT
- ADIS16240_XTRIG_CTRL
- ADIS16240_XYZPEAK_OUT
- ADIS16240_YACCL_OFF
- ADIS16240_YACCL_OUT
- ADIS16240_YPEAK_OUT
- ADIS16240_ZACCL_OFF
- ADIS16240_ZACCL_OUT
- ADIS16240_ZPEAK_OUT
- ADIS16251
- ADIS16260
- ADIS16260_ALM_CTRL
- ADIS16260_ALM_MAG1
- ADIS16260_ALM_MAG2
- ADIS16260_ALM_SMPL1
- ADIS16260_ALM_SMPL2
- ADIS16260_ANGL_OUT
- ADIS16260_AUX_ADC
- ADIS16260_AUX_DAC
- ADIS16260_DIAG_STAT
- ADIS16260_DIAG_STAT_ALARM1
- ADIS16260_DIAG_STAT_ALARM2
- ADIS16260_DIAG_STAT_FLASH_CHK_BIT
- ADIS16260_DIAG_STAT_FLASH_UPT_BIT
- ADIS16260_DIAG_STAT_OVERFLOW_BIT
- ADIS16260_DIAG_STAT_POWER_HIGH_BIT
- ADIS16260_DIAG_STAT_POWER_LOW_BIT
- ADIS16260_DIAG_STAT_SELF_TEST_BIT
- ADIS16260_DIAG_STAT_SPI_FAIL_BIT
- ADIS16260_ERROR_ACTIVE
- ADIS16260_FLASH_CNT
- ADIS16260_GLOB_CMD
- ADIS16260_GLOB_CMD_AUTO_NULL
- ADIS16260_GLOB_CMD_DAC_LATCH
- ADIS16260_GLOB_CMD_FAC_CALIB
- ADIS16260_GLOB_CMD_FLASH_UPD
- ADIS16260_GLOB_CMD_SW_RESET
- ADIS16260_GPIO_CTRL
- ADIS16260_GYRO_OFF
- ADIS16260_GYRO_OUT
- ADIS16260_GYRO_SCALE
- ADIS16260_LOT_ID1
- ADIS16260_LOT_ID2
- ADIS16260_MSC_CTRL
- ADIS16260_MSC_CTRL_DATA_RDY_DIO2
- ADIS16260_MSC_CTRL_DATA_RDY_EN
- ADIS16260_MSC_CTRL_DATA_RDY_POL_HIGH
- ADIS16260_MSC_CTRL_INT_SELF_TEST
- ADIS16260_MSC_CTRL_MEM_TEST
- ADIS16260_MSC_CTRL_NEG_SELF_TEST
- ADIS16260_MSC_CTRL_POS_SELF_TEST
- ADIS16260_NEW_DATA
- ADIS16260_PROD_ID
- ADIS16260_SCAN_ANGL
- ADIS16260_SCAN_AUX_ADC
- ADIS16260_SCAN_GYRO
- ADIS16260_SCAN_SUPPLY
- ADIS16260_SCAN_TEMP
- ADIS16260_SENS_AVG
- ADIS16260_SERIAL_NUM
- ADIS16260_SLP_CNT
- ADIS16260_SLP_CNT_POWER_OFF
- ADIS16260_SMPL_PRD
- ADIS16260_SMPL_PRD_DIV_MASK
- ADIS16260_SMPL_PRD_TIME_BASE
- ADIS16260_SPI_BURST
- ADIS16260_SPI_FAST
- ADIS16260_SPI_SLOW
- ADIS16260_STARTUP_DELAY
- ADIS16260_SUPPLY_OUT
- ADIS16260_TEMP_OUT
- ADIS16266
- ADIS16300
- ADIS16300_AUX_ADC
- ADIS16300_PITCH_OUT
- ADIS16300_ROLL_OUT
- ADIS16300_SCAN_INCLI_X
- ADIS16300_SCAN_INCLI_Y
- ADIS16334
- ADIS16334_LOT_ID1
- ADIS16334_LOT_ID2
- ADIS16334_RATE_DIV_SHIFT
- ADIS16334_RATE_INT_CLK
- ADIS16334_SERIAL_NUMBER
- ADIS16350
- ADIS16350_SCAN_TEMP_X
- ADIS16350_SCAN_TEMP_Y
- ADIS16350_SCAN_TEMP_Z
- ADIS16350_XTEMP_OUT
- ADIS16350_YTEMP_OUT
- ADIS16350_ZTEMP_OUT
- ADIS16360
- ADIS16362
- ADIS16364
- ADIS16367
- ADIS16375
- ADIS16400
- ADIS16400_ACCEL_CHAN
- ADIS16400_ALM_CTRL
- ADIS16400_ALM_MAG1
- ADIS16400_ALM_MAG2
- ADIS16400_ALM_SMPL1
- ADIS16400_ALM_SMPL2
- ADIS16400_AUX_ADC
- ADIS16400_AUX_ADC_CHAN
- ADIS16400_AUX_DAC
- ADIS16400_BURST_DIAG_STAT
- ADIS16400_DIAG_STAT
- ADIS16400_DIAG_STAT_ALARM1
- ADIS16400_DIAG_STAT_ALARM2
- ADIS16400_DIAG_STAT_FLASH_CHK
- ADIS16400_DIAG_STAT_FLASH_UPT
- ADIS16400_DIAG_STAT_OVERFLOW
- ADIS16400_DIAG_STAT_POWER_HIGH
- ADIS16400_DIAG_STAT_POWER_LOW
- ADIS16400_DIAG_STAT_SELF_TEST
- ADIS16400_DIAG_STAT_SPI_FAIL
- ADIS16400_DIAG_STAT_XACCL_FAIL
- ADIS16400_DIAG_STAT_XGYRO_FAIL
- ADIS16400_DIAG_STAT_YACCL_FAIL
- ADIS16400_DIAG_STAT_YGYRO_FAIL
- ADIS16400_DIAG_STAT_ZACCL_FAIL
- ADIS16400_DIAG_STAT_ZGYRO_FAIL
- ADIS16400_ERROR_ACTIVE
- ADIS16400_FLASH_CNT
- ADIS16400_GLOB_CMD
- ADIS16400_GLOB_CMD_AUTO_NULL
- ADIS16400_GLOB_CMD_DAC_LATCH
- ADIS16400_GLOB_CMD_FAC_CALIB
- ADIS16400_GLOB_CMD_FLASH_UPD
- ADIS16400_GLOB_CMD_P_AUTO_NULL
- ADIS16400_GLOB_CMD_SW_RESET
- ADIS16400_GPIO_CTRL
- ADIS16400_GYRO_CHAN
- ADIS16400_HAS_PROD_ID
- ADIS16400_HAS_SERIAL_NUMBER
- ADIS16400_HAS_SLOW_MODE
- ADIS16400_INCLI_CHAN
- ADIS16400_MAGN_CHAN
- ADIS16400_MOD_TEMP_CHAN
- ADIS16400_MOD_TEMP_NAME_X
- ADIS16400_MOD_TEMP_NAME_Y
- ADIS16400_MOD_TEMP_NAME_Z
- ADIS16400_MSC_CTRL
- ADIS16400_MSC_CTRL_ACCL_ALIGN
- ADIS16400_MSC_CTRL_DATA_RDY_DIO2
- ADIS16400_MSC_CTRL_DATA_RDY_EN
- ADIS16400_MSC_CTRL_DATA_RDY_POL_HIGH
- ADIS16400_MSC_CTRL_GYRO_BIAS
- ADIS16400_MSC_CTRL_INT_SELF_TEST
- ADIS16400_MSC_CTRL_MEM_TEST
- ADIS16400_MSC_CTRL_NEG_SELF_TEST
- ADIS16400_MSC_CTRL_POS_SELF_TEST
- ADIS16400_MTEST_DELAY
- ADIS16400_NEW_DATA
- ADIS16400_NO_BURST
- ADIS16400_PRODUCT_ID
- ADIS16400_SCAN_ACC_X
- ADIS16400_SCAN_ACC_Y
- ADIS16400_SCAN_ACC_Z
- ADIS16400_SCAN_ADC
- ADIS16400_SCAN_BARO
- ADIS16400_SCAN_GYRO_X
- ADIS16400_SCAN_GYRO_Y
- ADIS16400_SCAN_GYRO_Z
- ADIS16400_SCAN_MAGN_X
- ADIS16400_SCAN_MAGN_Y
- ADIS16400_SCAN_MAGN_Z
- ADIS16400_SCAN_SUPPLY
- ADIS16400_SCAN_TIMESTAMP
- ADIS16400_SENS_AVG
- ADIS16400_SLP_CNT
- ADIS16400_SLP_CNT_POWER_OFF
- ADIS16400_SMPL_PRD
- ADIS16400_SMPL_PRD_DIV_MASK
- ADIS16400_SMPL_PRD_TIME_BASE
- ADIS16400_SPI_BURST
- ADIS16400_SPI_FAST
- ADIS16400_SPI_SLOW
- ADIS16400_STARTUP_DELAY
- ADIS16400_SUPPLY_CHAN
- ADIS16400_SUPPLY_OUT
- ADIS16400_TEMP_CHAN
- ADIS16400_TEMP_OUT
- ADIS16400_VOLTAGE_CHAN
- ADIS16400_XACCL_OFF
- ADIS16400_XACCL_OUT
- ADIS16400_XGYRO_OFF
- ADIS16400_XGYRO_OUT
- ADIS16400_XMAGN_HIF
- ADIS16400_XMAGN_OUT
- ADIS16400_XMAGN_SIF
- ADIS16400_YACCL_OFF
- ADIS16400_YACCL_OUT
- ADIS16400_YGYRO_OFF
- ADIS16400_YGYRO_OUT
- ADIS16400_YMAGN_HIF
- ADIS16400_YMAGN_OUT
- ADIS16400_YMAGN_SIF
- ADIS16400_ZACCL_OFF
- ADIS16400_ZACCL_OUT
- ADIS16400_ZGYRO_OFF
- ADIS16400_ZGYRO_OUT
- ADIS16400_ZMAGN_HIF
- ADIS16400_ZMAGN_OUT
- ADIS16400_ZMAGN_SIF
- ADIS16445
- ADIS16448
- ADIS16448_BARO_OUT
- ADIS16448_TEMP_OUT
- ADIS16460_ACCEL_CHANNEL
- ADIS16460_DIAG_STAT_FLASH_MEM
- ADIS16460_DIAG_STAT_FLASH_UPT
- ADIS16460_DIAG_STAT_IN_CLK_OOS
- ADIS16460_DIAG_STAT_OVERRANGE
- ADIS16460_DIAG_STAT_SELF_TEST
- ADIS16460_DIAG_STAT_SPI_COMM
- ADIS16460_GYRO_CHANNEL
- ADIS16460_MOD_CHANNEL
- ADIS16460_REG_CAL_CRC
- ADIS16460_REG_CAL_SGNTR
- ADIS16460_REG_CODE_CRC
- ADIS16460_REG_CODE_SGNTR
- ADIS16460_REG_DEC_RATE
- ADIS16460_REG_DIAG_STAT
- ADIS16460_REG_FLASH_CNT
- ADIS16460_REG_FLTR_CTRL
- ADIS16460_REG_GLOB_CMD
- ADIS16460_REG_LOT_ID1
- ADIS16460_REG_LOT_ID2
- ADIS16460_REG_MSC_CTRL
- ADIS16460_REG_PROD_ID
- ADIS16460_REG_SERIAL_NUM
- ADIS16460_REG_SMPL_CNTR
- ADIS16460_REG_SYNC_SCAL
- ADIS16460_REG_TEMP_OUT
- ADIS16460_REG_X_ACCL_LOW
- ADIS16460_REG_X_ACCL_OFF
- ADIS16460_REG_X_ACCL_OUT
- ADIS16460_REG_X_DELT_ANG
- ADIS16460_REG_X_DELT_VEL
- ADIS16460_REG_X_GYRO_LOW
- ADIS16460_REG_X_GYRO_OFF
- ADIS16460_REG_X_GYRO_OUT
- ADIS16460_REG_Y_ACCL_LOW
- ADIS16460_REG_Y_ACCL_OFF
- ADIS16460_REG_Y_ACCL_OUT
- ADIS16460_REG_Y_DELT_ANG
- ADIS16460_REG_Y_DELT_VEL
- ADIS16460_REG_Y_GYRO_LOW
- ADIS16460_REG_Y_GYRO_OFF
- ADIS16460_REG_Y_GYRO_OUT
- ADIS16460_REG_Z_ACCL_LOW
- ADIS16460_REG_Z_ACCL_OFF
- ADIS16460_REG_Z_ACCL_OUT
- ADIS16460_REG_Z_DELT_ANG
- ADIS16460_REG_Z_DELT_VEL
- ADIS16460_REG_Z_GYRO_LOW
- ADIS16460_REG_Z_GYRO_OFF
- ADIS16460_REG_Z_GYRO_OUT
- ADIS16460_SCAN_ACCEL_X
- ADIS16460_SCAN_ACCEL_Y
- ADIS16460_SCAN_ACCEL_Z
- ADIS16460_SCAN_GYRO_X
- ADIS16460_SCAN_GYRO_Y
- ADIS16460_SCAN_GYRO_Z
- ADIS16460_SCAN_TEMP
- ADIS16460_TEMP_CHANNEL
- ADIS16480
- ADIS16480_ACCEL_CHANNEL
- ADIS16480_CLK_INT
- ADIS16480_CLK_PPS
- ADIS16480_CLK_SYNC
- ADIS16480_DIAG_STAT_BARO_FAIL
- ADIS16480_DIAG_STAT_XACCL_FAIL
- ADIS16480_DIAG_STAT_XGYRO_FAIL
- ADIS16480_DIAG_STAT_XMAGN_FAIL
- ADIS16480_DIAG_STAT_YACCL_FAIL
- ADIS16480_DIAG_STAT_YGYRO_FAIL
- ADIS16480_DIAG_STAT_YMAGN_FAIL
- ADIS16480_DIAG_STAT_ZACCL_FAIL
- ADIS16480_DIAG_STAT_ZGYRO_FAIL
- ADIS16480_DIAG_STAT_ZMAGN_FAIL
- ADIS16480_DRDY_EN
- ADIS16480_DRDY_EN_MSK
- ADIS16480_DRDY_POL
- ADIS16480_DRDY_POL_MSK
- ADIS16480_DRDY_SEL
- ADIS16480_DRDY_SEL_MSK
- ADIS16480_FIR_COEF
- ADIS16480_FIR_COEF_A
- ADIS16480_FIR_COEF_B
- ADIS16480_FIR_COEF_C
- ADIS16480_FIR_COEF_D
- ADIS16480_GYRO_CHANNEL
- ADIS16480_MAGN_CHANNEL
- ADIS16480_MOD_CHANNEL
- ADIS16480_PAGE_SIZE
- ADIS16480_PIN_DIO1
- ADIS16480_PIN_DIO2
- ADIS16480_PIN_DIO3
- ADIS16480_PIN_DIO4
- ADIS16480_PRESSURE_CHANNEL
- ADIS16480_REG
- ADIS16480_REG_ALM_CNFG0
- ADIS16480_REG_ALM_CNFG1
- ADIS16480_REG_ALM_CNFG2
- ADIS16480_REG_ALM_STS
- ADIS16480_REG_BAROM_BIAS
- ADIS16480_REG_BAROM_OUT
- ADIS16480_REG_BR_ALM_MAGN
- ADIS16480_REG_CONFIG
- ADIS16480_REG_DEC_RATE
- ADIS16480_REG_DIAG_STS
- ADIS16480_REG_FILTER_BNK0
- ADIS16480_REG_FILTER_BNK1
- ADIS16480_REG_FIRM_DM
- ADIS16480_REG_FIRM_REV
- ADIS16480_REG_FIRM_Y
- ADIS16480_REG_FLASH_CNT
- ADIS16480_REG_FNCTIO_CTRL
- ADIS16480_REG_GLOB_CMD
- ADIS16480_REG_GPIO_CTRL
- ADIS16480_REG_PAGE_ID
- ADIS16480_REG_PROD_ID
- ADIS16480_REG_SEQ_CNT
- ADIS16480_REG_SERIAL_NUM
- ADIS16480_REG_SLP_CNT
- ADIS16480_REG_SYS_E_FLA
- ADIS16480_REG_TEMP_OUT
- ADIS16480_REG_XA_ALM_MAGN
- ADIS16480_REG_XG_ALM_MAGN
- ADIS16480_REG_XM_ALM_MAGN
- ADIS16480_REG_X_ACCEL_BIAS
- ADIS16480_REG_X_ACCEL_OUT
- ADIS16480_REG_X_ACCEL_SCALE
- ADIS16480_REG_X_DELTAANG_OUT
- ADIS16480_REG_X_DELTAVEL_OUT
- ADIS16480_REG_X_GYRO_BIAS
- ADIS16480_REG_X_GYRO_OUT
- ADIS16480_REG_X_GYRO_SCALE
- ADIS16480_REG_X_HARD_IRON
- ADIS16480_REG_X_MAGN_OUT
- ADIS16480_REG_YA_ALM_MAGN
- ADIS16480_REG_YG_ALM_MAGN
- ADIS16480_REG_YM_ALM_MAGN
- ADIS16480_REG_Y_ACCEL_BIAS
- ADIS16480_REG_Y_ACCEL_OUT
- ADIS16480_REG_Y_ACCEL_SCALE
- ADIS16480_REG_Y_DELTAANG_OUT
- ADIS16480_REG_Y_DELTAVEL_OUT
- ADIS16480_REG_Y_GYRO_BIAS
- ADIS16480_REG_Y_GYRO_OUT
- ADIS16480_REG_Y_GYRO_SCALE
- ADIS16480_REG_Y_HARD_IRON
- ADIS16480_REG_Y_MAGN_OUT
- ADIS16480_REG_ZA_ALM_MAGN
- ADIS16480_REG_ZG_ALM_MAGN
- ADIS16480_REG_ZM_ALM_MAGN
- ADIS16480_REG_Z_ACCEL_BIAS
- ADIS16480_REG_Z_ACCEL_OUT
- ADIS16480_REG_Z_ACCEL_SCALE
- ADIS16480_REG_Z_DELTAANG_OUT
- ADIS16480_REG_Z_DELTAVEL_OUT
- ADIS16480_REG_Z_GYRO_BIAS
- ADIS16480_REG_Z_GYRO_OUT
- ADIS16480_REG_Z_GYRO_SCALE
- ADIS16480_REG_Z_HARD_IRON
- ADIS16480_REG_Z_MAGN_OUT
- ADIS16480_SCAN_ACCEL_X
- ADIS16480_SCAN_ACCEL_Y
- ADIS16480_SCAN_ACCEL_Z
- ADIS16480_SCAN_BARO
- ADIS16480_SCAN_GYRO_X
- ADIS16480_SCAN_GYRO_Y
- ADIS16480_SCAN_GYRO_Z
- ADIS16480_SCAN_MAGN_X
- ADIS16480_SCAN_MAGN_Y
- ADIS16480_SCAN_MAGN_Z
- ADIS16480_SCAN_TEMP
- ADIS16480_SYNC_EN
- ADIS16480_SYNC_EN_MSK
- ADIS16480_SYNC_MODE
- ADIS16480_SYNC_MODE_MSK
- ADIS16480_SYNC_SEL
- ADIS16480_SYNC_SEL_MSK
- ADIS16480_TEMP_CHANNEL
- ADIS16485
- ADIS16488
- ADIS16495_1
- ADIS16495_2
- ADIS16495_3
- ADIS16495_REG_SYNC_SCALE
- ADIS16497_1
- ADIS16497_2
- ADIS16497_3
- ADISC
- ADISC_RJT_RCVD
- ADISC_TMO
- ADIS_ACCEL_CHAN
- ADIS_AUX_ADC_CHAN
- ADIS_GLOB_CMD_SW_RESET
- ADIS_GYRO_CHAN
- ADIS_INCLI_CHAN
- ADIS_MOD_CHAN
- ADIS_MSC_CTRL_DATA_RDY_DIO2
- ADIS_MSC_CTRL_DATA_RDY_EN
- ADIS_MSC_CTRL_DATA_RDY_POL_HIGH
- ADIS_PAGE_SIZE
- ADIS_READ_REG
- ADIS_REG_PAGE_ID
- ADIS_ROT_CHAN
- ADIS_SUPPLY_CHAN
- ADIS_TEMP_CHAN
- ADIS_VOLTAGE_CHAN
- ADIS_WRITE_REG
- ADITHON_CTL_MASK
- ADITHON_CTL_MASK_SFT
- ADITHON_CTL_SFT
- ADITHVAL_CTL_MASK
- ADITHVAL_CTL_MASK_SFT
- ADITHVAL_CTL_SFT
- ADI_AXI_COMMON_H_
- ADI_AXI_PCORE_VER
- ADI_AXI_REG_VERSION
- ADI_BLKSZ
- ADI_DATA_DELAY
- ADI_FIFO_DRAIN_TIMEOUT
- ADI_FLAG_10BIT
- ADI_FLAG_HAT
- ADI_GNICEPLUS_PID
- ADI_GNICE_PID
- ADI_HWSPINLOCK_TIMEOUT
- ADI_HW_CHNS
- ADI_ID_MAX
- ADI_ID_TPD
- ADI_ID_WGP
- ADI_ID_WGPE
- ADI_INIT_DELAY
- ADI_MAX_CNAME_LENGTH
- ADI_MAX_LENGTH
- ADI_MAX_NAME_LENGTH
- ADI_MAX_PHYS_LENGTH
- ADI_MAX_START
- ADI_MAX_STROBE
- ADI_MAX_VERSION
- ADI_MIN_ID_LENGTH
- ADI_MIN_LENGTH
- ADI_MIN_LEN_LENGTH
- ADI_READ_TIMEOUT
- ADI_SLAVE_ADDR_SIZE
- ADI_SLAVE_OFFSET
- ADI_VID
- ADJD_S311_CAP_BLUE
- ADJD_S311_CAP_CLEAR
- ADJD_S311_CAP_GREEN
- ADJD_S311_CAP_MASK
- ADJD_S311_CAP_RED
- ADJD_S311_CAP_REG
- ADJD_S311_CHANNEL
- ADJD_S311_CONFIG
- ADJD_S311_CTRL
- ADJD_S311_CTRL_GOFS
- ADJD_S311_CTRL_GSSR
- ADJD_S311_DATA_BLUE
- ADJD_S311_DATA_CLEAR
- ADJD_S311_DATA_GREEN
- ADJD_S311_DATA_MASK
- ADJD_S311_DATA_RED
- ADJD_S311_DATA_REG
- ADJD_S311_DRV_NAME
- ADJD_S311_INT_BLUE
- ADJD_S311_INT_CLEAR
- ADJD_S311_INT_GREEN
- ADJD_S311_INT_MASK
- ADJD_S311_INT_RED
- ADJD_S311_INT_REG
- ADJD_S311_OFFSET_BLUE
- ADJD_S311_OFFSET_CLEAR
- ADJD_S311_OFFSET_GREEN
- ADJD_S311_OFFSET_RED
- ADJTIME_FIX
- ADJUST
- ADJUST_ADJ_DELAY_MASK
- ADJUST_ADJ_EN
- ADJUST_DISPLAY_CONFIG_SS_ENABLE
- ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
- ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
- ADJUST_DISPLAY_PLL_PARAMETERS
- ADJUST_DISPLAY_PLL_PS_ALLOCATION
- ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
- ADJUST_DS_EN
- ADJUST_MC_SETTING_PARAM
- ADJ_ADJTIME
- ADJ_ESTERROR
- ADJ_FREQUENCY
- ADJ_MAXERROR
- ADJ_MICRO
- ADJ_NANO
- ADJ_OFFSET
- ADJ_OFFSET_READONLY
- ADJ_OFFSET_SINGLESHOT
- ADJ_OFFSET_SS_READ
- ADJ_PWR_TBL_LEN
- ADJ_SETOFFSET
- ADJ_STATUS
- ADJ_TAI
- ADJ_TICK
- ADJ_TIMECONST
- ADK_FAST
- ADK_MFMPREC
- ADK_MSBSYNC
- ADK_PRECOMP0
- ADK_PRECOMP1
- ADK_SETCLR
- ADK_WORDSYNC
- ADLINK_ND6530_PRODUCT_ID
- ADLINK_PCI_DEVICE_ID
- ADLINK_PCI_VENDOR_ID
- ADLINK_VENDOR_ID
- ADM0_C0_RESET
- ADM0_C1_RESET
- ADM0_C2_RESET
- ADM0_CLK
- ADM0_PBUS_CLK
- ADM0_PBUS_RESET
- ADM0_RESET
- ADM1021_REG_CONFIG_R
- ADM1021_REG_CONFIG_W
- ADM1021_REG_CONV_RATE_R
- ADM1021_REG_CONV_RATE_W
- ADM1021_REG_DEV_ID
- ADM1021_REG_MAN_ID
- ADM1021_REG_ONESHOT
- ADM1021_REG_STATUS
- ADM1021_REG_TEMP
- ADM1021_REG_THYST_R
- ADM1021_REG_THYST_W
- ADM1021_REG_TOS_R
- ADM1021_REG_TOS_W
- ADM1023_REG_REM_OFFSET
- ADM1023_REG_REM_OFFSET_PREC
- ADM1023_REG_REM_TEMP_PREC
- ADM1023_REG_REM_THYST_PREC
- ADM1023_REG_REM_TOS_PREC
- ADM1025_REG_CHIP_ID
- ADM1025_REG_CONFIG
- ADM1025_REG_IN
- ADM1025_REG_IN_MAX
- ADM1025_REG_IN_MIN
- ADM1025_REG_MAN_ID
- ADM1025_REG_STATUS1
- ADM1025_REG_STATUS2
- ADM1025_REG_TEMP
- ADM1025_REG_TEMP_HIGH
- ADM1025_REG_TEMP_LOW
- ADM1025_REG_VID
- ADM1025_REG_VID4
- ADM1026_COMPANY_ANALOG_DEV
- ADM1026_CONFIG_INTERVAL
- ADM1026_DATA_INTERVAL
- ADM1026_FAN_ACTIVATION_TEMP_HYST
- ADM1026_FAN_CONTROL_TEMP_RANGE
- ADM1026_PWM_MAX
- ADM1026_REG_COMPANY
- ADM1026_REG_CONFIG1
- ADM1026_REG_CONFIG2
- ADM1026_REG_CONFIG3
- ADM1026_REG_DAC
- ADM1026_REG_E2CONFIG
- ADM1026_REG_FAN
- ADM1026_REG_FAN_DIV_0_3
- ADM1026_REG_FAN_DIV_4_7
- ADM1026_REG_FAN_MIN
- ADM1026_REG_GPIO_CFG_0_3
- ADM1026_REG_GPIO_CFG_12_15
- ADM1026_REG_GPIO_CFG_4_7
- ADM1026_REG_GPIO_CFG_8_11
- ADM1026_REG_GPIO_MASK_0_7
- ADM1026_REG_GPIO_MASK_8_15
- ADM1026_REG_GPIO_STATUS_0_7
- ADM1026_REG_GPIO_STATUS_8_15
- ADM1026_REG_MASK1
- ADM1026_REG_MASK2
- ADM1026_REG_MASK3
- ADM1026_REG_MASK4
- ADM1026_REG_PWM
- ADM1026_REG_STATUS1
- ADM1026_REG_STATUS2
- ADM1026_REG_STATUS3
- ADM1026_REG_STATUS4
- ADM1026_REG_VERSTEP
- ADM1026_VERSTEP_ADM1026
- ADM1026_VERSTEP_GENERIC
- ADM1027_REG_EXTEND_ADC1
- ADM1027_REG_EXTEND_ADC2
- ADM1029_REG_CHIP_ID
- ADM1029_REG_CONFIG
- ADM1029_REG_FAN1
- ADM1029_REG_FAN1_CONFIG
- ADM1029_REG_FAN1_MIN
- ADM1029_REG_FAN2
- ADM1029_REG_FAN2_CONFIG
- ADM1029_REG_FAN2_MIN
- ADM1029_REG_LOCAL_TEMP
- ADM1029_REG_LOCAL_TEMP_HIGH
- ADM1029_REG_LOCAL_TEMP_LOW
- ADM1029_REG_MAN_ID
- ADM1029_REG_NB_FAN_SUPPORT
- ADM1029_REG_REMOTE1_TEMP
- ADM1029_REG_REMOTE1_TEMP_HIGH
- ADM1029_REG_REMOTE1_TEMP_LOW
- ADM1029_REG_REMOTE2_TEMP
- ADM1029_REG_REMOTE2_TEMP_HIGH
- ADM1029_REG_REMOTE2_TEMP_LOW
- ADM1029_REG_TEMP_DEVICES_INSTALLED
- ADM1031_CONF1_AUTO_MODE
- ADM1031_CONF1_MONITOR_ENABLE
- ADM1031_CONF1_PWM_INVERT
- ADM1031_CONF2_PWM1_ENABLE
- ADM1031_CONF2_PWM2_ENABLE
- ADM1031_CONF2_TACH1_ENABLE
- ADM1031_CONF2_TACH2_ENABLE
- ADM1031_CONF2_TEMP_ENABLE
- ADM1031_REG_AUTO_TEMP
- ADM1031_REG_CONF1
- ADM1031_REG_CONF2
- ADM1031_REG_EXT_TEMP
- ADM1031_REG_FAN_DIV
- ADM1031_REG_FAN_FILTER
- ADM1031_REG_FAN_MIN
- ADM1031_REG_FAN_SPEED
- ADM1031_REG_PWM
- ADM1031_REG_STATUS
- ADM1031_REG_TEMP
- ADM1031_REG_TEMP_CRIT
- ADM1031_REG_TEMP_MAX
- ADM1031_REG_TEMP_MIN
- ADM1031_REG_TEMP_OFFSET
- ADM1031_UPDATE_RATE_MASK
- ADM1031_UPDATE_RATE_SHIFT
- ADM1075_IRANGE_25
- ADM1075_IRANGE_50
- ADM1075_IRANGE_MASK
- ADM1075_READ_VAUX
- ADM1075_VAUX_OV_WARN
- ADM1075_VAUX_OV_WARN_LIMIT
- ADM1075_VAUX_STATUS
- ADM1075_VAUX_UV_WARN
- ADM1075_VAUX_UV_WARN_LIMIT
- ADM1272_IRANGE
- ADM1275_DEVICE_CONFIG
- ADM1275_IOUT_WARN2_LIMIT
- ADM1275_IOUT_WARN2_SELECT
- ADM1275_MFR_STATUS_IOUT_WARN2
- ADM1275_PEAK_IOUT
- ADM1275_PEAK_VIN
- ADM1275_PEAK_VOUT
- ADM1275_PMON_CONFIG
- ADM1275_SAMPLES_AVG_MAX
- ADM1275_VIN_VOUT_SELECT
- ADM1275_VI_AVG_MASK
- ADM1275_VI_AVG_SHIFT
- ADM1275_VRANGE
- ADM1276_PEAK_PIN
- ADM1278_PEAK_TEMP
- ADM1278_PWR_AVG_MASK
- ADM1278_PWR_AVG_SHIFT
- ADM1278_TEMP1_EN
- ADM1278_VIN_EN
- ADM1278_VI_AVG_MASK
- ADM1278_VI_AVG_SHIFT
- ADM1278_VOUT_EN
- ADM1293_IOUT_MIN
- ADM1293_IRANGE_100
- ADM1293_IRANGE_200
- ADM1293_IRANGE_25
- ADM1293_IRANGE_50
- ADM1293_IRANGE_MASK
- ADM1293_MFR_STATUS_VAUX_OV_WARN
- ADM1293_MFR_STATUS_VAUX_UV_WARN
- ADM1293_PIN_MIN
- ADM1293_VAUX_EN
- ADM1293_VIN_SEL_012
- ADM1293_VIN_SEL_074
- ADM1293_VIN_SEL_210
- ADM1293_VIN_SEL_MASK
- ADM1_C0_RESET
- ADM1_C1_RESET
- ADM1_C2_RESET
- ADM1_C3_RESET
- ADM1_CLK
- ADM1_PBUS_CLK
- ADM1_PBUS_RESET
- ADM1_RESET
- ADM8211_AL2210L
- ADM8211_BBPCTL_ADDR
- ADM8211_BBPCTL_CCAP
- ADM8211_BBPCTL_DATA
- ADM8211_BBPCTL_MMISEL
- ADM8211_BBPCTL_RD
- ADM8211_BBPCTL_RF3000
- ADM8211_BBPCTL_RXCE
- ADM8211_BBPCTL_SPICADD
- ADM8211_BBPCTL_TXCE
- ADM8211_BBPCTL_TYPE
- ADM8211_BBPCTL_WR
- ADM8211_BBP_ADM8011
- ADM8211_BBP_RFMD3000
- ADM8211_BBP_RFMD3002
- ADM8211_CMDR_APM
- ADM8211_CMDR_DRT
- ADM8211_CMDR_DRT_16DW
- ADM8211_CMDR_DRT_8DW
- ADM8211_CMDR_DRT_SF
- ADM8211_CMDR_PM
- ADM8211_CMDR_RTE
- ADM8211_CSR_GPIO_EN0
- ADM8211_CSR_GPIO_EN1
- ADM8211_CSR_GPIO_EN2
- ADM8211_CSR_GPIO_EN3
- ADM8211_CSR_GPIO_EN4
- ADM8211_CSR_GPIO_EN5
- ADM8211_CSR_GPIO_IN
- ADM8211_CSR_GPIO_O0
- ADM8211_CSR_GPIO_O1
- ADM8211_CSR_GPIO_O2
- ADM8211_CSR_GPIO_O3
- ADM8211_CSR_GPIO_O4
- ADM8211_CSR_GPIO_O5
- ADM8211_CSR_READ
- ADM8211_CSR_TEST0_EPNE
- ADM8211_CSR_TEST0_EPRLD
- ADM8211_CSR_TEST0_EPSNM
- ADM8211_CSR_TEST0_EPTYP
- ADM8211_CSR_WRITE
- ADM8211_FER_INTR_EV_ENT
- ADM8211_FRCTL_AID
- ADM8211_FRCTL_AID_ON
- ADM8211_FRCTL_DRVBCON
- ADM8211_FRCTL_DRVPRSP
- ADM8211_FRCTL_MAXPSP
- ADM8211_FRCTL_PWRMGT
- ADM8211_H
- ADM8211_IDLE
- ADM8211_IDLE_RX
- ADM8211_IER_AIE
- ADM8211_IER_ATIMEIE
- ADM8211_IER_ATIMTCIE
- ADM8211_IER_BCNTCIE
- ADM8211_IER_FBEIE
- ADM8211_IER_GPIE
- ADM8211_IER_GPTIE
- ADM8211_IER_LinkOffIE
- ADM8211_IER_LinkOnIE
- ADM8211_IER_NIE
- ADM8211_IER_PCFIE
- ADM8211_IER_RCIE
- ADM8211_IER_REIE
- ADM8211_IER_RSIE
- ADM8211_IER_RUIE
- ADM8211_IER_SQLIE
- ADM8211_IER_TBTTIE
- ADM8211_IER_TCIE
- ADM8211_IER_TDUIE
- ADM8211_IER_TEIE
- ADM8211_IER_TLTTIE
- ADM8211_IER_TPSIE
- ADM8211_IER_TRTIE
- ADM8211_IER_TSCZE
- ADM8211_IER_TSFTFIE
- ADM8211_IER_TUIE
- ADM8211_IER_WEPIE
- ADM8211_INT
- ADM8211_MAX2820
- ADM8211_NAR_CFP
- ADM8211_NAR_CTX
- ADM8211_NAR_EA
- ADM8211_NAR_HF
- ADM8211_NAR_MM
- ADM8211_NAR_OM
- ADM8211_NAR_PB
- ADM8211_NAR_PR
- ADM8211_NAR_SF
- ADM8211_NAR_SQ
- ADM8211_NAR_SR
- ADM8211_NAR_ST
- ADM8211_NAR_STPDMA
- ADM8211_NAR_TR
- ADM8211_NAR_TXCF
- ADM8211_NAR_UTR
- ADM8211_PAR_BAR
- ADM8211_PAR_BLE
- ADM8211_PAR_CAL
- ADM8211_PAR_DSL
- ADM8211_PAR_MRLE
- ADM8211_PAR_MRME
- ADM8211_PAR_MWIE
- ADM8211_PAR_PBL
- ADM8211_PAR_RAP
- ADM8211_PAR_SWR
- ADM8211_RESTORE
- ADM8211_REV_AB
- ADM8211_REV_AF
- ADM8211_REV_BA
- ADM8211_REV_CA
- ADM8211_RFMD2948
- ADM8211_RFMD2958
- ADM8211_RFMD2958_RF3000_CONTROL_POWER
- ADM8211_SIG1
- ADM8211_SIG2
- ADM8211_SPR_SCLK
- ADM8211_SPR_SCS
- ADM8211_SPR_SDI
- ADM8211_SPR_SDO
- ADM8211_SPR_SRS
- ADM8211_SRAM
- ADM8211_SRAM_A_SHARE_KEY
- ADM8211_SRAM_A_SIZE
- ADM8211_SRAM_A_SSID
- ADM8211_SRAM_A_SUPP_RATE
- ADM8211_SRAM_B_SHARE_KEY
- ADM8211_SRAM_B_SIZE
- ADM8211_SRAM_B_SSID
- ADM8211_SRAM_B_SUPP_RATE
- ADM8211_SRAM_INDIV_KEY
- ADM8211_SRAM_SIZE
- ADM8211_SRAM_SSID
- ADM8211_SRAM_SUPP_RATE
- ADM8211_STSR_AISS
- ADM8211_STSR_ATIME
- ADM8211_STSR_ATIMTC
- ADM8211_STSR_BCNTC
- ADM8211_STSR_FBE
- ADM8211_STSR_GPINT
- ADM8211_STSR_GPTT
- ADM8211_STSR_LinkOff
- ADM8211_STSR_LinkOn
- ADM8211_STSR_NISS
- ADM8211_STSR_PCF
- ADM8211_STSR_RCI
- ADM8211_STSR_RDU
- ADM8211_STSR_REIS
- ADM8211_STSR_RPS
- ADM8211_STSR_SQL
- ADM8211_STSR_TBTT
- ADM8211_STSR_TCI
- ADM8211_STSR_TDU
- ADM8211_STSR_TEIS
- ADM8211_STSR_TLT
- ADM8211_STSR_TPS
- ADM8211_STSR_TRT
- ADM8211_STSR_TSCZ
- ADM8211_STSR_TSFTF
- ADM8211_STSR_TUF
- ADM8211_STSR_WEPTD
- ADM8211_SYNCTL_CAL
- ADM8211_SYNCTL_CS0
- ADM8211_SYNCTL_CS1
- ADM8211_SYNCTL_GENERAL
- ADM8211_SYNCTL_RD
- ADM8211_SYNCTL_RFMD
- ADM8211_SYNCTL_RFtype
- ADM8211_SYNCTL_SELCAL
- ADM8211_SYNCTL_WR
- ADM8211_SYNRF_CAL_EN
- ADM8211_SYNRF_IF_SELECT_0
- ADM8211_SYNRF_IF_SELECT_1
- ADM8211_SYNRF_LEIF
- ADM8211_SYNRF_LERF
- ADM8211_SYNRF_PA_PE
- ADM8211_SYNRF_PE1
- ADM8211_SYNRF_PE2
- ADM8211_SYNRF_PHYRST
- ADM8211_SYNRF_RADIO
- ADM8211_SYNRF_SELRF
- ADM8211_SYNRF_SELSYN
- ADM8211_SYNRF_SYNCLK
- ADM8211_SYNRF_SYNDATA
- ADM8211_SYNRF_TR_SW
- ADM8211_SYNRF_TR_SWN
- ADM8211_SYNRF_WRITE_CLOCK_0
- ADM8211_SYNRF_WRITE_CLOCK_1
- ADM8211_SYNRF_WRITE_SYNDATA_0
- ADM8211_SYNRF_WRITE_SYNDATA_1
- ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER
- ADM8211_TXHDRCTL_ENABLE_RTS
- ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE
- ADM8211_TXHDRCTL_FRAG_NO
- ADM8211_TXHDRCTL_MORE_DATA
- ADM8211_TXHDRCTL_MORE_FRAG
- ADM8211_TXHDRCTL_SHORT_PREAMBLE
- ADM8211_TYPE_ADMTEK
- ADM8211_TYPE_AIROHA
- ADM8211_TYPE_INTERSIL
- ADM8211_TYPE_MARVEL
- ADM8211_TYPE_RFMD
- ADM8211_WCSR_ATIMW
- ADM8211_WCSR_ATIMWE
- ADM8211_WCSR_CRCT
- ADM8211_WCSR_KEYUP
- ADM8211_WCSR_KEYWE
- ADM8211_WCSR_LSO
- ADM8211_WCSR_LSOE
- ADM8211_WCSR_MPR
- ADM8211_WCSR_MPRE
- ADM8211_WCSR_TIMW
- ADM8211_WCSR_TIMWE
- ADM8211_WCSR_TSFTW
- ADM8211_WCSR_TSFTWE
- ADM8211_WEPCTL_ADDR
- ADM8211_WEPCTL_CURRENT_TABLE
- ADM8211_WEPCTL_SEL_WEPTABLE
- ADM8211_WEPCTL_TABLE_RD
- ADM8211_WEPCTL_TABLE_WR
- ADM8211_WEPCTL_WEPENABLE
- ADM8211_WEPCTL_WEPRXBYP
- ADM8211_WEPCTL_WPAENABLE
- ADM8211_WESK_DATA
- ADM9240_REG_ANALOG_OUT
- ADM9240_REG_CHASSIS_CLEAR
- ADM9240_REG_CONFIG
- ADM9240_REG_DIE_REV
- ADM9240_REG_FAN
- ADM9240_REG_FAN_MIN
- ADM9240_REG_I2C_ADDR
- ADM9240_REG_IN
- ADM9240_REG_INT
- ADM9240_REG_INT_MASK
- ADM9240_REG_IN_MAX
- ADM9240_REG_IN_MIN
- ADM9240_REG_MAN_ID
- ADM9240_REG_TEMP
- ADM9240_REG_TEMP_CONF
- ADM9240_REG_TEMP_MAX
- ADM9240_REG_VID4
- ADM9240_REG_VID_FAN_DIV
- ADMA
- ADMA2_END
- ADMA2_NOP_END_VALID
- ADMA2_TRAN_VALID
- ADMAC
- ADMA_ACM_LPCG
- ADMA_ADC_0_LPCG
- ADMA_ADDRESS
- ADMA_AMIX_LPCG
- ADMA_ASRC_0_LPCG
- ADMA_ASRC_1_LPCG
- ADMA_ATA_REGS
- ADMA_B_ADDR
- ADMA_CH_CMD
- ADMA_CH_CONFIG
- ADMA_CH_CONFIG_BURST_SIZE_SHIFT
- ADMA_CH_CONFIG_MAX_BUFS
- ADMA_CH_CONFIG_MAX_BURST_SIZE
- ADMA_CH_CONFIG_SRC_BUF
- ADMA_CH_CONFIG_TRG_BUF
- ADMA_CH_CONFIG_WEIGHT_FOR_WRR
- ADMA_CH_CTRL
- ADMA_CH_CTRL_DIR
- ADMA_CH_CTRL_DIR_AHUB2MEM
- ADMA_CH_CTRL_DIR_MEM2AHUB
- ADMA_CH_CTRL_FLOWCTRL_EN
- ADMA_CH_CTRL_MODE_CONTINUOUS
- ADMA_CH_CTRL_XFER_PAUSE_SHIFT
- ADMA_CH_FIFO_CTRL
- ADMA_CH_INT_CLEAR
- ADMA_CH_INT_STATUS
- ADMA_CH_INT_STATUS_XFER_DONE
- ADMA_CH_LOWER_SRC_ADDR
- ADMA_CH_LOWER_TRG_ADDR
- ADMA_CH_REG_FIELD_VAL
- ADMA_CH_STATUS
- ADMA_CH_STATUS_XFER_EN
- ADMA_CH_STATUS_XFER_PAUSED
- ADMA_CH_TC
- ADMA_CH_TC_COUNT_MASK
- ADMA_CH_XFER_STATUS
- ADMA_CH_XFER_STATUS_COUNT_MASK
- ADMA_CONTROL
- ADMA_CPB_BYTES
- ADMA_CPB_COUNT
- ADMA_CPB_CURRENT
- ADMA_CPB_LOOKUP
- ADMA_CPB_NEXT
- ADMA_DMA_BOUNDARY
- ADMA_EDMA_0_LPCG
- ADMA_EDMA_1_LPCG
- ADMA_ESAI_0_LPCG
- ADMA_FIFO_IN
- ADMA_FIFO_OUT
- ADMA_FIFO_RD_THSHLD
- ADMA_FIFO_WR_THSHLD
- ADMA_FLEXCAN_0_LPCG
- ADMA_FLEXCAN_1_LPCG
- ADMA_FLEXCAN_2_LPCG
- ADMA_FTM_0_LPCG
- ADMA_FTM_1_LPCG
- ADMA_GLOBAL_CMD
- ADMA_GLOBAL_SOFT_RESET
- ADMA_GPT_10_LPCG
- ADMA_GPT_5_LPCG
- ADMA_GPT_6_LPCG
- ADMA_GPT_7_LPCG
- ADMA_GPT_8_LPCG
- ADMA_GPT_9_LPCG
- ADMA_HIFI_LPCG
- ADMA_LCD_LPCG
- ADMA_LL_DBG
- ADMA_LL_DEBUG
- ADMA_LPI2C_0_LPCG
- ADMA_LPI2C_1_LPCG
- ADMA_LPI2C_2_LPCG
- ADMA_LPI2C_3_LPCG
- ADMA_LPSPI_0_LPCG
- ADMA_LPSPI_1_LPCG
- ADMA_LPSPI_2_LPCG
- ADMA_LPSPI_3_LPCG
- ADMA_LPUART_0_LPCG
- ADMA_LPUART_1_LPCG
- ADMA_LPUART_2_LPCG
- ADMA_LPUART_3_LPCG
- ADMA_MCLKOUT0_LPCG
- ADMA_MCLKOUT1_LPCG
- ADMA_MMIO_BAR
- ADMA_MODE
- ADMA_MODE_LOCK
- ADMA_MQS_LPCG
- ADMA_OCRAM_LPCG
- ADMA_PKT_BYTES
- ADMA_PLL_CLK0_LPCG
- ADMA_PLL_CLK1_LPCG
- ADMA_PORTS
- ADMA_PORT_REGS
- ADMA_PRD_BYTES
- ADMA_PWM_LPCG
- ADMA_P_ADDR
- ADMA_REC_CLK0_LPCG
- ADMA_REC_CLK1_LPCG
- ADMA_REF
- ADMA_REGS
- ADMA_REGS_COMMAND
- ADMA_REGS_CONTROL
- ADMA_REGS_DEVICE
- ADMA_REGS_LBA_HIGH
- ADMA_REGS_LBA_LOW
- ADMA_REGS_LBA_MID
- ADMA_REGS_SECTOR_COUNT
- ADMA_SAI_0_LPCG
- ADMA_SAI_1_LPCG
- ADMA_SAI_2_LPCG
- ADMA_SAI_3_LPCG
- ADMA_SAI_4_LPCG
- ADMA_SAI_5_LPCG
- ADMA_SPDIF_0_LPCG
- ADMA_STATUS
- ADMIN_AENQ_SIZE
- ADMIN_CMD_TIMEOUT_US
- ADMIN_CQ_SIZE
- ADMIN_SQ_SIZE
- ADMIN_TIMEOUT
- ADM_CMDRSP_DEVICE_OPEN_V5
- ADM_CMD_DEVICE_CLOSE_V5
- ADM_CMD_DEVICE_OPEN_V5
- ADM_CMD_MATRIX_MAP_ROUTINGS_V5
- ADM_LEGACY_DEVICE_SESSION
- ADM_MATRIX_ID_AUDIO_RX
- ADM_MATRIX_ID_AUDIO_TX
- ADM_PATH_LIVE_REC
- ADM_PATH_PLAYBACK
- ADN2850_ID
- ADN2860_ID
- ADOFF_B
- ADOFF_GB
- ADOFF_GR
- ADOFF_R
- ADP1653_FLASH_INTENSITY_BASE
- ADP1653_FLASH_INTENSITY_MAX
- ADP1653_FLASH_INTENSITY_MIN
- ADP1653_FLASH_INTENSITY_REG_TO_mA
- ADP1653_FLASH_INTENSITY_STEP
- ADP1653_FLASH_INTENSITY_mA_TO_REG
- ADP1653_H
- ADP1653_I2C_ADDR
- ADP1653_INDICATOR_INTENSITY_MAX
- ADP1653_INDICATOR_INTENSITY_MIN
- ADP1653_INDICATOR_INTENSITY_REG_TO_uA
- ADP1653_INDICATOR_INTENSITY_STEP
- ADP1653_INDICATOR_INTENSITY_uA_TO_REG
- ADP1653_NAME
- ADP1653_REG_CONFIG
- ADP1653_REG_CONFIG_TMR_CFG
- ADP1653_REG_CONFIG_TMR_SET_MAX
- ADP1653_REG_CONFIG_TMR_SET_SHIFT
- ADP1653_REG_FAULT
- ADP1653_REG_FAULT_FLT_OT
- ADP1653_REG_FAULT_FLT_OV
- ADP1653_REG_FAULT_FLT_SCP
- ADP1653_REG_FAULT_FLT_TMR
- ADP1653_REG_OUT_SEL
- ADP1653_REG_OUT_SEL_HPLED_FLASH_MAX
- ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN
- ADP1653_REG_OUT_SEL_HPLED_SHIFT
- ADP1653_REG_OUT_SEL_HPLED_TORCH_MAX
- ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN
- ADP1653_REG_OUT_SEL_ILED_MAX
- ADP1653_REG_OUT_SEL_ILED_SHIFT
- ADP1653_REG_SW_STROBE
- ADP1653_REG_SW_STROBE_SW_STROBE
- ADP1653_TORCH_INTENSITY_MAX
- ADP1653_TORCH_INTENSITY_MIN
- ADP5020_MAX_BRIGHTNESS
- ADP5061_BATTERY_SHORT
- ADP5061_CHG_BAT_DET
- ADP5061_CHG_COMPLETE
- ADP5061_CHG_CURR
- ADP5061_CHG_CURR_ICHG_MODE
- ADP5061_CHG_CURR_ICHG_MSK
- ADP5061_CHG_CURR_ITRK_DEAD_MODE
- ADP5061_CHG_CURR_ITRK_DEAD_MSK
- ADP5061_CHG_FAST_CC
- ADP5061_CHG_FAST_CV
- ADP5061_CHG_LDO_MODE
- ADP5061_CHG_OFF
- ADP5061_CHG_STATUS_1
- ADP5061_CHG_STATUS_1_CHDONE
- ADP5061_CHG_STATUS_1_CHG_STATUS
- ADP5061_CHG_STATUS_1_THERM_LIM
- ADP5061_CHG_STATUS_1_VIN_ILIM
- ADP5061_CHG_STATUS_1_VIN_OK
- ADP5061_CHG_STATUS_1_VIN_OV
- ADP5061_CHG_STATUS_2
- ADP5061_CHG_STATUS_2_BAT_STATUS
- ADP5061_CHG_STATUS_2_RCH_LIM_INFO
- ADP5061_CHG_STATUS_2_THR_STATUS
- ADP5061_CHG_TIMER_EXP
- ADP5061_CHG_TRICKLE
- ADP5061_FAULT
- ADP5061_FUNC_SET_1
- ADP5061_FUNC_SET_2
- ADP5061_ICHG_MAX
- ADP5061_ID
- ADP5061_IEND
- ADP5061_IEND_IEND_MODE
- ADP5061_IEND_IEND_MSK
- ADP5061_INT_ACT
- ADP5061_INT_EN
- ADP5061_NO_BATTERY
- ADP5061_REV
- ADP5061_TERM_SET
- ADP5061_TERM_SET_CHG_VLIM_MODE
- ADP5061_TERM_SET_CHG_VLIM_MSK
- ADP5061_TERM_SET_VTRM_MODE
- ADP5061_TERM_SET_VTRM_MSK
- ADP5061_TIMER_SET
- ADP5061_VINX_SET
- ADP5061_VINX_SET_ILIM_MODE
- ADP5061_VINX_SET_ILIM_MSK
- ADP5061_VOLTAGE_TH
- ADP5061_VOLTAGE_TH_DIS_RCH_MODE
- ADP5061_VOLTAGE_TH_DIS_RCH_MSK
- ADP5061_VOLTAGE_TH_VRCH_MODE
- ADP5061_VOLTAGE_TH_VRCH_MSK
- ADP5061_VOLTAGE_TH_VTRK_DEAD_MODE
- ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK
- ADP5061_VOLTAGE_TH_VWEAK_MODE
- ADP5061_VOLTAGE_TH_VWEAK_MSK
- ADP5520_01_MAXLEDS
- ADP5520_ALS_CMPR_CFG
- ADP5520_AUTO_LD_EN
- ADP5520_BL_AMBL_FILT_10240ms
- ADP5520_BL_AMBL_FILT_1280ms
- ADP5520_BL_AMBL_FILT_160ms
- ADP5520_BL_AMBL_FILT_2560ms
- ADP5520_BL_AMBL_FILT_320ms
- ADP5520_BL_AMBL_FILT_5120ms
- ADP5520_BL_AMBL_FILT_640ms
- ADP5520_BL_AMBL_FILT_80ms
- ADP5520_BL_AUTO_ADJ
- ADP5520_BL_CONTROL
- ADP5520_BL_CUR_mA
- ADP5520_BL_EN
- ADP5520_BL_FADE
- ADP5520_BL_LAW
- ADP5520_BL_LAW_CUBIC1
- ADP5520_BL_LAW_CUBIC2
- ADP5520_BL_LAW_LINEAR
- ADP5520_BL_LAW_SQUARE
- ADP5520_BL_LVL
- ADP5520_BL_TIME
- ADP5520_BL_VALUE
- ADP5520_C3_MODE
- ADP5520_CMPR_IEN
- ADP5520_CMPR_INT
- ADP5520_COL_C0
- ADP5520_COL_C1
- ADP5520_COL_C2
- ADP5520_COL_C3
- ADP5520_DARK_DIM
- ADP5520_DARK_MAX
- ADP5520_DAYLIGHT_DIM
- ADP5520_DAYLIGHT_MAX
- ADP5520_DIM_EN
- ADP5520_FADE_T_1200ms
- ADP5520_FADE_T_1500ms
- ADP5520_FADE_T_1800ms
- ADP5520_FADE_T_2100ms
- ADP5520_FADE_T_2400ms
- ADP5520_FADE_T_2700ms
- ADP5520_FADE_T_3000ms
- ADP5520_FADE_T_300ms
- ADP5520_FADE_T_3500ms
- ADP5520_FADE_T_4000ms
- ADP5520_FADE_T_4500ms
- ADP5520_FADE_T_5000ms
- ADP5520_FADE_T_5500ms
- ADP5520_FADE_T_600ms
- ADP5520_FADE_T_900ms
- ADP5520_FADE_T_DIS
- ADP5520_FLAG_LED_MASK
- ADP5520_FLAG_OFFT_MASK
- ADP5520_FLAG_OFFT_SHIFT
- ADP5520_FOVR
- ADP5520_GPIO_C0
- ADP5520_GPIO_C1
- ADP5520_GPIO_C2
- ADP5520_GPIO_C3
- ADP5520_GPIO_CFG_1
- ADP5520_GPIO_CFG_2
- ADP5520_GPIO_DEBOUNCE
- ADP5520_GPIO_IN
- ADP5520_GPIO_INT_EN
- ADP5520_GPIO_INT_LVL
- ADP5520_GPIO_INT_STAT
- ADP5520_GPIO_OUT
- ADP5520_GPIO_PULLUP
- ADP5520_GPIO_R0
- ADP5520_GPIO_R1
- ADP5520_GPIO_R2
- ADP5520_GPIO_R3
- ADP5520_GPI_INT
- ADP5520_INTERRUPT_ENABLE
- ADP5520_KEY
- ADP5520_KEYMAPSIZE
- ADP5520_KEY_STAT_1
- ADP5520_KEY_STAT_2
- ADP5520_KP_BL_EN
- ADP5520_KP_IEN
- ADP5520_KP_INT
- ADP5520_KP_INT_STAT_1
- ADP5520_KP_INT_STAT_2
- ADP5520_KR_IEN
- ADP5520_KR_INT
- ADP5520_KR_INT_STAT_1
- ADP5520_KR_INT_STAT_2
- ADP5520_L2_COMP_CURR_uA
- ADP5520_L2_HYS
- ADP5520_L2_OUT
- ADP5520_L2_TRIP
- ADP5520_L3_COMP_CURR_uA
- ADP5520_L3_EN
- ADP5520_L3_HYS
- ADP5520_L3_OUT
- ADP5520_L3_TRIP
- ADP5520_LED1_CURRENT
- ADP5520_LED1_EN
- ADP5520_LED2_CURRENT
- ADP5520_LED2_EN
- ADP5520_LED3_CURRENT
- ADP5520_LED3_EN
- ADP5520_LED_CONTROL
- ADP5520_LED_DIS_BLINK
- ADP5520_LED_FADE
- ADP5520_LED_LAW
- ADP5520_LED_OFFT_1200ms
- ADP5520_LED_OFFT_600ms
- ADP5520_LED_OFFT_800ms
- ADP5520_LED_ONT_1200ms
- ADP5520_LED_ONT_200ms
- ADP5520_LED_ONT_600ms
- ADP5520_LED_ONT_800ms
- ADP5520_LED_TIME
- ADP5520_MAXGPIOS
- ADP5520_MAXKEYS
- ADP5520_MODE_STATUS
- ADP5520_OFFICE_DIM
- ADP5520_OFFICE_MAX
- ADP5520_OVP_EN
- ADP5520_OVP_IEN
- ADP5520_OVP_INT
- ADP5520_R3_MODE
- ADP5520_ROW_R0
- ADP5520_ROW_R1
- ADP5520_ROW_R2
- ADP5520_ROW_R3
- ADP5520_nSTNBY
- ADP5585_01
- ADP5585_02
- ADP5585_COL
- ADP5585_COL_MASK
- ADP5585_COL_SHIFT
- ADP5585_DEBOUNCE_DIS_A
- ADP5585_DEBOUNCE_DIS_B
- ADP5585_GENERAL_CFG
- ADP5585_GPIMAPSIZE_MAX
- ADP5585_GPIO_DIRECTION_A
- ADP5585_GPIO_DIRECTION_B
- ADP5585_GPI_EVENT_EN_A
- ADP5585_GPI_EVENT_EN_B
- ADP5585_GPI_INTERRUPT_EN_A
- ADP5585_GPI_INTERRUPT_EN_B
- ADP5585_GPI_INT_LEVEL_A
- ADP5585_GPI_INT_LEVEL_B
- ADP5585_GPI_PIN_BASE
- ADP5585_GPI_PIN_COL0
- ADP5585_GPI_PIN_COL1
- ADP5585_GPI_PIN_COL2
- ADP5585_GPI_PIN_COL3
- ADP5585_GPI_PIN_COL4
- ADP5585_GPI_PIN_COL_BASE
- ADP5585_GPI_PIN_COL_END
- ADP5585_GPI_PIN_END
- ADP5585_GPI_PIN_ROW0
- ADP5585_GPI_PIN_ROW1
- ADP5585_GPI_PIN_ROW2
- ADP5585_GPI_PIN_ROW3
- ADP5585_GPI_PIN_ROW4
- ADP5585_GPI_PIN_ROW5
- ADP5585_GPI_PIN_ROW_BASE
- ADP5585_GPI_PIN_ROW_END
- ADP5585_GPI_STATUS_A
- ADP5585_GPI_STATUS_B
- ADP5585_GPO_DATA_OUT_A
- ADP5585_GPO_DATA_OUT_B
- ADP5585_GPO_OUT_MODE_A
- ADP5585_GPO_OUT_MODE_B
- ADP5585_INT_EN
- ADP5585_KEYMAPSIZE
- ADP5585_LOGIC_CFG
- ADP5585_LOGIC_FF_CFG
- ADP5585_LOGIC_INT_EVENT_EN
- ADP5585_MAXGPIO
- ADP5585_MAX_COL_NUM
- ADP5585_MAX_ROW_NUM
- ADP5585_PIN_CONFIG_A
- ADP5585_PIN_CONFIG_B
- ADP5585_PIN_CONFIG_D
- ADP5585_POLL_PTIME_CFG
- ADP5585_PWM_CFG
- ADP5585_PWM_OFFT_HIGH
- ADP5585_PWM_OFFT_LOW
- ADP5585_PWM_ONT_HIGH
- ADP5585_PWM_ONT_LOW
- ADP5585_RESET1_EVENT_A
- ADP5585_RESET1_EVENT_B
- ADP5585_RESET1_EVENT_C
- ADP5585_RESET2_EVENT_A
- ADP5585_RESET2_EVENT_B
- ADP5585_RESET_CFG
- ADP5585_ROW
- ADP5585_ROW_MASK
- ADP5585_ROW_SHIFT
- ADP5585_RPULL_CONFIG_A
- ADP5585_RPULL_CONFIG_B
- ADP5585_RPULL_CONFIG_C
- ADP5585_RPULL_CONFIG_D
- ADP5588_AUTO_INC
- ADP5588_BANK
- ADP5588_BIT
- ADP5588_CMP1_INT
- ADP5588_CMP2_INT
- ADP5588_DEVICE_ID_MASK
- ADP5588_GPIEM_CFG
- ADP5588_GPIMAPSIZE_MAX
- ADP5588_GPI_IEN
- ADP5588_GPI_INT
- ADP5588_INT_CFG
- ADP5588_KEC
- ADP5588_KEYMAPSIZE
- ADP5588_KE_IEN
- ADP5588_KE_INT
- ADP5588_K_LCK_EN
- ADP5588_K_LCK_IM
- ADP5588_K_LCK_INT
- ADP5588_LCK21
- ADP5588_MAXGPIO
- ADP5588_OVR_FLOW_IEN
- ADP5588_OVR_FLOW_INT
- ADP5588_OVR_FLOW_M
- ADP5589
- ADP5589_5_DEVICE_ID_MASK
- ADP5589_5_FIFO_1
- ADP5589_5_FIFO_10
- ADP5589_5_FIFO_11
- ADP5589_5_FIFO_12
- ADP5589_5_FIFO_13
- ADP5589_5_FIFO_14
- ADP5589_5_FIFO_15
- ADP5589_5_FIFO_16
- ADP5589_5_FIFO_2
- ADP5589_5_FIFO_3
- ADP5589_5_FIFO_4
- ADP5589_5_FIFO_5
- ADP5589_5_FIFO_6
- ADP5589_5_FIFO_7
- ADP5589_5_FIFO_8
- ADP5589_5_FIFO_9
- ADP5589_5_GPI_INT_STAT_A
- ADP5589_5_GPI_INT_STAT_B
- ADP5589_5_ID
- ADP5589_5_INT_STATUS
- ADP5589_5_MAN_ID
- ADP5589_5_MAN_ID_MASK
- ADP5589_5_MAN_ID_SHIFT
- ADP5589_5_STATUS
- ADP5589_CLOCK_DIV_CFG
- ADP5589_COL_MASK
- ADP5589_COL_SHIFT
- ADP5589_DEBOUNCE_DIS_A
- ADP5589_DEBOUNCE_DIS_B
- ADP5589_DEBOUNCE_DIS_C
- ADP5589_EXT_LOCK_EVENT
- ADP5589_GENERAL_CFG
- ADP5589_GPIMAPSIZE_MAX
- ADP5589_GPIO_DIRECTION_A
- ADP5589_GPIO_DIRECTION_B
- ADP5589_GPIO_DIRECTION_C
- ADP5589_GPI_EVENT_EN_A
- ADP5589_GPI_EVENT_EN_B
- ADP5589_GPI_EVENT_EN_C
- ADP5589_GPI_INTERRUPT_EN_A
- ADP5589_GPI_INTERRUPT_EN_B
- ADP5589_GPI_INTERRUPT_EN_C
- ADP5589_GPI_INT_LEVEL_A
- ADP5589_GPI_INT_LEVEL_B
- ADP5589_GPI_INT_LEVEL_C
- ADP5589_GPI_INT_STAT_C
- ADP5589_GPI_PIN_BASE
- ADP5589_GPI_PIN_COL0
- ADP5589_GPI_PIN_COL1
- ADP5589_GPI_PIN_COL10
- ADP5589_GPI_PIN_COL2
- ADP5589_GPI_PIN_COL3
- ADP5589_GPI_PIN_COL4
- ADP5589_GPI_PIN_COL5
- ADP5589_GPI_PIN_COL6
- ADP5589_GPI_PIN_COL7
- ADP5589_GPI_PIN_COL8
- ADP5589_GPI_PIN_COL9
- ADP5589_GPI_PIN_COL_BASE
- ADP5589_GPI_PIN_COL_END
- ADP5589_GPI_PIN_END
- ADP5589_GPI_PIN_ROW0
- ADP5589_GPI_PIN_ROW1
- ADP5589_GPI_PIN_ROW2
- ADP5589_GPI_PIN_ROW3
- ADP5589_GPI_PIN_ROW4
- ADP5589_GPI_PIN_ROW5
- ADP5589_GPI_PIN_ROW6
- ADP5589_GPI_PIN_ROW7
- ADP5589_GPI_PIN_ROW_BASE
- ADP5589_GPI_PIN_ROW_END
- ADP5589_GPI_STATUS_A
- ADP5589_GPI_STATUS_B
- ADP5589_GPI_STATUS_C
- ADP5589_GPO_DATA_OUT_A
- ADP5589_GPO_DATA_OUT_B
- ADP5589_GPO_DATA_OUT_C
- ADP5589_GPO_OUT_MODE_A
- ADP5589_GPO_OUT_MODE_B
- ADP5589_GPO_OUT_MODE_C
- ADP5589_INT_EN
- ADP5589_KEYMAPSIZE
- ADP5589_LOCK_CFG
- ADP5589_LOGIC_1_CFG
- ADP5589_LOGIC_2_CFG
- ADP5589_LOGIC_FF_CFG
- ADP5589_LOGIC_INT_EVENT_EN
- ADP5589_MAXGPIO
- ADP5589_MAX_COL_NUM
- ADP5589_MAX_ROW_NUM
- ADP5589_PIN_CONFIG_A
- ADP5589_PIN_CONFIG_B
- ADP5589_PIN_CONFIG_C
- ADP5589_PIN_CONFIG_D
- ADP5589_POLL_PTIME_CFG
- ADP5589_PWM_CFG
- ADP5589_PWM_OFFT_HIGH
- ADP5589_PWM_OFFT_LOW
- ADP5589_PWM_ONT_HIGH
- ADP5589_PWM_ONT_LOW
- ADP5589_RESET1_EVENT_A
- ADP5589_RESET1_EVENT_B
- ADP5589_RESET1_EVENT_C
- ADP5589_RESET2_EVENT_A
- ADP5589_RESET2_EVENT_B
- ADP5589_RESET_CFG
- ADP5589_ROW_MASK
- ADP5589_RPULL_CONFIG_A
- ADP5589_RPULL_CONFIG_B
- ADP5589_RPULL_CONFIG_C
- ADP5589_RPULL_CONFIG_D
- ADP5589_RPULL_CONFIG_E
- ADP5589_SCAN_CYCLE_10ms
- ADP5589_SCAN_CYCLE_20ms
- ADP5589_SCAN_CYCLE_30ms
- ADP5589_SCAN_CYCLE_40ms
- ADP5589_UNLOCK1
- ADP5589_UNLOCK2
- ADP5589_UNLOCK_TIMERS
- ADP8860_BLDIM
- ADP8860_BLDM1
- ADP8860_BLDM2
- ADP8860_BLDM3
- ADP8860_BLFR
- ADP8860_BLMX1
- ADP8860_BLMX2
- ADP8860_BLMX3
- ADP8860_BLOFF
- ADP8860_BLSEN
- ADP8860_BL_AMBL_FILT_10240ms
- ADP8860_BL_AMBL_FILT_1280ms
- ADP8860_BL_AMBL_FILT_160ms
- ADP8860_BL_AMBL_FILT_2560ms
- ADP8860_BL_AMBL_FILT_320ms
- ADP8860_BL_AMBL_FILT_5120ms
- ADP8860_BL_AMBL_FILT_640ms
- ADP8860_BL_AMBL_FILT_80ms
- ADP8860_BL_CUR_mA
- ADP8860_BL_D1
- ADP8860_BL_D2
- ADP8860_BL_D3
- ADP8860_BL_D4
- ADP8860_BL_D5
- ADP8860_BL_D6
- ADP8860_BL_D7
- ADP8860_CCFG
- ADP8860_CCFG2
- ADP8860_CFGR
- ADP8860_DEVID
- ADP8860_EXT_FEATURES
- ADP8860_FADE_LAW_CUBIC1
- ADP8860_FADE_LAW_CUBIC2
- ADP8860_FADE_LAW_LINEAR
- ADP8860_FADE_LAW_SQUARE
- ADP8860_FADE_T_1200ms
- ADP8860_FADE_T_1500ms
- ADP8860_FADE_T_1800ms
- ADP8860_FADE_T_2100ms
- ADP8860_FADE_T_2400ms
- ADP8860_FADE_T_2700ms
- ADP8860_FADE_T_3000ms
- ADP8860_FADE_T_300ms
- ADP8860_FADE_T_3500ms
- ADP8860_FADE_T_4000ms
- ADP8860_FADE_T_4500ms
- ADP8860_FADE_T_5000ms
- ADP8860_FADE_T_5500ms
- ADP8860_FADE_T_600ms
- ADP8860_FADE_T_900ms
- ADP8860_FADE_T_DIS
- ADP8860_FLAG_LED_MASK
- ADP8860_INTR_EN
- ADP8860_ISC1
- ADP8860_ISC2
- ADP8860_ISC3
- ADP8860_ISC4
- ADP8860_ISC5
- ADP8860_ISC6
- ADP8860_ISC7
- ADP8860_ISCC
- ADP8860_ISCF
- ADP8860_ISCFR
- ADP8860_ISCT1
- ADP8860_ISCT2
- ADP8860_L2_COMP_CURR_uA
- ADP8860_L2_HYS
- ADP8860_L2_TRP
- ADP8860_L3_COMP_CURR_uA
- ADP8860_L3_HYS
- ADP8860_L3_TRP
- ADP8860_LED_D1
- ADP8860_LED_D2
- ADP8860_LED_D3
- ADP8860_LED_D4
- ADP8860_LED_D5
- ADP8860_LED_D6
- ADP8860_LED_D7
- ADP8860_LED_DIS_BLINK
- ADP8860_LED_OFFT_1200ms
- ADP8860_LED_OFFT_1800ms
- ADP8860_LED_OFFT_600ms
- ADP8860_LED_ONT_1200ms
- ADP8860_LED_ONT_200ms
- ADP8860_LED_ONT_600ms
- ADP8860_LED_ONT_800ms
- ADP8860_MANID
- ADP8860_MANUFID
- ADP8860_MAX_BRIGHTNESS
- ADP8860_MDCR
- ADP8860_MDCR2
- ADP8860_MFDVID
- ADP8860_PH1LEVH
- ADP8860_PH1LEVL
- ADP8860_PH2LEVH
- ADP8860_PH2LEVL
- ADP8860_USE_LEDS
- ADP8861_MANUFID
- ADP8863_MANUFID
- ADP8870_ALS1_EN
- ADP8870_ALS1_STAT
- ADP8870_ALS2_EN
- ADP8870_ALS2_STAT
- ADP8870_BLDIM
- ADP8870_BLDM1
- ADP8870_BLDM2
- ADP8870_BLDM3
- ADP8870_BLDM4
- ADP8870_BLDM5
- ADP8870_BLFR
- ADP8870_BLMX1
- ADP8870_BLMX2
- ADP8870_BLMX3
- ADP8870_BLMX4
- ADP8870_BLMX5
- ADP8870_BLOFF
- ADP8870_BLSEL
- ADP8870_BL_AMBL_FILT_10240ms
- ADP8870_BL_AMBL_FILT_1280ms
- ADP8870_BL_AMBL_FILT_160ms
- ADP8870_BL_AMBL_FILT_2560ms
- ADP8870_BL_AMBL_FILT_320ms
- ADP8870_BL_AMBL_FILT_5120ms
- ADP8870_BL_AMBL_FILT_640ms
- ADP8870_BL_AMBL_FILT_80ms
- ADP8870_BL_CUR_mA
- ADP8870_BL_D1
- ADP8870_BL_D2
- ADP8870_BL_D3
- ADP8870_BL_D4
- ADP8870_BL_D5
- ADP8870_BL_D6
- ADP8870_BL_D7
- ADP8870_CFGR
- ADP8870_CMP_CTL
- ADP8870_DEVID
- ADP8870_EXT_FEATURES
- ADP8870_FADE_LAW_CUBIC1
- ADP8870_FADE_LAW_CUBIC2
- ADP8870_FADE_LAW_LINEAR
- ADP8870_FADE_LAW_SQUARE
- ADP8870_FADE_T_1200ms
- ADP8870_FADE_T_1500ms
- ADP8870_FADE_T_1800ms
- ADP8870_FADE_T_2100ms
- ADP8870_FADE_T_2400ms
- ADP8870_FADE_T_2700ms
- ADP8870_FADE_T_3000ms
- ADP8870_FADE_T_300ms
- ADP8870_FADE_T_3500ms
- ADP8870_FADE_T_4000ms
- ADP8870_FADE_T_4500ms
- ADP8870_FADE_T_5000ms
- ADP8870_FADE_T_5500ms
- ADP8870_FADE_T_600ms
- ADP8870_FADE_T_900ms
- ADP8870_FADE_T_DIS
- ADP8870_FLAG_LED_MASK
- ADP8870_INT_EN
- ADP8870_INT_STAT
- ADP8870_ISC1
- ADP8870_ISC2
- ADP8870_ISC3
- ADP8870_ISC4
- ADP8870_ISC5
- ADP8870_ISC6
- ADP8870_ISC7
- ADP8870_ISC7_L2
- ADP8870_ISC7_L3
- ADP8870_ISC7_L4
- ADP8870_ISC7_L5
- ADP8870_ISCC
- ADP8870_ISCF
- ADP8870_ISCLAW
- ADP8870_ISCT1
- ADP8870_ISCT2
- ADP8870_L2HYS
- ADP8870_L2TRP
- ADP8870_L2_COMP_CURR_uA
- ADP8870_L3HYS
- ADP8870_L3TRP
- ADP8870_L3_COMP_CURR_uA
- ADP8870_L4HYS
- ADP8870_L4TRP
- ADP8870_L4_COMP_CURR_uA
- ADP8870_L5HYS
- ADP8870_L5TRP
- ADP8870_L5_COMP_CURR_uA
- ADP8870_LED_D1
- ADP8870_LED_D2
- ADP8870_LED_D3
- ADP8870_LED_D4
- ADP8870_LED_D5
- ADP8870_LED_D6
- ADP8870_LED_D7
- ADP8870_LED_DIS_BLINK
- ADP8870_LED_OFFT_1200ms
- ADP8870_LED_OFFT_1800ms
- ADP8870_LED_OFFT_600ms
- ADP8870_LED_ONT_1200ms
- ADP8870_LED_ONT_200ms
- ADP8870_LED_ONT_600ms
- ADP8870_LED_ONT_800ms
- ADP8870_MANID
- ADP8870_MANUFID
- ADP8870_MAX_BRIGHTNESS
- ADP8870_MDCR
- ADP8870_MFDVID
- ADP8870_PH1LEVH
- ADP8870_PH1LEVL
- ADP8870_PH2LEVH
- ADP8870_PH2LEVL
- ADP8870_PWMLED
- ADP8870_USE_LEDS
- ADPA
- ADPA_CRT_HOTPLUG_ENABLE
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER
- ADPA_CRT_HOTPLUG_MASK
- ADPA_CRT_HOTPLUG_MONITOR_COLOR
- ADPA_CRT_HOTPLUG_MONITOR_MASK
- ADPA_CRT_HOTPLUG_MONITOR_MONO
- ADPA_CRT_HOTPLUG_MONITOR_NONE
- ADPA_CRT_HOTPLUG_PERIOD_128
- ADPA_CRT_HOTPLUG_PERIOD_64
- ADPA_CRT_HOTPLUG_SAMPLE_2S
- ADPA_CRT_HOTPLUG_SAMPLE_4S
- ADPA_CRT_HOTPLUG_VOLREF_325MV
- ADPA_CRT_HOTPLUG_VOLREF_475MV
- ADPA_CRT_HOTPLUG_VOLTAGE_40
- ADPA_CRT_HOTPLUG_VOLTAGE_50
- ADPA_CRT_HOTPLUG_VOLTAGE_60
- ADPA_CRT_HOTPLUG_VOLTAGE_70
- ADPA_CRT_HOTPLUG_WARMUP_10MS
- ADPA_CRT_HOTPLUG_WARMUP_5MS
- ADPA_DAC_DISABLE
- ADPA_DAC_ENABLE
- ADPA_DPMS_CONTROL_MASK
- ADPA_DPMS_D0
- ADPA_DPMS_D1
- ADPA_DPMS_D2
- ADPA_DPMS_D3
- ADPA_DPMS_MASK
- ADPA_DPMS_OFF
- ADPA_DPMS_ON
- ADPA_DPMS_STANDBY
- ADPA_DPMS_SUSPEND
- ADPA_HOTPLUG_BITS
- ADPA_HSYNC_ACTIVE_HIGH
- ADPA_HSYNC_ACTIVE_LOW
- ADPA_HSYNC_ACTIVE_SHIFT
- ADPA_HSYNC_CNTL_DISABLE
- ADPA_HSYNC_CNTL_ENABLE
- ADPA_PIPE_A_SELECT
- ADPA_PIPE_B_SELECT
- ADPA_PIPE_SEL
- ADPA_PIPE_SELECT_MASK
- ADPA_PIPE_SELECT_SHIFT
- ADPA_PIPE_SEL_CPT
- ADPA_PIPE_SEL_MASK
- ADPA_PIPE_SEL_MASK_CPT
- ADPA_PIPE_SEL_SHIFT
- ADPA_PIPE_SEL_SHIFT_CPT
- ADPA_SETS_HVPOLARITY
- ADPA_SYNC_ACTIVE_HIGH
- ADPA_SYNC_ACTIVE_LOW
- ADPA_SYNC_ACTIVE_MASK
- ADPA_USE_VGA_HVPOLARITY
- ADPA_VSYNC_ACTIVE_HIGH
- ADPA_VSYNC_ACTIVE_LOW
- ADPA_VSYNC_ACTIVE_SHIFT
- ADPA_VSYNC_CNTL_DISABLE
- ADPA_VSYNC_CNTL_ENABLE
- ADPCTL
- ADPCTL_ADPENA
- ADPCTL_ADPRES
- ADPCTL_ADP_PRB_INT
- ADPCTL_ADP_PRB_INT_MSK
- ADPCTL_ADP_SNS_INT
- ADPCTL_ADP_SNS_INT_MSK
- ADPCTL_ADP_TMOUT_INT
- ADPCTL_ADP_TMOUT_INT_MSK
- ADPCTL_AR_MASK
- ADPCTL_AR_SHIFT
- ADPCTL_ENAPRB
- ADPCTL_ENASNS
- ADPCTL_PRB_DELTA_MASK
- ADPCTL_PRB_DELTA_SHIFT
- ADPCTL_PRB_DSCHRG_MASK
- ADPCTL_PRB_DSCHRG_SHIFT
- ADPCTL_PRB_PER_MASK
- ADPCTL_PRB_PER_SHIFT
- ADPCTL_RTIM_MASK
- ADPCTL_RTIM_SHIFT
- ADPLL_BWCTRL_BWCONTROL
- ADPLL_BWCTRL_BW_INCR_DECRZ
- ADPLL_BWCTRL_OFFSET
- ADPLL_CLKCTRL_CLKDCOLDOEN
- ADPLL_CLKCTRL_CLKDCOLDOPWDNZ
- ADPLL_CLKCTRL_CLKOUTEN
- ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ
- ADPLL_CLKCTRL_IDLE
- ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S
- ADPLL_CLKCTRL_LPMODE_ADPLL_S
- ADPLL_CLKCTRL_M2PWDNZ
- ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S
- ADPLL_CLKCTRL_OFFSET
- ADPLL_CLKCTRL_REGM4XEN_ADPLL_S
- ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ
- ADPLL_CLKCTRL_TINITZ
- ADPLL_CLKCTRL_ULOWCLKEN
- ADPLL_CLKINPHIFSEL_ADPLL_S
- ADPLL_FRACDIV_FRACTIONALM
- ADPLL_FRACDIV_FRACTIONALM_MASK
- ADPLL_FRACDIV_OFFSET
- ADPLL_FRACDIV_REGSD
- ADPLL_M2NDIV_M2
- ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH
- ADPLL_M2NDIV_M2_ADPLL_S_WIDTH
- ADPLL_M2NDIV_OFFSET
- ADPLL_M3DIV_M3
- ADPLL_M3DIV_M3_MASK
- ADPLL_M3DIV_M3_WIDTH
- ADPLL_M3DIV_OFFSET
- ADPLL_MAX_CON_ID
- ADPLL_MAX_RETRIES
- ADPLL_MN2DIV_N2
- ADPLL_MN2DIV_OFFSET
- ADPLL_PLLSS_MMR_LOCK_ENABLED
- ADPLL_PLLSS_MMR_LOCK_OFFSET
- ADPLL_PLLSS_MMR_UNLOCK_MAGIC
- ADPLL_PWRCTRL_ISORET
- ADPLL_PWRCTRL_ISOSCAN
- ADPLL_PWRCTRL_OFFMODE
- ADPLL_PWRCTRL_OFFSET
- ADPLL_PWRCTRL_PGOODIN
- ADPLL_PWRCTRL_PONIN
- ADPLL_PWRCTRL_RET
- ADPLL_RAMPCTRL_CLKRAMPLEVEL
- ADPLL_RAMPCTRL_CLKRAMPRATE
- ADPLL_RAMPCTRL_OFFSET
- ADPLL_RAMPCTRL_RELOCK_RAMP_EN
- ADPLL_RESERVED_OFFSET
- ADPLL_STATUS_BYPASS
- ADPLL_STATUS_BYPASSACK
- ADPLL_STATUS_CLKOUTENACK
- ADPLL_STATUS_FREQLOCK
- ADPLL_STATUS_HIGHJITTER
- ADPLL_STATUS_LDOPWDN
- ADPLL_STATUS_LOCK2
- ADPLL_STATUS_LOSSREF
- ADPLL_STATUS_M2CHANGEACK
- ADPLL_STATUS_OFFSET
- ADPLL_STATUS_PGOODOUT
- ADPLL_STATUS_PHASELOCK
- ADPLL_STATUS_PONOUT
- ADPLL_STATUS_PREPARED_MASK
- ADPLL_STATUS_RECAL_BSTATUS3
- ADPLL_STATUS_RECAL_OPPIN
- ADPLL_TENABLEDIV_OFFSET
- ADPLL_TENABLE_OFFSET
- ADPT_ARG
- ADPT_DECLARE_WAIT_QUEUE_HEAD
- ADPT_FMT
- ADP_COL
- ADP_ROW
- ADP_SZ
- ADQ12B_ADHIG
- ADQ12B_ADLOW
- ADQ12B_CTREG
- ADQ12B_CTREG_CHAN
- ADQ12B_CTREG_GTP
- ADQ12B_CTREG_MSKP
- ADQ12B_CTREG_RANGE
- ADQ12B_OUTBR
- ADQ12B_STINR
- ADQ12B_STINR_EOC
- ADQ12B_STINR_IN_MASK
- ADQ12B_STINR_OUT2
- ADQ12B_STINR_OUTP
- ADQ12B_TIMER_BASE
- ADRCNT2_E
- ADRCNT_1
- ADRCNT_2
- ADRCNT_3
- ADRCNT_4
- ADRENO_COMMON_XML
- ADRENO_FW_GMU
- ADRENO_FW_GPMU
- ADRENO_FW_MAX
- ADRENO_FW_PFP
- ADRENO_FW_PM4
- ADRENO_FW_SQE
- ADRENO_IDLE_TIMEOUT
- ADRENO_PM4_XML
- ADRENO_PROTECT_RDONLY
- ADRENO_PROTECT_RW
- ADRENO_QUIRK_FAULT_DETECT_MASK
- ADRENO_QUIRK_LMLOADKILL_DISABLE
- ADRENO_QUIRK_TWO_PASS_USE_WFI
- ADRENO_REV
- ADRMD_E
- ADRS
- ADRS_REG
- ADR_CFG_CSDEASSERT_ADD1
- ADR_CFG_CSDEASSERT_ADD2
- ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CUR_VUPDATE_LOCK_SET4__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET4__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CUR_VUPDATE_LOCK_SET5__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK
- ADR_CFG_CUR_VUPDATE_LOCK_SET5__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_CYCLES_ADD1
- ADR_CFG_CYCLES_ADD2
- ADR_CFG_PADS_1_ADD1
- ADR_CFG_PADS_1_ADD2
- ADR_CFG_PADS_2_ADD1
- ADR_CFG_PADS_2_ADD2
- ADR_CFG_PADS_4_ADD1
- ADR_CFG_PADS_4_ADD2
- ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET4__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET4__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CFG_VUPDATE_LOCK_SET5__ADR_CFG_VUPDATE_LOCK_SET_MASK
- ADR_CFG_VUPDATE_LOCK_SET5__ADR_CFG_VUPDATE_LOCK_SET__SHIFT
- ADR_CHTVRegDataPtr
- ADR_CHTVVCLKPtr
- ADR_CRT2PtrData
- ADR_IMM_HILOSPLIT
- ADR_IMM_HIMASK
- ADR_IMM_HISHIFT
- ADR_IMM_LOMASK
- ADR_IMM_LOSHIFT
- ADR_IMM_SIZE
- ADR_LVDSCRT1DataPtr
- ADR_LVDSDesPtrData
- ADR_PCM027_EEPROM
- ADR_PCM027_RTC
- ADR_POS
- ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_VUPDATE_LOCK_SET4__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET4__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_VUPDATE_LOCK_SET5__ADR_VUPDATE_LOCK_SET_MASK
- ADR_VUPDATE_LOCK_SET5__ADR_VUPDATE_LOCK_SET__SHIFT
- ADR_WIN_EN
- ADS1015
- ADS1015_AIN0
- ADS1015_AIN0_AIN1
- ADS1015_AIN0_AIN3
- ADS1015_AIN1
- ADS1015_AIN1_AIN3
- ADS1015_AIN2
- ADS1015_AIN2_AIN3
- ADS1015_AIN3
- ADS1015_CFG_COMP_DISABLE
- ADS1015_CFG_COMP_LAT_MASK
- ADS1015_CFG_COMP_LAT_SHIFT
- ADS1015_CFG_COMP_MODE_MASK
- ADS1015_CFG_COMP_MODE_SHIFT
- ADS1015_CFG_COMP_MODE_TRAD
- ADS1015_CFG_COMP_MODE_WINDOW
- ADS1015_CFG_COMP_POL_HIGH
- ADS1015_CFG_COMP_POL_LOW
- ADS1015_CFG_COMP_POL_MASK
- ADS1015_CFG_COMP_POL_SHIFT
- ADS1015_CFG_COMP_QUE_MASK
- ADS1015_CFG_COMP_QUE_SHIFT
- ADS1015_CFG_DR_MASK
- ADS1015_CFG_DR_SHIFT
- ADS1015_CFG_MOD_MASK
- ADS1015_CFG_MOD_SHIFT
- ADS1015_CFG_MUX_MASK
- ADS1015_CFG_MUX_SHIFT
- ADS1015_CFG_PGA_MASK
- ADS1015_CFG_PGA_SHIFT
- ADS1015_CFG_REG
- ADS1015_CHANNELS
- ADS1015_CONTINUOUS
- ADS1015_CONV_REG
- ADS1015_DEFAULT_CHAN
- ADS1015_DEFAULT_DATA_RATE
- ADS1015_DEFAULT_PGA
- ADS1015_DRV_NAME
- ADS1015_HI_THRESH_REG
- ADS1015_LO_THRESH_REG
- ADS1015_SINGLESHOT
- ADS1015_SLEEP_DELAY_MS
- ADS1015_TIMESTAMP
- ADS1015_V_CHAN
- ADS1015_V_DIFF_CHAN
- ADS1115
- ADS1115_V_CHAN
- ADS1115_V_DIFF_CHAN
- ADS117X_FORMATS
- ADS117X_RATES
- ADS124S06_ID
- ADS124S08_AIN0
- ADS124S08_AIN1
- ADS124S08_AIN10
- ADS124S08_AIN11
- ADS124S08_AIN2
- ADS124S08_AIN3
- ADS124S08_AIN4
- ADS124S08_AIN5
- ADS124S08_AIN6
- ADS124S08_AIN7
- ADS124S08_AIN8
- ADS124S08_AIN9
- ADS124S08_AINCOM
- ADS124S08_CHAN
- ADS124S08_CMD_NOP
- ADS124S08_CMD_PWRDWN
- ADS124S08_CMD_RDATA
- ADS124S08_CMD_RESET
- ADS124S08_CMD_RREG
- ADS124S08_CMD_SFOCAL
- ADS124S08_CMD_START
- ADS124S08_CMD_STOP
- ADS124S08_CMD_SYGCAL
- ADS124S08_CMD_SYOCAL
- ADS124S08_CMD_WAKEUP
- ADS124S08_CMD_WREG
- ADS124S08_DATA_RATE
- ADS124S08_FSCAL0
- ADS124S08_FSCAL1
- ADS124S08_FSCAL2
- ADS124S08_GPIOCON
- ADS124S08_GPIODAT
- ADS124S08_ID
- ADS124S08_IDACMAG
- ADS124S08_IDACMUX
- ADS124S08_ID_REG
- ADS124S08_INPUT_MUX
- ADS124S08_INT_REF
- ADS124S08_MAX_CHANNELS
- ADS124S08_NUM_BYTES_MASK
- ADS124S08_OFCAL0
- ADS124S08_OFCAL1
- ADS124S08_OFCAL2
- ADS124S08_PGA
- ADS124S08_POS_MUX_SHIFT
- ADS124S08_REF
- ADS124S08_START_CONV
- ADS124S08_START_REG_MASK
- ADS124S08_STATUS
- ADS124S08_STOP_CONV
- ADS124S08_SYS
- ADS124S08_VBIAS
- ADS5
- ADS6
- ADS7828_CMD_PD1
- ADS7828_CMD_PD3
- ADS7828_CMD_SD_SE
- ADS7828_EXT_VREF_MV_MAX
- ADS7828_EXT_VREF_MV_MIN
- ADS7828_INT_VREF_MV
- ADS7846_FILTER_IGNORE
- ADS7846_FILTER_OK
- ADS7846_FILTER_REPEAT
- ADS7846_PENDOWN_GPIO
- ADS786X_CHAN
- ADS8344_CHANNEL
- ADS8344_CLOCK_INTERNAL
- ADS8344_SINGLE_END
- ADS8344_START
- ADS8344_VOLTAGE_CHANNEL
- ADS8344_VOLTAGE_CHANNEL_DIFF
- ADS8688_CHAN
- ADS8688_CMD_DONT_CARE_BITS
- ADS8688_CMD_REG
- ADS8688_CMD_REG_MAN_CH
- ADS8688_CMD_REG_NOOP
- ADS8688_CMD_REG_RST
- ADS8688_MAX_CHANNELS
- ADS8688_PLUS125VREF
- ADS8688_PLUS25VREF
- ADS8688_PLUSMINUS0625VREF
- ADS8688_PLUSMINUS125VREF
- ADS8688_PLUSMINUS25VREF
- ADS8688_PROG_DONT_CARE_BITS
- ADS8688_PROG_REG
- ADS8688_PROG_REG_RANGE_CH
- ADS8688_PROG_WR_BIT
- ADS8688_REALBITS
- ADS8688_REG_PLUS125VREF
- ADS8688_REG_PLUS25VREF
- ADS8688_REG_PLUSMINUS0625VREF
- ADS8688_REG_PLUSMINUS125VREF
- ADS8688_REG_PLUSMINUS25VREF
- ADS8688_VREF_MV
- ADSLPLLCTL_M1BUS_MASK
- ADSLPLLCTL_M1BUS_SHIFT
- ADSLPLLCTL_M1CPU_MASK
- ADSLPLLCTL_M1CPU_SHIFT
- ADSLPLLCTL_M1REF_MASK
- ADSLPLLCTL_M1REF_SHIFT
- ADSLPLLCTL_M2BUS_MASK
- ADSLPLLCTL_M2BUS_SHIFT
- ADSLPLLCTL_M2REF_MASK
- ADSLPLLCTL_M2REF_SHIFT
- ADSLPLLCTL_N1_MASK
- ADSLPLLCTL_N1_SHIFT
- ADSLPLLCTL_N2_MASK
- ADSLPLLCTL_N2_SHIFT
- ADSLPLLCTL_VAL
- ADSP1_CLK_SEL_MASK
- ADSP1_CLK_SEL_SHIFT
- ADSP1_CLK_SEL_WIDTH
- ADSP1_CONTROL_1
- ADSP1_CONTROL_10
- ADSP1_CONTROL_11
- ADSP1_CONTROL_12
- ADSP1_CONTROL_13
- ADSP1_CONTROL_14
- ADSP1_CONTROL_15
- ADSP1_CONTROL_16
- ADSP1_CONTROL_17
- ADSP1_CONTROL_18
- ADSP1_CONTROL_19
- ADSP1_CONTROL_2
- ADSP1_CONTROL_20
- ADSP1_CONTROL_21
- ADSP1_CONTROL_22
- ADSP1_CONTROL_23
- ADSP1_CONTROL_24
- ADSP1_CONTROL_25
- ADSP1_CONTROL_26
- ADSP1_CONTROL_27
- ADSP1_CONTROL_28
- ADSP1_CONTROL_29
- ADSP1_CONTROL_3
- ADSP1_CONTROL_30
- ADSP1_CONTROL_31
- ADSP1_CONTROL_4
- ADSP1_CONTROL_5
- ADSP1_CONTROL_6
- ADSP1_CONTROL_7
- ADSP1_CONTROL_8
- ADSP1_CONTROL_9
- ADSP1_CORE_ENA
- ADSP1_CORE_ENA_MASK
- ADSP1_CORE_ENA_SHIFT
- ADSP1_CORE_ENA_WIDTH
- ADSP1_DBG_CLK_ENA
- ADSP1_DBG_CLK_ENA_MASK
- ADSP1_DBG_CLK_ENA_SHIFT
- ADSP1_DBG_CLK_ENA_WIDTH
- ADSP1_START
- ADSP1_START_MASK
- ADSP1_START_SHIFT
- ADSP1_START_WIDTH
- ADSP1_SYS_ENA
- ADSP1_SYS_ENA_MASK
- ADSP1_SYS_ENA_SHIFT
- ADSP1_SYS_ENA_WIDTH
- ADSP1_WDMA_BUFFER_LENGTH_MASK
- ADSP1_WDMA_BUFFER_LENGTH_SHIFT
- ADSP1_WDMA_BUFFER_LENGTH_WIDTH
- ADSP2V2_CLK_SEL_MASK
- ADSP2V2_CLK_SEL_SHIFT
- ADSP2V2_CLK_SEL_WIDTH
- ADSP2V2_CLOCKING
- ADSP2V2_RATE_MASK
- ADSP2V2_RATE_SHIFT
- ADSP2V2_RATE_WIDTH
- ADSP2V2_SCRATCH0_1
- ADSP2V2_SCRATCH2_3
- ADSP2V2_WDMA_CONFIG_2
- ADSP2_BUS_ERR_ADDR
- ADSP2_BUS_ERR_ADDR_MASK
- ADSP2_CLK_SEL_MASK
- ADSP2_CLK_SEL_SHIFT
- ADSP2_CLK_SEL_WIDTH
- ADSP2_CLOCKING
- ADSP2_CONTROL
- ADSP2_CORE_ENA
- ADSP2_CORE_ENA_MASK
- ADSP2_CORE_ENA_SHIFT
- ADSP2_CORE_ENA_WIDTH
- ADSP2_CTRL_ERR_EINT
- ADSP2_CTRL_ERR_PAUSE_ENA
- ADSP2_LOCK_CODE_0
- ADSP2_LOCK_CODE_1
- ADSP2_LOCK_REGION_1_LOCK_REGION_0
- ADSP2_LOCK_REGION_3_LOCK_REGION_2
- ADSP2_LOCK_REGION_5_LOCK_REGION_4
- ADSP2_LOCK_REGION_7_LOCK_REGION_6
- ADSP2_LOCK_REGION_9_LOCK_REGION_8
- ADSP2_LOCK_REGION_CTRL
- ADSP2_LOCK_REGION_SHIFT
- ADSP2_MEM_ENA
- ADSP2_MEM_ENA_MASK
- ADSP2_MEM_ENA_SHIFT
- ADSP2_MEM_ENA_WIDTH
- ADSP2_PMEM_ERR_ADDR_MASK
- ADSP2_PMEM_ERR_ADDR_SHIFT
- ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR
- ADSP2_RAM_RDY
- ADSP2_RAM_RDY_MASK
- ADSP2_RAM_RDY_SHIFT
- ADSP2_RAM_RDY_WIDTH
- ADSP2_RDMA_CONFIG_1
- ADSP2_REGION_LOCK_ERR_MASK
- ADSP2_REGION_LOCK_STATUS
- ADSP2_SCRATCH0
- ADSP2_SCRATCH1
- ADSP2_SCRATCH2
- ADSP2_SCRATCH3
- ADSP2_SLAVE_ERR_MASK
- ADSP2_START
- ADSP2_START_MASK
- ADSP2_START_SHIFT
- ADSP2_START_WIDTH
- ADSP2_STATUS1
- ADSP2_SYS_ENA
- ADSP2_SYS_ENA_MASK
- ADSP2_SYS_ENA_SHIFT
- ADSP2_SYS_ENA_WIDTH
- ADSP2_WATCHDOG
- ADSP2_WDMA_CONFIG_1
- ADSP2_WDMA_CONFIG_2
- ADSP2_WDT_ENA_MASK
- ADSP2_WDT_TIMEOUT_STS_MASK
- ADSP2_XMEM_ERR_ADDR_MASK
- ADSP_DOMAIN_ID
- ADSP_EABORTED
- ADSP_EALREADY
- ADSP_EBADPARAM
- ADSP_EBUSY
- ADSP_ECONTINUE
- ADSP_EFAILED
- ADSP_EHANDLE
- ADSP_EIMMEDIATE
- ADSP_ENEEDMORE
- ADSP_ENOMEMORY
- ADSP_ENORESOURCE
- ADSP_ENOTEXIST
- ADSP_ENOTIMPL
- ADSP_ENOTREADY
- ADSP_EOK
- ADSP_EPANIC
- ADSP_EPENDING
- ADSP_EPREEMPTED
- ADSP_EUNEXPECTED
- ADSP_EUNSUPPORTED
- ADSP_EVERSION
- ADSP_MAX_STD_CTRL_SIZE
- ADSP_MEMORY_MAP_SHMEM8_4K_POOL
- ADSP_STATE_READY_TIMEOUT_MS
- ADS_12_BIT
- ADS_8_BIT
- ADS_A2A1A0_d_x
- ADS_A2A1A0_d_y
- ADS_A2A1A0_d_z1
- ADS_A2A1A0_d_z2
- ADS_A2A1A0_temp0
- ADS_A2A1A0_temp1
- ADS_A2A1A0_vaux
- ADS_A2A1A0_vbatt
- ADS_DFR
- ADS_PD10_ADC_ON
- ADS_PD10_ALL_ON
- ADS_PD10_PDOWN
- ADS_PD10_REF_ON
- ADS_SER
- ADS_START
- ADSwitch
- ADT
- ADT0_CE_BIT
- ADT0_LE_BIT
- ADT0_PG_BIT
- ADT1_BD_SHIFT
- ADT1_CTRL_ASYNC_BD_MASK
- ADT1_DNE_BIT
- ADT1_ERR_BIT
- ADT1_ISOC_SYNC_BD_MASK
- ADT1_MEP_BIT
- ADT1_PS_BIT
- ADT1_RDY_BIT
- ADT7301_TEMP_MASK
- ADT7310_CMD_READ
- ADT7310_CMD_REG_OFFSET
- ADT7310_CONFIG
- ADT7310_ID
- ADT7310_STATUS
- ADT7310_TEMPERATURE
- ADT7310_T_ALARM_HIGH
- ADT7310_T_ALARM_LOW
- ADT7310_T_CRIT
- ADT7310_T_HYST
- ADT7316_ADCLK_22_5
- ADT7316_AD_MSB_DATA_BASE
- ADT7316_AD_MSB_DATA_REGS
- ADT7316_AD_SINGLE_CH_EX
- ADT7316_AD_SINGLE_CH_IN
- ADT7316_AD_SINGLE_CH_MASK
- ADT7316_AD_SINGLE_CH_MODE
- ADT7316_AD_SINGLE_CH_VDD
- ADT7316_CONFIG1
- ADT7316_CONFIG2
- ADT7316_CONFIG3
- ADT7316_DAC_CONFIG
- ADT7316_DAC_IN_VREF
- ADT7316_DA_10_BIT_LSB_SHIFT
- ADT7316_DA_12_BIT_LSB_SHIFT
- ADT7316_DA_2VREF_CH_MASK
- ADT7316_DA_DATA_BASE
- ADT7316_DA_EN_MODE_ABCD
- ADT7316_DA_EN_MODE_AB_CD
- ADT7316_DA_EN_MODE_LDAC
- ADT7316_DA_EN_MODE_MASK
- ADT7316_DA_EN_MODE_SHIFT
- ADT7316_DA_EN_MODE_SINGLE
- ADT7316_DA_EN_VIA_DAC_LDAC
- ADT7316_DA_HIGH_RESOLUTION
- ADT7316_DA_MSB_DATA_REGS
- ADT7316_DEVICE_ID
- ADT7316_DEVICE_REV
- ADT7316_DISABLE_AVERAGING
- ADT7316_EN
- ADT7316_EN_EX_TEMP_PROP_DACB
- ADT7316_EN_IN_TEMP_PROP_DACA
- ADT7316_EN_SMBUS_TIMEOUT
- ADT7316_EX_ANALOG_TEMP_OFFSET
- ADT7316_EX_TEMP_FAULT_INT_MASK
- ADT7316_EX_TEMP_HIGH
- ADT7316_EX_TEMP_HIGH_INT_MASK
- ADT7316_EX_TEMP_LOW
- ADT7316_EX_TEMP_LOW_INT_MASK
- ADT7316_EX_TEMP_OFFSET
- ADT7316_INT_EN
- ADT7316_INT_MASK1
- ADT7316_INT_MASK2
- ADT7316_INT_MASK2_VDD
- ADT7316_INT_POLARITY
- ADT7316_INT_STAT1
- ADT7316_INT_STAT2
- ADT7316_IN_ANALOG_TEMP_OFFSET
- ADT7316_IN_TEMP_HIGH
- ADT7316_IN_TEMP_HIGH_INT_MASK
- ADT7316_IN_TEMP_LOW
- ADT7316_IN_TEMP_LOW_INT_MASK
- ADT7316_IN_TEMP_OFFSET
- ADT7316_LDAC_CONFIG
- ADT7316_LDAC_EN_DA_MASK
- ADT7316_LSB_DAC_A
- ADT7316_LSB_DAC_B
- ADT7316_LSB_DAC_C
- ADT7316_LSB_DAC_D
- ADT7316_LSB_EX_TEMP_AIN
- ADT7316_LSB_EX_TEMP_MASK
- ADT7316_LSB_IN_TEMP_MASK
- ADT7316_LSB_IN_TEMP_VDD
- ADT7316_LSB_VDD_MASK
- ADT7316_LSB_VDD_OFFSET
- ADT7316_MANUFACTURE_ID
- ADT7316_MSB_DAC_A
- ADT7316_MSB_DAC_B
- ADT7316_MSB_DAC_C
- ADT7316_MSB_DAC_D
- ADT7316_MSB_EX_TEMP
- ADT7316_MSB_IN_TEMP
- ADT7316_MSB_VDD
- ADT7316_PD
- ADT7316_PM_OPS
- ADT7316_REG_MAX_ADDR
- ADT7316_RESET
- ADT7316_SPI_CMD_READ
- ADT7316_SPI_CMD_WRITE
- ADT7316_SPI_LOCK_STAT
- ADT7316_SPI_MAX_FREQ_HZ
- ADT7316_TEMP_AIN_INT_MASK
- ADT7316_TEMP_INT_MASK
- ADT7316_T_VALUE_FLOAT_MASK
- ADT7316_T_VALUE_FLOAT_OFFSET
- ADT7316_T_VALUE_SIGN
- ADT7316_VALUE_MASK
- ADT7316_VDD_HIGH
- ADT7316_VDD_INT_MASK
- ADT7316_VDD_LOW
- ADT7316_VREF_BYPASS_DAC_AB
- ADT7316_VREF_BYPASS_DAC_CD
- ADT7408_DEVID
- ADT7408_DEVID_MASK
- ADT7411_BIT_ATTR
- ADT7411_CFG1_EXT_TDM
- ADT7411_CFG1_RESERVED_BIT1
- ADT7411_CFG1_RESERVED_BIT3
- ADT7411_CFG1_START_MONITOR
- ADT7411_CFG2_DISABLE_AVG
- ADT7411_CFG3_ADC_CLK_225
- ADT7411_CFG3_REF_VDD
- ADT7411_CFG3_RESERVED_BIT1
- ADT7411_CFG3_RESERVED_BIT2
- ADT7411_CFG3_RESERVED_BIT3
- ADT7411_DEVICE_ID
- ADT7411_MANUFACTURER_ID
- ADT7411_REG_CFG1
- ADT7411_REG_CFG2
- ADT7411_REG_CFG3
- ADT7411_REG_DEVICE_ID
- ADT7411_REG_EXT_TEMP_AIN14_LSB
- ADT7411_REG_EXT_TEMP_AIN1_MSB
- ADT7411_REG_INT_TEMP_MSB
- ADT7411_REG_INT_TEMP_VDD_LSB
- ADT7411_REG_IN_HIGH
- ADT7411_REG_IN_LOW
- ADT7411_REG_MANUFACTURER_ID
- ADT7411_REG_STAT_1
- ADT7411_REG_STAT_2
- ADT7411_REG_TEMP_HIGH
- ADT7411_REG_TEMP_LOW
- ADT7411_REG_VDD_HIGH
- ADT7411_REG_VDD_LOW
- ADT7411_REG_VDD_MSB
- ADT7411_STAT_1_AIN2
- ADT7411_STAT_1_AIN3
- ADT7411_STAT_1_AIN4
- ADT7411_STAT_1_EXT_TEMP_FAULT
- ADT7411_STAT_1_EXT_TEMP_HIGH_AIN1
- ADT7411_STAT_1_EXT_TEMP_LOW
- ADT7411_STAT_1_INT_TEMP_HIGH
- ADT7411_STAT_1_INT_TEMP_LOW
- ADT7411_STAT_2_AIN5
- ADT7411_STAT_2_AIN6
- ADT7411_STAT_2_AIN7
- ADT7411_STAT_2_AIN8
- ADT7411_STAT_2_VDD
- ADT7460
- ADT7462_ALARM1
- ADT7462_ALARM2
- ADT7462_ALARM3
- ADT7462_ALARM4
- ADT7462_ALARM_FLAG_MASK
- ADT7462_ALARM_REG_COUNT
- ADT7462_ALARM_REG_SHIFT
- ADT7462_DEVICE
- ADT7462_DIODE1_INPUT
- ADT7462_DIODE3_INPUT
- ADT7462_F0_ALARM
- ADT7462_F1_ALARM
- ADT7462_F2_ALARM
- ADT7462_F3_ALARM
- ADT7462_F4_ALARM
- ADT7462_F5_ALARM
- ADT7462_F6_ALARM
- ADT7462_F7_ALARM
- ADT7462_FAN_COUNT
- ADT7462_FSPD_MASK
- ADT7462_LT_ALARM
- ADT7462_PIN13_INPUT
- ADT7462_PIN15_INPUT
- ADT7462_PIN19_INPUT
- ADT7462_PIN21_INPUT
- ADT7462_PIN22_INPUT
- ADT7462_PIN23_MASK
- ADT7462_PIN23_SHIFT
- ADT7462_PIN24_MASK
- ADT7462_PIN24_SHIFT
- ADT7462_PIN25_MASK
- ADT7462_PIN25_SHIFT
- ADT7462_PIN25_VOLT_INPUT
- ADT7462_PIN26_MASK
- ADT7462_PIN26_SHIFT
- ADT7462_PIN26_VOLT_INPUT
- ADT7462_PIN28_SHIFT
- ADT7462_PIN28_VOLT
- ADT7462_PIN7_INPUT
- ADT7462_PIN8_INPUT
- ADT7462_PIN_CFG_REG_COUNT
- ADT7462_PWM_CHANNEL_MASK
- ADT7462_PWM_CHANNEL_SHIFT
- ADT7462_PWM_COUNT
- ADT7462_PWM_HYST_MASK
- ADT7462_PWM_RANGE_MASK
- ADT7462_PWM_RANGE_SHIFT
- ADT7462_R1T_ALARM
- ADT7462_R2T_ALARM
- ADT7462_R3T_ALARM
- ADT7462_REG_ALARM1
- ADT7462_REG_ALARM2
- ADT7462_REG_ALARM3
- ADT7462_REG_ALARM4
- ADT7462_REG_CFG2
- ADT7462_REG_DEVICE
- ADT7462_REG_FAN
- ADT7462_REG_FAN2_BASE_ADDR
- ADT7462_REG_FAN2_MAX_ADDR
- ADT7462_REG_FAN_BASE_ADDR
- ADT7462_REG_FAN_ENABLE
- ADT7462_REG_FAN_MAX_ADDR
- ADT7462_REG_FAN_MIN
- ADT7462_REG_FAN_MIN_BASE_ADDR
- ADT7462_REG_FAN_MIN_MAX_ADDR
- ADT7462_REG_MAX_TEMP_BASE_ADDR
- ADT7462_REG_MAX_TEMP_MAX_ADDR
- ADT7462_REG_MIN_TEMP_BASE_ADDR
- ADT7462_REG_MIN_TEMP_MAX_ADDR
- ADT7462_REG_PIN_CFG
- ADT7462_REG_PIN_CFG_BASE_ADDR
- ADT7462_REG_PIN_CFG_MAX_ADDR
- ADT7462_REG_PWM
- ADT7462_REG_PWM_BASE_ADDR
- ADT7462_REG_PWM_CFG
- ADT7462_REG_PWM_CFG_BASE_ADDR
- ADT7462_REG_PWM_CFG_MAX_ADDR
- ADT7462_REG_PWM_MAX
- ADT7462_REG_PWM_MAX_ADDR
- ADT7462_REG_PWM_MIN
- ADT7462_REG_PWM_MIN_BASE_ADDR
- ADT7462_REG_PWM_MIN_MAX_ADDR
- ADT7462_REG_PWM_TEMP_MIN_BASE_ADDR
- ADT7462_REG_PWM_TEMP_MIN_MAX_ADDR
- ADT7462_REG_PWM_TEMP_RANGE_BASE_ADDR
- ADT7462_REG_PWM_TEMP_RANGE_MAX_ADDR
- ADT7462_REG_PWM_TMIN
- ADT7462_REG_PWM_TRANGE
- ADT7462_REG_REVISION
- ADT7462_REG_TEMP_BASE_ADDR
- ADT7462_REG_TEMP_MAX_ADDR
- ADT7462_REG_VENDOR
- ADT7462_REG_VOLT
- ADT7462_REG_VOLT_MAX
- ADT7462_REG_VOLT_MIN
- ADT7462_REVISION
- ADT7462_TEMP_COUNT
- ADT7462_TEMP_MAX_REG
- ADT7462_TEMP_MIN_REG
- ADT7462_TEMP_REG
- ADT7462_V0_ALARM
- ADT7462_V10_ALARM
- ADT7462_V11_ALARM
- ADT7462_V12_ALARM
- ADT7462_V1_ALARM
- ADT7462_V2_ALARM
- ADT7462_V3_ALARM
- ADT7462_V4_ALARM
- ADT7462_V5_ALARM
- ADT7462_V6_ALARM
- ADT7462_V7_ALARM
- ADT7462_V8_ALARM
- ADT7462_V9_ALARM
- ADT7462_VENDOR
- ADT7462_VID_INPUT
- ADT7462_VOLT_COUNT
- ADT7467
- ADT7468_HFPWM
- ADT7468_OFF64
- ADT7468_REG_CFG5
- ADT7470_CFG_LF
- ADT7470_DEVICE
- ADT7470_FAN1_ALARM
- ADT7470_FAN2_ALARM
- ADT7470_FAN3_ALARM
- ADT7470_FAN4_ALARM
- ADT7470_FAN_COUNT
- ADT7470_FREQ_MASK
- ADT7470_FREQ_SHIFT
- ADT7470_FSPD_MASK
- ADT7470_OOL_ALARM
- ADT7470_PWM1_AUTO_MASK
- ADT7470_PWM2_AUTO_MASK
- ADT7470_PWM3_AUTO_MASK
- ADT7470_PWM4_AUTO_MASK
- ADT7470_PWM_ALL_TEMPS
- ADT7470_PWM_AUTO_MASK
- ADT7470_PWM_COUNT
- ADT7470_R10T_ALARM
- ADT7470_R1T_ALARM
- ADT7470_R2T_ALARM
- ADT7470_R3T_ALARM
- ADT7470_R4T_ALARM
- ADT7470_R5T_ALARM
- ADT7470_R6T_ALARM
- ADT7470_R7T_ALARM
- ADT7470_R8T_ALARM
- ADT7470_R9T_ALARM
- ADT7470_REG_ACOUSTICS12
- ADT7470_REG_ACOUSTICS34
- ADT7470_REG_ALARM1
- ADT7470_REG_ALARM1_MASK
- ADT7470_REG_ALARM2
- ADT7470_REG_ALARM2_MASK
- ADT7470_REG_BASE_ADDR
- ADT7470_REG_CFG
- ADT7470_REG_CFG_2
- ADT7470_REG_DEVICE
- ADT7470_REG_FAN
- ADT7470_REG_FAN_BASE_ADDR
- ADT7470_REG_FAN_MAX
- ADT7470_REG_FAN_MAX_ADDR
- ADT7470_REG_FAN_MAX_BASE_ADDR
- ADT7470_REG_FAN_MAX_MAX_ADDR
- ADT7470_REG_FAN_MIN
- ADT7470_REG_FAN_MIN_BASE_ADDR
- ADT7470_REG_FAN_MIN_MAX_ADDR
- ADT7470_REG_MAX_ADDR
- ADT7470_REG_PWM
- ADT7470_REG_PWM12_CFG
- ADT7470_REG_PWM34_CFG
- ADT7470_REG_PWM_AUTO_TEMP
- ADT7470_REG_PWM_AUTO_TEMP_BASE_ADDR
- ADT7470_REG_PWM_AUTO_TEMP_MAX_ADDR
- ADT7470_REG_PWM_BASE_ADDR
- ADT7470_REG_PWM_CFG
- ADT7470_REG_PWM_CFG_BASE_ADDR
- ADT7470_REG_PWM_MAX
- ADT7470_REG_PWM_MAX_ADDR
- ADT7470_REG_PWM_MAX_BASE_ADDR
- ADT7470_REG_PWM_MAX_MAX_ADDR
- ADT7470_REG_PWM_MIN
- ADT7470_REG_PWM_MIN_BASE_ADDR
- ADT7470_REG_PWM_MIN_MAX_ADDR
- ADT7470_REG_PWM_TEMP_MIN_BASE_ADDR
- ADT7470_REG_PWM_TEMP_MIN_MAX_ADDR
- ADT7470_REG_PWM_TMIN
- ADT7470_REG_REVISION
- ADT7470_REG_TEMP_BASE_ADDR
- ADT7470_REG_TEMP_LIMITS_BASE_ADDR
- ADT7470_REG_TEMP_LIMITS_MAX_ADDR
- ADT7470_REG_TEMP_MAX_ADDR
- ADT7470_REG_VENDOR
- ADT7470_REVISION
- ADT7470_TEMP_COUNT
- ADT7470_TEMP_MAX_REG
- ADT7470_TEMP_MIN_REG
- ADT7470_TEMP_REG
- ADT7470_VENDOR
- ADT7475_PWM_COUNT
- ADT7475_TACH_COUNT
- ADT7475_TEMP_COUNT
- ADT7475_VOLTAGE_COUNT
- ADT7516_AD_MSB_DATA_REGS
- ADT7516_AD_SINGLE_CH_AIN1
- ADT7516_AD_SINGLE_CH_AIN2
- ADT7516_AD_SINGLE_CH_AIN3
- ADT7516_AD_SINGLE_CH_AIN4
- ADT7516_AD_SINGLE_CH_MASK
- ADT7516_AIN1_INT_MASK
- ADT7516_AIN2_HIGH
- ADT7516_AIN2_INT_MASK
- ADT7516_AIN2_LOW
- ADT7516_AIN3_HIGH
- ADT7516_AIN3_INT_MASK
- ADT7516_AIN3_LOW
- ADT7516_AIN4_HIGH
- ADT7516_AIN4_INT_MASK
- ADT7516_AIN4_LOW
- ADT7516_AIN_INT_MASK
- ADT7516_AIN_IN_VREF
- ADT7516_DAC_AB_IN_VREF
- ADT7516_DAC_CD_IN_VREF
- ADT7516_DAC_IN_VREF_MASK
- ADT7516_DAC_IN_VREF_OFFSET
- ADT7516_LSB_AIN_SHIFT
- ADT7516_MSB_AIN1
- ADT7516_MSB_AIN2
- ADT7516_MSB_AIN3
- ADT7516_MSB_AIN4
- ADT7516_SEL_AIN1_2_EX_TEMP_MASK
- ADT7516_SEL_AIN3
- ADT7516_SEL_EX_TEMP
- ADT7X10_CONFIG
- ADT7X10_CT_POLARITY
- ADT7X10_DEV_PM_OPS
- ADT7X10_EVENT_MODE
- ADT7X10_FAULT_QUEUE_MASK
- ADT7X10_FULL
- ADT7X10_ID
- ADT7X10_INT_POLARITY
- ADT7X10_MODE_MASK
- ADT7X10_PD
- ADT7X10_REG_TO_TEMP
- ADT7X10_RESOLUTION
- ADT7X10_STATUS
- ADT7X10_STAT_NOT_RDY
- ADT7X10_STAT_T_CRIT
- ADT7X10_STAT_T_HIGH
- ADT7X10_STAT_T_LOW
- ADT7X10_T13_VALUE_MASK
- ADT7X10_TEMPERATURE
- ADT7X10_TEMP_MAX
- ADT7X10_TEMP_MIN
- ADT7X10_TEMP_TO_REG
- ADT7X10_T_ALARM_HIGH
- ADT7X10_T_ALARM_LOW
- ADT7X10_T_CRIT
- ADT7X10_T_HYST
- ADT7X10_T_HYST_MASK
- ADTRG0_MARK
- ADTRG1_MARK
- ADTRG_MARK
- ADTRG_PD_MARK
- ADTRG_PE_MARK
- ADT_MANID
- ADT_OPT
- ADUMMY_DEV
- ADU_MINOR_BASE
- ADU_PRODUCT_ID
- ADU_VENDOR_ID
- ADV7180_AUTODETECT_DEFAULT
- ADV7180_BRI_DEF
- ADV7180_BRI_MAX
- ADV7180_BRI_MIN
- ADV7180_CON_DEF
- ADV7180_CON_MAX
- ADV7180_CON_MIN
- ADV7180_CSI_PWRDN
- ADV7180_CSI_REG_PWRDN
- ADV7180_CTRL_IRQ_SPACE
- ADV7180_DEFAULT_CSI_I2C_ADDR
- ADV7180_DEFAULT_VPP_I2C_ADDR
- ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS
- ADV7180_FLAG_I2P
- ADV7180_FLAG_MIPI_CSI2
- ADV7180_FLAG_RESET_POWERED
- ADV7180_FLAG_V2
- ADV7180_FLCONTROL_FL_ENABLE
- ADV7180_HUE_DEF
- ADV7180_HUE_MAX
- ADV7180_HUE_MIN
- ADV7180_ICONF1_ACTIVE_LOW
- ADV7180_ICONF1_ACTIVE_TO_CLR
- ADV7180_ICONF1_PSYNC_ONLY
- ADV7180_ID_7180
- ADV7180_INPUT_CONTROL_INSEL_MASK
- ADV7180_INPUT_CVBS_AIN1
- ADV7180_INPUT_CVBS_AIN2
- ADV7180_INPUT_CVBS_AIN3
- ADV7180_INPUT_CVBS_AIN4
- ADV7180_INPUT_CVBS_AIN5
- ADV7180_INPUT_CVBS_AIN6
- ADV7180_INPUT_SVIDEO_AIN1_AIN2
- ADV7180_INPUT_SVIDEO_AIN3_AIN4
- ADV7180_INPUT_SVIDEO_AIN5_AIN6
- ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3
- ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6
- ADV7180_IRQ1_LOCK
- ADV7180_IRQ1_UNLOCK
- ADV7180_IRQ3_AD_CHANGE
- ADV7180_NTSC_V_BIT_END_MANUAL_NVEND
- ADV7180_NUM_OF_SKIP_FRAMES
- ADV7180_PM_OPS
- ADV7180_PWR_MAN_OFF
- ADV7180_PWR_MAN_ON
- ADV7180_PWR_MAN_RES
- ADV7180_REG_ACE_CTRL1
- ADV7180_REG_ACE_CTRL5
- ADV7180_REG_AGC_ADJ1
- ADV7180_REG_AGC_ADJ2
- ADV7180_REG_ANALOG_CLAMP_CTL
- ADV7180_REG_AUTODETECT_ENABLE
- ADV7180_REG_BRI
- ADV7180_REG_CLAMP_ADJ
- ADV7180_REG_CON
- ADV7180_REG_CSI_SLAVE_ADDR
- ADV7180_REG_CTRL
- ADV7180_REG_CTRL_2
- ADV7180_REG_CVBS_TRIM
- ADV7180_REG_DIFF_MODE
- ADV7180_REG_EXTENDED_OUTPUT_CONTROL
- ADV7180_REG_FLCONTROL
- ADV7180_REG_HUE
- ADV7180_REG_ICONF1
- ADV7180_REG_ICR1
- ADV7180_REG_ICR3
- ADV7180_REG_IDENT
- ADV7180_REG_IMR1
- ADV7180_REG_IMR2
- ADV7180_REG_IMR3
- ADV7180_REG_IMR4
- ADV7180_REG_INPUT_CONTROL
- ADV7180_REG_ISR1
- ADV7180_REG_ISR3
- ADV7180_REG_LOCK_CNT
- ADV7180_REG_MANUAL_WIN_CTL_1
- ADV7180_REG_MANUAL_WIN_CTL_2
- ADV7180_REG_MANUAL_WIN_CTL_3
- ADV7180_REG_NTSC_V_BIT_END
- ADV7180_REG_OUTPUT_CONTROL
- ADV7180_REG_PWR_MAN
- ADV7180_REG_RES_CIR
- ADV7180_REG_RST_CLAMP
- ADV7180_REG_SD_SAT_CB
- ADV7180_REG_SD_SAT_CR
- ADV7180_REG_SHAP_FILTER_CTL_1
- ADV7180_REG_STATUS1
- ADV7180_REG_STATUS3
- ADV7180_REG_VPP_SLAVE_ADDR
- ADV7180_REG_VSYNC_FIELD_CTL_1
- ADV7180_SAT_DEF
- ADV7180_SAT_MAX
- ADV7180_SAT_MIN
- ADV7180_STATUS1_AUTOD_MASK
- ADV7180_STATUS1_AUTOD_NTSC_4_43
- ADV7180_STATUS1_AUTOD_NTSM_M_J
- ADV7180_STATUS1_AUTOD_PAL_60
- ADV7180_STATUS1_AUTOD_PAL_B_G
- ADV7180_STATUS1_AUTOD_PAL_COMB
- ADV7180_STATUS1_AUTOD_PAL_M
- ADV7180_STATUS1_AUTOD_SECAM
- ADV7180_STATUS1_AUTOD_SECAM_525
- ADV7180_STATUS1_IN_LOCK
- ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM
- ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED
- ADV7180_STD_AD_PAL_N_NTSC_J_SECAM
- ADV7180_STD_AD_PAL_N_NTSC_M_SECAM
- ADV7180_STD_NTSC_443
- ADV7180_STD_NTSC_J
- ADV7180_STD_NTSC_M
- ADV7180_STD_PAL60
- ADV7180_STD_PAL_BG
- ADV7180_STD_PAL_COMB_N
- ADV7180_STD_PAL_COMB_N_PED
- ADV7180_STD_PAL_M
- ADV7180_STD_PAL_M_PED
- ADV7180_STD_PAL_N
- ADV7180_STD_PAL_SECAM
- ADV7180_STD_PAL_SECAM_PED
- ADV7182_INPUT_CVBS_AIN1
- ADV7182_INPUT_CVBS_AIN2
- ADV7182_INPUT_CVBS_AIN3
- ADV7182_INPUT_CVBS_AIN4
- ADV7182_INPUT_CVBS_AIN5
- ADV7182_INPUT_CVBS_AIN6
- ADV7182_INPUT_CVBS_AIN7
- ADV7182_INPUT_CVBS_AIN8
- ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2
- ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4
- ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6
- ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8
- ADV7182_INPUT_SVIDEO_AIN1_AIN2
- ADV7182_INPUT_SVIDEO_AIN3_AIN4
- ADV7182_INPUT_SVIDEO_AIN5_AIN6
- ADV7182_INPUT_SVIDEO_AIN7_AIN8
- ADV7182_INPUT_TYPE_CVBS
- ADV7182_INPUT_TYPE_DIFF_CVBS
- ADV7182_INPUT_TYPE_SVIDEO
- ADV7182_INPUT_TYPE_YPBPR
- ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3
- ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6
- ADV7182_REG_INPUT_VIDSEL
- ADV7183_16BIT_OUT
- ADV7183_8BIT_OUT
- ADV7183_ADC_CTRL
- ADV7183_ADC_SWITCH_1
- ADV7183_ADC_SWITCH_2
- ADV7183_ADI_CTRL
- ADV7183_ADI_CTRL_2
- ADV7183_AGC_MODE_CTRL
- ADV7183_ANAL_CLAMP_CTRL
- ADV7183_AUTO_DET_EN
- ADV7183_BRIGHTNESS
- ADV7183_CCAP_1
- ADV7183_CCAP_2
- ADV7183_CGMS_1
- ADV7183_CGMS_2
- ADV7183_CGMS_3
- ADV7183_CHRO_GAIN_CTRL_1
- ADV7183_CHRO_GAIN_CTRL_2
- ADV7183_COMB_FILT_CTRL
- ADV7183_COMPONENT0
- ADV7183_COMPONENT1
- ADV7183_COMPOSITE0
- ADV7183_COMPOSITE1
- ADV7183_COMPOSITE10
- ADV7183_COMPOSITE2
- ADV7183_COMPOSITE3
- ADV7183_COMPOSITE4
- ADV7183_COMPOSITE5
- ADV7183_COMPOSITE6
- ADV7183_COMPOSITE7
- ADV7183_COMPOSITE8
- ADV7183_COMPOSITE9
- ADV7183_CONTRAST
- ADV7183_CRC_EN
- ADV7183_CTI_DNR_CTRL_1
- ADV7183_CTI_DNR_CTRL_2
- ADV7183_CTI_DNR_CTRL_4
- ADV7183_DEF_C
- ADV7183_DEF_Y
- ADV7183_DIGI_CLAMP_CTRL_1
- ADV7183_DRIVE_STR
- ADV7183_EDTV_1
- ADV7183_EDTV_2
- ADV7183_EDTV_3
- ADV7183_EXT_OUT_CTRL
- ADV7183_FREE_LINE_LEN
- ADV7183_GEMSTAR_CTRL_1
- ADV7183_GEMSTAR_CTRL_2
- ADV7183_GEMSTAR_CTRL_3
- ADV7183_GEMSTAR_CTRL_4
- ADV7183_GEMSTAR_CTRL_5
- ADV7183_HS_POS_CTRL_1
- ADV7183_HS_POS_CTRL_2
- ADV7183_HS_POS_CTRL_3
- ADV7183_HUE
- ADV7183_IDENT
- ADV7183_IF_COMP_CTRL
- ADV7183_IN_CTRL
- ADV7183_LETTERBOX_1
- ADV7183_LETTERBOX_2
- ADV7183_LETTERBOX_3
- ADV7183_LETTERBOX_CTRL_1
- ADV7183_LETTERBOX_CTRL_2
- ADV7183_LOCK_CNT
- ADV7183_LUMA_GAIN_CTRL_1
- ADV7183_LUMA_GAIN_CTRL_2
- ADV7183_MAN_WIN_CTRL
- ADV7183_MISC_GAIN_CTRL
- ADV7183_NTSC_COMB_CTRL
- ADV7183_NTSC_F_TOGGLE
- ADV7183_NTSC_V_BEGIN
- ADV7183_NTSC_V_END
- ADV7183_OUT_CTRL
- ADV7183_PAL_COMB_CTRL
- ADV7183_PAL_F_TOGGLE
- ADV7183_PAL_V_BEGIN
- ADV7183_PAL_V_END
- ADV7183_PIX_DELAY_CTRL
- ADV7183_POLARITY
- ADV7183_POW_MANAGE
- ADV7183_RESAMPLE_CTRL
- ADV7183_SD_OFFSET_CB
- ADV7183_SD_OFFSET_CR
- ADV7183_SD_SATURATION_CB
- ADV7183_SD_SATURATION_CR
- ADV7183_SHAP_FILT_CTRL
- ADV7183_SHAP_FILT_CTRL_2
- ADV7183_STATUS_1
- ADV7183_STATUS_2
- ADV7183_STATUS_3
- ADV7183_SVIDEO0
- ADV7183_SVIDEO1
- ADV7183_SVIDEO2
- ADV7183_VBI_INFO
- ADV7183_VD_SEL
- ADV7183_VS_FIELD_CTRL_1
- ADV7183_VS_FIELD_CTRL_2
- ADV7183_VS_FIELD_CTRL_3
- ADV7183_VS_MODE_CTRL
- ADV7183_WSS_1
- ADV7183_WSS_2
- ADV7343_BRIGHTNESS_DEF
- ADV7343_BRIGHTNESS_MAX
- ADV7343_BRIGHTNESS_MIN
- ADV7343_COMPONENT_ID
- ADV7343_COMPONENT_POWER_VALUE
- ADV7343_COMPOSITE_ID
- ADV7343_COMPOSITE_POWER_VALUE
- ADV7343_DAC2_OUTPUT_LEVEL
- ADV7343_FSC_REG0
- ADV7343_FSC_REG1
- ADV7343_FSC_REG2
- ADV7343_FSC_REG3
- ADV7343_GAIN_DEF
- ADV7343_GAIN_MAX
- ADV7343_GAIN_MIN
- ADV7343_H
- ADV7343_HD_MODE_REG1
- ADV7343_HD_MODE_REG1_DEFAULT
- ADV7343_HD_MODE_REG2
- ADV7343_HD_MODE_REG2_DEFAULT
- ADV7343_HD_MODE_REG3
- ADV7343_HD_MODE_REG3_DEFAULT
- ADV7343_HD_MODE_REG4
- ADV7343_HD_MODE_REG4_DEFAULT
- ADV7343_HD_MODE_REG5
- ADV7343_HD_MODE_REG5_DEFAULT
- ADV7343_HD_MODE_REG6
- ADV7343_HD_MODE_REG6_DEFAULT
- ADV7343_HD_MODE_REG7
- ADV7343_HD_MODE_REG7_DEFAULT
- ADV7343_HUE_DEF
- ADV7343_HUE_MAX
- ADV7343_HUE_MIN
- ADV7343_MODE_REG0
- ADV7343_MODE_SELECT_REG
- ADV7343_POWER_MODE_REG
- ADV7343_POWER_MODE_REG_DEFAULT
- ADV7343_REGS_H
- ADV7343_SD_BRIGHTNESS_WSS
- ADV7343_SD_BRIGHTNESS_WSS_DEFAULT
- ADV7343_SD_CGMS_WSS0
- ADV7343_SD_CGMS_WSS0_DEFAULT
- ADV7343_SD_HUE_REG
- ADV7343_SD_HUE_REG_DEFAULT
- ADV7343_SD_MODE_REG1
- ADV7343_SD_MODE_REG1_DEFAULT
- ADV7343_SD_MODE_REG2
- ADV7343_SD_MODE_REG2_DEFAULT
- ADV7343_SD_MODE_REG3
- ADV7343_SD_MODE_REG3_DEFAULT
- ADV7343_SD_MODE_REG4
- ADV7343_SD_MODE_REG4_DEFAULT
- ADV7343_SD_MODE_REG5
- ADV7343_SD_MODE_REG5_DEFAULT
- ADV7343_SD_MODE_REG6
- ADV7343_SD_MODE_REG6_DEFAULT
- ADV7343_SD_MODE_REG7
- ADV7343_SD_MODE_REG7_DEFAULT
- ADV7343_SD_MODE_REG8
- ADV7343_SD_MODE_REG8_DEFAULT
- ADV7343_SOFT_RESET
- ADV7343_SOFT_RESET_DEFAULT
- ADV7343_SVIDEO_ID
- ADV7343_SVIDEO_POWER_VALUE
- ADV7393_BRIGHTNESS_DEF
- ADV7393_BRIGHTNESS_MAX
- ADV7393_BRIGHTNESS_MIN
- ADV7393_COMPONENT_ID
- ADV7393_COMPONENT_POWER_VALUE
- ADV7393_COMPOSITE_ID
- ADV7393_COMPOSITE_POWER_VALUE
- ADV7393_DAC123_OUTPUT_LEVEL
- ADV7393_FSC_REG0
- ADV7393_FSC_REG1
- ADV7393_FSC_REG2
- ADV7393_FSC_REG3
- ADV7393_GAIN_DEF
- ADV7393_GAIN_MAX
- ADV7393_GAIN_MIN
- ADV7393_H
- ADV7393_HD_MODE_REG1
- ADV7393_HD_MODE_REG1_DEFAULT
- ADV7393_HD_MODE_REG2
- ADV7393_HD_MODE_REG2_DEFAULT
- ADV7393_HD_MODE_REG3
- ADV7393_HD_MODE_REG3_DEFAULT
- ADV7393_HD_MODE_REG4
- ADV7393_HD_MODE_REG4_DEFAULT
- ADV7393_HD_MODE_REG5
- ADV7393_HD_MODE_REG5_DEFAULT
- ADV7393_HD_MODE_REG6
- ADV7393_HD_MODE_REG6_DEFAULT
- ADV7393_HD_MODE_REG7
- ADV7393_HD_MODE_REG7_DEFAULT
- ADV7393_HUE_DEF
- ADV7393_HUE_MAX
- ADV7393_HUE_MIN
- ADV7393_MODE_REG0
- ADV7393_MODE_SELECT_REG
- ADV7393_POWER_MODE_REG
- ADV7393_POWER_MODE_REG_DEFAULT
- ADV7393_REGS_H
- ADV7393_SD_BRIGHTNESS_WSS
- ADV7393_SD_BRIGHTNESS_WSS_DEFAULT
- ADV7393_SD_CGMS_WSS0
- ADV7393_SD_CGMS_WSS0_DEFAULT
- ADV7393_SD_HUE_ADJUST
- ADV7393_SD_HUE_ADJUST_DEFAULT
- ADV7393_SD_MODE_REG1
- ADV7393_SD_MODE_REG1_DEFAULT
- ADV7393_SD_MODE_REG2
- ADV7393_SD_MODE_REG2_DEFAULT
- ADV7393_SD_MODE_REG3
- ADV7393_SD_MODE_REG3_DEFAULT
- ADV7393_SD_MODE_REG4
- ADV7393_SD_MODE_REG4_DEFAULT
- ADV7393_SD_MODE_REG5
- ADV7393_SD_MODE_REG5_DEFAULT
- ADV7393_SD_MODE_REG6
- ADV7393_SD_MODE_REG6_DEFAULT
- ADV7393_SD_MODE_REG7
- ADV7393_SD_MODE_REG7_DEFAULT
- ADV7393_SD_MODE_REG8
- ADV7393_SD_MODE_REG8_DEFAULT
- ADV7393_SD_TIMING_REG0
- ADV7393_SD_TIMING_REG0_DEFAULT
- ADV7393_SOFT_RESET
- ADV7393_SOFT_RESET_DEFAULT
- ADV7393_SVIDEO_ID
- ADV7393_SVIDEO_POWER_VALUE
- ADV748X_AFE_NR_PADS
- ADV748X_AFE_SINK_AIN0
- ADV748X_AFE_SINK_AIN1
- ADV748X_AFE_SINK_AIN2
- ADV748X_AFE_SINK_AIN3
- ADV748X_AFE_SINK_AIN4
- ADV748X_AFE_SINK_AIN5
- ADV748X_AFE_SINK_AIN6
- ADV748X_AFE_SINK_AIN7
- ADV748X_AFE_SOURCE
- ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM
- ADV748X_AFE_STD_AD_PAL_BG_NTSC_J_SECAM_PED
- ADV748X_AFE_STD_AD_PAL_N_NTSC_J_SECAM
- ADV748X_AFE_STD_AD_PAL_N_NTSC_M_SECAM
- ADV748X_AFE_STD_NTSC_443
- ADV748X_AFE_STD_NTSC_J
- ADV748X_AFE_STD_NTSC_M
- ADV748X_AFE_STD_PAL60
- ADV748X_AFE_STD_PAL_BG
- ADV748X_AFE_STD_PAL_COMB_N
- ADV748X_AFE_STD_PAL_COMB_N_PED
- ADV748X_AFE_STD_PAL_M
- ADV748X_AFE_STD_PAL_M_PED
- ADV748X_AFE_STD_PAL_N
- ADV748X_AFE_STD_PAL_SECAM
- ADV748X_AFE_STD_PAL_SECAM_PED
- ADV748X_CP_BRI
- ADV748X_CP_BRI_DEF
- ADV748X_CP_BRI_MAX
- ADV748X_CP_BRI_MIN
- ADV748X_CP_CLMP_POS
- ADV748X_CP_CLMP_POS_DIS_AUTO
- ADV748X_CP_CON
- ADV748X_CP_CON_DEF
- ADV748X_CP_CON_MAX
- ADV748X_CP_CON_MIN
- ADV748X_CP_DE_POS_END_LOW
- ADV748X_CP_DE_POS_HIGH
- ADV748X_CP_DE_POS_HIGH_SET
- ADV748X_CP_DE_POS_START_LOW
- ADV748X_CP_HUE
- ADV748X_CP_HUE_DEF
- ADV748X_CP_HUE_MAX
- ADV748X_CP_HUE_MIN
- ADV748X_CP_PAT_GEN
- ADV748X_CP_PAT_GEN_EN
- ADV748X_CP_SAT
- ADV748X_CP_SAT_DEF
- ADV748X_CP_SAT_MAX
- ADV748X_CP_SAT_MIN
- ADV748X_CP_VID_ADJ
- ADV748X_CP_VID_ADJ_2
- ADV748X_CP_VID_ADJ_2_INTERLACED
- ADV748X_CP_VID_ADJ_2_INTERLACED_3D
- ADV748X_CP_VID_ADJ_ENABLE
- ADV748X_CSI2_MAX_SUBDEVS
- ADV748X_CSI2_NR_PADS
- ADV748X_CSI2_SINK
- ADV748X_CSI2_SOURCE
- ADV748X_CSI_FS_AS_LS
- ADV748X_CSI_FS_AS_LS_UNKNOWN
- ADV748X_CSI_VC_REF
- ADV748X_CSI_VC_REF_SHIFT
- ADV748X_HDMI_F0H1
- ADV748X_HDMI_F0H1_HEIGHT_MASK
- ADV748X_HDMI_F1H1
- ADV748X_HDMI_F1H1_INTERLACED
- ADV748X_HDMI_HBACK_PORCH
- ADV748X_HDMI_HBACK_PORCH_MASK
- ADV748X_HDMI_HFRONT_PORCH
- ADV748X_HDMI_HFRONT_PORCH_MASK
- ADV748X_HDMI_HSYNC_WIDTH
- ADV748X_HDMI_HSYNC_WIDTH_MASK
- ADV748X_HDMI_LW1
- ADV748X_HDMI_LW1_DE_REGEN
- ADV748X_HDMI_LW1_VERT_FILTER
- ADV748X_HDMI_LW1_WIDTH_MASK
- ADV748X_HDMI_MAX_HEIGHT
- ADV748X_HDMI_MAX_PIXELCLOCK
- ADV748X_HDMI_MAX_WIDTH
- ADV748X_HDMI_MIN_HEIGHT
- ADV748X_HDMI_MIN_PIXELCLOCK
- ADV748X_HDMI_MIN_WIDTH
- ADV748X_HDMI_NR_PADS
- ADV748X_HDMI_SINK
- ADV748X_HDMI_SOURCE
- ADV748X_HDMI_TMDS_1
- ADV748X_HDMI_TMDS_2
- ADV748X_HDMI_VBACK_PORCH
- ADV748X_HDMI_VBACK_PORCH_MASK
- ADV748X_HDMI_VFRONT_PORCH
- ADV748X_HDMI_VFRONT_PORCH_MASK
- ADV748X_HDMI_VSYNC_WIDTH
- ADV748X_HDMI_VSYNC_WIDTH_MASK
- ADV748X_IO_10
- ADV748X_IO_10_CSI1_EN
- ADV748X_IO_10_CSI4_EN
- ADV748X_IO_10_CSI4_IN_SEL_AFE
- ADV748X_IO_10_PIX_OUT_EN
- ADV748X_IO_CHIP_REV_ID_1
- ADV748X_IO_CHIP_REV_ID_2
- ADV748X_IO_DATAPATH
- ADV748X_IO_DATAPATH_VFREQ_M
- ADV748X_IO_DATAPATH_VFREQ_SHIFT
- ADV748X_IO_PD
- ADV748X_IO_PD_RX_EN
- ADV748X_IO_REG_01
- ADV748X_IO_REG_01_PWRDN2B
- ADV748X_IO_REG_01_PWRDNB
- ADV748X_IO_REG_01_PWRDN_MASK
- ADV748X_IO_REG_04
- ADV748X_IO_REG_04_FORCE_FR
- ADV748X_IO_REG_F2
- ADV748X_IO_REG_F2_READ_AUTO_INC
- ADV748X_IO_REG_FF
- ADV748X_IO_REG_FF_MAIN_RESET
- ADV748X_IO_SLAVE_ADDR_BASE
- ADV748X_IO_VID_STD
- ADV748X_PAGE_CBUS
- ADV748X_PAGE_CEC
- ADV748X_PAGE_CP
- ADV748X_PAGE_DPLL
- ADV748X_PAGE_EDID
- ADV748X_PAGE_EOR
- ADV748X_PAGE_HDMI
- ADV748X_PAGE_INFOFRAME
- ADV748X_PAGE_IO
- ADV748X_PAGE_MAX
- ADV748X_PAGE_REPEATER
- ADV748X_PAGE_SDP
- ADV748X_PAGE_TXA
- ADV748X_PAGE_TXB
- ADV748X_PORT_AIN0
- ADV748X_PORT_AIN1
- ADV748X_PORT_AIN2
- ADV748X_PORT_AIN3
- ADV748X_PORT_AIN4
- ADV748X_PORT_AIN5
- ADV748X_PORT_AIN6
- ADV748X_PORT_AIN7
- ADV748X_PORT_HDMI
- ADV748X_PORT_MAX
- ADV748X_PORT_TTL
- ADV748X_PORT_TXA
- ADV748X_PORT_TXB
- ADV748X_REGMAP_CONF
- ADV748X_REPEATER_EDID_CTL
- ADV748X_REPEATER_EDID_CTL_EN
- ADV748X_REPEATER_EDID_SZ
- ADV748X_REPEATER_EDID_SZ_SHIFT
- ADV748X_SDP_BRI
- ADV748X_SDP_BRI_DEF
- ADV748X_SDP_BRI_MAX
- ADV748X_SDP_BRI_MIN
- ADV748X_SDP_CON
- ADV748X_SDP_CON_DEF
- ADV748X_SDP_CON_MAX
- ADV748X_SDP_CON_MIN
- ADV748X_SDP_DEF
- ADV748X_SDP_DEF_VAL_AUTO_EN
- ADV748X_SDP_DEF_VAL_EN
- ADV748X_SDP_FRP
- ADV748X_SDP_FRP_MASK
- ADV748X_SDP_HUE
- ADV748X_SDP_HUE_DEF
- ADV748X_SDP_HUE_MAX
- ADV748X_SDP_HUE_MIN
- ADV748X_SDP_INSEL
- ADV748X_SDP_MAP_SEL
- ADV748X_SDP_MAP_SEL_RO_MAIN
- ADV748X_SDP_RO_10
- ADV748X_SDP_RO_10_IN_LOCK
- ADV748X_SDP_SAT_DEF
- ADV748X_SDP_SAT_MAX
- ADV748X_SDP_SAT_MIN
- ADV748X_SDP_SD_SAT_U
- ADV748X_SDP_SD_SAT_V
- ADV748X_SDP_VID_SEL
- ADV748X_SDP_VID_SEL_MASK
- ADV748X_SDP_VID_SEL_SHIFT
- ADV7511
- ADV7511_ARC_CTRL_POWER_DOWN
- ADV7511_AUDIO_CFG3_LEN_MASK
- ADV7511_AUDIO_SELECT_DSD
- ADV7511_AUDIO_SELECT_DST
- ADV7511_AUDIO_SELECT_HBR
- ADV7511_AUDIO_SELECT_I2C
- ADV7511_AUDIO_SELECT_SPDIF
- ADV7511_AUDIO_SOURCE_I2S
- ADV7511_AUDIO_SOURCE_SPDIF
- ADV7511_CEC_CTRL_POWER_DOWN
- ADV7511_CEC_I2C_ADDR_DEFAULT
- ADV7511_CSC_ENABLE
- ADV7511_CSC_SCALING_1
- ADV7511_CSC_SCALING_2
- ADV7511_CSC_SCALING_4
- ADV7511_CSC_UPDATE_MODE
- ADV7511_EDID_DETECT
- ADV7511_EDID_I2C_ADDR_DEFAULT
- ADV7511_H
- ADV7511_HDMI_CFG_MODE_DVI
- ADV7511_HDMI_CFG_MODE_HDMI
- ADV7511_HDMI_CFG_MODE_MASK
- ADV7511_I2C_FREQ_ID_CFG_RATE_MASK
- ADV7511_I2S_FORMAT_I2S
- ADV7511_I2S_FORMAT_LEFT_J
- ADV7511_I2S_FORMAT_RIGHT_J
- ADV7511_I2S_SAMPLE_LEN_16
- ADV7511_I2S_SAMPLE_LEN_17
- ADV7511_I2S_SAMPLE_LEN_18
- ADV7511_I2S_SAMPLE_LEN_19
- ADV7511_I2S_SAMPLE_LEN_20
- ADV7511_I2S_SAMPLE_LEN_21
- ADV7511_I2S_SAMPLE_LEN_22
- ADV7511_I2S_SAMPLE_LEN_23
- ADV7511_I2S_SAMPLE_LEN_24
- ADV7511_INPUT_CLOCK_1X
- ADV7511_INPUT_CLOCK_2X
- ADV7511_INPUT_CLOCK_DDR
- ADV7511_INPUT_JUSTIFICATION_EVENLY
- ADV7511_INPUT_JUSTIFICATION_LEFT
- ADV7511_INPUT_JUSTIFICATION_RIGHT
- ADV7511_INPUT_SYNC_PULSE_DE
- ADV7511_INPUT_SYNC_PULSE_HSYNC
- ADV7511_INPUT_SYNC_PULSE_NONE
- ADV7511_INPUT_SYNC_PULSE_VSYNC
- ADV7511_INT0_AUDIO_FIFO_FULL
- ADV7511_INT0_EDID_READY
- ADV7511_INT0_HDCP_AUTHENTICATED
- ADV7511_INT0_HPD
- ADV7511_INT0_VSYNC
- ADV7511_INT1_BKSV
- ADV7511_INT1_CEC_MASK
- ADV7511_INT1_CEC_RX_READY1
- ADV7511_INT1_CEC_RX_READY2
- ADV7511_INT1_CEC_RX_READY3
- ADV7511_INT1_CEC_TX_ARBIT_LOST
- ADV7511_INT1_CEC_TX_READY
- ADV7511_INT1_CEC_TX_RETRY_TIMEOUT
- ADV7511_INT1_DDC_ERROR
- ADV7511_LOW_REFRESH_RATE_24HZ
- ADV7511_LOW_REFRESH_RATE_25HZ
- ADV7511_LOW_REFRESH_RATE_30HZ
- ADV7511_LOW_REFRESH_RATE_NONE
- ADV7511_MAX_ADDRS
- ADV7511_MAX_HEIGHT
- ADV7511_MAX_PIXELCLOCK
- ADV7511_MAX_WIDTH
- ADV7511_MIN_PIXELCLOCK
- ADV7511_MONITOR_DETECT
- ADV7511_PACKET
- ADV7511_PACKET_ACP
- ADV7511_PACKET_ENABLE_ACP
- ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME
- ADV7511_PACKET_ENABLE_AUDIO_SAMPLE
- ADV7511_PACKET_ENABLE_AVI_INFOFRAME
- ADV7511_PACKET_ENABLE_GC
- ADV7511_PACKET_ENABLE_GM
- ADV7511_PACKET_ENABLE_ISRC
- ADV7511_PACKET_ENABLE_MPEG
- ADV7511_PACKET_ENABLE_N_CTS
- ADV7511_PACKET_ENABLE_SPARE1
- ADV7511_PACKET_ENABLE_SPARE2
- ADV7511_PACKET_ENABLE_SPD
- ADV7511_PACKET_GM
- ADV7511_PACKET_I2C_ADDR_DEFAULT
- ADV7511_PACKET_ISRC1
- ADV7511_PACKET_ISRC2
- ADV7511_PACKET_MPEG
- ADV7511_PACKET_SDP
- ADV7511_PACKET_SPARE
- ADV7511_POWER_POWER_DOWN
- ADV7511_REG_AN
- ADV7511_REG_ARC_CTRL
- ADV7511_REG_AUDIO_CFG1
- ADV7511_REG_AUDIO_CFG2
- ADV7511_REG_AUDIO_CFG3
- ADV7511_REG_AUDIO_CONFIG
- ADV7511_REG_AUDIO_INFOFRAME
- ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM
- ADV7511_REG_AUDIO_INFOFRAME_LENGTH
- ADV7511_REG_AUDIO_INFOFRAME_VERSION
- ADV7511_REG_AUDIO_SOURCE
- ADV7511_REG_AUDIO_SUB_SRC0
- ADV7511_REG_AUDIO_SUB_SRC1
- ADV7511_REG_AUDIO_SUB_SRC2
- ADV7511_REG_AUDIO_SUB_SRC3
- ADV7511_REG_AUX_VIC_DETECTED
- ADV7511_REG_AVI_INFOFRAME
- ADV7511_REG_AVI_INFOFRAME_CHECKSUM
- ADV7511_REG_AVI_INFOFRAME_LENGTH
- ADV7511_REG_AVI_INFOFRAME_VERSION
- ADV7511_REG_BCAPS
- ADV7511_REG_BKSV
- ADV7511_REG_BSTATUS
- ADV7511_REG_CEC_CLK_DIV
- ADV7511_REG_CEC_CTRL
- ADV7511_REG_CEC_I2C_ADDR
- ADV7511_REG_CEC_LOG_ADDR_0_1
- ADV7511_REG_CEC_LOG_ADDR_2
- ADV7511_REG_CEC_LOG_ADDR_MASK
- ADV7511_REG_CEC_RX_BUFFERS
- ADV7511_REG_CEC_RX_ENABLE
- ADV7511_REG_CEC_RX_FRAME_DATA0
- ADV7511_REG_CEC_RX_FRAME_HDR
- ADV7511_REG_CEC_RX_FRAME_LEN
- ADV7511_REG_CEC_SOFT_RESET
- ADV7511_REG_CEC_TX_ENABLE
- ADV7511_REG_CEC_TX_FRAME_DATA0
- ADV7511_REG_CEC_TX_FRAME_HDR
- ADV7511_REG_CEC_TX_FRAME_LEN
- ADV7511_REG_CEC_TX_LOW_DRV_CNT
- ADV7511_REG_CEC_TX_RETRY
- ADV7511_REG_CHIP_ID_HIGH
- ADV7511_REG_CHIP_ID_LOW
- ADV7511_REG_CHIP_REVISION
- ADV7511_REG_CSC_LOWER
- ADV7511_REG_CSC_UPPER
- ADV7511_REG_CTS_AUTOMATIC1
- ADV7511_REG_CTS_AUTOMATIC2
- ADV7511_REG_CTS_MANUAL0
- ADV7511_REG_CTS_MANUAL1
- ADV7511_REG_CTS_MANUAL2
- ADV7511_REG_DDC_STATUS
- ADV7511_REG_DE_GENERATOR
- ADV7511_REG_DSD_ENABLE
- ADV7511_REG_EDID_I2C_ADDR
- ADV7511_REG_EDID_READ_CTRL
- ADV7511_REG_EDID_SEGMENT
- ADV7511_REG_GC
- ADV7511_REG_HDCP_HDMI_CFG
- ADV7511_REG_HDCP_STATUS
- ADV7511_REG_HDMI_POWER
- ADV7511_REG_HSYNC_PLACEMENT_MSB
- ADV7511_REG_I2C_FREQ_ID_CFG
- ADV7511_REG_I2S_CONFIG
- ADV7511_REG_I2S_WIDTH
- ADV7511_REG_INFOFRAME_UPDATE
- ADV7511_REG_INPUT_CLK_DIV
- ADV7511_REG_INT
- ADV7511_REG_INT_ENABLE
- ADV7511_REG_N0
- ADV7511_REG_N1
- ADV7511_REG_N2
- ADV7511_REG_PACKET_ENABLE0
- ADV7511_REG_PACKET_ENABLE1
- ADV7511_REG_PACKET_I2C_ADDR
- ADV7511_REG_PIXEL_REPETITION
- ADV7511_REG_PLL_STATUS
- ADV7511_REG_POWER
- ADV7511_REG_POWER2
- ADV7511_REG_POWER2_GATE_INPUT_CLK
- ADV7511_REG_POWER2_HPD_SRC_BOTH
- ADV7511_REG_POWER2_HPD_SRC_CEC
- ADV7511_REG_POWER2_HPD_SRC_HPD
- ADV7511_REG_POWER2_HPD_SRC_MASK
- ADV7511_REG_POWER2_HPD_SRC_NONE
- ADV7511_REG_POWER2_TDMS_ENABLE
- ADV7511_REG_SPDIF_FREQ
- ADV7511_REG_STATUS
- ADV7511_REG_SYNC_ADJUSTMENT
- ADV7511_REG_SYNC_DECODER
- ADV7511_REG_TIMING_GEN_SEQ
- ADV7511_REG_TMDS_CLOCK_INV
- ADV7511_REG_VIC_DETECTED
- ADV7511_REG_VIC_MANUAL
- ADV7511_REG_VIC_SEND
- ADV7511_REG_VIDEO_INPUT_CFG1
- ADV7511_REG_VIDEO_INPUT_CFG2
- ADV7511_SAMPLE_FREQ_176400
- ADV7511_SAMPLE_FREQ_192000
- ADV7511_SAMPLE_FREQ_32000
- ADV7511_SAMPLE_FREQ_44100
- ADV7511_SAMPLE_FREQ_48000
- ADV7511_SAMPLE_FREQ_88200
- ADV7511_SAMPLE_FREQ_96000
- ADV7511_STATUS_HPD
- ADV7511_STATUS_I2S_32BIT_MODE
- ADV7511_STATUS_MONITOR_SENSE
- ADV7511_STATUS_POWER_DOWN_POLARITY
- ADV7511_SYNC_POLARITY_HIGH
- ADV7511_SYNC_POLARITY_LOW
- ADV7511_SYNC_POLARITY_PASSTHROUGH
- ADV7533
- ADV7533_REG_CEC_OFFSET
- ADV7604
- ADV7604_AIN10_11_12_NC_SYNC_4_1
- ADV7604_AIN1_2_3_NC_SYNC_1_2
- ADV7604_AIN4_5_6_NC_SYNC_2_1
- ADV7604_AIN7_8_9_NC_SYNC_3_1
- ADV7604_AIN9_4_5_6_SYNC_2_1
- ADV7604_BUS_ORDER_BGR
- ADV7604_BUS_ORDER_BRG
- ADV7604_BUS_ORDER_GBR
- ADV7604_BUS_ORDER_GRB
- ADV7604_BUS_ORDER_RBG
- ADV7604_BUS_ORDER_RGB
- ADV7604_OP_FORMAT_MODE0
- ADV7604_OP_FORMAT_MODE1
- ADV7604_OP_FORMAT_MODE2
- ADV7604_OP_FORMAT_SEL_10BIT
- ADV7604_OP_MODE_SEL_ADI_CM
- ADV7604_OP_MODE_SEL_DDR_422
- ADV7604_OP_MODE_SEL_DDR_444
- ADV7604_PAD_HDMI_PORT_B
- ADV7604_PAD_HDMI_PORT_C
- ADV7604_PAD_HDMI_PORT_D
- ADV7604_PAD_SOURCE
- ADV7604_PAD_VGA_COMP
- ADV7604_PAD_VGA_RGB
- ADV7604_PAGE_AVLINK
- ADV7604_PAGE_DPP
- ADV7604_PAGE_ESDP
- ADV7604_PAGE_VDP
- ADV7611
- ADV7611_PAD_SOURCE
- ADV7612
- ADV76XX_DR_STR_HIGH
- ADV76XX_DR_STR_MEDIUM_HIGH
- ADV76XX_DR_STR_MEDIUM_LOW
- ADV76XX_FSC
- ADV76XX_HOTPLUG
- ADV76XX_INP_COLOR_SPACE_AUTO
- ADV76XX_INP_COLOR_SPACE_FULL_RGB
- ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601
- ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709
- ADV76XX_INP_COLOR_SPACE_LIM_RGB
- ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601
- ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709
- ADV76XX_INP_COLOR_SPACE_XVYCC_601
- ADV76XX_INP_COLOR_SPACE_XVYCC_709
- ADV76XX_INT1_CONFIG_ACTIVE_HIGH
- ADV76XX_INT1_CONFIG_ACTIVE_LOW
- ADV76XX_INT1_CONFIG_DISABLED
- ADV76XX_INT1_CONFIG_OPEN_DRAIN
- ADV76XX_MAX_ADDRS
- ADV76XX_OP_CH_SEL_BGR
- ADV76XX_OP_CH_SEL_BRG
- ADV76XX_OP_CH_SEL_GBR
- ADV76XX_OP_CH_SEL_GRB
- ADV76XX_OP_CH_SEL_RBG
- ADV76XX_OP_CH_SEL_RGB
- ADV76XX_OP_FORMAT_SEL_12BIT
- ADV76XX_OP_FORMAT_SEL_8BIT
- ADV76XX_OP_MODE_SEL_SDR_422
- ADV76XX_OP_MODE_SEL_SDR_422_2X
- ADV76XX_OP_MODE_SEL_SDR_444
- ADV76XX_OP_SWAP_CB_CR
- ADV76XX_PAD_HDMI_PORT_A
- ADV76XX_PAD_MAX
- ADV76XX_PAGE_AFE
- ADV76XX_PAGE_CEC
- ADV76XX_PAGE_CP
- ADV76XX_PAGE_EDID
- ADV76XX_PAGE_HDMI
- ADV76XX_PAGE_INFOFRAME
- ADV76XX_PAGE_IO
- ADV76XX_PAGE_MAX
- ADV76XX_PAGE_REP
- ADV76XX_PAGE_TEST
- ADV76XX_REG
- ADV76XX_REG_SEQ_TERM
- ADV76XX_RGB_OUT
- ADV7842_AIN10_11_12_NC_SYNC_4_1
- ADV7842_AIN1_2_3_NC_SYNC_1_2
- ADV7842_AIN4_5_6_NC_SYNC_2_1
- ADV7842_AIN7_8_9_NC_SYNC_3_1
- ADV7842_AIN9_4_5_6_SYNC_2_1
- ADV7842_BUS_ORDER_BGR
- ADV7842_BUS_ORDER_BRG
- ADV7842_BUS_ORDER_GBR
- ADV7842_BUS_ORDER_GRB
- ADV7842_BUS_ORDER_RBG
- ADV7842_BUS_ORDER_RGB
- ADV7842_CMD_RAM_TEST
- ADV7842_DR_STR_HIGH
- ADV7842_DR_STR_LOW
- ADV7842_DR_STR_MEDIUM_HIGH
- ADV7842_DR_STR_MEDIUM_LOW
- ADV7842_EDID_PORT_A
- ADV7842_EDID_PORT_B
- ADV7842_EDID_PORT_VGA
- ADV7842_HDMI_COMP_VID_STD_HD_1250P
- ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE
- ADV7842_INP_COLOR_SPACE_AUTO
- ADV7842_INP_COLOR_SPACE_FULL_RGB
- ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601
- ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709
- ADV7842_INP_COLOR_SPACE_LIM_RGB
- ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601
- ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709
- ADV7842_INP_COLOR_SPACE_XVYCC_601
- ADV7842_INP_COLOR_SPACE_XVYCC_709
- ADV7842_MAX_ADDRS
- ADV7842_MODE_COMP
- ADV7842_MODE_HDMI
- ADV7842_MODE_RGB
- ADV7842_MODE_SDP
- ADV7842_OP_CH_SEL_BGR
- ADV7842_OP_CH_SEL_BRG
- ADV7842_OP_CH_SEL_GBR
- ADV7842_OP_CH_SEL_GRB
- ADV7842_OP_CH_SEL_RBG
- ADV7842_OP_CH_SEL_RGB
- ADV7842_OP_FORMAT_MODE0
- ADV7842_OP_FORMAT_MODE1
- ADV7842_OP_FORMAT_MODE2
- ADV7842_OP_FORMAT_SEL_10BIT
- ADV7842_OP_FORMAT_SEL_12BIT
- ADV7842_OP_FORMAT_SEL_8BIT
- ADV7842_OP_MODE_SEL_ADI_CM
- ADV7842_OP_MODE_SEL_DDR_422
- ADV7842_OP_MODE_SEL_DDR_444
- ADV7842_OP_MODE_SEL_SDR_422
- ADV7842_OP_MODE_SEL_SDR_422_2X
- ADV7842_OP_MODE_SEL_SDR_444
- ADV7842_OP_SWAP_CB_CR
- ADV7842_PAD_SOURCE
- ADV7842_RGB_OUT
- ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE
- ADV7842_SDP_VID_STD_CVBS_SD_4x1
- ADV7842_SDP_VID_STD_YC_SD4_x1
- ADV7842_SELECT_HDMI_PORT_A
- ADV7842_SELECT_HDMI_PORT_B
- ADV7842_SELECT_SDP_CVBS
- ADV7842_SELECT_SDP_YC
- ADV7842_SELECT_VGA_COMP
- ADV7842_SELECT_VGA_RGB
- ADV7842_fsc
- ADVANCE
- ADVANCED_BM_WRITE
- ADVANCED_SEQS
- ADVANCE_DMA
- ADVANCE_LP_RING
- ADVANCE_ONLY_NEXT
- ADVANCE_RING
- ADVANCE_RX_PTR
- ADVANCE_TDLS
- ADVANSYS_DEBUG
- ADVANSYS_STATS
- ADVEEP_3550_CONFIG
- ADVEEP_38C0800_CONFIG
- ADVEEP_38C1600_CONFIG
- ADVERTISED
- ADVERTISED_10000baseKR_Full
- ADVERTISED_10000baseKX4_Full
- ADVERTISED_10000baseR_FEC
- ADVERTISED_10000baseT_Full
- ADVERTISED_1000baseKX_Full
- ADVERTISED_1000baseT_Full
- ADVERTISED_1000baseT_Half
- ADVERTISED_100baseT_Full
- ADVERTISED_100baseT_Half
- ADVERTISED_10baseT_Full
- ADVERTISED_10baseT_Half
- ADVERTISED_20000baseKR2_Full
- ADVERTISED_20000baseMLD2_Full
- ADVERTISED_2500baseX_Full
- ADVERTISED_40000baseCR4_Full
- ADVERTISED_40000baseKR4_Full
- ADVERTISED_40000baseLR4_Full
- ADVERTISED_40000baseSR4_Full
- ADVERTISED_56000baseCR4_Full
- ADVERTISED_56000baseKR4_Full
- ADVERTISED_56000baseLR4_Full
- ADVERTISED_56000baseSR4_Full
- ADVERTISED_ALL
- ADVERTISED_ASYM_PAUSE
- ADVERTISED_AUI
- ADVERTISED_Asym_Pause
- ADVERTISED_Autoneg
- ADVERTISED_BNC
- ADVERTISED_Backplane
- ADVERTISED_FIBRE
- ADVERTISED_INTERFACES
- ADVERTISED_MASK
- ADVERTISED_MII
- ADVERTISED_MPD
- ADVERTISED_PAUSE
- ADVERTISED_Pause
- ADVERTISED_TP
- ADVERTISE_1000FULL
- ADVERTISE_1000HALF
- ADVERTISE_1000XFULL
- ADVERTISE_1000XHALF
- ADVERTISE_1000XPAUSE
- ADVERTISE_1000XPSE_ASYM
- ADVERTISE_1000_FULL
- ADVERTISE_1000_HALF
- ADVERTISE_100BASE4
- ADVERTISE_100FULL
- ADVERTISE_100HALF
- ADVERTISE_100_FULL
- ADVERTISE_100_HALF
- ADVERTISE_10FULL
- ADVERTISE_10HALF
- ADVERTISE_10_FULL
- ADVERTISE_10_HALF
- ADVERTISE_2500_FULL
- ADVERTISE_2500_HALF
- ADVERTISE_ALL
- ADVERTISE_CSMA
- ADVERTISE_DEFAULT_CAP
- ADVERTISE_FC_SUPPORTED
- ADVERTISE_FIBER_1000FULL
- ADVERTISE_FIBER_1000HALF
- ADVERTISE_FULL
- ADVERTISE_LPACK
- ADVERTISE_MASK
- ADVERTISE_NPAGE
- ADVERTISE_PAUSE
- ADVERTISE_PAUSE_ALL
- ADVERTISE_PAUSE_ASYM
- ADVERTISE_PAUSE_ASYM_FIBER
- ADVERTISE_PAUSE_CAP
- ADVERTISE_PAUSE_FIBER
- ADVERTISE_RESV
- ADVERTISE_RFAULT
- ADVERTISE_SLCT
- ADVERT_MASK
- ADVFH
- ADVFL
- ADVRTSD_MSK_10G
- ADV_10G_FULL
- ADV_1G_FULL
- ADV_1G_HALF
- ADV_32BALIGN
- ADV_3550_MEMSIZE
- ADV_38C0800_MEMSIZE
- ADV_38C1600_MEMSIZE
- ADV_ACTIVE
- ADV_ASYNC_CARRIER_READY_FAILURE
- ADV_ASYNC_RDMA_FAILURE
- ADV_ASYNC_SCSI_BUS_RESET_DET
- ADV_BUSY
- ADV_CAPINFO_NOLUN
- ADV_CARRIER_BUFSIZE
- ADV_CARRIER_COUNT
- ADV_CARR_T
- ADV_CHIP_ASC3550
- ADV_CHIP_ASC38C0800
- ADV_CHIP_ASC38C1600
- ADV_CHIP_ID_BYTE
- ADV_CHIP_ID_WORD
- ADV_CQ_STOPPER
- ADV_CTRL_REG_ANY_INTR
- ADV_CTRL_REG_CMD_RD_IO_REG
- ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE
- ADV_CTRL_REG_CMD_RESET
- ADV_CTRL_REG_CMD_WR_IO_REG
- ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE
- ADV_CTRL_REG_DPE_INTR
- ADV_CTRL_REG_DPR_INTR
- ADV_CTRL_REG_HOST_INTR
- ADV_CTRL_REG_POWER_DONE
- ADV_CTRL_REG_RES_BIT14
- ADV_CTRL_REG_RMA_INTR
- ADV_CTRL_REG_RTA_INTR
- ADV_CTRL_REG_SEL_INTR
- ADV_DBG_PRT_ADV_SCSI_REQ_Q
- ADV_DVC_CFG
- ADV_DVC_VAR
- ADV_EEPROM_BIG_ENDIAN
- ADV_EEPROM_BIOS_ENABLE
- ADV_EEPROM_CIS_LD
- ADV_EEPROM_INTAB
- ADV_EEPROM_TERM_POL
- ADV_EEP_DELAY_MS
- ADV_EEP_DVC_CFG_BEGIN
- ADV_EEP_DVC_CFG_END
- ADV_EEP_DVC_CTL_BEGIN
- ADV_EEP_MAX_WORD_ADDR
- ADV_ERROR
- ADV_FALSE
- ADV_GET_CARRP
- ADV_GRACOLORKEY
- ADV_HOST_SCSI_BUS_RESET
- ADV_HWC32ARGB
- ADV_HWC32BLEND
- ADV_HWC32ENABLE
- ADV_IDLE
- ADV_INTR_ENABLE_DPE_INTR
- ADV_INTR_ENABLE_DPR_INTR
- ADV_INTR_ENABLE_GLOBAL_INTR
- ADV_INTR_ENABLE_HOST_INTR
- ADV_INTR_ENABLE_RMA_INTR
- ADV_INTR_ENABLE_RST_INTR
- ADV_INTR_ENABLE_RTA_INTR
- ADV_INTR_ENABLE_SEL_INTR
- ADV_INTR_STATUS_INTRA
- ADV_INTR_STATUS_INTRB
- ADV_INTR_STATUS_INTRC
- ADV_MAX_CDB_LEN
- ADV_MAX_LUN
- ADV_MAX_SG_LIST
- ADV_MAX_TID
- ADV_MEM_READB
- ADV_MEM_READW
- ADV_MEM_WRITEB
- ADV_MEM_WRITEDW
- ADV_MEM_WRITEW
- ADV_MOD_DCII_C_OQPSK
- ADV_MOD_DCII_C_QPSK
- ADV_MOD_DCII_I_QPSK
- ADV_MOD_DCII_Q_QPSK
- ADV_MOD_DSS_QPSK
- ADV_MOD_DVB_BPSK
- ADV_MOD_DVB_QPSK
- ADV_MOD_TURBO_16QAM
- ADV_MOD_TURBO_8PSK
- ADV_MOD_TURBO_QPSK
- ADV_NEXT_VPA_MASK
- ADV_NOWAIT
- ADV_RAW_CMP
- ADV_RDMA_IN_CARR_AND_Q_INVALID
- ADV_RISC_CSR_RUN
- ADV_RISC_CSR_SINGLE_STEP
- ADV_RISC_CSR_STOP
- ADV_RISC_TEST_COND
- ADV_RQ_DONE
- ADV_RQ_GOOD
- ADV_SCAN_LUN
- ADV_SCSI_BIT_ID_TYPE
- ADV_SCSI_REQ_Q
- ADV_SG_BLOCK
- ADV_SG_LIST_MAX_BYTE_SIZE
- ADV_SUCCESS
- ADV_TICKLE_A
- ADV_TICKLE_B
- ADV_TICKLE_C
- ADV_TICKLE_NOP
- ADV_TID_TO_TIDMASK
- ADV_TOT_SG_BLOCK
- ADV_TRUE
- ADV_UNIT
- ADV_VIDCOLORKEY
- ADV_VSYNCOFFEN
- ADV_VSYNC_H_OFF
- ADV_VSYNC_L_OFF
- ADXER_MFP_GEN12
- ADXER_MFP_WAC97
- ADXER_MFP_WFLASH
- ADXER_MFP_WI2C
- ADXER_MFP_WMAXTRIX
- ADXER_MFP_WMMC1
- ADXER_MFP_WMMC2
- ADXER_MFP_WSSP1
- ADXER_MFP_WSSP2
- ADXER_MFP_WSSP3
- ADXER_MFP_WSSP4
- ADXER_MFP_WUART1
- ADXER_MFP_WUART2
- ADXER_MFP_WUART3
- ADXER_WDMUX2
- ADXER_WDMUX3
- ADXER_WEXTWAKE0
- ADXER_WEXTWAKE1
- ADXER_WKP
- ADXER_WMSL0
- ADXER_WOST
- ADXER_WOTG
- ADXER_WRTC
- ADXER_WTSI
- ADXER_WUSB2
- ADXER_WUSBH
- ADXER_WUSIM0
- ADXER_WUSIM1
- ADXL345
- ADXL345_BASE_RATE_NANO_HZ
- ADXL345_BW_RATE
- ADXL345_CHANNEL
- ADXL345_DATA_FORMAT_16G
- ADXL345_DATA_FORMAT_2G
- ADXL345_DATA_FORMAT_4G
- ADXL345_DATA_FORMAT_8G
- ADXL345_DATA_FORMAT_FULL_RES
- ADXL345_DEVID
- ADXL345_MAX_SPI_FREQ_HZ
- ADXL345_POWER_CTL_MEASURE
- ADXL345_POWER_CTL_STANDBY
- ADXL345_REG_BW_RATE
- ADXL345_REG_DATAX0
- ADXL345_REG_DATAY0
- ADXL345_REG_DATAZ0
- ADXL345_REG_DATA_AXIS
- ADXL345_REG_DATA_FORMAT
- ADXL345_REG_DEVID
- ADXL345_REG_OFSX
- ADXL345_REG_OFSY
- ADXL345_REG_OFSZ
- ADXL345_REG_OFS_AXIS
- ADXL345_REG_POWER_CTL
- ADXL346_2D_LANDSCAPE_NEG
- ADXL346_2D_LANDSCAPE_POS
- ADXL346_2D_ORIENT
- ADXL346_2D_PORTRAIT_NEG
- ADXL346_2D_PORTRAIT_POS
- ADXL346_2D_VALID
- ADXL346_3D_BACK
- ADXL346_3D_BOTTOM
- ADXL346_3D_FRONT
- ADXL346_3D_LEFT
- ADXL346_3D_ORIENT
- ADXL346_3D_RIGHT
- ADXL346_3D_TOP
- ADXL346_3D_VALID
- ADXL34X_CMD_MULTB
- ADXL34X_CMD_READ
- ADXL34X_READCMD
- ADXL34X_READMB_CMD
- ADXL34X_WRITECMD
- ADXL372_ACCEL_CHANNEL
- ADXL372_ACTIVITY
- ADXL372_ACTIVITY2
- ADXL372_BW_1600HZ
- ADXL372_BW_200HZ
- ADXL372_BW_3200HZ
- ADXL372_BW_400HZ
- ADXL372_BW_800HZ
- ADXL372_DEFAULT
- ADXL372_DEVID
- ADXL372_DEVID_MST
- ADXL372_DEVID_VAL
- ADXL372_FIFO_BYPASSED
- ADXL372_FIFO_CTL
- ADXL372_FIFO_CTL_FORMAT_MODE
- ADXL372_FIFO_CTL_FORMAT_MSK
- ADXL372_FIFO_CTL_MODE_MODE
- ADXL372_FIFO_CTL_MODE_MSK
- ADXL372_FIFO_CTL_SAMPLES_MODE
- ADXL372_FIFO_CTL_SAMPLES_MSK
- ADXL372_FIFO_DATA
- ADXL372_FIFO_ENTRIES_1
- ADXL372_FIFO_ENTRIES_2
- ADXL372_FIFO_OLD_SAVED
- ADXL372_FIFO_SAMPLES
- ADXL372_FIFO_SIZE
- ADXL372_FIFO_STREAMED
- ADXL372_FIFO_TRIGGERED
- ADXL372_FULL_BW_MEASUREMENT
- ADXL372_HPF
- ADXL372_INACTIVITY
- ADXL372_INSTANT_ON
- ADXL372_INT1_MAP
- ADXL372_INT1_MAP_ACT_MODE
- ADXL372_INT1_MAP_ACT_MSK
- ADXL372_INT1_MAP_AWAKE_MODE
- ADXL372_INT1_MAP_AWAKE_MSK
- ADXL372_INT1_MAP_DATA_RDY_MODE
- ADXL372_INT1_MAP_DATA_RDY_MSK
- ADXL372_INT1_MAP_FIFO_FULL_MODE
- ADXL372_INT1_MAP_FIFO_FULL_MSK
- ADXL372_INT1_MAP_FIFO_OVR_MODE
- ADXL372_INT1_MAP_FIFO_OVR_MSK
- ADXL372_INT1_MAP_FIFO_RDY_MODE
- ADXL372_INT1_MAP_FIFO_RDY_MSK
- ADXL372_INT1_MAP_INACT_MODE
- ADXL372_INT1_MAP_INACT_MSK
- ADXL372_INT1_MAP_LOW_MODE
- ADXL372_INT1_MAP_LOW_MSK
- ADXL372_INT2_MAP
- ADXL372_LINKED
- ADXL372_LOOPED
- ADXL372_MEASURE
- ADXL372_MEASURE_BANDWIDTH_MODE
- ADXL372_MEASURE_BANDWIDTH_MSK
- ADXL372_MEASURE_LINKLOOP_MODE
- ADXL372_MEASURE_LINKLOOP_MSK
- ADXL372_ODR_1600HZ
- ADXL372_ODR_3200HZ
- ADXL372_ODR_400HZ
- ADXL372_ODR_6400HZ
- ADXL372_ODR_800HZ
- ADXL372_OFFSET_X
- ADXL372_OFFSET_Y
- ADXL372_OFFSET_Z
- ADXL372_PARTID
- ADXL372_PARTID_VAL
- ADXL372_POWER_CTL
- ADXL372_POWER_CTL_MODE
- ADXL372_POWER_CTL_MODE_MSK
- ADXL372_RESET
- ADXL372_RESET_CODE
- ADXL372_REVID
- ADXL372_SELF_TEST
- ADXL372_STANDBY
- ADXL372_STATUS_1
- ADXL372_STATUS_1_AWAKE
- ADXL372_STATUS_1_DATA_RDY
- ADXL372_STATUS_1_ERR_USR_REGS
- ADXL372_STATUS_1_FIFO_FULL
- ADXL372_STATUS_1_FIFO_OVR
- ADXL372_STATUS_1_FIFO_RDY
- ADXL372_STATUS_1_USR_NVM_BUSY
- ADXL372_STATUS_2
- ADXL372_TIME_ACT
- ADXL372_TIME_INACT_H
- ADXL372_TIME_INACT_L
- ADXL372_TIMING
- ADXL372_TIMING_ODR_MODE
- ADXL372_TIMING_ODR_MSK
- ADXL372_USCALE
- ADXL372_WAKE_UP
- ADXL372_XYZ_FIFO
- ADXL372_XYZ_PEAK_FIFO
- ADXL372_XY_FIFO
- ADXL372_XZ_FIFO
- ADXL372_X_DATA_H
- ADXL372_X_DATA_L
- ADXL372_X_FIFO
- ADXL372_X_MAXPEAK_H
- ADXL372_X_MAXPEAK_L
- ADXL372_X_THRESH_ACT2_H
- ADXL372_X_THRESH_ACT2_L
- ADXL372_X_THRESH_ACT_H
- ADXL372_X_THRESH_ACT_L
- ADXL372_X_THRESH_INACT_H
- ADXL372_X_THRESH_INACT_L
- ADXL372_YZ_FIFO
- ADXL372_Y_DATA_H
- ADXL372_Y_DATA_L
- ADXL372_Y_FIFO
- ADXL372_Y_MAXPEAK_H
- ADXL372_Y_MAXPEAK_L
- ADXL372_Y_THRESH_ACT2_H
- ADXL372_Y_THRESH_ACT2_L
- ADXL372_Y_THRESH_ACT_H
- ADXL372_Y_THRESH_ACT_L
- ADXL372_Y_THRESH_INACT_H
- ADXL372_Y_THRESH_INACT_L
- ADXL372_Z_DATA_H
- ADXL372_Z_DATA_L
- ADXL372_Z_FIFO
- ADXL372_Z_MAXPEAK_H
- ADXL372_Z_MAXPEAK_L
- ADXL372_Z_THRESH_ACT2_H
- ADXL372_Z_THRESH_ACT2_L
- ADXL372_Z_THRESH_ACT_H
- ADXL372_Z_THRESH_ACT_L
- ADXL372_Z_THRESH_INACT_H
- ADXL372_Z_THRESH_INACT_L
- ADXL375
- ADXL_ACT_ACDC
- ADXL_ACT_X_EN
- ADXL_ACT_Y_EN
- ADXL_ACT_Z_EN
- ADXL_AUTO_SLEEP
- ADXL_DEADZONE_ANGLE_0p0
- ADXL_DEADZONE_ANGLE_10p8
- ADXL_DEADZONE_ANGLE_14p4
- ADXL_DEADZONE_ANGLE_18p0
- ADXL_DEADZONE_ANGLE_21p6
- ADXL_DEADZONE_ANGLE_25p2
- ADXL_DEADZONE_ANGLE_3p6
- ADXL_DEADZONE_ANGLE_7p2
- ADXL_DEBUG
- ADXL_EN_ORIENTATION_2D
- ADXL_EN_ORIENTATION_2D_3D
- ADXL_EN_ORIENTATION_3D
- ADXL_FIFO_BYPASS
- ADXL_FIFO_FIFO
- ADXL_FIFO_STREAM
- ADXL_FIXEDRES_MAX_VAL
- ADXL_FULLRES_MAX_VAL
- ADXL_FULL_RES
- ADXL_IDX_FORWARD_TRANSLATE
- ADXL_IDX_GET_ADDR_PARAMS
- ADXL_INACT_ACDC
- ADXL_INACT_X_EN
- ADXL_INACT_Y_EN
- ADXL_INACT_Z_EN
- ADXL_LINK
- ADXL_LP_FILTER_DIVISOR_128
- ADXL_LP_FILTER_DIVISOR_16
- ADXL_LP_FILTER_DIVISOR_2
- ADXL_LP_FILTER_DIVISOR_256
- ADXL_LP_FILTER_DIVISOR_32
- ADXL_LP_FILTER_DIVISOR_4
- ADXL_LP_FILTER_DIVISOR_64
- ADXL_LP_FILTER_DIVISOR_8
- ADXL_MAX_COMPONENTS
- ADXL_RANGE_PM_16g
- ADXL_RANGE_PM_2g
- ADXL_RANGE_PM_4g
- ADXL_RANGE_PM_8g
- ADXL_REVISION
- ADXL_SUPPRESS
- ADXL_TAP_X_EN
- ADXL_TAP_Y_EN
- ADXL_TAP_Z_EN
- ADXL_X_AXIS
- ADXL_Y_AXIS
- ADXL_Z_AXIS
- ADXRS450_AMP
- ADXRS450_CHK
- ADXRS450_CST
- ADXRS450_DNC1
- ADXRS450_FAIL
- ADXRS450_FAULT1
- ADXRS450_GET_ST
- ADXRS450_HICST1
- ADXRS450_LOCST1
- ADXRS450_MAX_RX
- ADXRS450_MAX_TX
- ADXRS450_NVM
- ADXRS450_OV
- ADXRS450_P
- ADXRS450_PID1
- ADXRS450_PLL
- ADXRS450_POR
- ADXRS450_PWR
- ADXRS450_Q
- ADXRS450_QUAD1
- ADXRS450_RATE1
- ADXRS450_READ_DATA
- ADXRS450_SENSOR_DATA
- ADXRS450_SNH
- ADXRS450_SNL
- ADXRS450_STARTUP_DELAY
- ADXRS450_TEMP1
- ADXRS450_UV
- ADXRS450_WRERR_MASK
- ADXRS450_WRITE_DATA
- ADXR_L2
- ADXR_R0
- ADXR_R1
- ADXR_R2
- ADXR_R3
- ADXR_R4
- ADXR_R5
- AD_AC97_ACIC
- AD_AC97_ACIC_ACIE
- AD_AC97_ACIC_ACRD
- AD_AC97_ACIC_ACRDY
- AD_AC97_ACIC_ASOE
- AD_AC97_ACIC_FSDH
- AD_AC97_ACIC_FSYH
- AD_AC97_ACIC_VSRM
- AD_AC97_BASE
- AD_AC97_PWR_ADC
- AD_AC97_PWR_CTL
- AD_AC97_PWR_DAC
- AD_AC97_PWR_PR0
- AD_AC97_PWR_PR1
- AD_AC97_RESET
- AD_AC97_SR0
- AD_AC97_SR0_48K
- AD_AC97_SR1
- AD_ACTOR_CHURN_TIMER
- AD_ADC_STATE
- AD_ADDR
- AD_ADDR_ALIGN
- AD_ADDR_MASK
- AD_AEN
- AD_AG32
- AD_AGGREGATE_WAIT_TIME
- AD_AGGREGATOR_SELECTION_TIMER
- AD_ALPHA_C_MASK
- AD_ALPHA_C_SHIFT
- AD_BLT
- AD_BLUE_C_MASK
- AD_BLUE_C_SHIFT
- AD_BS
- AD_BYTE_F
- AD_CHAN_ADC
- AD_CHAN_RES
- AD_CHAN_SYN
- AD_CHAN_WAV
- AD_CHURN
- AD_CHURN_DETECTION_TIME
- AD_CHURN_MONITOR
- AD_CLEAR_REG
- AD_CLK
- AD_CLK_B_MARK
- AD_CLK_MARK
- AD_CMD
- AD_CMD_REG
- AD_COLLECTOR_MAX_DELAY
- AD_COMP_0_MASK
- AD_COMP_0_SHIFT
- AD_COMP_1_MASK
- AD_COMP_1_SHIFT
- AD_COMP_2_MASK
- AD_COMP_2_SHIFT
- AD_COMP_3_MASK
- AD_COMP_3_SHIFT
- AD_CONTROL
- AD_CURRENT_WHILE_TIMER
- AD_DATA
- AD_DI_B_MARK
- AD_DI_MARK
- AD_DMA_ADC
- AD_DMA_ADCBA
- AD_DMA_ADCBC
- AD_DMA_ADCCA
- AD_DMA_ADCCC
- AD_DMA_ADCIB
- AD_DMA_ADCIC
- AD_DMA_CHSS
- AD_DMA_CHSS_ADCS
- AD_DMA_CHSS_RESS
- AD_DMA_CHSS_SYNS
- AD_DMA_CHSS_WAVS
- AD_DMA_DISR
- AD_DMA_DISR_ADCI
- AD_DMA_DISR_PMAE
- AD_DMA_DISR_PMAI
- AD_DMA_DISR_PTAE
- AD_DMA_DISR_PTAI
- AD_DMA_DISR_RESI
- AD_DMA_DISR_SEPS
- AD_DMA_DISR_SYNI
- AD_DMA_DISR_WAVI
- AD_DMA_EOL
- AD_DMA_IBC
- AD_DMA_ICC
- AD_DMA_IM
- AD_DMA_IM_CNT
- AD_DMA_IM_DIS
- AD_DMA_IM_EOL
- AD_DMA_IM_SGD
- AD_DMA_LOOP
- AD_DMA_RES
- AD_DMA_RESBA
- AD_DMA_RESBC
- AD_DMA_RESCA
- AD_DMA_RESCC
- AD_DMA_RESIB
- AD_DMA_RESIC
- AD_DMA_SFLG
- AD_DMA_SGDE
- AD_DMA_SGDS
- AD_DMA_SYNBA
- AD_DMA_SYNBC
- AD_DMA_SYNCA
- AD_DMA_SYNCC
- AD_DMA_SYNIB
- AD_DMA_SYNIC
- AD_DMA_SYNTH
- AD_DMA_WAV
- AD_DMA_WAVBA
- AD_DMA_WAVBC
- AD_DMA_WAVCA
- AD_DMA_WAVCC
- AD_DMA_WAVIB
- AD_DMA_WAVIC
- AD_DO_B_MARK
- AD_DO_MARK
- AD_DS_CCS
- AD_DS_CCS_ADO
- AD_DS_CCS_CLKEN
- AD_DS_CCS_PDALL
- AD_DS_CCS_REO
- AD_DS_CCS_SYU
- AD_DS_CCS_WAU
- AD_DS_CCS_XTD
- AD_DS_MEMSIZE
- AD_DS_RAMC
- AD_DS_RAMC_ACRQ
- AD_DS_RAMC_AD16
- AD_DS_RAMC_ADEN
- AD_DS_RAMC_ADST
- AD_DS_RAMC_REEN
- AD_DS_RAMC_RERQ
- AD_DS_RES
- AD_DS_RES_RES
- AD_DS_SYDA
- AD_DS_SYDA_LSYA
- AD_DS_SYDA_LSYM
- AD_DS_SYDA_RSYA
- AD_DS_SYDA_RSYM
- AD_DS_WADA
- AD_DS_WADA_LWAA
- AD_DS_WADA_LWAM
- AD_DS_WADA_RWAA
- AD_DS_WADA_RWAM
- AD_DS_WAS
- AD_DS_WAS_WAS
- AD_DS_WSMC
- AD_DS_WSMC_SYEN
- AD_DS_WSMC_SYRQ
- AD_DS_WSMC_WA16
- AD_DS_WSMC_WAEN
- AD_DS_WSMC_WARQ
- AD_DS_WSMC_WAST
- AD_DUPLEX_KEY_MASKS
- AD_FAST_PERIODIC
- AD_FAST_PERIODIC_TIME
- AD_FIFO_REG
- AD_GPIO_IP
- AD_GPIO_IPC
- AD_GPIO_OP
- AD_GREEN_C_MASK
- AD_GREEN_C_SHIFT
- AD_HIBIT
- AD_IF
- AD_IFE
- AD_INTR_MASK
- AD_IU_EXT_ERASED
- AD_LACP_FAST
- AD_LACP_SLOW
- AD_LINK_SPEED_100000MBPS
- AD_LINK_SPEED_10000MBPS
- AD_LINK_SPEED_1000MBPS
- AD_LINK_SPEED_100MBPS
- AD_LINK_SPEED_10MBPS
- AD_LINK_SPEED_14000MBPS
- AD_LINK_SPEED_1MBPS
- AD_LINK_SPEED_20000MBPS
- AD_LINK_SPEED_25000MBPS
- AD_LINK_SPEED_2500MBPS
- AD_LINK_SPEED_40000MBPS
- AD_LINK_SPEED_50000MBPS
- AD_LINK_SPEED_5000MBPS
- AD_LINK_SPEED_56000MBPS
- AD_LONG_TIMEOUT
- AD_LONG_TIMEOUT_TIME
- AD_LUT
- AD_MAGIC
- AD_MARKER_INFORMATION_SUBTYPE
- AD_MARKER_RESPONSE_SUBTYPE
- AD_MASK
- AD_MAX_STATES
- AD_MAX_TX_IN_SECOND
- AD_MIDI_MEMSIZE
- AD_MISC_CTL
- AD_MISC_CTL_ALSR
- AD_MISC_CTL_ARSR
- AD_MISC_CTL_DACZ
- AD_MISC_CTL_DLSR
- AD_MISC_CTL_DRSR
- AD_MUX_ATTACHED
- AD_MUX_COLLECTING_DISTRIBUTING
- AD_MUX_DETACHED
- AD_MUX_DUMMY
- AD_MUX_WAITING
- AD_NCS_MARK
- AD_NCS_N_B_MARK
- AD_NCS_N_MARK
- AD_NEG_REF
- AD_NO_CHURN
- AD_NO_PERIODIC
- AD_OPL_MEMSIZE
- AD_PALETTE
- AD_PARTNER_CHURN_TIMER
- AD_PERIODIC_DUMMY
- AD_PERIODIC_TIMER
- AD_PERIODIC_TX
- AD_PIXEL_S_MASK
- AD_PIXEL_S_SHIFT
- AD_PORT_ACTOR_CHURN
- AD_PORT_BEGIN
- AD_PORT_CHURNED
- AD_PORT_LACP_ENABLED
- AD_PORT_MATCHED
- AD_PORT_MOVED
- AD_PORT_PARTNER_CHURN
- AD_PORT_READY
- AD_PORT_READY_N
- AD_PORT_SELECTED
- AD_PORT_STANDBY
- AD_POS_REF
- AD_READ
- AD_RED_C_MASK
- AD_RED_C_SHIFT
- AD_RST
- AD_RX_CURRENT
- AD_RX_DEFAULTED
- AD_RX_DUMMY
- AD_RX_EXPIRED
- AD_RX_INITIALIZE
- AD_RX_LACP_DISABLED
- AD_RX_PORT_DISABLED
- AD_SD_CHANNEL
- AD_SD_CHANNEL_NO_SAMP_FREQ
- AD_SD_COMM_CHAN_MASK
- AD_SD_DIFF_CHANNEL
- AD_SD_MODE_CONTINUOUS
- AD_SD_MODE_IDLE
- AD_SD_MODE_POWERDOWN
- AD_SD_MODE_SINGLE
- AD_SD_REG_COMM
- AD_SD_REG_DATA
- AD_SD_SHORTED_CHANNEL
- AD_SD_SUPPLY_CHANNEL
- AD_SD_TEMP_CHANNEL
- AD_SHORT_TIMEOUT
- AD_SHORT_TIMEOUT_TIME
- AD_SLOW_PERIODIC
- AD_SLOW_PERIODIC_TIME
- AD_SPEED_KEY_MASKS
- AD_SP_MASK
- AD_SP_SHIFT
- AD_STANDBY
- AD_STATE_AGGREGATION
- AD_STATE_COLLECTING
- AD_STATE_DEFAULTED
- AD_STATE_DISTRIBUTING
- AD_STATE_EXPIRED
- AD_STATE_LACP_ACTIVITY
- AD_STATE_LACP_TIMEOUT
- AD_STATE_SYNCHRONIZATION
- AD_ST_BRIDGE
- AD_ST_MASK
- AD_ST_MWRAP
- AD_ST_SHIFT
- AD_ST_SLAVE
- AD_ST_SWRAP
- AD_SZ_16K
- AD_SZ_4K
- AD_SZ_8K
- AD_SZ_BASE
- AD_SZ_MASK
- AD_SZ_SHIFT
- AD_SZ_SZD
- AD_TH
- AD_TIMER_INTERVAL
- AD_TRANSMIT
- AD_TX_DUMMY
- AD_TYPE_LACPDU
- AD_TYPE_MARKER
- AD_USER_KEY_MASKS
- AD_WAIT_WHILE_TIMER
- AD_WAV_STATE
- AD_WB
- AD_WRITE
- AD_YT
- AE
- AE10
- AE11
- AE12
- AE14
- AE15
- AE16
- AE18
- AE19
- AE25
- AE26
- AE5_CA0113_OUT_SET_COMMANDS
- AE5_HEADPHONE_GAIN_ENUM
- AE5_HEADPHONE_GAIN_MAX
- AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS
- AE5_SOUND_FILTER_ENUM
- AE5_SOUND_FILTER_MAX
- AE7
- AE8
- AEAD_CTX
- AEAD_DESC_JOB_IO_LEN
- AEAD_EXPLICIT_DATA_SIZE
- AEAD_H_SIZE
- AEAD_TYPE_LAST
- AEB
- AEC
- AECH
- AECNT
- AEC_1p2
- AEC_1p4
- AEC_2p3
- AEC_BND
- AEC_FULL
- AEC_NO_LIMIT
- AEC_ON
- AEC_ON_OFF
- AEGIS128_BLOCK_ALIGN
- AEGIS128_BLOCK_SIZE
- AEGIS128_KEY_SIZE
- AEGIS128_MAX_AUTH_SIZE
- AEGIS128_MIN_AUTH_SIZE
- AEGIS128_NONCE_SIZE
- AEGIS128_STATE_BLOCKS
- AEGIS_ALIGNED
- AEGIS_BLOCK_ALIGN
- AEGIS_BLOCK_SIZE
- AEL1002_LB_EN
- AEL1002_PWR_DOWN_HI
- AEL1002_PWR_DOWN_LO
- AEL1002_XFI_EQL
- AEL100X_TX_CONFIG1
- AEL2005_GPIO_CTRL
- AEL2005_GPIO_STAT
- AEL2005_MODDET_IRQ
- AEL2005_OPT_EDC_NAME
- AEL2005_TWX_EDC_NAME
- AEL2020_GPIO_0
- AEL2020_GPIO_1
- AEL2020_GPIO_CFG
- AEL2020_GPIO_CTRL
- AEL2020_GPIO_INTR
- AEL2020_GPIO_LSTAT
- AEL2020_GPIO_MODDET
- AEL2020_GPIO_SDA
- AEL2020_GPIO_STAT
- AEL2020_TWX_EDC_NAME
- AEL_I2C_CTRL
- AEL_I2C_DATA
- AEL_I2C_STAT
- AEL_OPT_SETTINGS
- AEM1_NUM_ENERGY_REGS
- AEM1_NUM_SENSORS
- AEM2_NUM_ENERGY_REGS
- AEM2_NUM_PCAP_REGS
- AEM2_NUM_SENSORS
- AEM2_NUM_TEMP_REGS
- AEM_CLEAR_REG_MASK
- AEM_CLOCK_ELEMENT
- AEM_CONTROL_ELEMENT
- AEM_DEFAULT_POWER_INTERVAL
- AEM_ELEMENT_CMD
- AEM_ENERGY_ELEMENT
- AEM_EXHAUST_ELEMENT
- AEM_FIND_FW_CMD
- AEM_FW_INSTANCE_CMD
- AEM_MIN_POWER_INTERVAL
- AEM_MODULE_TYPE_ID
- AEM_NETFN
- AEM_NUM_ENERGY_REGS
- AEM_NUM_SENSORS
- AEM_POWER_CAP_ELEMENT
- AEM_POWER_ELEMENT
- AEM_READ_BUFFER
- AEM_READ_ELEMENT_CFG
- AEM_READ_ELEMENT_CFG2
- AEM_READ_REGISTER
- AEM_SET_REG_MASK
- AEM_WRITE_REGISTER
- AENC_FNC
- AEN_AEN_LOST
- AEN_AEN_SFP_IN
- AEN_AEN_SFP_OUT
- AEN_DCBX_CHG
- AEN_FW_INIT_DONE
- AEN_FW_INIT_FAIL
- AEN_IDC_CMPLT
- AEN_IDC_EXT
- AEN_IDC_REQ
- AEN_LINK_DOWN
- AEN_LINK_UP
- AEN_MAILBOX_REGISTER_COUNT_FX00
- AEN_SYS_ERR
- AEP_MASK
- AEP_SHIFT_BIT
- AEQRX_REG_BANK_0
- AEQRX_REG_BANK_1
- AEQRX_SLCAL0_CTRL0
- AEQRX_SLCAL1_CTRL0
- AEQ_CONTROL1
- AEQ_CONTROL1_ENABLE
- AEQ_CONTROL1_FREEZE
- AEQ_CREATED
- AEQ_FRC_EQ
- AEQ_FRC_EQ_FORCE
- AEQ_FRC_EQ_FORCE_VAL
- AEQ_FRC_EQ_VAL_MASK
- AEQ_FRC_EQ_VAL_SHIFT
- AER
- AEROFLEX_UT699
- AERO_SERIES
- AER_AGENT_COMPLETER
- AER_AGENT_COMPLETER_MASK
- AER_AGENT_RECEIVER
- AER_AGENT_REQUESTER
- AER_AGENT_REQUESTER_MASK
- AER_AGENT_TRANSMITTER
- AER_AGENT_TRANSMITTER_MASK
- AER_CORRECTABLE
- AER_DATA_LINK_LAYER_ERROR
- AER_DATA_LINK_LAYER_ERROR_MASK
- AER_ENABLED
- AER_ERROR_SOURCES_MAX
- AER_FATAL
- AER_GET_AGENT
- AER_GET_LAYER_ERROR
- AER_LOG_TLP_MASKS
- AER_MAX_MULTI_ERR_DEVICES
- AER_MAX_TYPEOF_COR_ERRS
- AER_MAX_TYPEOF_UNCOR_ERRS
- AER_NONFATAL
- AER_PHYSICAL_LAYER_ERROR
- AER_PHYSICAL_LAYER_ERROR_MASK
- AER_RECOVER_RING_ORDER
- AER_RECOVER_RING_SIZE
- AER_TRANSACTION_LAYER_ERROR
- AES32
- AES32_CHANNELS
- AESCCMP_ENCRYPTION
- AESCMAC_ENCRYPTION
- AESIE
- AESIF
- AESLEN0
- AESLEN1
- AESMAC_and_BYPASS
- AESNI_ALIGN
- AESNI_ALIGN_ATTR
- AESNI_ALIGN_EXTRA
- AESOP0
- AESOP1
- AESST
- AESS_AUTO_GATING_ENABLE_OFFSET
- AESS_AUTO_GATING_ENABLE_SHIFT
- AES_128_BIT
- AES_128_KEY
- AES_128_KEY_0
- AES_128_KEY_1
- AES_128_KEY_2
- AES_128_KEY_3
- AES_128_RANDOM_0
- AES_128_RANDOM_1
- AES_192_BIT
- AES_192_KEY
- AES_256_BIT
- AES_256_KEY
- AES_32_DATA_IN
- AES_32_DATA_OUT_
- AES_32_KEY_
- AES_AADLENR
- AES_ALPHAR
- AES_AUTH_TAG_ERR
- AES_BLOCK128
- AES_BLOCK_32
- AES_BLOCK_LEN
- AES_BLOCK_MASK
- AES_BLOCK_SIZE
- AES_BLOCK_WORDS
- AES_BUF_ORDER
- AES_BUF_SIZE
- AES_CBC
- AES_CCM
- AES_CCM_H
- AES_CFB
- AES_CLENR
- AES_CMAC_H
- AES_CMAC_INIT
- AES_CMAC_SIZE0
- AES_CMD0
- AES_CMD1
- AES_CMD2
- AES_CR
- AES_CRYPT
- AES_CR_LOADSEED
- AES_CR_START
- AES_CR_SWRST
- AES_CTR
- AES_CTRLA_REG
- AES_CTRL_B
- AES_CTRL_CBC
- AES_CTRL_DCA
- AES_CTRL_DECRYPT
- AES_CTRL_ENCRYPT
- AES_CTRL_SCA
- AES_CTRL_START
- AES_CTRL_WRKEY
- AES_CTRR
- AES_CT_CTRL_HDR
- AES_DIR_DECRYPT
- AES_DIR_ENCRYPT
- AES_DROUND01
- AES_DROUND01_L
- AES_DROUND23
- AES_DROUND23_L
- AES_DSTA_REG
- AES_ECB
- AES_EFUSE_ENABLE
- AES_EMR
- AES_EMR_APEN
- AES_EMR_APM
- AES_EMR_APM_IPSEC
- AES_EMR_APM_SSL
- AES_EMR_NHEAD
- AES_EMR_NHEAD_MASK
- AES_EMR_NHEAD_OFFSET
- AES_EMR_PADLEN
- AES_EMR_PADLEN_MASK
- AES_EMR_PADLEN_OFFSET
- AES_EMR_PLIPD
- AES_EMR_PLIPEN
- AES_ENABLED
- AES_ENDPROC
- AES_ENTRY
- AES_EROUND01
- AES_EROUND01_L
- AES_EROUND23
- AES_EROUND23_L
- AES_FLAGS_BUSY
- AES_FLAGS_CBC
- AES_FLAGS_CFB128
- AES_FLAGS_CFB16
- AES_FLAGS_CFB32
- AES_FLAGS_CFB64
- AES_FLAGS_CFB8
- AES_FLAGS_CIPHER_MSK
- AES_FLAGS_CTR
- AES_FLAGS_DUMP_REG
- AES_FLAGS_ECB
- AES_FLAGS_ENCRYPT
- AES_FLAGS_GCM
- AES_FLAGS_GTAGEN
- AES_FLAGS_HIDDENKEY
- AES_FLAGS_MODE_MASK
- AES_FLAGS_OFB
- AES_FLAGS_OPMODE_MASK
- AES_FLAGS_OWN_SHA
- AES_FLAGS_PERSISTENT
- AES_FLAGS_XTS
- AES_GCM
- AES_GCMHR
- AES_GCM_CMD0
- AES_GCM_CMD1
- AES_GCM_CMD2
- AES_GCM_CMD3
- AES_GCM_CMD4
- AES_GCM_CMD5
- AES_GCM_CMD6
- AES_GCM_H
- AES_GHASHR
- AES_GMAC_H
- AES_HW_VERSION
- AES_IDATAR
- AES_IDR
- AES_IER
- AES_IMR
- AES_INTRA_PENDING
- AES_INTRB_PENDING
- AES_INTR_MASK
- AES_INTR_PENDING
- AES_INTR_REG
- AES_INT_DATARDY
- AES_INT_TAGRDY
- AES_INT_URAD
- AES_ISR
- AES_ISR_URAT_IDR_WR_PROC
- AES_ISR_URAT_MASK
- AES_ISR_URAT_MR_WR_PROC
- AES_ISR_URAT_MR_WR_SUBK
- AES_ISR_URAT_ODR_RD_PROC
- AES_ISR_URAT_ODR_RD_SUBK
- AES_ISR_URAT_WOR_RD
- AES_IV
- AES_IVR
- AES_IV_SIZE
- AES_KEXPAND0
- AES_KEXPAND1
- AES_KEXPAND2
- AES_KEYLENGTH_128BIT
- AES_KEYLENGTH_192BIT
- AES_KEYLENGTH_256BIT
- AES_KEYSIZE_128
- AES_KEYSIZE_192
- AES_KEYSIZE_256
- AES_KEYWR
- AES_KEY_BASE_B
- AES_KEY_IN_BASE
- AES_KEY_LEN
- AES_LENA_REG
- AES_MAC_END
- AES_MAX_CT_SIZE
- AES_MAX_KEYLENGTH
- AES_MAX_KEYLENGTH_U32
- AES_MAX_KEY_SIZE
- AES_MAX_STATE_BUF_SIZE
- AES_MIN_KEY_SIZE
- AES_MODE_CBC
- AES_MODE_CCM
- AES_MODE_ECB
- AES_MODE_NONE
- AES_MR
- AES_MR_CFBS_128b
- AES_MR_CFBS_16b
- AES_MR_CFBS_32b
- AES_MR_CFBS_64b
- AES_MR_CFBS_8b
- AES_MR_CFBS_MASK
- AES_MR_CKEY_MASK
- AES_MR_CKEY_OFFSET
- AES_MR_CMTYP_MASK
- AES_MR_CMTYP_OFFSET
- AES_MR_CYPHER_DEC
- AES_MR_CYPHER_ENC
- AES_MR_DUALBUFF
- AES_MR_GTAGEN
- AES_MR_KEYSIZE_128
- AES_MR_KEYSIZE_192
- AES_MR_KEYSIZE_256
- AES_MR_KEYSIZE_MASK
- AES_MR_LOD
- AES_MR_OPMOD_CBC
- AES_MR_OPMOD_CFB
- AES_MR_OPMOD_CTR
- AES_MR_OPMOD_ECB
- AES_MR_OPMOD_GCM
- AES_MR_OPMOD_MASK
- AES_MR_OPMOD_OFB
- AES_MR_OPMOD_XTS
- AES_MR_PROCDLY_MASK
- AES_MR_PROCDLY_OFFSET
- AES_MR_SMOD_AUTO
- AES_MR_SMOD_IDATAR0
- AES_MR_SMOD_MANUAL
- AES_MR_SMOD_MASK
- AES_ODATAR
- AES_OP_TIMEOUT
- AES_PORTA_CONTROL_REG_BASE
- AES_PORTB_CONTROL_REG_BASE
- AES_PRIV_SIZE
- AES_QUEUE_SIZE
- AES_RANDOM_DATA_BASE
- AES_REG_AUTOIDLE
- AES_REG_A_LEN
- AES_REG_CTRL
- AES_REG_CTRL_CBC
- AES_REG_CTRL_CONTEXT_READY
- AES_REG_CTRL_CTR
- AES_REG_CTRL_CTR_WIDTH_128
- AES_REG_CTRL_CTR_WIDTH_32
- AES_REG_CTRL_CTR_WIDTH_64
- AES_REG_CTRL_CTR_WIDTH_96
- AES_REG_CTRL_CTR_WIDTH_MASK
- AES_REG_CTRL_DIRECTION
- AES_REG_CTRL_GCM
- AES_REG_CTRL_INPUT_READY
- AES_REG_CTRL_KEY_SIZE
- AES_REG_CTRL_MASK
- AES_REG_CTRL_OUTPUT_READY
- AES_REG_C_LEN_0
- AES_REG_C_LEN_1
- AES_REG_DATA_N
- AES_REG_IRQ_DATA_IN
- AES_REG_IRQ_DATA_OUT
- AES_REG_IRQ_ENABLE
- AES_REG_IRQ_STATUS
- AES_REG_IV
- AES_REG_KEY
- AES_REG_LENGTH_N
- AES_REG_MASK
- AES_REG_MASK_DMA_IN_EN
- AES_REG_MASK_DMA_OUT_EN
- AES_REG_MASK_SIDLE
- AES_REG_MASK_SOFTRESET
- AES_REG_MASK_START
- AES_REG_REV
- AES_REG_TAG_N
- AES_ROUND
- AES_SAMPLE_WIDTH
- AES_SK
- AES_SOURCEA_REG
- AES_SW_DEC_CNT_INC
- AES_SW_ENC_CNT_INC
- AES_TAGR
- AES_TFM_128BITS
- AES_TFM_192BITS
- AES_TFM_256BITS
- AES_TFM_3IV
- AES_TFM_BASIC_IN
- AES_TFM_BASIC_OUT
- AES_TFM_CBC
- AES_TFM_CFB128
- AES_TFM_CTR_INIT
- AES_TFM_CTR_LOAD
- AES_TFM_ECB
- AES_TFM_ENC_HASH
- AES_TFM_FULL_IV
- AES_TFM_GCM_IN
- AES_TFM_GCM_OUT
- AES_TFM_GHASH
- AES_TFM_GHASH_DIGEST
- AES_TFM_IV_CTR_MODE
- AES_TFM_OFB
- AES_TFM_SIZE
- AES_TO_AES
- AES_TO_PCM
- AES_TWR
- AES_WRITEIV0_REG
- AES_WRITEKEY0_REG
- AES_XTS
- AES_and_HASH
- AES_to_AES_to_HASH
- AES_to_AES_to_HASH_and_DOUT
- AES_to_HASH
- AES_to_HASH_and_AES
- AES_to_HASH_and_DOUT
- AETH_ACK
- AETH_ACK_UNLIMITED
- AETH_MSN_MASK
- AETH_NAK
- AETH_NAK_INVALID_REQ
- AETH_NAK_INV_RD_REQ
- AETH_NAK_PSN_SEQ_ERROR
- AETH_NAK_REM_ACC_ERR
- AETH_NAK_REM_OP_ERR
- AETH_PRN
- AETH_RNR_NAK
- AETH_RSVD
- AETH_SYN_MASK
- AETH_TYPE_MASK
- AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0
- AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0
- AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1
- AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
- AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
- AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_SPIO5
- AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
- AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT
- AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
- AEU_INVERT_REG_SPECIAL_CNIG_0
- AEU_INVERT_REG_SPECIAL_CNIG_1
- AEU_INVERT_REG_SPECIAL_CNIG_2
- AEU_INVERT_REG_SPECIAL_CNIG_3
- AEU_INVERT_REG_SPECIAL_MAX
- AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
- AEW
- AEWB_PACKET_SIZE
- AEWB_SATURATION_LIMIT
- AEWINBLK_CHNG
- AEWINSTART_CHNG
- AEWSUBWIN_CHNG
- AEWWIN1_CHNG
- AE_ABORT_METHOD
- AE_ACCESS
- AE_ACQUIRE_DEADLOCK
- AE_ALREADY_ACQUIRED
- AE_ALREADY_EXISTS
- AE_AML_ALIGNMENT
- AE_AML_BAD_NAME
- AE_AML_BAD_OPCODE
- AE_AML_BAD_RESOURCE_LENGTH
- AE_AML_BAD_RESOURCE_VALUE
- AE_AML_BUFFER_LENGTH
- AE_AML_BUFFER_LIMIT
- AE_AML_CIRCULAR_REFERENCE
- AE_AML_DIVIDE_BY_ZERO
- AE_AML_ILLEGAL_ADDRESS
- AE_AML_INTERNAL
- AE_AML_INVALID_INDEX
- AE_AML_INVALID_RESOURCE_TYPE
- AE_AML_INVALID_SPACE_ID
- AE_AML_LOOP_TIMEOUT
- AE_AML_METHOD_LIMIT
- AE_AML_MUTEX_NOT_ACQUIRED
- AE_AML_MUTEX_ORDER
- AE_AML_NAME_NOT_FOUND
- AE_AML_NOT_OWNER
- AE_AML_NO_OPERAND
- AE_AML_NO_RESOURCE_END_TAG
- AE_AML_NO_RETURN_VALUE
- AE_AML_NO_WHILE
- AE_AML_NUMERIC_OVERFLOW
- AE_AML_OPERAND_TYPE
- AE_AML_OPERAND_VALUE
- AE_AML_PACKAGE_LIMIT
- AE_AML_PROTOCOL
- AE_AML_REGION_LIMIT
- AE_AML_REGISTER_LIMIT
- AE_AML_STRING_LIMIT
- AE_AML_TARGET_TYPE
- AE_AML_UNINITIALIZED_ARG
- AE_AML_UNINITIALIZED_ELEMENT
- AE_AML_UNINITIALIZED_LOCAL
- AE_AML_UNINITIALIZED_NODE
- AE_BAD_ADDRESS
- AE_BAD_CHARACTER
- AE_BAD_CHECKSUM
- AE_BAD_DATA
- AE_BAD_DECIMAL_CONSTANT
- AE_BAD_HEADER
- AE_BAD_HEX_CONSTANT
- AE_BAD_OCTAL_CONSTANT
- AE_BAD_PARAMETER
- AE_BAD_PATHNAME
- AE_BAD_SIGNATURE
- AE_BAD_VALUE
- AE_BUFFER_OVERFLOW
- AE_CODE_ACPI_TABLES
- AE_CODE_AML
- AE_CODE_AML_MAX
- AE_CODE_CONTROL
- AE_CODE_CTRL_MAX
- AE_CODE_ENVIRONMENTAL
- AE_CODE_ENV_MAX
- AE_CODE_MASK
- AE_CODE_MAX
- AE_CODE_PGM_MAX
- AE_CODE_PROGRAMMER
- AE_CODE_TBL_MAX
- AE_CONTROL_SPEED
- AE_CORES_PER_CLUSTER
- AE_CORE_REQ
- AE_CSR
- AE_CSR_ADDR
- AE_CTL10_REG
- AE_CTL1_REG
- AE_CTL2_REG
- AE_CTL9_REG
- AE_CTL_REG
- AE_CTRL_BREAK
- AE_CTRL_CONTINUE
- AE_CTRL_DEPTH
- AE_CTRL_END
- AE_CTRL_FALSE
- AE_CTRL_PARSE_CONTINUE
- AE_CTRL_PARSE_PENDING
- AE_CTRL_PENDING
- AE_CTRL_RETURN_VALUE
- AE_CTRL_TERMINATE
- AE_CTRL_TRANSFER
- AE_CTRL_TRUE
- AE_DECIMAL_OVERFLOW
- AE_END_OF_TABLE
- AE_ERROR
- AE_EV_PRESET_CAPTURE
- AE_EV_PRESET_MONITOR
- AE_F
- AE_FINE_CTL_REG
- AE_FRM_CTL_REG
- AE_FW
- AE_F_SET
- AE_HEX_OVERFLOW
- AE_INDEX
- AE_INFO
- AE_INVALID_TABLE_LENGTH
- AE_IO_ERROR
- AE_ISO
- AE_IS_VER1
- AE_LIMIT
- AE_LOCK
- AE_MAN_GAIN_CAP
- AE_MAN_GAIN_MON
- AE_MAX_CORES
- AE_MAX_GAIN_MON
- AE_MISC_CONTROL
- AE_MISSING_ARGUMENTS
- AE_MODE
- AE_NAME_PORT_ID_IDX
- AE_NAME_SIZE
- AE_NOT_ACQUIRED
- AE_NOT_CONFIGURED
- AE_NOT_EXIST
- AE_NOT_FOUND
- AE_NOT_IMPLEMENTED
- AE_NO_ACPI_TABLES
- AE_NO_GLOBAL_LOCK
- AE_NO_HANDLER
- AE_NO_HARDWARE_RESPONSE
- AE_NO_MEMORY
- AE_NO_NAMESPACE
- AE_NULL_ENTRY
- AE_NULL_OBJECT
- AE_NUMERIC_OVERFLOW
- AE_OCTAL_OVERFLOW
- AE_OK
- AE_OWNER_ID_LIMIT
- AE_RELEASE_DEADLOCK
- AE_SAME_HANDLER
- AE_STACK_OVERFLOW
- AE_STACK_UNDERFLOW
- AE_SUPPORT
- AE_TIME
- AE_TYPE
- AE_TYPES
- AE_VERSION_1
- AE_VERSION_2
- AE_WGT_REG
- AE_XFER
- AE_XFER_ADDR
- AE_YLVL_REG
- AE_YTH_REG
- AF
- AF0
- AF1
- AF10
- AF11
- AF12
- AF13
- AF14
- AF15
- AF1_in
- AF1_out
- AF2
- AF24
- AF25
- AF2_COREDUMP_AVAIL
- AF2_COREDUMP_SAVED
- AF2_DEV_CNT_OK
- AF2_DEV_SCAN
- AF2_INIT_DONE
- AF2_INT_PENDING
- AF2_IRQ_CLAIMED
- AF2_MSI_ENABLED
- AF2_SERIAL_FLASH
- AF2_THUNDERBOLT
- AF2_THUNDERLINK
- AF2_TIMER_TICK
- AF2_VDA_POWER_DOWN
- AF2_in
- AF2_out
- AF3
- AF4
- AF5
- AF6
- AF7
- AF8
- AF9
- AF9005_CMD_AUTOINC
- AF9005_CMD_BURST
- AF9005_CMD_OFDM_REG
- AF9005_CMD_READ
- AF9005_CMD_TUNER
- AF9005_CMD_WRITE
- AF9005_OFDM_REG
- AF9005_REGISTER_RW
- AF9005_REGISTER_RW_ACK
- AF9005_TUNER_REG
- AF9013_FIRMWARE
- AF9013_GPIO_EN
- AF9013_GPIO_HI
- AF9013_GPIO_I
- AF9013_GPIO_LO
- AF9013_GPIO_O
- AF9013_GPIO_ON
- AF9013_GPIO_TUNER_OFF
- AF9013_GPIO_TUNER_ON
- AF9013_H
- AF9013_PRIV_H
- AF9013_TS_MODE_PARALLEL
- AF9013_TS_MODE_SERIAL
- AF9013_TS_MODE_USB
- AF9013_TUNER_ENV77H11D5
- AF9013_TUNER_MC44S803
- AF9013_TUNER_MT2060
- AF9013_TUNER_MT2060_2
- AF9013_TUNER_MXL5003D
- AF9013_TUNER_MXL5005D
- AF9013_TUNER_MXL5005R
- AF9013_TUNER_MXL5007T
- AF9013_TUNER_QT1010
- AF9013_TUNER_QT1010A
- AF9013_TUNER_TDA18218
- AF9013_TUNER_TDA18271
- AF9013_TUNER_UNKNOWN
- AF9015_EEPROM_DEMOD2_I2C
- AF9015_EEPROM_IF1H
- AF9015_EEPROM_IF1L
- AF9015_EEPROM_IF2H
- AF9015_EEPROM_IF2L
- AF9015_EEPROM_IR_MODE
- AF9015_EEPROM_IR_REMOTE_TYPE
- AF9015_EEPROM_MT2060_IF1H
- AF9015_EEPROM_MT2060_IF1L
- AF9015_EEPROM_MT2060_IF2H
- AF9015_EEPROM_MT2060_IF2L
- AF9015_EEPROM_OFFSET
- AF9015_EEPROM_SAW_BW1
- AF9015_EEPROM_SAW_BW2
- AF9015_EEPROM_SIZE
- AF9015_EEPROM_SPEC_INV1
- AF9015_EEPROM_SPEC_INV2
- AF9015_EEPROM_TS_MODE
- AF9015_EEPROM_TUNER_ID1
- AF9015_EEPROM_TUNER_ID2
- AF9015_EEPROM_XTAL_TYPE1
- AF9015_EEPROM_XTAL_TYPE2
- AF9015_FIRMWARE
- AF9015_H
- AF9015_I2C_DEMOD
- AF9015_I2C_EEPROM
- AF9015_IR_MODE_DISABLED
- AF9015_IR_MODE_HID
- AF9015_IR_MODE_POLLING
- AF9015_IR_MODE_RC6
- AF9015_IR_MODE_RLC
- AF9015_REMOTE_AVERMEDIA_KS
- AF9015_REMOTE_A_LINK_DTU_M
- AF9015_REMOTE_DIGITTRADE_DVB_T
- AF9015_REMOTE_MSI_DIGIVOX_MINI_II_V3
- AF9015_REMOTE_MYGICTV_U718
- AF9015_REMOTE_NONE
- AF9015_USB_TIMEOUT
- AF9033_ADC_MULTIPLIER_1X
- AF9033_ADC_MULTIPLIER_2X
- AF9033_H
- AF9033_PRIV_H
- AF9033_TS_MODE_PARALLEL
- AF9033_TS_MODE_SERIAL
- AF9033_TS_MODE_USB
- AF9033_TUNER_FC0011
- AF9033_TUNER_FC0012
- AF9033_TUNER_FC2580
- AF9033_TUNER_IT9135_38
- AF9033_TUNER_IT9135_51
- AF9033_TUNER_IT9135_52
- AF9033_TUNER_IT9135_60
- AF9033_TUNER_IT9135_61
- AF9033_TUNER_IT9135_62
- AF9033_TUNER_MXL5007T
- AF9033_TUNER_TDA18218
- AF9033_TUNER_TUA9001
- AF9035_FIRMWARE_AF9035
- AF9035_FIRMWARE_IT9135_V1
- AF9035_FIRMWARE_IT9135_V2
- AF9035_FIRMWARE_IT9303
- AF9035_H
- AF9035_I2C_CLIENT_MAX
- AF9035_IS_I2C_XFER_READ
- AF9035_IS_I2C_XFER_WRITE
- AF9035_IS_I2C_XFER_WRITE_READ
- AFAB_AXI_S0_FCLK
- AFAB_AXI_S1_FCLK
- AFAB_AXI_S2_FCLK
- AFAB_AXI_S3_FCLK
- AFAB_AXI_S4_FCLK
- AFAB_CLK_SRC
- AFAB_CORE_CLK
- AFAB_CORE_RESET
- AFAB_EBI1_CH0_A_CLK
- AFAB_EBI1_CH0_RESET
- AFAB_EBI1_CH1_A_CLK
- AFAB_EBI1_CH1_RESET
- AFAB_EBI1_S_RESET
- AFAB_SFAB_M0_A_CLK
- AFAB_SFAB_M0_RESET
- AFAB_SFAB_M1_A_CLK
- AFAB_SFAB_M1_RESET
- AFAB_SMPSS_M0_RESET
- AFAB_SMPSS_M1_RESET
- AFAB_SMPSS_S_RESET
- AFATECH_AF9005
- AFBC
- AFBC_16x16
- AFBC_32x8
- AFBC_BODY_START_ALIGNMENT
- AFBC_CBR
- AFBC_ENABLE
- AFBC_FORMAT_MOD_BCH
- AFBC_FORMAT_MOD_BLOCK_SIZE_16x16
- AFBC_FORMAT_MOD_BLOCK_SIZE_32x8
- AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4
- AFBC_FORMAT_MOD_BLOCK_SIZE_64x4
- AFBC_FORMAT_MOD_BLOCK_SIZE_MASK
- AFBC_FORMAT_MOD_CBR
- AFBC_FORMAT_MOD_DB
- AFBC_FORMAT_MOD_SC
- AFBC_FORMAT_MOD_SPARSE
- AFBC_FORMAT_MOD_SPLIT
- AFBC_FORMAT_MOD_TILED
- AFBC_FORMAT_MOD_YTR
- AFBC_HEADER_SIZE
- AFBC_MOD_VALID_BITS
- AFBC_SC
- AFBC_SIZE_16X16
- AFBC_SIZE_MASK
- AFBC_SPARSE
- AFBC_SPLIT
- AFBC_SUPERBLK_ALIGNMENT
- AFBC_SUPERBLK_PIXELS
- AFBC_TH_BODY_START_ALIGNMENT
- AFBC_TH_LAYOUT_ALIGNMENT
- AFBC_TILED
- AFBC_YTR
- AFBC_YUV_422_FORMAT_ID
- AFB_TH
- AFB_TH_SC_YTR
- AFB_TH_SC_YTR_BS
- AFCEXEN_set
- AFCOEF_OFFSET
- AFCR
- AFC_CFG
- AFC_CFG_AFC_HI_
- AFC_CFG_AFC_LO_
- AFC_CFG_BACK_DUR_
- AFC_CFG_DEFAULT
- AFC_CFG_FCADD_
- AFC_CFG_FCANY_
- AFC_CFG_FCBRD_
- AFC_CFG_FCMULT_
- AFC_CFG_FC_ADD_
- AFC_CFG_FC_ANY_
- AFC_CFG_FC_BRD_
- AFC_CFG_FC_MULT_
- AFC_CFG_HI_
- AFC_CFG_LO_
- AFC_SEAR_TH
- AFE
- AFE4403_DRIVER_NAME
- AFE4403_TIAGAIN
- AFE4403_TIA_AMB_GAIN
- AFE4403_TIMING_PAIRS
- AFE4404_AVG_LED1_ALED1VAL
- AFE4404_AVG_LED2_ALED2VAL
- AFE4404_CLKDIV_PRF
- AFE4404_DEC
- AFE4404_DRIVER_NAME
- AFE4404_LED3LEDENDC
- AFE4404_LED3LEDSTC
- AFE4404_OFFDAC
- AFE4404_PROG_TG_ENDC
- AFE4404_PROG_TG_STC
- AFE4404_TIA_GAIN
- AFE4404_TIA_GAIN_SEP
- AFE4404_TIMING_PAIRS
- AFE440X_ADCRSTENDCT0
- AFE440X_ADCRSTENDCT1
- AFE440X_ADCRSTENDCT2
- AFE440X_ADCRSTENDCT3
- AFE440X_ADCRSTSTCT0
- AFE440X_ADCRSTSTCT1
- AFE440X_ADCRSTSTCT2
- AFE440X_ADCRSTSTCT3
- AFE440X_ALARM
- AFE440X_ALED1CONVEND
- AFE440X_ALED1CONVST
- AFE440X_ALED1ENDC
- AFE440X_ALED1STC
- AFE440X_ALED1VAL
- AFE440X_ALED2CONVEND
- AFE440X_ALED2CONVST
- AFE440X_ALED2ENDC
- AFE440X_ALED2STC
- AFE440X_ALED2VAL
- AFE440X_ATTR
- AFE440X_CONTROL0
- AFE440X_CONTROL0_READ
- AFE440X_CONTROL0_REG_READ
- AFE440X_CONTROL0_SW_RESET
- AFE440X_CONTROL0_TM_COUNT_RST
- AFE440X_CONTROL0_WRITE
- AFE440X_CONTROL1
- AFE440X_CONTROL1_TIMEREN
- AFE440X_CONTROL2
- AFE440X_CONTROL2_DYNAMIC1
- AFE440X_CONTROL2_DYNAMIC2
- AFE440X_CONTROL2_DYNAMIC3
- AFE440X_CONTROL2_DYNAMIC4
- AFE440X_CONTROL2_OSC_ENABLE
- AFE440X_CONTROL2_PDN_AFE
- AFE440X_CONTROL2_PDN_RX
- AFE440X_CONTROL3
- AFE440X_CONTROL3_CLKDIV
- AFE440X_CURRENT_CHAN
- AFE440X_INTENSITY_CHAN
- AFE440X_LED1CONVEND
- AFE440X_LED1CONVST
- AFE440X_LED1ENDC
- AFE440X_LED1LEDENDC
- AFE440X_LED1LEDSTC
- AFE440X_LED1STC
- AFE440X_LED1VAL
- AFE440X_LED1_ALED1VAL
- AFE440X_LED2CONVEND
- AFE440X_LED2CONVST
- AFE440X_LED2ENDC
- AFE440X_LED2LEDENDC
- AFE440X_LED2LEDSTC
- AFE440X_LED2STC
- AFE440X_LED2VAL
- AFE440X_LED2_ALED2VAL
- AFE440X_LEDCNTRL
- AFE440X_PDNCYCLEENDC
- AFE440X_PDNCYCLESTC
- AFE440X_PRPCOUNT
- AFE440X_TABLE_ATTR
- AFE440X_TIAGAIN_ENSEPGAIN
- AFEIF
- AFEX_LIST_TABLE_SIZE
- AFEX_UPDATE
- AFE_22M_ON_MASK
- AFE_22M_ON_MASK_SFT
- AFE_22M_ON_SFT
- AFE_24M_ON_MASK
- AFE_24M_ON_MASK_SFT
- AFE_24M_ON_SFT
- AFE_AB_CTRL
- AFE_AB_DIAG_CTRL
- AFE_ADD6A_UL_SRC_MON0
- AFE_ADD6_UL_SRC_CON1
- AFE_ADDA2_TOP_CON0
- AFE_ADDA6_CKDIV_RST_MASK
- AFE_ADDA6_CKDIV_RST_MASK_SFT
- AFE_ADDA6_CKDIV_RST_SFT
- AFE_ADDA6_FIFO_AUTO_RST_MASK
- AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT
- AFE_ADDA6_FIFO_AUTO_RST_SFT
- AFE_ADDA6_IIR_COEF_02_01
- AFE_ADDA6_IIR_COEF_04_03
- AFE_ADDA6_IIR_COEF_06_05
- AFE_ADDA6_IIR_COEF_08_07
- AFE_ADDA6_IIR_COEF_10_09
- AFE_ADDA6_SRC_DEBUG
- AFE_ADDA6_SRC_DEBUG_MON0
- AFE_ADDA6_TOP_CON0
- AFE_ADDA6_ULCF_CFG_02_01
- AFE_ADDA6_ULCF_CFG_04_03
- AFE_ADDA6_ULCF_CFG_06_05
- AFE_ADDA6_ULCF_CFG_08_07
- AFE_ADDA6_ULCF_CFG_10_09
- AFE_ADDA6_ULCF_CFG_12_11
- AFE_ADDA6_ULCF_CFG_14_13
- AFE_ADDA6_ULCF_CFG_16_15
- AFE_ADDA6_ULCF_CFG_18_17
- AFE_ADDA6_ULCF_CFG_20_19
- AFE_ADDA6_ULCF_CFG_22_21
- AFE_ADDA6_ULCF_CFG_24_23
- AFE_ADDA6_ULCF_CFG_26_25
- AFE_ADDA6_ULCF_CFG_28_27
- AFE_ADDA6_ULCF_CFG_30_29
- AFE_ADDA6_UL_LR_SWAP_MASK
- AFE_ADDA6_UL_LR_SWAP_MASK_SFT
- AFE_ADDA6_UL_LR_SWAP_SFT
- AFE_ADDA6_UL_SRC_CON0
- AFE_ADDA6_UL_SRC_MON1
- AFE_ADDA_DL_DC_COMP_CFG0
- AFE_ADDA_DL_DC_COMP_CFG1
- AFE_ADDA_DL_SDM_DCCOMP_CON
- AFE_ADDA_DL_SDM_FIFO_MON
- AFE_ADDA_DL_SDM_OUT_MON
- AFE_ADDA_DL_SDM_TEST
- AFE_ADDA_DL_SRC2_CON0
- AFE_ADDA_DL_SRC2_CON1
- AFE_ADDA_DL_SRC_LCH_MON
- AFE_ADDA_DL_SRC_RCH_MON
- AFE_ADDA_IIR_COEF_02_01
- AFE_ADDA_IIR_COEF_04_03
- AFE_ADDA_IIR_COEF_06_05
- AFE_ADDA_IIR_COEF_08_07
- AFE_ADDA_IIR_COEF_10_09
- AFE_ADDA_MTKAIF_CFG0
- AFE_ADDA_MTKAIF_MON0
- AFE_ADDA_MTKAIF_MON1
- AFE_ADDA_MTKAIF_RX_CFG0
- AFE_ADDA_MTKAIF_RX_CFG1
- AFE_ADDA_MTKAIF_RX_CFG2
- AFE_ADDA_MTKAIF_TX_CFG1
- AFE_ADDA_NEWIF_CFG0
- AFE_ADDA_NEWIF_CFG1
- AFE_ADDA_NEWIF_CFG2
- AFE_ADDA_PREDIS_CON0
- AFE_ADDA_PREDIS_CON1
- AFE_ADDA_PREDIS_CON2
- AFE_ADDA_PREDIS_CON3
- AFE_ADDA_SRC_DEBUG
- AFE_ADDA_SRC_DEBUG_MON0
- AFE_ADDA_SRC_DEBUG_MON1
- AFE_ADDA_TOP_CON0
- AFE_ADDA_UL_DL_CON0
- AFE_ADDA_UL_SRC_CON0
- AFE_ADDA_UL_SRC_CON1
- AFE_ADDA_UL_SRC_MON0
- AFE_ADDA_UL_SRC_MON1
- AFE_API_VERSION_CLOCK_SET
- AFE_API_VERSION_HDMI_CONFIG
- AFE_API_VERSION_I2S_CONFIG
- AFE_API_VERSION_SLIMBUS_CONFIG
- AFE_API_VERSION_SLOT_MAPPING_CONFIG
- AFE_API_VERSION_TDM_CONFIG
- AFE_APLL1_TUNER_CFG
- AFE_APLL2_TUNER_CFG
- AFE_ARB1_BASE
- AFE_ARB1_CUR
- AFE_ASRC2_CON0
- AFE_ASRC2_CON1
- AFE_ASRC2_CON10
- AFE_ASRC2_CON11
- AFE_ASRC2_CON12
- AFE_ASRC2_CON13
- AFE_ASRC2_CON14
- AFE_ASRC2_CON2
- AFE_ASRC2_CON3
- AFE_ASRC2_CON4
- AFE_ASRC2_CON5
- AFE_ASRC2_CON6
- AFE_ASRC2_CON7
- AFE_ASRC2_CON8
- AFE_ASRC2_CON9
- AFE_ASRC3_CON0
- AFE_ASRC3_CON1
- AFE_ASRC3_CON10
- AFE_ASRC3_CON11
- AFE_ASRC3_CON12
- AFE_ASRC3_CON13
- AFE_ASRC3_CON14
- AFE_ASRC3_CON2
- AFE_ASRC3_CON3
- AFE_ASRC3_CON4
- AFE_ASRC3_CON5
- AFE_ASRC3_CON6
- AFE_ASRC3_CON7
- AFE_ASRC3_CON8
- AFE_ASRC3_CON9
- AFE_ASRC4_CON0
- AFE_ASRC4_CON1
- AFE_ASRC4_CON10
- AFE_ASRC4_CON11
- AFE_ASRC4_CON12
- AFE_ASRC4_CON13
- AFE_ASRC4_CON14
- AFE_ASRC4_CON2
- AFE_ASRC4_CON3
- AFE_ASRC4_CON4
- AFE_ASRC4_CON5
- AFE_ASRC4_CON6
- AFE_ASRC4_CON7
- AFE_ASRC4_CON8
- AFE_ASRC4_CON9
- AFE_ASRC_2CH_CON0
- AFE_ASRC_2CH_CON1
- AFE_ASRC_2CH_CON10
- AFE_ASRC_2CH_CON12
- AFE_ASRC_2CH_CON13
- AFE_ASRC_2CH_CON2
- AFE_ASRC_2CH_CON3
- AFE_ASRC_2CH_CON4
- AFE_ASRC_2CH_CON5
- AFE_ASRC_2CH_CON6
- AFE_ASRC_2CH_CON7
- AFE_ASRC_2CH_CON8
- AFE_ASRC_2CH_CON9
- AFE_ASRC_CON0
- AFE_ASRC_CON1
- AFE_ASRC_CON10
- AFE_ASRC_CON11
- AFE_ASRC_CON13
- AFE_ASRC_CON14
- AFE_ASRC_CON15
- AFE_ASRC_CON16
- AFE_ASRC_CON17
- AFE_ASRC_CON18
- AFE_ASRC_CON19
- AFE_ASRC_CON2
- AFE_ASRC_CON20
- AFE_ASRC_CON21
- AFE_ASRC_CON3
- AFE_ASRC_CON4
- AFE_ASRC_CON5
- AFE_ASRC_CON6
- AFE_ASRC_CON7
- AFE_ASRC_CON8
- AFE_ASRC_CON9
- AFE_AUD_PAD_TOP
- AFE_AWB2_BASE
- AFE_AWB2_BASE_MSB
- AFE_AWB2_CUR
- AFE_AWB2_CUR_MSB
- AFE_AWB2_END
- AFE_AWB2_END_MSB
- AFE_AWB_BASE
- AFE_AWB_BASE_MSB
- AFE_AWB_CUR
- AFE_AWB_CUR_MSB
- AFE_AWB_END
- AFE_AWB_END_MSB
- AFE_AWB_RETM_MASK
- AFE_AWB_RETM_MASK_SFT
- AFE_AWB_RETM_SFT
- AFE_BASE_END_OFFSET
- AFE_BGEN
- AFE_BG_PWRDWNB
- AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY
- AFE_BUS_CFG
- AFE_BUS_MON0
- AFE_CBIP_CFG0
- AFE_CBIP_MON0
- AFE_CBIP_SLV_DECODER_MON0
- AFE_CBIP_SLV_MUX_MON0
- AFE_CD_CTRL
- AFE_CD_DIAG_CTRL
- AFE_CLK_INIT_MODE_PAPD
- AFE_CLK_INIT_MODE_TXRX2X
- AFE_CLK_OUT_CTRL
- AFE_CMD_RESP_AVAIL
- AFE_CMD_RESP_NONE
- AFE_CONF_ADDR
- AFE_CONN0
- AFE_CONN0_1
- AFE_CONN1
- AFE_CONN10
- AFE_CONN10_1
- AFE_CONN11
- AFE_CONN11_1
- AFE_CONN12
- AFE_CONN12_1
- AFE_CONN13
- AFE_CONN13_1
- AFE_CONN14
- AFE_CONN14_1
- AFE_CONN15
- AFE_CONN15_1
- AFE_CONN16
- AFE_CONN16_1
- AFE_CONN17
- AFE_CONN17_1
- AFE_CONN18
- AFE_CONN18_1
- AFE_CONN19
- AFE_CONN19_1
- AFE_CONN1_1
- AFE_CONN2
- AFE_CONN20
- AFE_CONN20_1
- AFE_CONN21
- AFE_CONN21_1
- AFE_CONN22
- AFE_CONN22_1
- AFE_CONN23
- AFE_CONN23_1
- AFE_CONN24
- AFE_CONN24_1
- AFE_CONN25
- AFE_CONN25_1
- AFE_CONN26
- AFE_CONN26_1
- AFE_CONN27
- AFE_CONN27_1
- AFE_CONN28
- AFE_CONN28_1
- AFE_CONN29
- AFE_CONN29_1
- AFE_CONN2_1
- AFE_CONN3
- AFE_CONN30
- AFE_CONN30_1
- AFE_CONN31
- AFE_CONN31_1
- AFE_CONN32
- AFE_CONN32_1
- AFE_CONN33
- AFE_CONN33_1
- AFE_CONN34
- AFE_CONN34_1
- AFE_CONN35
- AFE_CONN35_1
- AFE_CONN36
- AFE_CONN36_1
- AFE_CONN37
- AFE_CONN37_1
- AFE_CONN38
- AFE_CONN38_1
- AFE_CONN39
- AFE_CONN39_1
- AFE_CONN3_1
- AFE_CONN4
- AFE_CONN40
- AFE_CONN40_1
- AFE_CONN41
- AFE_CONN41_1
- AFE_CONN42
- AFE_CONN42_1
- AFE_CONN43
- AFE_CONN43_1
- AFE_CONN4_1
- AFE_CONN5
- AFE_CONN5_1
- AFE_CONN6
- AFE_CONN6_1
- AFE_CONN7
- AFE_CONN7_1
- AFE_CONN8
- AFE_CONN8_1
- AFE_CONN9
- AFE_CONN9_1
- AFE_CONNSYS_I2S_CON
- AFE_CONNSYS_I2S_MON
- AFE_CONN_24BIT
- AFE_CONN_24BIT_1
- AFE_CONN_24BIT_O03
- AFE_CONN_24BIT_O04
- AFE_CONN_DI
- AFE_CONN_DI_1
- AFE_CONN_REG
- AFE_CONN_RS
- AFE_CONN_RS_1
- AFE_CORERDY_VDDC
- AFE_CTRL
- AFE_CTRL_C2HH_SRC_CTRL
- AFE_DAC_CON0
- AFE_DAC_CON0_AFE_ON
- AFE_DAC_CON1
- AFE_DAC_CON2
- AFE_DAC_CON3
- AFE_DAC_CON4
- AFE_DAC_MON
- AFE_DAIBT_CON0
- AFE_DAIBT_CON0_BT_FUNC_EN
- AFE_DAIBT_CON0_BT_FUNC_RDY
- AFE_DAIBT_CON0_BT_WIDE_MODE_EN
- AFE_DAIBT_CON0_DAIBT_EN
- AFE_DAIBT_CON0_MRG_USE
- AFE_DAI_BASE
- AFE_DAI_CUR
- AFE_DAI_END
- AFE_DEVICE_ADDRESS
- AFE_DIAG_CTRL1
- AFE_DIAG_CTRL3
- AFE_DL1_BASE
- AFE_DL1_BASE_MSB
- AFE_DL1_CUR
- AFE_DL1_CUR_MSB
- AFE_DL1_DATA2_RETM_MASK
- AFE_DL1_DATA2_RETM_MASK_SFT
- AFE_DL1_DATA2_RETM_SFT
- AFE_DL1_END
- AFE_DL1_END_MSB
- AFE_DL1_RETM_MASK
- AFE_DL1_RETM_MASK_SFT
- AFE_DL1_RETM_SFT
- AFE_DL2_BASE
- AFE_DL2_BASE_MSB
- AFE_DL2_CUR
- AFE_DL2_CUR_MSB
- AFE_DL2_END
- AFE_DL2_END_MSB
- AFE_DL2_RETM_MASK
- AFE_DL2_RETM_MASK_SFT
- AFE_DL2_RETM_SFT
- AFE_DL3_BASE
- AFE_DL3_BASE_MSB
- AFE_DL3_CUR
- AFE_DL3_CUR_MSB
- AFE_DL3_END
- AFE_DL3_END_MSB
- AFE_DL4_BASE
- AFE_DL4_CUR
- AFE_DL5_BASE
- AFE_DL5_CUR
- AFE_DLMCH_BASE
- AFE_DLMCH_CUR
- AFE_DL_LR_SWAP_MASK
- AFE_DL_LR_SWAP_MASK_SFT
- AFE_DL_LR_SWAP_SFT
- AFE_DMA_CTL
- AFE_DMA_MON0
- AFE_DMA_MON1
- AFE_EF_CTRL
- AFE_EF_DIAG_CTRL
- AFE_FS_MARK
- AFE_GAIN1_CON0
- AFE_GAIN1_CON1
- AFE_GAIN1_CON2
- AFE_GAIN1_CON3
- AFE_GAIN1_CUR
- AFE_GAIN1_CUR_MASK
- AFE_GAIN1_CUR_MASK_SFT
- AFE_GAIN1_CUR_SFT
- AFE_GAIN2_CON0
- AFE_GAIN2_CON1
- AFE_GAIN2_CON2
- AFE_GAIN2_CON3
- AFE_GAIN2_CUR
- AFE_GAIN2_CUR_MASK
- AFE_GAIN2_CUR_MASK_SFT
- AFE_GAIN2_CUR_SFT
- AFE_GENERAL1_ASRC_2CH_CON0
- AFE_GENERAL1_ASRC_2CH_CON1
- AFE_GENERAL1_ASRC_2CH_CON10
- AFE_GENERAL1_ASRC_2CH_CON12
- AFE_GENERAL1_ASRC_2CH_CON13
- AFE_GENERAL1_ASRC_2CH_CON2
- AFE_GENERAL1_ASRC_2CH_CON3
- AFE_GENERAL1_ASRC_2CH_CON4
- AFE_GENERAL1_ASRC_2CH_CON5
- AFE_GENERAL1_ASRC_2CH_CON6
- AFE_GENERAL1_ASRC_2CH_CON7
- AFE_GENERAL1_ASRC_2CH_CON8
- AFE_GENERAL1_ASRC_2CH_CON9
- AFE_GENERAL2_ASRC_2CH_CON0
- AFE_GENERAL2_ASRC_2CH_CON1
- AFE_GENERAL2_ASRC_2CH_CON10
- AFE_GENERAL2_ASRC_2CH_CON12
- AFE_GENERAL2_ASRC_2CH_CON13
- AFE_GENERAL2_ASRC_2CH_CON2
- AFE_GENERAL2_ASRC_2CH_CON3
- AFE_GENERAL2_ASRC_2CH_CON4
- AFE_GENERAL2_ASRC_2CH_CON5
- AFE_GENERAL2_ASRC_2CH_CON6
- AFE_GENERAL2_ASRC_2CH_CON7
- AFE_GENERAL2_ASRC_2CH_CON8
- AFE_GENERAL2_ASRC_2CH_CON9
- AFE_GENERAL_REG0
- AFE_GENERAL_REG1
- AFE_GENERAL_REG10
- AFE_GENERAL_REG11
- AFE_GENERAL_REG12
- AFE_GENERAL_REG13
- AFE_GENERAL_REG14
- AFE_GENERAL_REG15
- AFE_GENERAL_REG2
- AFE_GENERAL_REG3
- AFE_GENERAL_REG4
- AFE_GENERAL_REG5
- AFE_GENERAL_REG6
- AFE_GENERAL_REG7
- AFE_GENERAL_REG8
- AFE_GENERAL_REG9
- AFE_GH_CTRL
- AFE_GH_DIAG_CTRL
- AFE_HC1_MARK
- AFE_HDMI_BASE
- AFE_HDMI_CONN0
- AFE_HDMI_CONN0_O30_I30
- AFE_HDMI_CONN0_O31_I31
- AFE_HDMI_CONN0_O32_I34
- AFE_HDMI_CONN0_O33_I35
- AFE_HDMI_CONN0_O34_I32
- AFE_HDMI_CONN0_O35_I33
- AFE_HDMI_CONN0_O36_I36
- AFE_HDMI_CONN0_O37_I37
- AFE_HDMI_CUR
- AFE_HDMI_END
- AFE_HDMI_OUT_BASE
- AFE_HDMI_OUT_BASE_MSB
- AFE_HDMI_OUT_BIT_WIDTH_MASK
- AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT
- AFE_HDMI_OUT_BIT_WIDTH_SFT
- AFE_HDMI_OUT_CH_NUM_MASK
- AFE_HDMI_OUT_CH_NUM_MASK_SFT
- AFE_HDMI_OUT_CH_NUM_SFT
- AFE_HDMI_OUT_CON0
- AFE_HDMI_OUT_CUR
- AFE_HDMI_OUT_CUR_MSB
- AFE_HDMI_OUT_END
- AFE_HDMI_OUT_END_MSB
- AFE_HDMI_OUT_ON_MASK
- AFE_HDMI_OUT_ON_MASK_SFT
- AFE_HDMI_OUT_ON_RETM_MASK
- AFE_HDMI_OUT_ON_RETM_MASK_SFT
- AFE_HDMI_OUT_ON_RETM_SFT
- AFE_HDMI_OUT_ON_SFT
- AFE_HD_ENGEN_ENABLE
- AFE_HPF_TRIM_OTHERS
- AFE_I2S_CON
- AFE_I2S_CON1
- AFE_I2S_CON1_EN
- AFE_I2S_CON1_FORMAT_I2S
- AFE_I2S_CON1_LOW_JITTER_CLK
- AFE_I2S_CON1_RATE
- AFE_I2S_CON2
- AFE_I2S_CON2_EN
- AFE_I2S_CON2_FORMAT_I2S
- AFE_I2S_CON2_LOW_JITTER_CLK
- AFE_I2S_CON2_RATE
- AFE_I2S_CON3
- AFE_I2S_CON4
- AFE_I2S_MON
- AFE_IRQ0_MCU_CNT_MON
- AFE_IRQ11_MCU_CNT_MON
- AFE_IRQ12_MCU_CNT_MON
- AFE_IRQ1_MCU_CNT_MON
- AFE_IRQ1_MCU_EN_CNT_MON
- AFE_IRQ2_MCU_CNT_MON
- AFE_IRQ3_MCU_CNT_MON
- AFE_IRQ4_MCU_CNT_MON
- AFE_IRQ5_MCU_CNT_MON
- AFE_IRQ6_MCU_CNT_MON
- AFE_IRQ7_MCU_CNT_MON
- AFE_IRQ8_MCU_CNT_MON
- AFE_IRQ_CLR
- AFE_IRQ_CM4_EN_MASK
- AFE_IRQ_CM4_EN_MASK_SFT
- AFE_IRQ_CM4_EN_SFT
- AFE_IRQ_CNT1
- AFE_IRQ_CNT2
- AFE_IRQ_CNT5
- AFE_IRQ_CNT7
- AFE_IRQ_MCU_CLR
- AFE_IRQ_MCU_CNT0
- AFE_IRQ_MCU_CNT1
- AFE_IRQ_MCU_CNT11
- AFE_IRQ_MCU_CNT12
- AFE_IRQ_MCU_CNT1_MASK
- AFE_IRQ_MCU_CNT1_MASK_SFT
- AFE_IRQ_MCU_CNT1_SFT
- AFE_IRQ_MCU_CNT2
- AFE_IRQ_MCU_CNT2_MASK
- AFE_IRQ_MCU_CNT2_MASK_SFT
- AFE_IRQ_MCU_CNT2_SFT
- AFE_IRQ_MCU_CNT3
- AFE_IRQ_MCU_CNT3_MASK
- AFE_IRQ_MCU_CNT3_MASK_SFT
- AFE_IRQ_MCU_CNT3_SFT
- AFE_IRQ_MCU_CNT4
- AFE_IRQ_MCU_CNT4_MASK
- AFE_IRQ_MCU_CNT4_MASK_SFT
- AFE_IRQ_MCU_CNT4_SFT
- AFE_IRQ_MCU_CNT5
- AFE_IRQ_MCU_CNT5_MASK
- AFE_IRQ_MCU_CNT5_MASK_SFT
- AFE_IRQ_MCU_CNT5_SFT
- AFE_IRQ_MCU_CNT6
- AFE_IRQ_MCU_CNT7
- AFE_IRQ_MCU_CNT7_MASK
- AFE_IRQ_MCU_CNT7_MASK_SFT
- AFE_IRQ_MCU_CNT7_SFT
- AFE_IRQ_MCU_CNT8
- AFE_IRQ_MCU_CON
- AFE_IRQ_MCU_CON0
- AFE_IRQ_MCU_CON1
- AFE_IRQ_MCU_CON2
- AFE_IRQ_MCU_EN
- AFE_IRQ_MCU_EN1
- AFE_IRQ_MCU_EN_MASK
- AFE_IRQ_MCU_EN_MASK_SFT
- AFE_IRQ_MCU_EN_SFT
- AFE_IRQ_MCU_MON2
- AFE_IRQ_MCU_STATUS
- AFE_IRQ_MD32_EN_MASK
- AFE_IRQ_MD32_EN_MASK_SFT
- AFE_IRQ_MD32_EN_SFT
- AFE_IRQ_STATUS
- AFE_IRQ_STATUS_BITS
- AFE_LATCHOUT
- AFE_LDO_PWRDWNB
- AFE_LINEAR_PCM_DATA
- AFE_MASK
- AFE_MAX_CHAN_COUNT
- AFE_MAX_PORTS
- AFE_MAX_REGISTER
- AFE_MBEN
- AFE_MEMIF_HDALIGN
- AFE_MEMIF_HD_CON0
- AFE_MEMIF_HD_CON1
- AFE_MEMIF_HD_MODE
- AFE_MEMIF_MAXLEN
- AFE_MEMIF_MINLEN
- AFE_MEMIF_MON0
- AFE_MEMIF_MON1
- AFE_MEMIF_MON12
- AFE_MEMIF_MON13
- AFE_MEMIF_MON14
- AFE_MEMIF_MON15
- AFE_MEMIF_MON16
- AFE_MEMIF_MON17
- AFE_MEMIF_MON18
- AFE_MEMIF_MON19
- AFE_MEMIF_MON2
- AFE_MEMIF_MON20
- AFE_MEMIF_MON21
- AFE_MEMIF_MON22
- AFE_MEMIF_MON23
- AFE_MEMIF_MON24
- AFE_MEMIF_MON3
- AFE_MEMIF_MON4
- AFE_MEMIF_MON5
- AFE_MEMIF_MON6
- AFE_MEMIF_MON7
- AFE_MEMIF_MON8
- AFE_MEMIF_MON9
- AFE_MEMIF_MSB
- AFE_MEMIF_PBUF_SIZE
- AFE_MEMIF_PBUF_SIZE_DLM_32BYTES
- AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK
- AFE_MEMIF_PBUF_SIZE_DLM_CH
- AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK
- AFE_MEMIF_PBUF_SIZE_DLM_MASK
- AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE
- AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE
- AFE_MISC
- AFE_MISC_BGEN
- AFE_MISC_BGEN_SHT
- AFE_MISC_E32_EN
- AFE_MISC_E32_EN_SHT
- AFE_MISC_I32_EN
- AFE_MISC_I32_EN_SHT
- AFE_MISC_LD12_VDAJ
- AFE_MISC_LD12_VDAJ_MSK
- AFE_MISC_LD12_VDAJ_SHT
- AFE_MISC_MBEN
- AFE_MISC_MBEN_SHT
- AFE_MISC_USB_BGEN
- AFE_MISC_USB_BGEN_SHT
- AFE_MISC_USB_MBEN
- AFE_MISC_USB_MBEN_SHT
- AFE_MISC_WL_XTAL_CTRL
- AFE_MODE
- AFE_MODE_BASEBAND
- AFE_MODE_EU_HI_IF
- AFE_MODE_JAPAN_HI_IF
- AFE_MODE_LOW_IF
- AFE_MODE_US_HI_IF
- AFE_MODULE_AUDIO_DEV_INTERFACE
- AFE_MODULE_CLOCK_SET
- AFE_MODULE_TDM
- AFE_MOD_DAI_BASE
- AFE_MOD_DAI_BASE_MSB
- AFE_MOD_DAI_CUR
- AFE_MOD_DAI_CUR_MSB
- AFE_MOD_DAI_END
- AFE_MOD_DAI_END_MSB
- AFE_MOD_PCM_BASE
- AFE_MOD_PCM_CUR
- AFE_MON_SEL_MASK
- AFE_MON_SEL_MASK_SFT
- AFE_MON_SEL_SFT
- AFE_MRGIF_CON
- AFE_MRGIF_CON_I2S_MODE_32K
- AFE_MRGIF_CON_I2S_MODE_MASK
- AFE_MRGIF_CON_MRG_EN
- AFE_MRGIF_CON_MRG_I2S_EN
- AFE_MRGIF_MON0
- AFE_MRGIF_MON1
- AFE_MRGIF_MON2
- AFE_ON_MASK
- AFE_ON_MASK_SFT
- AFE_ON_RETM_MASK
- AFE_ON_RETM_MASK_SFT
- AFE_ON_RETM_SFT
- AFE_ON_SFT
- AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG
- AFE_PARAM_ID_CLOCK_SET
- AFE_PARAM_ID_HDMI_CONFIG
- AFE_PARAM_ID_I2S_CONFIG
- AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG
- AFE_PARAM_ID_LPAIF_CLK_CONFIG
- AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG
- AFE_PARAM_ID_SLIMBUS_CONFIG
- AFE_PARAM_ID_TDM_CONFIG
- AFE_PCM_NAME
- AFE_PHASE_SEL
- AFE_PLL_320_ENABLE
- AFE_PLL_CTRL
- AFE_PLL_EDGE_SELECT
- AFE_PLL_ENABLE
- AFE_PLL_LPF_ENABLE
- AFE_PLL_PWRDWNB
- AFE_PLL_WDOGB
- AFE_PORT_CMDRSP_GET_PARAM_V2
- AFE_PORT_CMD_DEVICE_START
- AFE_PORT_CMD_DEVICE_STOP
- AFE_PORT_CMD_SET_PARAM_V2
- AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL
- AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL
- AFE_PORT_I2S_6CHS
- AFE_PORT_I2S_8CHS
- AFE_PORT_I2S_MONO
- AFE_PORT_I2S_QUAD01
- AFE_PORT_I2S_QUAD23
- AFE_PORT_I2S_SD0
- AFE_PORT_I2S_SD0_1_2_3_MASK
- AFE_PORT_I2S_SD0_1_2_MASK
- AFE_PORT_I2S_SD0_1_MASK
- AFE_PORT_I2S_SD0_MASK
- AFE_PORT_I2S_SD1
- AFE_PORT_I2S_SD1_MASK
- AFE_PORT_I2S_SD2
- AFE_PORT_I2S_SD2_3_MASK
- AFE_PORT_I2S_SD2_MASK
- AFE_PORT_I2S_SD3
- AFE_PORT_I2S_SD3_MASK
- AFE_PORT_I2S_STEREO
- AFE_PORT_ID_HDMI_OVER_DP_RX
- AFE_PORT_ID_MULTICHAN_HDMI_RX
- AFE_PORT_ID_PRIMARY_MI2S_RX
- AFE_PORT_ID_PRIMARY_MI2S_TX
- AFE_PORT_ID_PRIMARY_TDM_RX
- AFE_PORT_ID_PRIMARY_TDM_RX_1
- AFE_PORT_ID_PRIMARY_TDM_RX_2
- AFE_PORT_ID_PRIMARY_TDM_RX_3
- AFE_PORT_ID_PRIMARY_TDM_RX_4
- AFE_PORT_ID_PRIMARY_TDM_RX_5
- AFE_PORT_ID_PRIMARY_TDM_RX_6
- AFE_PORT_ID_PRIMARY_TDM_RX_7
- AFE_PORT_ID_PRIMARY_TDM_TX
- AFE_PORT_ID_PRIMARY_TDM_TX_1
- AFE_PORT_ID_PRIMARY_TDM_TX_2
- AFE_PORT_ID_PRIMARY_TDM_TX_3
- AFE_PORT_ID_PRIMARY_TDM_TX_4
- AFE_PORT_ID_PRIMARY_TDM_TX_5
- AFE_PORT_ID_PRIMARY_TDM_TX_6
- AFE_PORT_ID_PRIMARY_TDM_TX_7
- AFE_PORT_ID_QUATERNARY_MI2S_RX
- AFE_PORT_ID_QUATERNARY_MI2S_TX
- AFE_PORT_ID_QUATERNARY_TDM_RX
- AFE_PORT_ID_QUATERNARY_TDM_RX_1
- AFE_PORT_ID_QUATERNARY_TDM_RX_2
- AFE_PORT_ID_QUATERNARY_TDM_RX_3
- AFE_PORT_ID_QUATERNARY_TDM_RX_4
- AFE_PORT_ID_QUATERNARY_TDM_RX_5
- AFE_PORT_ID_QUATERNARY_TDM_RX_6
- AFE_PORT_ID_QUATERNARY_TDM_RX_7
- AFE_PORT_ID_QUATERNARY_TDM_TX
- AFE_PORT_ID_QUATERNARY_TDM_TX_1
- AFE_PORT_ID_QUATERNARY_TDM_TX_2
- AFE_PORT_ID_QUATERNARY_TDM_TX_3
- AFE_PORT_ID_QUATERNARY_TDM_TX_4
- AFE_PORT_ID_QUATERNARY_TDM_TX_5
- AFE_PORT_ID_QUATERNARY_TDM_TX_6
- AFE_PORT_ID_QUATERNARY_TDM_TX_7
- AFE_PORT_ID_QUINARY_TDM_RX
- AFE_PORT_ID_QUINARY_TDM_RX_1
- AFE_PORT_ID_QUINARY_TDM_RX_2
- AFE_PORT_ID_QUINARY_TDM_RX_3
- AFE_PORT_ID_QUINARY_TDM_RX_4
- AFE_PORT_ID_QUINARY_TDM_RX_5
- AFE_PORT_ID_QUINARY_TDM_RX_6
- AFE_PORT_ID_QUINARY_TDM_RX_7
- AFE_PORT_ID_QUINARY_TDM_TX
- AFE_PORT_ID_QUINARY_TDM_TX_1
- AFE_PORT_ID_QUINARY_TDM_TX_2
- AFE_PORT_ID_QUINARY_TDM_TX_3
- AFE_PORT_ID_QUINARY_TDM_TX_4
- AFE_PORT_ID_QUINARY_TDM_TX_5
- AFE_PORT_ID_QUINARY_TDM_TX_6
- AFE_PORT_ID_QUINARY_TDM_TX_7
- AFE_PORT_ID_SECONDARY_MI2S_RX
- AFE_PORT_ID_SECONDARY_MI2S_TX
- AFE_PORT_ID_SECONDARY_TDM_RX
- AFE_PORT_ID_SECONDARY_TDM_RX_1
- AFE_PORT_ID_SECONDARY_TDM_RX_2
- AFE_PORT_ID_SECONDARY_TDM_RX_3
- AFE_PORT_ID_SECONDARY_TDM_RX_4
- AFE_PORT_ID_SECONDARY_TDM_RX_5
- AFE_PORT_ID_SECONDARY_TDM_RX_6
- AFE_PORT_ID_SECONDARY_TDM_RX_7
- AFE_PORT_ID_SECONDARY_TDM_TX
- AFE_PORT_ID_SECONDARY_TDM_TX_1
- AFE_PORT_ID_SECONDARY_TDM_TX_2
- AFE_PORT_ID_SECONDARY_TDM_TX_3
- AFE_PORT_ID_SECONDARY_TDM_TX_4
- AFE_PORT_ID_SECONDARY_TDM_TX_5
- AFE_PORT_ID_SECONDARY_TDM_TX_6
- AFE_PORT_ID_SECONDARY_TDM_TX_7
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX
- AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX
- AFE_PORT_ID_TDM_PORT_RANGE_END
- AFE_PORT_ID_TDM_PORT_RANGE_SIZE
- AFE_PORT_ID_TDM_PORT_RANGE_START
- AFE_PORT_ID_TERTIARY_MI2S_RX
- AFE_PORT_ID_TERTIARY_MI2S_TX
- AFE_PORT_ID_TERTIARY_TDM_RX
- AFE_PORT_ID_TERTIARY_TDM_RX_1
- AFE_PORT_ID_TERTIARY_TDM_RX_2
- AFE_PORT_ID_TERTIARY_TDM_RX_3
- AFE_PORT_ID_TERTIARY_TDM_RX_4
- AFE_PORT_ID_TERTIARY_TDM_RX_5
- AFE_PORT_ID_TERTIARY_TDM_RX_6
- AFE_PORT_ID_TERTIARY_TDM_RX_7
- AFE_PORT_ID_TERTIARY_TDM_TX
- AFE_PORT_ID_TERTIARY_TDM_TX_1
- AFE_PORT_ID_TERTIARY_TDM_TX_2
- AFE_PORT_ID_TERTIARY_TDM_TX_3
- AFE_PORT_ID_TERTIARY_TDM_TX_4
- AFE_PORT_ID_TERTIARY_TDM_TX_5
- AFE_PORT_ID_TERTIARY_TDM_TX_6
- AFE_PORT_ID_TERTIARY_TDM_TX_7
- AFE_PORT_MAX
- AFE_PORT_MAX_AUDIO_CHAN_CNT
- AFE_RDET_MARK
- AFE_REGISTER_WRITE_DELAY
- AFE_REG_AFE_REG_SPARE_BASEADDR
- AFE_REG_AFE_REG_SPARE_BASEADDR1
- AFE_REG_AFE_REG_SPARE_BASEADDR2
- AFE_REG_AFE_REG_SPARE_BASEADDR3
- AFE_REG_D2A_FSK_BIAS_BASEADDR
- AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR
- AFE_REG_NUM
- AFE_RESERVED_MASK
- AFE_RESERVED_MASK_SFT
- AFE_RESERVED_SFT
- AFE_RLYCNT_MARK
- AFE_RXCONFIG_0
- AFE_RXCONFIG_1
- AFE_RXCONFIG_2
- AFE_RXIN_MARK
- AFE_RX_LP_COUNTER
- AFE_SCLK_MARK
- AFE_SGEN_CON0
- AFE_SHIFT
- AFE_SIDETONE_COEFF
- AFE_SIDETONE_CON0
- AFE_SIDETONE_CON1
- AFE_SIDETONE_DEBUG
- AFE_SIDETONE_GAIN
- AFE_SIDETONE_MON
- AFE_SINEGEN_CON0
- AFE_SINEGEN_CON2
- AFE_SINEGEN_CON_TDM
- AFE_SRAM_DELSEL_CON0
- AFE_SRAM_DELSEL_CON1
- AFE_SRAM_DELSEL_CON2
- AFE_SRAM_DELSEL_CON3
- AFE_SVC_CMD_SET_PARAM
- AFE_TDM_CH_START_O30_O31
- AFE_TDM_CH_START_O32_O33
- AFE_TDM_CH_START_O34_O35
- AFE_TDM_CH_START_O36_O37
- AFE_TDM_CH_ZERO
- AFE_TDM_CON1
- AFE_TDM_CON1_1_BCK_DELAY
- AFE_TDM_CON1_32_BCK_CYCLES
- AFE_TDM_CON1_BCK_INV
- AFE_TDM_CON1_EN
- AFE_TDM_CON1_LRCK_INV
- AFE_TDM_CON1_LRCK_WIDTH
- AFE_TDM_CON1_MSB_ALIGNED
- AFE_TDM_CON1_WLEN_32BIT
- AFE_TDM_CON2
- AFE_TOP_CON0
- AFE_TXOUT_MARK
- AFE_TX_CONFIG
- AFE_UL2_BASE
- AFE_UL2_CUR
- AFE_UL2_END
- AFE_UL3_BASE
- AFE_UL3_CUR
- AFE_UL3_END
- AFE_UL4_BASE
- AFE_UL4_CUR
- AFE_UL4_END
- AFE_UL5_BASE
- AFE_UL5_CUR
- AFE_UL5_END
- AFE_UL_DL_CON0_RESERVED_MASK
- AFE_UL_DL_CON0_RESERVED_MASK_SFT
- AFE_UL_DL_CON0_RESERVED_SFT
- AFE_UL_LR_SWAP_MASK
- AFE_UL_LR_SWAP_MASK_SFT
- AFE_UL_LR_SWAP_SFT
- AFE_VDAC_OTHERS_0
- AFE_VDCA_ICTRL_0
- AFE_VUL2_BASE
- AFE_VUL2_BASE_MSB
- AFE_VUL2_CUR
- AFE_VUL2_CUR_MSB
- AFE_VUL2_END
- AFE_VUL2_END_MSB
- AFE_VUL_BASE
- AFE_VUL_BASE_MSB
- AFE_VUL_CUR
- AFE_VUL_CUR_MSB
- AFE_VUL_D2_BASE
- AFE_VUL_D2_BASE_MSB
- AFE_VUL_D2_CUR
- AFE_VUL_D2_CUR_MSB
- AFE_VUL_D2_END
- AFE_VUL_D2_END_MSB
- AFE_VUL_END
- AFE_VUL_END_MSB
- AFE_XTAL_BT_GATE
- AFE_XTAL_B_SELECT
- AFE_XTAL_CTRL
- AFE_XTAL_ENABLE
- AFE_XTAL_GATE_AFE
- AFE_XTAL_GATE_DIG
- AFE_XTAL_GATE_USB
- AFE_XTAL_RF_GATE
- AFF
- AFFD
- AFFD_MASK
- AFFD_SHIFT
- AFFINITY
- AFFINITY_LIST
- AFFINITY_MASK
- AFFSNAMEMAX
- AFFS_AC_MASK
- AFFS_AC_SIZE
- AFFS_BLOCK
- AFFS_CACHE_SIZE
- AFFS_DATA
- AFFS_DATA_HEAD
- AFFS_EPOCH_DELTA
- AFFS_GET_HASHENTRY
- AFFS_HARDBLOCKS_H
- AFFS_HEAD
- AFFS_I
- AFFS_LC_SIZE
- AFFS_MOUNT_SF_BM_VALID
- AFFS_MOUNT_SF_IMMUTABLE
- AFFS_MOUNT_SF_INTL
- AFFS_MOUNT_SF_MUFS
- AFFS_MOUNT_SF_NO_TRUNCATE
- AFFS_MOUNT_SF_OFS
- AFFS_MOUNT_SF_PREFIX
- AFFS_MOUNT_SF_QUIET
- AFFS_MOUNT_SF_SETGID
- AFFS_MOUNT_SF_SETMODE
- AFFS_MOUNT_SF_SETUID
- AFFS_MOUNT_SF_VERBOSE
- AFFS_ROOT_BMAPS
- AFFS_ROOT_HEAD
- AFFS_ROOT_TAIL
- AFFS_SB
- AFFS_SUPER_MAGIC
- AFFS_TAIL
- AFF_AUTO
- AFF_DEV_LOCAL
- AFF_IRQ_LOCAL
- AFF_MASK
- AFF_MERGED
- AFF_NUMA_LOCAL
- AFF_OFFSETS_SET
- AFF_SHIFT
- AFGTxAccumPhi
- AFH_PSD
- AFIFO_OVER
- AFIFO_UNDER
- AFI_AFI_INTR_ENABLE
- AFI_AXI_BAR0_START
- AFI_AXI_BAR0_SZ
- AFI_AXI_BAR1_START
- AFI_AXI_BAR1_SZ
- AFI_AXI_BAR2_START
- AFI_AXI_BAR2_SZ
- AFI_AXI_BAR3_START
- AFI_AXI_BAR3_SZ
- AFI_AXI_BAR4_START
- AFI_AXI_BAR4_SZ
- AFI_AXI_BAR5_START
- AFI_AXI_BAR5_SZ
- AFI_CACHE_BAR0_ST
- AFI_CACHE_BAR0_SZ
- AFI_CACHE_BAR1_ST
- AFI_CACHE_BAR1_SZ
- AFI_CONFIGURATION
- AFI_CONFIGURATION_CLKEN_OVERRIDE
- AFI_CONFIGURATION_EN_FPCI
- AFI_FPCI_BAR0
- AFI_FPCI_BAR1
- AFI_FPCI_BAR2
- AFI_FPCI_BAR3
- AFI_FPCI_BAR4
- AFI_FPCI_BAR5
- AFI_FPCI_ERROR_MASKS
- AFI_FUSE
- AFI_FUSE_PCIE_T0_GEN2_DIS
- AFI_INTR_AXI_DECODE_ERROR
- AFI_INTR_CLKCLAMP_SENSE
- AFI_INTR_CODE
- AFI_INTR_CODE_MASK
- AFI_INTR_EN_AXI_DECERR
- AFI_INTR_EN_DFPCI_DECERR
- AFI_INTR_EN_FPCI_TIMEOUT
- AFI_INTR_EN_INI_DECERR
- AFI_INTR_EN_INI_SLVERR
- AFI_INTR_EN_PRSNT_SENSE
- AFI_INTR_EN_TGT_DECERR
- AFI_INTR_EN_TGT_SLVERR
- AFI_INTR_EN_TGT_WRERR
- AFI_INTR_FPCI_DECODE_ERROR
- AFI_INTR_FPCI_TIMEOUT
- AFI_INTR_INI_DECODE_ERROR
- AFI_INTR_INI_SLAVE_ERROR
- AFI_INTR_INVALID_WRITE
- AFI_INTR_LEGACY
- AFI_INTR_MASK
- AFI_INTR_MASK_INT_MASK
- AFI_INTR_MASK_MSI_MASK
- AFI_INTR_MASTER_ABORT
- AFI_INTR_P2P_ERROR
- AFI_INTR_PE_CLKREQ_SENSE
- AFI_INTR_PE_PRSNT_SENSE
- AFI_INTR_RDY4PD_SENSE
- AFI_INTR_SIGNATURE
- AFI_INTR_TARGET_ABORT
- AFI_MSI_AXI_BAR_ST
- AFI_MSI_BAR_SZ
- AFI_MSI_EN_VEC0
- AFI_MSI_EN_VEC1
- AFI_MSI_EN_VEC2
- AFI_MSI_EN_VEC3
- AFI_MSI_EN_VEC4
- AFI_MSI_EN_VEC5
- AFI_MSI_EN_VEC6
- AFI_MSI_EN_VEC7
- AFI_MSI_FPCI_BAR_ST
- AFI_MSI_VEC0
- AFI_MSI_VEC1
- AFI_MSI_VEC2
- AFI_MSI_VEC3
- AFI_MSI_VEC4
- AFI_MSI_VEC5
- AFI_MSI_VEC6
- AFI_MSI_VEC7
- AFI_PCIE_CONFIG
- AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO
- AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL
- AFI_PCIE_CONFIG_PCIE_DISABLE
- AFI_PCIE_CONFIG_PCIE_DISABLE_ALL
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1
- AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1
- AFI_PCIE_PME
- AFI_PEX0_CTRL
- AFI_PEX1_CTRL
- AFI_PEXBIAS_CTRL_0
- AFI_PEX_CTRL_CLKREQ_EN
- AFI_PEX_CTRL_OVERRIDE_EN
- AFI_PEX_CTRL_REFCLK_EN
- AFI_PEX_CTRL_RST
- AFI_PLLE_CONTROL
- AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL
- AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN
- AFI_SM_INTR_ENABLE
- AFI_SM_INTR_INTA_ASSERT
- AFI_SM_INTR_INTA_DEASSERT
- AFI_SM_INTR_INTB_ASSERT
- AFI_SM_INTR_INTB_DEASSERT
- AFI_SM_INTR_INTC_ASSERT
- AFI_SM_INTR_INTC_DEASSERT
- AFI_SM_INTR_INTD_ASSERT
- AFI_SM_INTR_INTD_DEASSERT
- AFI_UPPER_FPCI_ADDRESS
- AFLAG
- AFMT_60958_0
- AFMT_60958_0__AFMT_60958_CS_A_MASK
- AFMT_60958_0__AFMT_60958_CS_A__SHIFT
- AFMT_60958_0__AFMT_60958_CS_B_MASK
- AFMT_60958_0__AFMT_60958_CS_B__SHIFT
- AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK
- AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT
- AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK
- AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
- AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT
- AFMT_60958_0__AFMT_60958_CS_C_MASK
- AFMT_60958_0__AFMT_60958_CS_C__SHIFT
- AFMT_60958_0__AFMT_60958_CS_D_MASK
- AFMT_60958_0__AFMT_60958_CS_D__SHIFT
- AFMT_60958_0__AFMT_60958_CS_MODE_MASK
- AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT
- AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK
- AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK
- AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT
- AFMT_60958_1
- AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK
- AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK
- AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT
- AFMT_60958_1__AFMT_60958_VALID_L_MASK
- AFMT_60958_1__AFMT_60958_VALID_L__SHIFT
- AFMT_60958_1__AFMT_60958_VALID_R_MASK
- AFMT_60958_1__AFMT_60958_VALID_R__SHIFT
- AFMT_60958_2
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK
- AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AFMT_60958_CS_A
- AFMT_60958_CS_B
- AFMT_60958_CS_C
- AFMT_60958_CS_CATEGORY_CODE
- AFMT_60958_CS_CHANNEL_NUMBER_2
- AFMT_60958_CS_CHANNEL_NUMBER_3
- AFMT_60958_CS_CHANNEL_NUMBER_4
- AFMT_60958_CS_CHANNEL_NUMBER_5
- AFMT_60958_CS_CHANNEL_NUMBER_6
- AFMT_60958_CS_CHANNEL_NUMBER_7
- AFMT_60958_CS_CHANNEL_NUMBER_L
- AFMT_60958_CS_CHANNEL_NUMBER_R
- AFMT_60958_CS_CLOCK_ACCURACY
- AFMT_60958_CS_D
- AFMT_60958_CS_MODE
- AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY
- AFMT_60958_CS_SAMPLING_FREQUENCY
- AFMT_60958_CS_SOURCE
- AFMT_60958_CS_SOURCE_NUMBER
- AFMT_60958_CS_UPDATE
- AFMT_60958_CS_VALID_L
- AFMT_60958_CS_VALID_R
- AFMT_60958_CS_WORD_LENGTH
- AFMT_AC3
- AFMT_AUDIO_CHANNEL_ENABLE
- AFMT_AUDIO_CHANNEL_SWAP
- AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT
- AFMT_AUDIO_CRC_AUTO_RESTART
- AFMT_AUDIO_CRC_CH0_SIG
- AFMT_AUDIO_CRC_CH1_SIG
- AFMT_AUDIO_CRC_CH2_SIG
- AFMT_AUDIO_CRC_CH3_SIG
- AFMT_AUDIO_CRC_CH4_SIG
- AFMT_AUDIO_CRC_CH5_SIG
- AFMT_AUDIO_CRC_CH6_SIG
- AFMT_AUDIO_CRC_CH7_SIG
- AFMT_AUDIO_CRC_CONTROL
- AFMT_AUDIO_CRC_CONTROL_CH_SEL
- AFMT_AUDIO_CRC_CONTROL_CONT
- AFMT_AUDIO_CRC_CONTROL_SOURCE
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK
- AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT
- AFMT_AUDIO_CRC_EN
- AFMT_AUDIO_CRC_ONESHOT
- AFMT_AUDIO_CRC_RESERVED
- AFMT_AUDIO_CRC_RESERVED_10
- AFMT_AUDIO_CRC_RESERVED_11
- AFMT_AUDIO_CRC_RESERVED_12
- AFMT_AUDIO_CRC_RESERVED_13
- AFMT_AUDIO_CRC_RESERVED_14
- AFMT_AUDIO_CRC_RESERVED_8
- AFMT_AUDIO_CRC_RESERVED_9
- AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK
- AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT
- AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK
- AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT
- AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT
- AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK
- AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT
- AFMT_AUDIO_ENABLE
- AFMT_AUDIO_HBR_ENABLE
- AFMT_AUDIO_INFO0
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK
- AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT
- AFMT_AUDIO_INFO1
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK
- AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT
- AFMT_AUDIO_INFO_CA
- AFMT_AUDIO_INFO_CC
- AFMT_AUDIO_INFO_CHECKSUM
- AFMT_AUDIO_INFO_CHECKSUM_OFFSET
- AFMT_AUDIO_INFO_CT
- AFMT_AUDIO_INFO_CXT
- AFMT_AUDIO_INFO_DM_INH
- AFMT_AUDIO_INFO_DM_INH_LSV
- AFMT_AUDIO_INFO_LFEBPL
- AFMT_AUDIO_INFO_LSV
- AFMT_AUDIO_INFO_SOURCE
- AFMT_AUDIO_INFO_UPDATE
- AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS
- AFMT_AUDIO_LAYOUT_OVRD
- AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER
- AFMT_AUDIO_LAYOUT_SELECT
- AFMT_AUDIO_PACKET_CONTROL
- AFMT_AUDIO_PACKET_CONTROL2
- AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK
- AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT
- AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND
- AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS
- AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT
- AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK
- AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT
- AFMT_AUDIO_PACKET_SENT_DISABLED
- AFMT_AUDIO_PACKET_SENT_ENABLED
- AFMT_AUDIO_SAMPLE_SEND
- AFMT_AUDIO_SRC_CONTROL
- AFMT_AUDIO_SRC_CONTROL_SELECT
- AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK
- AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
- AFMT_AUDIO_SRC_FROM_AZ_STREAM0
- AFMT_AUDIO_SRC_FROM_AZ_STREAM1
- AFMT_AUDIO_SRC_FROM_AZ_STREAM2
- AFMT_AUDIO_SRC_FROM_AZ_STREAM3
- AFMT_AUDIO_SRC_FROM_AZ_STREAM4
- AFMT_AUDIO_SRC_FROM_AZ_STREAM5
- AFMT_AUDIO_SRC_RESERVED
- AFMT_AUDIO_SRC_SELECT
- AFMT_AUDIO_TEST_CH_DISABLE
- AFMT_AUDIO_TEST_EN
- AFMT_AVI_INFO0
- AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT
- AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK
- AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT
- AFMT_AVI_INFO1
- AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT
- AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT
- AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT
- AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT
- AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT
- AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK
- AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT
- AFMT_AVI_INFO2
- AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK
- AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT
- AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK
- AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT
- AFMT_AVI_INFO3
- AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK
- AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT
- AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK
- AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT
- AFMT_AVI_INFO_A
- AFMT_AVI_INFO_B
- AFMT_AVI_INFO_BOTTOM
- AFMT_AVI_INFO_C
- AFMT_AVI_INFO_CHECKSUM
- AFMT_AVI_INFO_CN
- AFMT_AVI_INFO_C_M_R
- AFMT_AVI_INFO_EC
- AFMT_AVI_INFO_ITC
- AFMT_AVI_INFO_ITC_EC_Q_SC
- AFMT_AVI_INFO_LEFT
- AFMT_AVI_INFO_M
- AFMT_AVI_INFO_PR
- AFMT_AVI_INFO_Q
- AFMT_AVI_INFO_R
- AFMT_AVI_INFO_RIGHT
- AFMT_AVI_INFO_S
- AFMT_AVI_INFO_SC
- AFMT_AVI_INFO_TOP
- AFMT_AVI_INFO_VERSION
- AFMT_AVI_INFO_VIC
- AFMT_AVI_INFO_Y
- AFMT_AVI_INFO_YQ
- AFMT_AVI_INFO_Y_A_B_S
- AFMT_AVI_INFO_Y_RGB
- AFMT_AVI_INFO_Y_YCBCR422
- AFMT_AVI_INFO_Y_YCBCR444
- AFMT_AZ_AUDIO_ENABLE_CHG
- AFMT_AZ_AUDIO_ENABLE_CHG_ACK
- AFMT_AZ_AUDIO_ENABLE_CHG_MASK
- AFMT_AZ_FORMAT_WTRIG
- AFMT_AZ_FORMAT_WTRIG_ACK
- AFMT_AZ_FORMAT_WTRIG_INT
- AFMT_AZ_FORMAT_WTRIG_MASK
- AFMT_A_LAW
- AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK
- AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT
- AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK
- AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT
- AFMT_DP_AUDIO_STREAM_ID
- AFMT_FLOAT
- AFMT_GENERIC0_0
- AFMT_GENERIC0_1
- AFMT_GENERIC0_2
- AFMT_GENERIC0_3
- AFMT_GENERIC0_4
- AFMT_GENERIC0_5
- AFMT_GENERIC0_6
- AFMT_GENERIC0_7
- AFMT_GENERIC0_HDR
- AFMT_GENERIC0_UPDATE
- AFMT_GENERIC1_0
- AFMT_GENERIC1_1
- AFMT_GENERIC1_2
- AFMT_GENERIC1_3
- AFMT_GENERIC1_4
- AFMT_GENERIC1_5
- AFMT_GENERIC1_6
- AFMT_GENERIC1_HDR
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK
- AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK
- AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK
- AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK
- AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK
- AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK
- AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK
- AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK
- AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK
- AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT
- AFMT_I2S
- AFMT_IMA_ADPCM
- AFMT_INFOFRAME_CONTROL0
- AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE
- AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK
- AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT
- AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
- AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT
- AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK
- AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT
- AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS
- AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK
- AFMT_INTERRUPT_DISABLE
- AFMT_INTERRUPT_ENABLE
- AFMT_INTERRUPT_STATUS_CHG_MASK
- AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK
- AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT
- AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK
- AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT
- AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK
- AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK
- AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK
- AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK
- AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK
- AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK
- AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK
- AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK
- AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK
- AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT
- AFMT_MPEG
- AFMT_MPEG_INFO0
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK
- AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT
- AFMT_MPEG_INFO1
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK
- AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT
- AFMT_MPEG_INFO_CHECKSUM
- AFMT_MPEG_INFO_FR
- AFMT_MPEG_INFO_MB0
- AFMT_MPEG_INFO_MB1
- AFMT_MPEG_INFO_MB2
- AFMT_MPEG_INFO_MB3
- AFMT_MPEG_INFO_MF
- AFMT_MPEG_INFO_UPDATE
- AFMT_MU_LAW
- AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED
- AFMT_QUERY
- AFMT_RAMP_CONTROL0
- AFMT_RAMP_CONTROL0_SIGN
- AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK
- AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT
- AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK
- AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT
- AFMT_RAMP_CONTROL1
- AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK
- AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT
- AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK
- AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT
- AFMT_RAMP_CONTROL2
- AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK
- AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT
- AFMT_RAMP_CONTROL3
- AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK
- AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT
- AFMT_RAMP_DATA_SIGN
- AFMT_RAMP_DEC_COUNT
- AFMT_RAMP_INC_COUNT
- AFMT_RAMP_MAX_COUNT
- AFMT_RAMP_MIN_COUNT
- AFMT_RAMP_SIGNED
- AFMT_RAMP_UNSIGNED
- AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED
- AFMT_RESET_FIFO_WHEN_AUDIO_DIS
- AFMT_S16_BE
- AFMT_S16_LE
- AFMT_S16_NE
- AFMT_S24_BE
- AFMT_S24_LE
- AFMT_S24_PACKED
- AFMT_S32_BE
- AFMT_S32_LE
- AFMT_S8
- AFMT_SPDIF
- AFMT_SPDIF_RAW
- AFMT_STATUS
- AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK
- AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT
- AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK
- AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT
- AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK
- AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT
- AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK
- AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT
- AFMT_U16_BE
- AFMT_U16_LE
- AFMT_U8
- AFMT_UNUSED
- AFMT_VBI_GSP0_INDEX
- AFMT_VBI_GSP10_INDEX
- AFMT_VBI_GSP1_INDEX
- AFMT_VBI_GSP2_INDEX
- AFMT_VBI_GSP3_INDEX
- AFMT_VBI_GSP4_INDEX
- AFMT_VBI_GSP5_INDEX
- AFMT_VBI_GSP6_INDEX
- AFMT_VBI_GSP7_INDEX
- AFMT_VBI_GSP8_INDEX
- AFMT_VBI_GSP9_INDEX
- AFMT_VBI_GSP_INDEX
- AFMT_VBI_PACKET_CONTROL
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK
- AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT
- AFMT_VORBIS
- AFMT__MEM_PG
- AFMT__MEM_PG__0
- AFORK
- AFOU
- AFPID
- AFR
- AFR0
- AFR1
- AFR2
- AFRAFRC_MASK
- AFRALFRC_MASK
- AFRB_MASK
- AFRC_MASK
- AFR_1p2
- AFR_1p4
- AFR_1p8
- AFR_CARDBEN
- AFR_CLKRUN_SEL
- AFR_CardBEn
- AFR_FUNCREGEN
- AFR_FuncRegEn
- AFR_NO_RATE
- AFR_ON_OFF
- AFR_SPPED
- AFSCBMAX
- AFSCM_CB_DROPPED
- AFSCM_CB_EXCLUSIVE
- AFSCM_CB_SHARED
- AFSCM_CB_UNTYPED
- AFSM_HSUS
- AFSM_PCIE
- AFSNAMEMAX
- AFSOPAQUEMAX
- AFSPATHMAX
- AFSR0_EL1
- AFSR1_EL1
- AFSRE
- AFSTOKEN_BDATALN_MAX
- AFSTOKEN_CELL_MAX
- AFSTOKEN_DATA_MAX
- AFSTOKEN_GK_KEY_MAX
- AFSTOKEN_GK_TOKEN_MAX
- AFSTOKEN_K5_ADDRESSES_MAX
- AFSTOKEN_K5_AUTHDATA_MAX
- AFSTOKEN_K5_COMPONENTS_MAX
- AFSTOKEN_K5_NAME_MAX
- AFSTOKEN_K5_REALM_MAX
- AFSTOKEN_K5_TIX_MAX
- AFSTOKEN_LENGTH_MAX
- AFSTOKEN_MAX
- AFSTOKEN_RK_TIX_MAX
- AFSTOKEN_STRING_MAX
- AFSV1_FOOTER_MAGIC
- AFSV2_FOOTER_MAGIC1
- AFSV2_FOOTER_MAGIC2
- AFSVL_BACKVOL
- AFSVL_BADENTRY
- AFSVL_BADINDEX
- AFSVL_BADNAME
- AFSVL_BADPARTITION
- AFSVL_BADREFCOUNT
- AFSVL_BADRELLOCKTYPE
- AFSVL_BADSERVER
- AFSVL_BADSERVERFLAG
- AFSVL_BADVOLIDBUMP
- AFSVL_BADVOLOPER
- AFSVL_BADVOLTYPE
- AFSVL_CREATEFAIL
- AFSVL_DUPREPSERVER
- AFSVL_EMPTY
- AFSVL_ENTDELETED
- AFSVL_ENTRYLOCKED
- AFSVL_Errors
- AFSVL_IDALREADYHASHED
- AFSVL_IDEXIST
- AFSVL_IO
- AFSVL_NAMEEXIST
- AFSVL_NOENT
- AFSVL_NOMEM
- AFSVL_NOREPSERVER
- AFSVL_Operations
- AFSVL_PERM
- AFSVL_REPSFULL
- AFSVL_RERELEASE
- AFSVL_ROVOL
- AFSVL_RWNOTFOUND
- AFSVL_RWVOL
- AFSVL_SIZEEXCEEDED
- AFSXE
- AFS_ACE_ADMINISTER
- AFS_ACE_DELETE
- AFS_ACE_INSERT
- AFS_ACE_LOCK
- AFS_ACE_LOOKUP
- AFS_ACE_READ
- AFS_ACE_USER_A
- AFS_ACE_USER_B
- AFS_ACE_USER_C
- AFS_ACE_USER_D
- AFS_ACE_USER_E
- AFS_ACE_USER_F
- AFS_ACE_USER_G
- AFS_ACE_USER_H
- AFS_ACE_WRITE
- AFS_BLOCK_SIZE
- AFS_BVEC_MAX
- AFS_CALL_CL_AWAIT_REPLY
- AFS_CALL_CL_PROC_REPLY
- AFS_CALL_CL_REQUESTING
- AFS_CALL_COMPLETE
- AFS_CALL_SV_AWAIT_ACK
- AFS_CALL_SV_AWAIT_OP_ID
- AFS_CALL_SV_AWAIT_REQUEST
- AFS_CALL_SV_REPLYING
- AFS_CAP_ERROR_TRANSLATION
- AFS_CELL_ACTIVATING
- AFS_CELL_ACTIVE
- AFS_CELL_DEACTIVATING
- AFS_CELL_FAILED
- AFS_CELL_FL_DO_LOOKUP
- AFS_CELL_FL_NO_GC
- AFS_CELL_INACTIVE
- AFS_CELL_MAX_ADDRS
- AFS_CELL_UNSET
- AFS_CM_H
- AFS_CM_Operations
- AFS_CM_PORT
- AFS_DEBUG_KDEBUG
- AFS_DEBUG_KENTER
- AFS_DEBUG_KLEAVE
- AFS_DIR_BLOCKS_PER_PAGE
- AFS_DIR_BLOCKS_WITH_CTR
- AFS_DIR_BLOCK_SIZE
- AFS_DIR_DIRENT_SIZE
- AFS_DIR_HASHTBL_SIZE
- AFS_DIR_MAGIC
- AFS_DIR_MAX_BLOCKS
- AFS_DIR_MAX_SLOTS
- AFS_DIR_RESV_BLOCKS
- AFS_DIR_RESV_BLOCKS0
- AFS_DIR_SLOTS_PER_BLOCK
- AFS_FSTATUS_VERSION
- AFS_FS_CURSOR_CUR_ONLY
- AFS_FS_CURSOR_INTR
- AFS_FS_CURSOR_NO_VSLEEP
- AFS_FS_CURSOR_STOP
- AFS_FS_CURSOR_VBUSY
- AFS_FS_CURSOR_VMOVED
- AFS_FS_CURSOR_VNOVOL
- AFS_FS_Errors
- AFS_FS_H
- AFS_FS_I
- AFS_FS_MAGIC
- AFS_FS_Operations
- AFS_FS_PORT
- AFS_FS_S
- AFS_FTYPE_DIR
- AFS_FTYPE_FILE
- AFS_FTYPE_INVALID
- AFS_FTYPE_SYMLINK
- AFS_H
- AFS_LOCKWAIT
- AFS_LOCK_GRANTED
- AFS_LOCK_PENDING
- AFS_LOCK_READ
- AFS_LOCK_WRITE
- AFS_LOCK_YOUR_TRY
- AFS_MAXCELLNAME
- AFS_MAXNSERVERS
- AFS_MAXTYPES
- AFS_MAXVOLNAME
- AFS_MAX_ADDRESSES
- AFS_NMAXNSERVERS
- AFS_NR_SYSNAME
- AFS_PRIV_MAX
- AFS_PRIV_SHIFT
- AFS_PROBE_MAX_LIFESPAN
- AFS_SERVER_FL_HAVE_EPOCH
- AFS_SERVER_FL_IS_YFS
- AFS_SERVER_FL_MAY_HAVE_CB
- AFS_SERVER_FL_NOT_FOUND
- AFS_SERVER_FL_NOT_READY
- AFS_SERVER_FL_NO_IBULK
- AFS_SERVER_FL_NO_RM2
- AFS_SERVER_FL_PROBED
- AFS_SERVER_FL_PROBING
- AFS_SERVER_FL_UPDATING
- AFS_SERVER_FL_VL_FAIL
- AFS_SET_GROUP
- AFS_SET_MODE
- AFS_SET_MTIME
- AFS_SET_OWNER
- AFS_SET_SEG_SIZE
- AFS_SUPER_MAGIC
- AFS_VLADDR_INDEX
- AFS_VLADDR_IPADDR
- AFS_VLADDR_UUID
- AFS_VLDB_HAS_BAK
- AFS_VLDB_HAS_RO
- AFS_VLDB_HAS_RW
- AFS_VLDB_MAXNAMELEN
- AFS_VLDB_QUERY_ERROR
- AFS_VLDB_QUERY_VALID
- AFS_VLF_BACKEXISTS
- AFS_VLF_ROEXISTS
- AFS_VLF_RWEXISTS
- AFS_VLSERVER_FL_IS_YFS
- AFS_VLSERVER_FL_PROBED
- AFS_VLSERVER_FL_PROBING
- AFS_VLSF_BACKVOL
- AFS_VLSF_DONTUSE
- AFS_VLSF_NEWREPSITE
- AFS_VLSF_ROVOL
- AFS_VLSF_RWVOL
- AFS_VLSF_UUID
- AFS_VL_CURSOR_RETRIED
- AFS_VL_CURSOR_RETRY
- AFS_VL_CURSOR_STOP
- AFS_VL_H
- AFS_VL_MAX_LIFESPAN
- AFS_VL_PORT
- AFS_VNODE_AUTOCELL
- AFS_VNODE_CB_PROMISED
- AFS_VNODE_DELETED
- AFS_VNODE_DIR_VALID
- AFS_VNODE_LOCK_DELETED
- AFS_VNODE_LOCK_EXTENDING
- AFS_VNODE_LOCK_GRANTED
- AFS_VNODE_LOCK_NEED_UNLOCK
- AFS_VNODE_LOCK_NONE
- AFS_VNODE_LOCK_SETTING
- AFS_VNODE_LOCK_UNLOCKING
- AFS_VNODE_LOCK_WAITING_FOR_CB
- AFS_VNODE_MOUNTPOINT
- AFS_VNODE_NEW_CONTENT
- AFS_VNODE_PSEUDODIR
- AFS_VNODE_TO_I
- AFS_VNODE_UNSET
- AFS_VNODE_ZAP_DATA
- AFS_VOLUME_BUSY
- AFS_VOLUME_DELETED
- AFS_VOLUME_NEEDS_UPDATE
- AFS_VOLUME_OFFLINE
- AFS_VOLUME_UPDATING
- AFS_VOLUME_WAIT
- AFS_VOL_VTM_BAK
- AFS_VOL_VTM_RO
- AFS_VOL_VTM_RW
- AFTER_EQ
- AFTER_LAST_ERR_CODE
- AFTER_SUSPEND_DOWN
- AFTER_SUSPEND_POWER
- AFTER_SUSPEND_RESTART
- AFTER_SUSPEND_UP
- AFUD_AFU_DIRECTED
- AFUD_CR_LEN
- AFUD_DEDICATED_PROCESS
- AFUD_EB_LEN
- AFUD_MULTIMODE
- AFUD_NUM_CRS
- AFUD_NUM_INTS_PER_PROC
- AFUD_NUM_PROCS
- AFUD_PPPSA_LEN
- AFUD_PPPSA_PP
- AFUD_PPPSA_PSA
- AFUD_PUSH_BLOCK_TRANSFER
- AFUD_READ
- AFUD_READ_CR
- AFUD_READ_CR_OFF
- AFUD_READ_EB
- AFUD_READ_EB_OFF
- AFUD_READ_INFO
- AFUD_READ_LE
- AFUD_READ_PPPSA
- AFUD_READ_PPPSA_OFF
- AFUD_TIME_SLICED
- AFULL
- AFULL_MASK
- AFULL_SHIFT
- AFU_COMMANDS
- AFU_EVENT_BODY_MAX_SIZE
- AFU_GSYNC
- AFU_HW_SYNC
- AFU_INDEX_MASK
- AFU_INDEX_SHIFT
- AFU_LW_SYNC
- AFU_PRESENT
- AF_16x
- AF_2x
- AF_4x
- AF_8044_NO_FW_DUMP
- AF_82XX_DUMP_READING
- AF_82XX_FW_DUMPED
- AF_83XX_IOCB_INTR_ON
- AF_83XX_MBOX_INTR_ON
- AF_8XXX_RST_OWNER
- AF_8x
- AF_AFINCV
- AF_ALAW_EN
- AF_ALG
- AF_APPLETALK
- AF_ASH
- AF_ATMPVC
- AF_ATMSVC
- AF_AX25
- AF_BIST_SIGNAT
- AF_BLUETOOTH
- AF_BRIDGE
- AF_BUILD_DDB_LIST
- AF_BUSRST_DETECTED
- AF_BUSRST_NEEDED
- AF_BUSRST_PENDING
- AF_BUSYAF
- AF_CAIF
- AF_CAN
- AF_CAN_H
- AF_CHPRST_DETECTED
- AF_CHPRST_NEEDED
- AF_CHPRST_PENDING
- AF_CHPRST_STARTED
- AF_COEF_MASK0
- AF_COEF_MASK1
- AF_COEF_SHIFT
- AF_COMM_LIST_TOGGLE
- AF_DECnet
- AF_DEGRADED_MODE
- AF_DISABLED
- AF_DISABLE_ACB_COMPLETE
- AF_DISC_IN_PROG
- AF_DISC_PENDING
- AF_DISC_POLLED
- AF_ECONET
- AF_EEH_BUSY
- AF_EN
- AF_EXECUTE
- AF_EXTRA_DATA
- AF_FIRST_INIT
- AF_FLASHING
- AF_FLASH_LOCK
- AF_FREQ_SET
- AF_FVMODE
- AF_FW_RECOVERY
- AF_GET_CRASH_RECORD
- AF_HA_REMOVAL
- AF_HEARTBEAT
- AF_HEARTBEAT_ENB
- AF_HZ_START_SHIFT
- AF_IB
- AF_IEEE802154
- AF_INET
- AF_INET6
- AF_INET_FAMILY
- AF_INIT_DONE
- AF_INTERRUPTS_ON
- AF_IPX
- AF_IRDA
- AF_IRQ_ATTACHED
- AF_ISDN
- AF_IUCV
- AF_IUCV_FLAG_ACK
- AF_IUCV_FLAG_FIN
- AF_IUCV_FLAG_SHT
- AF_IUCV_FLAG_SYN
- AF_IUCV_FLAG_WIN
- AF_IUCV_TRANS_HIPER
- AF_IUCV_TRANS_IUCV
- AF_KCM
- AF_KEY
- AF_LEGACY_SGE_MODE
- AF_LINE_INCR_SHIFT
- AF_LINK_UP
- AF_LLC
- AF_LOCAL
- AF_LOOPBACK
- AF_MAX
- AF_MBOX_COMMAND
- AF_MBOX_COMMAND_DONE
- AF_MBOX_COMMAND_NOPOLL
- AF_MED_EN
- AF_MED_TH
- AF_MED_TH_SHIFT
- AF_MODE
- AF_MPLS
- AF_NETBEUI
- AF_NETLINK
- AF_NETROM
- AF_NFC
- AF_NOT_PRESENT
- AF_NVR_VALID
- AF_ONLINE
- AF_OS_RESET
- AF_PACKET
- AF_PAXH
- AF_PAXHC
- AF_PAXSH
- AF_PAXSV
- AF_PAXVC
- AF_PAXW
- AF_PAXW_SHIFT
- AF_PCI_CHANNEL_IO_PERM_FAILURE
- AF_PCR_MASK
- AF_PEER_SEARCH_CNT
- AF_PHONET
- AF_PHONET_H
- AF_PORT_CHANGE
- AF_POWER_DOWN
- AF_POWER_MGT
- AF_PPPOX
- AF_QIPCRTR
- AF_RDS
- AF_RGBPOS
- AF_RGBPOS_SHIFT
- AF_ROSE
- AF_ROUTE
- AF_RXRPC
- AF_SECURITY
- AF_SMC
- AF_SNA
- AF_STATUS
- AF_ST_DISCOVERY_IN_PROGRESS
- AF_TASKLET_SCHEDULED
- AF_TIPC
- AF_UNIX
- AF_UNSPEC
- AF_VERSION
- AF_VSOCK
- AF_VSOCK_OP_CONNECT
- AF_VSOCK_OP_CONTROL
- AF_VSOCK_OP_DISCONNECT
- AF_VSOCK_OP_PAYLOAD
- AF_VSOCK_OP_UNKNOWN
- AF_VSOCK_TRANSPORT_NO_INFO
- AF_VSOCK_TRANSPORT_UNKNOWN
- AF_VSOCK_TRANSPORT_VIRTIO
- AF_VT_COUNT_SHIFT
- AF_WANPIPE
- AF_X25
- AF_XDP
- AG71XX_DEFAULT_MSG_ENABLE
- AG71XX_DESC_SIZE
- AG71XX_DMA_DELAY
- AG71XX_DMA_RETRY
- AG71XX_INT_ERR
- AG71XX_INT_INIT
- AG71XX_INT_POLL
- AG71XX_INT_RX
- AG71XX_INT_RX_BE
- AG71XX_INT_RX_OF
- AG71XX_INT_RX_PR
- AG71XX_INT_TX
- AG71XX_INT_TX_BE
- AG71XX_INT_TX_PS
- AG71XX_INT_TX_UR
- AG71XX_MDIO_DELAY
- AG71XX_MDIO_MAX_CLK
- AG71XX_MDIO_RETRY
- AG71XX_NAPI_WEIGHT
- AG71XX_OOM_REFILL
- AG71XX_REG_FIFO_CFG0
- AG71XX_REG_FIFO_CFG1
- AG71XX_REG_FIFO_CFG2
- AG71XX_REG_FIFO_CFG3
- AG71XX_REG_FIFO_CFG4
- AG71XX_REG_FIFO_CFG5
- AG71XX_REG_FIFO_DEPTH
- AG71XX_REG_INT_ENABLE
- AG71XX_REG_INT_STATUS
- AG71XX_REG_MAC_ADDR1
- AG71XX_REG_MAC_ADDR2
- AG71XX_REG_MAC_CFG1
- AG71XX_REG_MAC_CFG2
- AG71XX_REG_MAC_IFCTL
- AG71XX_REG_MAC_MFL
- AG71XX_REG_MII_ADDR
- AG71XX_REG_MII_CFG
- AG71XX_REG_MII_CMD
- AG71XX_REG_MII_CTRL
- AG71XX_REG_MII_IND
- AG71XX_REG_MII_STATUS
- AG71XX_REG_RX_CTRL
- AG71XX_REG_RX_DESC
- AG71XX_REG_RX_SM
- AG71XX_REG_RX_STATUS
- AG71XX_REG_TX_CTRL
- AG71XX_REG_TX_DESC
- AG71XX_REG_TX_SM
- AG71XX_REG_TX_STATUS
- AG71XX_RX_RING_SIZE_DEFAULT
- AG71XX_TX_MTU_LEN
- AG71XX_TX_RING_DS_PER_PKT
- AG71XX_TX_RING_SIZE_DEFAULT
- AG71XX_TX_RING_SPLIT
- AGC1ADJ
- AGC1AMM
- AGC1CFG
- AGC1CN
- AGC1OK
- AGC1QUAD
- AGC1REF
- AGC2I0
- AGC2I1
- AGC2O
- AGC2OK
- AGC2REF
- AGCGAIN
- AGCIQIN0
- AGCIQIN1
- AGCIQ_VALUE0
- AGCIQ_VALUE1
- AGCLAST
- AGCLOCKED
- AGCNEG
- AGCRDL_T
- AGCRDU_T
- AGCREAD_S
- AGCSET2_T
- AGCSET2_T_IFPOLINV_INC
- AGCSET2_T_RFPOLINV_INC
- AGCSTS_A2P_TCOUNT
- AGCSTS_BIST_MASK
- AGCSTS_CONTROL_MASK
- AGCSTS_FIFO_ST_MASK
- AGCSTS_FS_A2P_EMPTY
- AGCSTS_FS_A2P_FULL
- AGCSTS_FS_A2P_HALF
- AGCSTS_FS_P2A_EMPTY
- AGCSTS_FS_P2A_FULL
- AGCSTS_FS_P2A_HALF
- AGCSTS_NV_ACC_MASK
- AGCSTS_NV_DA_MASK
- AGCSTS_P2A_TCOUNT
- AGCSTS_RESET_A2P_FIFO
- AGCSTS_RESET_FIFOS
- AGCSTS_RESET_MASK
- AGCSTS_RESET_MBFLAGS
- AGCSTS_RESET_P2A_FIFO
- AGCSTS_STATUS_MASK
- AGCSTS_TCZERO_MASK
- AGCSTS_TC_ENABLE
- AGCTAB_1T
- AGCTAB_1TARRAYLENGTH
- AGCTAB_2G_ARRAYLENGTH
- AGCTAB_2T
- AGCTAB_2TARRAYLENGTH
- AGCTAB_5G_ARRAYLENGTH
- AGCTAB_ARRAYLENGTH
- AGCTAB_ArrayLength
- AGCTAB_ArrayLengthPciE
- AGCV3_T
- AGC_260K_SEL_CH1_CTL_MASK
- AGC_260K_SEL_CH1_CTL_MASK_SFT
- AGC_260K_SEL_CH1_CTL_SFT
- AGC_260K_SEL_CH2_CTL_MASK
- AGC_260K_SEL_CH2_CTL_MASK_SFT
- AGC_260K_SEL_CH2_CTL_SFT
- AGC_CTL
- AGC_CTRL
- AGC_CTRL_AUTO
- AGC_CTRL_MODE
- AGC_CTRL_OFF
- AGC_CTRL_USER
- AGC_DELAY0
- AGC_DELAY1
- AGC_DELAY2
- AGC_DIFF_CONFIG
- AGC_DIFF_CONFIG_MP
- AGC_DIFF_CONFIG_TC
- AGC_EN_RSSI
- AGC_FUNC_CTRL1
- AGC_FUNC_CTRL2
- AGC_FUNC_CTRL3
- AGC_GAIN_0
- AGC_GAIN_1
- AGC_GAIN_2
- AGC_GAIN_3
- AGC_H
- AGC_IF
- AGC_INIT
- AGC_INIT_BASE
- AGC_INIT_MSG_MAGIC
- AGC_INIT_MSG_VALUE
- AGC_L
- AGC_LEVEL_CONFIG
- AGC_LK_TH
- AGC_LM_CONFIG
- AGC_LM_CONFIG_BCL_DISABLED
- AGC_LM_CONFIG_ENABLE_ERROR
- AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE
- AGC_LM_CONFIG_GPU_VERSION_SHIFT
- AGC_LM_CONFIG_ISENSE_ENABLE
- AGC_LM_CONFIG_LLM_ENABLED
- AGC_LM_CONFIG_THROTTLE_DISABLE
- AGC_LOOP_BANDWIDTH0
- AGC_LOOP_BANDWIDTH1
- AGC_M
- AGC_MAX
- AGC_MIN
- AGC_MODE_FORMATTER
- AGC_MSG_BASE
- AGC_MSG_COMMAND
- AGC_MSG_PAYLOAD
- AGC_MSG_PAYLOAD_SIZE
- AGC_MSG_STATE
- AGC_ON
- AGC_POWER_CONFIG_PRODUCTION_ID
- AGC_PWR_SET
- AGC_REF
- AGC_RF
- AGC_RFIF_ACC0
- AGC_RFIF_ACC1
- AGC_RFIF_ACC2
- AGC_RF_BANDWIDTH0
- AGC_RF_BANDWIDTH1
- AGC_RF_BANDWIDTH2
- AGC_SECONDS
- AGC_STATUS
- AGC_TARGET
- AGC_table_select
- AGDSP_SLEEP
- AGDSP_SLEEP_MODE
- AGENP
- AGENT_MASK
- AGENT_OFFLINE_ERR_MASK
- AGENT_STATE_ACTIVE
- AGENT_STATE_DEAD
- AGENT_STATE_RESET
- AGENT_STATE_SUSPENDED
- AGE_BUFFER
- AGE_NAME
- AGE_PORT_MASK
- AGE_TIMER
- AGE_TIMER_MASK
- AGE_VID_MASK
- AGGLEN_LMT_H
- AGGLEN_LMT_L
- AGGRE0_NOC_GDSC
- AGGREGATE_I
- AGGREGATION_SIZE
- AGGRESSIVE_CHECK__
- AGGRESSIVE_TEST_
- AGGRE_SIZE
- AGGRE_SIZE_E
- AGGR_BUF_FIRST
- AGGR_BUF_LAST
- AGGR_BUF_MIDDLE
- AGGR_BUF_NONE
- AGGR_CORE
- AGGR_DCRM_IDX
- AGGR_DIE
- AGGR_GLOBAL
- AGGR_INCR_IDX
- AGGR_INODE_TABLE_START
- AGGR_NONE
- AGGR_NR_HIGH_BOUND
- AGGR_NR_LOW_BOUND
- AGGR_NUM_OF_FREE_NETBUFS
- AGGR_OPERATIONAL
- AGGR_PROGRESS
- AGGR_RESERVED_I
- AGGR_RSVD_BLOCKS
- AGGR_RSVD_BYTES
- AGGR_RX_TIMEOUT
- AGGR_SOCKET
- AGGR_START
- AGGR_STATS_RX_SIZE_LEN
- AGGR_STATS_TX_AGG
- AGGR_STOP
- AGGR_SZ_DEFAULT
- AGGR_THREAD
- AGGR_TRFC_LD
- AGGR_UNSET
- AGGR_WIN_IDX
- AGGR_WIN_SZ_MAX
- AGGR_WIN_SZ_MIN
- AGG_BK
- AGG_EN
- AGG_TX_STATE_
- AGG_TX_STATE_ABORT
- AGG_TX_STATE_ABORT_MSK
- AGG_TX_STATE_BT_PRIO
- AGG_TX_STATE_BT_PRIO_MSK
- AGG_TX_STATE_DELAY_TX
- AGG_TX_STATE_DELAY_TX_MSK
- AGG_TX_STATE_DUMP_TX
- AGG_TX_STATE_DUMP_TX_MSK
- AGG_TX_STATE_FAIL
- AGG_TX_STATE_FEW_BYTES
- AGG_TX_STATE_FEW_BYTES_MSK
- AGG_TX_STATE_LAST_SENT_BT_KILL
- AGG_TX_STATE_LAST_SENT_BT_KILL_MSK
- AGG_TX_STATE_LAST_SENT_MSK
- AGG_TX_STATE_LAST_SENT_TRY_CNT
- AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK
- AGG_TX_STATE_LAST_SENT_TTL_MSK
- AGG_TX_STATE_RESPONSE
- AGG_TX_STATE_RESPONSE_MSK
- AGG_TX_STATE_SCD_QUERY
- AGG_TX_STATE_SCD_QUERY_MSK
- AGG_TX_STATE_SEQ_NUM_MSK
- AGG_TX_STATE_SEQ_NUM_POS
- AGG_TX_STATE_STATUS_MSK
- AGG_TX_STATE_TEST_BAD_CRC32
- AGG_TX_STATE_TEST_BAD_CRC32_MSK
- AGG_TX_STATE_TRANSMITTED
- AGG_TX_STATE_TRY_CNT_MSK
- AGG_TX_STATE_TRY_CNT_POS
- AGG_TX_STATE_TX_ON_AIR_DROP
- AGG_TX_STATE_UNDERRUN
- AGG_TX_STATE_UNDERRUN_MSK
- AGG_TX_STATUS_MSK
- AGG_TX_STAT_FRAME_NOT_SENT
- AGG_TX_TRY_MSK
- AGG_TX_TRY_POS
- AGL_GMX_PRT_CFG
- AGL_GMX_RX_ADR_CAM0
- AGL_GMX_RX_ADR_CAM1
- AGL_GMX_RX_ADR_CAM2
- AGL_GMX_RX_ADR_CAM3
- AGL_GMX_RX_ADR_CAM4
- AGL_GMX_RX_ADR_CAM5
- AGL_GMX_RX_ADR_CAM_EN
- AGL_GMX_RX_ADR_CTL
- AGL_GMX_RX_FRM_CTL
- AGL_GMX_RX_FRM_MAX
- AGL_GMX_RX_JABBER
- AGL_GMX_RX_STATS_CTL
- AGL_GMX_RX_STATS_OCTS_DRP
- AGL_GMX_RX_STATS_PKTS_BAD
- AGL_GMX_RX_STATS_PKTS_DRP
- AGL_GMX_TX_CLK
- AGL_GMX_TX_CTL
- AGL_GMX_TX_STAT0
- AGL_GMX_TX_STAT1
- AGL_GMX_TX_STAT2
- AGL_GMX_TX_STAT3
- AGL_GMX_TX_STAT4
- AGL_GMX_TX_STAT5
- AGL_GMX_TX_STAT6
- AGL_GMX_TX_STAT7
- AGL_GMX_TX_STAT8
- AGL_GMX_TX_STAT9
- AGL_GMX_TX_STATS_CTL
- AGND
- AGP1_CNTL
- AGP2_CNTL
- AGP2_RESERVED_MASK
- AGP3_RESERVED_MASK
- AGP8X_MODE
- AGP8X_MODE_BIT
- AGPAPSIZE
- AGPCMD
- AGPCTRL
- AGPCTRL_APERENB
- AGPCTRL_GTLBEN
- AGPEXTERN
- AGPGARTHI
- AGPGARTLO
- AGPGART_MINOR
- AGPGART_VERSION_MAJOR
- AGPGART_VERSION_MINOR
- AGPINIT
- AGPIOC_ACQUIRE
- AGPIOC_ACQUIRE32
- AGPIOC_ALLOCATE
- AGPIOC_ALLOCATE32
- AGPIOC_BASE
- AGPIOC_BIND
- AGPIOC_BIND32
- AGPIOC_CHIPSET_FLUSH
- AGPIOC_CHIPSET_FLUSH32
- AGPIOC_DEALLOCATE
- AGPIOC_DEALLOCATE32
- AGPIOC_INFO
- AGPIOC_INFO32
- AGPIOC_PROTECT
- AGPIOC_PROTECT32
- AGPIOC_RELEASE
- AGPIOC_RELEASE32
- AGPIOC_RESERVE
- AGPIOC_RESERVE32
- AGPIOC_SETUP
- AGPIOC_SETUP32
- AGPIOC_UNBIND
- AGPIOC_UNBIND32
- AGPNEPG
- AGPNICMD
- AGPNISTAT
- AGPSTAT
- AGPSTAT2_1X
- AGPSTAT2_2X
- AGPSTAT2_4X
- AGPSTAT3_4X
- AGPSTAT3_8X
- AGPSTAT3_RSVD
- AGPSTAT_AGP_ENABLE
- AGPSTAT_ARQSZ
- AGPSTAT_ARQSZ_SHIFT
- AGPSTAT_CAL_MASK
- AGPSTAT_FW
- AGPSTAT_MODE_3_0
- AGPSTAT_RQ_DEPTH
- AGPSTAT_RQ_DEPTH_SHIFT
- AGPSTAT_SBA
- AGP_1X
- AGP_2X
- AGP_4X
- AGP_8X
- AGP_APBASE
- AGP_APERTURE_BAR
- AGP_APER_OFFSET
- AGP_BASE
- AGP_BURST_LENGTH
- AGP_CAP_ID
- AGP_CMD_QUEUE
- AGP_CMD_QUEUE_CAP
- AGP_CNTL
- AGP_CNTL__AGP_MISC_MASK
- AGP_CNTL__AGP_MISC__SHIFT
- AGP_CNTL__AGP_REV_ID
- AGP_CNTL__AGP_REV_ID_MASK
- AGP_CNTL__AGP_REV_ID__SHIFT
- AGP_CNTL__DELAY_FIRST_SBA_EN
- AGP_CNTL__DELAY_FIRST_SBA_EN_MASK
- AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT
- AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK
- AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT
- AGP_CNTL__DIS_QUEUED_GNT_FIX
- AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK
- AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT
- AGP_CNTL__DIS_RBF
- AGP_CNTL__DIS_RBF_MASK
- AGP_CNTL__DIS_RBF__SHIFT
- AGP_CNTL__EN_2X_STBB
- AGP_CNTL__EN_2X_STBB_MASK
- AGP_CNTL__EN_2X_STBB__SHIFT
- AGP_CNTL__EN_EXTENDED_AD_STB_2X
- AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK
- AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT
- AGP_CNTL__EN_RBFCALM
- AGP_CNTL__EN_RBFCALM_MASK
- AGP_CNTL__EN_RBFCALM__SHIFT
- AGP_CNTL__EN_RDATA2X4X_MULTIRESET
- AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK
- AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT
- AGP_CNTL__FORCE_EXT_VREF
- AGP_CNTL__FORCE_EXT_VREF_MASK
- AGP_CNTL__FORCE_EXT_VREF__SHIFT
- AGP_CNTL__FORCE_FULL_SBA
- AGP_CNTL__FORCE_FULL_SBA_MASK
- AGP_CNTL__FORCE_FULL_SBA__SHIFT
- AGP_CNTL__FORCE_INT_VREF
- AGP_CNTL__FORCE_INT_VREF_MASK
- AGP_CNTL__FORCE_INT_VREF__SHIFT
- AGP_CNTL__HOLD_RD_FIFO
- AGP_CNTL__HOLD_RD_FIFO_MASK
- AGP_CNTL__HOLD_RD_FIFO__SHIFT
- AGP_CNTL__HOLD_RQ_FIFO
- AGP_CNTL__HOLD_RQ_FIFO_MASK
- AGP_CNTL__HOLD_RQ_FIFO__SHIFT
- AGP_CNTL__MAX_IDLE_CLK_MASK
- AGP_CNTL__MAX_IDLE_CLK__SHIFT
- AGP_CNTL__PENDING_SLOTS_SEL
- AGP_CNTL__PENDING_SLOTS_SEL_MASK
- AGP_CNTL__PENDING_SLOTS_SEL__SHIFT
- AGP_CNTL__PENDING_SLOTS_VAL_MASK
- AGP_CNTL__PENDING_SLOTS_VAL__SHIFT
- AGP_CNTL__REG_CRIPPLE_AGP2X4X
- AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK
- AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT
- AGP_CNTL__REG_CRIPPLE_AGP4X
- AGP_CNTL__REG_CRIPPLE_AGP4X_MASK
- AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT
- AGP_CNTL__SBA_DIS
- AGP_CNTL__SBA_DIS_MASK
- AGP_CNTL__SBA_DIS__SHIFT
- AGP_COMMAND
- AGP_DCACHE_MEMORY
- AGP_DEVICE
- AGP_ERRATA_1X
- AGP_ERRATA_FASTWRITES
- AGP_ERRATA_SBA
- AGP_FF_ALLOW_CLIENT
- AGP_FF_ALLOW_CONTROLLER
- AGP_FF_IS_CLIENT
- AGP_FF_IS_CONTROLLER
- AGP_FF_IS_VALID
- AGP_FIFO_WATERMARK
- AGP_GENERIC_SIZES_ENTRIES
- AGP_H
- AGP_MAJOR_VERSION_SHIFT
- AGP_MINOR_VERSION_SHIFT
- AGP_NORMAL_MEMORY
- AGP_PAGE_DESTROY_FREE
- AGP_PAGE_DESTROY_UNMAP
- AGP_PHYSICAL_MEMORY
- AGP_PHYS_MEMORY
- AGP_PLL_CNTL
- AGP_STATUS
- AGP_TYPE
- AGP_UNKNOWN
- AGP_USER_CACHED_MEMORY
- AGP_USER_CACHED_MEMORY_GFDT
- AGP_USER_MEMORY
- AGP_USER_TYPES
- AGTOBLK
- AG_ABRTH_REG
- AG_CNT_START
- AG_ISA_IO_B
- AG_ISA_IO_W
- AG_LOCK
- AG_LOCK_INIT
- AG_SAT_TH_REG
- AG_UNLOCK
- AH
- AHA152X_MAXQUEUE
- AHA152X_PCMCIA
- AHA152X_REVID
- AHA152X_STAT
- AHA1542_MAILBOXES
- AHA1542_REGION_SIZE
- AHA1740CMD_DIAG
- AHA1740CMD_DOWN
- AHA1740CMD_INIT
- AHA1740CMD_NOP
- AHA1740CMD_RINQ
- AHA1740CMD_SCSI
- AHA1740CMD_SENSE
- AHA1740CMD_TARG
- AHA1740_ECBS
- AHA1740_SCATTER
- AHASH_INIT_SIZE
- AHASH_MAX
- AHASH_MAX_SIZE
- AHASH_MAX_TUNED
- AHASH_REQUEST_ON_STACK
- AHB0_INT_IDX
- AHB1
- AHB2
- AHB2PCIE_SIZE
- AHB2STBUS_INSREG01
- AHBBRST_MASK
- AHBB_VER
- AHBDMA_MST_ID
- AHBIX_CLK
- AHBSPEED_MASK
- AHBSPEED_SHIFT
- AHB_ADDR_LSB
- AHB_AMODE_20MHZ
- AHB_AMODE_40MHZ
- AHB_AMODE_80MHZ
- AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID
- AHB_ARBITRATION_DISABLE
- AHB_ARBITRATION_PRIORITY_CTRL
- AHB_ARBITRATION_XBAR_CTRL
- AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE
- AHB_AXI_BUS_HALT_ACK
- AHB_AXI_BUS_HALT_REQ
- AHB_BASE
- AHB_BUS_NORMAL_PIO_OPRTN
- AHB_CAT
- AHB_CLK_SRC
- AHB_CLRLVL0INT
- AHB_CRW
- AHB_CRW_ENABLE
- AHB_CRW_NSE
- AHB_CRW_ROE
- AHB_CRW_SZMASK
- AHB_CRW_WTYPE_MEM
- AHB_DATA_LSB
- AHB_DMAEN
- AHB_DMARLD
- AHB_DMA_BRST_DFLT
- AHB_ERR
- AHB_ERR_M
- AHB_GIZMO_AHB_MEM
- AHB_GIZMO_AHB_XBAR_BRIDGE
- AHB_GIZMO_APB_DMA
- AHB_GIZMO_BSEA
- AHB_GIZMO_BSEV
- AHB_GIZMO_COP_AHB_BRIDGE
- AHB_GIZMO_CPU_AHB_BRIDGE
- AHB_GIZMO_IDE
- AHB_GIZMO_NAND
- AHB_GIZMO_NOR
- AHB_GIZMO_SDMMC1
- AHB_GIZMO_SDMMC2
- AHB_GIZMO_SDMMC3
- AHB_GIZMO_SDMMC4
- AHB_GIZMO_USB
- AHB_GIZMO_USB2
- AHB_GIZMO_USB3
- AHB_GIZMO_VCP_AHB_BRIDGE
- AHB_GIZMO_XBAR_APB_CTLR
- AHB_GIZMO_XIO
- AHB_GMODE_22MHZ
- AHB_GMODE_44MHZ
- AHB_GMODE_88MHZ
- AHB_IDLE_EN_EXT_MASK
- AHB_IDLE_EN_EXT_MASK_SFT
- AHB_IDLE_EN_EXT_SFT
- AHB_IDLE_EN_INT_MASK
- AHB_IDLE_EN_INT_MASK_SFT
- AHB_IDLE_EN_INT_SFT
- AHB_INTENLVL0
- AHB_INTMASK
- AHB_LVL0INT
- AHB_LVLINTMASK
- AHB_MAPB
- AHB_MASTER_CFG
- AHB_MEM_PREFETCH_CFG1
- AHB_MEM_PREFETCH_CFG2
- AHB_MEM_PREFETCH_CFG3
- AHB_MEM_PREFETCH_CFG4
- AHB_MEM_PREFETCH_CFG_X
- AHB_MSB_ADDR_PTR
- AHB_PEXHBASE
- AHB_PEXLBASE
- AHB_PRIORITY_WEIGHT
- AHB_SEC_SLV_CLK_CGC_ON
- AHB_STATIC_40MHZ
- AHB_TRANS_RDY
- AHB_TRANS_TRIES
- AHB_VBUS_INT
- AHB_WR
- AHCI_BISTAFR
- AHCI_BISTCR
- AHCI_BISTDECR
- AHCI_BISTFCTR
- AHCI_BISTSR
- AHCI_CMD_ATAPI
- AHCI_CMD_CLR_BUSY
- AHCI_CMD_PREFETCH
- AHCI_CMD_RESET
- AHCI_CMD_SLOT_SZ
- AHCI_CMD_SZ
- AHCI_CMD_TBL_AR_SZ
- AHCI_CMD_TBL_CDB
- AHCI_CMD_TBL_HDR_OFFSET
- AHCI_CMD_TBL_HDR_SZ
- AHCI_CMD_TBL_OFFSET
- AHCI_CMD_TBL_SGL_OFFSET
- AHCI_CMD_TBL_SGL_SZ
- AHCI_CMD_TBL_SZ
- AHCI_CMD_WRITE
- AHCI_DIAGNR0
- AHCI_DIAGNR1
- AHCI_DM816_DRV_NAME
- AHCI_DM816_P0PHYCR_REG
- AHCI_DM816_P1PHYCR_REG
- AHCI_DM816_PHY_ENPLL
- AHCI_DM816_PHY_LOS
- AHCI_DM816_PHY_MPY
- AHCI_DM816_PHY_RXCDR
- AHCI_DM816_PHY_RXEQ
- AHCI_DM816_PHY_TXSWING
- AHCI_DM816_PLL_OUT
- AHCI_DMA_BOUNDARY
- AHCI_ENABLE
- AHCI_FLAG_COMMON
- AHCI_GLOBAL_CTL
- AHCI_GPARAM1R
- AHCI_GPARAM2R
- AHCI_HFLAGS
- AHCI_HFLAG_32BIT_ONLY
- AHCI_HFLAG_DELAY_ENGINE
- AHCI_HFLAG_IGN_IRQ_IF_ERR
- AHCI_HFLAG_IGN_SERR_INTERNAL
- AHCI_HFLAG_IS_MOBILE
- AHCI_HFLAG_MULTI_MSI
- AHCI_HFLAG_MV_PATA
- AHCI_HFLAG_NO_DEVSLP
- AHCI_HFLAG_NO_FBS
- AHCI_HFLAG_NO_FPDMA_AA
- AHCI_HFLAG_NO_MSI
- AHCI_HFLAG_NO_PMP
- AHCI_HFLAG_NO_SNTF
- AHCI_HFLAG_NO_SUSPEND
- AHCI_HFLAG_NO_WRITE_TO_RO
- AHCI_HFLAG_SECT255
- AHCI_HFLAG_SRST_TOUT_IS_OFFLINE
- AHCI_HFLAG_SUSPEND_PHYS
- AHCI_HFLAG_WAKE_BEFORE_STOP
- AHCI_HFLAG_YES_ALPM
- AHCI_HFLAG_YES_FBS
- AHCI_HFLAG_YES_NCQ
- AHCI_IDFY_OFFSET
- AHCI_IDFY_SZ
- AHCI_IDR
- AHCI_IMX53
- AHCI_IMX6Q
- AHCI_IMX6QP
- AHCI_IMX8QM
- AHCI_IRQ_ON_SG
- AHCI_LS1021A
- AHCI_LS1028A
- AHCI_LS1043A
- AHCI_LS1046A
- AHCI_LS1088A
- AHCI_LS2080A
- AHCI_LS2088A
- AHCI_LX2160A
- AHCI_MAX_CLKS
- AHCI_MAX_CMDS
- AHCI_MAX_PORTS
- AHCI_MAX_REMAP
- AHCI_MAX_SG
- AHCI_OOBR
- AHCI_P0DMACR
- AHCI_P0PHYCR
- AHCI_P0PHYSR
- AHCI_PCI_BAR
- AHCI_PCI_BAR_CAVIUM
- AHCI_PCI_BAR_CAVIUM_GEN5
- AHCI_PCI_BAR_ENMOTUS
- AHCI_PCI_BAR_STA2X11
- AHCI_PCI_BAR_STANDARD
- AHCI_PHYCS0R
- AHCI_PHYCS1R
- AHCI_PHYCS2R
- AHCI_PLATFORM_GET_RESETS
- AHCI_PORT_AXICC_CFG
- AHCI_PORT_PHY2_CFG
- AHCI_PORT_PHY3_CFG
- AHCI_PORT_PHY_1_CFG
- AHCI_PORT_PRIV_DMA_SZ
- AHCI_PORT_PRIV_FBS_DMA_SZ
- AHCI_PORT_TRANS_CFG
- AHCI_PPARAMR
- AHCI_REMAP_CAP
- AHCI_REMAP_N_DCC
- AHCI_REMAP_N_OFFSET
- AHCI_REMAP_N_SIZE
- AHCI_RWCR
- AHCI_RX_FIS_OFFSET
- AHCI_RX_FIS_SZ
- AHCI_SECTBUF_OFFSET
- AHCI_SECTBUF_SZ
- AHCI_SHT
- AHCI_SMARTBUF_OFFSET
- AHCI_SMARTBUF_SZ
- AHCI_TESTR
- AHCI_TIMER1MS
- AHCI_VENDOR_SPECIFIC_0_ADDR
- AHCI_VENDOR_SPECIFIC_0_DATA
- AHCI_VEND_AXICC
- AHCI_VEND_PAXIC
- AHCI_VEND_PCFG
- AHCI_VEND_PP2C
- AHCI_VEND_PP3C
- AHCI_VEND_PP4C
- AHCI_VEND_PP5C
- AHCI_VEND_PPCFG
- AHCI_VEND_PTC
- AHCI_VERSIONR
- AHCI_VSCAP
- AHCI_WINDOW_BASE
- AHCI_WINDOW_CTRL
- AHCI_WINDOW_SIZE
- AHCLKRDIV
- AHCLKRDIV_MASK
- AHCLKRE
- AHCLKRPOL
- AHCLKXDIV
- AHCLKXDIV_MASK
- AHCLKXE
- AHCLKXPOL
- AHCMSG_1B
- AHCMSG_2B
- AHCMSG_EXT
- AHC_394X_SLOT_CHANNEL_A
- AHC_394X_SLOT_CHANNEL_B
- AHC_398X_SLOT_CHANNEL_A
- AHC_398X_SLOT_CHANNEL_B
- AHC_398X_SLOT_CHANNEL_C
- AHC_39BIT_ADDRESSING
- AHC_494X_SLOT_CHANNEL_A
- AHC_494X_SLOT_CHANNEL_B
- AHC_494X_SLOT_CHANNEL_C
- AHC_494X_SLOT_CHANNEL_D
- AHC_AIC7770
- AHC_AIC7770_FE
- AHC_AIC7850
- AHC_AIC7850_FE
- AHC_AIC7855
- AHC_AIC7859
- AHC_AIC7860
- AHC_AIC7860_FE
- AHC_AIC7870
- AHC_AIC7870_FE
- AHC_AIC7880
- AHC_AIC7880_FE
- AHC_AIC7890
- AHC_AIC7890_FE
- AHC_AIC7892
- AHC_AIC7892_FE
- AHC_AIC7895
- AHC_AIC7895C
- AHC_AIC7895C_FE
- AHC_AIC7895_FE
- AHC_AIC7896
- AHC_AIC7896_FE
- AHC_AIC7899
- AHC_AIC7899_FE
- AHC_ALL_INTERRUPTS
- AHC_ASYNC_XFER_PERIOD
- AHC_AUTOFLUSH_BUG
- AHC_AUTOPAUSE
- AHC_AUTORATE
- AHC_BIOS_ENABLED
- AHC_BUGNONE
- AHC_BUSRESET_DELAY
- AHC_BUS_MASK
- AHC_CACHETHEN_BUG
- AHC_CACHETHEN_DIS_BUG
- AHC_CHIPID_MASK
- AHC_CMD_CHAN
- AHC_DEBUG
- AHC_DEBUG_OPTS
- AHC_DEBUG_SEQUENCER
- AHC_DEV_FREEZE_TIL_EMPTY
- AHC_DEV_PERIODIC_OTAG
- AHC_DEV_Q_BASIC
- AHC_DEV_Q_TAGGED
- AHC_DISABLE_PCI_PERR
- AHC_DMA_LAST_SEG
- AHC_DT
- AHC_DUMP_SEEPROM
- AHC_EDGE_INTERRUPT
- AHC_EISA
- AHC_EISA_IOSIZE
- AHC_EISA_SLOT_OFFSET
- AHC_EXTENDED_TRANS_A
- AHC_EXTENDED_TRANS_B
- AHC_FENONE
- AHC_FNONE
- AHC_HAS_TERM_LOGIC
- AHC_HS_MAILBOX
- AHC_HVD
- AHC_INITIATORROLE
- AHC_INT50_SPEEDFLEX
- AHC_LARGE_SCBS
- AHC_LARGE_SEEPROM
- AHC_LINUX_NOIRQ
- AHC_LOCK_TAGS_COUNT
- AHC_LSCBS_ENABLED
- AHC_MAXTRANSFER_SIZE
- AHC_MAX_QUEUE
- AHC_MAX_STEPS
- AHC_MORE_SRAM
- AHC_MULTIROLE
- AHC_MULTI_FUNC
- AHC_MULTI_TID
- AHC_NEG_ALWAYS
- AHC_NEG_IF_NON_ASYNC
- AHC_NEG_TO_GOAL
- AHC_NEWEEPROM_FMT
- AHC_NEW_TERMCTL
- AHC_NONE
- AHC_NO_BIOS_INIT
- AHC_NSEG
- AHC_NUM_LUNS
- AHC_NUM_TARGETS
- AHC_OFFSET_UNKNOWN
- AHC_OTAG_THRESH
- AHC_PAGESCBS
- AHC_PCI
- AHC_PCI_2_1_RETRY_BUG
- AHC_PCI_CONFIG
- AHC_PCI_IOADDR
- AHC_PCI_MEMADDR
- AHC_PCI_MWI_BUG
- AHC_PCI_TARGET_PERR_THRESH
- AHC_PERIOD_UNKNOWN
- AHC_POWER_STATE_D0
- AHC_POWER_STATE_D1
- AHC_POWER_STATE_D2
- AHC_POWER_STATE_D3
- AHC_PPR_OPTS_UNKNOWN
- AHC_PRIMARY_CHANNEL
- AHC_QUEUE_BASIC
- AHC_QUEUE_NONE
- AHC_QUEUE_REGS
- AHC_QUEUE_TAGGED
- AHC_REMOVABLE
- AHC_RESET_BUS_A
- AHC_RESET_BUS_B
- AHC_RUN_QOUTFIFO
- AHC_RUN_TQINFIFO
- AHC_SCBCHAN_UPLOAD_BUG
- AHC_SCB_BTT
- AHC_SCB_CONFIG_USED
- AHC_SCB_MAX
- AHC_SCB_MAX_ALLOC
- AHC_SEQUENCER_DEBUG
- AHC_SG_HIGH_ADDR_MASK
- AHC_SG_LEN_MASK
- AHC_SG_PRELOAD
- AHC_SHARED_SRAM
- AHC_SHOW_DV
- AHC_SHOW_MASKED_ERRORS
- AHC_SHOW_MEMORY
- AHC_SHOW_MESSAGES
- AHC_SHOW_MISC
- AHC_SHOW_QFULL
- AHC_SHOW_QUEUE
- AHC_SHOW_SELTO
- AHC_SHOW_SENSE
- AHC_SHOW_TERMCTL
- AHC_SHOW_TQIN
- AHC_SPIOCAP
- AHC_SYNCRATE_DT
- AHC_SYNCRATE_FAST
- AHC_SYNCRATE_MAX
- AHC_SYNCRATE_MIN
- AHC_SYNCRATE_ULTRA
- AHC_SYNCRATE_ULTRA2
- AHC_TAG_SUCCESS_INTERVAL
- AHC_TARGETMODE
- AHC_TARGETROLE
- AHC_TERM_ENB_A
- AHC_TERM_ENB_B
- AHC_TMODE_CMDS
- AHC_TMODE_ENABLE
- AHC_TMODE_EVENT_BUFFER_SIZE
- AHC_TMODE_WIDEODD_BUG
- AHC_TQINFIFO_BLOCKED
- AHC_TRANS_ACTIVE
- AHC_TRANS_CUR
- AHC_TRANS_GOAL
- AHC_TRANS_USER
- AHC_TWIN
- AHC_ULTRA
- AHC_ULTRA2
- AHC_ULTRA2_XFER_PERIOD
- AHC_USEDEFAULTS
- AHC_VL
- AHC_WIDE
- AHC_WIDTH_UNKNOWN
- AHDMSG_1B
- AHDMSG_2B
- AHDMSG_EXT
- AHD_39BIT_ADDRESSING
- AHD_64BIT_ADDRESSING
- AHD_ABORT_LQI_BUG
- AHD_AIC7901
- AHD_AIC7901A
- AHD_AIC7901A_FE
- AHD_AIC7901_FE
- AHD_AIC7902
- AHD_AIC7902_FE
- AHD_AIC79XXB_SLOWCRC
- AHD_ALL_INTERRUPTS
- AHD_AMPLITUDE_INDEX
- AHD_ASSERT_MODES
- AHD_ASYNC_XFER_PERIOD
- AHD_AUTOFLUSH_BUG
- AHD_BIOS_ENABLED
- AHD_BOOT_CHANNEL
- AHD_BUGNONE
- AHD_BUILD_COL_IDX
- AHD_BUSFREEREV_BUG
- AHD_BUSRESET_DELAY
- AHD_BUS_MASK
- AHD_BUS_RESET_ACTIVE
- AHD_CHIPID_MASK
- AHD_CLRLQO_AUTOCLR_BUG
- AHD_COPY_COL_IDX
- AHD_COPY_SCB_COL_IDX
- AHD_CURRENT_SENSING
- AHD_DEBUG
- AHD_DEBUG_OPTS
- AHD_DEBUG_SEQUENCER
- AHD_DEV_FREEZE_TIL_EMPTY
- AHD_DEV_PERIODIC_OTAG
- AHD_DEV_Q_BASIC
- AHD_DEV_Q_TAGGED
- AHD_DMA_LAST_SEG
- AHD_DUMP_SEEPROM
- AHD_EARLY_REQ_BUG
- AHD_EISA_IOSIZE
- AHD_EISA_SLOT_OFFSET
- AHD_EXTENDED_TRANS_A
- AHD_FAINT_LED_BUG
- AHD_FAST_CDB_DELIVERY
- AHD_FENONE
- AHD_FNONE
- AHD_GET_SCB_COL_IDX
- AHD_HAD_FIRST_SEL
- AHD_HP_BOARD
- AHD_INITIATORROLE
- AHD_INT50_SPEEDFLEX
- AHD_INTCOLLISION_BUG
- AHD_INT_COALESCING_MAXCMDS_DEFAULT
- AHD_INT_COALESCING_MAXCMDS_MAX
- AHD_INT_COALESCING_MINCMDS_DEFAULT
- AHD_INT_COALESCING_MINCMDS_MAX
- AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT
- AHD_INT_COALESCING_THRESHOLD_DEFAULT
- AHD_INT_COALESCING_TIMER_DEFAULT
- AHD_LINUX_ERR_THRESH
- AHD_LINUX_NOIRQ
- AHD_LOCK_TAGS_COUNT
- AHD_LONG_SETIMO_BUG
- AHD_LQOOVERRUN_BUG
- AHD_LQO_ATNO_BUG
- AHD_MAXTRANSFER_SIZE
- AHD_MAX_LQ_CRC_ERRORS
- AHD_MAX_QUEUE
- AHD_MAX_STEPS
- AHD_MDFF_WSCBPTR_BUG
- AHD_MK_MSK
- AHD_MODE_ANY_MSK
- AHD_MODE_CCHAN
- AHD_MODE_CCHAN_MSK
- AHD_MODE_CFG
- AHD_MODE_CFG_MSK
- AHD_MODE_DFF0
- AHD_MODE_DFF0_MSK
- AHD_MODE_DFF1
- AHD_MODE_DFF1_MSK
- AHD_MODE_SCSI
- AHD_MODE_SCSI_MSK
- AHD_MODE_UNKNOWN
- AHD_MODE_UNKNOWN_MSK
- AHD_MULTIROLE
- AHD_MULTI_FUNC
- AHD_NEG_ALWAYS
- AHD_NEG_IF_NON_ASYNC
- AHD_NEG_TO_GOAL
- AHD_NEVER_COL_IDX
- AHD_NEW_DFCNTRL_OPTS
- AHD_NEW_IOCELL_OPTS
- AHD_NLQICRC_DELAYED_BUG
- AHD_NONE
- AHD_NONPACKFIFO_BUG
- AHD_NSEG
- AHD_NUM_LUNS
- AHD_NUM_LUNS_NONPKT
- AHD_NUM_TARGETS
- AHD_OFFSET_UNKNOWN
- AHD_OTAG_THRESH
- AHD_PACED_NEGTABLE_BUG
- AHD_PCI
- AHD_PCIX
- AHD_PCIX_BUG_MASK
- AHD_PCIX_CHIPRST_BUG
- AHD_PCIX_MMAPIO_BUG
- AHD_PCIX_SCBRAM_RD_BUG
- AHD_PCI_CONFIG
- AHD_PCI_IOADDR0
- AHD_PCI_IOADDR1
- AHD_PCI_MEMADDR
- AHD_PERIOD_10MHz
- AHD_PERIOD_UNKNOWN
- AHD_PKTIZED_STATUS_BUG
- AHD_PKT_BITBUCKET_BUG
- AHD_PKT_LUN_BUG
- AHD_POWER_STATE_D0
- AHD_POWER_STATE_D1
- AHD_POWER_STATE_D2
- AHD_POWER_STATE_D3
- AHD_PPR_OPTS_UNKNOWN
- AHD_PRECOMP_SLEW_INDEX
- AHD_QIN_SIZE
- AHD_QIN_WRAP
- AHD_QOUT_SIZE
- AHD_QUEUE_BASIC
- AHD_QUEUE_NONE
- AHD_QUEUE_TAGGED
- AHD_REG_SLOW_SETTLE_BUG
- AHD_REMOVABLE
- AHD_RESET_BUS_A
- AHD_RESOURCE_SHORTAGE
- AHD_RTI
- AHD_RUNNING_QOUTFIFO
- AHD_RUN_QOUTFIFO
- AHD_RUN_TQINFIFO
- AHD_SCB_CONFIG_USED
- AHD_SCB_MAX
- AHD_SCB_MAX_ALLOC
- AHD_SCSIRST_BUG
- AHD_SENT_SCB_UPDATE_BUG
- AHD_SEQUENCER_DEBUG
- AHD_SET_AMPLITUDE
- AHD_SET_MODE_BUG
- AHD_SET_PRECOMP
- AHD_SET_SCB_COL_IDX
- AHD_SET_SLEWRATE
- AHD_SG_HIGH_ADDR_MASK
- AHD_SG_LEN_MASK
- AHD_SHOW_DV
- AHD_SHOW_FIFOS
- AHD_SHOW_INT_COALESCING
- AHD_SHOW_MASKED_ERRORS
- AHD_SHOW_MEMORY
- AHD_SHOW_MESSAGES
- AHD_SHOW_MISC
- AHD_SHOW_MODEPTR
- AHD_SHOW_QFULL
- AHD_SHOW_QUEUE
- AHD_SHOW_RECOVERY
- AHD_SHOW_SELTO
- AHD_SHOW_SENSE
- AHD_SHOW_SG
- AHD_SHOW_TERMCTL
- AHD_SHOW_TQIN
- AHD_SPCHK_ENB_A
- AHD_STAT_BUCKETS
- AHD_STAT_UPDATE_US
- AHD_STPWLEVEL_A
- AHD_SYNCRATE_160
- AHD_SYNCRATE_ASYNC
- AHD_SYNCRATE_DT
- AHD_SYNCRATE_FAST
- AHD_SYNCRATE_MAX
- AHD_SYNCRATE_MIN
- AHD_SYNCRATE_MIN_DT
- AHD_SYNCRATE_PACED
- AHD_SYNCRATE_REVA_120
- AHD_SYNCRATE_REVA_160
- AHD_SYNCRATE_SYNC
- AHD_SYNCRATE_ULTRA
- AHD_SYNCRATE_ULTRA2
- AHD_TAG_SUCCESS_INTERVAL
- AHD_TARGETMODE
- AHD_TARGETROLE
- AHD_TERM_ENB_A
- AHD_TMODE_CMDS
- AHD_TMODE_ENABLE
- AHD_TMODE_EVENT_BUFFER_SIZE
- AHD_TQINFIFO_BLOCKED
- AHD_TRANS_ACTIVE
- AHD_TRANS_CUR
- AHD_TRANS_GOAL
- AHD_TRANS_USER
- AHD_UPDATE_PEND_CMDS
- AHD_USEDEFAULTS
- AHD_WIDE
- AHD_WIDTH_UNKNOWN
- AHEAD_TO_SYNC_SOURCE
- AHG_KDETH_ARRAY_SIZE
- AHG_KDETH_INTR_SHIFT
- AHG_KDETH_SH_SHIFT
- AHPOUTPOW
- AHPOUTPOW_HP_ON
- AHSV8888_1X32
- AHZ
- AH_ESP_V4_FLOW
- AH_ESP_V6_FLOW
- AH_FASTCC
- AH_NO_EEP_SWAP
- AH_PCIE_LINK_PARAMS
- AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK
- AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT
- AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK
- AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT
- AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK
- AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT
- AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK
- AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT
- AH_RX_STOP_DMA_TIMEOUT
- AH_SKB_CB
- AH_TIME_QUANTUM
- AH_TSF_WRITE_TIMEOUT
- AH_UNPLUGGED
- AH_USE_EEPROM
- AH_V4_FLOW
- AH_V6_FLOW
- AH_WAIT_TIMEOUT
- AH_WOW_BEACON_MISS
- AH_WOW_LINK_CHANGE
- AH_WOW_MAGIC_PATTERN_EN
- AH_WOW_USER_PATTERN_EN
- AIC23_FORMATS
- AIC23_RATES
- AIC26_DATFM_DSP
- AIC26_DATFM_I2S
- AIC26_DATFM_LEFTJ
- AIC26_DATFM_RIGHTJ
- AIC26_DIV_1
- AIC26_DIV_1_5
- AIC26_DIV_2
- AIC26_DIV_3
- AIC26_DIV_4
- AIC26_DIV_5
- AIC26_DIV_5_5
- AIC26_DIV_6
- AIC26_FORMATS
- AIC26_PAGE_ADDR
- AIC26_RATES
- AIC26_REG_ADC_GAIN
- AIC26_REG_AUDIO_CTRL1
- AIC26_REG_AUDIO_CTRL2
- AIC26_REG_AUDIO_CTRL3
- AIC26_REG_AUDIO_CTRL4
- AIC26_REG_AUDIO_CTRL5
- AIC26_REG_AUX
- AIC26_REG_AUX_ADC
- AIC26_REG_BAT1
- AIC26_REG_BAT2
- AIC26_REG_DAC_GAIN
- AIC26_REG_FILTER_COEFF_L_D1
- AIC26_REG_FILTER_COEFF_L_D2
- AIC26_REG_FILTER_COEFF_L_D4
- AIC26_REG_FILTER_COEFF_L_D5
- AIC26_REG_FILTER_COEFF_L_N0
- AIC26_REG_FILTER_COEFF_L_N1
- AIC26_REG_FILTER_COEFF_L_N2
- AIC26_REG_FILTER_COEFF_L_N3
- AIC26_REG_FILTER_COEFF_L_N4
- AIC26_REG_FILTER_COEFF_L_N5
- AIC26_REG_FILTER_COEFF_R_D1
- AIC26_REG_FILTER_COEFF_R_D2
- AIC26_REG_FILTER_COEFF_R_D4
- AIC26_REG_FILTER_COEFF_R_D5
- AIC26_REG_FILTER_COEFF_R_N0
- AIC26_REG_FILTER_COEFF_R_N1
- AIC26_REG_FILTER_COEFF_R_N2
- AIC26_REG_FILTER_COEFF_R_N3
- AIC26_REG_FILTER_COEFF_R_N4
- AIC26_REG_FILTER_COEFF_R_N5
- AIC26_REG_PLL_PROG1
- AIC26_REG_PLL_PROG2
- AIC26_REG_POWER_CTRL
- AIC26_REG_REFERENCE
- AIC26_REG_RESET
- AIC26_REG_SIDETONE
- AIC26_REG_STATUS
- AIC26_REG_TEMP1
- AIC26_REG_TEMP2
- AIC26_WLEN_16
- AIC26_WLEN_20
- AIC26_WLEN_24
- AIC26_WLEN_32
- AIC3100
- AIC3110
- AIC3111
- AIC3120
- AIC31XX_ADC2BCLK
- AIC31XX_ADCFGA
- AIC31XX_ADCFLAG
- AIC31XX_ADCMOD2BCLK
- AIC31XX_ADCPRB
- AIC31XX_ADCPWRSTATUS_MASK
- AIC31XX_ADCSETUP
- AIC31XX_ADCVOL
- AIC31XX_ADC_OF
- AIC31XX_ADC_OF_SHIFTER
- AIC31XX_AGCNOISE
- AIC31XX_AOSR
- AIC31XX_BCLKINV_MASK
- AIC31XX_BCLKN
- AIC31XX_BCLK_MASTER
- AIC31XX_BDIVCLK_MASK
- AIC31XX_BUTTONPRESS
- AIC31XX_BUTTONPRESSDET
- AIC31XX_CLKMUX
- AIC31XX_CLKOUTMUX
- AIC31XX_CLKOUTMVAL
- AIC31XX_CODEC_CLKIN_BCLK
- AIC31XX_CODEC_CLKIN_GPIO1
- AIC31XX_CODEC_CLKIN_MASK
- AIC31XX_CODEC_CLKIN_MCLK
- AIC31XX_CODEC_CLKIN_PLL
- AIC31XX_CODEC_CLKIN_SHIFT
- AIC31XX_DAC2BCLK
- AIC31XX_DACAINT
- AIC31XX_DACFLAG1
- AIC31XX_DACFLAG2
- AIC31XX_DACMIXERROUTE
- AIC31XX_DACMOD2BCLK
- AIC31XX_DACMUTE
- AIC31XX_DACMUTE_MASK
- AIC31XX_DACPRB
- AIC31XX_DACSETUP
- AIC31XX_DACSINT
- AIC31XX_DAC_OF_LEFT
- AIC31XX_DAC_OF_RIGHT
- AIC31XX_DAC_OF_SHIFTER
- AIC31XX_DATA_OFFSET
- AIC31XX_DATA_OFFSET_MASK
- AIC31XX_DOSRLSB
- AIC31XX_DOSRMSB
- AIC31XX_DRCTHRES
- AIC31XX_DSP_MODE
- AIC31XX_ENGINE
- AIC31XX_FORMATS
- AIC31XX_GPIO1
- AIC31XX_GPIO1_ADC_MOD_CLK
- AIC31XX_GPIO1_ADC_WCLK
- AIC31XX_GPIO1_CLKOUT
- AIC31XX_GPIO1_DISABLED
- AIC31XX_GPIO1_FUNC_MASK
- AIC31XX_GPIO1_FUNC_SHIFT
- AIC31XX_GPIO1_GPI
- AIC31XX_GPIO1_GPO
- AIC31XX_GPIO1_INPUT
- AIC31XX_GPIO1_INT1
- AIC31XX_GPIO1_INT2
- AIC31XX_GPIO1_SBCLK
- AIC31XX_GPIO1_SDOUT
- AIC31XX_GPIO1_SWCLK
- AIC31XX_HPCONTROL
- AIC31XX_HPDRIVER
- AIC31XX_HPLDRVPWRSTATUS_MASK
- AIC31XX_HPLGAIN
- AIC31XX_HPLSCDETECT
- AIC31XX_HPPOP
- AIC31XX_HPRDRVPWRSTATUS_MASK
- AIC31XX_HPRGAIN
- AIC31XX_HPRSCDETECT
- AIC31XX_HSDETECT
- AIC31XX_HSD_ENABLE
- AIC31XX_HSD_HP
- AIC31XX_HSD_HS
- AIC31XX_HSD_NONE
- AIC31XX_HSD_TYPE_MASK
- AIC31XX_HSD_TYPE_SHIFT
- AIC31XX_HSPLUG
- AIC31XX_HSPLUGDET
- AIC31XX_I2C
- AIC31XX_I2S_MODE
- AIC31XX_IFACE1
- AIC31XX_IFACE1_DATALEN_MASK
- AIC31XX_IFACE1_DATALEN_SHIFT
- AIC31XX_IFACE1_DATATYPE_MASK
- AIC31XX_IFACE1_DATATYPE_SHIFT
- AIC31XX_IFACE1_MASTER_MASK
- AIC31XX_IFACE2
- AIC31XX_IFACESEC1
- AIC31XX_IFACESEC2
- AIC31XX_IFACESEC3
- AIC31XX_INT1CTRL
- AIC31XX_INT2CTRL
- AIC31XX_INTRADCFLAG
- AIC31XX_INTRADCFLAG2
- AIC31XX_INTRDACFLAG
- AIC31XX_INTRDACFLAG2
- AIC31XX_JACK_MASK
- AIC31XX_KEEP_I2SCLK
- AIC31XX_LANALOGHPL
- AIC31XX_LANALOGSPL
- AIC31XX_LDACPWRSTATUS_MASK
- AIC31XX_LDACVOL
- AIC31XX_LDRCTHRES
- AIC31XX_LEFT_JUSTIFIED_MODE
- AIC31XX_MADC
- AIC31XX_MDAC
- AIC31XX_MICBIAS
- AIC31XX_MICBIAS_MASK
- AIC31XX_MICBIAS_SHIFT
- AIC31XX_MICPGA
- AIC31XX_MICPGACM
- AIC31XX_MICPGAMI
- AIC31XX_MICPGAPI
- AIC31XX_MINIDSP_BIT
- AIC31XX_MINI_DSP_INPOL
- AIC31XX_NADC
- AIC31XX_NDAC
- AIC31XX_NUM_SUPPLIES
- AIC31XX_OFFLAG
- AIC31XX_OT_FLAG
- AIC31XX_PAGECTL
- AIC31XX_PLLDLSB
- AIC31XX_PLLDMSB
- AIC31XX_PLLJ
- AIC31XX_PLLPR
- AIC31XX_PLL_CLKIN_BCKL
- AIC31XX_PLL_CLKIN_DIN
- AIC31XX_PLL_CLKIN_GPIO1
- AIC31XX_PLL_CLKIN_MASK
- AIC31XX_PLL_CLKIN_MCLK
- AIC31XX_PLL_CLKIN_SHIFT
- AIC31XX_PLL_MASK
- AIC31XX_PM_MASK
- AIC31XX_RANALOGHPR
- AIC31XX_RANALOGSPR
- AIC31XX_RATES
- AIC31XX_RDACPWRSTATUS_MASK
- AIC31XX_RDACVOL
- AIC31XX_RDRCTHRES
- AIC31XX_REG
- AIC31XX_RESET
- AIC31XX_RIGHT_JUSTIFIED_MODE
- AIC31XX_SC
- AIC31XX_SOFTSTEP_MASK
- AIC31XX_SPKAMP
- AIC31XX_SPLDRVPWRSTATUS_MASK
- AIC31XX_SPLGAIN
- AIC31XX_SPPGARAMP
- AIC31XX_SPRDRVPWRSTATUS_MASK
- AIC31XX_SPRGAIN
- AIC31XX_STEREO_CLASS_D_BIT
- AIC31XX_WCLK_MASTER
- AIC31XX_WORD_LEN_16BITS
- AIC31XX_WORD_LEN_20BITS
- AIC31XX_WORD_LEN_24BITS
- AIC31XX_WORD_LEN_32BITS
- AIC32X4_ADC2BCLK
- AIC32X4_ADCFGA
- AIC32X4_ADCMOD2BCLK
- AIC32X4_ADCSETUP
- AIC32X4_ADCSPB
- AIC32X4_AOSR
- AIC32X4_AVDDWEAKDISABLE
- AIC32X4_BCLKEN
- AIC32X4_BCLKINV_MASK
- AIC32X4_BCLKMASTER
- AIC32X4_BCLKN
- AIC32X4_BCLK_MASK
- AIC32X4_BDIVCLK_MASK
- AIC32X4_BDIVCLK_SHIFT
- AIC32X4_CLKMUX
- AIC32X4_CLKMUX2
- AIC32X4_CLKOUTM
- AIC32X4_CMMODE
- AIC32X4_CODEC_CLKIN_BCLK
- AIC32X4_CODEC_CLKIN_GPIO1
- AIC32X4_CODEC_CLKIN_MASK
- AIC32X4_CODEC_CLKIN_MCLK
- AIC32X4_CODEC_CLKIN_PLL
- AIC32X4_CODEC_CLKIN_SHIFT
- AIC32X4_DAC2BCLK
- AIC32X4_DACMOD2BCLK
- AIC32X4_DACMUTE
- AIC32X4_DACSETUP
- AIC32X4_DACSPB
- AIC32X4_DAC_CHAN_MASK
- AIC32X4_DATA_OFFSET_MASK
- AIC32X4_DINCTL
- AIC32X4_DIVEN
- AIC32X4_DIV_MASK
- AIC32X4_DOSRLSB
- AIC32X4_DOSRMSB
- AIC32X4_DOUTCTL
- AIC32X4_DSP_MODE
- AIC32X4_FLOATINGINPUT
- AIC32X4_FORMATS
- AIC32X4_GPIOCTL
- AIC32X4_HEADSTART
- AIC32X4_HPLGAIN
- AIC32X4_HPLROUTE
- AIC32X4_HPRGAIN
- AIC32X4_HPRROUTE
- AIC32X4_I2S_MODE
- AIC32X4_IFACE1
- AIC32X4_IFACE1_DATALEN_MASK
- AIC32X4_IFACE1_DATALEN_SHIFT
- AIC32X4_IFACE1_DATATYPE_MASK
- AIC32X4_IFACE1_DATATYPE_SHIFT
- AIC32X4_IFACE1_MASTER_MASK
- AIC32X4_IFACE2
- AIC32X4_IFACE3
- AIC32X4_IFACE4
- AIC32X4_IFACE5
- AIC32X4_IFACE6
- AIC32X4_LADCVOL
- AIC32X4_LADC_EN
- AIC32X4_LAGC1
- AIC32X4_LAGC2
- AIC32X4_LAGC3
- AIC32X4_LAGC4
- AIC32X4_LAGC5
- AIC32X4_LAGC6
- AIC32X4_LAGC7
- AIC32X4_LDAC2LCHN
- AIC32X4_LDAC2RCHN
- AIC32X4_LDACVOL
- AIC32X4_LDOCTL
- AIC32X4_LDOCTLEN
- AIC32X4_LDOIN2HP
- AIC32X4_LDOIN_18_36
- AIC32X4_LEFT_JUSTIFIED_MODE
- AIC32X4_LMICPGANIN
- AIC32X4_LMICPGANIN_CM1L_10K
- AIC32X4_LMICPGANIN_IN2R_10K
- AIC32X4_LMICPGAPIN
- AIC32X4_LMICPGAVOL
- AIC32X4_LOLGAIN
- AIC32X4_LOLROUTE
- AIC32X4_LORGAIN
- AIC32X4_LORROUTE
- AIC32X4_LPLAYBACK
- AIC32X4_MADC
- AIC32X4_MADCEN
- AIC32X4_MADC_MASK
- AIC32X4_MAX_CODEC_CLKIN_FREQ
- AIC32X4_MAX_DOSR_FREQ
- AIC32X4_MAX_PLL_CLKIN
- AIC32X4_MDAC
- AIC32X4_MDACEN
- AIC32X4_MDAC_MASK
- AIC32X4_MFP1_DIN_DISABLED
- AIC32X4_MFP1_DIN_ENABLED
- AIC32X4_MFP1_GPIO_IN
- AIC32X4_MFP2_GPIO_OUT_HIGH
- AIC32X4_MFP2_GPIO_OUT_LOW
- AIC32X4_MFP5_GPIO_DISABLED
- AIC32X4_MFP5_GPIO_INPUT
- AIC32X4_MFP5_GPIO_OUTPUT
- AIC32X4_MFP5_GPIO_OUT_HIGH
- AIC32X4_MFP5_GPIO_OUT_LOW
- AIC32X4_MFPX_DEFAULT_VALUE
- AIC32X4_MFP_GPIO_ENABLED
- AIC32X4_MICBIAS
- AIC32X4_MICBIAS_2075V
- AIC32X4_MICBIAS_LDOIN
- AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K
- AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K
- AIC32X4_MIN_DOSR_FREQ
- AIC32X4_MISOCTL
- AIC32X4_MUTEON
- AIC32X4_NADC
- AIC32X4_NADCEN
- AIC32X4_NADC_MASK
- AIC32X4_NDAC
- AIC32X4_NDACEN
- AIC32X4_NDAC_MASK
- AIC32X4_OUTPWRCTL
- AIC32X4_PLLDLSB
- AIC32X4_PLLDMSB
- AIC32X4_PLLEN
- AIC32X4_PLLJ
- AIC32X4_PLLPR
- AIC32X4_PLL_CLKIN_BCKL
- AIC32X4_PLL_CLKIN_DIN
- AIC32X4_PLL_CLKIN_GPIO1
- AIC32X4_PLL_CLKIN_MASK
- AIC32X4_PLL_CLKIN_MCLK
- AIC32X4_PLL_CLKIN_SHIFT
- AIC32X4_PLL_P_MASK
- AIC32X4_PLL_P_SHIFT
- AIC32X4_PLL_R_MASK
- AIC32X4_PSEL
- AIC32X4_PWRCFG
- AIC32X4_PWR_AIC32X4_LDO_ENABLE
- AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE
- AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED
- AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36
- AIC32X4_PWR_MICBIAS_2075_LDOIN
- AIC32X4_RADCVOL
- AIC32X4_RADC_EN
- AIC32X4_RAGC1
- AIC32X4_RAGC2
- AIC32X4_RAGC3
- AIC32X4_RAGC4
- AIC32X4_RAGC5
- AIC32X4_RAGC6
- AIC32X4_RAGC7
- AIC32X4_RATES
- AIC32X4_RDAC2LCHN
- AIC32X4_RDAC2RCHN
- AIC32X4_RDACVOL
- AIC32X4_REG
- AIC32X4_RESET
- AIC32X4_RIGHT_JUSTIFIED_MODE
- AIC32X4_RMICPGANIN
- AIC32X4_RMICPGANIN_CM1R_10K
- AIC32X4_RMICPGANIN_IN1L_10K
- AIC32X4_RMICPGAPIN
- AIC32X4_RMICPGAVOL
- AIC32X4_RPLAYBACK
- AIC32X4_SCLKCTL
- AIC32X4_WCLKMASTER
- AIC32X4_WORD_LEN_16BITS
- AIC32X4_WORD_LEN_20BITS
- AIC32X4_WORD_LEN_24BITS
- AIC32X4_WORD_LEN_32BITS
- AIC32x4_MICBIAS_MASK
- AIC3X_ASD_INTF_CTRLA
- AIC3X_ASD_INTF_CTRLB
- AIC3X_ASD_INTF_CTRLC
- AIC3X_BUTTON_DEBOUNCE_0MS
- AIC3X_BUTTON_DEBOUNCE_16MS
- AIC3X_BUTTON_DEBOUNCE_32MS
- AIC3X_BUTTON_DEBOUNCE_8MS
- AIC3X_BUTTON_DEBOUNCE_MASK
- AIC3X_BUTTON_DEBOUNCE_SHIFT
- AIC3X_CACHEREGNUM
- AIC3X_CLKGEN_CTRL_REG
- AIC3X_CODEC_DATAPATH_REG
- AIC3X_CODEC_DFILT_CTRL
- AIC3X_FORMATS
- AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ
- AIC3X_GPIO1_FUNC_ALL_IRQ
- AIC3X_GPIO1_FUNC_AUDIO_WORDCLK
- AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC
- AIC3X_GPIO1_FUNC_BUTTON_IRQ
- AIC3X_GPIO1_FUNC_CLOCK_MUX
- AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2
- AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4
- AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8
- AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
- AIC3X_GPIO1_FUNC_DISABLED
- AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ
- AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ
- AIC3X_GPIO1_FUNC_INPUT
- AIC3X_GPIO1_FUNC_OUTPUT
- AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ
- AIC3X_GPIO1_REG
- AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ
- AIC3X_GPIO2_FUNC_ALL_IRQ
- AIC3X_GPIO2_FUNC_AUDIO_BITCLK
- AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ
- AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT
- AIC3X_GPIO2_FUNC_DISABLED
- AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ
- AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ
- AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ
- AIC3X_GPIO2_FUNC_INPUT
- AIC3X_GPIO2_FUNC_OUTPUT
- AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ
- AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ
- AIC3X_GPIO2_REG
- AIC3X_GPIOA_REG
- AIC3X_GPIOB_REG
- AIC3X_HEADSET_DEBOUNCE_128MS
- AIC3X_HEADSET_DEBOUNCE_16MS
- AIC3X_HEADSET_DEBOUNCE_256MS
- AIC3X_HEADSET_DEBOUNCE_32MS
- AIC3X_HEADSET_DEBOUNCE_512MS
- AIC3X_HEADSET_DEBOUNCE_64MS
- AIC3X_HEADSET_DEBOUNCE_MASK
- AIC3X_HEADSET_DEBOUNCE_SHIFT
- AIC3X_HEADSET_DETECT_BOTH
- AIC3X_HEADSET_DETECT_CELLULAR
- AIC3X_HEADSET_DETECT_CTRL_A
- AIC3X_HEADSET_DETECT_CTRL_B
- AIC3X_HEADSET_DETECT_ENABLED
- AIC3X_HEADSET_DETECT_MASK
- AIC3X_HEADSET_DETECT_OFF
- AIC3X_HEADSET_DETECT_SHIFT
- AIC3X_HEADSET_DETECT_STEREO
- AIC3X_MICBIAS_2_0V
- AIC3X_MICBIAS_2_5V
- AIC3X_MICBIAS_AVDDV
- AIC3X_MICBIAS_OFF
- AIC3X_MODEL_3007
- AIC3X_MODEL_3104
- AIC3X_MODEL_33
- AIC3X_MODEL_3X
- AIC3X_NUM_SUPPLIES
- AIC3X_OVRF_STATUS_AND_PLLR_REG
- AIC3X_PAGE_SELECT
- AIC3X_PLL_PROGA_REG
- AIC3X_PLL_PROGB_REG
- AIC3X_PLL_PROGC_REG
- AIC3X_PLL_PROGD_REG
- AIC3X_RATES
- AIC3X_RESET
- AIC3X_RT_IRQ_FLAGS_REG
- AIC3X_SAMPLE_RATE_SEL_REG
- AIC3X_STICKY_IRQ_FLAGS_REG
- AIC79XX_AMPLITUDE_INDEX
- AIC79XX_CMDS_PER_DEVICE
- AIC79XX_CONFIGED_TAG_COMMANDS
- AIC79XX_DEFAULT_AMPLITUDE
- AIC79XX_DEFAULT_IOOPTS
- AIC79XX_DEFAULT_PRECOMP
- AIC79XX_DEFAULT_SLEWRATE
- AIC79XX_DRIVER_VERSION
- AIC79XX_PRECOMP_INDEX
- AIC79XX_RESET_DELAY
- AIC79XX_SLEWRATE_INDEX
- AIC7XXX_CMDS_PER_DEVICE
- AIC7XXX_CONFIGED_TAG_COMMANDS
- AIC7XXX_DRIVER_VERSION
- AIC7XXX_RESET_DELAY
- AIC9410_DEV_REV_B0
- AIC94XX_SCB_TIMEOUT
- AICA_BUFFER_SIZE
- AICA_CHANNEL0_CONTROL_OFFSET
- AICA_CHANNEL0_OFFSET
- AICA_CHANNEL1_OFFSET
- AICA_CMD_KICK
- AICA_CMD_NONE
- AICA_CMD_START
- AICA_CMD_STOP
- AICA_CMD_VOL
- AICA_CONTROL_CHANNEL_SAMPLE_NUMBER
- AICA_CONTROL_POINT
- AICA_DMA_CHANNEL
- AICA_DMA_MODE
- AICA_PERIOD_NUMBER
- AICA_PERIOD_SIZE
- AICA_RTC_SECS_H
- AICA_RTC_SECS_L
- AICSR
- AICV
- AIC_ACK
- AIC_CAL_STATE_DONE
- AIC_CAL_STATE_ERROR
- AIC_CAL_STATE_IDLE
- AIC_CAL_STATE_STARTED
- AIC_CTRL
- AIC_DEBUG_REGISTERS
- AIC_ENABLED_STAT
- AIC_ENABLE_CLR
- AIC_ENABLE_CTRL
- AIC_ENABLE_SET
- AIC_G_ACK
- AIC_G_ENABLED_STAT
- AIC_G_ENABLE_CLR
- AIC_G_ENABLE_CTRL
- AIC_G_ENABLE_SET
- AIC_G_OPTIONS
- AIC_G_POL_CTRL
- AIC_G_RAW_STAT
- AIC_G_TYPE_CTRL
- AIC_G_VERSION
- AIC_HI_ADDR
- AIC_LIB_PREFIX
- AIC_LO_ADDR
- AIC_OPTIONS
- AIC_OP_ADC
- AIC_OP_ADC16
- AIC_OP_ADD
- AIC_OP_ADD16
- AIC_OP_AND
- AIC_OP_AND16
- AIC_OP_BMOV
- AIC_OP_CALL
- AIC_OP_CALL16
- AIC_OP_CALLF
- AIC_OP_CMPXCHG
- AIC_OP_JC
- AIC_OP_JC16
- AIC_OP_JCF
- AIC_OP_JE
- AIC_OP_JE16
- AIC_OP_JMP
- AIC_OP_JMP16
- AIC_OP_JMPF
- AIC_OP_JNC
- AIC_OP_JNC16
- AIC_OP_JNCF
- AIC_OP_JNE
- AIC_OP_JNE16
- AIC_OP_JNZ
- AIC_OP_JNZ16
- AIC_OP_JZ
- AIC_OP_JZ16
- AIC_OP_MVI16
- AIC_OP_OR
- AIC_OP_OR16
- AIC_OP_ROL
- AIC_OP_ROR
- AIC_OP_SHL
- AIC_OP_SHR
- AIC_OP_XOR
- AIC_OP_XOR16
- AIC_POL_CTRL
- AIC_PT_BASE
- AIC_RAW_STAL
- AIC_STAT
- AIC_TLB_ADDR
- AIC_TLB_DATA
- AIC_TYPE_CTRL
- AIC_VERSION
- AID_1
- AID_2
- AID_3
- AID_DISABLE
- AIF1_CAP
- AIF1_PB
- AIF2_CAP
- AIF2_PB
- AIF3_CAP
- AIF3_PB
- AIF4_PB
- AIFSN_BE
- AIFSN_BK
- AIFSN_CSR
- AIFSN_CSR_AIFSN0
- AIFSN_CSR_AIFSN1
- AIFSN_CSR_AIFSN2
- AIFSN_CSR_AIFSN3
- AIFSN_VI
- AIFSN_VO
- AIFSR
- AIFS_DIFS
- AIFS_PIFS
- AIF_FLUSH
- AIF_LISTEN
- AIF_RESET
- AIF_SNIFF_TIMEOUT
- AIF_TALK
- AIGAIN
- AIMAP_B
- AIMAP_OFF
- AIMODE_HALF_FULL
- AIMODE_NONE
- AIMODE_SAMPLE
- AIMODE_SCAN
- AIMS_BIT_TUN_CE
- AIMS_BIT_TUN_CLK
- AIMS_BIT_TUN_DATA
- AIMS_BIT_TUN_STRQ
- AIMS_BIT_VOL_CE
- AIMS_BIT_VOL_DN
- AIMS_BIT_VOL_UP
- AIM_ARC
- AIM_CHECK
- AIM_NXT
- AIN34_SEL
- AINC
- AINNERSHARED
- AINNERSHARED_MASK
- AINNERSHARED_SHIFT
- AINST
- AINST_MASK
- AINST_SHIFT
- AINT_BIST_INT
- AINT_BM_ERROR
- AINT_IMB_BYTE
- AINT_IMB_ENABLE
- AINT_IMB_SELECT
- AINT_INT_ASSERTED
- AINT_INT_MASK
- AINT_IN_MB_INT
- AINT_IS_ENSEL_MASK
- AINT_OMB_BYTE
- AINT_OMB_ENABLE
- AINT_OMB_SELECT
- AINT_OUT_MB_INT
- AINT_READ_COMPL
- AINT_RT_COMPLETE
- AINT_SEL_MASK
- AINT_WRITE_COMPL
- AINT_WT_COMPLETE
- AIN_BUF_SIZE
- AIO
- AIO12_8_8254_BASE_REG
- AIO12_8_8255_BASE_REG
- AIO12_8_ADC_ACQ
- AIO12_8_ADC_ACQ_3USEC
- AIO12_8_ADC_ACQ_PROGRAM
- AIO12_8_ADC_CHAN
- AIO12_8_ADC_MODE
- AIO12_8_ADC_MODE_INT_CLK
- AIO12_8_ADC_MODE_NORMAL
- AIO12_8_ADC_MODE_POWERDOWN
- AIO12_8_ADC_MODE_STANDBY
- AIO12_8_ADC_RANGE
- AIO12_8_ADC_REG
- AIO12_8_ADC_TRIGGER_CHAN
- AIO12_8_ADC_TRIGGER_RANGE
- AIO12_8_ADC_TRIGGER_REG
- AIO12_8_COS_REG
- AIO12_8_DAC_ENABLE_REF_ENA
- AIO12_8_DAC_ENABLE_REG
- AIO12_8_DAC_REG
- AIO12_8_DIO_CONTROL_REG
- AIO12_8_DIO_CONTROL_TST
- AIO12_8_INTERRUPT_ADC
- AIO12_8_INTERRUPT_COS
- AIO12_8_INTERRUPT_COUNTER1
- AIO12_8_INTERRUPT_ENA
- AIO12_8_INTERRUPT_PORT_C0
- AIO12_8_INTERRUPT_PORT_C3
- AIO12_8_INTERRUPT_REG
- AIO12_8_STATUS_ADC_EOC
- AIO12_8_STATUS_IRQ_ENA
- AIO12_8_STATUS_PORT_C_COS
- AIO12_8_STATUS_REG
- AIO12_8_TRIGGER_ADTRIG
- AIO12_8_TRIGGER_DACTRIG
- AIO12_8_TRIGGER_REG
- AIOPID_0001
- AIOPID_NULL
- AIOP_BUFFER_OFFSET
- AIOP_BUFFER_SIZE
- AIOP_CTL_SIZE
- AIOP_INTR_BITS
- AIOP_INTR_BIT_0
- AIOP_INTR_BIT_1
- AIOP_INTR_BIT_2
- AIOP_INTR_BIT_3
- AIOP_OFFSET_DELTA
- AIO_EVENTS_FIRST_PAGE
- AIO_EVENTS_OFFSET
- AIO_EVENTS_PER_PAGE
- AIO_IIRO_16_INPUT_0_7
- AIO_IIRO_16_INPUT_8_15
- AIO_IIRO_16_IRQ
- AIO_IIRO_16_RELAY_0_7
- AIO_IIRO_16_RELAY_8_15
- AIO_IIRO_16_STATUS
- AIO_IIRO_16_STATUS_INPUT_0_7
- AIO_IIRO_16_STATUS_INPUT_8_15
- AIO_IIRO_16_STATUS_IRQE
- AIO_IN_DS_CHANNELS
- AIO_IN_QS_CHANNELS
- AIO_IN_SS_CHANNELS
- AIO_MAX
- AIO_OUT_DS_CHANNELS
- AIO_OUT_QS_CHANNELS
- AIO_OUT_SS_CHANNELS
- AIO_PATH
- AIO_PLUG_THRESHOLD
- AIO_RING_COMPAT_FEATURES
- AIO_RING_INCOMPAT_FEATURES
- AIO_RING_MAGIC
- AIO_RING_PAGES
- AIP
- AIPCKEN
- AIPEN
- AIPTEK_COORDINATE_ABSOLUTE_MODE
- AIPTEK_COORDINATE_RELATIVE_MODE
- AIPTEK_DIAGNOSTIC_NA
- AIPTEK_DIAGNOSTIC_SENDING_ABSOLUTE_IN_RELATIVE
- AIPTEK_DIAGNOSTIC_SENDING_RELATIVE_IN_ABSOLUTE
- AIPTEK_DIAGNOSTIC_TOOL_DISALLOWED
- AIPTEK_INVALID_VALUE
- AIPTEK_JITTER_DELAY_DEFAULT
- AIPTEK_MOUSE_LEFT_BUTTON
- AIPTEK_MOUSE_MIDDLE_BUTTON
- AIPTEK_MOUSE_RIGHT_BUTTON
- AIPTEK_PACKET_LENGTH
- AIPTEK_POINTER_ALLOW_MOUSE_MODE
- AIPTEK_POINTER_ALLOW_STYLUS_MODE
- AIPTEK_POINTER_EITHER_MODE
- AIPTEK_POINTER_ONLY_MOUSE_MODE
- AIPTEK_POINTER_ONLY_STYLUS_MODE
- AIPTEK_PROGRAMMABLE_DELAY_100
- AIPTEK_PROGRAMMABLE_DELAY_200
- AIPTEK_PROGRAMMABLE_DELAY_25
- AIPTEK_PROGRAMMABLE_DELAY_300
- AIPTEK_PROGRAMMABLE_DELAY_400
- AIPTEK_PROGRAMMABLE_DELAY_50
- AIPTEK_PROGRAMMABLE_DELAY_DEFAULT
- AIPTEK_REPORT_TOOL_MOUSE
- AIPTEK_REPORT_TOOL_STYLUS
- AIPTEK_REPORT_TOOL_UNKNOWN
- AIPTEK_STYLUS_LOWER_BUTTON
- AIPTEK_STYLUS_UPPER_BUTTON
- AIPTEK_TILT_DISABLE
- AIPTEK_TILT_MAX
- AIPTEK_TILT_MIN
- AIPTEK_TOOL_BUTTON_AIRBRUSH_MODE
- AIPTEK_TOOL_BUTTON_BRUSH_MODE
- AIPTEK_TOOL_BUTTON_ERASER_MODE
- AIPTEK_TOOL_BUTTON_LENS_MODE
- AIPTEK_TOOL_BUTTON_MOUSE_MODE
- AIPTEK_TOOL_BUTTON_PENCIL_MODE
- AIPTEK_TOOL_BUTTON_PEN_MODE
- AIPTEK_WHEEL_DISABLE
- AIPTEK_WHEEL_MAX
- AIPTEK_WHEEL_MIN
- AIP_CLKSEL_AIP_I2S
- AIP_CLKSEL_AIP_SPDIF
- AIP_CLKSEL_FS_ACLK
- AIP_CLKSEL_FS_FS64SPDIF
- AIP_CLKSEL_FS_MCLK
- AIP_CNTRL_0_ACR_MAN
- AIP_CNTRL_0_LAYOUT
- AIP_CNTRL_0_RST_CTS
- AIP_CNTRL_0_RST_FIFO
- AIP_CNTRL_0_SWAP
- AIP_LIMIT
- AIRBUS_DS_P8GR
- AIRBUS_DS_VID
- AIRCABLE_USB_PID
- AIRCABLE_VID
- AIRC_RESET
- AIROFLPUTBUF
- AIROFLSHGCHR
- AIROFLSHPCHR
- AIROFLSHRST
- AIROFLSHSTFL
- AIROGCAP
- AIROGCFG
- AIROGDRVNAM
- AIROGEHTENC
- AIROGFLAGS
- AIROGID
- AIROGMICRID
- AIROGMICSTATS
- AIROGSLIST
- AIROGSTAT
- AIROGSTATSC32
- AIROGSTATSD32
- AIROGVLIST
- AIROGWEPKNV
- AIROGWEPKTMP
- AIROIDIFC
- AIROIOCTL
- AIROMAGIC
- AIROOLDIDIFC
- AIROOLDIOCTL
- AIROPAPLIST
- AIROPCAP
- AIROPCFG
- AIROPLEAPPWD
- AIROPLEAPUSR
- AIROPMACOFF
- AIROPMACON
- AIROPSIDS
- AIROPSLIST
- AIROPSTCLR
- AIROPVLIST
- AIROPWEPKEY
- AIROPWEPKEYNV
- AIRORESTART
- AIRORRID
- AIRORSWVERSION
- AIRO_DEF_MTU
- AIRO_FLASH
- AIRO_MAX_NETWORK_COUNT
- AIRPLUS_PRODUCT_MCD650
- AIRPLUS_VENDOR_ID
- AIRPORT_IO_LEN
- AIRQ_IV_ALLOC
- AIRQ_IV_BITLOCK
- AIRQ_IV_CACHELINE
- AIRQ_IV_DATA
- AIRQ_IV_PTR
- AIRQ_PTR_ALLOCATED
- AIRTIME_USE_RX
- AIRTIME_USE_TX
- AIR_COOLING
- AIS_MODE_MASK
- AITBL_B
- AITBL_OFF
- AIUINT_INPUT_DATA
- AIUINT_INPUT_DATALOST
- AIUINT_INPUT_DMAEND
- AIUINT_INPUT_DMAHALT
- AIUINT_OUTPUT_DMAEND
- AIUINT_OUTPUT_DMAHALT
- AIUINT_OUTPUT_NODATA
- AIU_CLOCK
- AIU_IRQ
- AIVEC_M
- AIVEC_S
- AIVEC_V
- AIX
- AIX_EVENT
- AIX_FORMAT
- AIX_LABEL_MAGIC1
- AIX_LABEL_MAGIC2
- AIX_LABEL_MAGIC3
- AIX_LABEL_MAGIC4
- AIX_REVERSE
- AI_BUFFER_SIZE
- AI_GREENLAND_P_A0
- AI_GREENLAND_P_A1
- AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE
- AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE
- AI_MAILBOX_POLL_ACK_TIMEDOUT
- AI_MAILBOX_POLL_FLR_TIMEDOUT
- AI_MAILBOX_POLL_MSG_TIMEDOUT
- AI_SHIFT
- AI_UNKNOWN
- AI_VEGA12_P_A0
- AI_VEGA20_P_A0
- AK09911
- AK09911_DEVICE_ID
- AK09911_REG_INFO1
- AK09911_REG_INFO2
- AK09912
- AK09912_DEVICE_ID
- AK09912_MAX_REGS
- AK09912_REG_ASAX
- AK09912_REG_ASAY
- AK09912_REG_ASAZ
- AK09912_REG_CNTL1
- AK09912_REG_CNTL2
- AK09912_REG_CNTL2_MODE_MASK
- AK09912_REG_CNTL2_MODE_SHIFT
- AK09912_REG_CNTL3
- AK09912_REG_CNTL_MODE_FUSE_ROM
- AK09912_REG_CNTL_MODE_ONCE
- AK09912_REG_CNTL_MODE_POWER_DOWN
- AK09912_REG_CNTL_MODE_SELF_TEST
- AK09912_REG_HXH
- AK09912_REG_HXL
- AK09912_REG_HYH
- AK09912_REG_HYL
- AK09912_REG_HZH
- AK09912_REG_HZL
- AK09912_REG_I2CDIS
- AK09912_REG_ST1
- AK09912_REG_ST1_DRDY_MASK
- AK09912_REG_ST1_DRDY_SHIFT
- AK09912_REG_ST2
- AK09912_REG_ST2_HOFL_MASK
- AK09912_REG_ST2_HOFL_SHIFT
- AK09912_REG_TMPS
- AK09912_REG_TS1
- AK09912_REG_TS2
- AK09912_REG_TS3
- AK09912_REG_TS4
- AK09912_REG_WIA1
- AK09912_REG_WIA2
- AK4104_CONTROL1_DIF0
- AK4104_CONTROL1_DIF1
- AK4104_CONTROL1_PW
- AK4104_CONTROL1_RSTN
- AK4104_CONTROL2_MODE
- AK4104_CONTROL2_SEL0
- AK4104_CONTROL2_SEL1
- AK4104_NUM_REGS
- AK4104_READ
- AK4104_REG_CHN_STATUS
- AK4104_REG_CONTROL1
- AK4104_REG_CONTROL2
- AK4104_REG_MASK
- AK4104_REG_RESERVED
- AK4104_REG_TX
- AK4104_RESERVED_VAL
- AK4104_TX_TXE
- AK4104_TX_V
- AK4104_WRITE
- AK4113_ADDR
- AK4113_AUDION
- AK4113_AUTO
- AK4113_BCU
- AK4113_CCRC
- AK4113_CCRC_ERRORS
- AK4113_CHECK_NO_RATE
- AK4113_CHECK_NO_STAT
- AK4113_CINT
- AK4113_CM0
- AK4113_CM1
- AK4113_CONTROLS
- AK4113_CS12
- AK4113_DAT
- AK4113_DCNT
- AK4113_DEAU
- AK4113_DEM0
- AK4113_DEM1
- AK4113_DEM_32KHZ
- AK4113_DEM_44KHZ
- AK4113_DEM_48KHZ
- AK4113_DEM_OFF
- AK4113_DIF0
- AK4113_DIF1
- AK4113_DIF2
- AK4113_DIF_16R
- AK4113_DIF_18R
- AK4113_DIF_20R
- AK4113_DIF_24I2S
- AK4113_DIF_24L
- AK4113_DIF_24R
- AK4113_DIF_I24I2S
- AK4113_DIF_I24L
- AK4113_DIV
- AK4113_DTS14
- AK4113_DTS16
- AK4113_DTSCD
- AK4113_EFH0
- AK4113_EFH1
- AK4113_EFH_1024LRCLK
- AK4113_EFH_2048LRCLK
- AK4113_EFH_4096LRCLK
- AK4113_EFH_512LRCLK
- AK4113_FAST
- AK4113_FS0
- AK4113_FS1
- AK4113_FS2
- AK4113_FS3
- AK4113_FS_11025HZ
- AK4113_FS_16000HZ
- AK4113_FS_176400HZ
- AK4113_FS_192000HZ
- AK4113_FS_22050HZ
- AK4113_FS_24000HZ
- AK4113_FS_32000HZ
- AK4113_FS_44100HZ
- AK4113_FS_48000HZ
- AK4113_FS_64000HZ
- AK4113_FS_8000HZ
- AK4113_FS_88200HZ
- AK4113_FS_96000HZ
- AK4113_IPS
- AK4113_IPS0
- AK4113_IPS1
- AK4113_IPS2
- AK4113_MAN
- AK4113_MAUT
- AK4113_MCIT
- AK4113_MDAT0
- AK4113_MDAT1
- AK4113_MPR
- AK4113_MQI
- AK4113_MULK
- AK4113_NPCM
- AK4113_NUM_ERRORS
- AK4113_OCKS0
- AK4113_OCKS1
- AK4113_OPS0
- AK4113_OPS1
- AK4113_OPS2
- AK4113_PAR
- AK4113_PARITY_ERRORS
- AK4113_PEM
- AK4113_PWN
- AK4113_QCRC
- AK4113_QCRC_ERRORS
- AK4113_QINT
- AK4113_REG_DATDTS
- AK4113_REG_FORMAT
- AK4113_REG_INT0_MASK
- AK4113_REG_INT1_MASK
- AK4113_REG_IO0
- AK4113_REG_IO1
- AK4113_REG_PWRDN
- AK4113_REG_Pc0
- AK4113_REG_Pc1
- AK4113_REG_Pd0
- AK4113_REG_Pd1
- AK4113_REG_QSUB_ABSFRM
- AK4113_REG_QSUB_ABSMIN
- AK4113_REG_QSUB_ABSSEC
- AK4113_REG_QSUB_ADDR
- AK4113_REG_QSUB_FRAME
- AK4113_REG_QSUB_INDEX
- AK4113_REG_QSUB_MINUTE
- AK4113_REG_QSUB_SECOND
- AK4113_REG_QSUB_SIZE
- AK4113_REG_QSUB_TRACK
- AK4113_REG_QSUB_ZERO
- AK4113_REG_RCS0
- AK4113_REG_RCS1
- AK4113_REG_RCS2
- AK4113_REG_RXCSB0
- AK4113_REG_RXCSB1
- AK4113_REG_RXCSB2
- AK4113_REG_RXCSB3
- AK4113_REG_RXCSB4
- AK4113_REG_RXCSB_SIZE
- AK4113_RST
- AK4113_STC
- AK4113_TXE
- AK4113_UCE
- AK4113_UNLCK
- AK4113_V
- AK4113_VTX
- AK4113_V_BIT_ERRORS
- AK4113_WRITABLE_REGS
- AK4113_XMCK
- AK4113_XTL0
- AK4113_XTL1
- AK4113_XTL_11_2896M
- AK4113_XTL_12_288M
- AK4113_XTL_24_576M
- AK4114_ADDR
- AK4114_AUDION
- AK4114_AUTO
- AK4114_BCU
- AK4114_CCRC
- AK4114_CCRC_ERRORS
- AK4114_CHECK_NO_RATE
- AK4114_CHECK_NO_STAT
- AK4114_CINT
- AK4114_CM0
- AK4114_CM1
- AK4114_CONTROLS
- AK4114_CS12
- AK4114_DEAU
- AK4114_DEM0
- AK4114_DEM1
- AK4114_DEM_32KHZ
- AK4114_DEM_44KHZ
- AK4114_DEM_48KHZ
- AK4114_DEM_96KHZ
- AK4114_DFS
- AK4114_DIF0
- AK4114_DIF1
- AK4114_DIF2
- AK4114_DIF_16R
- AK4114_DIF_18R
- AK4114_DIF_20R
- AK4114_DIF_24I2S
- AK4114_DIF_24L
- AK4114_DIF_24R
- AK4114_DIF_I24I2S
- AK4114_DIF_I24L
- AK4114_DIT
- AK4114_DTSCD
- AK4114_EFH0
- AK4114_EFH1
- AK4114_EFH_1024
- AK4114_EFH_2048
- AK4114_EFH_4096
- AK4114_EFH_512
- AK4114_FS0
- AK4114_FS1
- AK4114_FS2
- AK4114_FS3
- AK4114_FS_176400HZ
- AK4114_FS_192000HZ
- AK4114_FS_32000HZ
- AK4114_FS_44100HZ
- AK4114_FS_48000HZ
- AK4114_FS_88200HZ
- AK4114_FS_96000HZ
- AK4114_IPS
- AK4114_IPS0
- AK4114_IPS1
- AK4114_IPS2
- AK4114_MONO
- AK4114_NUM_ERRORS
- AK4114_OCKS0
- AK4114_OCKS1
- AK4114_OPS00
- AK4114_OPS01
- AK4114_OPS02
- AK4114_OPS10
- AK4114_OPS11
- AK4114_OPS12
- AK4114_PAR
- AK4114_PARITY_ERRORS
- AK4114_PEM
- AK4114_PWN
- AK4114_QCRC
- AK4114_QCRC_ERRORS
- AK4114_QINT
- AK4114_REG_FORMAT
- AK4114_REG_INT0_MASK
- AK4114_REG_INT1_MASK
- AK4114_REG_IO0
- AK4114_REG_IO1
- AK4114_REG_PWRDN
- AK4114_REG_Pc0
- AK4114_REG_Pc1
- AK4114_REG_Pd0
- AK4114_REG_Pd1
- AK4114_REG_QSUB_ABSFRM
- AK4114_REG_QSUB_ABSMIN
- AK4114_REG_QSUB_ABSSEC
- AK4114_REG_QSUB_ADDR
- AK4114_REG_QSUB_FRAME
- AK4114_REG_QSUB_INDEX
- AK4114_REG_QSUB_MINUTE
- AK4114_REG_QSUB_SECOND
- AK4114_REG_QSUB_SIZE
- AK4114_REG_QSUB_TRACK
- AK4114_REG_QSUB_ZERO
- AK4114_REG_RCS0
- AK4114_REG_RCS1
- AK4114_REG_RXCSB0
- AK4114_REG_RXCSB1
- AK4114_REG_RXCSB2
- AK4114_REG_RXCSB3
- AK4114_REG_RXCSB4
- AK4114_REG_RXCSB_SIZE
- AK4114_REG_TXCSB0
- AK4114_REG_TXCSB1
- AK4114_REG_TXCSB2
- AK4114_REG_TXCSB3
- AK4114_REG_TXCSB4
- AK4114_REG_TXCSB_SIZE
- AK4114_RST
- AK4114_TLR
- AK4114_TX0E
- AK4114_TX1E
- AK4114_UDIT
- AK4114_UNLCK
- AK4114_V
- AK4114_V_BIT_ERRORS
- AK4117_ADDR
- AK4117_AUDION
- AK4117_AUTO
- AK4117_CCRC
- AK4117_CCRC_ERRORS
- AK4117_CHECK_NO_RATE
- AK4117_CHECK_NO_STAT
- AK4117_CINT
- AK4117_CM0
- AK4117_CM1
- AK4117_CM_MONITOR
- AK4117_CM_PLL
- AK4117_CM_PLL_XTAL
- AK4117_CM_XTAL
- AK4117_CONTROLS
- AK4117_CS12
- AK4117_DIF0
- AK4117_DIF1
- AK4117_DIF2
- AK4117_DIF_16R
- AK4117_DIF_18R
- AK4117_DIF_20R
- AK4117_DIF_24I2S
- AK4117_DIF_24L
- AK4117_DIF_24R
- AK4117_DIV
- AK4117_DTSCD
- AK4117_EFH1
- AK4117_EFH2
- AK4117_EFH_1024LRCLK
- AK4117_EFH_2048LRCLK
- AK4117_EFH_4096LRCLK
- AK4117_EFH_512LRCLK
- AK4117_EXCT
- AK4117_FS0
- AK4117_FS1
- AK4117_FS2
- AK4117_FS3
- AK4117_FS_176400HZ
- AK4117_FS_192000HZ
- AK4117_FS_32000HZ
- AK4117_FS_44100HZ
- AK4117_FS_48000HZ
- AK4117_FS_88200HZ
- AK4117_FS_96000HZ
- AK4117_IPS
- AK4117_LP
- AK4117_MAN
- AK4117_MAT
- AK4117_MAUD
- AK4117_MAUTO
- AK4117_MCI
- AK4117_MCIT
- AK4117_MDTS
- AK4117_MPAR
- AK4117_MPE
- AK4117_MPR
- AK4117_MQI
- AK4117_MQIT
- AK4117_MSTC
- AK4117_MUL
- AK4117_MULK
- AK4117_MV
- AK4117_NPCM
- AK4117_NUM_ERRORS
- AK4117_PAR
- AK4117_PARITY_ERRORS
- AK4117_PEM
- AK4117_PKCS0
- AK4117_PKCS1
- AK4117_PKCS_128fs
- AK4117_PKCS_256fs
- AK4117_PKCS_512fs
- AK4117_PWN
- AK4117_QCRC
- AK4117_QCRC_ERRORS
- AK4117_QINT
- AK4117_REG_CLOCK
- AK4117_REG_INT0_MASK
- AK4117_REG_INT1_MASK
- AK4117_REG_IO
- AK4117_REG_PWRDN
- AK4117_REG_Pc0
- AK4117_REG_Pc1
- AK4117_REG_Pd0
- AK4117_REG_Pd1
- AK4117_REG_QSUB_ABSFRM
- AK4117_REG_QSUB_ABSMIN
- AK4117_REG_QSUB_ABSSEC
- AK4117_REG_QSUB_ADDR
- AK4117_REG_QSUB_FRAME
- AK4117_REG_QSUB_INDEX
- AK4117_REG_QSUB_MINUTE
- AK4117_REG_QSUB_SECOND
- AK4117_REG_QSUB_SIZE
- AK4117_REG_QSUB_TRACK
- AK4117_REG_QSUB_ZERO
- AK4117_REG_RCS0
- AK4117_REG_RCS1
- AK4117_REG_RCS2
- AK4117_REG_RXCSB0
- AK4117_REG_RXCSB1
- AK4117_REG_RXCSB2
- AK4117_REG_RXCSB3
- AK4117_REG_RXCSB4
- AK4117_REG_RXCSB_SIZE
- AK4117_RST
- AK4117_STC
- AK4117_UNLCK
- AK4117_UOUTE
- AK4117_V
- AK4117_V_BIT_ERRORS
- AK4117_XCKS0
- AK4117_XCKS1
- AK4117_XCKS_1024fs
- AK4117_XCKS_128fs
- AK4117_XCKS_256fs
- AK4117_XCKS_512fs
- AK4117_XTL0
- AK4117_XTL1
- AK4117_XTL_11_2896M
- AK4117_XTL_12_288M
- AK4117_XTL_24_576M
- AK4117_XTL_EXT
- AK4118_REG_BURST_PREAMB_PC0
- AK4118_REG_BURST_PREAMB_PC1
- AK4118_REG_BURST_PREAMB_PD0
- AK4118_REG_BURST_PREAMB_PD1
- AK4118_REG_CLK_PWR_CTL
- AK4118_REG_DAT_MASK_DTS
- AK4118_REG_FORMAT_CTL
- AK4118_REG_FORMAT_CTL_DIF0
- AK4118_REG_FORMAT_CTL_DIF1
- AK4118_REG_FORMAT_CTL_DIF2
- AK4118_REG_GPDR
- AK4118_REG_GPE
- AK4118_REG_GPLR
- AK4118_REG_GPSCR
- AK4118_REG_INT0_MASK
- AK4118_REG_INT1_MASK
- AK4118_REG_IO_CTL0
- AK4118_REG_IO_CTL1
- AK4118_REG_MAX
- AK4118_REG_QSUB_ABS_FRAME
- AK4118_REG_QSUB_ABS_MIN
- AK4118_REG_QSUB_ABS_SEC
- AK4118_REG_QSUB_CTL
- AK4118_REG_QSUB_FRAME
- AK4118_REG_QSUB_INDEX
- AK4118_REG_QSUB_MIN
- AK4118_REG_QSUB_SEC
- AK4118_REG_QSUB_TRACK
- AK4118_REG_QSUB_ZERO
- AK4118_REG_RCV_STATUS0
- AK4118_REG_RCV_STATUS1
- AK4118_REG_RXCHAN_STATUS0
- AK4118_REG_RXCHAN_STATUS1
- AK4118_REG_RXCHAN_STATUS2
- AK4118_REG_RXCHAN_STATUS3
- AK4118_REG_RXCHAN_STATUS4
- AK4118_REG_RXCHAN_STATUS5
- AK4118_REG_RX_DETECT
- AK4118_REG_STC_DAT_DETECT
- AK4118_REG_TXCHAN_STATUS0
- AK4118_REG_TXCHAN_STATUS1
- AK4118_REG_TXCHAN_STATUS2
- AK4118_REG_TXCHAN_STATUS3
- AK4118_REG_TXCHAN_STATUS4
- AK4118_REG_TXCHAN_STATUS5
- AK4358_ADDR
- AK4396_ACKS
- AK4396_ADDR
- AK4396_CCLK
- AK4396_CDTI
- AK4396_CONTROL_1
- AK4396_CONTROL_2
- AK4396_CONTROL_3
- AK4396_CSN
- AK4396_CTRL1
- AK4396_CTRL2
- AK4396_CTRL3
- AK4396_DCKB
- AK4396_DCKS
- AK4396_DEM_32
- AK4396_DEM_441
- AK4396_DEM_48
- AK4396_DEM_MASK
- AK4396_DEM_OFF
- AK4396_DFS_DOUBLE
- AK4396_DFS_MASK
- AK4396_DFS_NORMAL
- AK4396_DFS_QUAD
- AK4396_DIF_16_LSB
- AK4396_DIF_20_LSB
- AK4396_DIF_24_I2S
- AK4396_DIF_24_LSB
- AK4396_DIF_24_MSB
- AK4396_DIF_MASK
- AK4396_DSD
- AK4396_DSDM
- AK4396_DZFB
- AK4396_DZFE
- AK4396_DZFM
- AK4396_D_P_MASK
- AK4396_H_INCLUDED
- AK4396_LCH_ATT
- AK4396_PCM
- AK4396_RCH_ATT
- AK4396_RSTN
- AK4396_SLOW
- AK4396_SMUTE
- AK4396_WRITE
- AK4458_00_CONTROL1
- AK4458_01_CONTROL2
- AK4458_02_CONTROL3
- AK4458_03_LCHATT
- AK4458_04_RCHATT
- AK4458_05_CONTROL4
- AK4458_06_DSD1
- AK4458_07_CONTROL5
- AK4458_08_SOUND_CONTROL
- AK4458_09_DSD2
- AK4458_0A_CONTROL6
- AK4458_0B_CONTROL7
- AK4458_0C_CONTROL8
- AK4458_0D_CONTROL9
- AK4458_0E_CONTROL10
- AK4458_0F_L2CHATT
- AK4458_10_R2CHATT
- AK4458_11_L3CHATT
- AK4458_12_R3CHATT
- AK4458_13_L4CHATT
- AK4458_14_R4CHATT
- AK4458_ATS_MASK
- AK4458_ATS_SHIFT
- AK4458_DIF_16BIT_LSB
- AK4458_DIF_24BIT_I2S
- AK4458_DIF_32BIT_I2S
- AK4458_DIF_32BIT_LSB
- AK4458_DIF_32BIT_MSB
- AK4458_DIF_MASK
- AK4458_DIF_SHIFT
- AK4458_FORMATS
- AK4458_MODE_MASK
- AK4458_MODE_NORMAL
- AK4458_MODE_SHIFT
- AK4458_MODE_TDM128
- AK4458_MODE_TDM256
- AK4458_MODE_TDM512
- AK4458_RSTN
- AK4458_RSTN_MASK
- AK4458_SD_MASK
- AK4458_SLOW_MASK
- AK4458_SSLOW_MASK
- AK4531_AD_IN
- AK4531_CLOCK
- AK4531_DOUBLE
- AK4531_DOUBLE_TLV
- AK4531_INPUT_SW
- AK4531_LAUXA
- AK4531_LCD
- AK4531_LFM
- AK4531_LIN_SW1
- AK4531_LIN_SW2
- AK4531_LLINE
- AK4531_LMASTER
- AK4531_LVOICE
- AK4531_MIC
- AK4531_MIC_GAIN
- AK4531_MONO1
- AK4531_MONO2
- AK4531_MONO_OUT
- AK4531_OUT_SW1
- AK4531_OUT_SW2
- AK4531_RAUXA
- AK4531_RCD
- AK4531_RESET
- AK4531_RFM
- AK4531_RIN_SW1
- AK4531_RIN_SW2
- AK4531_RLINE
- AK4531_RMASTER
- AK4531_RVOICE
- AK4531_SINGLE
- AK4531_SINGLE_TLV
- AK4535_ALC1
- AK4535_ALC2
- AK4535_DAC
- AK4535_LATT
- AK4535_MIC
- AK4535_MODE1
- AK4535_MODE2
- AK4535_PGA
- AK4535_PM1
- AK4535_PM2
- AK4535_RATES
- AK4535_RATT
- AK4535_SIG1
- AK4535_SIG2
- AK4535_STATUS
- AK4535_TIMER
- AK4535_VOL
- AK4613_PCM_FMTBIT
- AK4613_PCM_RATE
- AK4620_ADDR
- AK4620_CKS0
- AK4620_CKS1
- AK4620_DEEMVOL_REG
- AK4620_DFS0
- AK4620_DFS1
- AK4620_DFS_REG
- AK4620_SMUTE
- AK4641_ALC1
- AK4641_ALC2
- AK4641_BTIF
- AK4641_DAC
- AK4641_EQHI
- AK4641_EQLO
- AK4641_EQMID
- AK4641_FORMATS
- AK4641_LATT
- AK4641_MIC
- AK4641_MODE1
- AK4641_MODE2
- AK4641_PGA
- AK4641_PM1
- AK4641_PM2
- AK4641_RATES
- AK4641_RATES_BT
- AK4641_RATT
- AK4641_SIG1
- AK4641_SIG2
- AK4641_STATUS
- AK4641_TIMER
- AK4641_VOL
- AK4671_AD_DA_POWER_MANAGEMENT
- AK4671_ALC_MODE_CONTROL
- AK4671_ALC_REFERENCE_SELECT
- AK4671_ALC_TIMER_SELECT
- AK4671_BCKP
- AK4671_DIF
- AK4671_DIF_DSP_MODE
- AK4671_DIF_I2S_MODE
- AK4671_DIF_MSB_MODE
- AK4671_DIGITAL_FILTER_SELECT
- AK4671_DIGITAL_FILTER_SELECT2
- AK4671_DIGITAL_MIXING_CONTROL
- AK4671_DIGITAL_MIXING_CONTROL2
- AK4671_DIGITAL_VOLUME_B_CONTROL
- AK4671_DIGITAL_VOLUME_C_CONTROL
- AK4671_E1_COEFFICIENT0
- AK4671_E1_COEFFICIENT1
- AK4671_E1_COEFFICIENT2
- AK4671_E1_COEFFICIENT3
- AK4671_E1_COEFFICIENT4
- AK4671_E1_COEFFICIENT5
- AK4671_E2_COEFFICIENT0
- AK4671_E2_COEFFICIENT1
- AK4671_E2_COEFFICIENT2
- AK4671_E2_COEFFICIENT3
- AK4671_E2_COEFFICIENT4
- AK4671_E2_COEFFICIENT5
- AK4671_E3_COEFFICIENT0
- AK4671_E3_COEFFICIENT1
- AK4671_E3_COEFFICIENT2
- AK4671_E3_COEFFICIENT3
- AK4671_E3_COEFFICIENT4
- AK4671_E3_COEFFICIENT5
- AK4671_E4_COEFFICIENT0
- AK4671_E4_COEFFICIENT1
- AK4671_E4_COEFFICIENT2
- AK4671_E4_COEFFICIENT3
- AK4671_E4_COEFFICIENT4
- AK4671_E4_COEFFICIENT5
- AK4671_E5_COEFFICIENT0
- AK4671_E5_COEFFICIENT1
- AK4671_E5_COEFFICIENT2
- AK4671_E5_COEFFICIENT3
- AK4671_E5_COEFFICIENT4
- AK4671_E5_COEFFICIENT5
- AK4671_EQ_COEFFICIENT0
- AK4671_EQ_COEFFICIENT1
- AK4671_EQ_COEFFICIENT2
- AK4671_EQ_COEFFICIENT3
- AK4671_EQ_COEFFICIENT4
- AK4671_EQ_COEFFICIENT5
- AK4671_EQ_CONTROL_250HZ_100HZ
- AK4671_EQ_CONTROL_3500HZ_1KHZ
- AK4671_EQ_CONTRO_10KHZ
- AK4671_FIL1_COEFFICIENT0
- AK4671_FIL1_COEFFICIENT1
- AK4671_FIL1_COEFFICIENT2
- AK4671_FIL1_COEFFICIENT3
- AK4671_FIL2_COEFFICIENT0
- AK4671_FIL2_COEFFICIENT1
- AK4671_FIL2_COEFFICIENT2
- AK4671_FIL2_COEFFICIENT3
- AK4671_FIL3_COEFFICIENT0
- AK4671_FIL3_COEFFICIENT1
- AK4671_FIL3_COEFFICIENT2
- AK4671_FIL3_COEFFICIENT3
- AK4671_FORMATS
- AK4671_FORMAT_SELECT
- AK4671_FS
- AK4671_FS_11_025KHZ
- AK4671_FS_12KHZ
- AK4671_FS_16KHZ
- AK4671_FS_22_05KHZ
- AK4671_FS_24KHZ
- AK4671_FS_32KHZ
- AK4671_FS_44_1KHZ
- AK4671_FS_48KHZ
- AK4671_FS_8KHZ
- AK4671_LCH_INPUT_VOLUME_CONTROL
- AK4671_LCH_OUTPUT_VOLUME_CONTROL
- AK4671_LOUT1_POWER_MANAGERMENT
- AK4671_LOUT1_SIGNAL_SELECT
- AK4671_LOUT2_POWER_MANAGERMENT
- AK4671_LOUT2_SIGNAL_SELECT
- AK4671_LOUT3_POWER_MANAGERMENT
- AK4671_LOUT3_SIGNAL_SELECT
- AK4671_MIC_AMP_GAIN
- AK4671_MIC_SIGNAL_SELECT
- AK4671_MIXING_POWER_MANAGEMENT0
- AK4671_MIXING_POWER_MANAGEMENT1
- AK4671_MODE_CONTROL1
- AK4671_MODE_CONTROL2
- AK4671_MSBS
- AK4671_MUTEN
- AK4671_M_S
- AK4671_OUTPUT_VOLUME_CONTROL
- AK4671_PCM_IF_CONTROL0
- AK4671_PCM_IF_CONTROL1
- AK4671_PCM_IF_CONTROL2
- AK4671_PLL
- AK4671_PLL_11_2896MHZ
- AK4671_PLL_12MHZ
- AK4671_PLL_12_288MHZ
- AK4671_PLL_13MHZ
- AK4671_PLL_13_5MHZ
- AK4671_PLL_19_2MHZ
- AK4671_PLL_24MHZ
- AK4671_PLL_26MHZ
- AK4671_PLL_27MHZ
- AK4671_PLL_MODE_SELECT0
- AK4671_PLL_MODE_SELECT1
- AK4671_PMPLL
- AK4671_PMVCM
- AK4671_RATES
- AK4671_RCH_INPUT_VOLUME_CONTROL
- AK4671_RCH_OUTPUT_VOLUME_CONTROL
- AK4671_ROUT1_SIGNAL_SELECT
- AK4671_ROUT2_SIGNAL_SELECT
- AK4671_ROUT3_SIGNAL_SELECT
- AK4671_SAR_ADC_CONTROL
- AK4671_SDOD
- AK4671_SIDETONE_A_CONTROL
- AK4671_SIDETONE_VOLUME_CONTROL
- AK4XXX_IMAGE_SIZE
- AK4XXX_MAX_CHIPS
- AK5365_NUM_INPUTS
- AK5558_00_POWER_MANAGEMENT1
- AK5558_01_POWER_MANAGEMENT2
- AK5558_02_CONTROL1
- AK5558_03_CONTROL2
- AK5558_04_CONTROL3
- AK5558_05_DSD
- AK5558_BITS
- AK5558_CKS
- AK5558_CKS_1024FS_16KHZ
- AK5558_CKS_128FS_192KHZ
- AK5558_CKS_192FS_192KHZ
- AK5558_CKS_256FS_48KHZ
- AK5558_CKS_256FS_96KHZ
- AK5558_CKS_32FS_768KHZ
- AK5558_CKS_384FS_48KHZ
- AK5558_CKS_384FS_96KHZ
- AK5558_CKS_48FS_768KHZ
- AK5558_CKS_512FS_48KHZ
- AK5558_CKS_64FS_384KHZ
- AK5558_CKS_64FS_768KHZ
- AK5558_CKS_768FS_48KHZ
- AK5558_CKS_96FS_384KHZ
- AK5558_CKS_AUTO
- AK5558_DIF
- AK5558_DIF_24BIT_MODE
- AK5558_DIF_32BIT_MODE
- AK5558_DIF_I2S_MODE
- AK5558_DIF_MSB_MODE
- AK5558_FORMATS
- AK5558_MODE_BITS
- AK5558_MODE_NORMAL
- AK5558_MODE_TDM128
- AK5558_MODE_TDM256
- AK5558_MODE_TDM512
- AK7375_CTRL_DELAY_US
- AK7375_CTRL_STEPS
- AK7375_FOCUS_STEPS
- AK7375_MAX_FOCUS_POS
- AK7375_MODE_ACTIVE
- AK7375_MODE_STANDBY
- AK7375_REG_CONT
- AK7375_REG_POSITION
- AK881X_COMPONENT
- AK881X_DAC_MODE
- AK881X_DEVICE_ID
- AK881X_DEVICE_REVISION
- AK881X_FIELD
- AK881X_H
- AK881X_IF_MODE_BT656
- AK881X_IF_MODE_MASK
- AK881X_IF_MODE_MASTER
- AK881X_IF_MODE_SLAVE
- AK881X_INTERFACE_MODE
- AK881X_STATUS
- AK881X_VIDEO_PROCESS1
- AK881X_VIDEO_PROCESS2
- AK881X_VIDEO_PROCESS3
- AK8963
- AK8974_ACTIVATE_DELAY
- AK8974_AUTOSUSPEND_DELAY
- AK8974_AXIS_CHANNEL
- AK8974_CTRL1
- AK8974_CTRL1_FORCE_EN
- AK8974_CTRL1_MODE2
- AK8974_CTRL1_POWER
- AK8974_CTRL1_RATE
- AK8974_CTRL2
- AK8974_CTRL2_DRDY_EN
- AK8974_CTRL2_DRDY_POL
- AK8974_CTRL2_INT_EN
- AK8974_CTRL2_RESDEF
- AK8974_CTRL3
- AK8974_CTRL3_FORCE
- AK8974_CTRL3_RESDEF
- AK8974_CTRL3_RESET
- AK8974_CTRL3_SELFTEST
- AK8974_DATA_X
- AK8974_DATA_Y
- AK8974_DATA_Z
- AK8974_INFO
- AK8974_INT_CLEAR
- AK8974_INT_CTRL
- AK8974_INT_CTRL_POL
- AK8974_INT_CTRL_PULSE
- AK8974_INT_CTRL_RESDEF
- AK8974_INT_CTRL_XEN
- AK8974_INT_CTRL_XYZEN
- AK8974_INT_CTRL_YEN
- AK8974_INT_CTRL_ZEN
- AK8974_INT_RANGE
- AK8974_INT_SRC
- AK8974_INT_THRES
- AK8974_INT_X_HIGH
- AK8974_INT_X_LOW
- AK8974_INT_Y_HIGH
- AK8974_INT_Y_LOW
- AK8974_INT_Z_HIGH
- AK8974_INT_Z_LOW
- AK8974_MAX_RANGE
- AK8974_MEASTIME
- AK8974_OFFSET_X
- AK8974_OFFSET_Y
- AK8974_OFFSET_Z
- AK8974_POWERON_DELAY
- AK8974_PRESET
- AK8974_PWR_OFF
- AK8974_PWR_ON
- AK8974_SELFTEST
- AK8974_SELFTEST_DELAY
- AK8974_SELFTEST_IDLE
- AK8974_SELFTEST_OK
- AK8974_STATUS
- AK8974_STATUS_DRDY
- AK8974_STATUS_INT
- AK8974_STATUS_OVERRUN
- AK8974_TEMP
- AK8974_WHOAMI
- AK8974_WHOAMI_VALUE_AK8974
- AK8974_WHOAMI_VALUE_AMI305
- AK8974_WHOAMI_VALUE_AMI306
- AK8975
- AK8975_CHANNEL
- AK8975_CONVERSION_DONE_POLL_TIME
- AK8975_DATA_READY_TIMEOUT
- AK8975_DEVICE_ID
- AK8975_MAX_CONVERSION_TIMEOUT
- AK8975_MAX_REGS
- AK8975_REG_ASAX
- AK8975_REG_ASAY
- AK8975_REG_ASAZ
- AK8975_REG_ASTC
- AK8975_REG_CNTL
- AK8975_REG_CNTL_MODE_FUSE_ROM
- AK8975_REG_CNTL_MODE_MASK
- AK8975_REG_CNTL_MODE_ONCE
- AK8975_REG_CNTL_MODE_POWER_DOWN
- AK8975_REG_CNTL_MODE_SELF_TEST
- AK8975_REG_CNTL_MODE_SHIFT
- AK8975_REG_HXH
- AK8975_REG_HXL
- AK8975_REG_HYH
- AK8975_REG_HYL
- AK8975_REG_HZH
- AK8975_REG_HZL
- AK8975_REG_I2CDIS
- AK8975_REG_INFO
- AK8975_REG_RSVC
- AK8975_REG_ST1
- AK8975_REG_ST1_DRDY_MASK
- AK8975_REG_ST1_DRDY_SHIFT
- AK8975_REG_ST2
- AK8975_REG_ST2_DERR_MASK
- AK8975_REG_ST2_DERR_SHIFT
- AK8975_REG_ST2_HOFL_MASK
- AK8975_REG_ST2_HOFL_SHIFT
- AK8975_REG_TS1
- AK8975_REG_TS2
- AK8975_REG_WIA
- AKITA_GPIO_AKIN_PULLUP
- AKITA_GPIO_BACKLIGHT_CONT
- AKITA_GPIO_BACKLIGHT_ON
- AKITA_GPIO_IR_ON
- AKITA_GPIO_MIC_BIAS
- AKITA_GPIO_RESERVED_0
- AKITA_GPIO_RESERVED_1
- AKITA_GPIO_RESERVED_7
- AKITA_IOEXP_GPIO_BASE
- AKM_CLOCK_INF_55K_CMD
- AKM_CLOCK_SUP_55K_CMD
- AKM_CODEC_CLOCK_FORMAT_CMD
- AKM_CODEC_LEFT_LEVEL_CMD
- AKM_CODEC_MUTE_CMD
- AKM_CODEC_POWER_CONTROL_CMD
- AKM_CODEC_RESET_OFF_CMD
- AKM_CODEC_RESET_ON_CMD
- AKM_CODEC_RIGHT_LEVEL_CMD
- AKM_CODEC_UNMUTE_CMD
- AKM_LEFT_LEVEL_CMD
- AKM_MUTE_CMD
- AKM_POWER_CONTROL_CMD
- AKM_RESET_OFF_CMD
- AKM_RESET_ON_CMD
- AKM_RIGHT_LEVEL_CMD
- AKM_UNMUTE_CMD
- AK_COMPOSE
- AK_CONTROL
- AK_DAC
- AK_GET_ADDR
- AK_GET_CHIP
- AK_GET_INVERT
- AK_GET_IPGA
- AK_GET_MASK
- AK_GET_NEEDSMSB
- AK_GET_SHIFT
- AK_GET_VOL_CVT
- AK_INVERT
- AK_IPGA
- AK_MAX_TYPE
- AK_NEEDSMSB
- AK_VOL_CVT
- AL
- AL2210_RF
- AL2230S_RF
- AL2230_PWR_IDX_LEN
- AL2230_RF
- AL3320A_CONFIG_DISABLE
- AL3320A_CONFIG_ENABLE
- AL3320A_DEFAULT_MEAN_TIME
- AL3320A_DEFAULT_WAIT_TIME
- AL3320A_DRV_NAME
- AL3320A_GAIN_MASK
- AL3320A_GAIN_SHIFT
- AL3320A_RANGE_1
- AL3320A_RANGE_2
- AL3320A_RANGE_3
- AL3320A_RANGE_4
- AL3320A_REG_ADUMMY
- AL3320A_REG_CONFIG
- AL3320A_REG_CONFIG_RANGE
- AL3320A_REG_DATA_LOW
- AL3320A_REG_HIGH_THRESH_HIGH
- AL3320A_REG_HIGH_THRESH_LOW
- AL3320A_REG_INT
- AL3320A_REG_LOW_THRESH_HIGH
- AL3320A_REG_LOW_THRESH_LOW
- AL3320A_REG_MEAN_TIME
- AL3320A_REG_PERSIST
- AL3320A_REG_STATUS
- AL3320A_REG_WAIT
- AL3320A_SCALE_AVAILABLE
- AL5_DCACHE_ADDR_OFFSET_LSB
- AL5_DCACHE_ADDR_OFFSET_MSB
- AL5_ICACHE_ADDR_OFFSET_LSB
- AL5_ICACHE_ADDR_OFFSET_MSB
- AL5_ITC_CPU_IRQ_CLR
- AL5_ITC_CPU_IRQ_MSK
- AL5_ITC_CPU_IRQ_STA
- AL5_ITC_CPU_IRQ_STA_TRIGGERED
- AL5_MCU_INTERRUPT
- AL5_MCU_RESET
- AL5_MCU_RESET_MODE
- AL5_MCU_RESET_MODE_HALT
- AL5_MCU_RESET_MODE_SLEEP
- AL5_MCU_RESET_REGS
- AL5_MCU_RESET_SOFT
- AL5_MCU_STA
- AL5_MCU_STA_SLEEP
- AL5_MCU_WAKEUP
- AL7230B_RF
- AL7230_PWR_IDX_LEN
- ALARM
- ALARM0_IRQ
- ALARM0_STATUS
- ALARM1
- ALARM1_IRQ
- ALARM1_STATUS
- ALARM2
- ALARMS_FROM_REG
- ALARMTIMER_NORESTART
- ALARMTIMER_RESTART
- ALARMTIMER_STATE_ENQUEUED
- ALARMTIMER_STATE_INACTIVE
- ALARM_1SEC
- ALARM_ALARM_COUNT
- ALARM_BOOTTIME
- ALARM_BOOTTIME_FREEZER
- ALARM_CFG
- ALARM_CNT_THRESHOLD
- ALARM_CTRL_FORCE_ENABLE
- ALARM_CTRL_RTSACS
- ALARM_DATE_REG
- ALARM_DAY_BIT
- ALARM_DAY_MASK
- ALARM_DAY_S
- ALARM_DCDC1
- ALARM_DCDC2
- ALARM_DCDC3
- ALARM_DELTA
- ALARM_DISABLED
- ALARM_EN
- ALARM_ENABLE_MASK
- ALARM_ENABLE_SHIFT
- ALARM_FILTER
- ALARM_HOUR_BIT
- ALARM_INTERVAL_SECS
- ALARM_INT_STATUS
- ALARM_IRQ_FLAG
- ALARM_LCD
- ALARM_LDO1
- ALARM_LDO2
- ALARM_MIN_BIT
- ALARM_NRST
- ALARM_NUMTYPE
- ALARM_OFFSET
- ALARM_POWERUP
- ALARM_REALTIME
- ALARM_REALTIME_FREEZER
- ALARM_REG
- ALARM_REGS_OFFSET
- ALARM_SEC_BIT
- ALARM_STATS
- ALARM_STATUS
- ALARM_TEMP_HOT
- ALARM_TEMP_WARM
- ALARM_THRESHOLD_SET
- ALARM_THROTTLE_PERIOD
- ALARM_TIME_REG
- ALARM_USB_ALARM
- ALARM_USB_WARN
- ALARM_WAKEUP
- ALATCH_DIS_BIT32
- ALATCH_DIS_DMA
- ALATCH_DIS_INT
- ALATCH_DIS_TERM
- ALATCH_DMA_IN
- ALATCH_DMA_OUT
- ALATCH_ENA_BIT32
- ALATCH_ENA_DMA
- ALATCH_ENA_INT
- ALATCH_ENA_TERM
- ALAUDA_ACK_SM_MEDIA_CHANGE
- ALAUDA_ACK_XD_MEDIA_CHANGE
- ALAUDA_BULK_CMD
- ALAUDA_BULK_ERASE_BLOCK
- ALAUDA_BULK_GET_REDU_DATA
- ALAUDA_BULK_GET_STATUS2
- ALAUDA_BULK_READ_BLOCK
- ALAUDA_BULK_RESET_MEDIA
- ALAUDA_BULK_WRITE_BLOCK
- ALAUDA_GET_SM_MEDIA_SIG
- ALAUDA_GET_SM_MEDIA_STATUS
- ALAUDA_GET_XD_MEDIA_SIG
- ALAUDA_GET_XD_MEDIA_STATUS
- ALAUDA_PORT_SM
- ALAUDA_PORT_XD
- ALAUDA_STATUS_ERROR
- ALAUDA_STATUS_READY
- ALB
- ALB_TIMER_TICKS_PER_SEC
- ALC
- ALC1220_FIXUP_CLEVO_P950
- ALC1220_FIXUP_CLEVO_PB51ED
- ALC1220_FIXUP_CLEVO_PB51ED_PINS
- ALC1220_FIXUP_GB_DUAL_CODECS
- ALC1220_VB_DESKTOP
- ALC221_FIXUP_HP_FRONT_MIC
- ALC221_FIXUP_HP_HEADSET_MIC
- ALC221_FIXUP_HP_MIC_NO_PRESENCE
- ALC225_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC225_FIXUP_DELL_WYSE_AIO_MIC_NO_PRESENCE
- ALC225_FIXUP_DELL_WYSE_MIC_NO_PRESENCE
- ALC225_FIXUP_DISABLE_MIC_VREF
- ALC225_FIXUP_HEADSET_JACK
- ALC225_FIXUP_S3_POP_NOISE
- ALC225_FIXUP_WYSE_AUTO_MUTE
- ALC225_FIXUP_WYSE_DISABLE_MIC_VREF
- ALC225_STANDARD_PINS
- ALC233_FIXUP_ACER_HEADSET_MIC
- ALC233_FIXUP_ASUS_MIC_NO_PRESENCE
- ALC233_FIXUP_EAPD_COEF_AND_MIC_NO_PRESENCE
- ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY
- ALC233_FIXUP_LENOVO_MULTI_CODECS
- ALC236_FIXUP_HP_MUTE_LED
- ALC255_FIXUP_ACER_HEADSET_MIC
- ALC255_FIXUP_ACER_MIC_NO_PRESENCE
- ALC255_FIXUP_ASUS_MIC_NO_PRESENCE
- ALC255_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC255_FIXUP_DELL2_MIC_NO_PRESENCE
- ALC255_FIXUP_DELL_HEADSET_MIC
- ALC255_FIXUP_DELL_SPK_NOISE
- ALC255_FIXUP_DUMMY_LINEOUT_VERB
- ALC255_FIXUP_HEADSET_MODE
- ALC255_FIXUP_HEADSET_MODE_NO_HP_MIC
- ALC255_FIXUP_LIFEBOOK_U7x7_HEADSET_MIC
- ALC255_FIXUP_MIC_MUTE_LED
- ALC256_FIXUP_ASUS_AIO_GPIO2
- ALC256_FIXUP_ASUS_HEADSET_MIC
- ALC256_FIXUP_ASUS_HEADSET_MODE
- ALC256_FIXUP_ASUS_MIC
- ALC256_FIXUP_ASUS_MIC_NO_PRESENCE
- ALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER
- ALC256_FIXUP_HUAWEI_MACH_WX9_PINS
- ALC256_FIXUP_MEDION_HEADSET_NO_PRESENCE
- ALC256_STANDARD_PINS
- ALC260_FIXUP_COEF
- ALC260_FIXUP_FSC_S7020
- ALC260_FIXUP_FSC_S7020_JWSE
- ALC260_FIXUP_GPIO1
- ALC260_FIXUP_GPIO1_TOGGLE
- ALC260_FIXUP_HP_B1900
- ALC260_FIXUP_HP_DC5750
- ALC260_FIXUP_HP_PIN_0F
- ALC260_FIXUP_KN1
- ALC260_FIXUP_REPLACER
- ALC260_FIXUP_VAIO_PINS
- ALC262_FIXUP_BENQ
- ALC262_FIXUP_BENQ_T31
- ALC262_FIXUP_FSC_H270
- ALC262_FIXUP_FSC_S7110
- ALC262_FIXUP_HP_Z200
- ALC262_FIXUP_INTEL_BAYLEYBAY
- ALC262_FIXUP_INV_DMIC
- ALC262_FIXUP_LENOVO_3000
- ALC262_FIXUP_TYAN
- ALC268_FIXUP_HP_EAPD
- ALC268_FIXUP_INV_DMIC
- ALC268_FIXUP_SPDIF
- ALC269VB_FIXUP_AMIC
- ALC269VB_FIXUP_ASUS_ZENBOOK
- ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A
- ALC269VB_FIXUP_DMIC
- ALC269VB_FIXUP_ORDISSIMO_EVE2
- ALC269_FIXUP_ACER_AC700
- ALC269_FIXUP_AMIC
- ALC269_FIXUP_ASPIRE_HEADSET_MIC
- ALC269_FIXUP_ASUS_G73JW
- ALC269_FIXUP_ASUS_X101
- ALC269_FIXUP_ASUS_X101_FUNC
- ALC269_FIXUP_ASUS_X101_VERB
- ALC269_FIXUP_ATIV_BOOK_8
- ALC269_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC269_FIXUP_DELL2_MIC_NO_PRESENCE
- ALC269_FIXUP_DELL3_MIC_NO_PRESENCE
- ALC269_FIXUP_DELL4_MIC_NO_PRESENCE
- ALC269_FIXUP_DELL_M101Z
- ALC269_FIXUP_DMIC
- ALC269_FIXUP_DMIC_THINKPAD_ACPI
- ALC269_FIXUP_HEADSET_MIC
- ALC269_FIXUP_HEADSET_MODE
- ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC
- ALC269_FIXUP_HP_DOCK_GPIO_MIC1_LED
- ALC269_FIXUP_HP_GPIO_LED
- ALC269_FIXUP_HP_GPIO_MIC1_LED
- ALC269_FIXUP_HP_LINE1_MIC1_LED
- ALC269_FIXUP_HP_MUTE_LED
- ALC269_FIXUP_HP_MUTE_LED_MIC1
- ALC269_FIXUP_HP_MUTE_LED_MIC2
- ALC269_FIXUP_HP_MUTE_LED_MIC3
- ALC269_FIXUP_INV_DMIC
- ALC269_FIXUP_LENOVO_DOCK
- ALC269_FIXUP_LENOVO_DOCK_LIMIT_BOOST
- ALC269_FIXUP_LENOVO_EAPD
- ALC269_FIXUP_LIFEBOOK
- ALC269_FIXUP_LIFEBOOK_EXTMIC
- ALC269_FIXUP_LIFEBOOK_HP_PIN
- ALC269_FIXUP_LIFEBOOK_NO_HP_TO_LINEOUT
- ALC269_FIXUP_LIMIT_INT_MIC_BOOST
- ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED
- ALC269_FIXUP_NO_SHUTUP
- ALC269_FIXUP_PCM_44K
- ALC269_FIXUP_PINCFG_NO_HP_TO_LINEOUT
- ALC269_FIXUP_QUANTA_MUTE
- ALC269_FIXUP_SKU_IGNORE
- ALC269_FIXUP_SONY_VAIO
- ALC269_FIXUP_STEREO_DMIC
- ALC269_FIXUP_THINKPAD_ACPI
- ALC269_TYPE_ALC215
- ALC269_TYPE_ALC225
- ALC269_TYPE_ALC255
- ALC269_TYPE_ALC256
- ALC269_TYPE_ALC257
- ALC269_TYPE_ALC269VA
- ALC269_TYPE_ALC269VB
- ALC269_TYPE_ALC269VC
- ALC269_TYPE_ALC269VD
- ALC269_TYPE_ALC280
- ALC269_TYPE_ALC282
- ALC269_TYPE_ALC283
- ALC269_TYPE_ALC284
- ALC269_TYPE_ALC286
- ALC269_TYPE_ALC293
- ALC269_TYPE_ALC294
- ALC269_TYPE_ALC298
- ALC269_TYPE_ALC300
- ALC269_TYPE_ALC623
- ALC269_TYPE_ALC700
- ALC271_FIXUP_AMIC_MIC2
- ALC271_FIXUP_DMIC
- ALC271_FIXUP_HP_GATE_MIC_JACK
- ALC271_FIXUP_HP_GATE_MIC_JACK_E1_572
- ALC272_FIXUP_MARIO
- ALC274_FIXUP_DELL_AIO_LINEOUT_VERB
- ALC274_FIXUP_DELL_BIND_DACS
- ALC275_FIXUP_DELL_XPS
- ALC275_FIXUP_SONY_DISABLE_AAMIX
- ALC275_FIXUP_SONY_HWEQ
- ALC275_FIXUP_SONY_VAIO_GPIO2
- ALC280_FIXUP_HP_9480M
- ALC280_FIXUP_HP_DOCK_PINS
- ALC280_FIXUP_HP_GPIO2_MIC_HOTKEY
- ALC280_FIXUP_HP_GPIO4
- ALC280_FIXUP_HP_HEADSET_MIC
- ALC282_FIXUP_ASPIRE_V5_PINS
- ALC282_FIXUP_ASUS_TX300
- ALC282_STANDARD_PINS
- ALC283_FIXUP_CHROME_BOOK
- ALC283_FIXUP_HEADSET_MIC
- ALC283_FIXUP_INT_MIC
- ALC283_FIXUP_SENSE_COMBO_JACK
- ALC285_FIXUP_HP_GPIO_LED
- ALC285_FIXUP_HP_MUTE_LED
- ALC285_FIXUP_LENOVO_HEADPHONE_NOISE
- ALC285_FIXUP_LENOVO_PC_BEEP_IN_NOISE
- ALC285_FIXUP_SPEAKER2_TO_DAC1
- ALC285_FIXUP_THINKPAD_HEADSET_JACK
- ALC286_FIXUP_ACER_AIO_HEADSET_MIC
- ALC286_FIXUP_ACER_AIO_MIC_NO_PRESENCE
- ALC286_FIXUP_HP_GPIO_LED
- ALC286_FIXUP_SONY_MIC_NO_PRESENCE
- ALC288_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC288_FIXUP_DELL_HEADSET_MODE
- ALC288_FIXUP_DELL_XPS_13
- ALC288_FIXUP_DISABLE_AAMIX
- ALC289_FIXUP_DELL_SPK2
- ALC289_FIXUP_DUAL_SPK
- ALC290_FIXUP_MONO_SPEAKERS
- ALC290_FIXUP_MONO_SPEAKERS_HSJACK
- ALC290_FIXUP_SUBWOOFER
- ALC290_FIXUP_SUBWOOFER_HSJACK
- ALC290_STANDARD_PINS
- ALC292_FIXUP_DELL_E7X
- ALC292_FIXUP_DELL_E7X_AAMIX
- ALC292_FIXUP_DISABLE_AAMIX
- ALC292_FIXUP_TPT440
- ALC292_FIXUP_TPT440_DOCK
- ALC292_FIXUP_TPT460
- ALC292_STANDARD_PINS
- ALC293_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC293_FIXUP_DISABLE_AAMIX_MULTIJACK
- ALC293_FIXUP_LENOVO_SPK_NOISE
- ALC293_FIXUP_SYSTEM76_MIC_NO_PRESENCE
- ALC294_FIXUP_ASUS_COEF_1B
- ALC294_FIXUP_ASUS_DUAL_SPK
- ALC294_FIXUP_ASUS_HEADSET_MIC
- ALC294_FIXUP_ASUS_HPE
- ALC294_FIXUP_ASUS_MIC
- ALC294_FIXUP_ASUS_SPK
- ALC294_FIXUP_LENOVO_MIC_LOCATION
- ALC294_FIXUP_SPK2_TO_DAC1
- ALC295_FIXUP_ASUS_MIC_NO_PRESENCE
- ALC295_FIXUP_CHROME_BOOK
- ALC295_FIXUP_DISABLE_DAC3
- ALC295_FIXUP_HP_AUTO_MUTE
- ALC295_FIXUP_HP_X360
- ALC295_STANDARD_PINS
- ALC298_FIXUP_ALIENWARE_MIC_NO_PRESENCE
- ALC298_FIXUP_DELL1_MIC_NO_PRESENCE
- ALC298_FIXUP_DELL_AIO_MIC_NO_PRESENCE
- ALC298_FIXUP_HUAWEI_MBX_STEREO
- ALC298_FIXUP_SAMSUNG_HEADPHONE_VERY_QUIET
- ALC298_FIXUP_SPK_VOLUME
- ALC298_FIXUP_TPT470_DOCK
- ALC298_FIXUP_TPT470_DOCK_FIX
- ALC298_STANDARD_PINS
- ALC299_FIXUP_PREDATOR_SPK
- ALC5623_ADC_REC_GAIN
- ALC5623_ADC_REC_MIXER
- ALC5623_ADD1_POWER_EN
- ALC5623_ADD1_POWER_EN_5622
- ALC5623_ADD2_POWER_EN
- ALC5623_ADD3_POWER_EN
- ALC5623_ADD_CTRL_REG
- ALC5623_AUXIN_VOL
- ALC5623_AVC_CTRL
- ALC5623_COMPANDING_CTRL
- ALC5623_DAI_ADC_DATA_L_R_SWAP
- ALC5623_DAI_CONTROL
- ALC5623_DAI_DAC_DATA_L_R_SWAP
- ALC5623_DAI_I2S_DF_I2S
- ALC5623_DAI_I2S_DF_LEFT
- ALC5623_DAI_I2S_DF_PCM
- ALC5623_DAI_I2S_DF_RIGHT
- ALC5623_DAI_I2S_DL_16
- ALC5623_DAI_I2S_DL_20
- ALC5623_DAI_I2S_DL_24
- ALC5623_DAI_I2S_DL_32
- ALC5623_DAI_I2S_DL_MASK
- ALC5623_DAI_I2S_PCM_MODE
- ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL
- ALC5623_DAI_SDP_MASTER_MODE
- ALC5623_DAI_SDP_SLAVE_MODE
- ALC5623_EQ_CTRL
- ALC5623_EQ_MODE_ENABLE
- ALC5623_FORMATS
- ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV1
- ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV2
- ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV4
- ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV8
- ALC5623_GBL_CLK_PLL_PRE_DIV1
- ALC5623_GBL_CLK_PLL_PRE_DIV2
- ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK
- ALC5623_GBL_CLK_PLL_SOUR_SEL_MCLK
- ALC5623_GBL_CLK_SYS_SOUR_SEL_MCLK
- ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL
- ALC5623_GLOBAL_CLK_CTRL_REG
- ALC5623_GPIO_OUTPUT_PIN_CTRL
- ALC5623_GPIO_PIN_CONFIG
- ALC5623_GPIO_PIN_POLARITY
- ALC5623_GPIO_PIN_SHARING
- ALC5623_GPIO_PIN_STATUS
- ALC5623_GPIO_PIN_STICKY
- ALC5623_GPIO_PIN_WAKEUP
- ALC5623_HID_CTRL_DATA
- ALC5623_HID_CTRL_INDEX
- ALC5623_HP_OUT_VOL
- ALC5623_JACK_DET_CTRL
- ALC5623_LINE_IN_VOL
- ALC5623_MIC_CTRL
- ALC5623_MIC_ROUTING_CTRL
- ALC5623_MIC_VOL
- ALC5623_MISC_AUXOUT_DEPOP_MODE1_EN
- ALC5623_MISC_AUXOUT_DEPOP_MODE2_EN
- ALC5623_MISC_AUXOUT_DEPOP_MODE3_EN
- ALC5623_MISC_CTRL
- ALC5623_MISC_DISABLE_FAST_VREG
- ALC5623_MISC_HP_DEPOP_MODE1_EN
- ALC5623_MISC_HP_DEPOP_MODE2_EN
- ALC5623_MISC_HP_DEPOP_MODE3_EN
- ALC5623_MISC_IRQOUT_INV_CTRL
- ALC5623_MISC_M_DAC_L_INPUT
- ALC5623_MISC_M_DAC_R_INPUT
- ALC5623_MISC_SPK_CLASS_AB_OC_DET
- ALC5623_MISC_SPK_CLASS_AB_OC_PD
- ALC5623_MONO_AUX_OUT_VOL
- ALC5623_OUTPUT_MIXER_CTRL
- ALC5623_OVER_CURR_STATUS
- ALC5623_PLL_CTRL
- ALC5623_PLL_CTRL_K_VAL
- ALC5623_PLL_CTRL_M_VAL
- ALC5623_PLL_CTRL_N_VAL
- ALC5623_PLL_FR_BCK
- ALC5623_PLL_FR_MCLK
- ALC5623_PSEDUEO_SPATIAL_CTRL
- ALC5623_PWR_ADD1_AUX_OUT_AMP
- ALC5623_PWR_ADD1_AUX_OUT_ENH_AMP
- ALC5623_PWR_ADD1_DEPOP_BUF_AUX
- ALC5623_PWR_ADD1_DEPOP_BUF_HP
- ALC5623_PWR_ADD1_HP_OUT_AMP
- ALC5623_PWR_ADD1_HP_OUT_ENH_AMP
- ALC5623_PWR_ADD1_MAIN_I2S_EN
- ALC5623_PWR_ADD1_MIC1_BIAS_EN
- ALC5623_PWR_ADD1_SHORT_CURR_DET_EN
- ALC5623_PWR_ADD1_SOFTGEN_EN
- ALC5623_PWR_ADD1_ZC_DET_PD_EN
- ALC5623_PWR_ADD2_CLASS_AB
- ALC5623_PWR_ADD2_CLASS_D
- ALC5623_PWR_ADD2_DAC_REF_CIR
- ALC5623_PWR_ADD2_LINEOUT
- ALC5623_PWR_ADD2_L_ADC_CLK_GAIN
- ALC5623_PWR_ADD2_L_ADC_REC_MIXER
- ALC5623_PWR_ADD2_L_DAC_CLK
- ALC5623_PWR_ADD2_L_HP_MIXER
- ALC5623_PWR_ADD2_MONO_MIXER
- ALC5623_PWR_ADD2_PLL
- ALC5623_PWR_ADD2_R_ADC_CLK_GAIN
- ALC5623_PWR_ADD2_R_ADC_REC_MIXER
- ALC5623_PWR_ADD2_R_DAC_CLK
- ALC5623_PWR_ADD2_R_HP_MIXER
- ALC5623_PWR_ADD2_SPK_MIXER
- ALC5623_PWR_ADD2_VREF
- ALC5623_PWR_ADD3_AUXIN_L_VOL
- ALC5623_PWR_ADD3_AUXIN_R_VOL
- ALC5623_PWR_ADD3_AUXOUT_L_VOL_AMP
- ALC5623_PWR_ADD3_AUXOUT_R_VOL_AMP
- ALC5623_PWR_ADD3_HP_L_OUT_VOL
- ALC5623_PWR_ADD3_HP_R_OUT_VOL
- ALC5623_PWR_ADD3_LINEIN_L_VOL
- ALC5623_PWR_ADD3_LINEIN_R_VOL
- ALC5623_PWR_ADD3_MAIN_BIAS
- ALC5623_PWR_ADD3_MIC1_BOOST_AD
- ALC5623_PWR_ADD3_MIC1_FUN_CTRL
- ALC5623_PWR_ADD3_MIC2_BOOST_AD
- ALC5623_PWR_ADD3_MIC2_FUN_CTRL
- ALC5623_PWR_ADD3_SPK_OUT
- ALC5623_PWR_MANAG_ADD1
- ALC5623_PWR_MANAG_ADD2
- ALC5623_PWR_MANAG_ADD3
- ALC5623_RESET
- ALC5623_SOFT_VOL_CTRL_TIME
- ALC5623_SPK_OUT_VOL
- ALC5623_STEREO_AD_DA_CLK_CTRL
- ALC5623_STEREO_DAC_VOL
- ALC5623_VENDOR_ID1
- ALC5623_VENDOR_ID2
- ALC5632_ADC_REC_AUX
- ALC5632_ADC_REC_GAIN
- ALC5632_ADC_REC_GAIN_BASE
- ALC5632_ADC_REC_GAIN_RANGE
- ALC5632_ADC_REC_GAIN_STEP
- ALC5632_ADC_REC_HP
- ALC5632_ADC_REC_LINE_IN
- ALC5632_ADC_REC_MIC1
- ALC5632_ADC_REC_MIC2
- ALC5632_ADC_REC_MIXER
- ALC5632_ADC_REC_MONOMIX
- ALC5632_ADC_REC_SPK
- ALC5632_ADD1_POWER_EN
- ALC5632_ADD2_POWER_EN
- ALC5632_ADD3_POWER_EN
- ALC5632_AUX_OUT_VOL
- ALC5632_DAC_CLK_CTRL1
- ALC5632_DAC_CLK_CTRL2
- ALC5632_DAC_CLK_CTRL2_DIV1_2
- ALC5632_DAC_FUNC_SELECT
- ALC5632_DAI_CONTROL
- ALC5632_DAI_CONTROL2
- ALC5632_DAI_HPF_CLK_CTRL
- ALC5632_DAI_I2S_DF_I2S
- ALC5632_DAI_I2S_DF_LEFT
- ALC5632_DAI_I2S_DF_MASK
- ALC5632_DAI_I2S_DF_PCM_A
- ALC5632_DAI_I2S_DF_PCM_B
- ALC5632_DAI_I2S_DL_16
- ALC5632_DAI_I2S_DL_20
- ALC5632_DAI_I2S_DL_24
- ALC5632_DAI_I2S_DL_8
- ALC5632_DAI_I2S_DL_MASK
- ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL
- ALC5632_DAI_MAIN_I2S_LRCK_INV
- ALC5632_DAI_MAIN_I2S_SYSCLK_SEL
- ALC5632_DAI_SADLRCK_MODE
- ALC5632_DAI_SDP_MASTER_MODE
- ALC5632_DAI_SDP_SLAVE_MODE
- ALC5632_DAI_VOICE_DF_I2S
- ALC5632_DAI_VOICE_DF_LEFT
- ALC5632_DAI_VOICE_DF_MASK
- ALC5632_DAI_VOICE_DF_PCM_A
- ALC5632_DAI_VOICE_DF_PCM_B
- ALC5632_DAI_VOICE_DL_16
- ALC5632_DAI_VOICE_DL_20
- ALC5632_DAI_VOICE_DL_24
- ALC5632_DAI_VOICE_DL_8
- ALC5632_DAI_VOICE_DL_MASK
- ALC5632_DAI_VOICE_I2S_LR_INV
- ALC5632_DAI_VOICE_I2S_SYSCLK_SEL
- ALC5632_DAI_VOICE_MODE_SEL
- ALC5632_DAI_VOICE_PCM_ENABLE
- ALC5632_DAI_VOICE_VBCLK_SYSCLK_SEL
- ALC5632_DIGI_BOOST_CTRL
- ALC5632_EQ_CTRL
- ALC5632_FORMATS
- ALC5632_GPCR1
- ALC5632_GPCR1_CLK_SYS_SRC_SEL_MCLK
- ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1
- ALC5632_GPCR1_DAC_HI_FLT_EN
- ALC5632_GPCR1_SPK_AMP_CTRL
- ALC5632_GPCR1_VDD_100
- ALC5632_GPCR1_VDD_125
- ALC5632_GPCR1_VDD_150
- ALC5632_GPCR1_VDD_175
- ALC5632_GPCR1_VDD_200
- ALC5632_GPCR1_VDD_225
- ALC5632_GPCR2
- ALC5632_GPCR2_CLK_PLL_PRE_DIV1
- ALC5632_GPCR2_PLL1_SOUR_SEL
- ALC5632_GPIO_OUPUT_PIN_CTRL
- ALC5632_GPIO_PIN_CONFIG
- ALC5632_GPIO_PIN_POLARITY
- ALC5632_GPIO_PIN_SHARING
- ALC5632_GPIO_PIN_STATUS
- ALC5632_GPIO_PIN_STICKY
- ALC5632_GPIO_PIN_WAKEUP
- ALC5632_HID_CTRL_DATA
- ALC5632_HID_CTRL_INDEX
- ALC5632_HP_OUT_VOL
- ALC5632_I2S_OUT_CTL
- ALC5632_LINE_IN_VOL
- ALC5632_MAX_REGISTER
- ALC5632_MIC_BOOST_20DB
- ALC5632_MIC_BOOST_30DB
- ALC5632_MIC_BOOST_40DB
- ALC5632_MIC_BOOST_BYPASS
- ALC5632_MIC_BOOST_RANGE
- ALC5632_MIC_BOOST_STEP
- ALC5632_MIC_CTRL
- ALC5632_MIC_ROUTE_HP
- ALC5632_MIC_ROUTE_MONOMIX
- ALC5632_MIC_ROUTE_SPK
- ALC5632_MIC_ROUTING_CTRL
- ALC5632_MIC_VOL
- ALC5632_MISC_AVC_TRGT_BOTH
- ALC5632_MISC_AVC_TRGT_LEFT
- ALC5632_MISC_AVC_TRGT_RIGHT
- ALC5632_MISC_AVC_TRGT_SEL
- ALC5632_MISC_CTRL
- ALC5632_MISC_DISABLE_FAST_VREG
- ALC5632_MISC_GPIO_WAKEUP_CTRL
- ALC5632_MISC_HP_DEPOP_MODE1_EN
- ALC5632_MISC_HP_DEPOP_MODE2_EN
- ALC5632_MISC_HP_DEPOP_MUTE
- ALC5632_MISC_HP_DEPOP_MUTE_L
- ALC5632_MISC_HP_DEPOP_MUTE_R
- ALC5632_MISC_IRQOUT_INV_CTRL
- ALC5632_OUTPUT_MIXER_AUX_HP_LR
- ALC5632_OUTPUT_MIXER_AUX_SPK
- ALC5632_OUTPUT_MIXER_CTRL
- ALC5632_OUTPUT_MIXER_HP
- ALC5632_OUTPUT_MIXER_HP_L
- ALC5632_OUTPUT_MIXER_HP_R
- ALC5632_OUTPUT_MIXER_RP
- ALC5632_OUTPUT_MIXER_WEEK
- ALC5632_OVER_CURR_STATUS
- ALC5632_PHONE_IN_VOL
- ALC5632_PLL1_CTRL
- ALC5632_PLL1_CTRL_K_VAL
- ALC5632_PLL1_CTRL_M_VAL
- ALC5632_PLL1_CTRL_N_VAL
- ALC5632_PLL1_M_BYPASS
- ALC5632_PLL2_CTRL
- ALC5632_PLL2_EN
- ALC5632_PLL2_RATIO
- ALC5632_PLL_FR_BCLK
- ALC5632_PLL_FR_MCLK
- ALC5632_PLL_FR_VBCLK
- ALC5632_PSEUDO_SPATIAL_CTRL
- ALC5632_PWR_ADC_STATUS
- ALC5632_PWR_ADD1_DAC_L_EN
- ALC5632_PWR_ADD1_DAC_REF
- ALC5632_PWR_ADD1_DAC_R_EN
- ALC5632_PWR_ADD1_HP_OUT_AMP
- ALC5632_PWR_ADD1_HP_OUT_ENH_AMP
- ALC5632_PWR_ADD1_MAIN_BIAS
- ALC5632_PWR_ADD1_MAIN_I2S_EN
- ALC5632_PWR_ADD1_MIC1_EN
- ALC5632_PWR_ADD1_MIC1_SHORT_CURR
- ALC5632_PWR_ADD1_MIC2_EN
- ALC5632_PWR_ADD1_MIC2_SHORT_CURR
- ALC5632_PWR_ADD1_SOFTGEN_EN
- ALC5632_PWR_ADD1_SPK_AMP_EN
- ALC5632_PWR_ADD1_VOICE_DAC_MIX
- ALC5632_PWR_ADD1_ZERO_CROSS
- ALC5632_PWR_ADD2_L_ADC_CLK_GAIN
- ALC5632_PWR_ADD2_L_ADC_REC_MIXER
- ALC5632_PWR_ADD2_L_DAC_CLK
- ALC5632_PWR_ADD2_L_HP_MIXER
- ALC5632_PWR_ADD2_MONO_MIXER
- ALC5632_PWR_ADD2_OVT_DET
- ALC5632_PWR_ADD2_PLL1
- ALC5632_PWR_ADD2_PLL2
- ALC5632_PWR_ADD2_R_ADC_CLK_GAIN
- ALC5632_PWR_ADD2_R_ADC_REC_MIXER
- ALC5632_PWR_ADD2_R_DAC_CLK
- ALC5632_PWR_ADD2_R_HP_MIXER
- ALC5632_PWR_ADD2_SPK_MIXER
- ALC5632_PWR_ADD2_VOICE_DAC
- ALC5632_PWR_ADD2_VREF
- ALC5632_PWR_ADD3_AUXIN_MIX
- ALC5632_PWR_ADD3_AUXIN_VOL
- ALC5632_PWR_ADD3_AUXOUT_VOL
- ALC5632_PWR_ADD3_HP_L_OUT_VOL
- ALC5632_PWR_ADD3_HP_R_OUT_VOL
- ALC5632_PWR_ADD3_LINEIN_L_VOL
- ALC5632_PWR_ADD3_LINEIN_R_VOL
- ALC5632_PWR_ADD3_MIC1_BOOST_AD
- ALC5632_PWR_ADD3_MIC1_VOL
- ALC5632_PWR_ADD3_MIC2_BOOST_AD
- ALC5632_PWR_ADD3_MIC2_VOL
- ALC5632_PWR_ADD3_SPK_L_OUT
- ALC5632_PWR_ADD3_SPK_R_OUT
- ALC5632_PWR_AMIX_STATUS
- ALC5632_PWR_DAC_STATUS
- ALC5632_PWR_DOWN_CTRL_STATUS
- ALC5632_PWR_DOWN_CTRL_STATUS_MASK
- ALC5632_PWR_MANAG_ADD1
- ALC5632_PWR_MANAG_ADD1_MASK
- ALC5632_PWR_MANAG_ADD2
- ALC5632_PWR_MANAG_ADD2_MASK
- ALC5632_PWR_MANAG_ADD3
- ALC5632_PWR_MANAG_ADD3_MASK
- ALC5632_PWR_VREF_PR2
- ALC5632_PWR_VREF_PR3
- ALC5632_PWR_VREF_STATUS
- ALC5632_RESET
- ALC5632_SOFTVOL_CTRL
- ALC5632_SPK_OUT_VOL
- ALC5632_SPK_OUT_VOL_STEP
- ALC5632_STEREO_DAC_IN_VOL
- ALC5632_VENDOR_ID1
- ALC5632_VENDOR_ID2
- ALC5632_VOICE_DAC_PCM_CLK_CTRL1
- ALC5632_VOICE_DAC_VOL
- ALC660VD_FIX_ASUS_GPIO1
- ALC660_FIXUP_ASUS_W7J
- ALC662_FIXUP_ACER_NITRO_HEADSET_MODE
- ALC662_FIXUP_ACER_VERITON
- ALC662_FIXUP_ACER_X2660G_HEADSET_MODE
- ALC662_FIXUP_ASPIRE
- ALC662_FIXUP_ASUS_MODE1
- ALC662_FIXUP_ASUS_MODE2
- ALC662_FIXUP_ASUS_MODE3
- ALC662_FIXUP_ASUS_MODE4
- ALC662_FIXUP_ASUS_MODE5
- ALC662_FIXUP_ASUS_MODE6
- ALC662_FIXUP_ASUS_MODE7
- ALC662_FIXUP_ASUS_MODE8
- ALC662_FIXUP_ASUS_Nx50
- ALC662_FIXUP_BASS_16
- ALC662_FIXUP_BASS_1A
- ALC662_FIXUP_BASS_CHMAP
- ALC662_FIXUP_BASS_MODE4_CHMAP
- ALC662_FIXUP_CZC_P10T
- ALC662_FIXUP_DELL_MIC_NO_PRESENCE
- ALC662_FIXUP_HEADSET_MODE
- ALC662_FIXUP_HP_RP5800
- ALC662_FIXUP_IDEAPAD
- ALC662_FIXUP_INV_DMIC
- ALC662_FIXUP_LED_GPIO1
- ALC662_FIXUP_LENOVO_MULTI_CODECS
- ALC662_FIXUP_NO_JACK_DETECT
- ALC662_FIXUP_SKU_IGNORE
- ALC662_FIXUP_USI_FUNC
- ALC662_FIXUP_USI_HEADSET_MODE
- ALC662_FIXUP_ZOTAC_Z68
- ALC668_FIXUP_ASUS_G751
- ALC668_FIXUP_ASUS_Nx51
- ALC668_FIXUP_ASUS_Nx51_HEADSET_MODE
- ALC668_FIXUP_AUTO_MUTE
- ALC668_FIXUP_DELL_DISABLE_AAMIX
- ALC668_FIXUP_DELL_MIC_NO_PRESENCE
- ALC668_FIXUP_DELL_XPS13
- ALC668_FIXUP_HEADSET_MODE
- ALC668_FIXUP_MIC_COEF
- ALC669_FIXUP_ACER_ASPIRE_ETHOS
- ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET
- ALC671_FIXUP_HP_HEADSET_MIC2
- ALC700_FIXUP_INTEL_REFERENCE
- ALC861VD_FIX_DALLAS
- ALC861_FIXUP_AMP_VREF_0F
- ALC861_FIXUP_ASUS_A6RP
- ALC861_FIXUP_FSC_AMILO_PI1505
- ALC861_FIXUP_NO_JACK_DETECT
- ALC880_FIXUP_3ST
- ALC880_FIXUP_3ST_BASE
- ALC880_FIXUP_3ST_DIG
- ALC880_FIXUP_5ST
- ALC880_FIXUP_5ST_BASE
- ALC880_FIXUP_5ST_DIG
- ALC880_FIXUP_6ST
- ALC880_FIXUP_6ST_AUTOMUTE
- ALC880_FIXUP_6ST_BASE
- ALC880_FIXUP_6ST_DIG
- ALC880_FIXUP_ASUS_W5A
- ALC880_FIXUP_EAPD_COEF
- ALC880_FIXUP_F1734
- ALC880_FIXUP_FUJITSU
- ALC880_FIXUP_GPIO1
- ALC880_FIXUP_GPIO2
- ALC880_FIXUP_LG
- ALC880_FIXUP_LG_LW25
- ALC880_FIXUP_MEDION_RIM
- ALC880_FIXUP_TCL_S700
- ALC880_FIXUP_UNIWILL
- ALC880_FIXUP_UNIWILL_DIG
- ALC880_FIXUP_VOL_KNOB
- ALC880_FIXUP_W810
- ALC880_FIXUP_Z71V
- ALC882_FIXUP_ABIT_AW9D_MAX
- ALC882_FIXUP_ACER_ASPIRE_4930G
- ALC882_FIXUP_ACER_ASPIRE_7736
- ALC882_FIXUP_ACER_ASPIRE_8930G
- ALC882_FIXUP_ASPIRE_8930G_VERBS
- ALC882_FIXUP_ASUS_W2JC
- ALC882_FIXUP_ASUS_W90V
- ALC882_FIXUP_EAPD
- ALC882_FIXUP_GPIO1
- ALC882_FIXUP_GPIO2
- ALC882_FIXUP_GPIO3
- ALC882_FIXUP_INV_DMIC
- ALC882_FIXUP_LENOVO_Y530
- ALC882_FIXUP_NO_PRIMARY_HP
- ALC882_FIXUP_PB_M5210
- ALC883_FIXUP_ACER_EAPD
- ALC883_FIXUP_EAPD
- ALC885_FIXUP_MACPRO_GPIO
- ALC887_FIXUP_ASUS_BASS
- ALC887_FIXUP_BASS_CHMAP
- ALC888_FIXUP_EEE1601
- ALC889_FIXUP_CD
- ALC889_FIXUP_COEF
- ALC889_FIXUP_DAC_ROUTE
- ALC889_FIXUP_FRONT_HP_NO_PRESENCE
- ALC889_FIXUP_IMAC91_VREF
- ALC889_FIXUP_MBA11_VREF
- ALC889_FIXUP_MBA21_VREF
- ALC889_FIXUP_MBP_VREF
- ALC889_FIXUP_MP11_VREF
- ALC889_FIXUP_MP41_VREF
- ALC889_FIXUP_VAIO_TT
- ALC891_FIXUP_DELL_MIC_NO_PRESENCE
- ALC891_FIXUP_HEADSET_MODE
- ALC892_FIXUP_ASROCK_MOBO
- ALCATEL_BROADCAST_PKT
- ALCATEL_MULTICAST_PKT
- ALCATEL_PRODUCT_ID
- ALCATEL_PRODUCT_L100V
- ALCATEL_PRODUCT_L800MA
- ALCATEL_PRODUCT_X060S_X200
- ALCATEL_PRODUCT_X220_X500D
- ALCATEL_VENDOR_ID
- ALCHEMY_AUXPLL2_CLK
- ALCHEMY_AUXPLL_CLK
- ALCHEMY_CPU_AU1000
- ALCHEMY_CPU_AU1100
- ALCHEMY_CPU_AU1200
- ALCHEMY_CPU_AU1300
- ALCHEMY_CPU_AU1500
- ALCHEMY_CPU_AU1550
- ALCHEMY_CPU_CLK
- ALCHEMY_CPU_UNKNOWN
- ALCHEMY_FG0_CLK
- ALCHEMY_FG1_CLK
- ALCHEMY_FG2_CLK
- ALCHEMY_FG3_CLK
- ALCHEMY_FG4_CLK
- ALCHEMY_FG5_CLK
- ALCHEMY_GPIC_INT_BASE
- ALCHEMY_GPIC_INT_LAST
- ALCHEMY_GPIC_INT_NUM
- ALCHEMY_GPIO1_BASE
- ALCHEMY_GPIO1_MAX
- ALCHEMY_GPIO1_NUM
- ALCHEMY_GPIO2_BASE
- ALCHEMY_GPIO2_MAX
- ALCHEMY_GPIO2_NUM
- ALCHEMY_LR_CLK
- ALCHEMY_MEM_CLK
- ALCHEMY_PCI_IOWIN_END
- ALCHEMY_PCI_IOWIN_START
- ALCHEMY_PCI_MEMWIN_END
- ALCHEMY_PCI_MEMWIN_START
- ALCHEMY_PERIPH_CLK
- ALCHEMY_ROOTCLK_RATE
- ALCHEMY_ROOT_CLK
- ALCHEMY_SYSBUS_CLK
- ALCHEMY_USB_EHCI0
- ALCHEMY_USB_OHCI0
- ALCHEMY_USB_OHCI1
- ALCHEMY_USB_OTG0
- ALCHEMY_USB_UDC0
- ALCOR_CAP_START_OFFSET
- ALCOR_GRU_INT_REQ_BITS
- ALCOR_MS_CARD
- ALCOR_PCIE_LINK_CAP_OFFSET
- ALCOR_PCIE_LINK_CTRL_OFFSET
- ALCOR_PRODUCT_ID
- ALCOR_SD_CARD
- ALCOR_VENDOR_ID
- ALC_CTL1
- ALC_CTL2
- ALC_CTL3
- ALC_EN
- ALC_FIXUP_SKU_IGNORE
- ALC_HEADSET_MODE_HEADPHONE
- ALC_HEADSET_MODE_HEADSET
- ALC_HEADSET_MODE_MIC
- ALC_HEADSET_MODE_UNKNOWN
- ALC_HEADSET_MODE_UNPLUGGED
- ALC_HEADSET_TYPE_CTIA
- ALC_HEADSET_TYPE_OMTP
- ALC_HEADSET_TYPE_UNKNOWN
- ALC_HOLD
- ALC_INIT_DEFAULT
- ALC_INIT_NONE
- ALC_INIT_UNDEFINED
- ALC_KEY_MICMUTE_INDEX
- ALD
- ALDO1
- ALDO10
- ALDO2
- ALDO3
- ALDO4
- ALDO5
- ALDO6
- ALDO7
- ALDO8
- ALDO9
- ALDPS_PROXY_MODE
- ALDPS_SPDWN_RATIO
- ALD_EN
- ALEA_FIRST_TIMEOUT
- ALEA_PRODUCT_ID
- ALEA_VENDOR_ID
- ALED1
- ALED2
- ALEN
- ALEN_MASK
- ALEN_SHIFT
- ALERT_CH_NUM
- ALE_AGEOUT
- ALE_ALL_PORTS
- ALE_AUTH_ENABLE
- ALE_BLOCKED
- ALE_BYPASS
- ALE_CLEAR
- ALE_CONTROL
- ALE_ENABLE
- ALE_ENTRY_BITS
- ALE_ENTRY_WORDS
- ALE_IDVER
- ALE_MCAST_BLOCK_LEARN_FWD
- ALE_MCAST_FWD
- ALE_MCAST_FWD_2
- ALE_MCAST_FWD_LEARN
- ALE_NO_PORT_VLAN
- ALE_NUM_CONTROLS
- ALE_OUI_DENY
- ALE_P0_UNI_FLOOD
- ALE_PIN_CTL
- ALE_PORTCTL
- ALE_PORT_1
- ALE_PORT_2
- ALE_PORT_BCAST_LIMIT
- ALE_PORT_DROP_UNKNOWN_VLAN
- ALE_PORT_DROP_UNTAGGED
- ALE_PORT_HOST
- ALE_PORT_MCAST_LIMIT
- ALE_PORT_NOLEARN
- ALE_PORT_NO_SA_UPDATE
- ALE_PORT_STATE
- ALE_PORT_STATE_BLOCK
- ALE_PORT_STATE_DISABLE
- ALE_PORT_STATE_FORWARD
- ALE_PORT_STATE_LEARN
- ALE_PORT_UNKNOWN_MCAST_FLOOD
- ALE_PORT_UNKNOWN_REG_MCAST_FLOOD
- ALE_PORT_UNKNOWN_VLAN_MEMBER
- ALE_PORT_UNTAGGED_EGRESS
- ALE_PRESCALE
- ALE_RATE_LIMIT
- ALE_RATE_LIMIT_TX
- ALE_SECURE
- ALE_STATUS
- ALE_STATUS_SIZE_MASK
- ALE_SUPER
- ALE_TABLE
- ALE_TABLE_CONTROL
- ALE_TABLE_SIZE_DEFAULT
- ALE_TABLE_SIZE_MULTIPLIER
- ALE_TABLE_WRITE
- ALE_TYPE_ADDR
- ALE_TYPE_FREE
- ALE_TYPE_VLAN
- ALE_TYPE_VLAN_ADDR
- ALE_UCAST_OUI
- ALE_UCAST_PERSISTANT
- ALE_UCAST_TOUCHED
- ALE_UCAST_UNTOUCHED
- ALE_UNKNOWNVLAN
- ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS
- ALE_UNKNOWNVLAN_MEMBER
- ALE_UNKNOWNVLAN_REG_MCAST_FLOOD
- ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD
- ALE_VERSION_1R3
- ALE_VERSION_1R4
- ALE_VERSION_MAJOR
- ALE_VERSION_MINOR
- ALE_VLAN
- ALE_VLAN_AWARE
- ALE_VLAN_MASK_MUX
- ALE_VLAN_NOLEARN
- ALFPS_DTCT_EN
- ALGORITHM
- ALGORITHM_LEFT_ASYMMETRIC
- ALGORITHM_LEFT_ASYMMETRIC_6
- ALGORITHM_LEFT_SYMMETRIC
- ALGORITHM_LEFT_SYMMETRIC_6
- ALGORITHM_PARITY_0
- ALGORITHM_PARITY_0_6
- ALGORITHM_PARITY_N
- ALGORITHM_PARITY_N_6
- ALGORITHM_RAID10_DEFAULT
- ALGORITHM_RAID10_FAR
- ALGORITHM_RAID10_NEAR
- ALGORITHM_RAID10_OFFSET
- ALGORITHM_RIGHT_ASYMMETRIC
- ALGORITHM_RIGHT_ASYMMETRIC_6
- ALGORITHM_RIGHT_SYMMETRIC
- ALGORITHM_RIGHT_SYMMETRIC_6
- ALGORITHM_ROTATING_N_CONTINUE
- ALGORITHM_ROTATING_N_RESTART
- ALGORITHM_ROTATING_ZERO_RESTART
- ALGOSWRST
- ALGO_BT_MONITOR
- ALGO_BT_RSSI_STATE
- ALGO_TRACE
- ALGO_TRACE_FW
- ALGO_TRACE_FW_DETAIL
- ALGO_TRACE_FW_EXEC
- ALGO_TRACE_SW
- ALGO_TRACE_SW_DETAIL
- ALGO_TRACE_SW_EXEC
- ALGO_WIFI_RSSI_STATE
- ALG_MAX_PAGES
- ALG_OP_DECRYPT
- ALG_OP_ENCRYPT
- ALG_SET_AEAD_ASSOCLEN
- ALG_SET_AEAD_AUTHSIZE
- ALG_SET_IV
- ALG_SET_KEY
- ALG_SET_OP
- ALG_TYPE_CIPHER
- ALG_TYPE_HASH
- ALG_XM_FIELD
- ALI1535_A_HIGH_BIT8
- ALI1535_A_HIGH_BIT9
- ALI1535_BLOCK_CLR
- ALI1535_BLOCK_DATA
- ALI1535_BYTE
- ALI1535_BYTE_DATA
- ALI1535_DEV10B_EN
- ALI1535_D_HI_MASK
- ALI1535_I2C_READ
- ALI1535_KILL
- ALI1535_LOCK
- ALI1535_QUICK
- ALI1535_RD_ADDR
- ALI1535_SMBIO_EN
- ALI1535_SMB_DEFAULTBASE
- ALI1535_SMB_IOSIZE
- ALI1535_STS_BUSERR
- ALI1535_STS_BUSY
- ALI1535_STS_DEV
- ALI1535_STS_DONE
- ALI1535_STS_ERR
- ALI1535_STS_FAIL
- ALI1535_STS_IDLE
- ALI1535_T_OUT
- ALI1535_WORD_DATA
- ALI1563_MAX_TIMEOUT
- ALI1563_SMBBA
- ALI1563_SMB_HOSTEN
- ALI1563_SMB_IOEN
- ALI1563_SMB_IOSIZE
- ALI15X3_ABORT
- ALI15X3_BLOCK_CLR
- ALI15X3_BLOCK_DATA
- ALI15X3_BYTE
- ALI15X3_BYTE_DATA
- ALI15X3_LOCK
- ALI15X3_QUICK
- ALI15X3_SMB_DEFAULTBASE
- ALI15X3_SMB_IOSIZE
- ALI15X3_STS_BUSY
- ALI15X3_STS_COLL
- ALI15X3_STS_DEV
- ALI15X3_STS_DONE
- ALI15X3_STS_ERR
- ALI15X3_STS_IDLE
- ALI15X3_STS_TERM
- ALI15X3_T_OUT
- ALI15X3_WORD_DATA
- ALI5451_SPDIF
- ALIAS
- ALIAS_10BIT_IO
- ALIAS_MV
- ALIAS_SIZE
- ALIAS_TABLE_ENTRY_SIZE
- ALICNT
- ALID_AC97SPDIFOUT
- ALID_LAST
- ALID_MDMIN
- ALID_MDMLAST
- ALID_MDMOUT
- ALID_MIC
- ALID_PCMIN
- ALID_PCMOUT
- ALID_SPDIFIN
- ALID_SPDIFOUT
- ALIGN
- ALIGN16
- ALIGN32
- ALIGN8
- ALIGNED
- ALIGNED_EFFECTIVE
- ALIGNED_PHYSICAL
- ALIGNED_QDSS_SIZE
- ALIGNED_QUEUE_SIZE
- ALIGNED_RX_BUF_SIZE_MASK
- ALIGNED_RX_BUF_SIZE_SHIFT
- ALIGNED_RX_SKB_ADDR
- ALIGNED_SFR_SIZE
- ALIGNED_TYPE_SIZE
- ALIGNED_UPIU_SIZE
- ALIGNMENT
- ALIGNMENT_EXCEPTION
- ALIGNMENT_MODE
- ALIGNMENT_OF_UCC_HDLC_PRAM
- ALIGNMENT_OF_UCC_SLOW_PRAM
- ALIGNMENT_UNIT
- ALIGNSTAT
- ALIGNUP
- ALIGN_0_DATA_k
- ALIGN_1_DATA_k
- ALIGN_512M_MASK
- ALIGN_8
- ALIGN_ADDR
- ALIGN_ADDRESS
- ALIGN_BITS
- ALIGN_CNT1
- ALIGN_CNT2
- ALIGN_CNT3
- ALIGN_CNT4
- ALIGN_DESTINATION
- ALIGN_DEST_TO8_DN
- ALIGN_DEST_TO8_UP
- ALIGN_DOWN
- ALIGN_EN
- ALIGN_ENTRY_TEXT_BEGIN
- ALIGN_ENTRY_TEXT_END
- ALIGN_FUNCTION
- ALIGN_H
- ALIGN_MASK
- ALIGN_PAGE_SIZE
- ALIGN_PRE
- ALIGN_PTR_DOWN
- ALIGN_PTR_UP
- ALIGN_SIZE
- ALIGN_SKB_CHOP_LEN_MASK
- ALIGN_SKB_FLAG
- ALIGN_STR
- ALIGN_SZ
- ALIGN_UP
- ALIGN_VA_32
- ALIGN_VA_64
- ALIGN_W
- ALIMIT
- ALINEPOW
- ALINEPOW_LIN1_POWD
- ALINEPOW_LIN2_POWD
- ALINK_PRODUCT_3GU
- ALINK_PRODUCT_PH300
- ALINK_VENDOR_ID
- ALINSW1
- ALINSW1_SEL1_SHIFT
- ALIVE_RESP_RFKILL
- ALIVE_RESP_UCODE_OK
- ALI_5451_V02
- ALI_7101_GPIO
- ALI_7101_GPIO_O
- ALI_7101_WDT
- ALI_AC97_GPIO
- ALI_AC97_GPIO_DATA_SHIFT
- ALI_AC97_GPIO_ENABLE
- ALI_AC97_READ
- ALI_AC97_WRITE
- ALI_AGPCTRL
- ALI_AINT
- ALI_AINTEN
- ALI_ATTBASE
- ALI_CACHE_FLUSH_ADDR_MASK
- ALI_CACHE_FLUSH_CTRL
- ALI_CACHE_FLUSH_EN
- ALI_CAS_SEM_BUSY
- ALI_CENTER_CHANNEL
- ALI_CHANNELS
- ALI_CHANNEL_REGS
- ALI_CPR_ADDR_READ
- ALI_CPR_ADDR_SECONDARY
- ALI_CSO_ALPHA_FMS
- ALI_CSPF
- ALI_CSPSR_CODEC_READY
- ALI_CSPSR_READ_OK
- ALI_CSPSR_WRITE_OK
- ALI_EBUF1
- ALI_EBUF2
- ALI_ESO_DELTA
- ALI_GC_CIR
- ALI_GLOBAL_CONTROL
- ALI_GLOBAL_REGS
- ALI_GVSEL_PAN_VOC_CTRL_EC
- ALI_INT_CENTEROUT
- ALI_INT_CODECSPDIFOUT
- ALI_INT_CPRAIS
- ALI_INT_GPIO
- ALI_INT_I2SIN
- ALI_INT_LFEOUT
- ALI_INT_MASK
- ALI_INT_MICIN
- ALI_INT_MICIN2
- ALI_INT_PCMIN
- ALI_INT_PCMIN2
- ALI_INT_PCMOUT
- ALI_INT_SPDIFIN
- ALI_INT_SPDIFOUT
- ALI_INT_SPRAIS
- ALI_LBA
- ALI_LEF_CHANNEL
- ALI_LEGACY_DMAR0
- ALI_LEGACY_DMAR11
- ALI_LEGACY_DMAR15
- ALI_LEGACY_DMAR4
- ALI_MISCINT
- ALI_MODEM_IN_CHANNEL
- ALI_MODEM_OUT_CHANNEL
- ALI_MPUR0
- ALI_MPUR1
- ALI_MPUR2
- ALI_MPUR3
- ALI_NUM_PORTS
- ALI_PCM_IN_CHANNEL
- ALI_PCM_IN_ENABLE
- ALI_PM_OPS
- ALI_REG
- ALI_SBBL_SBCL
- ALI_SBCTRL_SBE2R_SBDD
- ALI_SBDELTA_DELTA_R
- ALI_SCTRL
- ALI_SCTRL_CODEC1_READY
- ALI_SCTRL_CODEC2_READY
- ALI_SCTRL_GPIO_IN2
- ALI_SCTRL_GPIO_OUT_EN
- ALI_SCTRL_LINE_IN2
- ALI_SCTRL_LINE_OUT_EN
- ALI_SPDIF_CS
- ALI_SPDIF_CTRL
- ALI_SPDIF_IN_CHANNEL
- ALI_SPDIF_IN_CH_ENABLE
- ALI_SPDIF_IN_CH_STATUS
- ALI_SPDIF_IN_FUNC_ENABLE
- ALI_SPDIF_IN_SUPPORT
- ALI_SPDIF_OUT_CHANNEL
- ALI_SPDIF_OUT_CH_ENABLE
- ALI_SPDIF_OUT_CH_STATUS
- ALI_SPDIF_OUT_ENABLE
- ALI_SPDIF_OUT_SEL_PCM
- ALI_START
- ALI_STIMER
- ALI_STOP
- ALI_SURR_LEFT_CHANNEL
- ALI_SURR_RIGHT_CHANNEL
- ALI_TAGCTRL
- ALI_TLBCTRL
- ALI_VOLUME
- ALI_WDT_ARM
- ALL
- ALLEGRO_GOP_SIZE_DEFAULT
- ALLEGRO_GOP_SIZE_MAX
- ALLEGRO_HEIGHT_DEFAULT
- ALLEGRO_HEIGHT_MAX
- ALLEGRO_HEIGHT_MIN
- ALLEGRO_STATE_DRAIN
- ALLEGRO_STATE_ENCODING
- ALLEGRO_STATE_STOPPED
- ALLEGRO_STATE_WAIT_FOR_BUFFER
- ALLEGRO_WIDTH_DEFAULT
- ALLEGRO_WIDTH_MAX
- ALLEGRO_WIDTH_MIN
- ALLINTS
- ALLIRQS
- ALLOC
- ALLOCATE_FOR_PANNING
- ALLOCATE_MEMORY_ADDR_ZERO
- ALLOCATE_MEMORY_TRY_ALT_UNIT
- ALLOCATION_STATE
- ALLOCSTALL
- ALLOC_AFTER
- ALLOC_BEFORE
- ALLOC_BUF_SIZE
- ALLOC_CHROMA_DPB_SIZE
- ALLOC_CHUNK
- ALLOC_CHUNK_FORCE
- ALLOC_CMA
- ALLOC_CMD_URB
- ALLOC_COMPL_TIMEOUT
- ALLOC_CPUSET
- ALLOC_DATA
- ALLOC_DATA_IN_URB
- ALLOC_DATA_OUT_URB
- ALLOC_DECS_NUM
- ALLOC_DELETION
- ALLOC_ERR
- ALLOC_FAILURE_MSG
- ALLOC_FASTPATH
- ALLOC_FMR
- ALLOC_FROM_PARTIAL
- ALLOC_FWD_MAX
- ALLOC_FWD_MIN
- ALLOC_G
- ALLOC_GC
- ALLOC_GROUPS_FROM_GLOBAL
- ALLOC_GROW
- ALLOC_GROW_DEPTH
- ALLOC_GROW_HEIGHT
- ALLOC_HARDER
- ALLOC_HIGH
- ALLOC_KSWAPD
- ALLOC_LEFT
- ALLOC_LIST
- ALLOC_LUMA_DPB_SIZE
- ALLOC_M
- ALLOC_MEM_FLAGS_AQL_QUEUE_MEM
- ALLOC_MEM_FLAGS_COHERENT
- ALLOC_MEM_FLAGS_DOORBELL
- ALLOC_MEM_FLAGS_EXECUTABLE
- ALLOC_MEM_FLAGS_GTT
- ALLOC_MEM_FLAGS_MMIO_REMAP
- ALLOC_MEM_FLAGS_NO_SUBSTITUTE
- ALLOC_MEM_FLAGS_PUBLIC
- ALLOC_MEM_FLAGS_USERPTR
- ALLOC_MEM_FLAGS_VRAM
- ALLOC_MEM_FLAGS_WRITABLE
- ALLOC_MID
- ALLOC_MODE_DEFAULT
- ALLOC_MODE_REUSE
- ALLOC_MR
- ALLOC_MV_SIZE
- ALLOC_NEW_GROUP
- ALLOC_NEXT
- ALLOC_NODE
- ALLOC_NODE_MISMATCH
- ALLOC_NOFRAGMENT
- ALLOC_NORETRY
- ALLOC_NORMAL
- ALLOC_NO_WATERMARKS
- ALLOC_OOM
- ALLOC_PD
- ALLOC_PERIOD
- ALLOC_REFILL
- ALLOC_RIGHT
- ALLOC_S
- ALLOC_SLAB
- ALLOC_SLOWPATH
- ALLOC_SPLIT_PTLOCKS
- ALLOC_STACK_FRAME
- ALLOC_UCONTEXT
- ALLOC_UNUSABLE
- ALLOC_USABLE
- ALLOC_WMARK_HIGH
- ALLOC_WMARK_LOW
- ALLOC_WMARK_MASK
- ALLOC_WMARK_MIN
- ALLONES
- ALLOW
- ALLOW8_SPRG
- ALLOWABLE_FS_COUNT
- ALLOWED_AS_FIRST_OP
- ALLOWED_CHILD1
- ALLOWED_CHILD2
- ALLOWED_ON_ABSENT_FS
- ALLOWED_SIGS
- ALLOWED_WITHOUT_FH
- ALLOWINT
- ALLOW_CONN_PEER_MGMT_WHILE_BUF_FULL
- ALLOW_CORRUPT
- ALLOW_CTRL_ASSOC_PEER
- ALLOW_DATA_ASSOC_PEER
- ALLOW_DEBUG
- ALLOW_DMA
- ALLOW_ERROR_INJECTION
- ALLOW_FAIL
- ALLOW_FDX
- ALLOW_IOV_BYPASS
- ALLOW_IOV_BYPASS_SG
- ALLOW_MEDIUM_REMOVAL
- ALLOW_MGMT_ASSOC_PEER
- ALLOW_OVERFLOW
- ALLOW_PKT
- ALLOW_RESEL
- ALLOW_SERIAL_NUMBER
- ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK
- ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT
- ALLOW_SR_ON_TRANS_REQ
- ALLOW_SR_ON_TRANS_REQ_DISABLE
- ALLOW_SR_ON_TRANS_REQ_ENABLE
- ALLOW_SYNC
- ALLOW_UNKNOWN
- ALLPHYS
- ALLZEROS
- ALL_802_11_BANDS
- ALL_AREAS
- ALL_ATX_RESET
- ALL_AUTO_MODE_MASKS
- ALL_BAND_FILTER
- ALL_BASE_ADDR
- ALL_BSS_FILTER
- ALL_BUT_BSS_FILTER
- ALL_BUT_PROFILE_FILTER
- ALL_CHANNELS
- ALL_CMDS_NOTIFIED
- ALL_CODEC_NOT_READY
- ALL_COLOR_LED
- ALL_COMP_DECOMP_EN
- ALL_COUNTER_CLR
- ALL_DEVICES_SUPPORTED
- ALL_DIRECT_INTS_MASK
- ALL_ENGINES
- ALL_EXIT_DATA_SECTIONS
- ALL_EXIT_SECTIONS
- ALL_EXIT_TEXT_SECTIONS
- ALL_FALLBACK_ON
- ALL_FANOTIFY_EVENT_BITS
- ALL_FROZE
- ALL_FSNOTIFY_BITS
- ALL_FSNOTIFY_DIRENT_EVENTS
- ALL_FSNOTIFY_EVENTS
- ALL_FSNOTIFY_FLAGS
- ALL_FSNOTIFY_PERM_EVENTS
- ALL_HASH
- ALL_INDEXED_INTS_MASK
- ALL_INIT_DATA_SECTIONS
- ALL_INIT_SECTIONS
- ALL_INIT_TEXT_SECTIONS
- ALL_INOTIFY_BITS
- ALL_INT
- ALL_INTS
- ALL_INT_CLR
- ALL_INT_EXT
- ALL_INT_MASK
- ALL_IRSR
- ALL_IRSR_ML
- ALL_L3_SLICES
- ALL_LAYER_ALPHA_SEL
- ALL_LEDS
- ALL_LUNS
- ALL_MBOX_BITS
- ALL_MIFS
- ALL_MPAGES
- ALL_MULTI
- ALL_NWRITE
- ALL_NWRITE_R
- ALL_PCI_ERRORS
- ALL_PCI_INIT_SECTIONS
- ALL_PERMS_MASK
- ALL_PIO_FREEZE_ERR
- ALL_PORTS
- ALL_PORTS_COAL_DONE
- ALL_PORTS_COAL_IRQ
- ALL_PORTS_MASK
- ALL_PORT_VAL_OPEN
- ALL_POWER_DOWN
- ALL_QUEUES
- ALL_READ
- ALL_RXE_FREEZE_ERR
- ALL_RXE_PAUSE
- ALL_RX_IT
- ALL_SDMA_ENG_HALT_ERRS
- ALL_SDMA_FREEZE_ERR
- ALL_SEND_CID
- ALL_SLAVES
- ALL_SNT
- ALL_SUB_MPAGES
- ALL_TARGETS
- ALL_TARGETS_MASK
- ALL_TARGET_HT20_0_8_16
- ALL_TARGET_HT20_12
- ALL_TARGET_HT20_13
- ALL_TARGET_HT20_14
- ALL_TARGET_HT20_15
- ALL_TARGET_HT20_1_3_9_11_17_19
- ALL_TARGET_HT20_20
- ALL_TARGET_HT20_21
- ALL_TARGET_HT20_22
- ALL_TARGET_HT20_23
- ALL_TARGET_HT20_4
- ALL_TARGET_HT20_5
- ALL_TARGET_HT20_6
- ALL_TARGET_HT20_7
- ALL_TARGET_HT40_0_8_16
- ALL_TARGET_HT40_12
- ALL_TARGET_HT40_13
- ALL_TARGET_HT40_14
- ALL_TARGET_HT40_15
- ALL_TARGET_HT40_1_3_9_11_17_19
- ALL_TARGET_HT40_20
- ALL_TARGET_HT40_21
- ALL_TARGET_HT40_22
- ALL_TARGET_HT40_23
- ALL_TARGET_HT40_4
- ALL_TARGET_HT40_5
- ALL_TARGET_HT40_6
- ALL_TARGET_HT40_7
- ALL_TARGET_LEGACY_11L
- ALL_TARGET_LEGACY_11S
- ALL_TARGET_LEGACY_1L_5L
- ALL_TARGET_LEGACY_36
- ALL_TARGET_LEGACY_48
- ALL_TARGET_LEGACY_54
- ALL_TARGET_LEGACY_5S
- ALL_TARGET_LEGACY_6_24
- ALL_TC2PFC
- ALL_TEXT_SECTIONS
- ALL_TIME_REGS
- ALL_TXE_EGRESS_FREEZE_ERR
- ALL_TXE_PAUSE
- ALL_TX_IT
- ALL_VIFS
- ALL_VIRT
- ALL_WAKE_EVENTS
- ALL_WORDS_DISABLED
- ALL_WRITE
- ALL_WRITE_UPDATE
- ALL_XXXEXIT_SECTIONS
- ALL_XXXINIT_SECTIONS
- ALL_ZEROS
- ALM1
- ALM1EN
- ALM1P
- ALM1_VALID_RANGE_IN_SEC
- ALM2
- ALM2EN
- ALM2P
- ALMASK
- ALMOST_EMPTY_BITS
- ALMOST_FULL_BITS
- ALMOST_FULL_INT
- ALM_SCD_ARASTAT_REG
- ALM_SCD_BASE
- ALM_SCD_MODE_REG
- ALM_SCD_SBYP_MODE_1_REG
- ALM_SCD_SBYP_MODE_2_REG
- ALM_SCD_TXF4MF_REG
- ALM_SCD_TXF5MF_REG
- ALM_SCD_TXFACT_REG
- ALNCTL
- ALO1OUTPOW
- ALO1OUTPOW_LO1_ON
- ALO2OUTPOW
- ALO2OUTPOW_ADAC2_MUTE
- ALO2OUTPOW_LO2_ON
- ALOCK
- ALOCK_MASK
- ALOCK_SHIFT
- ALOG
- ALPHA
- ALPHANUM
- ALPHASWITCH
- ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
- ALPHA_BASE
- ALPHA_BITWIDTH
- ALPHA_BLEND
- ALPHA_BLENDING
- ALPHA_CHROMA_KEY
- ALPHA_CHROMA_KEY_MASK_MASK
- ALPHA_CHROMA_KEY_VALUE_MASK
- ALPHA_COLOR_LOOKUP_01
- ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK
- ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK
- ALPHA_COLOR_LOOKUP_01_0_MASK
- ALPHA_COLOR_LOOKUP_01_0_RED_MASK
- ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK
- ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK
- ALPHA_COLOR_LOOKUP_01_1_MASK
- ALPHA_COLOR_LOOKUP_01_1_RED_MASK
- ALPHA_COLOR_LOOKUP_23
- ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK
- ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK
- ALPHA_COLOR_LOOKUP_23_2_MASK
- ALPHA_COLOR_LOOKUP_23_2_RED_MASK
- ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK
- ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK
- ALPHA_COLOR_LOOKUP_23_3_MASK
- ALPHA_COLOR_LOOKUP_23_3_RED_MASK
- ALPHA_COLOR_LOOKUP_45
- ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK
- ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK
- ALPHA_COLOR_LOOKUP_45_4_MASK
- ALPHA_COLOR_LOOKUP_45_4_RED_MASK
- ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK
- ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK
- ALPHA_COLOR_LOOKUP_45_5_MASK
- ALPHA_COLOR_LOOKUP_45_5_RED_MASK
- ALPHA_COLOR_LOOKUP_67
- ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK
- ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK
- ALPHA_COLOR_LOOKUP_67_6_MASK
- ALPHA_COLOR_LOOKUP_67_6_RED_MASK
- ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK
- ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK
- ALPHA_COLOR_LOOKUP_67_7_MASK
- ALPHA_COLOR_LOOKUP_67_7_RED_MASK
- ALPHA_COLOR_LOOKUP_89
- ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK
- ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK
- ALPHA_COLOR_LOOKUP_89_8_MASK
- ALPHA_COLOR_LOOKUP_89_8_RED_MASK
- ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK
- ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK
- ALPHA_COLOR_LOOKUP_89_9_MASK
- ALPHA_COLOR_LOOKUP_89_9_RED_MASK
- ALPHA_COLOR_LOOKUP_AB
- ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK
- ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK
- ALPHA_COLOR_LOOKUP_AB_A_MASK
- ALPHA_COLOR_LOOKUP_AB_A_RED_MASK
- ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK
- ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK
- ALPHA_COLOR_LOOKUP_AB_B_MASK
- ALPHA_COLOR_LOOKUP_AB_B_RED_MASK
- ALPHA_COLOR_LOOKUP_CD
- ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK
- ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK
- ALPHA_COLOR_LOOKUP_CD_C_MASK
- ALPHA_COLOR_LOOKUP_CD_C_RED_MASK
- ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK
- ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK
- ALPHA_COLOR_LOOKUP_CD_D_MASK
- ALPHA_COLOR_LOOKUP_CD_D_RED_MASK
- ALPHA_COLOR_LOOKUP_EF
- ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK
- ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK
- ALPHA_COLOR_LOOKUP_EF_E_MASK
- ALPHA_COLOR_LOOKUP_EF_E_RED_MASK
- ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK
- ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK
- ALPHA_COLOR_LOOKUP_EF_F_MASK
- ALPHA_COLOR_LOOKUP_EF_F_RED_MASK
- ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK
- ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT
- ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
- ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT
- ALPHA_DATA_ON_ALPHA_PORT
- ALPHA_DATA_ON_CB_B_PORT
- ALPHA_DATA_ON_CR_R_PORT
- ALPHA_DATA_ON_Y_G_PORT
- ALPHA_DISPLAY_CTRL
- ALPHA_DISPLAY_CTRL_ALPHA_MASK
- ALPHA_DISPLAY_CTRL_CHROMA_KEY
- ALPHA_DISPLAY_CTRL_FIFO_1
- ALPHA_DISPLAY_CTRL_FIFO_11
- ALPHA_DISPLAY_CTRL_FIFO_3
- ALPHA_DISPLAY_CTRL_FIFO_7
- ALPHA_DISPLAY_CTRL_FIFO_MASK
- ALPHA_DISPLAY_CTRL_FORMAT_16
- ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4
- ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4
- ALPHA_DISPLAY_CTRL_FORMAT_MASK
- ALPHA_DISPLAY_CTRL_PIXEL_MASK
- ALPHA_DISPLAY_CTRL_SELECT
- ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK
- ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK
- ALPHA_FB_ADDRESS
- ALPHA_FB_ADDRESS_ADDRESS_MASK
- ALPHA_FB_ADDRESS_EXT
- ALPHA_FB_ADDRESS_STATUS
- ALPHA_FB_WIDTH
- ALPHA_FB_WIDTH_OFFSET_MASK
- ALPHA_FB_WIDTH_WIDTH_MASK
- ALPHA_GLOBAL
- ALPHA_GRAPHNVIDEO
- ALPHA_INVERSE
- ALPHA_KLUDGE_MCR
- ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER
- ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE
- ALPHA_MAX
- ALPHA_MAX_ISA_DMA_ADDRESS
- ALPHA_MIN
- ALPHA_NOGRAPHIC
- ALPHA_NOVIDEO
- ALPHA_NO_SATURATION
- ALPHA_ONE
- ALPHA_PER_PIX
- ALPHA_PER_PIX_GLOBAL
- ALPHA_PLANE_BR
- ALPHA_PLANE_BR_BOTTOM_MASK
- ALPHA_PLANE_BR_RIGHT_MASK
- ALPHA_PLANE_TL
- ALPHA_PLANE_TL_LEFT_MASK
- ALPHA_PLANE_TL_TOP_MASK
- ALPHA_PLL_ACK_LATCH
- ALPHA_REG
- ALPHA_REG_16BIT_WIDTH
- ALPHA_REG_BITWIDTH
- ALPHA_RESTORE_SRM_SETUP
- ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
- ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
- ALPHA_SATURATION
- ALPHA_SCALE
- ALPHA_SHIFT
- ALPHA_SRC
- ALPHA_SRC_GLOBAL
- ALPHA_SRC_INVERSE
- ALPHA_SRC_NO_PRE_MUL
- ALPHA_SRC_PRE_MUL
- ALPHA_START
- ALPHA_STRAIGHT
- ALPHA_TST_CNTL
- ALPHA_WARNING
- ALPHA_XL_MAX_ISA_DMA_ADDRESS
- ALPHA_X_INC
- ALPHA_Y_INC
- ALPHA_ZERO
- ALPINE_CPU_RESUME_H_
- ALPINE_MSIX_SPI_TARGET_CLUSTER0
- ALPS_BUTTONPAD
- ALPS_CMD_NIBBLE_10
- ALPS_DUALPOINT
- ALPS_DUALPOINT_WITH_PRESSURE
- ALPS_FOUR_BUTTONS
- ALPS_FW_BK_1
- ALPS_FW_BK_2
- ALPS_PASS
- ALPS_PROTO_V1
- ALPS_PROTO_V2
- ALPS_PROTO_V3
- ALPS_PROTO_V3_RUSHMORE
- ALPS_PROTO_V4
- ALPS_PROTO_V5
- ALPS_PROTO_V6
- ALPS_PROTO_V7
- ALPS_PROTO_V8
- ALPS_PROTO_V9
- ALPS_PS2_INTERLEAVED
- ALPS_QUIRK_TRACKSTICK_BUTTONS
- ALPS_REG_BASE_PINNACLE
- ALPS_REG_BASE_RUSHMORE
- ALPS_REG_BASE_V7
- ALPS_STICK_BITS
- ALPS_WHEEL
- ALP_CLOCK
- ALREADYACTIVE_SWITCH
- ALRM1_OV_VOLT_SHUTDOWN
- ALRM1_POWER_LIMIT
- ALRM1_PRIMARY_FAULT
- ALRM1_TEMP_SHUTDOWN
- ALRM1_TEMP_WARNING
- ALRM1_VIN_OUT_LIMIT
- ALRM1_VIN_OVERCURRENT
- ALRM1_VOUT_OUT_LIMIT
- ALRM2_5V_OUT_LIMIT
- ALRM2_DCDC_TEMP_HIGH
- ALRM2_FAN_FAULT
- ALRM2_NO_PRIMARY
- ALRM2_OV_LOW
- ALRM2_PRI_TEMP_HIGH
- ALRM2_TEMP_FAULT
- ALRM_DAY_A1E
- ALRM_DAY_A2E
- ALRM_DISABLE
- ALRM_HR_A1E
- ALRM_HR_A2E
- ALRM_MIN_A1E
- ALRM_MIN_A2E
- ALRM_MON_A1E
- ALRM_SEC_A1E
- ALR_STS_MAKE_PEND
- ALS
- ALS300P_DRAM_IRQ_STATUS
- ALS300P_IRQ_STATUS
- ALS300_IRQ_STATUS
- ALS4000_FORMAT_16BIT
- ALS4000_FORMAT_SIGNED
- ALS4000_FORMAT_STEREO
- ALS4K_CR0_DMA_90H_MODE_CTRL
- ALS4K_CR0_DMA_CONTIN_MODE_CTRL
- ALS4K_CR0_MX80_81_REG_WRITE_ENABLE
- ALS4K_CR0_SB_CONFIG
- ALS4K_CR17_FIFO_STATUS
- ALS4K_CR18_ESP_MAJOR_VERSION
- ALS4K_CR19_ESP_MINOR_VERSION
- ALS4K_CR1A_MPU401_UART_MODE_CONTROL
- ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO
- ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI
- ALS4K_CR1E_FIFO2_CONTROL
- ALS4K_CR2_MISC_CONTROL
- ALS4K_CR3A_MISC_CONTROL
- ALS4K_CR3B_CRC32_BYTE0
- ALS4K_CR3C_CRC32_BYTE1
- ALS4K_CR3D_CRC32_BYTE2
- ALS4K_CR3E_CRC32_BYTE3
- ALS4K_CR3_CONFIGURATION
- ALS4K_GCR8C_CHIP_REV_MASK
- ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE
- ALS4K_GCR8C_MISC_CTRL
- ALS4K_GCR90_TEST_MODE_REG
- ALS4K_GCR91_DMA0_ADDR
- ALS4K_GCR92_DMA0_MODE_COUNT
- ALS4K_GCR93_DMA1_ADDR
- ALS4K_GCR94_DMA1_MODE_COUNT
- ALS4K_GCR95_DMA3_ADDR
- ALS4K_GCR96_DMA3_MODE_COUNT
- ALS4K_GCR99_DMA_EMULATION_CTRL
- ALS4K_GCRA0_FIFO1_CURRENT_ADDR
- ALS4K_GCRA1_FIFO1_STATUS_BYTECOUNT
- ALS4K_GCRA2_FIFO2_PCIADDR
- ALS4K_GCRA3_FIFO2_COUNT
- ALS4K_GCRA4_FIFO2_CURRENT_ADDR
- ALS4K_GCRA5_FIFO1_STATUS_BYTECOUNT
- ALS4K_GCRA6_PM_CTRL
- ALS4K_GCRA7_PCI_ACCESS_STORAGE
- ALS4K_GCRA8_LEGACY_CFG1
- ALS4K_GCRA9_LEGACY_CFG2
- ALS4K_GCRFF_DUMMY_SCRATCH
- ALS4K_IOB_06_AC97_STATUS
- ALS4K_IOB_07_IRQSTATUS
- ALS4K_IOB_0C_GCR_INDEX
- ALS4K_IOB_0E_CR1E_IRQ
- ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU
- ALS4K_IOB_0E_MPU_IRQ
- ALS4K_IOB_0E_SB_DMA_IRQ
- ALS4K_IOB_10_ADLIB_ADDR0
- ALS4K_IOB_11_ADLIB_ADDR1
- ALS4K_IOB_12_ADLIB_ADDR2
- ALS4K_IOB_13_ADLIB_ADDR3
- ALS4K_IOB_14_MIXER_INDEX
- ALS4K_IOB_15_MIXER_DATA
- ALS4K_IOB_16_ACK_FOR_CR1E
- ALS4K_IOB_16_ESP_RESET
- ALS4K_IOB_18_OPL_ADDR0
- ALS4K_IOB_19_OPL_ADDR1
- ALS4K_IOB_1A_ESP_RD_DATA
- ALS4K_IOB_1C_ESP_CMD_DATA
- ALS4K_IOB_1C_ESP_WR_STATUS
- ALS4K_IOB_1E_ESP_RD_STATUS8
- ALS4K_IOB_1F_ESP_RD_STATUS16
- ALS4K_IOB_20_ESP_GAMEPORT_200
- ALS4K_IOB_21_ESP_GAMEPORT_201
- ALS4K_IOB_30_MIDI_DATA
- ALS4K_IOB_31_MIDI_COMMAND
- ALS4K_IOB_31_MIDI_STATUS
- ALS4K_IOD_00_AC97_ACCESS
- ALS4K_IOD_08_GCR_DATA
- ALS4K_IOW_04_AC97_READ
- ALS4K_IRQTYPE_CR1E_DMA
- ALSA_CAPTURE_OPEN
- ALSA_CAPTURE_RUNNING
- ALSA_PLAYBACK_OPEN
- ALSA_PLAYBACK_RUNNING
- ALSPRX
- ALSPRX2
- ALST
- ALSZ
- ALS_ATTR
- ALS_CCFG_VAL
- ALS_CMPR_CFG_VAL
- ALS_HYSTERESIS_ATTR_RO
- ALS_MAX_RANGE_VAL
- ALS_MIN_RANGE_VAL
- ALS_TARGET_ATTR_RW
- ALS_THRESH_FALLING_ATTR_RW
- ALS_THRESH_RAISING_ATTR_RW
- ALT0
- ALT1
- ALT2
- ALT3
- ALT4
- ALT5
- ALT6
- ALT7
- ALTCIOADR
- ALTDMODE
- ALTELECTRICALSEL
- ALTERA_BUFFER_SIZE
- ALTERA_CVP_MGR_NAME
- ALTERA_CVP_V1_SIZE
- ALTERA_CVP_V2_SIZE
- ALTERA_DTYPE_MSGDMA
- ALTERA_DTYPE_SGDMA
- ALTERA_EXPRT_H
- ALTERA_GPIO_DATA
- ALTERA_GPIO_DIR
- ALTERA_GPIO_EDGE_CAP
- ALTERA_GPIO_IRQ_MASK
- ALTERA_GPIO_MAX_NGPIO
- ALTERA_JTAGUART_CONSOLE
- ALTERA_JTAGUART_CONTROL_AC_MSK
- ALTERA_JTAGUART_CONTROL_REG
- ALTERA_JTAGUART_CONTROL_RE_MSK
- ALTERA_JTAGUART_CONTROL_RI_MSK
- ALTERA_JTAGUART_CONTROL_RI_OFF
- ALTERA_JTAGUART_CONTROL_WE_MSK
- ALTERA_JTAGUART_CONTROL_WI_MSK
- ALTERA_JTAGUART_CONTROL_WSPACE_MSK
- ALTERA_JTAGUART_CONTROL_WSPACE_OFF
- ALTERA_JTAGUART_DATA_DATA_MSK
- ALTERA_JTAGUART_DATA_RAVAIL_MSK
- ALTERA_JTAGUART_DATA_RAVAIL_OFF
- ALTERA_JTAGUART_DATA_REG
- ALTERA_JTAGUART_DATA_RVALID_MSK
- ALTERA_JTAGUART_MAJOR
- ALTERA_JTAGUART_MAXPORTS
- ALTERA_JTAGUART_MINOR
- ALTERA_JTAGUART_SIZE
- ALTERA_JTAG_H
- ALTERA_MESSAGE_LENGTH
- ALTERA_PCIE_V1
- ALTERA_PCIE_V2
- ALTERA_REQUEST_SIZE
- ALTERA_RXDMABUFFER_SIZE
- ALTERA_SPI_CONTROL
- ALTERA_SPI_CONTROL_IE_MSK
- ALTERA_SPI_CONTROL_IROE_MSK
- ALTERA_SPI_CONTROL_IRRDY_MSK
- ALTERA_SPI_CONTROL_ITOE_MSK
- ALTERA_SPI_CONTROL_ITRDY_MSK
- ALTERA_SPI_CONTROL_SSO_MSK
- ALTERA_SPI_RXDATA
- ALTERA_SPI_SLAVE_SEL
- ALTERA_SPI_STATUS
- ALTERA_SPI_STATUS_E_MSK
- ALTERA_SPI_STATUS_ROE_MSK
- ALTERA_SPI_STATUS_RRDY_MSK
- ALTERA_SPI_STATUS_TMT_MSK
- ALTERA_SPI_STATUS_TOE_MSK
- ALTERA_SPI_STATUS_TRDY_MSK
- ALTERA_SPI_TXDATA
- ALTERA_STACK_SIZE
- ALTERA_TIMER_CONTROL_CONT_MSK
- ALTERA_TIMER_CONTROL_ITO_MSK
- ALTERA_TIMER_CONTROL_REG
- ALTERA_TIMER_CONTROL_START_MSK
- ALTERA_TIMER_CONTROL_STOP_MSK
- ALTERA_TIMER_PERIODH_REG
- ALTERA_TIMER_PERIODL_REG
- ALTERA_TIMER_SNAPH_REG
- ALTERA_TIMER_SNAPL_REG
- ALTERA_TIMER_STATUS_REG
- ALTERA_TSE_MAC_FIFO_WIDTH
- ALTERA_TSE_PAUSE_QUANTA
- ALTERA_TSE_RESOURCE_NAME
- ALTERA_TSE_RX_ALMOST_EMPTY
- ALTERA_TSE_RX_ALMOST_FULL
- ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16
- ALTERA_TSE_RX_SECTION_EMPTY
- ALTERA_TSE_RX_SECTION_FULL
- ALTERA_TSE_SW_RESET_WATCHDOG_CNTR
- ALTERA_TSE_TX_ALMOST_EMPTY
- ALTERA_TSE_TX_ALMOST_FULL
- ALTERA_TSE_TX_CMD_STAT_OMIT_CRC
- ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16
- ALTERA_TSE_TX_IPG_LENGTH
- ALTERA_TSE_TX_SECTION_EMPTY
- ALTERA_TSE_TX_SECTION_FULL
- ALTERA_UART_CONSOLE
- ALTERA_UART_CONTROL_BRK_MSK
- ALTERA_UART_CONTROL_DCTS_MSK
- ALTERA_UART_CONTROL_EOP_MSK
- ALTERA_UART_CONTROL_E_MSK
- ALTERA_UART_CONTROL_FE_MSK
- ALTERA_UART_CONTROL_PE_MSK
- ALTERA_UART_CONTROL_REG
- ALTERA_UART_CONTROL_ROE_MSK
- ALTERA_UART_CONTROL_RRDY_MSK
- ALTERA_UART_CONTROL_RTS_MSK
- ALTERA_UART_CONTROL_TMT_MSK
- ALTERA_UART_CONTROL_TOE_MSK
- ALTERA_UART_CONTROL_TRBK_MSK
- ALTERA_UART_CONTROL_TRDY_MSK
- ALTERA_UART_DIVISOR_REG
- ALTERA_UART_EOP_REG
- ALTERA_UART_RXDATA_REG
- ALTERA_UART_SIZE
- ALTERA_UART_STATUS_BRK_MSK
- ALTERA_UART_STATUS_CTS_MSK
- ALTERA_UART_STATUS_DCTS_MSK
- ALTERA_UART_STATUS_EOP_MSK
- ALTERA_UART_STATUS_E_MSK
- ALTERA_UART_STATUS_FE_MSK
- ALTERA_UART_STATUS_PE_MSK
- ALTERA_UART_STATUS_REG
- ALTERA_UART_STATUS_ROE_MSK
- ALTERA_UART_STATUS_RRDY_MSK
- ALTERA_UART_STATUS_TMT_MSK
- ALTERA_UART_STATUS_TOE_MSK
- ALTERA_UART_STATUS_TRDY_MSK
- ALTERA_UART_TXDATA_REG
- ALTERNATE_FUNCTION
- ALTERNATE_FUNCTIONS
- ALTERNATIVE
- ALTERNATIVE_2
- ALTERNATIVE_3
- ALTERNATIVE_CB
- ALTERNATIVE_CODE
- ALTER_GAMA
- ALTI2_N3_PID
- ALTI2_VID
- ALTINSTR_ENTRY
- ALTINSTR_ENTRY_CB
- ALTINSTR_REPLACEMENT
- ALTMODE
- ALTMODEV
- ALTMODEV2
- ALTMODE_DISCOVERY_MAX
- ALTR_A10SR_BITS_PER_REGISTER
- ALTR_A10SR_FMCAB_REG
- ALTR_A10SR_HPS_RST_REG
- ALTR_A10SR_I2C_M_REG
- ALTR_A10SR_IN_VALID_RANGE_HI
- ALTR_A10SR_IN_VALID_RANGE_LO
- ALTR_A10SR_LED_REG
- ALTR_A10SR_LED_VALID_SHIFT
- ALTR_A10SR_NOP
- ALTR_A10SR_OUT_VALID_RANGE_HI
- ALTR_A10SR_OUT_VALID_RANGE_LO
- ALTR_A10SR_PBDSW_IRQ_REG
- ALTR_A10SR_PBDSW_REG
- ALTR_A10SR_PMBUS_REG
- ALTR_A10SR_PWR_GOOD1_REG
- ALTR_A10SR_PWR_GOOD2_REG
- ALTR_A10SR_PWR_GOOD3_REG
- ALTR_A10SR_REG_BIT
- ALTR_A10SR_REG_BIT_CHG
- ALTR_A10SR_REG_BIT_MASK
- ALTR_A10SR_REG_OFFSET
- ALTR_A10SR_SFPA_REG
- ALTR_A10SR_SFPB_REG
- ALTR_A10SR_USB_QSPI_REG
- ALTR_A10SR_VERSION_READ
- ALTR_A10SR_WARM_RST_REG
- ALTR_A10SR_WR_KEY_REG
- ALTR_A10_COMMON_ECC_EN_CTL
- ALTR_A10_ECC_CTRL_OFST
- ALTR_A10_ECC_DERRPENA
- ALTR_A10_ECC_DERRPENB
- ALTR_A10_ECC_EN
- ALTR_A10_ECC_ERRINTENR_OFST
- ALTR_A10_ECC_ERRINTENS_OFST
- ALTR_A10_ECC_ERRINTEN_OFST
- ALTR_A10_ECC_ERRPENA_MASK
- ALTR_A10_ECC_ERRPENB_MASK
- ALTR_A10_ECC_INITA
- ALTR_A10_ECC_INITB
- ALTR_A10_ECC_INITCOMPLETEA
- ALTR_A10_ECC_INITCOMPLETEB
- ALTR_A10_ECC_INITSTAT_OFST
- ALTR_A10_ECC_INIT_WATCHDOG_10US
- ALTR_A10_ECC_INTMODE
- ALTR_A10_ECC_INTMODE_OFST
- ALTR_A10_ECC_INTSTAT_OFST
- ALTR_A10_ECC_INTTEST_OFST
- ALTR_A10_ECC_SERRINTEN
- ALTR_A10_ECC_SERRPENA
- ALTR_A10_ECC_SERRPENB
- ALTR_A10_ECC_TDERRA
- ALTR_A10_ECC_TDERRB
- ALTR_A10_ECC_TSERRA
- ALTR_A10_ECC_TSERRB
- ALTR_A10_L2_ECC_CE_INJ_MASK
- ALTR_A10_L2_ECC_CLR_OFST
- ALTR_A10_L2_ECC_CTL_OFST
- ALTR_A10_L2_ECC_EN_CTL
- ALTR_A10_L2_ECC_INJ_OFST
- ALTR_A10_L2_ECC_MERR_CLR
- ALTR_A10_L2_ECC_MERR_PEND
- ALTR_A10_L2_ECC_SERR_CLR
- ALTR_A10_L2_ECC_SERR_PEND
- ALTR_A10_L2_ECC_STATUS
- ALTR_A10_L2_ECC_STAT_OFST
- ALTR_A10_L2_ECC_UE_INJ_MASK
- ALTR_A10_OCRAM_ECC_EN_CTL
- ALTR_A10_SDMMC_IRQ_MASK
- ALTR_I2C_ALL_IRQ
- ALTR_I2C_CTRL
- ALTR_I2C_CTRL_BSPEED
- ALTR_I2C_CTRL_EN
- ALTR_I2C_CTRL_RXT_SHFT
- ALTR_I2C_CTRL_TCT_SHFT
- ALTR_I2C_DFLT_FIFO_SZ
- ALTR_I2C_ISER
- ALTR_I2C_ISER_ARB_EN
- ALTR_I2C_ISER_NACK_EN
- ALTR_I2C_ISER_RXOF_EN
- ALTR_I2C_ISER_RXRDY_EN
- ALTR_I2C_ISER_TXRDY_EN
- ALTR_I2C_ISR
- ALTR_I2C_ISR_ARB
- ALTR_I2C_ISR_NACK
- ALTR_I2C_ISR_RXOF
- ALTR_I2C_ISR_RXRDY
- ALTR_I2C_ISR_TXRDY
- ALTR_I2C_RX_DATA
- ALTR_I2C_RX_FIFO_LVL
- ALTR_I2C_SCL_HIGH
- ALTR_I2C_SCL_LOW
- ALTR_I2C_SDA_HOLD
- ALTR_I2C_STATUS
- ALTR_I2C_STAT_CORE
- ALTR_I2C_TC_FIFO_LVL
- ALTR_I2C_TFR_CMD
- ALTR_I2C_TFR_CMD_RW_D
- ALTR_I2C_TFR_CMD_STA
- ALTR_I2C_TFR_CMD_STO
- ALTR_I2C_THRESHOLD
- ALTR_I2C_TIMEOUT
- ALTR_I2C_XFER_TIMEOUT
- ALTR_L2_ECC_EN
- ALTR_L2_ECC_INJD
- ALTR_L2_ECC_INJS
- ALTR_L2_ECC_REG_OFFSET
- ALTR_MAN_GRP_L2_ECC_OFFSET
- ALTR_MAN_GRP_OCRAM_ECC_OFFSET
- ALTR_OCRAM_CLEAR_ECC
- ALTR_OCRAM_ECC_EN
- ALTR_OCR_ECC_DERR
- ALTR_OCR_ECC_EN
- ALTR_OCR_ECC_INJD
- ALTR_OCR_ECC_INJS
- ALTR_OCR_ECC_REG_OFFSET
- ALTR_OCR_ECC_SERR
- ALTR_S10_DERR_ADDRA_OFST
- ALTR_S10_ECC_CTRL_SDRAM_OFST
- ALTR_S10_ECC_DERRPENA
- ALTR_S10_ECC_EN
- ALTR_S10_ECC_ERRINTENR_OFST
- ALTR_S10_ECC_ERRINTENS_OFST
- ALTR_S10_ECC_ERRINTEN_OFST
- ALTR_S10_ECC_ERRPENA_MASK
- ALTR_S10_ECC_INTMODE
- ALTR_S10_ECC_INTMODE_OFST
- ALTR_S10_ECC_INTSTAT_OFST
- ALTR_S10_ECC_INTTEST_OFST
- ALTR_S10_ECC_SERRINTEN
- ALTR_S10_ECC_SERRPENA
- ALTR_S10_ECC_TDERRA
- ALTR_S10_ECC_TDERRB
- ALTR_S10_ECC_TSERRA
- ALTR_S10_ECC_TSERRB
- ALTR_TIMER_COMPATIBLE
- ALTR_TRIGGER_READ_WRD_CNT
- ALTR_TRIG_L2C_BYTE_SIZE
- ALTR_TRIG_OCRAM_BYTE_SIZE
- ALTR_UE_TRIGGER_CHAR
- ALTSMODE
- ALTTAGINFO_LEN
- ALT_AD_RG
- ALT_CALGARY
- ALT_CODE_TYPE_PA_RISC_64
- ALT_CODE_TYPE_UNKNOWN
- ALT_COND_ALWAYS
- ALT_COND_NO_DCACHE
- ALT_COND_NO_ICACHE
- ALT_COND_NO_IOC_FDC
- ALT_COND_NO_SMP
- ALT_COND_NO_SPLIT_TLB
- ALT_COND_RUN_ON_QEMU
- ALT_CPU_FREQ
- ALT_CS
- ALT_DATA
- ALT_ENTRY_SIZE
- ALT_FEATURE_OFFSET
- ALT_FQ_FQID_MASK
- ALT_FTR_SECTION_END
- ALT_FTR_SECTION_END_IFCLR
- ALT_FTR_SECTION_END_IFSET
- ALT_FTR_SECTION_END_NESTED
- ALT_FTR_SECTION_END_NESTED_IFCLR
- ALT_FTR_SECTION_END_NESTED_IFSET
- ALT_FW_8051_NAME_ASIC
- ALT_FW_FABRIC_NAME
- ALT_FW_FTR_SECTION_END
- ALT_FW_FTR_SECTION_END_IFCLR
- ALT_FW_FTR_SECTION_END_IFSET
- ALT_FW_FTR_SECTION_END_NESTED
- ALT_FW_FTR_SECTION_END_NESTED_IFCLR
- ALT_FW_FTR_SECTION_END_NESTED_IFSET
- ALT_FW_PCIE_NAME
- ALT_FW_SBUS_NAME
- ALT_L3_REMAP_H2F_MSK
- ALT_L3_REMAP_LWH2F_MSK
- ALT_L3_REMAP_MPUZERO_MSK
- ALT_L3_REMAP_OFST
- ALT_LDST_PIN
- ALT_MAST_DIS
- ALT_MMU_FTR_SECTION_END
- ALT_MMU_FTR_SECTION_END_IFCLR
- ALT_MMU_FTR_SECTION_END_IFSET
- ALT_MMU_FTR_SECTION_END_NESTED
- ALT_MMU_FTR_SECTION_END_NESTED_IFCLR
- ALT_MMU_FTR_SECTION_END_NESTED_IFSET
- ALT_NAK_OUT_PACKETS
- ALT_NEW_LEN_OFFSET
- ALT_NEW_OFFSET
- ALT_ORIG_LEN_OFFSET
- ALT_ORIG_OFFSET
- ALT_ORIG_PTR
- ALT_OUT_SET_MAX_COMMANDS
- ALT_PIN_IN_SEL
- ALT_PIN_OUT_SEL
- ALT_PPS_PIN
- ALT_PR_CSR_OFST
- ALT_PR_CSR_PR_START
- ALT_PR_CSR_STATUS_BAD_BITS
- ALT_PR_CSR_STATUS_CRC_ERR
- ALT_PR_CSR_STATUS_MSK
- ALT_PR_CSR_STATUS_NRESET
- ALT_PR_CSR_STATUS_PR_ERR
- ALT_PR_CSR_STATUS_PR_IN_PROG
- ALT_PR_CSR_STATUS_PR_SUCCESS
- ALT_PR_CSR_STATUS_SFT
- ALT_PR_DATA_OFST
- ALT_RD
- ALT_RDY
- ALT_REPL_PTR
- ALT_SDR_CTL_FPGAPORTRST_CTRL_SHIFT
- ALT_SDR_CTL_FPGAPORTRST_OFST
- ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK
- ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT
- ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT
- ALT_SMB302_VERSION_STRING
- ALT_SMB311_VERSION_STRING
- ALT_SMP
- ALT_SYNC
- ALT_TCK
- ALT_TDI
- ALT_TDO
- ALT_UP
- ALT_UP_B
- ALT_WR
- ALU
- ALUA_ACCESS_STATE_ACTIVE_NON_OPTIMIZED
- ALUA_ACCESS_STATE_ACTIVE_OPTIMIZED
- ALUA_ACCESS_STATE_LBA_DEPENDENT
- ALUA_ACCESS_STATE_OFFLINE
- ALUA_ACCESS_STATE_STANDBY
- ALUA_ACCESS_STATE_TRANSITION
- ALUA_ACCESS_STATE_UNAVAILABLE
- ALUA_AN_SUP
- ALUA_AO_SUP
- ALUA_DEFAULT_IMPLICIT_TRANS_SECS
- ALUA_DEFAULT_NONOP_DELAY_MSECS
- ALUA_DEFAULT_TRANS_DELAY_MSECS
- ALUA_DH_NAME
- ALUA_DH_VER
- ALUA_FAILOVER_RETRIES
- ALUA_FAILOVER_TIMEOUT
- ALUA_LBD_SUP
- ALUA_MAX_IMPLICIT_TRANS_SECS
- ALUA_MAX_NONOP_DELAY_MSECS
- ALUA_MAX_TRANS_DELAY_MSECS
- ALUA_MD_BUF_LEN
- ALUA_OPTIMIZE_STPG
- ALUA_O_SUP
- ALUA_PG_RUNNING
- ALUA_PG_RUN_RTPG
- ALUA_PG_RUN_STPG
- ALUA_POLICY_SWITCH_ALL
- ALUA_POLICY_SWITCH_CURRENT
- ALUA_RTPG_DELAY_MSECS
- ALUA_RTPG_EXT_HDR_UNSUPP
- ALUA_RTPG_RETRY_DELAY
- ALUA_RTPG_SIZE
- ALUA_STATUS_ALTERED_BY_EXPLICIT_STPG
- ALUA_STATUS_ALTERED_BY_IMPLICIT_ALUA
- ALUA_STATUS_NONE
- ALUA_SUPPORTED_STATE_ATTR
- ALUA_S_SUP
- ALUA_T_SUP
- ALUA_U_SUP
- ALU_ACTION
- ALU_DIRECT
- ALU_DIRECT_INDEX_M
- ALU_DST_A
- ALU_DST_B
- ALU_FID_INDEX_S
- ALU_INST_PREFER_VECTOR
- ALU_MAC_ADDR_HI
- ALU_OP_ADD
- ALU_OP_ADD_2B
- ALU_OP_ADD_C
- ALU_OP_AND
- ALU_OP_AND_NOT_A
- ALU_OP_AND_NOT_B
- ALU_OP_NONE
- ALU_OP_NOT
- ALU_OP_OR
- ALU_OP_SUB
- ALU_OP_SUB_C
- ALU_OP_XOR
- ALU_OUT
- ALU_READ
- ALU_RESV_MCAST_ADDR
- ALU_RESV_MCAST_INDEX_M
- ALU_SEARCH
- ALU_START
- ALU_STAT_INDEX_M
- ALU_STAT_INDEX_S
- ALU_STAT_READ
- ALU_STAT_START
- ALU_UPDATE_FIFO_HIWATER
- ALU_VALID
- ALU_VALID_CNT_M
- ALU_VALID_CNT_S
- ALU_V_DST_FILTER
- ALU_V_FID_M
- ALU_V_FID_S
- ALU_V_MAC_ADDR_HI
- ALU_V_MSTP_M
- ALU_V_OVERRIDE
- ALU_V_PORT_MAP
- ALU_V_PRIO_AGE_CNT_M
- ALU_V_PRIO_AGE_CNT_S
- ALU_V_SRC_FILTER
- ALU_V_STATIC_VALID
- ALU_V_USE_FID
- ALU_WRITE
- ALWAYS
- ALWAYS_CALL_BUSY
- ALWAYS_CHECK_MII
- ALWAYS_ENABLED
- ALWAYS_ON
- ALWAYS_ON_FEATURES
- ALWAYS_ON_OFFLOADS
- ALWAYS_SET_DTC2278_PIO_MODE
- ALWAYS_SYNC
- ALX_ACER_FIXED_PTN0
- ALX_ACER_FIXED_PTN0_MASK
- ALX_ACER_FIXED_PTN0_SHIFT
- ALX_ACER_FIXED_PTN1
- ALX_ACER_FIXED_PTN1_MASK
- ALX_ACER_FIXED_PTN1_SHIFT
- ALX_ACER_MAGIC
- ALX_ACER_MAGIC_EN
- ALX_ACER_MAGIC_FF_CHECK
- ALX_ACER_MAGIC_FIX_LEN_MASK
- ALX_ACER_MAGIC_FIX_LEN_SHIFT
- ALX_ACER_MAGIC_MATCH
- ALX_ACER_MAGIC_PME_EN
- ALX_ACER_MAGIC_RAN_LEN_MASK
- ALX_ACER_MAGIC_RAN_LEN_SHIFT
- ALX_ACER_RANDOM_NUM0
- ALX_ACER_RANDOM_NUM0_MASK
- ALX_ACER_RANDOM_NUM0_SHIFT
- ALX_ACER_RANDOM_NUM1
- ALX_ACER_RANDOM_NUM1_MASK
- ALX_ACER_RANDOM_NUM1_SHIFT
- ALX_ACER_RANDOM_NUM2
- ALX_ACER_RANDOM_NUM2_MASK
- ALX_ACER_RANDOM_NUM2_SHIFT
- ALX_ACER_RANDOM_NUM3
- ALX_ACER_RANDOM_NUM3_MASK
- ALX_ACER_RANDOM_NUM3_SHIFT
- ALX_ACER_TIMER
- ALX_ACER_TIMER_EN
- ALX_ACER_TIMER_MATCH
- ALX_ACER_TIMER_PME_EN
- ALX_ACER_TIMER_THRES_DEF
- ALX_ACER_TIMER_THRES_MASK
- ALX_ACER_TIMER_THRES_SHIFT
- ALX_AFE_10BT_100M_TH
- ALX_AGC_2_VGA_MASK
- ALX_AGC_2_VGA_SHIFT
- ALX_AGC_LONG100M_LIMT
- ALX_AGC_LONG1G_LIMT
- ALX_ANACTRL_DEF
- ALX_AZ_ANADECT_DEF
- ALX_AZ_ANADECT_LONG
- ALX_CLDCTRL3_BP_CABLE1TH_DET_GT
- ALX_CLDCTRL5_BP_VD_HLFBIAS
- ALX_CLDCTRL6_CAB_LEN_MASK
- ALX_CLDCTRL6_CAB_LEN_SHIFT
- ALX_CLDCTRL6_CAB_LEN_SHORT100M
- ALX_CLDCTRL6_CAB_LEN_SHORT1G
- ALX_CLK_GATE
- ALX_CLK_GATE_ALL
- ALX_CLK_GATE_DMAR
- ALX_CLK_GATE_DMAW
- ALX_CLK_GATE_RXMAC
- ALX_CLK_GATE_RXQ
- ALX_CLK_GATE_TXMAC
- ALX_CLK_GATE_TXQ
- ALX_DEFAULT_TX_WORK
- ALX_DEF_RXBUF_SIZE
- ALX_DEV_CTRL
- ALX_DEV_CTRL_MAXRRS_MIN
- ALX_DEV_ID_AR8161
- ALX_DEV_ID_AR8162
- ALX_DEV_ID_AR8171
- ALX_DEV_ID_AR8172
- ALX_DEV_ID_E2200
- ALX_DEV_ID_E2400
- ALX_DEV_ID_E2500
- ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG
- ALX_DMA
- ALX_DMA_MAC_RST_TO
- ALX_DMA_RCHNL_SEL_MASK
- ALX_DMA_RCHNL_SEL_SHIFT
- ALX_DMA_RDLY_CNT_DEF
- ALX_DMA_RDLY_CNT_MASK
- ALX_DMA_RDLY_CNT_SHIFT
- ALX_DMA_RORDER_MODE_MASK
- ALX_DMA_RORDER_MODE_OUT
- ALX_DMA_RORDER_MODE_SHIFT
- ALX_DMA_RREQ_BLEN_MASK
- ALX_DMA_RREQ_BLEN_SHIFT
- ALX_DMA_RREQ_PRI_DATA
- ALX_DMA_WDLY_CNT_DEF
- ALX_DMA_WDLY_CNT_MASK
- ALX_DMA_WDLY_CNT_SHIFT
- ALX_DRV
- ALX_DRV_PHY_10
- ALX_DRV_PHY_100
- ALX_DRV_PHY_1000
- ALX_DRV_PHY_AUTO
- ALX_DRV_PHY_DUPLEX
- ALX_DRV_PHY_MASK
- ALX_DRV_PHY_PAUSE
- ALX_DRV_PHY_SHIFT
- ALX_DRV_PHY_UNKNOWN
- ALX_EFLD
- ALX_EFLD_E_EXIST
- ALX_EFLD_F_EXIST
- ALX_EFLD_START
- ALX_EFLD_STAT
- ALX_FC_ANEG
- ALX_FC_RX
- ALX_FC_TX
- ALX_FRAME_PAD
- ALX_GET_FIELD
- ALX_GIGA_PSSR_1000MBS
- ALX_GIGA_PSSR_100MBS
- ALX_GIGA_PSSR_10MBS
- ALX_GIGA_PSSR_DPLX
- ALX_GIGA_PSSR_SPD_DPLX_RESOLVED
- ALX_GIGA_PSSR_SPEED
- ALX_GREENCFG2_BP_GREEN
- ALX_GREENCFG2_GATE_DFSE_EN
- ALX_GREENCFG_DEF
- ALX_HASH_TBL0
- ALX_HASH_TBL1
- ALX_HIBNEG_DEF
- ALX_HIBNEG_HIB_PSE
- ALX_HIBNEG_NOHIB
- ALX_HIBNEG_PSHIB_EN
- ALX_HQTPD
- ALX_HQTPD_BURST_EN
- ALX_HQTPD_Q1_NUMPREF_MASK
- ALX_HQTPD_Q1_NUMPREF_SHIFT
- ALX_HQTPD_Q2_NUMPREF_MASK
- ALX_HQTPD_Q2_NUMPREF_SHIFT
- ALX_HQTPD_Q3_NUMPREF_MASK
- ALX_HQTPD_Q3_NUMPREF_SHIFT
- ALX_HRTBT_EXT_CTRL
- ALX_HRTBT_EXT_CTRL_ARP_EN
- ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK
- ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT
- ALX_HRTBT_EXT_CTRL_IS_8023
- ALX_HRTBT_EXT_CTRL_IS_IPV6
- ALX_HRTBT_EXT_CTRL_NS_EN
- ALX_HRTBT_EXT_CTRL_WAKEUP_EN
- ALX_HRTBT_HOST_IPV4_ADDR
- ALX_HRTBT_REM_IPV4_ADDR
- ALX_HRTBT_REM_IPV6_ADDR0
- ALX_HRTBT_REM_IPV6_ADDR1
- ALX_HRTBT_REM_IPV6_ADDR2
- ALX_HRTBT_REM_IPV6_ADDR3
- ALX_HW_H_
- ALX_IDLE_DECISN_TIMER
- ALX_IDLE_DECISN_TIMER_DEF
- ALX_IER_LINK_DOWN
- ALX_IER_LINK_UP
- ALX_IMR
- ALX_INT_RETRIG
- ALX_INT_RETRIG_TO
- ALX_IRQ_MODU_TIMER
- ALX_IRQ_MODU_TIMER1_MASK
- ALX_IRQ_MODU_TIMER1_SHIFT
- ALX_ISR
- ALX_ISR_ALERT
- ALX_ISR_ALL_QUEUES
- ALX_ISR_DIS
- ALX_ISR_DMAR
- ALX_ISR_DMAW
- ALX_ISR_FATAL
- ALX_ISR_MANU
- ALX_ISR_MISC
- ALX_ISR_PCIE_LNKDOWN
- ALX_ISR_PHY
- ALX_ISR_RFD_UR
- ALX_ISR_RXF_OV
- ALX_ISR_RX_Q0
- ALX_ISR_RX_Q1
- ALX_ISR_RX_Q2
- ALX_ISR_RX_Q3
- ALX_ISR_RX_Q4
- ALX_ISR_RX_Q5
- ALX_ISR_RX_Q6
- ALX_ISR_RX_Q7
- ALX_ISR_SMB
- ALX_ISR_TIMER
- ALX_ISR_TXF_UR
- ALX_ISR_TX_Q0
- ALX_ISR_TX_Q1
- ALX_ISR_TX_Q2
- ALX_ISR_TX_Q3
- ALX_LEGCYPS_DEF
- ALX_LEGCYPS_EN
- ALX_LOCAL_EEEADV_1000BT
- ALX_LOCAL_EEEADV_100BT
- ALX_LPI_CTRL
- ALX_LPI_CTRL_EN
- ALX_MAC_CTRL
- ALX_MAC_CTRL_BRD_EN
- ALX_MAC_CTRL_CRCE
- ALX_MAC_CTRL_FAST_PAUSE
- ALX_MAC_CTRL_FULLD
- ALX_MAC_CTRL_MHASH_ALG_HI5B
- ALX_MAC_CTRL_MULTIALL_EN
- ALX_MAC_CTRL_PCRCE
- ALX_MAC_CTRL_PRMBLEN_MASK
- ALX_MAC_CTRL_PRMBLEN_SHIFT
- ALX_MAC_CTRL_PROMISC_EN
- ALX_MAC_CTRL_RXFC_EN
- ALX_MAC_CTRL_RX_EN
- ALX_MAC_CTRL_SPEED_1000
- ALX_MAC_CTRL_SPEED_10_100
- ALX_MAC_CTRL_SPEED_MASK
- ALX_MAC_CTRL_SPEED_SHIFT
- ALX_MAC_CTRL_TXFC_EN
- ALX_MAC_CTRL_TX_EN
- ALX_MAC_CTRL_VLANSTRIP
- ALX_MAC_CTRL_WOLSPED_SWEN
- ALX_MAC_STS
- ALX_MAC_STS_IDLE
- ALX_MAC_STS_RXMAC_BUSY
- ALX_MAC_STS_RXQ_BUSY
- ALX_MAC_STS_TXMAC_BUSY
- ALX_MAC_STS_TXQ_BUSY
- ALX_MASTER
- ALX_MASTER_DMA_MAC_RST
- ALX_MASTER_IRQMOD1_EN
- ALX_MASTER_IRQMOD2_EN
- ALX_MASTER_OOB_DIS
- ALX_MASTER_PCLKSEL_SRDS
- ALX_MASTER_SYSALVTIMER_EN
- ALX_MASTER_WAKEN_25M
- ALX_MAX_FRAME_LEN
- ALX_MAX_FRAME_SIZE
- ALX_MAX_HANDLED_INTRS
- ALX_MAX_JUMBO_PKT_SIZE
- ALX_MAX_MSIX_INTRS
- ALX_MAX_NAPIS
- ALX_MAX_RX_QUEUES
- ALX_MAX_SETUP_LNK_CYCLE
- ALX_MAX_TSO_PKT_SIZE
- ALX_MAX_TX_QUEUES
- ALX_MDIO
- ALX_MDIO_BUSY
- ALX_MDIO_CLK_SEL_25MD128
- ALX_MDIO_CLK_SEL_25MD4
- ALX_MDIO_CLK_SEL_MASK
- ALX_MDIO_CLK_SEL_SHIFT
- ALX_MDIO_DATA_MASK
- ALX_MDIO_DATA_SHIFT
- ALX_MDIO_EXTN
- ALX_MDIO_EXTN_DEVAD_MASK
- ALX_MDIO_EXTN_DEVAD_SHIFT
- ALX_MDIO_EXTN_REG_MASK
- ALX_MDIO_EXTN_REG_SHIFT
- ALX_MDIO_MAX_AC_TO
- ALX_MDIO_MODE_EXT
- ALX_MDIO_OP_READ
- ALX_MDIO_REG_MASK
- ALX_MDIO_REG_SHIFT
- ALX_MDIO_SPRES_PRMBL
- ALX_MDIO_START
- ALX_MIB_BASE
- ALX_MIB_RX_ALIGN_ERR
- ALX_MIB_RX_BCAST
- ALX_MIB_RX_BCCNT
- ALX_MIB_RX_BYTE_CNT
- ALX_MIB_RX_CTRL
- ALX_MIB_RX_ERRADDR
- ALX_MIB_RX_FCS_ERR
- ALX_MIB_RX_FRAG
- ALX_MIB_RX_LEN_ERR
- ALX_MIB_RX_MCAST
- ALX_MIB_RX_MCCNT
- ALX_MIB_RX_OK
- ALX_MIB_RX_OV_RRD
- ALX_MIB_RX_OV_RXF
- ALX_MIB_RX_OV_SZ
- ALX_MIB_RX_PAUSE
- ALX_MIB_RX_RUNT
- ALX_MIB_RX_SZ_1023B
- ALX_MIB_RX_SZ_127B
- ALX_MIB_RX_SZ_1518B
- ALX_MIB_RX_SZ_255B
- ALX_MIB_RX_SZ_511B
- ALX_MIB_RX_SZ_64B
- ALX_MIB_RX_SZ_MAX
- ALX_MIB_TX_ABORT_COL
- ALX_MIB_TX_BCAST
- ALX_MIB_TX_BCCNT
- ALX_MIB_TX_BYTE_CNT
- ALX_MIB_TX_CTRL
- ALX_MIB_TX_DEFER
- ALX_MIB_TX_EXC_DEFER
- ALX_MIB_TX_LATE_COL
- ALX_MIB_TX_LEN_ERR
- ALX_MIB_TX_MCAST
- ALX_MIB_TX_MCCNT
- ALX_MIB_TX_MULTI_COL
- ALX_MIB_TX_OK
- ALX_MIB_TX_PAUSE
- ALX_MIB_TX_SINGLE_COL
- ALX_MIB_TX_SZ_1023B
- ALX_MIB_TX_SZ_127B
- ALX_MIB_TX_SZ_1518B
- ALX_MIB_TX_SZ_255B
- ALX_MIB_TX_SZ_511B
- ALX_MIB_TX_SZ_64B
- ALX_MIB_TX_SZ_MAX
- ALX_MIB_TX_TRD_EOP
- ALX_MIB_TX_TRUNC
- ALX_MIB_TX_UNDERRUN
- ALX_MIB_UPDATE
- ALX_MIIDBG_AGC
- ALX_MIIDBG_ANACTRL
- ALX_MIIDBG_AZ_ANADECT
- ALX_MIIDBG_GREENCFG
- ALX_MIIDBG_GREENCFG2
- ALX_MIIDBG_HIBNEG
- ALX_MIIDBG_LEGCYPS
- ALX_MIIDBG_MSE16DB
- ALX_MIIDBG_MSE20DB
- ALX_MIIDBG_SRDSYSMOD
- ALX_MIIDBG_SYSMODCTRL
- ALX_MIIDBG_TST100BTCFG
- ALX_MIIDBG_TST10BTCFG
- ALX_MIIEXT_AFE
- ALX_MIIEXT_ANEG
- ALX_MIIEXT_CLDCTRL3
- ALX_MIIEXT_CLDCTRL5
- ALX_MIIEXT_CLDCTRL6
- ALX_MIIEXT_LOCAL_EEEADV
- ALX_MIIEXT_NLP78
- ALX_MIIEXT_NLP78_120M_DEF
- ALX_MIIEXT_PCS
- ALX_MIIEXT_S3DIG10
- ALX_MIIEXT_S3DIG10_DEF
- ALX_MIIEXT_S3DIG10_SL
- ALX_MIIEXT_VDRVBIAS
- ALX_MII_DBG_ADDR
- ALX_MII_DBG_DATA
- ALX_MII_GIGA_PSSR
- ALX_MII_IER
- ALX_MII_ISR
- ALX_MISC
- ALX_MISC3
- ALX_MISC3_25M_BY_SW
- ALX_MISC3_25M_NOTO_INTNL
- ALX_MISC_INTNLOSC_OPEN
- ALX_MISC_ISO_EN
- ALX_MISC_PSW_OCP_DEF
- ALX_MISC_PSW_OCP_MASK
- ALX_MISC_PSW_OCP_SHIFT
- ALX_MSE16DB_DOWN
- ALX_MSE16DB_UP
- ALX_MSE20DB_TH_DEF
- ALX_MSE20DB_TH_HI
- ALX_MSE20DB_TH_MASK
- ALX_MSE20DB_TH_SHIFT
- ALX_MSIC2
- ALX_MSIC2_CALB_START
- ALX_MSIX_ENTRY_BASE
- ALX_MSIX_MASK
- ALX_MSI_ID_MAP
- ALX_MSI_MAP_TBL1
- ALX_MSI_MAP_TBL1_RXQ0_SHIFT
- ALX_MSI_MAP_TBL1_RXQ1_SHIFT
- ALX_MSI_MAP_TBL1_RXQ2_SHIFT
- ALX_MSI_MAP_TBL1_RXQ3_SHIFT
- ALX_MSI_MAP_TBL1_TXQ0_SHIFT
- ALX_MSI_MAP_TBL1_TXQ1_SHIFT
- ALX_MSI_MAP_TBL2
- ALX_MSI_MAP_TBL2_RXQ4_SHIFT
- ALX_MSI_MAP_TBL2_RXQ5_SHIFT
- ALX_MSI_MAP_TBL2_RXQ6_SHIFT
- ALX_MSI_MAP_TBL2_RXQ7_SHIFT
- ALX_MSI_MAP_TBL2_TXQ2_SHIFT
- ALX_MSI_MAP_TBL2_TXQ3_SHIFT
- ALX_MSI_MASK_SEL_LINE
- ALX_MSI_RETRANS_TIMER
- ALX_MSI_RETRANS_TM_MASK
- ALX_MSI_RETRANS_TM_SHIFT
- ALX_MTU
- ALX_MTU_JUMBO_TH
- ALX_MTU_STD_ALGN
- ALX_NUM_STATS
- ALX_PCI_CMD
- ALX_PCI_REVID_SHIFT
- ALX_PDLL_TRNS1
- ALX_PDLL_TRNS1_D3PLLOFF_EN
- ALX_PHY_CTRL
- ALX_PHY_CTRL_100AB_EN
- ALX_PHY_CTRL_CLS
- ALX_PHY_CTRL_DSPRST_OUT
- ALX_PHY_CTRL_DSPRST_TO
- ALX_PHY_CTRL_GATE_25M
- ALX_PHY_CTRL_HIB_EN
- ALX_PHY_CTRL_HIB_PULSE
- ALX_PHY_CTRL_IDDQ
- ALX_PHY_CTRL_LED_MODE
- ALX_PHY_CTRL_PLL_ON
- ALX_PHY_CTRL_POWER_DOWN
- ALX_PHY_CTRL_RST_ANALOG
- ALX_PHY_INITED
- ALX_PMCTRL
- ALX_PMCTRL_ASPM_FCEN
- ALX_PMCTRL_HOTRST_WTEN
- ALX_PMCTRL_L0S_EN
- ALX_PMCTRL_L1REG_TO_DEF
- ALX_PMCTRL_L1REQ_TO_MASK
- ALX_PMCTRL_L1REQ_TO_SHIFT
- ALX_PMCTRL_L1_BUFSRX_EN
- ALX_PMCTRL_L1_CLKSW_EN
- ALX_PMCTRL_L1_EN
- ALX_PMCTRL_L1_SRDSPLL_EN
- ALX_PMCTRL_L1_SRDSRX_PWD
- ALX_PMCTRL_L1_SRDS_EN
- ALX_PMCTRL_L1_TIMER_16US
- ALX_PMCTRL_L1_TIMER_MASK
- ALX_PMCTRL_L1_TIMER_SHIFT
- ALX_PMCTRL_LCKDET_TIMER_DEF
- ALX_PMCTRL_LCKDET_TIMER_MASK
- ALX_PMCTRL_LCKDET_TIMER_SHIFT
- ALX_PMCTRL_RCVR_WT_1US
- ALX_PMCTRL_RXL1_AFTER_L0S
- ALX_PMCTRL_SADLY_EN
- ALX_PMCTRL_TXL1_AFTER_L0S
- ALX_PM_OPS
- ALX_RAW_MTU
- ALX_REG_H
- ALX_REV_A0
- ALX_REV_A1
- ALX_REV_B0
- ALX_REV_C0
- ALX_RFD_ADDR_LO
- ALX_RFD_BUF_SZ
- ALX_RFD_CIDX
- ALX_RFD_PIDX
- ALX_RFD_RING_SZ
- ALX_RRD_ADDR_LO
- ALX_RRD_RING_SZ
- ALX_RSS_HASH_TYPE_ALL
- ALX_RSS_HASH_TYPE_IPV4
- ALX_RSS_HASH_TYPE_IPV4_TCP
- ALX_RSS_HASH_TYPE_IPV6
- ALX_RSS_HASH_TYPE_IPV6_TCP
- ALX_RSS_IDT_TBL0
- ALX_RSS_KEY0
- ALX_RSS_KEY1
- ALX_RSS_KEY2
- ALX_RSS_KEY3
- ALX_RSS_KEY4
- ALX_RSS_KEY5
- ALX_RSS_KEY6
- ALX_RSS_KEY7
- ALX_RSS_KEY8
- ALX_RSS_KEY9
- ALX_RXQ0
- ALX_RXQ0_ASPM_THRESH_100M
- ALX_RXQ0_ASPM_THRESH_MASK
- ALX_RXQ0_ASPM_THRESH_SHIFT
- ALX_RXQ0_EN
- ALX_RXQ0_IDT_TBL_SIZE_DEF
- ALX_RXQ0_IDT_TBL_SIZE_MASK
- ALX_RXQ0_IDT_TBL_SIZE_NORMAL
- ALX_RXQ0_IDT_TBL_SIZE_SHIFT
- ALX_RXQ0_IPV6_PARSE_EN
- ALX_RXQ0_NUM_RFD_PREF_DEF
- ALX_RXQ0_NUM_RFD_PREF_MASK
- ALX_RXQ0_NUM_RFD_PREF_SHIFT
- ALX_RXQ0_RSS_HASH_EN
- ALX_RXQ0_RSS_HSTYP_ALL
- ALX_RXQ0_RSS_HSTYP_IPV4_EN
- ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN
- ALX_RXQ0_RSS_HSTYP_IPV6_EN
- ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN
- ALX_RXQ0_RSS_HSTYP_MASK
- ALX_RXQ0_RSS_HSTYP_SHIFT
- ALX_RXQ0_RSS_MODE_DIS
- ALX_RXQ0_RSS_MODE_MASK
- ALX_RXQ0_RSS_MODE_MQMI
- ALX_RXQ0_RSS_MODE_SHIFT
- ALX_RXQ2
- ALX_RXQ2_RXF_FLOW_CTRL_RSVD
- ALX_RXQ2_RXF_XOFF_THRESH_MASK
- ALX_RXQ2_RXF_XOFF_THRESH_SHIFT
- ALX_RXQ2_RXF_XON_THRESH_MASK
- ALX_RXQ2_RXF_XON_THRESH_SHIFT
- ALX_RX_ALLOC_THRESH
- ALX_RX_BASE_ADDR_HI
- ALX_SERDES
- ALX_SERDES_MACCLK_SLWDWN
- ALX_SERDES_PHYCLK_SLWDWN
- ALX_SET_FIELD
- ALX_SLD
- ALX_SLD_MAX_TO
- ALX_SLD_START
- ALX_SLD_STAT
- ALX_SLEEP_ACTIVE
- ALX_SLEEP_CIFS
- ALX_SLEEP_WOL_MAGIC
- ALX_SLEEP_WOL_PHY
- ALX_SMB_TIMER
- ALX_SRAM5
- ALX_SRAM9
- ALX_SRAM_LOAD_PTR
- ALX_SRAM_RXF_LEN_8K
- ALX_SRAM_RXF_LEN_MASK
- ALX_SRAM_RXF_LEN_SHIFT
- ALX_SRDSYSMOD_DEEMP_EN
- ALX_SRDSYSMOD_DEF
- ALX_STAD0
- ALX_STAD1
- ALX_SWOI_ACER_CTRL
- ALX_SWOI_IOAC_CTRL_2
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK
- ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT
- ALX_SWOI_IOAC_CTRL_3
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK
- ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT
- ALX_SWOI_ORIG_ACK_ADDR_MASK
- ALX_SWOI_ORIG_ACK_ADDR_SHIFT
- ALX_SWOI_ORIG_ACK_NAK_EN
- ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK
- ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT
- ALX_SYSMODCTRL_IECHOADJ_DEF
- ALX_TINT_TIMER
- ALX_TINT_TPD_THRSHLD
- ALX_TPD_PRI0_ADDR_LO
- ALX_TPD_PRI0_CIDX
- ALX_TPD_PRI0_PIDX
- ALX_TPD_PRI1_ADDR_LO
- ALX_TPD_PRI1_CIDX
- ALX_TPD_PRI1_PIDX
- ALX_TPD_PRI2_ADDR_LO
- ALX_TPD_PRI2_CIDX
- ALX_TPD_PRI2_PIDX
- ALX_TPD_PRI3_ADDR_LO
- ALX_TPD_PRI3_CIDX
- ALX_TPD_PRI3_PIDX
- ALX_TPD_RING_SZ
- ALX_TST100BTCFG_DEF
- ALX_TST10BTCFG_DEF
- ALX_TXQ0
- ALX_TXQ0_EN
- ALX_TXQ0_LSO_8023_EN
- ALX_TXQ0_MODE_ENHANCE
- ALX_TXQ0_SUPT_IPOPT
- ALX_TXQ0_TPD_BURSTPREF_MASK
- ALX_TXQ0_TPD_BURSTPREF_SHIFT
- ALX_TXQ0_TXF_BURST_PREF_MASK
- ALX_TXQ0_TXF_BURST_PREF_SHIFT
- ALX_TXQ1
- ALX_TXQ1_ERRLGPKT_DROP_EN
- ALX_TXQ1_JUMBO_TSO_TH
- ALX_TXQ_TPD_BURSTPREF_DEF
- ALX_TXQ_TXF_BURST_PREF_DEF
- ALX_TX_BASE_ADDR_HI
- ALX_UE_SVRT
- ALX_UE_SVRT_DLPROTERR
- ALX_UE_SVRT_FCPROTERR
- ALX_VDRVBIAS_DEF
- ALX_WATCHDOG_TIME
- ALX_WOL0
- ALX_WOL0_LINK_EN
- ALX_WOL0_MAGIC_EN
- ALX_WOL0_PME_LINK
- ALX_WOL0_PME_MAGIC_EN
- ALX_WOL_CTRL2
- ALX_WOL_CTRL2_DATA_STORE
- ALX_WOL_CTRL2_PME_PTRN_EN
- ALX_WOL_CTRL2_PTRN_EN
- ALX_WOL_CTRL2_PTRN_EVT
- ALX_WOL_CTRL3
- ALX_WOL_CTRL3_PTRN_ADDR_MASK
- ALX_WOL_CTRL3_PTRN_ADDR_SHIFT
- ALX_WOL_CTRL4
- ALX_WOL_CTRL4_PT0_EN
- ALX_WOL_CTRL4_PT0_MATCH
- ALX_WOL_CTRL4_PT10_EN
- ALX_WOL_CTRL4_PT10_MATCH
- ALX_WOL_CTRL4_PT11_EN
- ALX_WOL_CTRL4_PT11_MATCH
- ALX_WOL_CTRL4_PT12_EN
- ALX_WOL_CTRL4_PT12_MATCH
- ALX_WOL_CTRL4_PT13_EN
- ALX_WOL_CTRL4_PT13_MATCH
- ALX_WOL_CTRL4_PT14_EN
- ALX_WOL_CTRL4_PT14_MATCH
- ALX_WOL_CTRL4_PT15_EN
- ALX_WOL_CTRL4_PT15_MATCH
- ALX_WOL_CTRL4_PT1_EN
- ALX_WOL_CTRL4_PT1_MATCH
- ALX_WOL_CTRL4_PT2_EN
- ALX_WOL_CTRL4_PT2_MATCH
- ALX_WOL_CTRL4_PT3_EN
- ALX_WOL_CTRL4_PT3_MATCH
- ALX_WOL_CTRL4_PT4_EN
- ALX_WOL_CTRL4_PT4_MATCH
- ALX_WOL_CTRL4_PT5_EN
- ALX_WOL_CTRL4_PT5_MATCH
- ALX_WOL_CTRL4_PT6_EN
- ALX_WOL_CTRL4_PT6_MATCH
- ALX_WOL_CTRL4_PT7_EN
- ALX_WOL_CTRL4_PT7_MATCH
- ALX_WOL_CTRL4_PT8_EN
- ALX_WOL_CTRL4_PT8_MATCH
- ALX_WOL_CTRL4_PT9_EN
- ALX_WOL_CTRL4_PT9_MATCH
- ALX_WOL_CTRL5
- ALX_WOL_CTRL5_PT0_LEN_MASK
- ALX_WOL_CTRL5_PT0_LEN_SHIFT
- ALX_WOL_CTRL5_PT10_LEN_MASK
- ALX_WOL_CTRL5_PT10_LEN_SHIFT
- ALX_WOL_CTRL5_PT11_LEN_MASK
- ALX_WOL_CTRL5_PT11_LEN_SHIFT
- ALX_WOL_CTRL5_PT12_LEN_MASK
- ALX_WOL_CTRL5_PT12_LEN_SHIFT
- ALX_WOL_CTRL5_PT13_LEN_MASK
- ALX_WOL_CTRL5_PT13_LEN_SHIFT
- ALX_WOL_CTRL5_PT14_LEN_MASK
- ALX_WOL_CTRL5_PT14_LEN_SHIFT
- ALX_WOL_CTRL5_PT15_LEN_MASK
- ALX_WOL_CTRL5_PT15_LEN_SHIFT
- ALX_WOL_CTRL5_PT1_LEN_MASK
- ALX_WOL_CTRL5_PT1_LEN_SHIFT
- ALX_WOL_CTRL5_PT2_LEN_MASK
- ALX_WOL_CTRL5_PT2_LEN_SHIFT
- ALX_WOL_CTRL5_PT3_LEN_MASK
- ALX_WOL_CTRL5_PT3_LEN_SHIFT
- ALX_WOL_CTRL5_PT4_LEN_MASK
- ALX_WOL_CTRL5_PT4_LEN_SHIFT
- ALX_WOL_CTRL5_PT5_LEN_MASK
- ALX_WOL_CTRL5_PT5_LEN_SHIFT
- ALX_WOL_CTRL5_PT6_LEN_MASK
- ALX_WOL_CTRL5_PT6_LEN_SHIFT
- ALX_WOL_CTRL5_PT7_LEN_MASK
- ALX_WOL_CTRL5_PT7_LEN_SHIFT
- ALX_WOL_CTRL5_PT8_LEN_MASK
- ALX_WOL_CTRL5_PT8_LEN_SHIFT
- ALX_WOL_CTRL5_PT9_LEN_MASK
- ALX_WOL_CTRL5_PT9_LEN_SHIFT
- ALX_WOL_CTRL6
- ALX_WOL_CTRL7
- ALX_WOL_CTRL8
- ALX_WRR
- ALX_WRR_PRI0_MASK
- ALX_WRR_PRI0_SHIFT
- ALX_WRR_PRI1_MASK
- ALX_WRR_PRI1_SHIFT
- ALX_WRR_PRI2_MASK
- ALX_WRR_PRI2_SHIFT
- ALX_WRR_PRI3_MASK
- ALX_WRR_PRI3_SHIFT
- ALX_WRR_PRI_MASK
- ALX_WRR_PRI_RESTRICT_NONE
- ALX_WRR_PRI_SHIFT
- AL_CONTEXT_PER_TRANSACTION
- AL_CPU_RESUME_MAGIC_NUM
- AL_CPU_RESUME_MAGIC_NUM_MASK
- AL_ECAM
- AL_ENC_SLICE_TYPE_B
- AL_ENC_SLICE_TYPE_I
- AL_ENC_SLICE_TYPE_P
- AL_EXTENT_SHIFT
- AL_EXTENT_SIZE
- AL_EXT_PER_BM_SECT
- AL_FIC_CAUSE
- AL_FIC_CONFIGURED_LEVEL
- AL_FIC_CONFIGURED_RISING_EDGE
- AL_FIC_CONTROL
- AL_FIC_MASK
- AL_FIC_SET_CAUSE
- AL_FIC_UNCONFIGURED
- AL_OPT_ADAPT_AUTO_QP
- AL_OPT_CONST_INTRA_PRED
- AL_OPT_CUSTOM_LDA
- AL_OPT_DEPENDENT_SLICES
- AL_OPT_DISABLE_INTRA
- AL_OPT_ENABLE_AUTO_QP
- AL_OPT_FIX_PREDICTOR
- AL_OPT_FORCE_LOAD
- AL_OPT_FORCE_MV_CLIP
- AL_OPT_FORCE_MV_OUT
- AL_OPT_FORCE_REC
- AL_OPT_LF
- AL_OPT_LF_X_SLICE
- AL_OPT_LF_X_TILE
- AL_OPT_LOWLAT_INT
- AL_OPT_LOWLAT_SYNC
- AL_OPT_QP_TAB_RELATIVE
- AL_OPT_RDO_COST_MODE
- AL_OPT_RESTART_GOP
- AL_OPT_SCENE_CHANGE
- AL_OPT_SCL_LST
- AL_OPT_TILE
- AL_OPT_TRANSFO_SKIP
- AL_OPT_UPDATE_PARAMS
- AL_OPT_USE_L2
- AL_OPT_USE_LONG_TERM
- AL_OPT_USE_QP_TABLE
- AL_OPT_WPP
- AL_PCIE_REV_ID_2
- AL_PCIE_REV_ID_3
- AL_PCIE_REV_ID_4
- AL_SUSPENDED
- AL_SYSFAB_POWER_CONTROL
- AL_TR_INITIALIZED
- AL_TR_UPDATE
- AL_UPDATES_PER_TRANSACTION
- AM
- AM2150_MACE_BANK
- AM2150_MACE_BASE
- AM2150_MAX_RX_FRAMES
- AM2150_MAX_TX_FRAMES
- AM2150_RCV
- AM2150_RCV_FRAME_COUNT
- AM2150_RCV_NEXT
- AM2150_XMT
- AM2150_XMT_SKIP
- AM2315_ALL_CHANNEL_MASK
- AM2315_DRIVER_NAME
- AM2315_FUNCTION_READ
- AM2315_HUM_OFFSET
- AM2315_REG_HUM_LSB
- AM2315_REG_HUM_MSB
- AM2315_REG_TEMP_LSB
- AM2315_REG_TEMP_MSB
- AM2315_TEMP_OFFSET
- AM29DL800BB
- AM29DL800BT
- AM29F002T
- AM29F016D
- AM29F017D
- AM29F032B
- AM29F040
- AM29F080
- AM29F800BB
- AM29F800BT
- AM29LV040B
- AM29LV160DB
- AM29LV160DT
- AM29LV400BB
- AM29LV400BT
- AM29LV800BB
- AM29LV800BT
- AM29SL800DB
- AM29SL800DT
- AM335X_CLASS
- AM335X_PHY0_WK_EN
- AM335X_PHY1_WK_EN
- AM335X_PIN_ECAP0_IN_PWM0_OUT
- AM335X_PIN_EMU0
- AM335X_PIN_EMU1
- AM335X_PIN_EXT_WAKEUP
- AM335X_PIN_GPMC_A0
- AM335X_PIN_GPMC_A1
- AM335X_PIN_GPMC_A10
- AM335X_PIN_GPMC_A11
- AM335X_PIN_GPMC_A2
- AM335X_PIN_GPMC_A3
- AM335X_PIN_GPMC_A4
- AM335X_PIN_GPMC_A5
- AM335X_PIN_GPMC_A6
- AM335X_PIN_GPMC_A7
- AM335X_PIN_GPMC_A8
- AM335X_PIN_GPMC_A9
- AM335X_PIN_GPMC_AD0
- AM335X_PIN_GPMC_AD1
- AM335X_PIN_GPMC_AD10
- AM335X_PIN_GPMC_AD11
- AM335X_PIN_GPMC_AD12
- AM335X_PIN_GPMC_AD13
- AM335X_PIN_GPMC_AD14
- AM335X_PIN_GPMC_AD15
- AM335X_PIN_GPMC_AD2
- AM335X_PIN_GPMC_AD3
- AM335X_PIN_GPMC_AD4
- AM335X_PIN_GPMC_AD5
- AM335X_PIN_GPMC_AD6
- AM335X_PIN_GPMC_AD7
- AM335X_PIN_GPMC_AD8
- AM335X_PIN_GPMC_AD9
- AM335X_PIN_GPMC_ADVN_ALE
- AM335X_PIN_GPMC_BEN0_CLE
- AM335X_PIN_GPMC_BEN1
- AM335X_PIN_GPMC_CLK
- AM335X_PIN_GPMC_CSN0
- AM335X_PIN_GPMC_CSN1
- AM335X_PIN_GPMC_CSN2
- AM335X_PIN_GPMC_CSN3
- AM335X_PIN_GPMC_OEN_REN
- AM335X_PIN_GPMC_WAIT0
- AM335X_PIN_GPMC_WEN
- AM335X_PIN_GPMC_WPN
- AM335X_PIN_I2C0_SCL
- AM335X_PIN_I2C0_SDA
- AM335X_PIN_LCD_AC_BIAS_EN
- AM335X_PIN_LCD_DATA0
- AM335X_PIN_LCD_DATA1
- AM335X_PIN_LCD_DATA10
- AM335X_PIN_LCD_DATA11
- AM335X_PIN_LCD_DATA12
- AM335X_PIN_LCD_DATA13
- AM335X_PIN_LCD_DATA14
- AM335X_PIN_LCD_DATA15
- AM335X_PIN_LCD_DATA2
- AM335X_PIN_LCD_DATA3
- AM335X_PIN_LCD_DATA4
- AM335X_PIN_LCD_DATA5
- AM335X_PIN_LCD_DATA6
- AM335X_PIN_LCD_DATA7
- AM335X_PIN_LCD_DATA8
- AM335X_PIN_LCD_DATA9
- AM335X_PIN_LCD_HSYNC
- AM335X_PIN_LCD_PCLK
- AM335X_PIN_LCD_VSYNC
- AM335X_PIN_MCASP0_ACLKR
- AM335X_PIN_MCASP0_ACLKX
- AM335X_PIN_MCASP0_AHCLKR
- AM335X_PIN_MCASP0_AHCLKX
- AM335X_PIN_MCASP0_AXR0
- AM335X_PIN_MCASP0_AXR1
- AM335X_PIN_MCASP0_FSR
- AM335X_PIN_MCASP0_FSX
- AM335X_PIN_MDC
- AM335X_PIN_MDIO
- AM335X_PIN_MII1_COL
- AM335X_PIN_MII1_CRS
- AM335X_PIN_MII1_RXD0
- AM335X_PIN_MII1_RXD1
- AM335X_PIN_MII1_RXD2
- AM335X_PIN_MII1_RXD3
- AM335X_PIN_MII1_RX_CLK
- AM335X_PIN_MII1_RX_DV
- AM335X_PIN_MII1_RX_ER
- AM335X_PIN_MII1_TXD0
- AM335X_PIN_MII1_TXD1
- AM335X_PIN_MII1_TXD2
- AM335X_PIN_MII1_TXD3
- AM335X_PIN_MII1_TX_CLK
- AM335X_PIN_MII1_TX_EN
- AM335X_PIN_MMC0_CLK
- AM335X_PIN_MMC0_CMD
- AM335X_PIN_MMC0_DAT0
- AM335X_PIN_MMC0_DAT1
- AM335X_PIN_MMC0_DAT2
- AM335X_PIN_MMC0_DAT3
- AM335X_PIN_NNMI
- AM335X_PIN_OFFSET_MAX
- AM335X_PIN_OFFSET_MIN
- AM335X_PIN_PMIC_POWER_EN
- AM335X_PIN_RMII1_REF_CLK
- AM335X_PIN_RTC_PWRONRSTN
- AM335X_PIN_SPI0_CS0
- AM335X_PIN_SPI0_CS1
- AM335X_PIN_SPI0_D0
- AM335X_PIN_SPI0_D1
- AM335X_PIN_SPI0_SCLK
- AM335X_PIN_TCK
- AM335X_PIN_TDI
- AM335X_PIN_TDO
- AM335X_PIN_TMS
- AM335X_PIN_TRSTN
- AM335X_PIN_UART0_CTSN
- AM335X_PIN_UART0_RTSN
- AM335X_PIN_UART0_RXD
- AM335X_PIN_UART0_TXD
- AM335X_PIN_UART1_CTSN
- AM335X_PIN_UART1_RTSN
- AM335X_PIN_UART1_RXD
- AM335X_PIN_UART1_TXD
- AM335X_PIN_USB0_DRVVBUS
- AM335X_PIN_USB1_DRVVBUS
- AM335X_PIN_WARMRSTN
- AM335X_PIN_XDMA_EVENT_INTR0
- AM335X_PIN_XDMA_EVENT_INTR1
- AM335X_REV_ES1_0
- AM335X_REV_ES2_0
- AM335X_REV_ES2_1
- AM335X_USB0_CTRL
- AM335X_USB1_CTRL
- AM335x_USB_WKUP
- AM33XX_800M_ARM_MPU_MAX_FREQ
- AM33XX_CLKOUT2DIV_SHIFT
- AM33XX_CLKOUT2DIV_WIDTH
- AM33XX_CLKOUT2EN_SHIFT
- AM33XX_CLKOUT2SOURCE_MASK
- AM33XX_CLKSEL_0_0_MASK
- AM33XX_CLKSEL_0_0_SHIFT
- AM33XX_CLKSEL_0_0_WIDTH
- AM33XX_CLKSEL_0_1_MASK
- AM33XX_CLKSEL_0_2_MASK
- AM33XX_CLKSEL_GFX_FCLK
- AM33XX_CLKSEL_GFX_FCLK_MASK
- AM33XX_CLKSEL_GFX_FCLK_OFFSET
- AM33XX_CLKSEL_GPIO0_DBCLK
- AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET
- AM33XX_CLKSEL_LCDC_PIXEL_CLK
- AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET
- AM33XX_CLKSEL_PRUSS_OCP_CLK
- AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET
- AM33XX_CLKSEL_TIMER1MS_CLK
- AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET
- AM33XX_CLKSEL_TIMER2_CLK
- AM33XX_CLKSEL_TIMER2_CLK_OFFSET
- AM33XX_CLKSEL_TIMER3_CLK
- AM33XX_CLKSEL_TIMER3_CLK_OFFSET
- AM33XX_CLKSEL_TIMER4_CLK
- AM33XX_CLKSEL_TIMER4_CLK_OFFSET
- AM33XX_CLKSEL_TIMER5_CLK
- AM33XX_CLKSEL_TIMER5_CLK_OFFSET
- AM33XX_CLKSEL_TIMER6_CLK
- AM33XX_CLKSEL_TIMER6_CLK_OFFSET
- AM33XX_CLKSEL_TIMER7_CLK
- AM33XX_CLKSEL_TIMER7_CLK_OFFSET
- AM33XX_CLKSEL_WDT1_CLK
- AM33XX_CLKSEL_WDT1_CLK_OFFSET
- AM33XX_CLKTRCTRL_MASK
- AM33XX_CLKTRCTRL_SHIFT
- AM33XX_CM_AUTOIDLE_DPLL_CORE
- AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET
- AM33XX_CM_AUTOIDLE_DPLL_DDR
- AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET
- AM33XX_CM_AUTOIDLE_DPLL_DISP
- AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET
- AM33XX_CM_AUTOIDLE_DPLL_MPU
- AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET
- AM33XX_CM_AUTOIDLE_DPLL_PER
- AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET
- AM33XX_CM_BASE
- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL
- AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET
- AM33XX_CM_CEFUSE_CLKSTCTRL
- AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET
- AM33XX_CM_CEFUSE_MOD
- AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
- AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
- AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
- AM33XX_CM_CLKDCOLDO_DPLL_PER
- AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET
- AM33XX_CM_CLKMODE_DPLL_CORE
- AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET
- AM33XX_CM_CLKMODE_DPLL_DDR
- AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET
- AM33XX_CM_CLKMODE_DPLL_DISP
- AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET
- AM33XX_CM_CLKMODE_DPLL_MPU
- AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET
- AM33XX_CM_CLKMODE_DPLL_PER
- AM33XX_CM_CLKMODE_DPLL_PER_OFFSET
- AM33XX_CM_CLKOUT_CTRL
- AM33XX_CM_CLKOUT_CTRL_OFFSET
- AM33XX_CM_CLKSEL_DPLL_CORE
- AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET
- AM33XX_CM_CLKSEL_DPLL_DDR
- AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET
- AM33XX_CM_CLKSEL_DPLL_DISP
- AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET
- AM33XX_CM_CLKSEL_DPLL_MPU
- AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET
- AM33XX_CM_CLKSEL_DPLL_PERIPH
- AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET
- AM33XX_CM_CPTS_RFT_CLKSEL
- AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET
- AM33XX_CM_DEVICE_MOD
- AM33XX_CM_DIV_M2_DPLL_DDR
- AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET
- AM33XX_CM_DIV_M2_DPLL_DISP
- AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET
- AM33XX_CM_DIV_M2_DPLL_MPU
- AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET
- AM33XX_CM_DIV_M2_DPLL_PER
- AM33XX_CM_DIV_M2_DPLL_PER_OFFSET
- AM33XX_CM_DIV_M4_DPLL_CORE
- AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET
- AM33XX_CM_DIV_M5_DPLL_CORE
- AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET
- AM33XX_CM_DIV_M6_DPLL_CORE
- AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET
- AM33XX_CM_DPLL_MOD
- AM33XX_CM_GFX_BITBLT_CLKCTRL
- AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET
- AM33XX_CM_GFX_GFX_CLKCTRL
- AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET
- AM33XX_CM_GFX_L3_CLKSTCTRL
- AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET
- AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1
- AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET
- AM33XX_CM_GFX_MMUCFG_CLKCTRL
- AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET
- AM33XX_CM_GFX_MMUDATA_CLKCTRL
- AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET
- AM33XX_CM_GFX_MOD
- AM33XX_CM_IDLEST_DPLL_CORE
- AM33XX_CM_IDLEST_DPLL_CORE_OFFSET
- AM33XX_CM_IDLEST_DPLL_DDR
- AM33XX_CM_IDLEST_DPLL_DDR_OFFSET
- AM33XX_CM_IDLEST_DPLL_DISP
- AM33XX_CM_IDLEST_DPLL_DISP_OFFSET
- AM33XX_CM_IDLEST_DPLL_MPU
- AM33XX_CM_IDLEST_DPLL_MPU_OFFSET
- AM33XX_CM_IDLEST_DPLL_PER
- AM33XX_CM_IDLEST_DPLL_PER_OFFSET
- AM33XX_CM_L3_AON_CLKSTCTRL
- AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET
- AM33XX_CM_L4_WKUP_AON_CLKSTCTRL
- AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET
- AM33XX_CM_MAC_CLKSEL
- AM33XX_CM_MAC_CLKSEL_OFFSET
- AM33XX_CM_MPU_CLKSTCTRL
- AM33XX_CM_MPU_CLKSTCTRL_OFFSET
- AM33XX_CM_MPU_MOD
- AM33XX_CM_MPU_MPU_CLKCTRL
- AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET
- AM33XX_CM_PER_AES0_CLKCTRL
- AM33XX_CM_PER_AES0_CLKCTRL_OFFSET
- AM33XX_CM_PER_AES1_CLKCTRL
- AM33XX_CM_PER_AES1_CLKCTRL_OFFSET
- AM33XX_CM_PER_CLKDIV32K_CLKCTRL
- AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET
- AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL
- AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_CPGMAC0_CLKCTRL
- AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
- AM33XX_CM_PER_CPSW_CLKSTCTRL
- AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_DCAN0_CLKCTRL
- AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET
- AM33XX_CM_PER_DCAN1_CLKCTRL
- AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET
- AM33XX_CM_PER_DES_CLKCTRL
- AM33XX_CM_PER_DES_CLKCTRL_OFFSET
- AM33XX_CM_PER_ELM_CLKCTRL
- AM33XX_CM_PER_ELM_CLKCTRL_OFFSET
- AM33XX_CM_PER_EMIF_CLKCTRL
- AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET
- AM33XX_CM_PER_EMIF_FW_CLKCTRL
- AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET
- AM33XX_CM_PER_EPWMSS0_CLKCTRL
- AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
- AM33XX_CM_PER_EPWMSS1_CLKCTRL
- AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
- AM33XX_CM_PER_EPWMSS2_CLKCTRL
- AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO1_CLKCTRL
- AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO2_CLKCTRL
- AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO3_CLKCTRL
- AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO4_CLKCTRL
- AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO5_CLKCTRL
- AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPIO6_CLKCTRL
- AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET
- AM33XX_CM_PER_GPMC_CLKCTRL
- AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET
- AM33XX_CM_PER_I2C1_CLKCTRL
- AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET
- AM33XX_CM_PER_I2C2_CLKCTRL
- AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET
- AM33XX_CM_PER_IEEE5000_CLKCTRL
- AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET
- AM33XX_CM_PER_L3S_CLKSTCTRL
- AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_L3_CLKCTRL
- AM33XX_CM_PER_L3_CLKCTRL_OFFSET
- AM33XX_CM_PER_L3_CLKSTCTRL
- AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_L3_INSTR_CLKCTRL
- AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
- AM33XX_CM_PER_L4FW_CLKCTRL
- AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET
- AM33XX_CM_PER_L4FW_CLKSTCTRL
- AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_L4HS_CLKCTRL
- AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET
- AM33XX_CM_PER_L4HS_CLKSTCTRL
- AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_L4LS_CLKCTRL
- AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET
- AM33XX_CM_PER_L4LS_CLKSTCTRL
- AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_LCDC_CLKCTRL
- AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET
- AM33XX_CM_PER_LCDC_CLKSTCTRL
- AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_MAILBOX0_CLKCTRL
- AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
- AM33XX_CM_PER_MAILBOX1_CLKCTRL
- AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET
- AM33XX_CM_PER_MCASP0_CLKCTRL
- AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET
- AM33XX_CM_PER_MCASP1_CLKCTRL
- AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET
- AM33XX_CM_PER_MCASP2_CLKCTRL
- AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET
- AM33XX_CM_PER_MLB_CLKCTRL
- AM33XX_CM_PER_MLB_CLKCTRL_OFFSET
- AM33XX_CM_PER_MMC0_CLKCTRL
- AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET
- AM33XX_CM_PER_MMC1_CLKCTRL
- AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET
- AM33XX_CM_PER_MMC2_CLKCTRL
- AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET
- AM33XX_CM_PER_MOD
- AM33XX_CM_PER_MSTR_EXPS_CLKCTRL
- AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET
- AM33XX_CM_PER_OCMCRAM_CLKCTRL
- AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
- AM33XX_CM_PER_OCPWP_CLKCTRL
- AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET
- AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL
- AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_PKA_CLKCTRL
- AM33XX_CM_PER_PKA_CLKCTRL_OFFSET
- AM33XX_CM_PER_PRUSS_CLKCTRL
- AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET
- AM33XX_CM_PER_PRUSS_CLKSTCTRL
- AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET
- AM33XX_CM_PER_RNG_CLKCTRL
- AM33XX_CM_PER_RNG_CLKCTRL_OFFSET
- AM33XX_CM_PER_SHA0_CLKCTRL
- AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET
- AM33XX_CM_PER_SLV_EXPS_CLKCTRL
- AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET
- AM33XX_CM_PER_SPI0_CLKCTRL
- AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET
- AM33XX_CM_PER_SPI1_CLKCTRL
- AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET
- AM33XX_CM_PER_SPI2_CLKCTRL
- AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET
- AM33XX_CM_PER_SPI3_CLKCTRL
- AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET
- AM33XX_CM_PER_SPINLOCK_CLKCTRL
- AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER2_CLKCTRL
- AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER3_CLKCTRL
- AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER4_CLKCTRL
- AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER5_CLKCTRL
- AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER6_CLKCTRL
- AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET
- AM33XX_CM_PER_TIMER7_CLKCTRL
- AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET
- AM33XX_CM_PER_TPCC_CLKCTRL
- AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET
- AM33XX_CM_PER_TPTC0_CLKCTRL
- AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET
- AM33XX_CM_PER_TPTC1_CLKCTRL
- AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET
- AM33XX_CM_PER_TPTC2_CLKCTRL
- AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET
- AM33XX_CM_PER_UART1_CLKCTRL
- AM33XX_CM_PER_UART1_CLKCTRL_OFFSET
- AM33XX_CM_PER_UART2_CLKCTRL
- AM33XX_CM_PER_UART2_CLKCTRL_OFFSET
- AM33XX_CM_PER_UART3_CLKCTRL
- AM33XX_CM_PER_UART3_CLKCTRL_OFFSET
- AM33XX_CM_PER_UART4_CLKCTRL
- AM33XX_CM_PER_UART4_CLKCTRL_OFFSET
- AM33XX_CM_PER_UART5_CLKCTRL
- AM33XX_CM_PER_UART5_CLKCTRL_OFFSET
- AM33XX_CM_PER_USB0_CLKCTRL
- AM33XX_CM_PER_USB0_CLKCTRL_OFFSET
- AM33XX_CM_REGADDR
- AM33XX_CM_RTC_CLKSTCTRL
- AM33XX_CM_RTC_CLKSTCTRL_OFFSET
- AM33XX_CM_RTC_MOD
- AM33XX_CM_RTC_RTC_CLKCTRL
- AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER
- AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET
- AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE
- AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET
- AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR
- AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET
- AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP
- AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET
- AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU
- AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET
- AM33XX_CM_SSC_MODFREQDIV_DPLL_PER
- AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET
- AM33XX_CM_WKUP_ADC_TSC_CLKCTRL
- AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_CLKSTCTRL
- AM33XX_CM_WKUP_CLKSTCTRL_OFFSET
- AM33XX_CM_WKUP_CONTROL_CLKCTRL
- AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL
- AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_GPIO0_CLKCTRL
- AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_I2C0_CLKCTRL
- AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_L4WKUP_CLKCTRL
- AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_MOD
- AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL
- AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL
- AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_TIMER0_CLKCTRL
- AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_TIMER1_CLKCTRL
- AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_UART0_CLKCTRL
- AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_WDT0_CLKCTRL
- AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_WDT1_CLKCTRL
- AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
- AM33XX_CM_WKUP_WKUP_M3_CLKCTRL
- AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET
- AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET
- AM33XX_CONTROL_BANDGAP_CTRL_OFFSET
- AM33XX_CONTROL_BANDGAP_TRIM_OFFSET
- AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET
- AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET
- AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET
- AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET
- AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET
- AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET
- AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET
- AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET
- AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET
- AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET
- AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET
- AM33XX_CONTROL_M3_TXEV_EOI
- AM33XX_CONTROL_MMU_CFG_OFFSET
- AM33XX_CONTROL_MOSC_CTRL_OFFSET
- AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET
- AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET
- AM33XX_CONTROL_MREQPRIO_0_OFFSET
- AM33XX_CONTROL_MREQPRIO_1_OFFSET
- AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET
- AM33XX_CONTROL_RCOSC_CTRL_OFFSET
- AM33XX_CONTROL_RESET_ISO_OFFSET
- AM33XX_CONTROL_SEC_CLK_CTRL
- AM33XX_CONTROL_SMRT_CTRL_OFFSET
- AM33XX_CONTROL_STATUS
- AM33XX_CONTROL_STATUS_OFFSET
- AM33XX_CONTROL_STATUS_SYSBOOT1_MASK
- AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT
- AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH
- AM33XX_CONTROL_SYSCONFIG_OFFSET
- AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET
- AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET
- AM33XX_CONTROL_TPTC_CFG_OFFSET
- AM33XX_CONTROL_USB_CTRL0_OFFSET
- AM33XX_CONTROL_USB_CTRL1_OFFSET
- AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET
- AM33XX_CONTROL_VREF_CTRL_OFFSET
- AM33XX_CTRL_BASE
- AM33XX_CTRL_IPC_REG_COUNT
- AM33XX_CTRL_IPC_REG_OFFSET
- AM33XX_CTRL_REGADDR
- AM33XX_DEV_FEATURE
- AM33XX_DPLL_CLKOUT_DIV_SHIFT
- AM33XX_DPLL_CLKOUT_DIV_WIDTH
- AM33XX_DPLL_DIV_MASK
- AM33XX_DPLL_EN_MASK
- AM33XX_DPLL_MULT_MASK
- AM33XX_DPLL_MULT_PERIPH_MASK
- AM33XX_DPLL_PER_DIV_MASK
- AM33XX_GFX_MEM_ONSTATE_MASK
- AM33XX_GFX_MEM_RETSTATE_MASK
- AM33XX_GFX_MEM_STATEST_MASK
- AM33XX_GLOBAL_WARM_SW_RST_MASK
- AM33XX_GMII_SEL_MODE_MII
- AM33XX_GMII_SEL_MODE_RGMII
- AM33XX_GMII_SEL_MODE_RMII
- AM33XX_GMII_SEL_RGMII1_IDMODE
- AM33XX_GMII_SEL_RGMII2_IDMODE
- AM33XX_GMII_SEL_RMII1_IO_CLK_EN
- AM33XX_GMII_SEL_RMII2_IO_CLK_EN
- AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT
- AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH
- AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT
- AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH
- AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT
- AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH
- AM33XX_IDLEST_MASK
- AM33XX_IDLEST_SHIFT
- AM33XX_IOPAD
- AM33XX_L4_WK_IO_ADDRESS
- AM33XX_L4_WK_IO_OFFSET
- AM33XX_LASTPOWERSTATEENTERED_MASK
- AM33XX_LASTPOWERSTATEENTERED_SHIFT
- AM33XX_LOGICRETSTATE_3_3_MASK
- AM33XX_LOGICRETSTATE_MASK
- AM33XX_LOGICSTATEST_MASK
- AM33XX_LOGICSTATEST_SHIFT
- AM33XX_LOWPOWERSTATECHANGE_MASK
- AM33XX_LOWPOWERSTATECHANGE_SHIFT
- AM33XX_M3_TXEV_ACK
- AM33XX_M3_TXEV_ENABLE
- AM33XX_MODULEMODE_MASK
- AM33XX_MODULEMODE_SHIFT
- AM33XX_MPU_L1_ONSTATE_MASK
- AM33XX_MPU_L1_RETSTATE_MASK
- AM33XX_MPU_L1_STATEST_MASK
- AM33XX_MPU_L2_ONSTATE_MASK
- AM33XX_MPU_L2_RETSTATE_MASK
- AM33XX_MPU_L2_STATEST_MASK
- AM33XX_MPU_RAM_ONSTATE_MASK
- AM33XX_MPU_RAM_RETSTATE_MASK
- AM33XX_MPU_RAM_STATEST_MASK
- AM33XX_OPTCLK_DEBUG_CLKA_SHIFT
- AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT
- AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT
- AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT
- AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT
- AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT
- AM33XX_PADCONF
- AM33XX_PER_MEM_ONSTATE_MASK
- AM33XX_PER_MEM_RETSTATE_MASK
- AM33XX_PER_MEM_STATEST_MASK
- AM33XX_PM_CEFUSE_PWRSTCTRL
- AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET
- AM33XX_PM_CEFUSE_PWRSTST
- AM33XX_PM_CEFUSE_PWRSTST_OFFSET
- AM33XX_PM_GFX_PWRSTCTRL
- AM33XX_PM_GFX_PWRSTCTRL_OFFSET
- AM33XX_PM_GFX_PWRSTST
- AM33XX_PM_GFX_PWRSTST_OFFSET
- AM33XX_PM_MPU_PWRSTCTRL
- AM33XX_PM_MPU_PWRSTCTRL_OFFSET
- AM33XX_PM_MPU_PWRSTST
- AM33XX_PM_MPU_PWRSTST_OFFSET
- AM33XX_PM_PER_PWRSTCTRL
- AM33XX_PM_PER_PWRSTCTRL_OFFSET
- AM33XX_PM_PER_PWRSTST
- AM33XX_PM_PER_PWRSTST_OFFSET
- AM33XX_PM_RTC_PWRSTCTRL
- AM33XX_PM_RTC_PWRSTCTRL_OFFSET
- AM33XX_PM_RTC_PWRSTST
- AM33XX_PM_RTC_PWRSTST_OFFSET
- AM33XX_PM_WKUP_PWRSTCTRL
- AM33XX_PM_WKUP_PWRSTCTRL_OFFSET
- AM33XX_PM_WKUP_PWRSTST
- AM33XX_PM_WKUP_PWRSTST_OFFSET
- AM33XX_PRCM_BASE
- AM33XX_PRM_BASE
- AM33XX_PRM_CEFUSE_MOD
- AM33XX_PRM_DEVICE_MOD
- AM33XX_PRM_GFX_MOD
- AM33XX_PRM_IRQENABLE_M3
- AM33XX_PRM_IRQENABLE_M3_OFFSET
- AM33XX_PRM_IRQENABLE_MPU
- AM33XX_PRM_IRQENABLE_MPU_OFFSET
- AM33XX_PRM_IRQSTATUS_M3
- AM33XX_PRM_IRQSTATUS_M3_OFFSET
- AM33XX_PRM_IRQSTATUS_MPU
- AM33XX_PRM_IRQSTATUS_MPU_OFFSET
- AM33XX_PRM_LDO_SRAM_CORE_CTRL
- AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET
- AM33XX_PRM_LDO_SRAM_CORE_SETUP
- AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET
- AM33XX_PRM_LDO_SRAM_MPU_CTRL
- AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET
- AM33XX_PRM_LDO_SRAM_MPU_SETUP
- AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET
- AM33XX_PRM_MPU_MOD
- AM33XX_PRM_OCP_SOCKET_MOD
- AM33XX_PRM_PER_MOD
- AM33XX_PRM_REGADDR
- AM33XX_PRM_RSTCTRL
- AM33XX_PRM_RSTCTRL_OFFSET
- AM33XX_PRM_RSTST
- AM33XX_PRM_RSTST_OFFSET
- AM33XX_PRM_RSTTIME
- AM33XX_PRM_RSTTIME_OFFSET
- AM33XX_PRM_RTC_MOD
- AM33XX_PRM_SRAM_COUNT
- AM33XX_PRM_SRAM_COUNT_OFFSET
- AM33XX_PRM_WKUP_MOD
- AM33XX_PRUSS_MEM_ONSTATE_MASK
- AM33XX_PRUSS_MEM_RETSTATE_MASK
- AM33XX_PRUSS_MEM_STATEST_MASK
- AM33XX_PWMSS0_TBCLKEN_SHIFT
- AM33XX_PWMSS1_TBCLKEN_SHIFT
- AM33XX_PWMSS2_TBCLKEN_SHIFT
- AM33XX_PWMSS_TBCLK_CLKCTRL
- AM33XX_RAM_MEM_ONSTATE_MASK
- AM33XX_RAM_MEM_RETSTATE_MASK
- AM33XX_RAM_MEM_STATEST_MASK
- AM33XX_REVISION_PRM
- AM33XX_REVISION_PRM_OFFSET
- AM33XX_RM_GFX_RSTCTRL
- AM33XX_RM_GFX_RSTCTRL_OFFSET
- AM33XX_RM_GFX_RSTST
- AM33XX_RM_GFX_RSTST_OFFSET
- AM33XX_RM_MPU_RSTST
- AM33XX_RM_MPU_RSTST_OFFSET
- AM33XX_RM_PER_RSTCTRL
- AM33XX_RM_PER_RSTCTRL_OFFSET
- AM33XX_RM_WKUP_RSTCTRL
- AM33XX_RM_WKUP_RSTCTRL_OFFSET
- AM33XX_RM_WKUP_RSTST
- AM33XX_RM_WKUP_RSTST_OFFSET
- AM33XX_RST_GLOBAL_WARM_SW_MASK
- AM33XX_SCM_BASE
- AM33XX_SGX_MASK
- AM33XX_STM_PMD_CLKDIVSEL_SHIFT
- AM33XX_STM_PMD_CLKDIVSEL_WIDTH
- AM33XX_STM_PMD_CLKSEL_SHIFT
- AM33XX_STM_PMD_CLKSEL_WIDTH
- AM33XX_ST_DPLL_CLKDCOLDO_SHIFT
- AM33XX_ST_DPLL_CLK_MASK
- AM33XX_TAP_BASE
- AM33XX_TRC_PMD_CLKDIVSEL_SHIFT
- AM33XX_TRC_PMD_CLKDIVSEL_WIDTH
- AM33XX_TRC_PMD_CLKSEL_SHIFT
- AM33XX_TRC_PMD_CLKSEL_WIDTH
- AM33XX_UART1_BASE
- AM35XX_CLASS
- AM35XX_CONTROL_CBA_PRIORITY
- AM35XX_CONTROL_DEVCONF2
- AM35XX_CONTROL_DEVCONF3
- AM35XX_CONTROL_IPSS_CLK_CTRL
- AM35XX_CONTROL_IP_SW_RESET
- AM35XX_CONTROL_LVL_INTR_CLEAR
- AM35XX_CONTROL_MSUSPENDMUX_6
- AM35XX_CPGMACSS_SW_RST
- AM35XX_CPGMAC_C0_MISC_PULSE_CLR
- AM35XX_CPGMAC_C0_RX_PULSE_CLR
- AM35XX_CPGMAC_C0_RX_THRESH_CLR
- AM35XX_CPGMAC_C0_TX_PULSE_CLR
- AM35XX_CPGMAC_FCLK_SHIFT
- AM35XX_CPGMAC_VBUSP_CLK_SHIFT
- AM35XX_EN_UART4_MASK
- AM35XX_EN_UART4_SHIFT
- AM35XX_HECC_SW_RST
- AM35XX_HECC_VBUSP_CLK_SHIFT
- AM35XX_IPSS_CLK_IDLEST_VAL
- AM35XX_IPSS_ICK_EN_ACK_OFFSET
- AM35XX_IPSS_ICK_FCK_OFFSET
- AM35XX_IPSS_ICK_MASK
- AM35XX_IPSS_USBOTGSS_BASE
- AM35XX_REV_ES1_0
- AM35XX_REV_ES1_1
- AM35XX_ST_IPSS_SHIFT
- AM35XX_ST_UART4_SHIFT
- AM35XX_UART4_BASE
- AM35XX_USBOTGSS_INT_CLR
- AM35XX_USBOTGSS_SW_RST
- AM35XX_USBOTG_FCLK_SHIFT
- AM35XX_USBOTG_VBUSP_CLK_SHIFT
- AM35XX_VPFE_CCDC_VD0_INT_CLR
- AM35XX_VPFE_CCDC_VD1_INT_CLR
- AM35XX_VPFE_CCDC_VD2_INT_CLR
- AM35XX_VPFE_FCLK_SHIFT
- AM35XX_VPFE_PCLK_SW_RST
- AM35XX_VPFE_VBUSP_CLK_SHIFT
- AM35XX_VPFE_VBUSP_SW_RST
- AM35X_INTR_DRVVBUS
- AM35X_INTR_RX_SHIFT
- AM35X_INTR_TX_SHIFT
- AM35X_INTR_USB_MASK
- AM35X_INTR_USB_SHIFT
- AM35X_RX_EP_MASK
- AM35X_RX_INTR_MASK
- AM35X_SOFT_RESET_MASK
- AM35X_TX_EP_MASK
- AM35X_TX_INTR_MASK
- AM3_ADC_TSC_CLKCTRL
- AM3_AES_CLKCTRL
- AM3_CEFUSE_CLKCTRL
- AM3_CLKCTRL_INDEX
- AM3_CLKCTRL_OFFSET
- AM3_CLKDIV32K_CLKCTRL
- AM3_CLK_24MHZ_CLKCTRL_INDEX
- AM3_CLK_24MHZ_CLKCTRL_OFFSET
- AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL
- AM3_CONTROL_CLKCTRL
- AM3_CPGMAC0_CLKCTRL
- AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL
- AM3_DEBUGSS_CLKCTRL
- AM3_D_CAN0_CLKCTRL
- AM3_D_CAN1_CLKCTRL
- AM3_ELM_CLKCTRL
- AM3_EMIF_CLKCTRL
- AM3_EPWMSS0_CLKCTRL
- AM3_EPWMSS1_CLKCTRL
- AM3_EPWMSS2_CLKCTRL
- AM3_GFX_CLKCTRL
- AM3_GFX_L3_CLKCTRL_INDEX
- AM3_GFX_L3_CLKCTRL_OFFSET
- AM3_GFX_L3_GFX_CLKCTRL
- AM3_GPIO1_CLKCTRL
- AM3_GPIO2_CLKCTRL
- AM3_GPIO3_CLKCTRL
- AM3_GPIO4_CLKCTRL
- AM3_GPMC_CLKCTRL
- AM3_I2C1_CLKCTRL
- AM3_I2C2_CLKCTRL
- AM3_I2C3_CLKCTRL
- AM3_L3S_CLKCTRL_INDEX
- AM3_L3S_CLKCTRL_OFFSET
- AM3_L3S_GPMC_CLKCTRL
- AM3_L3S_MCASP0_CLKCTRL
- AM3_L3S_MCASP1_CLKCTRL
- AM3_L3S_MMC3_CLKCTRL
- AM3_L3S_USB_OTG_HS_CLKCTRL
- AM3_L3_AES_CLKCTRL
- AM3_L3_AON_CLKCTRL_INDEX
- AM3_L3_AON_CLKCTRL_OFFSET
- AM3_L3_AON_DEBUGSS_CLKCTRL
- AM3_L3_CLKCTRL_INDEX
- AM3_L3_CLKCTRL_OFFSET
- AM3_L3_EMIF_CLKCTRL
- AM3_L3_INSTR_CLKCTRL
- AM3_L3_L3_INSTR_CLKCTRL
- AM3_L3_L3_MAIN_CLKCTRL
- AM3_L3_MAIN_CLKCTRL
- AM3_L3_OCMCRAM_CLKCTRL
- AM3_L3_SHAM_CLKCTRL
- AM3_L3_TPCC_CLKCTRL
- AM3_L3_TPTC0_CLKCTRL
- AM3_L3_TPTC1_CLKCTRL
- AM3_L3_TPTC2_CLKCTRL
- AM3_L4HS_CLKCTRL_INDEX
- AM3_L4HS_CLKCTRL_OFFSET
- AM3_L4HS_L4_HS_CLKCTRL
- AM3_L4LS_CLKCTRL_INDEX
- AM3_L4LS_CLKCTRL_OFFSET
- AM3_L4LS_D_CAN0_CLKCTRL
- AM3_L4LS_D_CAN1_CLKCTRL
- AM3_L4LS_ELM_CLKCTRL
- AM3_L4LS_EPWMSS0_CLKCTRL
- AM3_L4LS_EPWMSS1_CLKCTRL
- AM3_L4LS_EPWMSS2_CLKCTRL
- AM3_L4LS_GPIO2_CLKCTRL
- AM3_L4LS_GPIO3_CLKCTRL
- AM3_L4LS_GPIO4_CLKCTRL
- AM3_L4LS_I2C2_CLKCTRL
- AM3_L4LS_I2C3_CLKCTRL
- AM3_L4LS_L4_LS_CLKCTRL
- AM3_L4LS_MAILBOX_CLKCTRL
- AM3_L4LS_MMC1_CLKCTRL
- AM3_L4LS_MMC2_CLKCTRL
- AM3_L4LS_OCPWP_CLKCTRL
- AM3_L4LS_RNG_CLKCTRL
- AM3_L4LS_SPI0_CLKCTRL
- AM3_L4LS_SPI1_CLKCTRL
- AM3_L4LS_SPINLOCK_CLKCTRL
- AM3_L4LS_TIMER2_CLKCTRL
- AM3_L4LS_TIMER3_CLKCTRL
- AM3_L4LS_TIMER4_CLKCTRL
- AM3_L4LS_TIMER5_CLKCTRL
- AM3_L4LS_TIMER6_CLKCTRL
- AM3_L4LS_TIMER7_CLKCTRL
- AM3_L4LS_UART2_CLKCTRL
- AM3_L4LS_UART3_CLKCTRL
- AM3_L4LS_UART4_CLKCTRL
- AM3_L4LS_UART5_CLKCTRL
- AM3_L4LS_UART6_CLKCTRL
- AM3_L4_CEFUSE_CEFUSE_CLKCTRL
- AM3_L4_CEFUSE_CLKCTRL_INDEX
- AM3_L4_CEFUSE_CLKCTRL_OFFSET
- AM3_L4_HS_CLKCTRL
- AM3_L4_LS_CLKCTRL
- AM3_L4_PER_CLKCTRL_INDEX
- AM3_L4_PER_CLKCTRL_OFFSET
- AM3_L4_RTC_RTC_CLKCTRL
- AM3_L4_WKUP_ADC_TSC_CLKCTRL
- AM3_L4_WKUP_AON_CLKCTRL_INDEX
- AM3_L4_WKUP_AON_CLKCTRL_OFFSET
- AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL
- AM3_L4_WKUP_CLKCTRL
- AM3_L4_WKUP_CLKCTRL_INDEX
- AM3_L4_WKUP_CLKCTRL_OFFSET
- AM3_L4_WKUP_CONTROL_CLKCTRL
- AM3_L4_WKUP_GPIO1_CLKCTRL
- AM3_L4_WKUP_I2C1_CLKCTRL
- AM3_L4_WKUP_L4_WKUP_CLKCTRL
- AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL
- AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL
- AM3_L4_WKUP_TIMER1_CLKCTRL
- AM3_L4_WKUP_UART1_CLKCTRL
- AM3_L4_WKUP_WD_TIMER2_CLKCTRL
- AM3_LCDC_CLKCTRL
- AM3_LCDC_CLKCTRL_INDEX
- AM3_LCDC_CLKCTRL_OFFSET
- AM3_LCDC_LCDC_CLKCTRL
- AM3_MAILBOX_CLKCTRL
- AM3_MCASP0_CLKCTRL
- AM3_MCASP1_CLKCTRL
- AM3_MMC1_CLKCTRL
- AM3_MMC2_CLKCTRL
- AM3_MMC3_CLKCTRL
- AM3_MPU_CLKCTRL
- AM3_MPU_CLKCTRL_INDEX
- AM3_MPU_CLKCTRL_OFFSET
- AM3_MPU_MPU_CLKCTRL
- AM3_OCMCRAM_CLKCTRL
- AM3_OCPWP_CLKCTRL
- AM3_PRUSS_CLKCTRL
- AM3_PRUSS_OCP_CLKCTRL_INDEX
- AM3_PRUSS_OCP_CLKCTRL_OFFSET
- AM3_PRUSS_OCP_PRUSS_CLKCTRL
- AM3_RNG_CLKCTRL
- AM3_RTC_CLKCTRL
- AM3_SHAM_CLKCTRL
- AM3_SMARTREFLEX0_CLKCTRL
- AM3_SMARTREFLEX1_CLKCTRL
- AM3_SPI0_CLKCTRL
- AM3_SPI1_CLKCTRL
- AM3_SPINLOCK_CLKCTRL
- AM3_TIMER1_CLKCTRL
- AM3_TIMER2_CLKCTRL
- AM3_TIMER3_CLKCTRL
- AM3_TIMER4_CLKCTRL
- AM3_TIMER5_CLKCTRL
- AM3_TIMER6_CLKCTRL
- AM3_TIMER7_CLKCTRL
- AM3_TPCC_CLKCTRL
- AM3_TPTC0_CLKCTRL
- AM3_TPTC1_CLKCTRL
- AM3_TPTC2_CLKCTRL
- AM3_UART1_CLKCTRL
- AM3_UART2_CLKCTRL
- AM3_UART3_CLKCTRL
- AM3_UART4_CLKCTRL
- AM3_UART5_CLKCTRL
- AM3_UART6_CLKCTRL
- AM3_USB_OTG_HS_CLKCTRL
- AM3_WD_TIMER2_CLKCTRL
- AM3_WKUP_M3_CLKCTRL
- AM4372_IOPAD
- AM437X_CLASS
- AM437X_CTRL_USB2_OTGSESSEND_EN
- AM437X_CTRL_USB2_OTGVDET_EN
- AM437X_CTRL_USB2_OTG_PD
- AM437X_CTRL_USB2_PHY_PD
- AM437X_REV_ES1_0
- AM437X_REV_ES1_1
- AM437X_REV_ES1_2
- AM437X_USB2_OTGSESSEND_EN
- AM437X_USB2_OTGVDET_EN
- AM437X_USB2_OTG_PD
- AM437X_USB2_PHY_PD
- AM437X_VPFE_H
- AM437X_VPFE_REGS_H
- AM437X_VPFE_USER_H
- AM43XX_600M_ARM_MPU_MAX_FREQ
- AM43XX_CM_BASE
- AM43XX_CM_CEFUSE_CEFUSE_CDOFFS
- AM43XX_CM_CEFUSE_INST
- AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
- AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
- AM43XX_CM_DEVICE_INST
- AM43XX_CM_DPLL_INST
- AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET
- AM43XX_CM_GFX_GFX_L3_CDOFFS
- AM43XX_CM_GFX_INST
- AM43XX_CM_MPU_CLKSTCTRL
- AM43XX_CM_MPU_INST
- AM43XX_CM_MPU_MPU_CDOFFS
- AM43XX_CM_MPU_MPU_CLKCTRL
- AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET
- AM43XX_CM_PARTITION
- AM43XX_CM_PER_AES0_CLKCTRL_OFFSET
- AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET
- AM43XX_CM_PER_CPSW_CDOFFS
- AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET
- AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET
- AM43XX_CM_PER_DES_CLKCTRL_OFFSET
- AM43XX_CM_PER_DSS_CDOFFS
- AM43XX_CM_PER_DSS_CLKCTRL_OFFSET
- AM43XX_CM_PER_ELM_CLKCTRL_OFFSET
- AM43XX_CM_PER_EMIF_CDOFFS
- AM43XX_CM_PER_EMIF_CLKCTRL
- AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET
- AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET
- AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET
- AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET
- AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET
- AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET
- AM43XX_CM_PER_ICSS_CDOFFS
- AM43XX_CM_PER_INST
- AM43XX_CM_PER_L3S_CDOFFS
- AM43XX_CM_PER_L3_CDOFFS
- AM43XX_CM_PER_L3_CLKCTRL_OFFSET
- AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET
- AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET
- AM43XX_CM_PER_L4LS_CDOFFS
- AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET
- AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET
- AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET
- AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET
- AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET
- AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET
- AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET
- AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET
- AM43XX_CM_PER_OCPWP_L3_CDOFFS
- AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET
- AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET
- AM43XX_CM_PER_RNG_CLKCTRL_OFFSET
- AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET
- AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET
- AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET
- AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET
- AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET
- AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET
- AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET
- AM43XX_CM_PER_UART1_CLKCTRL_OFFSET
- AM43XX_CM_PER_UART2_CLKCTRL_OFFSET
- AM43XX_CM_PER_UART3_CLKCTRL_OFFSET
- AM43XX_CM_PER_UART4_CLKCTRL_OFFSET
- AM43XX_CM_PER_UART5_CLKCTRL_OFFSET
- AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET
- AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET
- AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET
- AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET
- AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET
- AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET
- AM43XX_CM_REGADDR
- AM43XX_CM_RTC_INST
- AM43XX_CM_RTC_RTC_CDOFFS
- AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET
- AM43XX_CM_TAMPER_INST
- AM43XX_CM_TAMPER_TAMPER_CDOFFS
- AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_INST
- AM43XX_CM_WKUP_L3S_TSC_CDOFFS
- AM43XX_CM_WKUP_L3_AON_CDOFFS
- AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS
- AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET
- AM43XX_CM_WKUP_WKUP_CDOFFS
- AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET
- AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET
- AM43XX_CONTROL_CQDETECT_STS2_OFFSET
- AM43XX_CONTROL_CQDETECT_STS_OFFSET
- AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET
- AM43XX_CONTROL_GMII_SEL_OFFSET
- AM43XX_CONTROL_MPUSS_CTRL_OFFSET
- AM43XX_CONTROL_MPU_L2_CTRL_OFFSET
- AM43XX_CONTROL_PWMSS_CTRL_OFFSET
- AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET
- AM43XX_CONTROL_USB_CTRL2_OFFSET
- AM43XX_CONTROL_VTP_CTRL_OFFSET
- AM43XX_EMIF_PHY_CTRL_REG_COUNT
- AM43XX_EMIF_POWEROFF_DISABLE
- AM43XX_EMIF_POWEROFF_ENABLE
- AM43XX_GIC_DIST_BASE
- AM43XX_IRQS
- AM43XX_NR_REG_BANKS
- AM43XX_PRCM_BASE
- AM43XX_PRM_CEFUSE_INST
- AM43XX_PRM_DEVICE_INST
- AM43XX_PRM_EMIF_CTRL_OFFSET
- AM43XX_PRM_GFX_INST
- AM43XX_PRM_IO_PMCTRL_OFFSET
- AM43XX_PRM_IRQENABLE_MPU_OFFSET
- AM43XX_PRM_IRQSTATUS_MPU_OFFSET
- AM43XX_PRM_MPU_INST
- AM43XX_PRM_OCP_SOCKET_INST
- AM43XX_PRM_PARTITION
- AM43XX_PRM_PER_INST
- AM43XX_PRM_RTC_INST
- AM43XX_PRM_TAMPER_INST
- AM43XX_PRM_WKUP_INST
- AM43XX_RM_GFX_RSTCTRL_OFFSET
- AM43XX_RM_GFX_RSTST_OFFSET
- AM43XX_RM_PER_RSTCTRL_OFFSET
- AM43XX_RM_PER_RSTST_OFFSET
- AM43XX_RM_WKUP_RSTCTRL_OFFSET
- AM43XX_RM_WKUP_RSTST_OFFSET
- AM4_ADC_TSC_CLKCTRL
- AM4_AES_CLKCTRL
- AM4_CLKCTRL_INDEX
- AM4_CLKCTRL_OFFSET
- AM4_CONTROL_CLKCTRL
- AM4_COUNTER_32K_CLKCTRL
- AM4_CPGMAC0_CLKCTRL
- AM4_CPSW_125MHZ_CLKCTRL_INDEX
- AM4_CPSW_125MHZ_CLKCTRL_OFFSET
- AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL
- AM4_DES_CLKCTRL
- AM4_DSS_CLKCTRL_INDEX
- AM4_DSS_CLKCTRL_OFFSET
- AM4_DSS_CORE_CLKCTRL
- AM4_DSS_DSS_CORE_CLKCTRL
- AM4_D_CAN0_CLKCTRL
- AM4_D_CAN1_CLKCTRL
- AM4_ELM_CLKCTRL
- AM4_EMIF_CLKCTRL
- AM4_EMIF_CLKCTRL_INDEX
- AM4_EMIF_CLKCTRL_OFFSET
- AM4_EMIF_EMIF_CLKCTRL
- AM4_EPWMSS0_CLKCTRL
- AM4_EPWMSS1_CLKCTRL
- AM4_EPWMSS2_CLKCTRL
- AM4_EPWMSS3_CLKCTRL
- AM4_EPWMSS4_CLKCTRL
- AM4_EPWMSS5_CLKCTRL
- AM4_GFX_CLKCTRL
- AM4_GFX_L3_GFX_CLKCTRL
- AM4_GPIO1_CLKCTRL
- AM4_GPIO2_CLKCTRL
- AM4_GPIO3_CLKCTRL
- AM4_GPIO4_CLKCTRL
- AM4_GPIO5_CLKCTRL
- AM4_GPIO6_CLKCTRL
- AM4_GPMC_CLKCTRL
- AM4_HDQ1W_CLKCTRL
- AM4_I2C1_CLKCTRL
- AM4_I2C2_CLKCTRL
- AM4_I2C3_CLKCTRL
- AM4_L3S_CLKCTRL_INDEX
- AM4_L3S_CLKCTRL_OFFSET
- AM4_L3S_GPMC_CLKCTRL
- AM4_L3S_MCASP0_CLKCTRL
- AM4_L3S_MCASP1_CLKCTRL
- AM4_L3S_MMC3_CLKCTRL
- AM4_L3S_QSPI_CLKCTRL
- AM4_L3S_TSC_ADC_TSC_CLKCTRL
- AM4_L3S_TSC_CLKCTRL_INDEX
- AM4_L3S_TSC_CLKCTRL_OFFSET
- AM4_L3S_USB_OTG_SS0_CLKCTRL
- AM4_L3S_USB_OTG_SS1_CLKCTRL
- AM4_L3S_VPFE0_CLKCTRL
- AM4_L3S_VPFE1_CLKCTRL
- AM4_L3_AES_CLKCTRL
- AM4_L3_DES_CLKCTRL
- AM4_L3_INSTR_CLKCTRL
- AM4_L3_L3_INSTR_CLKCTRL
- AM4_L3_L3_MAIN_CLKCTRL
- AM4_L3_L4_HS_CLKCTRL
- AM4_L3_MAIN_CLKCTRL
- AM4_L3_OCMCRAM_CLKCTRL
- AM4_L3_SHAM_CLKCTRL
- AM4_L3_TPCC_CLKCTRL
- AM4_L3_TPTC0_CLKCTRL
- AM4_L3_TPTC1_CLKCTRL
- AM4_L3_TPTC2_CLKCTRL
- AM4_L4LS_CLKCTRL_INDEX
- AM4_L4LS_CLKCTRL_OFFSET
- AM4_L4LS_D_CAN0_CLKCTRL
- AM4_L4LS_D_CAN1_CLKCTRL
- AM4_L4LS_ELM_CLKCTRL
- AM4_L4LS_EPWMSS0_CLKCTRL
- AM4_L4LS_EPWMSS1_CLKCTRL
- AM4_L4LS_EPWMSS2_CLKCTRL
- AM4_L4LS_EPWMSS3_CLKCTRL
- AM4_L4LS_EPWMSS4_CLKCTRL
- AM4_L4LS_EPWMSS5_CLKCTRL
- AM4_L4LS_GPIO2_CLKCTRL
- AM4_L4LS_GPIO3_CLKCTRL
- AM4_L4LS_GPIO4_CLKCTRL
- AM4_L4LS_GPIO5_CLKCTRL
- AM4_L4LS_GPIO6_CLKCTRL
- AM4_L4LS_HDQ1W_CLKCTRL
- AM4_L4LS_I2C2_CLKCTRL
- AM4_L4LS_I2C3_CLKCTRL
- AM4_L4LS_L4_LS_CLKCTRL
- AM4_L4LS_MAILBOX_CLKCTRL
- AM4_L4LS_MMC1_CLKCTRL
- AM4_L4LS_MMC2_CLKCTRL
- AM4_L4LS_OCP2SCP0_CLKCTRL
- AM4_L4LS_OCP2SCP1_CLKCTRL
- AM4_L4LS_RNG_CLKCTRL
- AM4_L4LS_SPI0_CLKCTRL
- AM4_L4LS_SPI1_CLKCTRL
- AM4_L4LS_SPI2_CLKCTRL
- AM4_L4LS_SPI3_CLKCTRL
- AM4_L4LS_SPI4_CLKCTRL
- AM4_L4LS_SPINLOCK_CLKCTRL
- AM4_L4LS_TIMER10_CLKCTRL
- AM4_L4LS_TIMER11_CLKCTRL
- AM4_L4LS_TIMER2_CLKCTRL
- AM4_L4LS_TIMER3_CLKCTRL
- AM4_L4LS_TIMER4_CLKCTRL
- AM4_L4LS_TIMER5_CLKCTRL
- AM4_L4LS_TIMER6_CLKCTRL
- AM4_L4LS_TIMER7_CLKCTRL
- AM4_L4LS_TIMER8_CLKCTRL
- AM4_L4LS_TIMER9_CLKCTRL
- AM4_L4LS_UART2_CLKCTRL
- AM4_L4LS_UART3_CLKCTRL
- AM4_L4LS_UART4_CLKCTRL
- AM4_L4LS_UART5_CLKCTRL
- AM4_L4LS_UART6_CLKCTRL
- AM4_L4_HS_CLKCTRL
- AM4_L4_LS_CLKCTRL
- AM4_L4_RTC_RTC_CLKCTRL
- AM4_L4_WKUP_AON_CLKCTRL_INDEX
- AM4_L4_WKUP_AON_CLKCTRL_OFFSET
- AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL
- AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL
- AM4_L4_WKUP_CLKCTRL
- AM4_L4_WKUP_CLKCTRL_INDEX
- AM4_L4_WKUP_CLKCTRL_OFFSET
- AM4_L4_WKUP_CONTROL_CLKCTRL
- AM4_L4_WKUP_GPIO1_CLKCTRL
- AM4_L4_WKUP_I2C1_CLKCTRL
- AM4_L4_WKUP_L4_WKUP_CLKCTRL
- AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL
- AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL
- AM4_L4_WKUP_TIMER1_CLKCTRL
- AM4_L4_WKUP_UART1_CLKCTRL
- AM4_L4_WKUP_WD_TIMER2_CLKCTRL
- AM4_MAILBOX_CLKCTRL
- AM4_MCASP0_CLKCTRL
- AM4_MCASP1_CLKCTRL
- AM4_MMC1_CLKCTRL
- AM4_MMC2_CLKCTRL
- AM4_MMC3_CLKCTRL
- AM4_MPU_CLKCTRL
- AM4_MPU_MPU_CLKCTRL
- AM4_OCMCRAM_CLKCTRL
- AM4_OCP2SCP0_CLKCTRL
- AM4_OCP2SCP1_CLKCTRL
- AM4_PRUSS_CLKCTRL
- AM4_PRUSS_OCP_CLKCTRL_INDEX
- AM4_PRUSS_OCP_CLKCTRL_OFFSET
- AM4_PRUSS_OCP_PRUSS_CLKCTRL
- AM4_QSPI_CLKCTRL
- AM4_RNG_CLKCTRL
- AM4_RTC_CLKCTRL
- AM4_SHAM_CLKCTRL
- AM4_SMARTREFLEX0_CLKCTRL
- AM4_SMARTREFLEX1_CLKCTRL
- AM4_SPI0_CLKCTRL
- AM4_SPI1_CLKCTRL
- AM4_SPI2_CLKCTRL
- AM4_SPI3_CLKCTRL
- AM4_SPI4_CLKCTRL
- AM4_SPINLOCK_CLKCTRL
- AM4_TIMER10_CLKCTRL
- AM4_TIMER11_CLKCTRL
- AM4_TIMER1_CLKCTRL
- AM4_TIMER2_CLKCTRL
- AM4_TIMER3_CLKCTRL
- AM4_TIMER4_CLKCTRL
- AM4_TIMER5_CLKCTRL
- AM4_TIMER6_CLKCTRL
- AM4_TIMER7_CLKCTRL
- AM4_TIMER8_CLKCTRL
- AM4_TIMER9_CLKCTRL
- AM4_TPCC_CLKCTRL
- AM4_TPTC0_CLKCTRL
- AM4_TPTC1_CLKCTRL
- AM4_TPTC2_CLKCTRL
- AM4_UART1_CLKCTRL
- AM4_UART2_CLKCTRL
- AM4_UART3_CLKCTRL
- AM4_UART4_CLKCTRL
- AM4_UART5_CLKCTRL
- AM4_UART6_CLKCTRL
- AM4_USB_OTG_SS0_CLKCTRL
- AM4_USB_OTG_SS1_CLKCTRL
- AM4_VPFE0_CLKCTRL
- AM4_VPFE1_CLKCTRL
- AM4_WD_TIMER2_CLKCTRL
- AM4_WKUP_M3_CLKCTRL
- AM654_HBMC_CALIB_COUNT
- AM654_PCIE_DEV_TYPE_MASK
- AM654_SERDES_CMU_REFCLK
- AM654_SERDES_CTRL_CLKSEL_MASK
- AM654_SERDES_CTRL_CLKSEL_SHIFT
- AM654_SERDES_LO_REFCLK
- AM654_SERDES_RO_REFCLK
- AM654_USB2_OTG_PD
- AM654_USB2_VBUSVALID_DET_EN
- AM654_USB2_VBUS_DET_EN
- AM654_WIN_SIZE
- AM65X_IOPAD
- AM65X_WKUP_IOPAD
- AM6_ERR_AER
- AM79C9XX_ETH_PHY
- AM79C9XX_HOME_PHY
- AM824_IN_PCM_FORMAT_BITS
- AM824_MAX_CHANNELS_FOR_MIDI
- AM824_MAX_CHANNELS_FOR_PCM
- AM824_OUT_PCM_FORMAT_BITS
- AM9513A_COM_REG
- AM9513A_DATA_REG
- AM9513A_STAT_REG
- AMAIR0
- AMAIR1
- AMAIR_EL1
- AMAPSIZE
- AMAP_1KB
- AMAP_2KB
- AMAP_4KB
- AMAP_BIT_OFFSET
- AMAP_CTRL_EN_SHIFT
- AMAP_CTRL_TYPE_MASK
- AMAP_CTRL_TYPE_SHIFT
- AMAP_GET_BITS
- AMAP_RSVD
- AMAP_SET_BITS
- AMASK_BWX
- AMASK_CIX
- AMASK_FIX
- AMASK_MAX
- AMASK_PRECISE_TRAP
- AMA_USBSS_BBONLY
- AMA_USBSS_U2_ONLY
- AMA_USBSS_U31_GEN1
- AMA_USBSS_U31_GEN2
- AMA_VCONN_PWR_1W
- AMA_VCONN_PWR_1W5
- AMA_VCONN_PWR_2W
- AMA_VCONN_PWR_3W
- AMA_VCONN_PWR_4W
- AMA_VCONN_PWR_5W
- AMA_VCONN_PWR_6W
- AMBASE
- AMBASSADOR_H
- AMBA_AHB_DEVICE
- AMBA_APB_DEVICE
- AMBA_CID
- AMBA_CLCD_REGS_H
- AMBA_CONFIG_BITS
- AMBA_CONSOLE
- AMBA_ERROR_RESPONSE_CRS_MASK
- AMBA_ERROR_RESPONSE_CRS_OKAY
- AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001
- AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF
- AMBA_ERROR_RESPONSE_CRS_SHIFT
- AMBA_ISR_PASS_LIMIT
- AMBA_LINUX_ID
- AMBA_MANF_BITS
- AMBA_MAXAPB_DEVS
- AMBA_MAXAPB_DEVS_PERBUS
- AMBA_MMCI_H
- AMBA_NR_IRQS
- AMBA_PART_BITS
- AMBA_PIO_ENABLE_SHIFT
- AMBA_PL011_H
- AMBA_PL08X_H
- AMBA_REV_BITS
- AMBA_VENDOR_ARM
- AMBA_VENDOR_LINUX
- AMBA_VENDOR_LSI
- AMBA_VENDOR_QCOM
- AMBA_VENDOR_ST
- AMBIENT_LIGHT_SENSE_ON
- AMBPRESENT_0
- AMBPRESENT_1
- AMB_CONFIG_SIZE
- AMB_DEV
- AMB_DOORBELL_BITS
- AMB_EXTENT
- AMB_FUNC_3_OFFSET
- AMB_INTERRUPT_BITS
- AMB_PRESENT_0
- AMB_PRESENT_1
- AMB_REG_TEMP_ADDR
- AMB_REG_TEMP_MAX_ADDR
- AMB_REG_TEMP_MID_ADDR
- AMB_REG_TEMP_MIN_ADDR
- AMB_REG_TEMP_STATUS_ADDR
- AMB_RESET_BITS
- AMB_SYSFS_NAME_LEN
- AMB_VCC
- AMC6821_CONF1_FANIE
- AMC6821_CONF1_FAN_FAULT_EN
- AMC6821_CONF1_FAN_INT_EN
- AMC6821_CONF1_FDRC0
- AMC6821_CONF1_FDRC1
- AMC6821_CONF1_PWMINV
- AMC6821_CONF1_START
- AMC6821_CONF1_THERMOVIE
- AMC6821_CONF2_LTOIE
- AMC6821_CONF2_PSVIE
- AMC6821_CONF2_PWM_EN
- AMC6821_CONF2_RST
- AMC6821_CONF2_RTFIE
- AMC6821_CONF2_RTOIE
- AMC6821_CONF2_TACH_EN
- AMC6821_CONF2_TACH_MODE
- AMC6821_CONF3_REV_MASK
- AMC6821_CONF3_THERM_FAN_EN
- AMC6821_CONF4_MODE
- AMC6821_CONF4_OVREN
- AMC6821_CONF4_PSPR
- AMC6821_CONF4_TACH_FAST
- AMC6821_REG_COMP_ID
- AMC6821_REG_CONF1
- AMC6821_REG_CONF2
- AMC6821_REG_CONF3
- AMC6821_REG_CONF4
- AMC6821_REG_DCY
- AMC6821_REG_DCY_LOW_TEMP
- AMC6821_REG_DEV_ID
- AMC6821_REG_LTEMP_CRIT
- AMC6821_REG_LTEMP_FAN_CTRL
- AMC6821_REG_LTEMP_HI
- AMC6821_REG_LTEMP_LIMIT_MAX
- AMC6821_REG_LTEMP_LIMIT_MIN
- AMC6821_REG_PSV_TEMP
- AMC6821_REG_RTEMP_CRIT
- AMC6821_REG_RTEMP_FAN_CTRL
- AMC6821_REG_RTEMP_HI
- AMC6821_REG_RTEMP_LIMIT_MAX
- AMC6821_REG_RTEMP_LIMIT_MIN
- AMC6821_REG_STAT1
- AMC6821_REG_STAT2
- AMC6821_REG_TACH_HLIMITH
- AMC6821_REG_TACH_HLIMITL
- AMC6821_REG_TACH_LLIMITH
- AMC6821_REG_TACH_LLIMITL
- AMC6821_REG_TDATA_HI
- AMC6821_REG_TDATA_LOW
- AMC6821_STAT1_FANS
- AMC6821_STAT1_LTH
- AMC6821_STAT1_LTL
- AMC6821_STAT1_RPM_ALARM
- AMC6821_STAT1_RTF
- AMC6821_STAT1_RTH
- AMC6821_STAT1_RTL
- AMC6821_STAT1_R_THERM
- AMC6821_STAT2_LPSV
- AMC6821_STAT2_LTC
- AMC6821_STAT2_L_THERM
- AMC6821_STAT2_RTC
- AMC6821_STAT2_THERM_IN
- AMCC_FIFO_DEPTH_BYTES
- AMCC_FIFO_DEPTH_DWORD
- AMCC_INTCSR
- AMCC_MCSR
- AMCC_OP_REG_AFIFO
- AMCC_OP_REG_AGCSTS
- AMCC_OP_REG_AIMB1
- AMCC_OP_REG_AIMB2
- AMCC_OP_REG_AIMB3
- AMCC_OP_REG_AIMB4
- AMCC_OP_REG_AINT
- AMCC_OP_REG_AMBEF
- AMCC_OP_REG_AMRAR
- AMCC_OP_REG_AMRTC
- AMCC_OP_REG_AMWAR
- AMCC_OP_REG_AMWTC
- AMCC_OP_REG_AOMB1
- AMCC_OP_REG_AOMB2
- AMCC_OP_REG_AOMB3
- AMCC_OP_REG_AOMB4
- AMCC_OP_REG_APTA
- AMCC_OP_REG_APTD
- AMCC_OP_REG_FIFO
- AMCC_OP_REG_IMB1
- AMCC_OP_REG_IMB2
- AMCC_OP_REG_IMB3
- AMCC_OP_REG_IMB4
- AMCC_OP_REG_INTCSR
- AMCC_OP_REG_INTCSR_FEC
- AMCC_OP_REG_INTCSR_SRC
- AMCC_OP_REG_MBEF
- AMCC_OP_REG_MCSR
- AMCC_OP_REG_MCSR_NVCMD
- AMCC_OP_REG_MCSR_NVDATA
- AMCC_OP_REG_MRAR
- AMCC_OP_REG_MRTC
- AMCC_OP_REG_MWAR
- AMCC_OP_REG_MWTC
- AMCC_OP_REG_OMB1
- AMCC_OP_REG_OMB2
- AMCC_OP_REG_OMB3
- AMCC_OP_REG_OMB4
- AMCC_OP_REG_SIZE
- AMCC_RXLEN
- AMCC_RXPTR
- AMCC_TXLEN
- AMCC_TXPTR
- AMC_B1
- AMC_B2
- AMD5536UDC_H
- AMD64_EVENTSEL_EVENT
- AMD64_EVENTSEL_GUESTONLY
- AMD64_EVENTSEL_HOSTONLY
- AMD64_EVENTSEL_INT_CORE_ENABLE
- AMD64_EVENTSEL_INT_CORE_SEL_MASK
- AMD64_EVENTSEL_INT_CORE_SEL_SHIFT
- AMD64_GARTAPERTUREBASE
- AMD64_GARTAPERTURECTL
- AMD64_GARTCACHECTL
- AMD64_GARTTABLEBASE
- AMD64_L3_SLICE_MASK
- AMD64_L3_SLICE_SHIFT
- AMD64_L3_THREAD_MASK
- AMD64_L3_THREAD_SHIFT
- AMD64_NUM_COUNTERS
- AMD64_NUM_COUNTERS_CORE
- AMD64_NUM_COUNTERS_NB
- AMD64_RAW_EVENT_MASK
- AMD64_RAW_EVENT_MASK_NB
- AMD756
- AMD756_BLOCK_DATA
- AMD756_BYTE
- AMD756_BYTE_DATA
- AMD756_PROCESS_CALL
- AMD756_QUICK
- AMD756_WORD_DATA
- AMD761
- AMD762
- AMD766
- AMD768
- AMD76X_DRAM_MODE_STATUS
- AMD76X_ECC_MODE_STATUS
- AMD76X_MEM_BASE_ADDR
- AMD76X_NR_CSROWS
- AMD76X_NR_DIMMS
- AMD7930_BBRB
- AMD7930_BBTB
- AMD7930_BCRB
- AMD7930_BCTB
- AMD7930_CR
- AMD7930_DCRB
- AMD7930_DCTB
- AMD7930_DER
- AMD7930_DR
- AMD7930_DSR1
- AMD7930_DSR2
- AMD7930_FLAG_CAPTURE
- AMD7930_FLAG_PLAYBACK
- AMD7930_IR
- AMD8111
- AMD8111E_MAX_MTU
- AMD8111E_MIN_MTU
- AMD8111E_REG_DUMP_LEN
- AMD8111E_TX_TIMEOUT
- AMD8111E_VLAN_TAG_USED
- AMD8111_EDAC_MOD_STR
- AMD8111_EDAC_REVISION
- AMD8131_EDAC_MOD_STR
- AMD8131_EDAC_REVISION
- AMDGIM_DATAEXCHANGE_OFFSET
- AMDGIM_ERROR_CATEGORY
- AMDGIM_ERROR_CATEGORY_GIM
- AMDGIM_ERROR_CATEGORY_MAX
- AMDGIM_ERROR_CATEGORY_MONITOR
- AMDGIM_ERROR_CATEGORY_NON_USED
- AMDGIM_ERROR_CATEGORY_PF
- AMDGIM_ERROR_CATEGORY_VBIOS
- AMDGIM_ERROR_CATEGORY_VF
- AMDGIM_ERROR_CODE
- AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX
- AMDGIM_ERROR_VF
- AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL
- AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL
- AMDGIM_ERROR_VF_ASIC_RESUME_FAIL
- AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL
- AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL
- AMDGIM_ERROR_VF_FENCE_INIT_FAIL
- AMDGIM_ERROR_VF_GPU_POST_ERROR
- AMDGIM_ERROR_VF_GPU_RESET_FAIL
- AMDGIM_ERROR_VF_IB_INIT_FAIL
- AMDGIM_ERROR_VF_MAX
- AMDGIM_ERROR_VF_NO_VBIOS
- AMDGIM_ERROR_VF_TEST
- AMDGIM_FEATURE_ERROR_LOG_COLLECT
- AMDGIM_FEATURE_FLAG
- AMDGIM_FEATURE_GIM_FLR_VRAMLOST
- AMDGIM_FEATURE_GIM_LOAD_UCODES
- AMDGIM_FEATURE_HW_PERF_SIMULATION
- AMDGIM_GET_STRUCTURE_RESERVED_SIZE
- AMDGPUFB_CONN_LIMIT
- AMDGPU_AMDKFD_H_INCLUDED
- AMDGPU_AMDKFD_USERPTR_BO
- AMDGPU_ASIC_RESET_DATA
- AMDGPU_AUDIO_AUTO
- AMDGPU_AUDIO_DISABLE
- AMDGPU_AUDIO_ENABLE
- AMDGPU_BENCHMARK_COMMON_MODES_N
- AMDGPU_BENCHMARK_ITERATIONS
- AMDGPU_BIOS_NUM_SCRATCH
- AMDGPU_BO_INVALID_OFFSET
- AMDGPU_BO_LIST_MAX_PRIORITY
- AMDGPU_BO_LIST_NUM_BUCKETS
- AMDGPU_BO_LIST_OP_CREATE
- AMDGPU_BO_LIST_OP_DESTROY
- AMDGPU_BO_LIST_OP_UPDATE
- AMDGPU_BO_MAX_PLACEMENTS
- AMDGPU_CHUNK_ID_BO_HANDLES
- AMDGPU_CHUNK_ID_DEPENDENCIES
- AMDGPU_CHUNK_ID_FENCE
- AMDGPU_CHUNK_ID_IB
- AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
- AMDGPU_CHUNK_ID_SYNCOBJ_IN
- AMDGPU_CHUNK_ID_SYNCOBJ_OUT
- AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL
- AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT
- AMDGPU_CPCE_UCODE_LOADED
- AMDGPU_CPMEC1_UCODE_LOADED
- AMDGPU_CPMEC2_UCODE_LOADED
- AMDGPU_CPME_UCODE_LOADED
- AMDGPU_CPPFP_UCODE_LOADED
- AMDGPU_CPRLC_UCODE_LOADED
- AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
- AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
- AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP
- AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP
- AMDGPU_CP_IRQ_LAST
- AMDGPU_CP_KIQ_IRQ_DRIVER0
- AMDGPU_CP_KIQ_IRQ_LAST
- AMDGPU_CRTC_IRQ_NONE
- AMDGPU_CRTC_IRQ_VBLANK1
- AMDGPU_CRTC_IRQ_VBLANK2
- AMDGPU_CRTC_IRQ_VBLANK3
- AMDGPU_CRTC_IRQ_VBLANK4
- AMDGPU_CRTC_IRQ_VBLANK5
- AMDGPU_CRTC_IRQ_VBLANK6
- AMDGPU_CRTC_IRQ_VLINE1
- AMDGPU_CRTC_IRQ_VLINE2
- AMDGPU_CRTC_IRQ_VLINE3
- AMDGPU_CRTC_IRQ_VLINE4
- AMDGPU_CRTC_IRQ_VLINE5
- AMDGPU_CRTC_IRQ_VLINE6
- AMDGPU_CSA_MANAGER_H
- AMDGPU_CSA_SDMA_OFFSET
- AMDGPU_CSA_SDMA_SIZE
- AMDGPU_CSA_SIZE
- AMDGPU_CTX_GUILTY_RESET
- AMDGPU_CTX_INNOCENT_RESET
- AMDGPU_CTX_NO_RESET
- AMDGPU_CTX_OP_ALLOC_CTX
- AMDGPU_CTX_OP_FREE_CTX
- AMDGPU_CTX_OP_QUERY_STATE
- AMDGPU_CTX_OP_QUERY_STATE2
- AMDGPU_CTX_PRIORITY_HIGH
- AMDGPU_CTX_PRIORITY_LOW
- AMDGPU_CTX_PRIORITY_NORMAL
- AMDGPU_CTX_PRIORITY_UNSET
- AMDGPU_CTX_PRIORITY_VERY_HIGH
- AMDGPU_CTX_PRIORITY_VERY_LOW
- AMDGPU_CTX_QUERY2_FLAGS_GUILTY
- AMDGPU_CTX_QUERY2_FLAGS_RAS_CE
- AMDGPU_CTX_QUERY2_FLAGS_RAS_UE
- AMDGPU_CTX_QUERY2_FLAGS_RESET
- AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST
- AMDGPU_CTX_UNKNOWN_RESET
- AMDGPU_DEBUGFS_MAX_COMPONENTS
- AMDGPU_DEFAULT_GTT_SIZE_MB
- AMDGPU_DEFAULT_PCIE_GEN_MASK
- AMDGPU_DEFAULT_PCIE_MLW_MASK
- AMDGPU_DEFAULT_UVD_HANDLES
- AMDGPU_DISPLAY_WATERMARK_HIGH
- AMDGPU_DISPLAY_WATERMARK_LOW
- AMDGPU_DM_DEFAULT_MAX_BACKLIGHT
- AMDGPU_DM_DEFAULT_MIN_BACKLIGHT
- AMDGPU_DM_MAX_DISPLAY_INDEX
- AMDGPU_DM_PIPE_CRC_SOURCE_CRTC
- AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER
- AMDGPU_DM_PIPE_CRC_SOURCE_DPRX
- AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER
- AMDGPU_DM_PIPE_CRC_SOURCE_INVALID
- AMDGPU_DM_PIPE_CRC_SOURCE_MAX
- AMDGPU_DM_PIPE_CRC_SOURCE_NONE
- AMDGPU_DOORBELL64_ASSIGNMENT
- AMDGPU_DOORBELL64_DIQ
- AMDGPU_DOORBELL64_FIRST_NON_CP
- AMDGPU_DOORBELL64_GFX_RING0
- AMDGPU_DOORBELL64_HIQ
- AMDGPU_DOORBELL64_IH
- AMDGPU_DOORBELL64_IH_RING1
- AMDGPU_DOORBELL64_IH_RING2
- AMDGPU_DOORBELL64_INVALID
- AMDGPU_DOORBELL64_KIQ
- AMDGPU_DOORBELL64_LAST_NON_CP
- AMDGPU_DOORBELL64_MAX_ASSIGNMENT
- AMDGPU_DOORBELL64_MEC_RING0
- AMDGPU_DOORBELL64_MEC_RING1
- AMDGPU_DOORBELL64_MEC_RING2
- AMDGPU_DOORBELL64_MEC_RING3
- AMDGPU_DOORBELL64_MEC_RING4
- AMDGPU_DOORBELL64_MEC_RING5
- AMDGPU_DOORBELL64_MEC_RING6
- AMDGPU_DOORBELL64_MEC_RING7
- AMDGPU_DOORBELL64_USERQUEUE_END
- AMDGPU_DOORBELL64_USERQUEUE_START
- AMDGPU_DOORBELL64_UVD_RING0_1
- AMDGPU_DOORBELL64_UVD_RING2_3
- AMDGPU_DOORBELL64_UVD_RING4_5
- AMDGPU_DOORBELL64_UVD_RING6_7
- AMDGPU_DOORBELL64_VCE_RING0_1
- AMDGPU_DOORBELL64_VCE_RING2_3
- AMDGPU_DOORBELL64_VCE_RING4_5
- AMDGPU_DOORBELL64_VCE_RING6_7
- AMDGPU_DOORBELL64_VCN0_1
- AMDGPU_DOORBELL64_VCN2_3
- AMDGPU_DOORBELL64_VCN4_5
- AMDGPU_DOORBELL64_VCN6_7
- AMDGPU_DOORBELL64_sDMA_ENGINE0
- AMDGPU_DOORBELL64_sDMA_ENGINE1
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0
- AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1
- AMDGPU_DOORBELL_ASSIGNMENT
- AMDGPU_DOORBELL_DIQ
- AMDGPU_DOORBELL_GFX_RING0
- AMDGPU_DOORBELL_HIQ
- AMDGPU_DOORBELL_IH
- AMDGPU_DOORBELL_INVALID
- AMDGPU_DOORBELL_KIQ
- AMDGPU_DOORBELL_MAX_ASSIGNMENT
- AMDGPU_DOORBELL_MEC_RING0
- AMDGPU_DOORBELL_MEC_RING1
- AMDGPU_DOORBELL_MEC_RING2
- AMDGPU_DOORBELL_MEC_RING3
- AMDGPU_DOORBELL_MEC_RING4
- AMDGPU_DOORBELL_MEC_RING5
- AMDGPU_DOORBELL_MEC_RING6
- AMDGPU_DOORBELL_MEC_RING7
- AMDGPU_DOORBELL_sDMA_ENGINE0
- AMDGPU_DOORBELL_sDMA_ENGINE1
- AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
- AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
- AMDGPU_DPM_EVENT_SRC_ANALOG
- AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
- AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
- AMDGPU_DPM_EVENT_SRC_DIGITAL
- AMDGPU_DPM_EVENT_SRC_EXTERNAL
- AMDGPU_FAMILY_AI
- AMDGPU_FAMILY_CI
- AMDGPU_FAMILY_CZ
- AMDGPU_FAMILY_KV
- AMDGPU_FAMILY_NV
- AMDGPU_FAMILY_RV
- AMDGPU_FAMILY_SI
- AMDGPU_FAMILY_UNKNOWN
- AMDGPU_FAMILY_VI
- AMDGPU_FENCE_FLAG_64BIT
- AMDGPU_FENCE_FLAG_INT
- AMDGPU_FENCE_FLAG_TC_WB_ONLY
- AMDGPU_FENCE_JIFFIES_TIMEOUT
- AMDGPU_FENCE_OWNER_KFD
- AMDGPU_FENCE_OWNER_UNDEFINED
- AMDGPU_FENCE_OWNER_VM
- AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ
- AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD
- AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD
- AMDGPU_FLIP_NONE
- AMDGPU_FLIP_PENDING
- AMDGPU_FLIP_SUBMITTED
- AMDGPU_FMT_DITHER_DISABLE
- AMDGPU_FMT_DITHER_ENABLE
- AMDGPU_FW_LOAD_DIRECT
- AMDGPU_FW_LOAD_PSP
- AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO
- AMDGPU_FW_LOAD_SMU
- AMDGPU_FW_VRAM_PF2VF_READ
- AMDGPU_FW_VRAM_VF2PF_READ
- AMDGPU_FW_VRAM_VF2PF_VER
- AMDGPU_FW_VRAM_VF2PF_WRITE
- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
- AMDGPU_GEM_CREATE_CPU_GTT_USWC
- AMDGPU_GEM_CREATE_EXPLICIT_SYNC
- AMDGPU_GEM_CREATE_MQD_GFX9
- AMDGPU_GEM_CREATE_NO_CPU_ACCESS
- AMDGPU_GEM_CREATE_SHADOW
- AMDGPU_GEM_CREATE_VM_ALWAYS_VALID
- AMDGPU_GEM_CREATE_VRAM_CLEARED
- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
- AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE
- AMDGPU_GEM_DOMAIN_CPU
- AMDGPU_GEM_DOMAIN_GDS
- AMDGPU_GEM_DOMAIN_GTT
- AMDGPU_GEM_DOMAIN_GWS
- AMDGPU_GEM_DOMAIN_MASK
- AMDGPU_GEM_DOMAIN_MAX
- AMDGPU_GEM_DOMAIN_OA
- AMDGPU_GEM_DOMAIN_VRAM
- AMDGPU_GEM_METADATA_OP_GET_METADATA
- AMDGPU_GEM_METADATA_OP_SET_METADATA
- AMDGPU_GEM_OP_GET_GEM_CREATE_INFO
- AMDGPU_GEM_OP_SET_PLACEMENT
- AMDGPU_GEM_USERPTR_ANONONLY
- AMDGPU_GEM_USERPTR_READONLY
- AMDGPU_GEM_USERPTR_REGISTER
- AMDGPU_GEM_USERPTR_VALIDATE
- AMDGPU_GFXHUB_0
- AMDGPU_GFX_CG_DISABLED_MODE
- AMDGPU_GFX_LBPW_DISABLED_MODE
- AMDGPU_GFX_MAX_SE
- AMDGPU_GFX_MAX_SH_PER_SE
- AMDGPU_GFX_NORMAL_MODE
- AMDGPU_GFX_PG_DISABLED_MODE
- AMDGPU_GFX_SAFE_MODE
- AMDGPU_GMC_FAULT_HASH_ORDER
- AMDGPU_GMC_FAULT_HASH_SIZE
- AMDGPU_GMC_FAULT_RING_ORDER
- AMDGPU_GMC_FAULT_RING_SIZE
- AMDGPU_GMC_FAULT_TIMEOUT
- AMDGPU_GMC_HOLE_END
- AMDGPU_GMC_HOLE_MASK
- AMDGPU_GMC_HOLE_START
- AMDGPU_GPU_PAGES_IN_CPU_PAGE
- AMDGPU_GPU_PAGE_ALIGN
- AMDGPU_GPU_PAGE_MASK
- AMDGPU_GPU_PAGE_SHIFT
- AMDGPU_GPU_PAGE_SIZE
- AMDGPU_GTT_MAX_TRANSFER_SIZE
- AMDGPU_GTT_NUM_TRANSFER_WINDOWS
- AMDGPU_HAVE_CTX_SWITCH
- AMDGPU_HPD_1
- AMDGPU_HPD_2
- AMDGPU_HPD_3
- AMDGPU_HPD_4
- AMDGPU_HPD_5
- AMDGPU_HPD_6
- AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
- AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
- AMDGPU_HPD_NONE
- AMDGPU_HW_IP_COMPUTE
- AMDGPU_HW_IP_DMA
- AMDGPU_HW_IP_GFX
- AMDGPU_HW_IP_INSTANCE_MAX_COUNT
- AMDGPU_HW_IP_NUM
- AMDGPU_HW_IP_UVD
- AMDGPU_HW_IP_UVD_ENC
- AMDGPU_HW_IP_VCE
- AMDGPU_HW_IP_VCN_DEC
- AMDGPU_HW_IP_VCN_ENC
- AMDGPU_HW_IP_VCN_JPEG
- AMDGPU_IB_FLAG_CE
- AMDGPU_IB_FLAG_PREAMBLE
- AMDGPU_IB_FLAG_PREEMPT
- AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
- AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
- AMDGPU_IB_POOL_SIZE
- AMDGPU_IB_PREEMPTED
- AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT
- AMDGPU_IB_TEST_TIMEOUT
- AMDGPU_IDS_FLAGS_FUSION
- AMDGPU_IDS_FLAGS_PREEMPTION
- AMDGPU_IH_MAX_NUM_IVS
- AMDGPU_INFO_ACCEL_WORKING
- AMDGPU_INFO_CRTC_FROM_ID
- AMDGPU_INFO_DEV_INFO
- AMDGPU_INFO_FW_ASD
- AMDGPU_INFO_FW_DMCU
- AMDGPU_INFO_FW_GFX_CE
- AMDGPU_INFO_FW_GFX_ME
- AMDGPU_INFO_FW_GFX_MEC
- AMDGPU_INFO_FW_GFX_PFP
- AMDGPU_INFO_FW_GFX_RLC
- AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL
- AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM
- AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM
- AMDGPU_INFO_FW_GMC
- AMDGPU_INFO_FW_SDMA
- AMDGPU_INFO_FW_SMC
- AMDGPU_INFO_FW_SOS
- AMDGPU_INFO_FW_TA
- AMDGPU_INFO_FW_UVD
- AMDGPU_INFO_FW_VCE
- AMDGPU_INFO_FW_VCN
- AMDGPU_INFO_FW_VERSION
- AMDGPU_INFO_GDS_CONFIG
- AMDGPU_INFO_GTT_USAGE
- AMDGPU_INFO_HW_IP_COUNT
- AMDGPU_INFO_HW_IP_INFO
- AMDGPU_INFO_MEMORY
- AMDGPU_INFO_MMR_SE_INDEX_MASK
- AMDGPU_INFO_MMR_SE_INDEX_SHIFT
- AMDGPU_INFO_MMR_SH_INDEX_MASK
- AMDGPU_INFO_MMR_SH_INDEX_SHIFT
- AMDGPU_INFO_NUM_BYTES_MOVED
- AMDGPU_INFO_NUM_EVICTIONS
- AMDGPU_INFO_NUM_HANDLES
- AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS
- AMDGPU_INFO_RAS_ENABLED_ATHUB
- AMDGPU_INFO_RAS_ENABLED_DF
- AMDGPU_INFO_RAS_ENABLED_FEATURES
- AMDGPU_INFO_RAS_ENABLED_FUSE
- AMDGPU_INFO_RAS_ENABLED_GFX
- AMDGPU_INFO_RAS_ENABLED_HDP
- AMDGPU_INFO_RAS_ENABLED_MMHUB
- AMDGPU_INFO_RAS_ENABLED_MP0
- AMDGPU_INFO_RAS_ENABLED_MP1
- AMDGPU_INFO_RAS_ENABLED_PCIE
- AMDGPU_INFO_RAS_ENABLED_SDMA
- AMDGPU_INFO_RAS_ENABLED_SEM
- AMDGPU_INFO_RAS_ENABLED_SMN
- AMDGPU_INFO_RAS_ENABLED_UMC
- AMDGPU_INFO_RAS_ENABLED_XGMI
- AMDGPU_INFO_READ_MMR_REG
- AMDGPU_INFO_SENSOR
- AMDGPU_INFO_SENSOR_GFX_MCLK
- AMDGPU_INFO_SENSOR_GFX_SCLK
- AMDGPU_INFO_SENSOR_GPU_AVG_POWER
- AMDGPU_INFO_SENSOR_GPU_LOAD
- AMDGPU_INFO_SENSOR_GPU_TEMP
- AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK
- AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK
- AMDGPU_INFO_SENSOR_VDDGFX
- AMDGPU_INFO_SENSOR_VDDNB
- AMDGPU_INFO_TIMESTAMP
- AMDGPU_INFO_VBIOS
- AMDGPU_INFO_VBIOS_IMAGE
- AMDGPU_INFO_VBIOS_SIZE
- AMDGPU_INFO_VCE_CLOCK_TABLE
- AMDGPU_INFO_VIS_VRAM_USAGE
- AMDGPU_INFO_VRAM_GTT
- AMDGPU_INFO_VRAM_LOST_COUNTER
- AMDGPU_INFO_VRAM_USAGE
- AMDGPU_IRQ_CLIENTID_LEGACY
- AMDGPU_IRQ_CLIENTID_MAX
- AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW
- AMDGPU_IRQ_STATE_DISABLE
- AMDGPU_IRQ_STATE_ENABLE
- AMDGPU_JOB_GET_TIMELINE_NAME
- AMDGPU_JOB_GET_VMID
- AMDGPU_MASK_BUF_MAX
- AMDGPU_MAX_AFMT_BLOCKS
- AMDGPU_MAX_BIOS_CONNECTOR
- AMDGPU_MAX_BL_LEVEL
- AMDGPU_MAX_COMPUTE_QUEUES
- AMDGPU_MAX_COMPUTE_RINGS
- AMDGPU_MAX_CRTCS
- AMDGPU_MAX_DF_PERFMONS
- AMDGPU_MAX_GFX_QUEUES
- AMDGPU_MAX_GFX_RINGS
- AMDGPU_MAX_HPD_PINS
- AMDGPU_MAX_I2C_BUS
- AMDGPU_MAX_IP_NUM
- AMDGPU_MAX_IRQ_CLIENT_ID
- AMDGPU_MAX_IRQ_SRC_ID
- AMDGPU_MAX_PLANES
- AMDGPU_MAX_PPLL
- AMDGPU_MAX_RINGS
- AMDGPU_MAX_SDMA_INSTANCES
- AMDGPU_MAX_TIMEOUT_PARAM_LENTH
- AMDGPU_MAX_USEC_TIMEOUT
- AMDGPU_MAX_UVD_ENC_RINGS
- AMDGPU_MAX_UVD_HANDLES
- AMDGPU_MAX_UVD_INSTANCES
- AMDGPU_MAX_VCE_HANDLES
- AMDGPU_MAX_VCE_RINGS
- AMDGPU_MAX_VCN_INSTANCES
- AMDGPU_MAX_VMHUBS
- AMDGPU_MAX_WB
- AMDGPU_MAX_XGMI_DEVICE_PER_HIVE
- AMDGPU_MAX_XGMI_HIVE
- AMDGPU_MMHUB_0
- AMDGPU_MMHUB_1
- AMDGPU_MM_DATA
- AMDGPU_MM_INDEX
- AMDGPU_MN_KEY
- AMDGPU_MN_TYPE_GFX
- AMDGPU_MN_TYPE_HSA
- AMDGPU_MODE_H
- AMDGPU_MTYPE_CC
- AMDGPU_MTYPE_NC
- AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP
- AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP
- AMDGPU_NAVI10_DOORBELL64_VCN0_1
- AMDGPU_NAVI10_DOORBELL64_VCN2_3
- AMDGPU_NAVI10_DOORBELL64_VCN4_5
- AMDGPU_NAVI10_DOORBELL64_VCN6_7
- AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
- AMDGPU_NAVI10_DOORBELL_DIQ
- AMDGPU_NAVI10_DOORBELL_GFX_RING0
- AMDGPU_NAVI10_DOORBELL_GFX_RING1
- AMDGPU_NAVI10_DOORBELL_HIQ
- AMDGPU_NAVI10_DOORBELL_IH
- AMDGPU_NAVI10_DOORBELL_INVALID
- AMDGPU_NAVI10_DOORBELL_KIQ
- AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT
- AMDGPU_NAVI10_DOORBELL_MEC_RING0
- AMDGPU_NAVI10_DOORBELL_MEC_RING1
- AMDGPU_NAVI10_DOORBELL_MEC_RING2
- AMDGPU_NAVI10_DOORBELL_MEC_RING3
- AMDGPU_NAVI10_DOORBELL_MEC_RING4
- AMDGPU_NAVI10_DOORBELL_MEC_RING5
- AMDGPU_NAVI10_DOORBELL_MEC_RING6
- AMDGPU_NAVI10_DOORBELL_MEC_RING7
- AMDGPU_NAVI10_DOORBELL_USERQUEUE_END
- AMDGPU_NAVI10_DOORBELL_USERQUEUE_START
- AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0
- AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1
- AMDGPU_NUM_OF_VMIDS
- AMDGPU_NUM_VMID
- AMDGPU_PAGEFLIP_IRQ_D1
- AMDGPU_PAGEFLIP_IRQ_D2
- AMDGPU_PAGEFLIP_IRQ_D3
- AMDGPU_PAGEFLIP_IRQ_D4
- AMDGPU_PAGEFLIP_IRQ_D5
- AMDGPU_PAGEFLIP_IRQ_D6
- AMDGPU_PAGEFLIP_IRQ_NONE
- AMDGPU_PASSTHROUGH_MODE
- AMDGPU_PCIE_DATA
- AMDGPU_PCIE_GEN1
- AMDGPU_PCIE_GEN2
- AMDGPU_PCIE_GEN3
- AMDGPU_PCIE_GEN_INVALID
- AMDGPU_PCIE_INDEX
- AMDGPU_PDE_BFS
- AMDGPU_PDE_PTE
- AMDGPU_PLL_IS_LCD
- AMDGPU_PLL_LEGACY
- AMDGPU_PLL_NO_ODD_POST_DIV
- AMDGPU_PLL_PREFER_CLOSEST_LOWER
- AMDGPU_PLL_PREFER_HIGH_FB_DIV
- AMDGPU_PLL_PREFER_HIGH_POST_DIV
- AMDGPU_PLL_PREFER_HIGH_REF_DIV
- AMDGPU_PLL_PREFER_LOW_FB_DIV
- AMDGPU_PLL_PREFER_LOW_POST_DIV
- AMDGPU_PLL_PREFER_LOW_REF_DIV
- AMDGPU_PLL_PREFER_MINM_OVER_MAXP
- AMDGPU_PLL_USE_BIOS_DIVS
- AMDGPU_PLL_USE_FRAC_FB_DIV
- AMDGPU_PLL_USE_POST_DIV
- AMDGPU_PLL_USE_REF_DIV
- AMDGPU_PL_FLAG_GDS
- AMDGPU_PL_FLAG_GWS
- AMDGPU_PL_FLAG_OA
- AMDGPU_PL_GDS
- AMDGPU_PL_GWS
- AMDGPU_PL_OA
- AMDGPU_PMU_ATTR
- AMDGPU_PM_DISPLAY_GAP_IGNORE
- AMDGPU_PM_DISPLAY_GAP_VBLANK
- AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM
- AMDGPU_PM_DISPLAY_GAP_WATERMARK
- AMDGPU_POISON
- AMDGPU_PP_SENSOR_EDGE_TEMP
- AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK
- AMDGPU_PP_SENSOR_GFX_MCLK
- AMDGPU_PP_SENSOR_GFX_SCLK
- AMDGPU_PP_SENSOR_GPU_LOAD
- AMDGPU_PP_SENSOR_GPU_POWER
- AMDGPU_PP_SENSOR_GPU_TEMP
- AMDGPU_PP_SENSOR_HOTSPOT_TEMP
- AMDGPU_PP_SENSOR_MAX_FAN_RPM
- AMDGPU_PP_SENSOR_MEM_LOAD
- AMDGPU_PP_SENSOR_MEM_TEMP
- AMDGPU_PP_SENSOR_MIN_FAN_RPM
- AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK
- AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK
- AMDGPU_PP_SENSOR_UVD_DCLK
- AMDGPU_PP_SENSOR_UVD_POWER
- AMDGPU_PP_SENSOR_UVD_VCLK
- AMDGPU_PP_SENSOR_VCE_ECCLK
- AMDGPU_PP_SENSOR_VCE_POWER
- AMDGPU_PP_SENSOR_VCN_POWER_STATE
- AMDGPU_PP_SENSOR_VDDGFX
- AMDGPU_PP_SENSOR_VDDNB
- AMDGPU_PREAMBLE_IB_PRESENT
- AMDGPU_PREAMBLE_IB_PRESENT_FIRST
- AMDGPU_PTE_DEFAULT_ATC
- AMDGPU_PTE_EXECUTABLE
- AMDGPU_PTE_FRAG
- AMDGPU_PTE_LOG
- AMDGPU_PTE_MTYPE_NV10
- AMDGPU_PTE_MTYPE_NV10_MASK
- AMDGPU_PTE_MTYPE_VG10
- AMDGPU_PTE_MTYPE_VG10_MASK
- AMDGPU_PTE_PRT
- AMDGPU_PTE_READABLE
- AMDGPU_PTE_SNOOPED
- AMDGPU_PTE_SYSTEM
- AMDGPU_PTE_TF
- AMDGPU_PTE_VALID
- AMDGPU_PTE_WRITEABLE
- AMDGPU_PX_QUIRK_FORCE_ATPX
- AMDGPU_RAS_BLOCK_COUNT
- AMDGPU_RAS_BLOCK_MASK
- AMDGPU_RAS_BLOCK__ATHUB
- AMDGPU_RAS_BLOCK__DF
- AMDGPU_RAS_BLOCK__FUSE
- AMDGPU_RAS_BLOCK__GFX
- AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH
- AMDGPU_RAS_BLOCK__GFX_CPC_UCODE
- AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1
- AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2
- AMDGPU_RAS_BLOCK__GFX_CPF_TAG
- AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ
- AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG
- AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_CPG_TAG
- AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1
- AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2
- AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1
- AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2
- AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1
- AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2
- AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM
- AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM
- AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM
- AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM
- AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM
- AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM
- AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM
- AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM
- AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM
- AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM
- AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM
- AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM
- AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM
- AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE
- AMDGPU_RAS_BLOCK__GFX_GDS_MEM
- AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM
- AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM
- AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM
- AMDGPU_RAS_BLOCK__GFX_MAX
- AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO
- AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO
- AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D
- AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I
- AMDGPU_RAS_BLOCK__GFX_SQ_SGPR
- AMDGPU_RAS_BLOCK__GFX_SQ_VGPR
- AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO
- AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO
- AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO
- AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO
- AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO
- AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1
- AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC
- AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER
- AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM
- AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG
- AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL
- AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA
- AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM
- AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ
- AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN
- AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN
- AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM
- AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM
- AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO
- AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM
- AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM
- AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0
- AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1
- AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO
- AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO
- AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END
- AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START
- AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI
- AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO
- AMDGPU_RAS_BLOCK__HDP
- AMDGPU_RAS_BLOCK__LAST
- AMDGPU_RAS_BLOCK__MMHUB
- AMDGPU_RAS_BLOCK__MP0
- AMDGPU_RAS_BLOCK__MP1
- AMDGPU_RAS_BLOCK__PCIE_BIF
- AMDGPU_RAS_BLOCK__SDMA
- AMDGPU_RAS_BLOCK__SEM
- AMDGPU_RAS_BLOCK__SMN
- AMDGPU_RAS_BLOCK__UMC
- AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK
- AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK
- AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE
- AMDGPU_RAS_BLOCK__UTC_VML2_WALKER
- AMDGPU_RAS_BLOCK__XGMI_WAFL
- AMDGPU_RAS_CE
- AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
- AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER
- AMDGPU_RAS_EEPROM_ERR_RECOVERABLE
- AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE
- AMDGPU_RAS_ERROR__NONE
- AMDGPU_RAS_ERROR__PARITY
- AMDGPU_RAS_ERROR__POISON
- AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE
- AMDGPU_RAS_FAIL
- AMDGPU_RAS_FLAG_INIT_BY_VBIOS
- AMDGPU_RAS_FLAG_INIT_NEED_RESET
- AMDGPU_RAS_PT
- AMDGPU_RAS_SUB_BLOCK
- AMDGPU_RAS_SUCCESS
- AMDGPU_RAS_UE
- AMDGPU_REGS_IDX
- AMDGPU_REGS_NO_KIQ
- AMDGPU_RESET_COMPUTE
- AMDGPU_RESET_CP
- AMDGPU_RESET_DISPLAY
- AMDGPU_RESET_DMA
- AMDGPU_RESET_DMA1
- AMDGPU_RESET_GFX
- AMDGPU_RESET_GRBM
- AMDGPU_RESET_IH
- AMDGPU_RESET_MAGIC_NUM
- AMDGPU_RESET_MC
- AMDGPU_RESET_RLC
- AMDGPU_RESET_SEM
- AMDGPU_RESET_UVD
- AMDGPU_RESET_VCE
- AMDGPU_RESET_VCE1
- AMDGPU_RESET_VMC
- AMDGPU_RESUME_MS
- AMDGPU_RING_TYPE_COMPUTE
- AMDGPU_RING_TYPE_GFX
- AMDGPU_RING_TYPE_KIQ
- AMDGPU_RING_TYPE_SDMA
- AMDGPU_RING_TYPE_UVD
- AMDGPU_RING_TYPE_UVD_ENC
- AMDGPU_RING_TYPE_VCE
- AMDGPU_RING_TYPE_VCN_DEC
- AMDGPU_RING_TYPE_VCN_ENC
- AMDGPU_RING_TYPE_VCN_JPEG
- AMDGPU_SA_NUM_FENCE_LISTS
- AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE
- AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE
- AMDGPU_SCLK_DOWN
- AMDGPU_SCLK_UP
- AMDGPU_SDMA0_UCODE_LOADED
- AMDGPU_SDMA1_UCODE_LOADED
- AMDGPU_SDMA_IRQ_INSTANCE0
- AMDGPU_SDMA_IRQ_INSTANCE1
- AMDGPU_SDMA_IRQ_INSTANCE2
- AMDGPU_SDMA_IRQ_INSTANCE3
- AMDGPU_SDMA_IRQ_INSTANCE4
- AMDGPU_SDMA_IRQ_INSTANCE5
- AMDGPU_SDMA_IRQ_INSTANCE6
- AMDGPU_SDMA_IRQ_INSTANCE7
- AMDGPU_SDMA_IRQ_LAST
- AMDGPU_SG_THRESHOLD
- AMDGPU_SRIOV_CAPS_ENABLE_IOV
- AMDGPU_SRIOV_CAPS_IS_VF
- AMDGPU_SRIOV_CAPS_RUNTIME
- AMDGPU_SRIOV_CAPS_SRIOV_VBIOS
- AMDGPU_TD_AUTO
- AMDGPU_TD_DOWN
- AMDGPU_TD_UP
- AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
- AMDGPU_THERMAL_IRQ_LAST
- AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
- AMDGPU_TILING_ARRAY_MODE_MASK
- AMDGPU_TILING_ARRAY_MODE_SHIFT
- AMDGPU_TILING_BANK_HEIGHT_MASK
- AMDGPU_TILING_BANK_HEIGHT_SHIFT
- AMDGPU_TILING_BANK_WIDTH_MASK
- AMDGPU_TILING_BANK_WIDTH_SHIFT
- AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK
- AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT
- AMDGPU_TILING_DCC_OFFSET_256B_MASK
- AMDGPU_TILING_DCC_OFFSET_256B_SHIFT
- AMDGPU_TILING_DCC_PITCH_MAX_MASK
- AMDGPU_TILING_DCC_PITCH_MAX_SHIFT
- AMDGPU_TILING_GET
- AMDGPU_TILING_MACRO_TILE_ASPECT_MASK
- AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT
- AMDGPU_TILING_MICRO_TILE_MODE_MASK
- AMDGPU_TILING_MICRO_TILE_MODE_SHIFT
- AMDGPU_TILING_NUM_BANKS_MASK
- AMDGPU_TILING_NUM_BANKS_SHIFT
- AMDGPU_TILING_PIPE_CONFIG_MASK
- AMDGPU_TILING_PIPE_CONFIG_SHIFT
- AMDGPU_TILING_SET
- AMDGPU_TILING_SWIZZLE_MODE_MASK
- AMDGPU_TILING_SWIZZLE_MODE_SHIFT
- AMDGPU_TILING_TILE_SPLIT_MASK
- AMDGPU_TILING_TILE_SPLIT_SHIFT
- AMDGPU_UCODE_ID
- AMDGPU_UCODE_ID_CP_CE
- AMDGPU_UCODE_ID_CP_ME
- AMDGPU_UCODE_ID_CP_MEC1
- AMDGPU_UCODE_ID_CP_MEC1_JT
- AMDGPU_UCODE_ID_CP_MEC2
- AMDGPU_UCODE_ID_CP_MEC2_JT
- AMDGPU_UCODE_ID_CP_MES
- AMDGPU_UCODE_ID_CP_MES_DATA
- AMDGPU_UCODE_ID_CP_PFP
- AMDGPU_UCODE_ID_DMCU_ERAM
- AMDGPU_UCODE_ID_DMCU_INTV
- AMDGPU_UCODE_ID_MAXIMUM
- AMDGPU_UCODE_ID_RLC_G
- AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
- AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
- AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
- AMDGPU_UCODE_ID_SDMA0
- AMDGPU_UCODE_ID_SDMA1
- AMDGPU_UCODE_ID_SDMA2
- AMDGPU_UCODE_ID_SDMA3
- AMDGPU_UCODE_ID_SDMA4
- AMDGPU_UCODE_ID_SDMA5
- AMDGPU_UCODE_ID_SDMA6
- AMDGPU_UCODE_ID_SDMA7
- AMDGPU_UCODE_ID_SMC
- AMDGPU_UCODE_ID_STORAGE
- AMDGPU_UCODE_ID_UVD
- AMDGPU_UCODE_ID_UVD1
- AMDGPU_UCODE_ID_VCE
- AMDGPU_UCODE_ID_VCN
- AMDGPU_UCODE_ID_VCN0_RAM
- AMDGPU_UCODE_ID_VCN1
- AMDGPU_UCODE_ID_VCN1_RAM
- AMDGPU_UCODE_STATUS
- AMDGPU_UCODE_STATUS_INVALID
- AMDGPU_UCODE_STATUS_LOADED
- AMDGPU_UCODE_STATUS_NOT_LOADED
- AMDGPU_USERPTR_RESTORE_DELAY_MS
- AMDGPU_UVD_FIRMWARE_OFFSET
- AMDGPU_UVD_FIRMWARE_SIZE
- AMDGPU_UVD_HARVEST_UVD0
- AMDGPU_UVD_HARVEST_UVD1
- AMDGPU_UVD_HEAP_SIZE
- AMDGPU_UVD_SESSION_SIZE
- AMDGPU_UVD_STACK_SIZE
- AMDGPU_UVD_STATUS_BUSY_MASK
- AMDGPU_VA_OP_CLEAR
- AMDGPU_VA_OP_MAP
- AMDGPU_VA_OP_REPLACE
- AMDGPU_VA_OP_UNMAP
- AMDGPU_VA_RESERVED_SIZE
- AMDGPU_VCE_CLOCK_TABLE_ENTRIES
- AMDGPU_VCE_FIRMWARE_OFFSET
- AMDGPU_VCE_FW_53_45
- AMDGPU_VCE_HARVEST_VCE0
- AMDGPU_VCE_HARVEST_VCE1
- AMDGPU_VCE_STATUS_BUSY_MASK
- AMDGPU_VCN_CONTEXT_SIZE
- AMDGPU_VCN_FIRMWARE_OFFSET
- AMDGPU_VCN_HARVEST_VCN0
- AMDGPU_VCN_HARVEST_VCN1
- AMDGPU_VCN_MAX_ENC_RINGS
- AMDGPU_VCN_STACK_SIZE
- AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP
- AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP
- AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1
- AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3
- AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5
- AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7
- AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1
- AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3
- AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5
- AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7
- AMDGPU_VEGA20_DOORBELL64_VCN0_1
- AMDGPU_VEGA20_DOORBELL64_VCN2_3
- AMDGPU_VEGA20_DOORBELL64_VCN4_5
- AMDGPU_VEGA20_DOORBELL64_VCN6_7
- AMDGPU_VEGA20_DOORBELL64_VCN8_9
- AMDGPU_VEGA20_DOORBELL64_VCNa_b
- AMDGPU_VEGA20_DOORBELL64_VCNc_d
- AMDGPU_VEGA20_DOORBELL64_VCNe_f
- AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
- AMDGPU_VEGA20_DOORBELL_DIQ
- AMDGPU_VEGA20_DOORBELL_GFX_RING0
- AMDGPU_VEGA20_DOORBELL_HIQ
- AMDGPU_VEGA20_DOORBELL_IH
- AMDGPU_VEGA20_DOORBELL_INVALID
- AMDGPU_VEGA20_DOORBELL_KIQ
- AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT
- AMDGPU_VEGA20_DOORBELL_MEC_RING0
- AMDGPU_VEGA20_DOORBELL_MEC_RING1
- AMDGPU_VEGA20_DOORBELL_MEC_RING2
- AMDGPU_VEGA20_DOORBELL_MEC_RING3
- AMDGPU_VEGA20_DOORBELL_MEC_RING4
- AMDGPU_VEGA20_DOORBELL_MEC_RING5
- AMDGPU_VEGA20_DOORBELL_MEC_RING6
- AMDGPU_VEGA20_DOORBELL_MEC_RING7
- AMDGPU_VEGA20_DOORBELL_USERQUEUE_END
- AMDGPU_VEGA20_DOORBELL_USERQUEUE_START
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6
- AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7
- AMDGPU_VF_ERROR_ENTRY_SIZE
- AMDGPU_VIRT_H
- AMDGPU_VIRT_SUPPORT_RLC_PRG_REG
- AMDGPU_VM_CONTEXT_COMPUTE
- AMDGPU_VM_CONTEXT_GFX
- AMDGPU_VM_DELAY_UPDATE
- AMDGPU_VM_FAULT_STOP_ALWAYS
- AMDGPU_VM_FAULT_STOP_FIRST
- AMDGPU_VM_FAULT_STOP_NEVER
- AMDGPU_VM_MAX_NUM_CTX
- AMDGPU_VM_MAX_RESERVED_VMID
- AMDGPU_VM_MAX_UPDATE_SIZE
- AMDGPU_VM_MTYPE_CC
- AMDGPU_VM_MTYPE_DEFAULT
- AMDGPU_VM_MTYPE_MASK
- AMDGPU_VM_MTYPE_NC
- AMDGPU_VM_MTYPE_UC
- AMDGPU_VM_MTYPE_WC
- AMDGPU_VM_OP_RESERVE_VMID
- AMDGPU_VM_OP_UNRESERVE_VMID
- AMDGPU_VM_PAGE_EXECUTABLE
- AMDGPU_VM_PAGE_PRT
- AMDGPU_VM_PAGE_READABLE
- AMDGPU_VM_PAGE_WRITEABLE
- AMDGPU_VM_PDB0
- AMDGPU_VM_PDB1
- AMDGPU_VM_PDB2
- AMDGPU_VM_PTB
- AMDGPU_VM_PTE_COUNT
- AMDGPU_VM_SDMA_MAX_NUM_DW
- AMDGPU_VM_SDMA_MIN_NUM_DW
- AMDGPU_VM_USE_CPU_FOR_COMPUTE
- AMDGPU_VM_USE_CPU_FOR_GFX
- AMDGPU_VRAM_TYPE_DDR2
- AMDGPU_VRAM_TYPE_DDR3
- AMDGPU_VRAM_TYPE_DDR4
- AMDGPU_VRAM_TYPE_GDDR1
- AMDGPU_VRAM_TYPE_GDDR3
- AMDGPU_VRAM_TYPE_GDDR4
- AMDGPU_VRAM_TYPE_GDDR5
- AMDGPU_VRAM_TYPE_GDDR6
- AMDGPU_VRAM_TYPE_HBM
- AMDGPU_VRAM_TYPE_UNKNOWN
- AMDGPU_WAIT_IDLE_TIMEOUT
- AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS
- AMDGPU_XGMI_MAX_CONNECTED_NODES
- AMDGPU_XGMI_SET_FICAA
- AMDKFD_COMMAND_END
- AMDKFD_COMMAND_START
- AMDKFD_CORE_IOCTL_COUNT
- AMDKFD_IO
- AMDKFD_IOCTL_BASE
- AMDKFD_IOCTL_DEF
- AMDKFD_IOC_ACQUIRE_VM
- AMDKFD_IOC_ALLOC_MEMORY_OF_GPU
- AMDKFD_IOC_CREATE_EVENT
- AMDKFD_IOC_CREATE_QUEUE
- AMDKFD_IOC_DBG_ADDRESS_WATCH
- AMDKFD_IOC_DBG_REGISTER
- AMDKFD_IOC_DBG_UNREGISTER
- AMDKFD_IOC_DBG_WAVE_CONTROL
- AMDKFD_IOC_DESTROY_EVENT
- AMDKFD_IOC_DESTROY_QUEUE
- AMDKFD_IOC_FREE_MEMORY_OF_GPU
- AMDKFD_IOC_GET_CLOCK_COUNTERS
- AMDKFD_IOC_GET_DMABUF_INFO
- AMDKFD_IOC_GET_PROCESS_APERTURES
- AMDKFD_IOC_GET_PROCESS_APERTURES_NEW
- AMDKFD_IOC_GET_QUEUE_WAVE_STATE
- AMDKFD_IOC_GET_TILE_CONFIG
- AMDKFD_IOC_GET_VERSION
- AMDKFD_IOC_IMPORT_DMABUF
- AMDKFD_IOC_MAP_MEMORY_TO_GPU
- AMDKFD_IOC_RESET_EVENT
- AMDKFD_IOC_SET_CU_MASK
- AMDKFD_IOC_SET_EVENT
- AMDKFD_IOC_SET_MEMORY_POLICY
- AMDKFD_IOC_SET_SCRATCH_BACKING_VA
- AMDKFD_IOC_SET_TRAP_HANDLER
- AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU
- AMDKFD_IOC_UPDATE_QUEUE
- AMDKFD_IOC_WAIT_EVENTS
- AMDKFD_IOR
- AMDKFD_IOW
- AMDKFD_IOWR
- AMDPLC
- AMDTP_FDF_AM824
- AMDTP_FDF_NO_DATA
- AMDTP_FMT_TSCM_RX
- AMDTP_FMT_TSCM_TX
- AMDTP_IN_STREAM
- AMDTP_OUT_STREAM
- AMD_141b_MMIO_BASE
- AMD_141b_MMIO_BASE_MMIOBASE_MASK
- AMD_141b_MMIO_BASE_RE_MASK
- AMD_141b_MMIO_BASE_WE_MASK
- AMD_141b_MMIO_HIGH
- AMD_141b_MMIO_HIGH_MMIOBASE_MASK
- AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK
- AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT
- AMD_141b_MMIO_LIMIT
- AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK
- AMD_8111_PCI_IRQ_ROUTING
- AMD_813X_MISC
- AMD_813X_NOIOAMODE
- AMD_813X_REV_B1
- AMD_813X_REV_B2
- AMD_8BIT_TIMING
- AMD_ACPI_DESCRIPTION_HEADER
- AMD_ACPI_H
- AMD_ADDBITS
- AMD_ADDRESS_SETUP
- AMD_APSIZE
- AMD_ASIC_MASK
- AMD_ATTBASE
- AMD_ATTRIBUTE
- AMD_AUTO_TUNE_SEL
- AMD_BAR1LMT_OFFSET
- AMD_BAR1XLAT_OFFSET
- AMD_BAR23LMT_OFFSET
- AMD_BAR23XLAT_OFFSET
- AMD_BAR45LMT_OFFSET
- AMD_BAR45XLAT_OFFSET
- AMD_BIT
- AMD_BIT_MASK
- AMD_BOOTLOC_BUG
- AMD_BUSWIDTH
- AMD_C2P_MSG0
- AMD_C2P_MSG1
- AMD_C2P_MSG2
- AMD_C2P_MSG3
- AMD_C2P_MSG4
- AMD_C2P_MSG5
- AMD_C2P_MSG6
- AMD_C2P_MSG7
- AMD_C2P_MSG8
- AMD_C2P_MSG9
- AMD_CABLE_DETECT
- AMD_CACHEENTRY
- AMD_CG_STATE_GATE
- AMD_CG_STATE_UNGATE
- AMD_CG_SUPPORT_ATHUB_LS
- AMD_CG_SUPPORT_ATHUB_MGCG
- AMD_CG_SUPPORT_BIF_LS
- AMD_CG_SUPPORT_BIF_MGCG
- AMD_CG_SUPPORT_DF_MGCG
- AMD_CG_SUPPORT_DRM_LS
- AMD_CG_SUPPORT_DRM_MGCG
- AMD_CG_SUPPORT_GFX_3D_CGCG
- AMD_CG_SUPPORT_GFX_3D_CGLS
- AMD_CG_SUPPORT_GFX_CGCG
- AMD_CG_SUPPORT_GFX_CGLS
- AMD_CG_SUPPORT_GFX_CGTS
- AMD_CG_SUPPORT_GFX_CGTS_LS
- AMD_CG_SUPPORT_GFX_CP_LS
- AMD_CG_SUPPORT_GFX_MGCG
- AMD_CG_SUPPORT_GFX_MGLS
- AMD_CG_SUPPORT_GFX_RLC_LS
- AMD_CG_SUPPORT_HDP_DS
- AMD_CG_SUPPORT_HDP_LS
- AMD_CG_SUPPORT_HDP_MGCG
- AMD_CG_SUPPORT_HDP_SD
- AMD_CG_SUPPORT_IH_CG
- AMD_CG_SUPPORT_MC_LS
- AMD_CG_SUPPORT_MC_MGCG
- AMD_CG_SUPPORT_ROM_MGCG
- AMD_CG_SUPPORT_SDMA_LS
- AMD_CG_SUPPORT_SDMA_MGCG
- AMD_CG_SUPPORT_UVD_MGCG
- AMD_CG_SUPPORT_VCE_MGCG
- AMD_CG_SUPPORT_VCN_MGCG
- AMD_CHIPSET_BEFORE_ML
- AMD_CHIPSET_BOLTON
- AMD_CHIPSET_CZ
- AMD_CHIPSET_HUDSON2
- AMD_CHIPSET_NL
- AMD_CHIPSET_SB600
- AMD_CHIPSET_SB700
- AMD_CHIPSET_SB800
- AMD_CHIPSET_TAISHAN
- AMD_CHIPSET_UNKNOWN
- AMD_CHIPSET_YANGTZE
- AMD_CLEAR_BIT
- AMD_CNTL_OFFSET
- AMD_CONFIG_REG_BASE
- AMD_CONFIG_REG_END
- AMD_CONFIG_REG_SIZE
- AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
- AMD_DBFM_OFFSET
- AMD_DBMASK_OFFSET
- AMD_DBREQ_OFFSET
- AMD_DBSTAT_OFFSET
- AMD_DB_CNT
- AMD_DPM_FORCED_LEVEL_AUTO
- AMD_DPM_FORCED_LEVEL_HIGH
- AMD_DPM_FORCED_LEVEL_LOW
- AMD_DPM_FORCED_LEVEL_MANUAL
- AMD_DPM_FORCED_LEVEL_PROFILE_EXIT
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK
- AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK
- AMD_DPM_FORCED_LEVEL_PROFILE_PEAK
- AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD
- AMD_DRIVE_TIMING
- AMD_EC_CMD
- AMD_EC_CMD_BD
- AMD_EC_CMD_BE
- AMD_EC_CMD_QR
- AMD_EC_CMD_RD
- AMD_EC_CMD_WR
- AMD_EC_DATA
- AMD_EC_ICR
- AMD_EC_SC
- AMD_EC_SC_BURST
- AMD_EC_SC_CMD
- AMD_EC_SC_IBF
- AMD_EC_SC_OBF
- AMD_EC_SC_SCI
- AMD_EC_SC_SMI
- AMD_EVENT_CU
- AMD_EVENT_DC
- AMD_EVENT_DE
- AMD_EVENT_EX_LS
- AMD_EVENT_FP
- AMD_EVENT_IC_DE
- AMD_EVENT_INTMASK
- AMD_EVENT_LS
- AMD_EVENT_NB
- AMD_EVENT_TYPE_MASK
- AMD_EXP_HW_SUPPORT
- AMD_FAM14H_STATE_NUM
- AMD_FAN_CTRL_AUTO
- AMD_FAN_CTRL_MANUAL
- AMD_FAN_CTRL_NONE
- AMD_FCH_GPIO_BANK0_BASE
- AMD_FCH_GPIO_DRIVER_NAME
- AMD_FCH_GPIO_FLAG_DIRECTION
- AMD_FCH_GPIO_FLAG_READ
- AMD_FCH_GPIO_FLAG_WRITE
- AMD_FCH_GPIO_REG_GPIO32_GE1
- AMD_FCH_GPIO_REG_GPIO33_GE2
- AMD_FCH_GPIO_REG_GPIO49
- AMD_FCH_GPIO_REG_GPIO50
- AMD_FCH_GPIO_REG_GPIO51
- AMD_FCH_GPIO_REG_GPIO57
- AMD_FCH_GPIO_REG_GPIO58
- AMD_FCH_GPIO_REG_GPIO59_DEVSLP0
- AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
- AMD_FCH_GPIO_REG_GPIO64
- AMD_FCH_GPIO_REG_GPIO66_SPKR
- AMD_FCH_GPIO_REG_GPIO68
- AMD_FCH_GPIO_REG_GPIO71
- AMD_FCH_GPIO_SIZE
- AMD_FCH_MMIO_BASE
- AMD_FIFO_PTR
- AMD_FIFO_SIZE
- AMD_FLAGS_MASK
- AMD_FLUSHTRIG_OFFSET
- AMD_FORMAT_ATTR
- AMD_GARTENABLE
- AMD_GETBITS
- AMD_GPIO_DEBOUNCE
- AMD_GPIO_LTCH_STS
- AMD_GPIO_MODE_ALTFN
- AMD_GPIO_MODE_IN
- AMD_GPIO_MODE_MASK
- AMD_GPIO_MODE_OUT
- AMD_GPIO_PINS_BANK0
- AMD_GPIO_PINS_BANK1
- AMD_GPIO_PINS_BANK2
- AMD_GPIO_PINS_BANK3
- AMD_GPIO_PINS_PER_BANK
- AMD_GPIO_RTIN
- AMD_GPIO_X_IN_ACTIVEHI
- AMD_GPIO_X_IN_LATCH
- AMD_GPIO_X_MASK
- AMD_GPIO_X_OUT_CLK0
- AMD_GPIO_X_OUT_CLK1
- AMD_GPIO_X_OUT_HI
- AMD_GPIO_X_OUT_LOW
- AMD_I2C_TIMEOUT
- AMD_IDE_CONFIG
- AMD_INIT_SETBITS
- AMD_INTMASK_OFFSET
- AMD_INTSTAT_OFFSET
- AMD_IOMMU_DEVICE_FLAG_ATS_SUP
- AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
- AMD_IOMMU_DEVICE_FLAG_PASID_SUP
- AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
- AMD_IOMMU_DEVICE_FLAG_PRI_SUP
- AMD_IOMMU_EVENT_DESC
- AMD_IOMMU_FLAG_TRANS_PRE_ENABLED
- AMD_IOMMU_GUEST_IR_GA
- AMD_IOMMU_GUEST_IR_LEGACY
- AMD_IOMMU_GUEST_IR_LEGACY_GA
- AMD_IOMMU_GUEST_IR_VAPIC
- AMD_IOMMU_H
- AMD_IOMMU_INT_MASK
- AMD_IOMMU_INV_PRI_RSP_FAIL
- AMD_IOMMU_INV_PRI_RSP_INVALID
- AMD_IOMMU_INV_PRI_RSP_SUCCESS
- AMD_IOMMU_PGSIZES
- AMD_IP_BLOCK_TYPE_ACP
- AMD_IP_BLOCK_TYPE_COMMON
- AMD_IP_BLOCK_TYPE_DCE
- AMD_IP_BLOCK_TYPE_GFX
- AMD_IP_BLOCK_TYPE_GMC
- AMD_IP_BLOCK_TYPE_IH
- AMD_IP_BLOCK_TYPE_MES
- AMD_IP_BLOCK_TYPE_PSP
- AMD_IP_BLOCK_TYPE_SDMA
- AMD_IP_BLOCK_TYPE_SMC
- AMD_IP_BLOCK_TYPE_UVD
- AMD_IP_BLOCK_TYPE_VCE
- AMD_IP_BLOCK_TYPE_VCN
- AMD_IS_APU
- AMD_IS_MOBILITY
- AMD_IS_PX
- AMD_IS_VALID_VBIOS
- AMD_K7_NUM_IORR
- AMD_LEGACY_ERRATUM
- AMD_LINK_DOWN_EVENT
- AMD_LINK_HB_TIMEOUT
- AMD_LINK_STATUS_OFFSET
- AMD_LINK_UP_EVENT
- AMD_LTRLATENCY_OFFSET
- AMD_MAX_TUNE_VALUE
- AMD_MAX_USEC_TIMEOUT
- AMD_MAX_VCE_LEVELS
- AMD_MIRRDBSTAT_OFFSET
- AMD_MMBASE_BAR
- AMD_MMDATA_OFFSET
- AMD_MMINDEX_OFFSET
- AMD_MODECNTL
- AMD_MODECNTL2
- AMD_MODEL_RANGE
- AMD_MODEL_RANGE_END
- AMD_MODEL_RANGE_FAMILY
- AMD_MODEL_RANGE_START
- AMD_MP2_I2C_MAX_RW_LENGTH
- AMD_MSIX_VECTOR_CNT
- AMD_MSLEEP_DURATION
- AMD_MSR_RANGE
- AMD_NB_F0_NODE_ID
- AMD_NB_F0_UNIT_ID
- AMD_NB_F1_CONFIG_MAP_RANGES
- AMD_NB_F1_CONFIG_MAP_REG
- AMD_NB_GART
- AMD_NB_L3_INDEX_DISABLE
- AMD_NB_L3_PARTITIONING
- AMD_OSVW_ERRATUM
- AMD_P2C_MSG0
- AMD_P2C_MSG1
- AMD_P2C_MSG2
- AMD_P2C_MSG3
- AMD_P2C_MSG_INTEN
- AMD_P2C_MSG_INTSTS
- AMD_PCI_MISC
- AMD_PCI_MISC_INT
- AMD_PCI_MISC_SCI
- AMD_PCI_MISC_SPEEDUP
- AMD_PEER_D0_EVENT
- AMD_PEER_D3_EVENT
- AMD_PEER_FLUSH_EVENT
- AMD_PEER_OFFSET
- AMD_PEER_PMETO_EVENT
- AMD_PEER_RESET_EVENT
- AMD_PGSLV_OFFSET
- AMD_PG_STATE_GATE
- AMD_PG_STATE_UNGATE
- AMD_PG_SUPPORT_ACP
- AMD_PG_SUPPORT_ATHUB
- AMD_PG_SUPPORT_CP
- AMD_PG_SUPPORT_GDS
- AMD_PG_SUPPORT_GFX_DMG
- AMD_PG_SUPPORT_GFX_PG
- AMD_PG_SUPPORT_GFX_PIPELINE
- AMD_PG_SUPPORT_GFX_QUICK_MG
- AMD_PG_SUPPORT_GFX_SMG
- AMD_PG_SUPPORT_MMHUB
- AMD_PG_SUPPORT_RLC_SMU_HS
- AMD_PG_SUPPORT_SAMU
- AMD_PG_SUPPORT_SDMA
- AMD_PG_SUPPORT_UVD
- AMD_PG_SUPPORT_VCE
- AMD_PG_SUPPORT_VCN
- AMD_PG_SUPPORT_VCN_DPG
- AMD_PMESTAT_OFFSET
- AMD_PMSGTRIG_OFFSET
- AMD_POMBARXLAT_OFFSET
- AMD_POWER_EVENTSEL_PKG
- AMD_POWER_EVENT_MASK
- AMD_PP_DisplayConfigType_DP162
- AMD_PP_DisplayConfigType_DP216
- AMD_PP_DisplayConfigType_DP243
- AMD_PP_DisplayConfigType_DP27
- AMD_PP_DisplayConfigType_DP324
- AMD_PP_DisplayConfigType_DP432
- AMD_PP_DisplayConfigType_DP54
- AMD_PP_DisplayConfigType_DVI
- AMD_PP_DisplayConfigType_HDMI162
- AMD_PP_DisplayConfigType_HDMI297
- AMD_PP_DisplayConfigType_HDMI6G
- AMD_PP_DisplayConfigType_LVDS
- AMD_PP_DisplayConfigType_None
- AMD_PP_DisplayConfigType_VGA
- AMD_PP_DisplayConfigType_WIRELESS
- AMD_PP_TASK_COMPLETE_INIT
- AMD_PP_TASK_DISPLAY_CONFIG_CHANGE
- AMD_PP_TASK_ENABLE_USER_STATE
- AMD_PP_TASK_MAX
- AMD_PP_TASK_READJUST_POWER_STATE
- AMD_PRI_DEV_ERRATUM_ENABLE_RESET
- AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
- AMD_PSION_OFFSET
- AMD_REG_GPIO
- AMD_RESET_METHOD_BACO
- AMD_RESET_METHOD_LEGACY
- AMD_RESET_METHOD_MODE0
- AMD_RESET_METHOD_MODE1
- AMD_RESET_METHOD_MODE2
- AMD_ROMBARLMT_OFFSET
- AMD_RSMU_HCID
- AMD_RSMU_SIID
- AMD_RSPNUM_OFFSET
- AMD_SD_AUTO_PATTERN
- AMD_SD_MISC_CONTROL
- AMD_SEV_BIT
- AMD_SIDEINFO_OFFSET
- AMD_SIDE_MASK
- AMD_SIDE_READY
- AMD_SINRST_OFFSET
- AMD_SMB_ADDR
- AMD_SMB_ALRM_A
- AMD_SMB_ALRM_D
- AMD_SMB_BCNT
- AMD_SMB_CMD
- AMD_SMB_DATA
- AMD_SMB_PRTCL
- AMD_SMB_PRTCL_BLOCK_DATA
- AMD_SMB_PRTCL_BLOCK_PROC_CALL
- AMD_SMB_PRTCL_BYTE
- AMD_SMB_PRTCL_BYTE_DATA
- AMD_SMB_PRTCL_I2C_BLOCK_DATA
- AMD_SMB_PRTCL_PEC
- AMD_SMB_PRTCL_PROC_CALL
- AMD_SMB_PRTCL_QUICK
- AMD_SMB_PRTCL_READ
- AMD_SMB_PRTCL_WORD_DATA
- AMD_SMB_PRTCL_WRITE
- AMD_SMB_STATUS_ACC_DENY
- AMD_SMB_STATUS_BUSY
- AMD_SMB_STATUS_CMD_DENY
- AMD_SMB_STATUS_DERR
- AMD_SMB_STATUS_DNAK
- AMD_SMB_STATUS_FAIL
- AMD_SMB_STATUS_NOTSUP
- AMD_SMB_STATUS_OK
- AMD_SMB_STATUS_PEC
- AMD_SMB_STATUS_TIMEOUT
- AMD_SMB_STATUS_UNKNOWN
- AMD_SMB_STS
- AMD_SMB_STS_ALRM
- AMD_SMB_STS_DONE
- AMD_SMB_STS_RES
- AMD_SMB_STS_STATUS
- AMD_SME_BIT
- AMD_SMUACK_OFFSET
- AMD_SMU_SPADMUTEX
- AMD_SMU_SPADOFFSET
- AMD_SPADS_CNT
- AMD_SPAD_MUX_OFFSET
- AMD_SPAD_OFFSET
- AMD_SSION_OFFSET
- AMD_STA_OFFSET
- AMD_THERMAL_IRQ_HIGH_TO_LOW
- AMD_THERMAL_IRQ_LAST
- AMD_THERMAL_IRQ_LOW_TO_HIGH
- AMD_TLBFLUSH
- AMD_UDMA_TIMING
- AMD_UNMASK_BIT
- AMD_VBIOS_LENGTH
- AMD_VBIOS_SIGNATURE
- AMD_VBIOS_SIGNATURE_END
- AMD_VBIOS_SIGNATURE_OFFSET
- AMD_VBIOS_SIGNATURE_SIZE
- AMD_VCE_LEVEL_AC_ALL
- AMD_VCE_LEVEL_DC_EE
- AMD_VCE_LEVEL_DC_GP_HIGH
- AMD_VCE_LEVEL_DC_GP_LOW
- AMD_VCE_LEVEL_DC_LL_HIGH
- AMD_VCE_LEVEL_DC_LL_LOW
- AMD_VENDOR_ID
- AMD_VSA_SIG
- AMD_WINDOW_MAXSIZE
- AMEMTYPE
- AMEMTYPE_MASK
- AMEMTYPE_SHIFT
- AMEM_CLK_CFG
- AMEM_CLK_ENB
- AMF
- AMG88XX
- AMG88XX_FPSC_1FPS
- AMG88XX_PCTL_NORMAL
- AMG88XX_PCTL_SLEEP
- AMG88XX_REG_FPSC
- AMG88XX_REG_PCTL
- AMG88XX_REG_RST
- AMG88XX_REG_T01L
- AMG88XX_REG_TTHL
- AMG88XX_RST_FLAG
- AMG88XX_RST_INIT
- AMH
- AMI305_OFFSET_X
- AMI305_OFFSET_Y
- AMI305_OFFSET_Z
- AMI305_SN
- AMI305_TEMP
- AMI305_VER
- AMI306_CTRL4
- AMI306_FINEOUTPUT_X
- AMI306_FINEOUTPUT_Y
- AMI306_FINEOUTPUT_Z
- AMI306_GAIN_PARA_XY
- AMI306_GAIN_PARA_XZ
- AMI306_GAIN_PARA_YX
- AMI306_GAIN_PARA_YZ
- AMI306_GAIN_PARA_ZX
- AMI306_GAIN_PARA_ZY
- AMI306_OFFZERO_X
- AMI306_OFFZERO_Y
- AMI306_OFFZERO_Z
- AMI306_SENS_X
- AMI306_SENS_Y
- AMI306_SENS_Z
- AMIC_IDX_1A
- AMIC_IDX_1B
- AMIC_IDX_2
- AMIC_MICBIAS_UNKNOWN
- AMIC_MICBIAS_VAMIC1
- AMIC_MICBIAS_VAMIC2
- AMIC_TYPE_DIFFERENTIAL
- AMIC_TYPE_SINGLE_ENDED
- AMID
- AMID_MASK
- AMID_SHIFT
- AMIGAFFS_H
- AMIGAHW_ANNOUNCE
- AMIGAHW_DECLARE
- AMIGAHW_PRESENT
- AMIGAHW_SET
- AMIGA_BOOTI_VERSION
- AMIR0
- AMIR1
- AMIR2
- AMIXER
- AMIXER_LINEIN
- AMIXER_LINEIN_C
- AMIXER_MASTER_C
- AMIXER_MASTER_F
- AMIXER_MASTER_F_C
- AMIXER_MASTER_R
- AMIXER_MASTER_S
- AMIXER_MIC
- AMIXER_MIC_C
- AMIXER_PCM_C
- AMIXER_PCM_F
- AMIXER_PCM_F_C
- AMIXER_PCM_R
- AMIXER_PCM_S
- AMIXER_RESOURCE_NUM
- AMIXER_SPDIFI
- AMIXER_SPDIFI_C
- AMIXER_SPDIFO
- AMIXER_WAVE_C
- AMIXER_WAVE_F
- AMIXER_WAVE_R
- AMIXER_WAVE_S
- AMIXER_Y_IMMEDIATE
- AMI_1000
- AMI_1200
- AMI_2000
- AMI_2500
- AMI_3000
- AMI_3000PLUS
- AMI_3000T
- AMI_4000
- AMI_4000T
- AMI_500
- AMI_500PLUS
- AMI_600
- AMI_AUDIO_14
- AMI_AUDIO_8
- AMI_AUDIO_OFF
- AMI_CD32
- AMI_CDTV
- AMI_CT_ALAW
- AMI_CT_S16BE
- AMI_CT_S16LE
- AMI_CT_U16BE
- AMI_CT_U16LE
- AMI_CT_U8
- AMI_CT_ULAW
- AMI_DRACO
- AMI_IRQS
- AMI_MASK
- AMI_PLAY_LOADED
- AMI_PLAY_MASK
- AMI_PLAY_PLAYING
- AMI_STD_IRQS
- AMI_UNKNOWN
- AMKSTR
- AML
- AMLCOMMENT_INLINE
- AML_ACCESS_ATTRIBUTE
- AML_ACCESS_TYPE
- AML_ACQUIRE_OP
- AML_ADD_OP
- AML_ALIAS_OP
- AML_ARG0
- AML_ARG1
- AML_ARG2
- AML_ARG3
- AML_ARG4
- AML_ARG5
- AML_ARG6
- AML_BANK_FIELD_OP
- AML_BIT_AND_OP
- AML_BIT_NAND_OP
- AML_BIT_NOR_OP
- AML_BIT_NOT_OP
- AML_BIT_OR_OP
- AML_BIT_XOR_OP
- AML_BREAKPOINT_OP
- AML_BREAK_OP
- AML_BUFFER_OP
- AML_BYTE_OP
- AML_CLASS_ARGUMENT
- AML_CLASS_ASCII
- AML_CLASS_CONTROL
- AML_CLASS_CREATE
- AML_CLASS_EXECUTE
- AML_CLASS_INTERNAL
- AML_CLASS_METHOD_CALL
- AML_CLASS_NAMED_OBJECT
- AML_CLASS_PREFIX
- AML_CLASS_RETURN_VALUE
- AML_CLASS_UNKNOWN
- AML_COMMENT_CLOSE_BRACE
- AML_COMMENT_ENDBLK
- AML_COMMENT_END_NODE
- AML_COMMENT_INCLUDE
- AML_COMMENT_OP
- AML_COMMENT_STANDARD
- AML_CONCATENATE_OP
- AML_CONCATENATE_TEMPLATE_OP
- AML_CONDITIONAL_REF_OF_OP
- AML_CONSTANT
- AML_CONTINUE_OP
- AML_COPY_OBJECT_OP
- AML_CREATE
- AML_CREATE_BIT_FIELD_OP
- AML_CREATE_BYTE_FIELD_OP
- AML_CREATE_DWORD_FIELD_OP
- AML_CREATE_FIELD_OP
- AML_CREATE_QWORD_FIELD_OP
- AML_CREATE_WORD_FIELD_OP
- AML_DATA_REGION_OP
- AML_DEBUG_OP
- AML_DECREMENT_OP
- AML_DEFER
- AML_DEREF_OF_OP
- AML_DEVICE_OP
- AML_DIVIDE_OP
- AML_DUAL_NAME_PREFIX
- AML_DWORD_OP
- AML_ELSE_OP
- AML_EVENT_OP
- AML_EXTENDED_OPCODE
- AML_EXTENDED_PREFIX
- AML_EXTERNAL_OP
- AML_FATAL_OP
- AML_FIELD
- AML_FIELD_ACCESS_ANY
- AML_FIELD_ACCESS_BUFFER
- AML_FIELD_ACCESS_BYTE
- AML_FIELD_ACCESS_DWORD
- AML_FIELD_ACCESS_OP
- AML_FIELD_ACCESS_QWORD
- AML_FIELD_ACCESS_TYPE_MASK
- AML_FIELD_ACCESS_WORD
- AML_FIELD_ATTRIB_BLOCK
- AML_FIELD_ATTRIB_BLOCK_PROCESS_CALL
- AML_FIELD_ATTRIB_BYTE
- AML_FIELD_ATTRIB_BYTES
- AML_FIELD_ATTRIB_PROCESS_CALL
- AML_FIELD_ATTRIB_QUICK
- AML_FIELD_ATTRIB_RAW_BYTES
- AML_FIELD_ATTRIB_RAW_PROCESS_BYTES
- AML_FIELD_ATTRIB_SEND_RECEIVE
- AML_FIELD_ATTRIB_WORD
- AML_FIELD_CONNECTION_OP
- AML_FIELD_EXT_ACCESS_OP
- AML_FIELD_LOCK_ALWAYS
- AML_FIELD_LOCK_NEVER
- AML_FIELD_LOCK_RULE_MASK
- AML_FIELD_OFFSET_OP
- AML_FIELD_OP
- AML_FIELD_UPDATE_PRESERVE
- AML_FIELD_UPDATE_RULE_MASK
- AML_FIELD_UPDATE_WRITE_AS_ONES
- AML_FIELD_UPDATE_WRITE_AS_ZEROS
- AML_FIND_SET_LEFT_BIT_OP
- AML_FIND_SET_RIGHT_BIT_OP
- AML_FIRST_ARG_OP
- AML_FIRST_LOCAL_OP
- AML_FLAGS_EXEC_0A_0T_1R
- AML_FLAGS_EXEC_1A_0T_0R
- AML_FLAGS_EXEC_1A_0T_1R
- AML_FLAGS_EXEC_1A_1T_0R
- AML_FLAGS_EXEC_1A_1T_1R
- AML_FLAGS_EXEC_2A_0T_0R
- AML_FLAGS_EXEC_2A_0T_1R
- AML_FLAGS_EXEC_2A_1T_1R
- AML_FLAGS_EXEC_2A_2T_1R
- AML_FLAGS_EXEC_3A_0T_0R
- AML_FLAGS_EXEC_3A_1T_1R
- AML_FLAGS_EXEC_6A_0T_1R
- AML_FROM_BCD_OP
- AML_HAS_ARGS
- AML_HAS_RETVAL
- AML_HAS_TARGET
- AML_IF_OP
- AML_INCREMENT_OP
- AML_INDEX_FIELD_OP
- AML_INDEX_OP
- AML_INT_ACCESSFIELD_OP
- AML_INT_BYTELIST_OP
- AML_INT_CONNECTION_OP
- AML_INT_EVAL_SUBTREE_OP
- AML_INT_EXTACCESSFIELD_OP
- AML_INT_METHODCALL_OP
- AML_INT_NAMEDFIELD_OP
- AML_INT_NAMEPATH_OP
- AML_INT_RESERVEDFIELD_OP
- AML_INT_RETURN_VALUE_OP
- AML_LOAD_OP
- AML_LOAD_TABLE_OP
- AML_LOCAL0
- AML_LOCAL1
- AML_LOCAL2
- AML_LOCAL3
- AML_LOCAL4
- AML_LOCAL5
- AML_LOCAL6
- AML_LOCAL7
- AML_LOCK_RULE
- AML_LOGICAL
- AML_LOGICAL_AND_OP
- AML_LOGICAL_EQUAL_OP
- AML_LOGICAL_GREATER_EQUAL_OP
- AML_LOGICAL_GREATER_OP
- AML_LOGICAL_LESS_EQUAL_OP
- AML_LOGICAL_LESS_OP
- AML_LOGICAL_NOT_EQUAL_OP
- AML_LOGICAL_NOT_OP
- AML_LOGICAL_NUMERIC
- AML_LOGICAL_OR_OP
- AML_MATCH_OP
- AML_MATCH_OPERATOR
- AML_MATH
- AML_METHOD_ARG_COUNT
- AML_METHOD_OP
- AML_METHOD_SERIALIZED
- AML_METHOD_SYNC_LEVEL
- AML_MID_OP
- AML_MOD_OP
- AML_MULTIPLY_OP
- AML_MULTI_NAME_PREFIX
- AML_MUTEX_OP
- AML_NAMECOMMENT
- AML_NAMED
- AML_NAME_OP
- AML_NFW_SPACE
- AML_NOOP_OP
- AML_NOTIFY_OP
- AML_NO_OPERAND_RESOLVE
- AML_NSNODE
- AML_NSOBJECT
- AML_NSOPCODE
- AML_NUM_OPCODES
- AML_OBJECT_TYPE_OP
- AML_OFFSET
- AML_ONES_OP
- AML_ONE_OP
- AML_PACKAGE_OP
- AML_PARENT_PREFIX
- AML_POWER_RESOURCE_OP
- AML_PROCESSOR_OP
- AML_QWORD_OP
- AML_REF_OF_OP
- AML_REGION_OP
- AML_RELEASE_OP
- AML_RESET_OP
- AML_RESOURCE_ADDRESS_COMMON
- AML_RESOURCE_EXTENDED_ADDRESS_REVISION
- AML_RESOURCE_GPIO_REVISION
- AML_RESOURCE_GPIO_TYPE_INT
- AML_RESOURCE_GPIO_TYPE_IO
- AML_RESOURCE_I2C_MIN_DATA_LEN
- AML_RESOURCE_I2C_REVISION
- AML_RESOURCE_I2C_SERIALBUSTYPE
- AML_RESOURCE_I2C_TYPE_REVISION
- AML_RESOURCE_LARGE_HEADER_COMMON
- AML_RESOURCE_MAX_GPIOTYPE
- AML_RESOURCE_MAX_SERIALBUSTYPE
- AML_RESOURCE_PIN_CONFIG_REVISION
- AML_RESOURCE_PIN_FUNCTION_REVISION
- AML_RESOURCE_PIN_GROUP_CONFIG_REVISION
- AML_RESOURCE_PIN_GROUP_FUNCTION_REVISION
- AML_RESOURCE_PIN_GROUP_REVISION
- AML_RESOURCE_SERIAL_COMMON
- AML_RESOURCE_SMALL_HEADER_COMMON
- AML_RESOURCE_SPI_MIN_DATA_LEN
- AML_RESOURCE_SPI_REVISION
- AML_RESOURCE_SPI_SERIALBUSTYPE
- AML_RESOURCE_SPI_TYPE_REVISION
- AML_RESOURCE_UART_MIN_DATA_LEN
- AML_RESOURCE_UART_REVISION
- AML_RESOURCE_UART_SERIALBUSTYPE
- AML_RESOURCE_UART_TYPE_REVISION
- AML_RESOURCE_VENDOR_SERIALBUSTYPE
- AML_RETURN_OP
- AML_REVISION_OP
- AML_ROOT_PREFIX
- AML_SCOPE_OP
- AML_SHIFT_LEFT_BIT_OP
- AML_SHIFT_LEFT_OP
- AML_SHIFT_RIGHT_BIT_OP
- AML_SHIFT_RIGHT_OP
- AML_SIGNAL_OP
- AML_SIZE_OF_OP
- AML_SLEEP_OP
- AML_STALL_OP
- AML_STORE_OP
- AML_STRING_OP
- AML_SUBTRACT_OP
- AML_THERMAL_ZONE_OP
- AML_TIMER_OP
- AML_TO_BCD_OP
- AML_TO_BUFFER_OP
- AML_TO_DECIMAL_STRING_OP
- AML_TO_HEX_STRING_OP
- AML_TO_INTEGER_OP
- AML_TO_STRING_OP
- AML_TYPE_BOGUS
- AML_TYPE_CONSTANT
- AML_TYPE_CONTROL
- AML_TYPE_CREATE_FIELD
- AML_TYPE_CREATE_OBJECT
- AML_TYPE_DATA_TERM
- AML_TYPE_EXEC_0A_0T_1R
- AML_TYPE_EXEC_1A_0T_0R
- AML_TYPE_EXEC_1A_0T_1R
- AML_TYPE_EXEC_1A_1T_0R
- AML_TYPE_EXEC_1A_1T_1R
- AML_TYPE_EXEC_2A_0T_0R
- AML_TYPE_EXEC_2A_0T_1R
- AML_TYPE_EXEC_2A_1T_1R
- AML_TYPE_EXEC_2A_2T_1R
- AML_TYPE_EXEC_3A_0T_0R
- AML_TYPE_EXEC_3A_1T_1R
- AML_TYPE_EXEC_6A_0T_1R
- AML_TYPE_LITERAL
- AML_TYPE_LOCAL_VARIABLE
- AML_TYPE_METHOD_ARGUMENT
- AML_TYPE_METHOD_CALL
- AML_TYPE_NAMED_COMPLEX
- AML_TYPE_NAMED_FIELD
- AML_TYPE_NAMED_NO_OBJ
- AML_TYPE_NAMED_SIMPLE
- AML_TYPE_RETURN
- AML_TYPE_UNDEFINED
- AML_UART_BAUD_MASK
- AML_UART_BAUD_USE
- AML_UART_BAUD_XTAL
- AML_UART_CLEAR_ERR
- AML_UART_CONTROL
- AML_UART_DATA_LEN_5BIT
- AML_UART_DATA_LEN_6BIT
- AML_UART_DATA_LEN_7BIT
- AML_UART_DATA_LEN_8BIT
- AML_UART_DATA_LEN_MASK
- AML_UART_DEV_NAME
- AML_UART_ERR
- AML_UART_FRAME_ERR
- AML_UART_MISC
- AML_UART_PARITY_EN
- AML_UART_PARITY_ERR
- AML_UART_PARITY_TYPE
- AML_UART_PORT_NUM
- AML_UART_PORT_OFFSET
- AML_UART_RECV_IRQ
- AML_UART_REG5
- AML_UART_RFIFO
- AML_UART_RX_EMPTY
- AML_UART_RX_EN
- AML_UART_RX_INT_EN
- AML_UART_RX_RST
- AML_UART_STATUS
- AML_UART_STOP_BIT_1SB
- AML_UART_STOP_BIT_2SB
- AML_UART_STOP_BIT_LEN_MASK
- AML_UART_TWO_WIRE_EN
- AML_UART_TX_EMPTY
- AML_UART_TX_EN
- AML_UART_TX_FIFO_WERR
- AML_UART_TX_FULL
- AML_UART_TX_INT_EN
- AML_UART_TX_RST
- AML_UART_WFIFO
- AML_UART_XMIT_BUSY
- AML_UART_XMIT_IRQ
- AML_UNLOAD_OP
- AML_UPDATE_RULE
- AML_VARIABLE_PACKAGE_OP
- AML_WAIT_OP
- AML_WHILE_OP
- AML_WORD_OP
- AML_ZERO_OP
- AMOI_PRODUCT_H01
- AMOI_PRODUCT_H01A
- AMOI_PRODUCT_H02
- AMOI_PRODUCT_SKYPEPHONE_S2
- AMOI_VENDOR_ID
- AMOPHI
- AMOPHI_SADR
- AMOPHI_SE
- AMOPLO
- AMOPLO_IV
- AMOPLO_M
- AMOPLO_X
- AMOPLO_Y
- AMOP_END
- AMOP_START
- AMOUSE
- AMPDU_ACTION_ASSIGN
- AMPDU_ACTION_ENTRY
- AMPDU_ACTION_PR_ARG
- AMPDU_ACTION_PR_FMT
- AMPDU_AGG_HOST
- AMPDU_BA_WINSIZE
- AMPDU_BA_WINSIZE_FORCE_WINSIZE
- AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
- AMPDU_DEF_FFPLD_RSVD
- AMPDU_DEF_MPDU_DENSITY
- AMPDU_DEF_RETRY_LIMIT
- AMPDU_DEF_RR_RETRY_LIMIT
- AMPDU_DELIMITER_LEN
- AMPDU_DENSITY_SHT
- AMPDU_FBR_NULL_DELIM
- AMPDU_IND
- AMPDU_INI_FREE
- AMPDU_MAX_DUR
- AMPDU_MAX_MPDU
- AMPDU_MAX_MPDU_OVERHEAD
- AMPDU_MAX_SCB_TID
- AMPDU_MIN_SPACE
- AMPDU_NO_STREAM
- AMPDU_NUM_MPDU
- AMPDU_NUM_MPDU_LEGACY
- AMPDU_RX_BA_DEF_WSIZE
- AMPDU_RX_BA_MAX_WSIZE
- AMPDU_SCB_MAX_RELEASE
- AMPDU_STREAM_ACTIVE
- AMPDU_STREAM_IN_PROGRESS
- AMPDU_STREAM_NEW
- AMPDU_TX_BA_DEF_WSIZE
- AMPDU_TX_BA_MAX_WSIZE
- AMPLC_DIO200_H_INCLUDED
- AMPLC_DIO_CLK_100KHZ
- AMPLC_DIO_CLK_10KHZ
- AMPLC_DIO_CLK_10MHZ
- AMPLC_DIO_CLK_1KHZ
- AMPLC_DIO_CLK_1MHZ
- AMPLC_DIO_CLK_20MHZ
- AMPLC_DIO_CLK_CLKN
- AMPLC_DIO_CLK_EXT
- AMPLC_DIO_CLK_GND
- AMPLC_DIO_CLK_OUTNM1
- AMPLC_DIO_CLK_PAT_PRESENT
- AMPLC_DIO_CLK_VCC
- AMPLC_DIO_GAT_GATN
- AMPLC_DIO_GAT_GND
- AMPLC_DIO_GAT_NGATN
- AMPLC_DIO_GAT_NOUTNM2
- AMPLC_DIO_GAT_NPAT_GONE
- AMPLC_DIO_GAT_NPAT_OCCURRED
- AMPLC_DIO_GAT_NPAT_PRESENT
- AMPLC_DIO_GAT_OUTNM2
- AMPLC_DIO_GAT_PAT_GONE
- AMPLC_DIO_GAT_PAT_OCCURRED
- AMPLC_DIO_GAT_PAT_PRESENT
- AMPLC_DIO_GAT_RESERVED4
- AMPLC_DIO_GAT_RESERVED5
- AMPLC_DIO_GAT_RESERVED6
- AMPLC_DIO_GAT_RESERVED7
- AMPLC_DIO_GAT_VCC
- AMPLC_DIO_TS_CLK_1GHZ
- AMPLC_DIO_TS_CLK_1KHZ
- AMPLC_DIO_TS_CLK_1MHZ
- AMPLC_PC236_H_INCLUDED
- AMPLITUDE_GEN1
- AMPLITUDE_GEN1_SHIFT
- AMPLITUDE_GEN2
- AMPLITUDE_GEN2_SHIFT
- AMPLITUDE_GEN3
- AMPLITUDE_GEN3_SHIFT
- AMPLITUDE_MASK
- AMPREF_MASK
- AMPREF_MASK_SFT
- AMPREF_SFT
- AMP_AHB_CLK
- AMP_AUDIO2000_DEVICE_DESC
- AMP_BIAS_CTRL
- AMP_CH_HD
- AMP_CH_SPK
- AMP_CONTROL
- AMP_DIV_CH1_MASK
- AMP_DIV_CH1_MASK_SFT
- AMP_DIV_CH1_SFT
- AMP_DIV_CH2_MASK
- AMP_DIV_CH2_MASK_SFT
- AMP_DIV_CH2_SFT
- AMP_DN
- AMP_GAIN_0
- AMP_GAIN_1
- AMP_ID_BREDR
- AMP_IN_MUTE
- AMP_IN_UNMUTE
- AMP_LINK
- AMP_MUTE_SDL
- AMP_MUTE_SDR
- AMP_OUT_MUTE
- AMP_OUT_UNMUTE
- AMP_OUT_ZERO
- AMP_RESET
- AMP_STATUS_BLUETOOTH_ONLY
- AMP_STATUS_FULL_CAPACITY
- AMP_STATUS_HIGH_CAPACITY
- AMP_STATUS_LOW_CAPACITY
- AMP_STATUS_MEDIUM_CAPACITY
- AMP_STATUS_NO_CAPACITY
- AMP_STATUS_POWERED_DOWN
- AMP_TYPE_80211
- AMP_TYPE_BREDR
- AMP_VAL_COMPARE_MASK
- AMP_VAL_IDX_MASK
- AMP_VAL_IDX_SHIFT
- AMRADIO_GET_FREQ
- AMRADIO_GET_READY_FLAG
- AMRADIO_GET_SIGNAL
- AMRADIO_SET_FREQ
- AMRADIO_SET_LEFT_MUTE
- AMRADIO_SET_MONO
- AMRADIO_SET_MUTE
- AMRADIO_SET_RIGHT_MUTE
- AMRADIO_SET_SEARCH_DOWN
- AMRADIO_SET_SEARCH_LVL
- AMRADIO_SET_SEARCH_UP
- AMRADIO_STOP_SEARCH
- AMR_BITS_PER_PKEY
- AMR_DER_COLLISION
- AMR_DER_FCS
- AMR_DER_OVFL
- AMR_DER_OVRN
- AMR_DER_RABRT
- AMR_DER_RFRAME
- AMR_DER_UNFL
- AMR_DER_UNRN
- AMR_DLC_12_15
- AMR_DLC_1_7
- AMR_DLC_ASR
- AMR_DLC_DMR1
- AMR_DLC_DMR1_DRTHRSH_INT
- AMR_DLC_DMR1_DTTHRSH_INT
- AMR_DLC_DMR1_EN_ADDR1
- AMR_DLC_DMR1_EN_ADDR2
- AMR_DLC_DMR1_EN_ADDR3
- AMR_DLC_DMR1_EN_ADDR4
- AMR_DLC_DMR1_EN_ADDRS
- AMR_DLC_DMR1_EORP_INT
- AMR_DLC_DMR1_TAR_ENABL
- AMR_DLC_DMR2
- AMR_DLC_DMR2_COLL_INT
- AMR_DLC_DMR2_FCS_INT
- AMR_DLC_DMR2_OVFL_INT
- AMR_DLC_DMR2_OVRN_INT
- AMR_DLC_DMR2_RABRT_INT
- AMR_DLC_DMR2_RESID_INT
- AMR_DLC_DMR2_UNFL_INT
- AMR_DLC_DMR2_UNRN_INT
- AMR_DLC_DMR3
- AMR_DLC_DMR3_EOTP_INT
- AMR_DLC_DMR3_KEEP_FCS
- AMR_DLC_DMR3_LBRP_INT
- AMR_DLC_DMR3_LBT_INT
- AMR_DLC_DMR3_RBA_INT
- AMR_DLC_DMR3_RPLOST_INT
- AMR_DLC_DMR3_TBE_INT
- AMR_DLC_DMR3_VA_INT
- AMR_DLC_DMR4
- AMR_DLC_DMR4_ADDR_1ST
- AMR_DLC_DMR4_ADDR_2ND
- AMR_DLC_DMR4_ADDR_BOTH
- AMR_DLC_DMR4_CR_ENABLE
- AMR_DLC_DMR4_IDLE_FLAG
- AMR_DLC_DMR4_IDLE_MARK
- AMR_DLC_DMR4_RCV_1
- AMR_DLC_DMR4_RCV_16
- AMR_DLC_DMR4_RCV_2
- AMR_DLC_DMR4_RCV_24
- AMR_DLC_DMR4_RCV_30
- AMR_DLC_DMR4_RCV_4
- AMR_DLC_DMR4_RCV_8
- AMR_DLC_DMR4_XMT_1
- AMR_DLC_DMR4_XMT_10
- AMR_DLC_DMR4_XMT_14
- AMR_DLC_DMR4_XMT_2
- AMR_DLC_DMR4_XMT_4
- AMR_DLC_DMR4_XMT_8
- AMR_DLC_DRCR
- AMR_DLC_DRLR
- AMR_DLC_DTCR
- AMR_DLC_EFCR
- AMR_DLC_EFCR_EXTEND_FIFO
- AMR_DLC_EFCR_SEC_PKT_INT
- AMR_DLC_FRAR4
- AMR_DLC_FRAR_1_2_3
- AMR_DLC_RNGR1
- AMR_DLC_RNGR2
- AMR_DLC_SRAR4
- AMR_DLC_SRAR_1_2_3
- AMR_DLC_TAR
- AMR_DSR1_CXMT_ABRT
- AMR_DSR1_DBACK_OFF
- AMR_DSR1_DECHO_ON
- AMR_DSR1_DLOOP_ON
- AMR_DSR1_EORP
- AMR_DSR1_EOTP
- AMR_DSR1_PKT_IP
- AMR_DSR1_VADDR
- AMR_DSR2_FLAG_IDLE
- AMR_DSR2_LAST_BYTE
- AMR_DSR2_LBRP
- AMR_DSR2_MARK_IDLE
- AMR_DSR2_RBA
- AMR_DSR2_RPLOST
- AMR_DSR2_SECOND_PKT
- AMR_DSR2_TBE
- AMR_INIT
- AMR_INIT2
- AMR_IR_BBUF
- AMR_IR_DERI
- AMR_IR_DRTHRSH
- AMR_IR_DSR2I
- AMR_IR_DSRI
- AMR_IR_DTTHRSH
- AMR_IR_LSRI
- AMR_IR_MLTFRMI
- AMR_KUAP_BLOCKED
- AMR_KUAP_BLOCK_READ
- AMR_KUAP_BLOCK_WRITE
- AMR_KUAP_SHIFT
- AMR_LIU_2_4
- AMR_LIU_LMR1
- AMR_LIU_LMR2
- AMR_LIU_LPR
- AMR_LIU_LSR
- AMR_LIU_MF
- AMR_LIU_MFQB
- AMR_LIU_MFSB
- AMR_MAP_15_16
- AMR_MAP_1_10
- AMR_MAP_ATGR_1_2
- AMR_MAP_FTGR_1_2
- AMR_MAP_GER
- AMR_MAP_GR
- AMR_MAP_GX
- AMR_MAP_MMR1
- AMR_MAP_MMR2
- AMR_MAP_MMR3
- AMR_MAP_PEAKR
- AMR_MAP_PEAKX
- AMR_MAP_R
- AMR_MAP_STGR
- AMR_MAP_STRA
- AMR_MAP_STRF
- AMR_MAP_X
- AMR_MUX_1_4
- AMR_MUX_MCR1
- AMR_MUX_MCR2
- AMR_MUX_MCR3
- AMR_MUX_MCR4
- AMR_PP_CIRDR0
- AMR_PP_CIRDR1
- AMR_PP_CITDR0
- AMR_PP_CITDR1
- AMR_PP_MRDR
- AMR_PP_MTDR
- AMR_PP_PPCR1
- AMR_PP_PPCR2
- AMR_PP_PPCR3
- AMR_PP_PPIER
- AMR_PP_PPSR
- AMR_RD_BIT
- AMR_WR_BIT
- AMSDU_FRAMETAG
- AMSG_IN
- AMSG_OUT
- AMSR
- AMS_CMD_ERASEMEM
- AMS_CMD_NOOP
- AMS_CMD_READEE
- AMS_CMD_READMEM
- AMS_CMD_RESET
- AMS_CMD_START
- AMS_CMD_VERSION
- AMS_CMD_WRITEEE
- AMS_CMD_WRITEMEM
- AMS_COMMAND
- AMS_CONTROL
- AMS_CTRL1
- AMS_CTRL2
- AMS_CTRL3
- AMS_CTRLX
- AMS_CTRLY
- AMS_CTRLZ
- AMS_DATA1
- AMS_DATA2
- AMS_DATA3
- AMS_DATA4
- AMS_DATAX
- AMS_DATAY
- AMS_DATAZ
- AMS_DELTA_AGC
- AMS_DELTA_DEFAULT_CONTRAST
- AMS_DELTA_EARPIECE
- AMS_DELTA_GPIO_PIN_CONFIG
- AMS_DELTA_GPIO_PIN_HOOK_SWITCH
- AMS_DELTA_GPIO_PIN_KEYBRD_CLK
- AMS_DELTA_GPIO_PIN_KEYBRD_DATA
- AMS_DELTA_GPIO_PIN_MODEM_IRQ
- AMS_DELTA_GPIO_PIN_NAND_RB
- AMS_DELTA_GPIO_PIN_SCARD_IO
- AMS_DELTA_GPIO_PIN_SCARD_NOFF
- AMS_DELTA_HANDSET
- AMS_DELTA_HANDSFREE
- AMS_DELTA_LCD_POWER
- AMS_DELTA_MAX_CONTRAST
- AMS_DELTA_MICROPHONE
- AMS_DELTA_MIXED
- AMS_DELTA_MOUTHPIECE
- AMS_DELTA_SPEAKER
- AMS_DELTA_SPEAKERPHONE
- AMS_FF_CLEAR
- AMS_FF_DEBOUNCE
- AMS_FF_ENABLE
- AMS_FF_LOW_LIMIT
- AMS_FREEFALL
- AMS_IAQCORE_DATA_SIZE
- AMS_IAQCORE_VOC_CO2_IDX
- AMS_IAQCORE_VOC_RESISTANCE_IDX
- AMS_IAQCORE_VOC_TVOC_IDX
- AMS_IRQ_ALL
- AMS_IRQ_FREEFALL
- AMS_IRQ_GLOBAL
- AMS_IRQ_SHOCK
- AMS_REF
- AMS_SENSHIGH
- AMS_SENSLOW
- AMS_SHOCK
- AMS_SHOCK_CLEAR
- AMS_SHOCK_DEBOUNCE
- AMS_SHOCK_ENABLE
- AMS_SHOCK_HIGH_LIMIT
- AMS_STATUS
- AMS_UNKNOWN1
- AMS_UNKNOWN2
- AMS_UNKNOWN3
- AMS_VENDOR
- AMS_X
- AMS_Y
- AMS_Z
- AMT_BIOS_VERSION_LEN
- AMT_FCH_GPIO_REG_GEVT22
- AMT_HOST_IF_CODE_VERSIONS_REQUEST
- AMT_HOST_IF_CODE_VERSIONS_RESPONSE
- AMT_MAJOR_VERSION
- AMT_MINOR_VERSION
- AMT_STATUS_HOST_IF_EMPTY_RESPONSE
- AMT_STATUS_INTERNAL_ERROR
- AMT_STATUS_INVALID_AMT_MODE
- AMT_STATUS_INVALID_MESSAGE_LENGTH
- AMT_STATUS_NOT_READY
- AMT_STATUS_SDK_RESOURCES
- AMT_STATUS_SUCCESS
- AMT_UNICODE_STRING_LEN
- AMT_VERSIONS_NUMBER
- AMUX_RSV0
- AMUX_RSV1
- AMUX_RSV2
- AMUX_RSV3
- AMUX_RSV4
- AMUX_RSV5
- AMW0_EVENT_GUID
- AMW0_GUID1
- AMW0_GUID2
- AMW0_find_mailled
- AMW0_get_u32
- AMW0_set_cap_acpi_check_device
- AMW0_set_capabilities
- AMW0_set_u32
- AMX3_PM_SRAM_SYMBOL_OFFSET
- AM_1D_TILED_THICK
- AM_1D_TILED_THIN1
- AM_2D_TILED_THICK
- AM_2D_TILED_THIN1
- AM_2D_TILED_XTHICK
- AM_3D_TILED_THICK
- AM_3D_TILED_THIN1
- AM_3D_TILED_XTHICK
- AM_CFG_MAX_TRANS
- AM_CFG_SINGLE_PORT_MAX_TRANS
- AM_CTRL_GLOBAL
- AM_CTRL_SHUTDOWN_REQ_MSK
- AM_CTRL_SHUTDOWN_REQ_OFF
- AM_CURR_TRANS_RETURN
- AM_FM_DIFF
- AM_FREQ_RANGE_HIGH
- AM_FREQ_RANGE_LOW
- AM_IND_IO
- AM_INIT2_ENABLE_MULTIFRAME
- AM_INIT2_ENABLE_POWERDOWN
- AM_INIT_ACTIVE
- AM_INIT_DATAONLY
- AM_INIT_DISABLE_INTS
- AM_INIT_POWERDOWN
- AM_IO
- AM_LINEAR_ALIGNED
- AM_LINEAR_GENERAL
- AM_LIU_LMR1_B1_ENABL
- AM_LIU_LMR1_B2_ENABL
- AM_LIU_LMR1_F8_F3
- AM_LIU_LMR1_FA_DISABL
- AM_LIU_LMR1_F_DISABL
- AM_LIU_LMR1_LIU_ENABL
- AM_LIU_LMR1_REQ_ACTIV
- AM_LIU_LMR2_DBACKOFF
- AM_LIU_LMR2_DECHO
- AM_LIU_LMR2_DLOOP
- AM_LIU_LMR2_EN_F3_INT
- AM_LIU_LMR2_EN_F7_INT
- AM_LIU_LMR2_EN_F8_INT
- AM_LIU_LMR2_EN_HSW_INT
- AM_LIU_LSR_F3
- AM_LIU_LSR_F7
- AM_LIU_LSR_F8
- AM_LIU_LSR_HSW
- AM_LIU_LSR_HSW_CHG
- AM_LIU_LSR_STATE
- AM_MAP_MMR1_ALAW
- AM_MAP_MMR1_GER
- AM_MAP_MMR1_GR
- AM_MAP_MMR1_GX
- AM_MAP_MMR1_LOOPBACK
- AM_MAP_MMR1_R
- AM_MAP_MMR1_STG
- AM_MAP_MMR1_X
- AM_MAP_MMR2_AINB
- AM_MAP_MMR2_DISABLE_AUTOZERO
- AM_MAP_MMR2_DISABLE_HIGHPASS
- AM_MAP_MMR2_ENABLE_DTMF
- AM_MAP_MMR2_ENABLE_TONEGEN
- AM_MAP_MMR2_ENABLE_TONERING
- AM_MAP_MMR2_LS
- AM_MEMIO
- AM_MTS_DET
- AM_MUX_CHANNEL_B1
- AM_MUX_CHANNEL_B2
- AM_MUX_CHANNEL_Ba
- AM_MUX_CHANNEL_Bb
- AM_MUX_CHANNEL_Bc
- AM_MUX_CHANNEL_Bd
- AM_MUX_CHANNEL_Be
- AM_MUX_CHANNEL_Bf
- AM_MUX_MCR4_ENABLE_INTS
- AM_MUX_MCR4_REVERSE_Bb
- AM_MUX_MCR4_REVERSE_Bc
- AM_NONE
- AM_PRT_2D_TILED_THICK
- AM_PRT_2D_TILED_THIN1
- AM_PRT_3D_TILED_THICK
- AM_PRT_3D_TILED_THIN1
- AM_PRT_TILED_THICK
- AM_PRT_TILED_THIN1
- AM_ROB_ECC_ERR_ADDR
- AM_ROB_ECC_ERR_ADDR_MSK
- AM_ROB_ECC_ERR_ADDR_OFF
- AM_VIB
- AN0_MARK
- AN1_MARK
- AN2_MARK
- AN30259A_BLINK_MAX_TIME
- AN30259A_LED_DELAY
- AN30259A_LED_DT1
- AN30259A_LED_DT2
- AN30259A_LED_DT3
- AN30259A_LED_DT4
- AN30259A_LED_DUTYMAX
- AN30259A_LED_DUTYMID
- AN30259A_LED_DUTYMIN
- AN30259A_LED_EN
- AN30259A_LED_SLOPE
- AN30259A_LED_SLOPETIME1
- AN30259A_LED_SLOPETIME2
- AN30259A_LED_SRESET
- AN30259A_MAX_LEDS
- AN30259A_NAME
- AN30259A_REG_LEDCC
- AN30259A_REG_LEDCNT1
- AN30259A_REG_LEDCNT2
- AN30259A_REG_LEDCNT3
- AN30259A_REG_LEDCNT4
- AN30259A_REG_LED_ON
- AN30259A_REG_MAX
- AN30259A_REG_SLOPE
- AN30259A_REG_SRESET
- AN30259A_SLOPE_RESOLUTION
- AN3_MARK
- ANA
- ANA8M
- ANABLE
- ANACTRL_AFE_MODE_EN
- ANACTRL_CLASSA_EN
- ANACTRL_CLK125M_DELAY_EN
- ANACTRL_DEF
- ANACTRL_HBIAS_EN
- ANACTRL_HB_EN
- ANACTRL_LCKDET_EN
- ANACTRL_LCKDET_PHY
- ANACTRL_MANUSWON_BW3_4M
- ANACTRL_MANUSWON_SWR_1P7V
- ANACTRL_MANUSWON_SWR_1P8V
- ANACTRL_MANUSWON_SWR_1P9V
- ANACTRL_MANUSWON_SWR_2V
- ANACTRL_MANUSWON_SWR_MASK
- ANACTRL_MANUSWON_SWR_SHIFT
- ANACTRL_OEN_125M
- ANACTRL_RESTART_CAL
- ANACTRL_SEL_HSP
- ANACTRL_VCO_FAST
- ANACTRL_VCO_SLOW
- ANAD16V_EN
- ANADIG_ANA_MISC0
- ANADIG_ANA_MISC0_CLR
- ANADIG_ANA_MISC0_SET
- ANADIG_DIGPROG
- ANADIG_DIGPROG_IMX6SL
- ANADIG_DIGPROG_IMX7D
- ANADIG_DIGPROG_IMX8MM
- ANADIG_REG_2P5
- ANADIG_REG_CORE
- ANADIG_USB1_CHRG_DETECT
- ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B
- ANADIG_USB1_CHRG_DETECT_CHK_CONTACT
- ANADIG_USB1_CHRG_DETECT_CLR
- ANADIG_USB1_CHRG_DETECT_EN_B
- ANADIG_USB1_CHRG_DETECT_SET
- ANADIG_USB1_CHRG_DET_STAT
- ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED
- ANADIG_USB1_CHRG_DET_STAT_DM_STATE
- ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT
- ANADIG_USB1_LOOPBACK_CLR
- ANADIG_USB1_LOOPBACK_SET
- ANADIG_USB1_LOOPBACK_UTMI_TESTSTART
- ANADIG_USB1_MISC
- ANADIG_USB1_VBUS_DET_STAT
- ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID
- ANADIG_USB2_CHRG_DETECT
- ANADIG_USB2_CHRG_DETECT_SET
- ANADIG_USB2_LOOPBACK_CLR
- ANADIG_USB2_LOOPBACK_SET
- ANADIG_USB2_MISC
- ANADIG_USB2_VBUS_DET_STAT
- ANALOG
- ANALOGCARRIER
- ANALOGIX_DP_ANALOG_CTL_1
- ANALOGIX_DP_ANALOG_CTL_2
- ANALOGIX_DP_ANALOG_CTL_3
- ANALOGIX_DP_AUDIO_MARGIN
- ANALOGIX_DP_AUX_ADDR_15_8
- ANALOGIX_DP_AUX_ADDR_19_16
- ANALOGIX_DP_AUX_ADDR_7_0
- ANALOGIX_DP_AUX_CH_CTL_1
- ANALOGIX_DP_AUX_CH_CTL_2
- ANALOGIX_DP_AUX_CH_DEFER_CTL
- ANALOGIX_DP_AUX_CH_STA
- ANALOGIX_DP_AUX_HW_RETRY_CTL
- ANALOGIX_DP_AUX_RX_COMM
- ANALOGIX_DP_BUFFER_DATA_CTL
- ANALOGIX_DP_BUF_DATA_0
- ANALOGIX_DP_COMMON_INT_MASK_1
- ANALOGIX_DP_COMMON_INT_MASK_2
- ANALOGIX_DP_COMMON_INT_MASK_3
- ANALOGIX_DP_COMMON_INT_MASK_4
- ANALOGIX_DP_COMMON_INT_STA_1
- ANALOGIX_DP_COMMON_INT_STA_2
- ANALOGIX_DP_COMMON_INT_STA_3
- ANALOGIX_DP_COMMON_INT_STA_4
- ANALOGIX_DP_CRC_CON
- ANALOGIX_DP_DEBUG_CTL
- ANALOGIX_DP_FUNC_EN_1
- ANALOGIX_DP_FUNC_EN_2
- ANALOGIX_DP_HDCP_CTL
- ANALOGIX_DP_HPD_DEGLITCH_H
- ANALOGIX_DP_HPD_DEGLITCH_L
- ANALOGIX_DP_IF_PKT_DB1
- ANALOGIX_DP_IF_PKT_DB2
- ANALOGIX_DP_IF_TYPE
- ANALOGIX_DP_INT_CTL
- ANALOGIX_DP_INT_STA
- ANALOGIX_DP_INT_STA_MASK
- ANALOGIX_DP_LANE_COUNT_SET
- ANALOGIX_DP_LANE_MAP
- ANALOGIX_DP_LINK_BW_SET
- ANALOGIX_DP_LINK_DEBUG_CTL
- ANALOGIX_DP_LN0_LINK_TRAINING_CTL
- ANALOGIX_DP_LN1_LINK_TRAINING_CTL
- ANALOGIX_DP_LN2_LINK_TRAINING_CTL
- ANALOGIX_DP_LN3_LINK_TRAINING_CTL
- ANALOGIX_DP_M_AUD_GEN_FILTER_TH
- ANALOGIX_DP_M_VID_0
- ANALOGIX_DP_M_VID_1
- ANALOGIX_DP_M_VID_2
- ANALOGIX_DP_M_VID_GEN_FILTER_TH
- ANALOGIX_DP_N_VID_0
- ANALOGIX_DP_N_VID_1
- ANALOGIX_DP_N_VID_2
- ANALOGIX_DP_PD
- ANALOGIX_DP_PHY_PD
- ANALOGIX_DP_PHY_TEST
- ANALOGIX_DP_PKT_SEND_CTL
- ANALOGIX_DP_PLL_CTL
- ANALOGIX_DP_PLL_FILTER_CTL_1
- ANALOGIX_DP_PLL_REG_1
- ANALOGIX_DP_PLL_REG_2
- ANALOGIX_DP_PLL_REG_3
- ANALOGIX_DP_PLL_REG_4
- ANALOGIX_DP_PLL_REG_5
- ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL
- ANALOGIX_DP_SOC_GENERAL_CTL
- ANALOGIX_DP_SPDIF_AUDIO_CTL_0
- ANALOGIX_DP_SPD_HB0
- ANALOGIX_DP_SPD_HB1
- ANALOGIX_DP_SPD_HB2
- ANALOGIX_DP_SPD_HB3
- ANALOGIX_DP_SPD_PB0
- ANALOGIX_DP_SPD_PB1
- ANALOGIX_DP_SPD_PB2
- ANALOGIX_DP_SPD_PB3
- ANALOGIX_DP_SYS_CTL_1
- ANALOGIX_DP_SYS_CTL_2
- ANALOGIX_DP_SYS_CTL_3
- ANALOGIX_DP_SYS_CTL_4
- ANALOGIX_DP_TRAINING_PTN_SET
- ANALOGIX_DP_TX_AMP_TUNING_CTL
- ANALOGIX_DP_TX_SW_RESET
- ANALOGIX_DP_VIDEO_CTL_1
- ANALOGIX_DP_VIDEO_CTL_10
- ANALOGIX_DP_VIDEO_CTL_2
- ANALOGIX_DP_VIDEO_CTL_3
- ANALOGIX_DP_VIDEO_CTL_8
- ANALOGIX_DP_VIDEO_FIFO_THRD
- ANALOGIX_DP_VSC_SHADOW_DB0
- ANALOGIX_DP_VSC_SHADOW_DB1
- ANALOGUE_GAIN_CODE_GLOBAL_HI
- ANALOGUE_GAIN_CODE_GLOBAL_LO
- ANALOG_AGC_POWER_LEVEL_REG
- ANALOG_ANY_CHF
- ANALOG_AXES_STD
- ANALOG_AXIS_TIME
- ANALOG_BTNS_CHF
- ANALOG_BTNS_GAMEPAD
- ANALOG_BTNS_STD
- ANALOG_BTNS_TLR
- ANALOG_BTNS_TLR2
- ANALOG_BTN_TL
- ANALOG_BTN_TL2
- ANALOG_BTN_TR
- ANALOG_BTN_TR2
- ANALOG_CLOCK
- ANALOG_CONTROL
- ANALOG_CONTROL_0
- ANALOG_DELTA
- ANALOG_DEMOD_CTL
- ANALOG_EXTENSIONS
- ANALOG_FUZZ_BITS
- ANALOG_FUZZ_MAGIC
- ANALOG_GAIN_DEFAULT
- ANALOG_GAIN_MAX
- ANALOG_GAIN_MIN
- ANALOG_GAIN_STEP
- ANALOG_GAMEPAD
- ANALOG_HAT1_CHF
- ANALOG_HAT2_CHF
- ANALOG_HATS_ALL
- ANALOG_HAT_FCS
- ANALOG_HBTN_CHF
- ANALOG_INIT_RETRIES
- ANALOG_INTF_BASE_ADDRESS
- ANALOG_LOOP_TIME
- ANALOG_MAX_NAME_LENGTH
- ANALOG_MAX_PHYS_LENGTH
- ANALOG_MAX_PULSE
- ANALOG_MAX_TIME
- ANALOG_MIN_PULSE
- ANALOG_MUX_CTL
- ANALOG_PORTS
- ANALOG_POWER_OFF
- ANALOG_POWER_ON
- ANALOG_RUDDER
- ANALOG_SAITEK
- ANALOG_SAITEK_DELAY
- ANALOG_SAITEK_TIME
- ANALOG_THROTTLE
- ANALOG_TOTAL
- ANALOG_TUNER_STV0297
- ANALOG_TUNER_VES1820
- ANALOG_VID
- ANAME_SZ
- ANAPAR
- ANAPARAM_PWR0_MASK
- ANAPARAM_PWR0_SHIFT
- ANAPARAM_PWR1_MASK
- ANAPARAM_PWR1_SHIFT
- ANAPARAM_TXDACOFF_SHIFT
- ANAPAR_FOR_8192PciE
- ANAPLLCTL
- ANAR
- ANARANLPAR
- ANA_11N_013
- ANA_ADVLEARN
- ANA_ADVLEARN_LEARN_MIRROR
- ANA_ADVLEARN_VLAN_CHK
- ANA_AGENCTRL
- ANA_AGENCTRL_CPU_CPU_KILL_ENA
- ANA_AGENCTRL_FID_MASK
- ANA_AGENCTRL_FID_MASK_M
- ANA_AGENCTRL_FID_MASK_X
- ANA_AGENCTRL_FLOOD_IGNORE_VLAN
- ANA_AGENCTRL_FLOOD_SPECIAL
- ANA_AGENCTRL_GREEN_COUNT_MODE
- ANA_AGENCTRL_IGNORE_DMAC_FLAGS
- ANA_AGENCTRL_IGNORE_SMAC_FLAGS
- ANA_AGENCTRL_LEARN_CPU_COPY
- ANA_AGENCTRL_LEARN_FWD_KILL
- ANA_AGENCTRL_LEARN_IGNORE_VLAN
- ANA_AGENCTRL_MIRROR_CPU
- ANA_AGENCTRL_RED_COUNT_MODE
- ANA_AGENCTRL_YELLOW_COUNT_MODE
- ANA_AGGR_CFG
- ANA_AGGR_CFG_AC_DMAC_ENA
- ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA
- ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA
- ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA
- ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA
- ANA_AGGR_CFG_AC_ISDX_ENA
- ANA_AGGR_CFG_AC_RND_ENA
- ANA_AGGR_CFG_AC_SMAC_ENA
- ANA_ANAGEFIL
- ANA_ANAGEFIL_AGE_LOCKED
- ANA_ANAGEFIL_B_DOM_EN
- ANA_ANAGEFIL_B_DOM_VAL
- ANA_ANAGEFIL_PID_EN
- ANA_ANAGEFIL_PID_VAL
- ANA_ANAGEFIL_PID_VAL_M
- ANA_ANAGEFIL_PID_VAL_X
- ANA_ANAGEFIL_VID_EN
- ANA_ANAGEFIL_VID_VAL
- ANA_ANAGEFIL_VID_VAL_M
- ANA_ANEVENTS
- ANA_ANEVENTS_ACLKILL
- ANA_ANEVENTS_ACLUSED
- ANA_ANEVENTS_AGED_ENTRY
- ANA_ANEVENTS_AUTOAGE
- ANA_ANEVENTS_AUTO_LEARNED
- ANA_ANEVENTS_AUTO_LEARN_FAILED
- ANA_ANEVENTS_AUTO_MOVED
- ANA_ANEVENTS_BUCKET0_MATCH
- ANA_ANEVENTS_BUCKET1_MATCH
- ANA_ANEVENTS_BUCKET2_MATCH
- ANA_ANEVENTS_BUCKET3_MATCH
- ANA_ANEVENTS_CLASSIFIED_COPY
- ANA_ANEVENTS_CLASSIFIED_DROP
- ANA_ANEVENTS_CPU_LEARN_FAILED
- ANA_ANEVENTS_CPU_OPERATION
- ANA_ANEVENTS_DEST_KNOWN
- ANA_ANEVENTS_DMAC_LOOKUP
- ANA_ANEVENTS_DROPPED
- ANA_ANEVENTS_FLOOD_DISCARD
- ANA_ANEVENTS_FWD_DISCARD
- ANA_ANEVENTS_LEARN_DROP
- ANA_ANEVENTS_LEARN_REMOVE
- ANA_ANEVENTS_MSTI_DROP
- ANA_ANEVENTS_MULTICAST_FLOOD
- ANA_ANEVENTS_SEQ_GEN_ERR_0
- ANA_ANEVENTS_SEQ_GEN_ERR_1
- ANA_ANEVENTS_SMAC_LOOKUP
- ANA_ANEVENTS_STORM_DROP
- ANA_ANEVENTS_UNICAST_FLOOD
- ANA_ANEVENTS_VLAN_DISCARD
- ANA_ANEVENTS_VS2TTL1
- ANA_AUTOAGE
- ANA_AUTOAGE_AGE_FAST
- ANA_AUTOAGE_AGE_PERIOD
- ANA_AUTOAGE_AGE_PERIOD_M
- ANA_AUTOAGE_AGE_PERIOD_X
- ANA_AUTOAGE_AUTOAGE_LOCKED
- ANA_CLEAR_MASK
- ANA_CLK_CTL_EAR_HPHL_CLK_EN
- ANA_CLK_CTL_EAR_HPHR_CLK_EN
- ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK
- ANA_CLK_CTL_SPKR_CLK_EN
- ANA_CLK_CTL_SPKR_CLK_EN_MASK
- ANA_CLK_CTL_TXA_CLK25_EN
- ANA_COMMUNITY_PORTS
- ANA_CPUQ_8021_CFG
- ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL
- ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M
- ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X
- ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL
- ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M
- ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL
- ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M
- ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X
- ANA_CPUQ_8021_CFG_RSZ
- ANA_CPUQ_CFG
- ANA_CPUQ_CFG2
- ANA_CPUQ_CFG_CPUQ_ALLBRIDGE
- ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M
- ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X
- ANA_CPUQ_CFG_CPUQ_IGMP
- ANA_CPUQ_CFG_CPUQ_IGMP_M
- ANA_CPUQ_CFG_CPUQ_IGMP_X
- ANA_CPUQ_CFG_CPUQ_IPMC_CTRL
- ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M
- ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X
- ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE
- ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M
- ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X
- ANA_CPUQ_CFG_CPUQ_LRN
- ANA_CPUQ_CFG_CPUQ_LRN_M
- ANA_CPUQ_CFG_CPUQ_LRN_X
- ANA_CPUQ_CFG_CPUQ_MAC_COPY
- ANA_CPUQ_CFG_CPUQ_MAC_COPY_M
- ANA_CPUQ_CFG_CPUQ_MAC_COPY_X
- ANA_CPUQ_CFG_CPUQ_MIRROR
- ANA_CPUQ_CFG_CPUQ_MIRROR_M
- ANA_CPUQ_CFG_CPUQ_MIRROR_X
- ANA_CPUQ_CFG_CPUQ_MLD
- ANA_CPUQ_CFG_CPUQ_MLD_M
- ANA_CPUQ_CFG_CPUQ_MLD_X
- ANA_CPUQ_CFG_CPUQ_SFLOW
- ANA_CPUQ_CFG_CPUQ_SFLOW_M
- ANA_CPUQ_CFG_CPUQ_SRC_COPY
- ANA_CPUQ_CFG_CPUQ_SRC_COPY_M
- ANA_CPUQ_CFG_CPUQ_SRC_COPY_X
- ANA_CTL
- ANA_CUT_THRU_CFG
- ANA_CUT_THRU_CFG_RSZ
- ANA_DISCARD_CFG
- ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0
- ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA
- ANA_DISCARD_CFG_DROP_TAGGING_ISDX0
- ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA
- ANA_DSCP_CFG
- ANA_DSCP_CFG_DP_DSCP_VAL
- ANA_DSCP_CFG_DSCP_REWR_ENA
- ANA_DSCP_CFG_DSCP_TRANSLATE_VAL
- ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M
- ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X
- ANA_DSCP_CFG_DSCP_TRUST_ENA
- ANA_DSCP_CFG_QOS_DSCP_VAL
- ANA_DSCP_CFG_QOS_DSCP_VAL_M
- ANA_DSCP_CFG_QOS_DSCP_VAL_X
- ANA_DSCP_CFG_RSZ
- ANA_DSCP_REWR_CFG
- ANA_DSCP_REWR_CFG_RSZ
- ANA_EMIRRORPORTS
- ANA_EQ_EYE_CTRL_SIGNAL1
- ANA_EQ_EYE_CTRL_SIGNAL4
- ANA_EQ_EYE_CTRL_SIGNAL5
- ANA_FID_CFG
- ANA_FID_CFG_VID_MC_ENA
- ANA_FID_MAP_FID_MAP
- ANA_FID_MAP_FID_MAP_FID_B_VAL
- ANA_FID_MAP_FID_MAP_FID_B_VAL_M
- ANA_FID_MAP_FID_MAP_FID_C_VAL
- ANA_FID_MAP_FID_MAP_FID_C_VAL_M
- ANA_FID_MAP_FID_MAP_FID_C_VAL_X
- ANA_FID_MAP_FID_MAP_RSZ
- ANA_FLOODING
- ANA_FLOODING_FLD_BROADCAST
- ANA_FLOODING_FLD_BROADCAST_M
- ANA_FLOODING_FLD_BROADCAST_X
- ANA_FLOODING_FLD_MULTICAST
- ANA_FLOODING_FLD_MULTICAST_M
- ANA_FLOODING_FLD_UNICAST
- ANA_FLOODING_FLD_UNICAST_M
- ANA_FLOODING_FLD_UNICAST_X
- ANA_FLOODING_IPMC
- ANA_FLOODING_IPMC_FLD_MC4_CTRL
- ANA_FLOODING_IPMC_FLD_MC4_CTRL_M
- ANA_FLOODING_IPMC_FLD_MC4_CTRL_X
- ANA_FLOODING_IPMC_FLD_MC4_DATA
- ANA_FLOODING_IPMC_FLD_MC4_DATA_M
- ANA_FLOODING_IPMC_FLD_MC4_DATA_X
- ANA_FLOODING_IPMC_FLD_MC6_CTRL
- ANA_FLOODING_IPMC_FLD_MC6_CTRL_M
- ANA_FLOODING_IPMC_FLD_MC6_CTRL_X
- ANA_FLOODING_IPMC_FLD_MC6_DATA
- ANA_FLOODING_IPMC_FLD_MC6_DATA_M
- ANA_FLOODING_RSZ
- ANA_IN
- ANA_IPT_IPT
- ANA_IPT_IPT_GSZ
- ANA_IPT_IPT_IPT_CFG
- ANA_IPT_IPT_IPT_CFG_M
- ANA_IPT_IPT_IPT_CFG_X
- ANA_IPT_IPT_ISDX_P
- ANA_IPT_IPT_ISDX_P_M
- ANA_IPT_IPT_ISDX_P_X
- ANA_IPT_IPT_PPT_IDX
- ANA_IPT_IPT_PPT_IDX_M
- ANA_IPT_OAM_MEP_CFG
- ANA_IPT_OAM_MEP_CFG_GSZ
- ANA_IPT_OAM_MEP_CFG_MEP_IDX
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_M
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_P
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X
- ANA_IPT_OAM_MEP_CFG_MEP_IDX_X
- ANA_ISOLATED_PORTS
- ANA_LEARNDISC
- ANA_MACTOPTIONS
- ANA_MACTOPTIONS_REDUCED_TABLE
- ANA_MACTOPTIONS_SHADOW
- ANA_MIRRORPORTS
- ANA_MISC1
- ANA_MSTI_STATE
- ANA_MSTI_STATE_RSZ
- ANA_OAM_UPM_LM_CNT
- ANA_OAM_UPM_LM_CNT_RSZ
- ANA_OUT
- ANA_PFC_PFC_CFG
- ANA_PFC_PFC_CFG_FC_LINK_SPEED
- ANA_PFC_PFC_CFG_FC_LINK_SPEED_M
- ANA_PFC_PFC_CFG_GSZ
- ANA_PFC_PFC_CFG_RX_PFC_ENA
- ANA_PFC_PFC_CFG_RX_PFC_ENA_M
- ANA_PFC_PFC_CFG_RX_PFC_ENA_X
- ANA_PFC_PFC_TIMER
- ANA_PFC_PFC_TIMER_GSZ
- ANA_PFC_PFC_TIMER_RSZ
- ANA_PGID_PGID
- ANA_PGID_PGID_CPUQ_DST_PGID
- ANA_PGID_PGID_CPUQ_DST_PGID_M
- ANA_PGID_PGID_CPUQ_DST_PGID_X
- ANA_PGID_PGID_PGID
- ANA_PGID_PGID_PGID_M
- ANA_PGID_PGID_RSZ
- ANA_POL_CIR_CFG
- ANA_POL_CIR_CFG_CIR_BURST
- ANA_POL_CIR_CFG_CIR_BURST_M
- ANA_POL_CIR_CFG_CIR_RATE
- ANA_POL_CIR_CFG_CIR_RATE_M
- ANA_POL_CIR_CFG_CIR_RATE_X
- ANA_POL_CIR_CFG_GSZ
- ANA_POL_CIR_STATE
- ANA_POL_CIR_STATE_GSZ
- ANA_POL_FLOWC
- ANA_POL_FLOWC_POL_FLOWC
- ANA_POL_FLOWC_RSZ
- ANA_POL_HYST
- ANA_POL_HYST_POL_FC_HYST
- ANA_POL_HYST_POL_FC_HYST_M
- ANA_POL_HYST_POL_FC_HYST_X
- ANA_POL_HYST_POL_STOP_HYST
- ANA_POL_HYST_POL_STOP_HYST_M
- ANA_POL_MISC_CFG
- ANA_POL_MISC_CFG_POL_CLOSE_ALL
- ANA_POL_MISC_CFG_POL_LEAK_DIS
- ANA_POL_MODE_CFG
- ANA_POL_MODE_CFG_CIR_ENA
- ANA_POL_MODE_CFG_DLB_COUPLED
- ANA_POL_MODE_CFG_FRM_MODE
- ANA_POL_MODE_CFG_FRM_MODE_M
- ANA_POL_MODE_CFG_FRM_MODE_X
- ANA_POL_MODE_CFG_GSZ
- ANA_POL_MODE_CFG_IPG_SIZE
- ANA_POL_MODE_CFG_IPG_SIZE_M
- ANA_POL_MODE_CFG_IPG_SIZE_X
- ANA_POL_MODE_CFG_OVERSHOOT_ENA
- ANA_POL_PIR_CFG
- ANA_POL_PIR_CFG_GSZ
- ANA_POL_PIR_CFG_PIR_BURST
- ANA_POL_PIR_CFG_PIR_BURST_M
- ANA_POL_PIR_CFG_PIR_RATE
- ANA_POL_PIR_CFG_PIR_RATE_M
- ANA_POL_PIR_CFG_PIR_RATE_X
- ANA_POL_PIR_STATE
- ANA_POL_PIR_STATE_GSZ
- ANA_POL_STATE
- ANA_POL_STATE_GSZ
- ANA_PORT_B_DOMAIN
- ANA_PORT_CPU_FWD_BPDU_CFG
- ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA
- ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M
- ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X
- ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA
- ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M
- ANA_PORT_CPU_FWD_BPDU_CFG_GSZ
- ANA_PORT_CPU_FWD_CCM_CFG
- ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA
- ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M
- ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X
- ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA
- ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M
- ANA_PORT_CPU_FWD_CCM_CFG_GSZ
- ANA_PORT_CPU_FWD_CFG
- ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA
- ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA
- ANA_PORT_CPU_FWD_CFG_GSZ
- ANA_PORT_CPU_FWD_GARP_CFG
- ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA
- ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M
- ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X
- ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA
- ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M
- ANA_PORT_CPU_FWD_GARP_CFG_GSZ
- ANA_PORT_DROP_CFG
- ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA
- ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA
- ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA
- ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA
- ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA
- ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA
- ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA
- ANA_PORT_DROP_CFG_GSZ
- ANA_PORT_MODE
- ANA_PORT_MODE_L3_PARSE_CFG
- ANA_PORT_MODE_REDTAG_PARSE_CFG
- ANA_PORT_MODE_RSZ
- ANA_PORT_MODE_VLAN_PARSE_CFG
- ANA_PORT_MODE_VLAN_PARSE_CFG_M
- ANA_PORT_MODE_VLAN_PARSE_CFG_X
- ANA_PORT_PCP_DEI_MAP
- ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL
- ANA_PORT_PCP_DEI_MAP_GSZ
- ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL
- ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M
- ANA_PORT_PCP_DEI_MAP_RSZ
- ANA_PORT_POL_CFG
- ANA_PORT_POL_CFG_GSZ
- ANA_PORT_POL_CFG_POL_CPU_REDIR_8021
- ANA_PORT_POL_CFG_POL_CPU_REDIR_IP
- ANA_PORT_POL_CFG_POL_ORDER
- ANA_PORT_POL_CFG_POL_ORDER_M
- ANA_PORT_POL_CFG_PORT_POL_ENA
- ANA_PORT_POL_CFG_QUEUE_POL_ENA
- ANA_PORT_POL_CFG_QUEUE_POL_ENA_M
- ANA_PORT_POL_CFG_QUEUE_POL_ENA_X
- ANA_PORT_PORT_CFG
- ANA_PORT_PORT_CFG_GSZ
- ANA_PORT_PORT_CFG_LEARNAUTO
- ANA_PORT_PORT_CFG_LEARNCPU
- ANA_PORT_PORT_CFG_LEARNDROP
- ANA_PORT_PORT_CFG_LEARN_ENA
- ANA_PORT_PORT_CFG_LIMIT_CPU
- ANA_PORT_PORT_CFG_LIMIT_DROP
- ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU
- ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP
- ANA_PORT_PORT_CFG_LSR_MODE
- ANA_PORT_PORT_CFG_PORTID_VAL
- ANA_PORT_PORT_CFG_PORTID_VAL_M
- ANA_PORT_PORT_CFG_PORTID_VAL_X
- ANA_PORT_PORT_CFG_RECV_ENA
- ANA_PORT_PORT_CFG_SRC_MIRROR_ENA
- ANA_PORT_PORT_CFG_USE_B_DOM_TBL
- ANA_PORT_PTP_CFG
- ANA_PORT_PTP_CFG_GSZ
- ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE
- ANA_PORT_PTP_DLY1_CFG
- ANA_PORT_PTP_DLY1_CFG_GSZ
- ANA_PORT_PTP_DLY2_CFG
- ANA_PORT_PTP_DLY2_CFG_GSZ
- ANA_PORT_QOS_CFG
- ANA_PORT_QOS_CFG_DP_DEFAULT_VAL
- ANA_PORT_QOS_CFG_DSCP_REWR_CFG
- ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M
- ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA
- ANA_PORT_QOS_CFG_GSZ
- ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL
- ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M
- ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X
- ANA_PORT_QOS_CFG_QOS_DSCP_ENA
- ANA_PORT_QOS_CFG_QOS_PCP_ENA
- ANA_PORT_SFID_CFG
- ANA_PORT_SFID_CFG_GSZ
- ANA_PORT_SFID_CFG_RSZ
- ANA_PORT_SFID_CFG_SFID
- ANA_PORT_SFID_CFG_SFID_M
- ANA_PORT_SFID_CFG_SFID_VALID
- ANA_PORT_VCAP_CFG
- ANA_PORT_VCAP_CFG_GSZ
- ANA_PORT_VCAP_CFG_PAG_VAL
- ANA_PORT_VCAP_CFG_PAG_VAL_M
- ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA
- ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M
- ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X
- ANA_PORT_VCAP_CFG_S1_ENA
- ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA
- ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M
- ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X
- ANA_PORT_VCAP_S1_KEY_CFG
- ANA_PORT_VCAP_S1_KEY_CFG_GSZ
- ANA_PORT_VCAP_S1_KEY_CFG_RSZ
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG
- ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M
- ANA_PORT_VCAP_S2_CFG
- ANA_PORT_VCAP_S2_CFG_GSZ
- ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS
- ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M
- ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X
- ANA_PORT_VCAP_S2_CFG_S2_ENA
- ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA
- ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M
- ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X
- ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG
- ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M
- ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X
- ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS
- ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M
- ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X
- ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS
- ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M
- ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X
- ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS
- ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M
- ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS
- ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M
- ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X
- ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA
- ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M
- ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X
- ANA_PORT_VLAN_CFG
- ANA_PORT_VLAN_CFG_GSZ
- ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
- ANA_PORT_VLAN_CFG_VLAN_DEI
- ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA
- ANA_PORT_VLAN_CFG_VLAN_PCP
- ANA_PORT_VLAN_CFG_VLAN_PCP_M
- ANA_PORT_VLAN_CFG_VLAN_PCP_X
- ANA_PORT_VLAN_CFG_VLAN_POP_CNT
- ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M
- ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X
- ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE
- ANA_PORT_VLAN_CFG_VLAN_VID
- ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX
- ANA_PORT_VLAN_CFG_VLAN_VID_M
- ANA_PPT_PPT
- ANA_PPT_PPT_RSZ
- ANA_PWR_DOWN
- ANA_PWR_UP
- ANA_RG_CTRL_SIGNAL1
- ANA_RG_CTRL_SIGNAL4
- ANA_RG_CTRL_SIGNAL6
- ANA_SFLOW_CFG
- ANA_SFLOW_CFG_RSZ
- ANA_SFLOW_CFG_SF_RATE
- ANA_SFLOW_CFG_SF_RATE_M
- ANA_SFLOW_CFG_SF_RATE_X
- ANA_SFLOW_CFG_SF_SAMPLE_RX
- ANA_SFLOW_CFG_SF_SAMPLE_TX
- ANA_SG_ACCESS_CTRL
- ANA_SG_ACCESS_CTRL_CONFIG_CHANGE
- ANA_SG_ACCESS_CTRL_SGID
- ANA_SG_ACCESS_CTRL_SGID_M
- ANA_SG_CONFIG_REG_1
- ANA_SG_CONFIG_REG_2
- ANA_SG_CONFIG_REG_3
- ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB
- ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M
- ANA_SG_CONFIG_REG_3_GATE_ENABLE
- ANA_SG_CONFIG_REG_3_INIT_GATE_STATE
- ANA_SG_CONFIG_REG_3_INIT_IPS
- ANA_SG_CONFIG_REG_3_INIT_IPS_M
- ANA_SG_CONFIG_REG_3_INIT_IPS_X
- ANA_SG_CONFIG_REG_3_LIST_LENGTH
- ANA_SG_CONFIG_REG_3_LIST_LENGTH_M
- ANA_SG_CONFIG_REG_3_LIST_LENGTH_X
- ANA_SG_CONFIG_REG_4
- ANA_SG_CONFIG_REG_5
- ANA_SG_GCL_GS_CONFIG
- ANA_SG_GCL_GS_CONFIG_GATE_STATE
- ANA_SG_GCL_GS_CONFIG_IPS
- ANA_SG_GCL_GS_CONFIG_IPS_M
- ANA_SG_GCL_GS_CONFIG_RSZ
- ANA_SG_GCL_TI_CONFIG
- ANA_SG_GCL_TI_CONFIG_RSZ
- ANA_SG_STATUS_REG_1
- ANA_SG_STATUS_REG_2
- ANA_SG_STATUS_REG_3
- ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB
- ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M
- ANA_SG_STATUS_REG_3_CONFIG_PENDING
- ANA_SG_STATUS_REG_3_GATE_STATE
- ANA_SG_STATUS_REG_3_IPS
- ANA_SG_STATUS_REG_3_IPS_M
- ANA_SG_STATUS_REG_3_IPS_X
- ANA_STORMLIMIT_BURST
- ANA_STORMLIMIT_CFG
- ANA_STORMLIMIT_CFG_RSZ
- ANA_STORMLIMIT_CFG_STORM_MODE
- ANA_STORMLIMIT_CFG_STORM_MODE_M
- ANA_STORMLIMIT_CFG_STORM_RATE
- ANA_STORMLIMIT_CFG_STORM_RATE_M
- ANA_STORMLIMIT_CFG_STORM_RATE_X
- ANA_STORMLIMIT_CFG_STORM_UNIT
- ANA_TABLES_ANMOVED
- ANA_TABLES_ENTRYLIM
- ANA_TABLES_ENTRYLIM_ENTRYLIM
- ANA_TABLES_ENTRYLIM_ENTRYLIM_M
- ANA_TABLES_ENTRYLIM_ENTRYLIM_X
- ANA_TABLES_ENTRYLIM_ENTRYSTAT
- ANA_TABLES_ENTRYLIM_ENTRYSTAT_M
- ANA_TABLES_ENTRYLIM_RSZ
- ANA_TABLES_ISDXACCESS
- ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK
- ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M
- ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X
- ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD
- ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M
- ANA_TABLES_ISDXTIDX
- ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA
- ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA
- ANA_TABLES_ISDXTIDX_ISDX_INDEX
- ANA_TABLES_ISDXTIDX_ISDX_INDEX_M
- ANA_TABLES_ISDXTIDX_ISDX_MSTI
- ANA_TABLES_ISDXTIDX_ISDX_MSTI_M
- ANA_TABLES_ISDXTIDX_ISDX_MSTI_X
- ANA_TABLES_ISDXTIDX_ISDX_SDLBI
- ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M
- ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X
- ANA_TABLES_MACACCESS
- ANA_TABLES_MACACCESS_AGED_FLAG
- ANA_TABLES_MACACCESS_B_DOM
- ANA_TABLES_MACACCESS_DEST_IDX
- ANA_TABLES_MACACCESS_DEST_IDX_M
- ANA_TABLES_MACACCESS_DEST_IDX_X
- ANA_TABLES_MACACCESS_ENTRYTYPE
- ANA_TABLES_MACACCESS_ENTRYTYPE_M
- ANA_TABLES_MACACCESS_ENTRYTYPE_X
- ANA_TABLES_MACACCESS_IGNORE_VLAN
- ANA_TABLES_MACACCESS_MAC_CPU_COPY
- ANA_TABLES_MACACCESS_MAC_TABLE_CMD
- ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M
- ANA_TABLES_MACACCESS_SRC_KILL
- ANA_TABLES_MACACCESS_VALID
- ANA_TABLES_MACHDATA
- ANA_TABLES_MACHDATA_MACHDATA
- ANA_TABLES_MACHDATA_MACHDATA_M
- ANA_TABLES_MACHDATA_VID
- ANA_TABLES_MACHDATA_VID_M
- ANA_TABLES_MACHDATA_VID_X
- ANA_TABLES_MACLDATA
- ANA_TABLES_MACTINDX
- ANA_TABLES_MACTINDX_BUCKET
- ANA_TABLES_MACTINDX_M_INDEX
- ANA_TABLES_PTP_ID_HIGH
- ANA_TABLES_PTP_ID_LOW
- ANA_TABLES_SEQ_HISTORY
- ANA_TABLES_SEQ_MASK
- ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK
- ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M
- ANA_TABLES_SEQ_MASK_SPLIT_MASK
- ANA_TABLES_SEQ_MASK_SPLIT_MASK_M
- ANA_TABLES_SEQ_MASK_SPLIT_MASK_X
- ANA_TABLES_SFIDACCESS
- ANA_TABLES_SFIDACCESS_FORCE_BLOCK
- ANA_TABLES_SFIDACCESS_IGR_PRIO
- ANA_TABLES_SFIDACCESS_IGR_PRIO_M
- ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA
- ANA_TABLES_SFIDACCESS_IGR_PRIO_X
- ANA_TABLES_SFIDACCESS_MAX_SDU_LEN
- ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M
- ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X
- ANA_TABLES_SFIDACCESS_SFID_TBL_CMD
- ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M
- ANA_TABLES_SFIDTIDX
- ANA_TABLES_SFIDTIDX_POL_ENA
- ANA_TABLES_SFIDTIDX_POL_IDX
- ANA_TABLES_SFIDTIDX_POL_IDX_M
- ANA_TABLES_SFIDTIDX_POL_IDX_X
- ANA_TABLES_SFIDTIDX_SFID_INDEX
- ANA_TABLES_SFIDTIDX_SFID_INDEX_M
- ANA_TABLES_SFIDTIDX_SGID
- ANA_TABLES_SFIDTIDX_SGID_M
- ANA_TABLES_SFIDTIDX_SGID_VALID
- ANA_TABLES_SFIDTIDX_SGID_X
- ANA_TABLES_SFID_MASK
- ANA_TABLES_SFID_MASK_IGR_PORT_MASK
- ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M
- ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X
- ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA
- ANA_TABLES_STREAMACCESS
- ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM
- ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M
- ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X
- ANA_TABLES_STREAMACCESS_GEN_REC_TYPE
- ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA
- ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD
- ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M
- ANA_TABLES_STREAMDATA
- ANA_TABLES_STREAMDATA_SFID
- ANA_TABLES_STREAMDATA_SFID_M
- ANA_TABLES_STREAMDATA_SFID_VALID
- ANA_TABLES_STREAMDATA_SSID
- ANA_TABLES_STREAMDATA_SSID_M
- ANA_TABLES_STREAMDATA_SSID_VALID
- ANA_TABLES_STREAMDATA_SSID_X
- ANA_TABLES_STREAMTIDX
- ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR
- ANA_TABLES_STREAMTIDX_REDTAG_POP
- ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE
- ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS
- ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M
- ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X
- ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN
- ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M
- ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X
- ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2
- ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M
- ANA_TABLES_STREAMTIDX_STREAM_SPLIT
- ANA_TABLES_STREAMTIDX_S_INDEX
- ANA_TABLES_STREAMTIDX_S_INDEX_M
- ANA_TABLES_STREAMTIDX_S_INDEX_X
- ANA_TABLES_VLANACCESS
- ANA_TABLES_VLANACCESS_CMD_IDLE
- ANA_TABLES_VLANACCESS_CMD_INIT
- ANA_TABLES_VLANACCESS_CMD_WRITE
- ANA_TABLES_VLANACCESS_VLAN_PORT_MASK
- ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M
- ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X
- ANA_TABLES_VLANACCESS_VLAN_TBL_CMD
- ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M
- ANA_TABLES_VLANTIDX
- ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS
- ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED
- ANA_TABLES_VLANTIDX_VLAN_MIRROR
- ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN
- ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA
- ANA_TABLES_VLANTIDX_VLAN_SRC_CHK
- ANA_TABLES_VLANTIDX_V_INDEX
- ANA_TABLES_VLANTIDX_V_INDEX_M
- ANA_TEST_DC_CTRL
- ANA_VCAP_RNG_TYPE_CFG
- ANA_VCAP_RNG_TYPE_CFG_RSZ
- ANA_VCAP_RNG_VAL_CFG
- ANA_VCAP_RNG_VAL_CFG_RSZ
- ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL
- ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M
- ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL
- ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M
- ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X
- ANA_VLANMASK
- ANA_VRAP_CFG
- ANA_VRAP_CFG_VRAP_VID
- ANA_VRAP_CFG_VRAP_VID_M
- ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA
- ANA_VRAP_HDR_DATA
- ANA_VRAP_HDR_MASK
- ANAdvertise
- ANC0_CANVAS_ADDR
- ANCHOR
- ANCHOR_LEVEL
- ANCHOR_LOAD_EXTERNAL
- ANCHOR_LOAD_FPGA
- ANCHOR_LOAD_INTERNAL
- ANCHOR_MIN_LEVEL
- ANCHOR_NUM_LEVELS
- ANCHOR_NUM_PRIOS
- ANCHOR_PRIO
- ANCHOR_SIZE
- ANCStatus
- ANC_ACTIVE
- ANC_APPLY_FIR
- ANC_APPLY_FIR_IIR
- ANC_APPLY_IIR
- ANC_BYPASS
- ANC_FIR_CONFIGURED
- ANC_FIR_IIR_CONFIGURED
- ANC_IIR_CONFIGURED
- ANC_OFF
- ANC_STANDBY
- ANC_UNCONFIGURED
- ANCtrl
- AND
- ANDCC
- ANDCM
- ANDONE
- ANDROID_BOOT_DEV_MAX
- ANDROID_WIFI_CMD
- ANDROID_WIFI_CMD_BLOCK
- ANDROID_WIFI_CMD_BTCOEXMODE
- ANDROID_WIFI_CMD_BTCOEXSCAN_START
- ANDROID_WIFI_CMD_BTCOEXSCAN_STOP
- ANDROID_WIFI_CMD_COUNTRY
- ANDROID_WIFI_CMD_GETBAND
- ANDROID_WIFI_CMD_LINKSPEED
- ANDROID_WIFI_CMD_MACADDR
- ANDROID_WIFI_CMD_MAX
- ANDROID_WIFI_CMD_P2P_DEV_ADDR
- ANDROID_WIFI_CMD_P2P_GET_NOA
- ANDROID_WIFI_CMD_P2P_SET_NOA
- ANDROID_WIFI_CMD_P2P_SET_PS
- ANDROID_WIFI_CMD_RSSI
- ANDROID_WIFI_CMD_RXFILTER_ADD
- ANDROID_WIFI_CMD_RXFILTER_REMOVE
- ANDROID_WIFI_CMD_RXFILTER_START
- ANDROID_WIFI_CMD_RXFILTER_STOP
- ANDROID_WIFI_CMD_SCAN_ACTIVE
- ANDROID_WIFI_CMD_SCAN_PASSIVE
- ANDROID_WIFI_CMD_SETBAND
- ANDROID_WIFI_CMD_SETFWPATH
- ANDROID_WIFI_CMD_SETSUSPENDOPT
- ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE
- ANDROID_WIFI_CMD_START
- ANDROID_WIFI_CMD_STOP
- ANDROID_WIFI_CMD_WFD_DISABLE
- ANDROID_WIFI_CMD_WFD_ENABLE
- ANDROID_WIFI_CMD_WFD_SET_DEVTYPE
- ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT
- ANDROID_WIFI_CMD_WFD_SET_TCPPORT
- ANEG_CFG_ACK
- ANEG_CFG_FD
- ANEG_CFG_HD
- ANEG_CFG_INVAL
- ANEG_CFG_NP
- ANEG_CFG_PS1
- ANEG_CFG_PS2
- ANEG_CFG_RF1
- ANEG_CFG_RF2
- ANEG_DONE
- ANEG_FAILED
- ANEG_MULTIGBT_AN_CTRL
- ANEG_OK
- ANEG_STATE_ABILITY_DETECT
- ANEG_STATE_ABILITY_DETECT_INIT
- ANEG_STATE_ACK_DETECT
- ANEG_STATE_ACK_DETECT_INIT
- ANEG_STATE_AN_ENABLE
- ANEG_STATE_COMPLETE_ACK
- ANEG_STATE_COMPLETE_ACK_INIT
- ANEG_STATE_DISABLE_LINK_OK
- ANEG_STATE_IDLE_DETECT
- ANEG_STATE_IDLE_DETECT_INIT
- ANEG_STATE_LINK_OK
- ANEG_STATE_NEXT_PAGE_WAIT
- ANEG_STATE_NEXT_PAGE_WAIT_INIT
- ANEG_STATE_RESTART
- ANEG_STATE_RESTART_INIT
- ANEG_STATE_SETTLE_TIME
- ANEG_STATE_UNKNOWN
- ANEG_TIMER_ENAB
- ANEN
- ANEROCR
- ANEWDATA
- ANGELX_CD0_IRQ
- ANGELX_CD1_IRQ
- ANGELX_IRQ_BASE
- ANGELX_RDY0_IRQ
- ANGELX_RDY1_IRQ
- ANGELX_ST0_IRQ
- ANGELX_ST1_IRQ
- ANH
- ANI_H
- ANLG_ON
- ANLP
- ANLinkPartnerAbility
- ANNEXA
- ANNEXB
- ANNOTATE_IGNORE_ALTERNATIVE
- ANNOTATE_NOSPEC_ALTERNATIVE
- ANNOTATE_RETPOLINE_SAFE
- ANNOTATION__AVG_IPC_WIDTH
- ANNOTATION__CFG
- ANNOTATION__CYCLES_WIDTH
- ANNOTATION__IPC_WIDTH
- ANNOTATION__MAX_OFFSET_LEVEL
- ANNOTATION__MINMAX_CYCLES_WIDTH
- ANNOTATION__MIN_OFFSET_LEVEL
- ANNOTATION__OFFSET_CALL
- ANNOTATION__OFFSET_JUMP_TARGETS
- ANNUL
- ANNUL_BIT
- ANN_COL__LINE
- ANN_COL__OFFSET
- ANN_COL__PERCENT
- ANOBJ_ALLOCATED_BUFFER
- ANOBJ_EVALUATED
- ANOBJ_IS_EXTERNAL
- ANOBJ_IS_REFERENCED
- ANOBJ_METHOD_ARG
- ANOBJ_METHOD_LOCAL
- ANOBJ_METHOD_NO_RETVAL
- ANOBJ_METHOD_SOME_NO_RETVAL
- ANOBJ_NODE_EARLY_INIT
- ANOBJ_RESERVED
- ANOBJ_SUBTREE_HAS_INI
- ANOBJ_TEMPORARY
- ANODE_ALLOC_FWD
- ANODE_MAGIC
- ANODE_RD_AHEAD
- ANON_EXPECTED_IOCTLS
- ANON_INODE_FS_MAGIC
- ANON_VAL1
- ANON_VAL2
- ANOTHER_MSG_TYPE
- ANOTHER_TEST_STRING
- ANPWRDOWN
- ANS
- ANSEL_REG
- ANSI_PROTOTYPES
- ANSI_SCSI2
- ANSLCD_ADDR
- ANSLCD_CLEAR
- ANSLCD_CTRL_IX
- ANSLCD_DATA_IX
- ANSLCD_MINOR
- ANSLCD_SENDCTRL
- ANSLCD_SETLONGDELAY
- ANSLCD_SETSHORTDELAY
- ANSONIC_AF9005
- ANS_ACK
- ANS_ADET
- ANS_ANTENNA_A
- ANS_ANTENNA_B
- ANS_ANTENNA_MAX
- ANS_CACK
- ANS_FINISH_WAIT
- ANS_LCHK
- ANS_NDIS
- ANS_NWOK
- ANS_SUSPECT
- ANS_TDIS
- ANStatus
- ANTCFG_NONE
- ANTCNT
- ANTENNADIVERSITYVALUE
- ANTENNA_A
- ANTENNA_AB
- ANTENNA_ABC
- ANTENNA_ABCD
- ANTENNA_ABD
- ANTENNA_AC
- ANTENNA_ACD
- ANTENNA_AD
- ANTENNA_B
- ANTENNA_BC
- ANTENNA_BCD
- ANTENNA_BD
- ANTENNA_C
- ANTENNA_CD
- ANTENNA_D
- ANTENNA_DIVERSITY_SELECTION
- ANTENNA_DIVERSITY_VALUE
- ANTENNA_HW_DIVERSITY
- ANTENNA_MASK_VALUE
- ANTENNA_MODE_SAMPLE
- ANTENNA_NONE
- ANTENNA_PATH
- ANTENNA_RX_DIVERSITY
- ANTENNA_SEL_INT
- ANTENNA_SEL_TYPE
- ANTENNA_SEL_UFL
- ANTENNA_SW_DIVERSITY
- ANTENNA_TX_DIVERSITY
- ANTSEL_2x3
- ANTSEL_2x4
- ANTSEL_A
- ANTSEL_B
- ANTSEL_CLKDIV_4MHZ
- ANTSEL_NA
- ANTSWAP_AB
- ANTSWITCH_NONE
- ANTSWITCH_TYPE_1
- ANTSWITCH_TYPE_2
- ANTSWITCH_TYPE_3
- ANTTESTA
- ANTTESTALL
- ANTTESTB
- ANT_A
- ANT_AB
- ANT_ABC
- ANT_AC
- ANT_ALT
- ANT_AUX
- ANT_B
- ANT_BC
- ANT_C
- ANT_DETECTED_INFO
- ANT_DETECT_BY_RSSI
- ANT_DETECT_BY_SINGLE_TONE
- ANT_DIVERSITY
- ANT_DIVERSITY_BITMASK
- ANT_DIV_TYPE_E
- ANT_EXT_TWEAK
- ANT_HUNT_SLEEP
- ANT_INVALID
- ANT_LNA_INC
- ANT_MAIN
- ANT_NONE
- ANT_PATH_AUTO
- ANT_PATH_EXTERNAL
- ANT_PATH_INTERNAL
- ANT_RXA
- ANT_RXB
- ANT_RXD_TXA
- ANT_RXD_TXB
- ANT_RX_DIV_DEF
- ANT_RX_DIV_ENABLE
- ANT_RX_DIV_FORCE_0
- ANT_RX_DIV_FORCE_1
- ANT_RX_DIV_START_0
- ANT_RX_DIV_START_1
- ANT_SELCFG_AUTO
- ANT_SELCFG_DEF_2x2
- ANT_SELCFG_DEF_2x3
- ANT_SELCFG_DEF_2x4
- ANT_SELCFG_MASK
- ANT_SELCFG_MAX
- ANT_SELCFG_NUM_2x3
- ANT_SELCFG_NUM_2x4
- ANT_SELCFG_RX_DEF
- ANT_SELCFG_RX_UNICAST
- ANT_SELCFG_TX_DEF
- ANT_SELCFG_TX_UNICAST
- ANT_SELECT_WK_CID
- ANT_SEL_FRAME
- ANT_STAT_INC
- ANT_SWCTRL_TBL_REV3_IDX
- ANT_TXA
- ANT_TXB
- ANT_TX_DEF
- ANT_TX_FORCE_0
- ANT_TX_FORCE_1
- ANT_TX_LAST_RX
- ANT_UNKNOWN
- ANT_X1
- ANT_X2
- ANUBIS_BLOCK_SIZE
- ANUBIS_CTRL1_NANDSEL
- ANUBIS_IDEPRI
- ANUBIS_IDEPRIAUX
- ANUBIS_IDESEC
- ANUBIS_IDESECAUX
- ANUBIS_IDREG_REVMASK
- ANUBIS_IOADDR
- ANUBIS_IRQ_ASIX
- ANUBIS_IRQ_IDE0
- ANUBIS_IRQ_IDE1
- ANUBIS_MAX_KEY_SIZE
- ANUBIS_MAX_N
- ANUBIS_MAX_ROUNDS
- ANUBIS_MIN_KEY_SIZE
- ANUBIS_PA_CPLD
- ANUBIS_PA_CTRL1
- ANUBIS_PA_IDREG
- ANUBIS_VA_CTRL1
- ANUBIS_VA_IDREG
- ANW6410_EN_DM9000
- ANW6410_EN_LCD
- ANW6410_PA_DM9000
- ANW6410_PA_EXTDEV
- ANW6410_VA_EXTDEV
- ANXchngCtrl
- ANY
- ANYCAST_ADDR
- ANYDATA_PRODUCT_ADU_500A
- ANYDATA_PRODUCT_ADU_620UW
- ANYDATA_PRODUCT_ADU_E100A
- ANYDATA_VENDOR_ID
- ANYINTR
- ANYSEE_HW_507CD
- ANYSEE_HW_507DC
- ANYSEE_HW_507FA
- ANYSEE_HW_507SI
- ANYSEE_HW_507T
- ANYSEE_HW_508PS2
- ANYSEE_HW_508PTC
- ANYSEE_HW_508S2
- ANYSEE_HW_508T2C
- ANYSEE_HW_508TC
- ANYSEE_I2C_CLIENT_MAX
- ANYSIGNAL
- ANYSINT_MAX
- ANY_BOARD_ID
- ANY_CAPTURE_IRQ
- ANY_EXIT_TO_ANY_INIT
- ANY_GROUP
- ANY_ID
- ANY_INIT_TO_ANY_EXIT
- ANY_ISA_DMA
- ANY_PHASE_ID
- ANY_PLAYBACK_IRQ
- ANY_PROC_ID
- ANY_RETURN_P
- ANY_S5933_INT
- ANY_S593X_INT
- ANY_SSID_FLAG
- AN_CLK
- AN_COMPLETE
- AN_ENABLE
- AN_FALLBACK_AN
- AN_FALLBACK_CRC
- AN_FALLBACK_IE
- AN_PKT_SIZE
- AN_REF_CLK
- AN_REF_RST
- AN_RETRY_COUNT
- AN_RST
- AN_TYPE_LEN
- AN_TYPE_TYPE_LBN
- AN_TYPE_TYPE_LEN
- AN_TYPE_TYPE_OFST
- AN_TYPE_TYPE_WIDTH
- AOA_NOTIFY_HEADPHONE
- AOA_NOTIFY_LINE_IN
- AOA_NOTIFY_LINE_OUT
- AOB_NR_MSB
- AOEAFL_ASYNC
- AOEAFL_DEV
- AOEAFL_EXT
- AOEAFL_WRITE
- AOECCMD_FSET
- AOECCMD_PTEST
- AOECCMD_READ
- AOECCMD_SET
- AOECCMD_TEST
- AOECMD_ATA
- AOECMD_CFG
- AOECMD_VEND_MIN
- AOEFL_ERR
- AOEFL_RSP
- AOE_HVER
- AOE_MAJOR
- AOE_PARTITIONS
- AOF_NO_ABTS
- AOLDDATA
- AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK
- AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT
- AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK
- AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT
- AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK
- AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT
- AON_CTRL_HOST_MISC_CMDS
- AON_CTRL_PM_CPU_WAIT_COUNT
- AON_CTRL_PM_CTRL
- AON_CTRL_PM_INITIATE
- AON_CTRL_PM_STATUS
- AON_CTRL_RAM_SIZE
- AON_CTRL_REG
- AON_CTRL_RESET_CTRL
- AON_CTRL_SYSTEM_DATA_RAM_OFS
- AON_MUX
- AON_MUX_FLAG
- AON_PIN
- AON_REG_CONTROL_HASH_LEN
- AON_REG_CONTROL_HIGH
- AON_REG_CONTROL_LOW
- AON_REG_MAGIC_FLAGS
- AON_REG_PANIC
- AON_REG_S3_HASH
- AON_RESERVED0
- AON_RESERVED1
- AON_RESERVED2
- AON_RESERVED3
- AON_RESERVED4
- AON_RESERVED5
- AON_RESERVED6
- AON_RESERVED7
- AON_RESET
- AON_SAVE_SRAM
- AON_SYS_CTRL_RESERVED1
- AON_VAL
- AOPEN_ATID_G
- AOPEN_ATID_M
- AOPEN_ATID_S
- AOPEN_STATUS_G
- AOPEN_STATUS_M
- AOPEN_STATUS_S
- AOPOBJ_AML_CONSTANT
- AOPOBJ_DATA_VALID
- AOPOBJ_INVALID
- AOPOBJ_OBJECT_INITIALIZED
- AOPOBJ_REG_CONNECTED
- AOPOBJ_SETUP_COMPLETE
- AOPOBJ_STATIC_POINTER
- AOP_FLAG_CONT_EXPAND
- AOP_FLAG_NOFS
- AOP_TRUNCATED_PAGE
- AOP_WRITEPAGE_ACTIVATE
- AOSS_CC_CAMSS_RESTART
- AOSS_CC_DISPSS_RESTART
- AOSS_CC_GPU_RESTART
- AOSS_CC_LPASS_RESTART
- AOSS_CC_MSS_RESTART
- AOSS_CC_VENUS_RESTART
- AOSS_CC_WCSS_RESTART
- AOSS_QMP_LS_CDSP
- AOSS_QMP_LS_LPASS
- AOSS_QMP_LS_MODEM
- AOSS_QMP_LS_SLPI
- AOSS_QMP_LS_SPSS
- AOSS_QMP_LS_VENUS
- AOUTENCTR0
- AOUTENCTR1
- AOUTENCTR2
- AOUTFADECTR0
- AOUTHDR
- AOUTHDRSZ
- AOUTHSZ
- AOUTLEN
- AOUTRSTCTR0
- AOUTRSTCTR1
- AOUTRSTCTR2
- AOUTSRCRSTCTR0
- AOUTSRCRSTCTR1
- AOUTSRCRSTCTR2
- AOUTSZ
- AOUT_16BIT
- AOUT_20BIT
- AOUT_24BIT
- AOUT_BNUM_SEL_MASK
- AOUT_BURST_PREAMBLE_EN
- AOUT_CRC_CONT
- AOUT_CRC_CONT_EN
- AOUT_CRC_DISABLE
- AOUT_CRC_ENABLE
- AOUT_CRC_NO_RESET
- AOUT_CRC_ONE_SHOT
- AOUT_CRC_RESET
- AOUT_CRC_SOFT_RESET
- AOUT_CRC_TEST_EN
- AOUT_DISABLE
- AOUT_EN
- AOUT_ENABLE
- AOUT_FIFO_ADAP_CTRL
- AOUT_FIFO_START_ADDR
- AOUT_FIFO_START_ADDR_2
- AOUT_FIFO_START_ADDR_3
- AOUT_FROM_REG
- AOUT_MAGIC
- AOUT_TEXT_OFFSET
- AOUT_TO_REG
- AO_ACPUSCUL2C
- AO_BBPHARQMEM
- AO_BELOW_REF_BIT
- AO_BUFFER_SIZE
- AO_CEC_CLK_CNTL_REG0
- AO_CEC_CLK_CNTL_REG1
- AO_CHAN_OFFSET
- AO_CLK_GATE0
- AO_CLK_GATE0_SP
- AO_CMD_STARTED
- AO_CODECISP
- AO_CONTROL_OFFSET
- AO_CRT_CLK_CNTL1
- AO_DMA_RING_COUNT
- AO_G3D
- AO_HIFI
- AO_MCPU
- AO_OSCIN_CNTL
- AO_RTC_ALT_CLK_CNTL0
- AO_RTC_ALT_CLK_CNTL1
- AO_RTI_GEN_CNTL_REG0
- AO_RTI_GEN_PWR_ISO0
- AO_RTI_GEN_PWR_SLEEP0
- AO_RTI_PWR_CNTL_REG0
- AO_RTI_PWR_CNTL_REG1
- AO_RTI_STATUS_REG3
- AO_SAR_CLK
- AO_SCTRL_CTRL3
- AO_SCTRL_SEL18
- AO_SEC_SD_CFG8
- AO_SEC_SOCINFO_OFFSET
- AO_SHIFT
- AO_STATUS_OFFSET
- AO_VALUE_OFFSET
- AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET
- AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET
- AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET
- AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET
- AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET
- AP806_CA72MP2_0_PLL_RATIO_STATE
- AP806_CA72MP2_0_PLL_SR_REG_OFFSET
- AP806_CLK_NUM
- AP806_CPUS_PER_CLUSTER
- AP806_CPU_CLUSTER0
- AP806_CPU_CLUSTER1
- AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK
- AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET
- AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK
- AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET
- AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET
- AP806_PLL_CR_CPU_CLK_DIV_RATIO
- AP806_SAR_CLKFREQ_MODE_MASK
- AP806_SAR_REG
- AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
- AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET
- AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET
- AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET
- AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET
- AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET
- AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK
- AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET
- AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK
- AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET
- AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET
- AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK
- AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET
- AP807_PLL_CR_CPU_CLK_DIV_RATIO
- APAD_XMT
- APANA_ADC_IN_SELECT
- APANA_ENABLE_BYPASS
- APANA_ENABLE_MIC_BOOST
- APANA_ENABLE_MIC_BOOST2
- APANA_ENABLE_MIC_MUTE
- APANA_ENABLE_SIDETONE
- APANA_SELECT_DAC
- APANA_SIDETONE_ATTN
- APANEL
- APANEL_DEV_APPBTN
- APANEL_DEV_CDBTN
- APANEL_DEV_LCD
- APANEL_DEV_LED
- APANEL_DEV_MAX
- APANEL_DEV_NONE
- APANEL_NAME
- APARMBAREA
- APB1
- APB1_LOG_MSG_SIZE
- APB1_LOG_SIZE
- APB1_PCM
- APB2
- APB2_PCM
- APB3_SEL_MASK
- APB3_SEL_MASK_SFT
- APB3_SEL_SFT
- APBBASE
- APBBASE_CTRL_P
- APBBASE_DATA_P
- APBBASE_SCALAR_P
- APBBASE_STATUS_P
- APBCP_TWSI1
- APBCP_UART2
- APBC_APBCLK
- APBC_CLK
- APBC_CLK_OPS
- APBC_FNCLK
- APBC_FNCLKSEL
- APBC_GPIO
- APBC_KPC
- APBC_NO_BUS_CTRL
- APBC_POWER
- APBC_POWER_CTRL
- APBC_PWM0
- APBC_PWM1
- APBC_PWM2
- APBC_PWM3
- APBC_PWM4
- APBC_REG
- APBC_RST
- APBC_RTC
- APBC_SSP0
- APBC_SSP1
- APBC_SSP2
- APBC_SSP3
- APBC_SSP4
- APBC_SSP5
- APBC_TIMER
- APBC_TIMER0
- APBC_TIMER1
- APBC_TIMERS
- APBC_TWSI0
- APBC_TWSI1
- APBC_TWSI2
- APBC_TWSI3
- APBC_TWSI4
- APBC_TWSI5
- APBC_TWSI6
- APBC_UART0
- APBC_UART1
- APBC_UART2
- APBC_UART3
- APBC_UART4
- APBC_VIRT_BASE
- APBLOCK_MAJOR
- APBOOT_TO_APEXECUTE
- APBPS2_CTRL_RE
- APBPS2_CTRL_RI
- APBPS2_CTRL_TE
- APBPS2_CTRL_TI
- APBPS2_STATUS_DR
- APBPS2_STATUS_FE
- APBPS2_STATUS_KI
- APBPS2_STATUS_PE
- APBPS2_STATUS_RCNT
- APBPS2_STATUS_RF
- APBPS2_STATUS_TCNT
- APBPS2_STATUS_TF
- APBREG_BSR
- APBREG_BSR_SARAC
- APBREG_CAN
- APBREG_EMU_PCG
- APBREG_EMU_PCG_SARAC
- APBREG_MLB
- APBREG_PAER
- APBREG_PAER_SARAC
- APBREG_PCG
- APBREG_PCG_SARAC
- APBREG_PRAC
- APBREG_PRAC_SARAC
- APBREG_PUR
- APBREG_PUR_SARAC
- APBREG_PWAC
- APBREG_PWAC_SARAC
- APBREG_SARAC
- APBTMRS_COMP_VERSION
- APBTMRS_EOI
- APBTMRS_INT_STATUS
- APBTMRS_RAW_INT_STATUS
- APBTMRS_REG_SIZE
- APBTMR_CONTROL_ENABLE
- APBTMR_CONTROL_INT
- APBTMR_CONTROL_MODE_PERIODIC
- APBTMR_N_CONTROL
- APBTMR_N_CURRENT_VALUE
- APBTMR_N_EOI
- APBTMR_N_INT_STATUS
- APBTMR_N_LOAD_COUNT
- APBT_CLOCKEVENT0_NUM
- APBT_CLOCKEVENT_RATING
- APBT_CLOCKSOURCE_NUM
- APBT_CLOCKSOURCE_RATING
- APBT_DEFAULT_BASE
- APBT_DEV_USED
- APBT_MAX_FREQ
- APBT_MIN_DELTA_USEC
- APBT_MIN_FREQ
- APBT_MIN_PERIOD
- APBT_MMAP_SIZE
- APBUART_CONSOLE
- APB_CLK
- APB_CTRL
- APB_DIAG_REGISTER
- APB_DIV_MASK
- APB_DMA_AFAR
- APB_DMA_ASFR
- APB_DMA_BURST_MODE
- APB_DMA_CYCLES_MASK
- APB_DMA_DATA_WIDTH
- APB_DMA_DATA_WIDTH_1
- APB_DMA_DATA_WIDTH_2
- APB_DMA_DATA_WIDTH_4
- APB_DMA_DATA_WIDTH_MASK
- APB_DMA_DEST
- APB_DMA_DEST_DEC_1_4
- APB_DMA_DEST_DEC_2_8
- APB_DMA_DEST_DEC_4_16
- APB_DMA_DEST_INC_0
- APB_DMA_DEST_INC_1_4
- APB_DMA_DEST_INC_2_8
- APB_DMA_DEST_INC_4_16
- APB_DMA_DEST_MASK
- APB_DMA_DEST_REQ_NO
- APB_DMA_DEST_REQ_NO_MASK
- APB_DMA_DEST_SELECT
- APB_DMA_ENABLE
- APB_DMA_ERR_INT_EN
- APB_DMA_ERR_INT_STS
- APB_DMA_FIN_INT_EN
- APB_DMA_FIN_INT_STS
- APB_DMA_MAX_CHANNEL
- APB_DMA_SOURCE
- APB_DMA_SOURCE_DEC_1_4
- APB_DMA_SOURCE_DEC_2_8
- APB_DMA_SOURCE_DEC_4_16
- APB_DMA_SOURCE_INC_0
- APB_DMA_SOURCE_INC_1_4
- APB_DMA_SOURCE_INC_2_8
- APB_DMA_SOURCE_INC_4_16
- APB_DMA_SOURCE_MASK
- APB_DMA_SOURCE_REQ_NO
- APB_DMA_SOURCE_REQ_NO_MASK
- APB_DMA_SOURCE_SELECT
- APB_DMA_TARGET_LATENCY_TIMER
- APB_DMA_TARGET_RETRY_LIMIT
- APB_DRAM_PATH
- APB_ERR_EN
- APB_ERR_EN_SHIFT
- APB_INT_ACK
- APB_INT_BASE_OFFSET
- APB_INT_ENABLE_H
- APB_INT_ENABLE_L
- APB_INT_FINALSTATUS_H
- APB_INT_FINALSTATUS_L
- APB_INT_MASK
- APB_INT_MASK_H
- APB_INT_MASK_L
- APB_IO_ADDRESS_MAP
- APB_IRAM_PATH
- APB_MEM_ADDRESS_MAP
- APB_MISC_GP_HIDREV
- APB_MISC_XM2CFGCPADCTRL
- APB_MISC_XM2CFGCPADCTRL2
- APB_MISC_XM2CFGDPADCTRL
- APB_MISC_XM2CFGDPADCTRL2
- APB_MISC_XM2CLKCFGPADCTRL
- APB_MISC_XM2COMPPADCTRL
- APB_MISC_XM2VTTGENPADCTRL
- APB_PCI_CONTROL_HIGH
- APB_PCI_CONTROL_LOW
- APB_PCI_CTL_HIGH_ARBITER_EN
- APB_PCI_CTL_HIGH_SERR
- APB_PCI_CTL_LOW_ARB_PARK
- APB_PCI_CTL_LOW_ERRINT_EN
- APB_PHYS_BASE
- APB_PHYS_SIZE
- APB_PIO_AFAR
- APB_PIO_ASFR
- APB_PIO_TARGET_LATENCY_TIMER
- APB_PIO_TARGET_RETRY_LIMIT
- APB_PRIMARY_MASTER_RETRY_LIMIT
- APB_R2T_MASK
- APB_R2T_MASK_SFT
- APB_R2T_SFT
- APB_READ
- APB_SECONDARY_CONTROL
- APB_SECONDARY_MASTER_RETRY_LIMIT
- APB_STATUS_MASK
- APB_TICK_REGISTER
- APB_TIMEOUT_ACKNOWLEDGE
- APB_TIMEOUT_INT
- APB_VIRT_BASE
- APB_W2T_MASK
- APB_W2T_MASK_SFT
- APB_W2T_SFT
- APB_WRITE
- APB_WRITE2
- APB_XT_RESET
- APCB0_MASK_SIZE
- APCB1_MASK_SIZE
- APCC
- APCCC
- APCCNC
- APCCNVA
- APCCSR
- APCCVA
- APCH_CFG_OVPSET
- APCH_CFG_OVPSET_6V6
- APCH_CFG_OVPSET_7V
- APCH_CFG_OVPSET_7V5
- APCH_CFG_OVPSET_8V
- APCH_CFG_PRETIMO
- APCH_CFG_PRETIMO_40_MIN
- APCH_CFG_PRETIMO_60_MIN
- APCH_CFG_PRETIMO_80_MIN
- APCH_CFG_PRETIMO_DISABLED
- APCH_CFG_SUSCHG
- APCH_CFG_TOTTIMO
- APCH_CFG_TOTTIMO_3_HOUR
- APCH_CFG_TOTTIMO_4_HOUR
- APCH_CFG_TOTTIMO_5_HOUR
- APCH_CFG_TOTTIMO_DISABLED
- APCH_CTRL_CHGEOCIN
- APCH_CTRL_CHGEOCOUT
- APCH_CTRL_INCON
- APCH_CTRL_INDIS
- APCH_CTRL_TEMPIN
- APCH_CTRL_TEMPOUT
- APCH_CTRL_TIMRPRE
- APCH_CTRL_TIMRTOT
- APCH_STATE_ACINSTAT
- APCH_STATE_CSTATE
- APCH_STATE_CSTATE_DISABLED
- APCH_STATE_CSTATE_EOC
- APCH_STATE_CSTATE_FAST
- APCH_STATE_CSTATE_PRE
- APCH_STATE_CSTATE_SHIFT
- APCH_STATUS_CHGDAT
- APCH_STATUS_CHGSTAT
- APCH_STATUS_INDAT
- APCH_STATUS_INSTAT
- APCH_STATUS_TEMPDAT
- APCH_STATUS_TEMPSTAT
- APCH_STATUS_TIMRDAT
- APCH_STATUS_TIMRSTAT
- APCI1032_CTRL_INT_AND
- APCI1032_CTRL_INT_ENA
- APCI1032_CTRL_INT_MODE
- APCI1032_CTRL_INT_OR
- APCI1032_CTRL_REG
- APCI1032_DI_REG
- APCI1032_MODE1_REG
- APCI1032_MODE2_REG
- APCI1032_STATUS_REG
- APCI1500_CLK_SEL_REG
- APCI1500_DI_REG
- APCI1500_DO_REG
- APCI1500_Z8536_CTRL_REG
- APCI1500_Z8536_PORTA_REG
- APCI1500_Z8536_PORTB_REG
- APCI1500_Z8536_PORTC_REG
- APCI1516_DI_REG
- APCI1516_DO_REG
- APCI1516_WDOG_REG
- APCI1564_COUNTER
- APCI1564_DI_INT_MODE1_REG
- APCI1564_DI_INT_MODE2_REG
- APCI1564_DI_INT_MODE_MASK
- APCI1564_DI_INT_STATUS_REG
- APCI1564_DI_IRQ_ENA
- APCI1564_DI_IRQ_MODE
- APCI1564_DI_IRQ_REG
- APCI1564_DI_REG
- APCI1564_DO_INT_CTRL_CC_INT_ENA
- APCI1564_DO_INT_CTRL_REG
- APCI1564_DO_INT_CTRL_VCC_INT_ENA
- APCI1564_DO_INT_STATUS_CC
- APCI1564_DO_INT_STATUS_REG
- APCI1564_DO_INT_STATUS_VCC
- APCI1564_DO_IRQ_INTR
- APCI1564_DO_IRQ_REG
- APCI1564_DO_REG
- APCI1564_EEPROM_CLK
- APCI1564_EEPROM_CS
- APCI1564_EEPROM_DI
- APCI1564_EEPROM_DO
- APCI1564_EEPROM_REG
- APCI1564_EEPROM_TO_REV
- APCI1564_EEPROM_VCC_STATUS
- APCI1564_EVENT_COS
- APCI1564_EVENT_COUNTER
- APCI1564_EVENT_MASK
- APCI1564_EVENT_TIMER
- APCI1564_REV1_MAIN_IOBASE
- APCI1564_REV1_TIMER_IOBASE
- APCI1564_REV2_MAIN_IOBASE
- APCI1564_REV2_TIMER_IOBASE
- APCI1564_WDOG_IOBASE
- APCI16XX_DIR_REG
- APCI16XX_IN_REG
- APCI16XX_OUT_REG
- APCI2032_DO_REG
- APCI2032_INT_CTRL_CC_ENA
- APCI2032_INT_CTRL_REG
- APCI2032_INT_CTRL_VCC_ENA
- APCI2032_INT_STATUS_CC
- APCI2032_INT_STATUS_REG
- APCI2032_INT_STATUS_VCC
- APCI2032_STATUS_IRQ
- APCI2032_STATUS_REG
- APCI2032_WDOG_REG
- APCI2200_DI_REG
- APCI2200_DO_REG
- APCI2200_WDOG_REG
- APCI3120_ADDON_ADDR_REG
- APCI3120_ADDON_CTRL_A2P_FIFO_ENA
- APCI3120_ADDON_CTRL_AMWEN_ENA
- APCI3120_ADDON_CTRL_REG
- APCI3120_ADDON_DATA_REG
- APCI3120_AI_FIFO_REG
- APCI3120_AI_SOFTTRIG_REG
- APCI3120_AO_DATA
- APCI3120_AO_MUX
- APCI3120_AO_REG
- APCI3120_CHANLIST_GAIN
- APCI3120_CHANLIST_INDEX
- APCI3120_CHANLIST_MUX
- APCI3120_CHANLIST_REG
- APCI3120_CHANLIST_UNIPOLAR
- APCI3120_CTR0_DO_BITS
- APCI3120_CTR0_REG
- APCI3120_CTR0_TIMER_SEL
- APCI3120_CTRL_EXT_TRIG
- APCI3120_CTRL_GATE
- APCI3120_CTRL_PA
- APCI3120_CTRL_PR
- APCI3120_CTRL_REG
- APCI3120_FIFO_ADVANCE_ON_BYTE_2
- APCI3120_MODE_EOC_IRQ_ENA
- APCI3120_MODE_EOS_IRQ_ENA
- APCI3120_MODE_REG
- APCI3120_MODE_SCAN_ENA
- APCI3120_MODE_TIMER2_AS
- APCI3120_MODE_TIMER2_AS_COUNTER
- APCI3120_MODE_TIMER2_AS_MASK
- APCI3120_MODE_TIMER2_AS_TIMER
- APCI3120_MODE_TIMER2_AS_WDOG
- APCI3120_MODE_TIMER2_CLK
- APCI3120_MODE_TIMER2_CLK_EOC
- APCI3120_MODE_TIMER2_CLK_EOS
- APCI3120_MODE_TIMER2_CLK_MASK
- APCI3120_MODE_TIMER2_CLK_OSC
- APCI3120_MODE_TIMER2_CLK_OUT1
- APCI3120_MODE_TIMER2_IRQ_ENA
- APCI3120_REVA
- APCI3120_REVA_OSC_BASE
- APCI3120_REVB
- APCI3120_REVB_OSC_BASE
- APCI3120_STATUS_AMCC_INT
- APCI3120_STATUS_DA_READY
- APCI3120_STATUS_EOC_INT
- APCI3120_STATUS_EOS_INT
- APCI3120_STATUS_FIFO_EMPTY
- APCI3120_STATUS_FIFO_FULL
- APCI3120_STATUS_INT_MASK
- APCI3120_STATUS_REG
- APCI3120_STATUS_TIMER2_INT
- APCI3120_STATUS_TO_DI_BITS
- APCI3120_STATUS_TO_VERSION
- APCI3120_TIMER_MODE
- APCI3120_TIMER_MODE0
- APCI3120_TIMER_MODE2
- APCI3120_TIMER_MODE4
- APCI3120_TIMER_MODE5
- APCI3120_TIMER_MODE_MASK
- APCI3120_TIMER_MODE_REG
- APCI3120_TIMER_REG
- APCI3501_AO_CTRL_BIPOLAR
- APCI3501_AO_CTRL_STATUS_REG
- APCI3501_AO_DATA_BIPOLAR
- APCI3501_AO_DATA_CHAN
- APCI3501_AO_DATA_REG
- APCI3501_AO_DATA_VAL
- APCI3501_AO_STATUS_READY
- APCI3501_AO_TRIG_SCS_REG
- APCI3501_DI_REG
- APCI3501_DO_REG
- APCI3501_TIMER_BASE
- APCIOCGBPORT
- APCIOCGCPWR
- APCIOCGFANCTL
- APCIOCSBPORT
- APCIOCSCPWR
- APCIOCSFANCTL
- APCNC
- APCNVA
- APCONN_ACTIVE
- APCONN_NONE
- APCONN_SETUP
- APCPC
- APCPNC
- APCPNVA
- APCPVA
- APCS_CPU_PWR_CTL
- APCS_SAW2_2_VCTL
- APCS_SAW2_VCTL
- APCVA
- APC_BPMASK
- APC_BPORT_A
- APC_BPORT_B
- APC_BPORT_REG
- APC_CAPT_INT
- APC_CDC_RESET
- APC_CDMA_READY
- APC_CHIP_RESET
- APC_CNTL
- APC_CPAUSE
- APC_CPOWER_OFF
- APC_CPOWER_ON
- APC_CPOWER_REG
- APC_CTRL_IO
- APC_DEVNAME
- APC_FANCTL_HI
- APC_FANCTL_LO
- APC_FANCTL_REG
- APC_GENL_INT
- APC_IDLE_ON
- APC_IDLE_REG
- APC_INT_PENDING
- APC_IOC
- APC_LUT_AB
- APC_LUT_CD
- APC_LUT_EF
- APC_LUT_GH
- APC_LUT_IJ
- APC_LUT_KL
- APC_LUT_MN
- APC_LUT_OP
- APC_MINOR
- APC_OBPNAME
- APC_PDMA_READY
- APC_PLAY
- APC_PLAY_INT
- APC_PPAUSE
- APC_PWR_GATE_CTL
- APC_RECORD
- APC_REGMASK
- APC_XINT_CAPT
- APC_XINT_CEMP
- APC_XINT_CENA
- APC_XINT_CNVA
- APC_XINT_COVF
- APC_XINT_EMPT
- APC_XINT_ENA
- APC_XINT_GENL
- APC_XINT_PEMP
- APC_XINT_PENA
- APC_XINT_PLAY
- APC_XINT_PNVA
- APD
- APDAKEYHI_EL1
- APDAKEYLO_EL1
- APDBKEYHI_EL1
- APDBKEYLO_EL1
- APDIGI_DE_EMPHASIS
- APDIGI_ENABLE_ADC_HPF
- APDIGI_ENABLE_DAC_MUTE
- APDIGI_STORE_OFFSET
- APDM_HOST
- APDM_HPDN
- APDM_MAC
- APDO_TYPE_PPS
- APDS9300_CLEAR
- APDS9300_CMD
- APDS9300_CONTROL
- APDS9300_DATA0LOW
- APDS9300_DATA1LOW
- APDS9300_DRV_NAME
- APDS9300_INTERRUPT
- APDS9300_INTR_ENABLE
- APDS9300_IRQ_NAME
- APDS9300_PM_OPS
- APDS9300_POWER_OFF
- APDS9300_POWER_ON
- APDS9300_THRESHHIGHLOW
- APDS9300_THRESHLOWLOW
- APDS9300_THRESH_INTR
- APDS9300_THRESH_MAX
- APDS9300_WORD
- APDS9802ALS_PM_OPS
- APDS990X_AIHTH
- APDS990X_AIHTL
- APDS990X_AILTH
- APDS990X_AILTL
- APDS990X_APERS_SHIFT
- APDS990X_ATIME
- APDS990X_CDATAH
- APDS990X_CDATAL
- APDS990X_CONFIG
- APDS990X_CONTROL
- APDS990X_ENABLE
- APDS990X_EN_AEN
- APDS990X_EN_AIEN
- APDS990X_EN_DISABLE_ALL
- APDS990X_EN_PEN
- APDS990X_EN_PIEN
- APDS990X_EN_PON
- APDS990X_EN_WEN
- APDS990X_ID
- APDS990X_ID_0
- APDS990X_ID_29
- APDS990X_ID_4
- APDS990X_INT_ACK_ALS
- APDS990X_INT_ACK_BOTH
- APDS990X_INT_ACK_PS
- APDS990X_IRDATAH
- APDS990X_IRDATAL
- APDS990X_LUX_OUTPUT_SCALE
- APDS990X_MAX_AGAIN
- APDS990X_PDATAH
- APDS990X_PDATAL
- APDS990X_PERS
- APDS990X_PIHTH
- APDS990X_PIHTL
- APDS990X_PILTH
- APDS990X_PILTL
- APDS990X_PPCOUNT
- APDS990X_PPERS_SHIFT
- APDS990X_PTIME
- APDS990X_PTIME_DEFAULT
- APDS990X_REV
- APDS990X_STATUS
- APDS990X_ST_AINT
- APDS990X_ST_PINT
- APDS990X_TIME_TO_ADC
- APDS990X_WTIME
- APDS990X_WTIME_DEFAULT
- APDS990x_ADDR_SHIFT
- APDS990x_CMD
- APDS990x_CMD_TYPE_INC
- APDS990x_CMD_TYPE_MASK
- APDS990x_CMD_TYPE_RB
- APDS990x_CMD_TYPE_SPE
- APDS9960_DEFAULT_GEXTH
- APDS9960_DEFAULT_GPENTH
- APDS9960_DEFAULT_PERS
- APDS9960_DRV_NAME
- APDS9960_GESTURE_CHANNEL
- APDS9960_INTENSITY_CHANNEL
- APDS9960_MAX_ALS_THRES_VAL
- APDS9960_MAX_INT_TIME_IN_US
- APDS9960_MAX_PXS_THRES_VAL
- APDS9960_REGMAP_NAME
- APDS9960_REG_AICLEAR
- APDS9960_REG_AIHTH
- APDS9960_REG_AIHTL
- APDS9960_REG_AILTH
- APDS9960_REG_AILTL
- APDS9960_REG_ALS_BASE
- APDS9960_REG_ALS_CHANNEL
- APDS9960_REG_ATIME
- APDS9960_REG_CICLEAR
- APDS9960_REG_CONFIG_1
- APDS9960_REG_CONFIG_2
- APDS9960_REG_CONFIG_2_GGAIN_MASK
- APDS9960_REG_CONFIG_2_GGAIN_MASK_SHIFT
- APDS9960_REG_CONFIG_3
- APDS9960_REG_CONTROL
- APDS9960_REG_CONTROL_AGAIN_MASK
- APDS9960_REG_CONTROL_AGAIN_MASK_SHIFT
- APDS9960_REG_CONTROL_PGAIN_MASK
- APDS9960_REG_CONTROL_PGAIN_MASK_SHIFT
- APDS9960_REG_ENABLE
- APDS9960_REG_GCONF_1
- APDS9960_REG_GCONF_1_GFIFO_THRES_MASK
- APDS9960_REG_GCONF_1_GFIFO_THRES_MASK_SHIFT
- APDS9960_REG_GCONF_2
- APDS9960_REG_GCONF_3
- APDS9960_REG_GCONF_4
- APDS9960_REG_GEXTH
- APDS9960_REG_GFIFO_BASE
- APDS9960_REG_GFIFO_DIR
- APDS9960_REG_GFLVL
- APDS9960_REG_GOFFSET_D
- APDS9960_REG_GOFFSET_L
- APDS9960_REG_GOFFSET_R
- APDS9960_REG_GOFFSET_U
- APDS9960_REG_GPENTH
- APDS9960_REG_GPULSE
- APDS9960_REG_GSTATUS
- APDS9960_REG_ID
- APDS9960_REG_IFORCE
- APDS9960_REG_PDATA
- APDS9960_REG_PERS
- APDS9960_REG_PICLEAR
- APDS9960_REG_PIHT
- APDS9960_REG_PILT
- APDS9960_REG_POFFSET_DL
- APDS9960_REG_POFFSET_UR
- APDS9960_REG_PPULSE
- APDS9960_REG_RAM_END
- APDS9960_REG_RAM_START
- APDS9960_REG_STATUS
- APDS9960_REG_STATUS_ALS_INT
- APDS9960_REG_STATUS_GINT
- APDS9960_REG_STATUS_PS_INT
- APDS9960_REG_WTIME
- APDS_CALIB_SCALER
- APDS_DEFAULT_PROX_PERS
- APDS_IRLED_CURR_100mA
- APDS_IRLED_CURR_12mA
- APDS_IRLED_CURR_25mA
- APDS_IRLED_CURR_50mA
- APDS_LUX_AVERAGING_TIME
- APDS_LUX_DEFAULT_RATE
- APDS_LUX_DEF_THRES_HI
- APDS_LUX_DEF_THRES_LO
- APDS_LUX_GAIN_LO_LIMIT
- APDS_LUX_GAIN_LO_LIMIT_STRICT
- APDS_LUX_NEUTRAL_CALIB_VALUE
- APDS_PARAM_SCALE
- APDS_PDIODE_IR
- APDS_PGAIN_1X
- APDS_PROX_DEF_THRES
- APDS_PROX_HYSTERESIS
- APDS_PROX_NEUTRAL_CALIB_VALUE
- APDS_PROX_RANGE
- APDS_RANGE
- APDS_STARTUP_DELAY
- APDS_TIMEOUT
- APDW_MASK
- APD_ADDR
- APD_BIT
- APE
- APE1_FIXED_BITS_MASK
- APE1_LIMIT_ALIGNMENT
- APE1_MTYPE
- APECS_AND_LCA_DEFAULT_MEM_BASE
- APECS_CONF
- APECS_DENSE_MEM
- APECS_HAE_ADDRESS
- APECS_IACK_SC
- APECS_IO
- APECS_IOC_DCSR
- APECS_IOC_DR1
- APECS_IOC_DR2
- APECS_IOC_DR3
- APECS_IOC_HAXR0
- APECS_IOC_HAXR1
- APECS_IOC_HAXR2
- APECS_IOC_PB1R
- APECS_IOC_PB2R
- APECS_IOC_PEAR
- APECS_IOC_PM1R
- APECS_IOC_PM2R
- APECS_IOC_PMLT
- APECS_IOC_SEAR
- APECS_IOC_STAT0_CMD
- APECS_IOC_STAT0_CODE_MASK
- APECS_IOC_STAT0_CODE_SHIFT
- APECS_IOC_STAT0_ERR
- APECS_IOC_STAT0_LOST
- APECS_IOC_STAT0_P_NBR_MASK
- APECS_IOC_STAT0_P_NBR_SHIFT
- APECS_IOC_STAT0_THIT
- APECS_IOC_STAT0_TREF
- APECS_IOC_TB1R
- APECS_IOC_TB2R
- APECS_IOC_TBIA
- APECS_IOC_TLBDATA0
- APECS_IOC_TLBDATA1
- APECS_IOC_TLBDATA2
- APECS_IOC_TLBDATA3
- APECS_IOC_TLBDATA4
- APECS_IOC_TLBDATA5
- APECS_IOC_TLBDATA6
- APECS_IOC_TLBDATA7
- APECS_IOC_TLBTAG0
- APECS_IOC_TLBTAG1
- APECS_IOC_TLBTAG2
- APECS_IOC_TLBTAG3
- APECS_IOC_TLBTAG4
- APECS_IOC_TLBTAG5
- APECS_IOC_TLBTAG6
- APECS_IOC_TLBTAG7
- APECS_MEM_B0BAR
- APECS_MEM_B0BCR
- APECS_MEM_B0TRA
- APECS_MEM_B0TRB
- APECS_MEM_B1BAR
- APECS_MEM_B1BCR
- APECS_MEM_B1TRA
- APECS_MEM_B1TRB
- APECS_MEM_B2BAR
- APECS_MEM_B2BCR
- APECS_MEM_B2TRA
- APECS_MEM_B2TRB
- APECS_MEM_B3BAR
- APECS_MEM_B3BCR
- APECS_MEM_B3TRA
- APECS_MEM_B3TRB
- APECS_MEM_B4BAR
- APECS_MEM_B4BCR
- APECS_MEM_B4TRA
- APECS_MEM_B4TRB
- APECS_MEM_B5BAR
- APECS_MEM_B5BCR
- APECS_MEM_B5TRA
- APECS_MEM_B5TRB
- APECS_MEM_B6BAR
- APECS_MEM_B6BCR
- APECS_MEM_B6TRA
- APECS_MEM_B6TRB
- APECS_MEM_B7BAR
- APECS_MEM_B7BCR
- APECS_MEM_B7TRA
- APECS_MEM_B7TRB
- APECS_MEM_B8BAR
- APECS_MEM_B8BCR
- APECS_MEM_B8TRA
- APECS_MEM_B8TRB
- APECS_MEM_EDSR
- APECS_MEM_EHAR
- APECS_MEM_ELAR
- APECS_MEM_GCR
- APECS_MEM_GTR
- APECS_MEM_LDxHAR
- APECS_MEM_LDxLAR
- APECS_MEM_PDLDR
- APECS_MEM_PDhDR
- APECS_MEM_RTR
- APECS_MEM_SFT_RST
- APECS_MEM_TAR
- APECS_MEM_VFPR
- APECS_SET_HAE
- APECS_SPARSE_MEM
- APEI_ERST_CLEAR_RECORD
- APEI_ERST_GET_RECORD_COUNT
- APEI_ERST_INVALID_RECORD_ID
- APEI_EXEC_INS_ACCESS_REGISTER
- APEI_EXEC_PRESERVE_REGISTER
- APEI_EXEC_SET_IP
- APEI_INTERNAL_H
- APEI_PFX
- APEP
- APERFMPERF_CACHE_THRESHOLD_MS
- APERFMPERF_REFRESH_DELAY_MS
- APERFMPERF_STALE_THRESHOLD_MS
- APERR
- APERTURE_14
- APERTURE_4M_ENABLE
- APERTURE_8M_ENABLE
- APERTURE_CONF_REG
- APERTURE_LEN
- APERTURE_MAX_RANGES
- APERTURE_PAGE_INDEX
- APERTURE_PROPERTY
- APERTURE_RANGE_INDEX
- APERTURE_RANGE_PAGES
- APERTURE_RANGE_SHIFT
- APERTURE_RANGE_SIZE
- APERTURE_SIZE
- APEXECUTE_TO_APDEEPSLEEP
- APEXECUTE_TO_APIDLE
- APEXECUTE_TO_APSLEEP
- APEX_BAR2_REG_AXI_QUIESCE
- APEX_BAR2_REG_GCB_CLOCK_GATE
- APEX_BAR2_REG_IDLEGENERATOR_IDLEGEN_IDLEREGISTER
- APEX_BAR2_REG_KERNEL_HIB_DMA_PAUSE
- APEX_BAR2_REG_KERNEL_HIB_DMA_PAUSE_MASK
- APEX_BAR2_REG_KERNEL_HIB_EXTENDED_TABLE
- APEX_BAR2_REG_KERNEL_HIB_FATAL_ERR_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_INPUT_ACTV_QUEUE_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_INSTR_QUEUE_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_MSIX_PENDING_BIT_ARRAY0
- APEX_BAR2_REG_KERNEL_HIB_MSIX_PENDING_BIT_ARRAY1
- APEX_BAR2_REG_KERNEL_HIB_MSIX_TABLE
- APEX_BAR2_REG_KERNEL_HIB_MSIX_TABLE_INIT
- APEX_BAR2_REG_KERNEL_HIB_OUTPUT_ACTV_QUEUE_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE
- APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_INIT
- APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_SIZE
- APEX_BAR2_REG_KERNEL_HIB_PARAM_QUEUE_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_SC_HOST_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_STATUS_BLOCK_DELAY
- APEX_BAR2_REG_KERNEL_HIB_TOP_LEVEL_INTVECCTL
- APEX_BAR2_REG_KERNEL_HIB_TRANSLATION_ENABLE
- APEX_BAR2_REG_KERNEL_WIRE_INT_MASK_ARRAY
- APEX_BAR2_REG_KERNEL_WIRE_INT_PENDING_BIT_ARRAY
- APEX_BAR2_REG_SCALAR_CORE_ERROR_STATUS
- APEX_BAR2_REG_SCU_0
- APEX_BAR2_REG_SCU_1
- APEX_BAR2_REG_SCU_2
- APEX_BAR2_REG_SCU_3
- APEX_BAR2_REG_SCU_4
- APEX_BAR2_REG_SCU_5
- APEX_BAR2_REG_SCU_BASE
- APEX_BAR2_REG_USER_HIB_DMA_PAUSE
- APEX_BAR2_REG_USER_HIB_DMA_PAUSED
- APEX_BAR2_REG_USER_HIB_ERROR_STATUS
- APEX_BAR_BYTES
- APEX_BAR_INDEX
- APEX_BAR_OFFSET
- APEX_CH_MEM_BYTES
- APEX_CM_OFFSET
- APEX_DEVICE_NAME
- APEX_DRIVER_VERSION
- APEX_EXTENDED_SHIFT
- APEX_INTERRUPT_COUNT
- APEX_INTERRUPT_FATAL_ERR
- APEX_INTERRUPT_INPUT_ACTV_QUEUE
- APEX_INTERRUPT_INSTR_QUEUE
- APEX_INTERRUPT_OUTPUT_ACTV_QUEUE
- APEX_INTERRUPT_PARAM_QUEUE
- APEX_INTERRUPT_SC_HOST_0
- APEX_INTERRUPT_SC_HOST_1
- APEX_INTERRUPT_SC_HOST_2
- APEX_INTERRUPT_SC_HOST_3
- APEX_INTERRUPT_TOP_LEVEL_0
- APEX_INTERRUPT_TOP_LEVEL_1
- APEX_INTERRUPT_TOP_LEVEL_2
- APEX_INTERRUPT_TOP_LEVEL_3
- APEX_IOCTL_BASE
- APEX_IOCTL_GATE_CLOCK
- APEX_PAGE_TABLE_TOTAL_ENTRIES
- APEX_PCI_DEVICE_ID
- APEX_PCI_VENDOR_ID
- APEX_RESET_DELAY
- APEX_RESET_RETRY
- APE_100_OPP
- APE_50_OPP
- APE_50_PARTLY_25_OPP
- APE_EVENT_1
- APE_EVENT_STATUS_DRIVER_EVNT
- APE_EVENT_STATUS_EVENT_PENDING
- APE_EVENT_STATUS_SCRTCHPD_READ
- APE_EVENT_STATUS_SCRTCHPD_WRITE
- APE_EVENT_STATUS_STATE_CHNGE
- APE_EVENT_STATUS_STATE_START
- APE_EVENT_STATUS_STATE_SUSPEND
- APE_EVENT_STATUS_STATE_UNLOAD
- APE_EVENT_STATUS_STATE_WOL
- APE_FW_STATUS_READY
- APE_FW_VERSION_BLDMSK
- APE_FW_VERSION_MAJMSK
- APE_FW_VERSION_MAJSFT
- APE_FW_VERSION_MINMSK
- APE_FW_VERSION_MINSFT
- APE_FW_VERSION_REVMSK
- APE_FW_VERSION_REVSFT
- APE_HOST_BEHAV_NO_PHYLOCK
- APE_HOST_DRIVER_ID_LINUX
- APE_HOST_DRIVER_ID_MAGIC
- APE_HOST_HEARTBEAT_INT_5SEC
- APE_HOST_HEARTBEAT_INT_DISABLE
- APE_HOST_SEG_LEN_MAGIC
- APE_HOST_SEG_SIG_MAGIC
- APE_LOCK_GRANT_DRIVER
- APE_LOCK_PER_REQ_DRIVER
- APE_LOCK_REQ_DRIVER
- APE_NO_CHANGE
- APE_OPP_INIT
- APE_OTP_ADDR_CPU_ENABLE
- APE_OTP_CTRL_CMD_RD
- APE_OTP_CTRL_PROG_EN
- APE_OTP_CTRL_START
- APE_OTP_STATUS_CMD_DONE
- APE_PER_LOCK_GRANT_DRIVER
- APE_PLL_FREF_SELECT
- APE_SEG_SIG_MAGIC
- APF
- APFM_OFF
- APFM_ONMAC
- APFM_RSM
- APF_CPUINTENS
- APF_MASK
- APF_NETWORK
- APF_NORMAL
- APF_SHIFT
- APGAKEYHI_EL1
- APGAKEYLO_EL1
- APHY_CWMIN
- APHY_PREAMBLE_TIME
- APHY_SERVICE_NBITS
- APHY_SIFS_TIME
- APHY_SIGNAL_TIME
- APHY_SLOT_TIME
- APHY_SYMBOL_TIME
- APHY_TAIL_NBITS
- APHY_TSSI_TABLE_SIZE
- APIAKEYHI_EL1
- APIAKEYLO_EL1
- APIBKEYHI_EL1
- APIBKEYLO_EL1
- APICDB0_EVENT
- APICDB1_EVENT_GETEVENT
- APICDB1_HOST_GETEVENT
- APICID_BIT
- APICID_SOCKET_ID_BIT
- APICID_TO_IRTE_DEST_HI
- APICID_TO_IRTE_DEST_LO
- APIC_ACCESS_ADDR
- APIC_ACCESS_ADDR_HIGH
- APIC_ACCESS_OFFSET
- APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
- APIC_ACCESS_TYPE
- APIC_ALL_CPUS
- APIC_ARBPRI
- APIC_ARBPRI_MASK
- APIC_BASE
- APIC_BASE_MSR
- APIC_BROADCAST
- APIC_BUS_CYCLE_NS
- APIC_BUS_FREQUENCY
- APIC_CLUSTER
- APIC_CLUSTERID
- APIC_CPUID
- APIC_DEBUG
- APIC_DEFAULT_PHYS_BASE
- APIC_DEST_ALLBUT
- APIC_DEST_ALLINC
- APIC_DEST_LOGICAL
- APIC_DEST_MASK
- APIC_DEST_NOSHORT
- APIC_DEST_PHYSICAL
- APIC_DEST_SELF
- APIC_DFR
- APIC_DFR_CLUSTER
- APIC_DFR_FLAT
- APIC_DFR_VALUE
- APIC_DIVISOR
- APIC_DM_EXTINT
- APIC_DM_FIXED
- APIC_DM_FIXED_MASK
- APIC_DM_INIT
- APIC_DM_LOWEST
- APIC_DM_NMI
- APIC_DM_REMRD
- APIC_DM_SMI
- APIC_DM_STARTUP
- APIC_ECTRL
- APIC_EFEAT
- APIC_EILVT_LVTOFF
- APIC_EILVT_MASKED
- APIC_EILVT_MSG_EXT
- APIC_EILVT_MSG_FIX
- APIC_EILVT_MSG_NMI
- APIC_EILVT_MSG_SMI
- APIC_EILVT_NR_AMD_10H
- APIC_EILVT_NR_AMD_K8
- APIC_EILVT_NR_MAX
- APIC_EILVTn
- APIC_EOI
- APIC_EOI_ACK
- APIC_ESR
- APIC_ESR_ILLREGA
- APIC_ESR_RECVILL
- APIC_ESR_RECV_ACC
- APIC_ESR_RECV_CS
- APIC_ESR_SENDILL
- APIC_ESR_SEND_ACC
- APIC_ESR_SEND_CS
- APIC_EXTNMI_ALL
- APIC_EXTNMI_BSP
- APIC_EXTNMI_NONE
- APIC_EXT_SPACE
- APIC_ICR
- APIC_ICR2
- APIC_ICR_BUSY
- APIC_ICR_RR_INPROG
- APIC_ICR_RR_INVALID
- APIC_ICR_RR_MASK
- APIC_ICR_RR_VALID
- APIC_ID
- APIC_INPUT_POLARITY
- APIC_INTEGRATED
- APIC_INT_ASSERT
- APIC_INT_LEVELTRIG
- APIC_IRR
- APIC_IR_BITS
- APIC_IR_MAPSIZE
- APIC_IR_REGS
- APIC_ISR
- APIC_ISR_NR
- APIC_LDR
- APIC_LDR_MASK
- APIC_LVR
- APIC_LVR_DIRECTED_EOI
- APIC_LVR_MASK
- APIC_LVT0
- APIC_LVT1
- APIC_LVTCMCI
- APIC_LVTERR
- APIC_LVTPC
- APIC_LVTT
- APIC_LVTTHMR
- APIC_LVT_LEVEL_TRIGGER
- APIC_LVT_MASKED
- APIC_LVT_REMOTE_IRR
- APIC_LVT_TIMER_BASE_MASK
- APIC_LVT_TIMER_ONESHOT
- APIC_LVT_TIMER_PERIODIC
- APIC_LVT_TIMER_TSCDEADLINE
- APIC_MODE_EXTINT
- APIC_MODE_FIXED
- APIC_MODE_MASK
- APIC_MODE_NMI
- APIC_PIC
- APIC_PROCPRI
- APIC_QUIET
- APIC_REGS_MASK
- APIC_REG_MASK
- APIC_RRR
- APIC_SELF_IPI
- APIC_SEND_PENDING
- APIC_SHORT_MASK
- APIC_SPIV
- APIC_SPIV_APIC_ENABLED
- APIC_SPIV_DIRECTED_EOI
- APIC_SPIV_FOCUS_DISABLED
- APIC_SYMMETRIC_IO
- APIC_SYMMETRIC_IO_NO_ROUTING
- APIC_TASKPRI
- APIC_TDCR
- APIC_TDR_DIV_1
- APIC_TDR_DIV_128
- APIC_TDR_DIV_16
- APIC_TDR_DIV_2
- APIC_TDR_DIV_32
- APIC_TDR_DIV_4
- APIC_TDR_DIV_64
- APIC_TDR_DIV_8
- APIC_TDR_DIV_TMBASE
- APIC_TIMER_BASE_CLKIN
- APIC_TIMER_BASE_DIV
- APIC_TIMER_BASE_TMBASE
- APIC_TMCCT
- APIC_TMICT
- APIC_TMR
- APIC_TPRI_MASK
- APIC_VECTORS_PER_REG
- APIC_VECTOR_MASK
- APIC_VERBOSE
- APIC_VERSION
- APIC_VIRTUAL_WIRE
- APIC_VIRTUAL_WIRE_NO_CONFIG
- APIC_XAPIC
- APID
- APIDLE_TO_APSLEEP
- APID_MASK
- APID_SHIFT
- APIEXCP_ADI0
- APIEXCP_ADI1
- APIEXCP_ADRS0
- APIEXCP_ADRS1
- APIEXCP_DART
- APIEXCP_DERR
- APIEXCP_ECC_CE_H
- APIEXCP_ECC_CE_L
- APIEXCP_ECC_UE_H
- APIEXCP_ECC_UE_L
- APIEXCP_STAT
- APIMASK_ADI
- APIMASK_ADI0
- APIMASK_ADI1
- APIMASK_ADRS0
- APIMASK_ADRS1
- APIMASK_DART
- APIMASK_DERR
- APIMASK_ECC_CE_H
- APIMASK_ECC_CE_L
- APIMASK_ECC_UE_H
- APIMASK_ECC_UE_L
- APIMASK_STAT
- APINT0
- APINT0EN
- APINT1
- APINT1EN
- APINT2
- APINT2EN
- APINT3
- APINT3EN
- APINT4
- APINT4EN
- APINT5
- APINT5EN
- APIO_EN_MASK
- API_CACHE
- API_CHAIN_NUM_CELLS
- API_CMD_BUF_SIZE
- API_CMD_CELL_ALIGNMENT
- API_CMD_CELL_DATA_ADDR_SIZE
- API_CMD_CELL_DESC_SIZE
- API_CMD_CELL_SIZE
- API_CMD_CELL_SIZE_MIN
- API_CMD_CELL_SIZE_SHIFT
- API_CMD_CELL_SIZE_VAL
- API_CMD_TIMEOUT
- API_CMD_WRITE
- API_DMA
- API_ENTRY
- API_FAST
- API_FAST_RESULT
- API_HAL_RET_VALUE_FAIL
- API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR
- API_HAL_RET_VALUE_OK
- API_HAL_RET_VALUE_SERVICE_UNKNWON
- API_HIGH_VOL
- API_HYP_ENTRY
- API_NO_POLL
- API_NO_WAIT_MB
- API_NO_WAIT_RES
- API_RESULT
- API_SLOW
- API_VERSION
- API_VERSION_MAJ
- API_VERSION_MIN
- API_VER_ID
- APK_AFE_REG_NUM
- APK_BB_REG_NUM
- APK_CURVE_REG_NUM
- APL
- APL13_WORLD
- APL1_APLA
- APL1_ETSIC
- APL1_FCCA
- APL1_WORLD
- APL2_APLC
- APL2_APLD
- APL2_ETSIC
- APL2_FCCA
- APL2_WORLD
- APL3_FCCA
- APL3_WORLD
- APL4_WORLD
- APL5_WORLD
- APL6_WORLD
- APL7_FCCA
- APL8_WORLD
- APL9_WORLD
- APLCTRL
- APLERR
- APLIST_VER1
- APLL
- APLL1_W_NAME
- APLL2_W_NAME
- APLL_1MEN
- APLL_320EN
- APLL_320_EN
- APLL_80EN
- APLL_AUTO_IDLE
- APLL_BOOST_H
- APLL_BOOST_L
- APLL_CON
- APLL_CON0
- APLL_CON1
- APLL_EDGE_SEL
- APLL_EN
- APLL_FORCE_LOCK
- APLL_FREF_SEL
- APLL_HALF
- APLL_INT
- APLL_INT_MUX
- APLL_LOCK
- APLL_LPFEN
- APLL_NDPLL_SWITCH
- APLL_POST_SRC
- APLL_PRE_SRC
- APLL_REF_CLK_13MHZ
- APLL_REF_CLK_19_2MHZ
- APLL_REF_CLK_20MHZ
- APLL_REF_CLK_25MHZ
- APLL_REF_CLK_26MHZ
- APLL_REF_CLK_38_4MHZ
- APLL_REF_CLK_40MHZ
- APLL_STRAPS
- APLL_TO_LPD
- APLL_VAL_1000
- APLL_VAL_800
- APLL_WDOGB
- APLSTAT
- APL_ASYMSHIFT
- APL_Ax_DEVICE_ID
- APL_NUM_CHANNELS
- APL_RESERVED
- APL_RVP
- APL_SSP_BASE_OFFSET
- APL_SSP_COUNT
- APListRid
- APM
- APMAP_BOOTPATH
- APMC_PHP_SHUTDOWN_DELAY
- APMG_ANALOG_SVR_REG
- APMG_BASE
- APMG_CLK_CTRL_REG
- APMG_CLK_DIS_REG
- APMG_CLK_EN_REG
- APMG_CLK_VAL_BSM_CLK_RQT
- APMG_CLK_VAL_DMA_CLK_RQT
- APMG_DIGITAL_SVR_REG
- APMG_PCIDEV_STT_REG
- APMG_PCIDEV_STT_VAL_L1_ACT_DIS
- APMG_PCIDEV_STT_VAL_PERSIST_DIS
- APMG_PCIDEV_STT_VAL_WAKE_ME
- APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
- APMG_PS_CTRL_MSK_PWR_SRC
- APMG_PS_CTRL_REG
- APMG_PS_CTRL_VAL_PWR_SRC_MAX
- APMG_PS_CTRL_VAL_PWR_SRC_VAUX
- APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
- APMG_PS_CTRL_VAL_RESET_REQ
- APMG_RFKILL_REG
- APMG_RTC_INT_MSK_REG
- APMG_RTC_INT_STT_REG
- APMG_RTC_INT_STT_RFKILL
- APMG_SVR_DIGITAL_VOLTAGE_1_32
- APMG_SVR_VOLTAGE_CONFIG_BIT_MSK
- APMIXED_SYS_TS_CON1
- APMIXED_USB
- APML_CONTROL__APML_NMI_En_MASK
- APML_CONTROL__APML_NMI_En__SHIFT
- APML_CONTROL__APML_OutputDis_MASK
- APML_CONTROL__APML_OutputDis__SHIFT
- APML_CONTROL__APML_SyncFlood_En_MASK
- APML_CONTROL__APML_SyncFlood_En__SHIFT
- APML_STATUS__APML_Corr_MASK
- APML_STATUS__APML_Corr__SHIFT
- APML_STATUS__APML_EgressPoisonErrHi_MASK
- APML_STATUS__APML_EgressPoisonErrHi__SHIFT
- APML_STATUS__APML_EgressPoisonErrLo_MASK
- APML_STATUS__APML_EgressPoisonErrLo__SHIFT
- APML_STATUS__APML_Fatal_MASK
- APML_STATUS__APML_Fatal__SHIFT
- APML_STATUS__APML_IntPoisonErr_MASK
- APML_STATUS__APML_IntPoisonErr__SHIFT
- APML_STATUS__APML_NonFatal_MASK
- APML_STATUS__APML_NonFatal__SHIFT
- APML_STATUS__APML_Serr_MASK
- APML_STATUS__APML_Serr__SHIFT
- APML_SW_STATUS__APML_NMI_STATUS_MASK
- APML_SW_STATUS__APML_NMI_STATUS__SHIFT
- APML_TRIGGER__APML_NMI_TRIGGER_MASK
- APML_TRIGGER__APML_NMI_TRIGGER__SHIFT
- APMONCTL_O_MARK
- APMPWBTOUT_O_MARK
- APMPWRBTN_MARK
- APMS3N_MARK
- APMS5N_MARK
- APMSCI_O_MARK
- APMSLPBTN_MARK
- APMS_CLK_VAL_MRB_FUNC_MODE
- APMU_AXICLK_EN
- APMU_AXIRST_DIS
- APMU_CCIC0
- APMU_CCIC1
- APMU_CLK
- APMU_CLK_OPS
- APMU_DFC
- APMU_DISP0
- APMU_DISP1
- APMU_ETH
- APMU_FNCLK_EN
- APMU_FNRST_DIS
- APMU_LCD
- APMU_MC_HW_SLP_TYPE
- APMU_MOH_IDLE_CFG
- APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ
- APMU_MOH_IDLE_CFG_MOH_IDLE
- APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW
- APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN
- APMU_MOH_IDLE_CFG_MOH_PWRDWN
- APMU_MOH_IDLE_CFG_MOH_PWR_SW
- APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN
- APMU_NAND
- APMU_PJ_IDLE_CFG
- APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK
- APMU_PJ_IDLE_CFG_L2_PWR_SW
- APMU_PJ_IDLE_CFG_PJ_IDLE
- APMU_PJ_IDLE_CFG_PJ_PWRDWN
- APMU_PJ_IDLE_CFG_PWR_SW
- APMU_PXA168_CFI_WAKE_CLR
- APMU_PXA168_KP_WAKE_CLR
- APMU_PXA168_MSP_WAKE_CLR
- APMU_PXA168_SD1_WAKE_CLR
- APMU_PXA168_SD2_WAKE_CLR
- APMU_PXA168_SD3_WAKE_CLR
- APMU_PXA168_SD4_WAKE_CLR
- APMU_PXA168_XD_WAKE_CLR
- APMU_REG
- APMU_SDH0
- APMU_SDH1
- APMU_SDH2
- APMU_SDH3
- APMU_SQU_CLK_GATE_CTRL
- APMU_SRAM_PWR_DWN
- APMU_USB
- APMU_VIRT_BASE
- APMU_WAKE_CLR
- APMVDDON_MARK
- APM_16_BIT_SUPPORT
- APM_16_CONNECTED
- APM_16_UNSUPPORTED
- APM_32_BIT_SUPPORT
- APM_32_CONNECTED
- APM_32_UNSUPPORTED
- APM_AC_BACKUP
- APM_AC_OFFLINE
- APM_AC_ONLINE
- APM_AC_UNKNOWN
- APM_BAD_DEVICE
- APM_BAD_FUNCTION
- APM_BAD_PARAM
- APM_BAD_STATE
- APM_BATTERY_FLAG_CHARGING
- APM_BATTERY_FLAG_CRITICAL
- APM_BATTERY_FLAG_HIGH
- APM_BATTERY_FLAG_LOW
- APM_BATTERY_FLAG_NOT_PRESENT
- APM_BATTERY_FLAG_UNKNOWN
- APM_BATTERY_STATUS_CHARGING
- APM_BATTERY_STATUS_CRITICAL
- APM_BATTERY_STATUS_HIGH
- APM_BATTERY_STATUS_LOW
- APM_BATTERY_STATUS_NOT_PRESENT
- APM_BATTERY_STATUS_UNKNOWN
- APM_BIOS_DISABLED
- APM_BIOS_DISENGAGED
- APM_BIOS_MAGIC
- APM_CAPABILITY_CHANGE
- APM_CAP_GLOBAL_STANDBY
- APM_CAP_GLOBAL_SUSPEND
- APM_CAP_RESUME_STANDBY_PCMCIA
- APM_CAP_RESUME_STANDBY_RING
- APM_CAP_RESUME_STANDBY_TIMER
- APM_CAP_RESUME_SUSPEND_PCMCIA
- APM_CAP_RESUME_SUSPEND_RING
- APM_CAP_RESUME_SUSPEND_TIMER
- APM_CHECK_TIMEOUT
- APM_CONNECTED
- APM_CPU_PART_POTENZA
- APM_CRITICAL
- APM_CRITICAL_RESUME
- APM_CRITICAL_SUSPEND
- APM_CS
- APM_CS_16
- APM_DECL_SEGS
- APM_DEVICE_ALL
- APM_DEVICE_BALL
- APM_DEVICE_BATTERY
- APM_DEVICE_BIOS
- APM_DEVICE_CLASS
- APM_DEVICE_DISPLAY
- APM_DEVICE_MASK
- APM_DEVICE_NETWORK
- APM_DEVICE_OEM
- APM_DEVICE_OLD_ALL
- APM_DEVICE_PARALLEL
- APM_DEVICE_PCMCIA
- APM_DEVICE_SERIAL
- APM_DEVICE_STORAGE
- APM_DISABLED
- APM_DO_POP_SEGS
- APM_DO_RESTORE_SEGS
- APM_DO_SAVE_SEGS
- APM_DO_ZERO_SEGS
- APM_DS
- APM_FUNC_16BIT_CONN
- APM_FUNC_32BIT_CONN
- APM_FUNC_BUSY
- APM_FUNC_DISABLE_RING
- APM_FUNC_DISABLE_TIMER
- APM_FUNC_DISCONN
- APM_FUNC_ENABLE_DEV_PM
- APM_FUNC_ENABLE_PM
- APM_FUNC_ENABLE_RING
- APM_FUNC_ENGAGE_PM
- APM_FUNC_GET_CAP
- APM_FUNC_GET_EVENT
- APM_FUNC_GET_RING
- APM_FUNC_GET_STATE
- APM_FUNC_GET_STATUS
- APM_FUNC_GET_TIMER
- APM_FUNC_IDLE
- APM_FUNC_INST_CHECK
- APM_FUNC_REAL_CONN
- APM_FUNC_RESTORE_BIOS
- APM_FUNC_RESUME_ON_RING
- APM_FUNC_RESUME_TIMER
- APM_FUNC_SET_STATE
- APM_FUNC_SET_TIMER
- APM_FUNC_TIMER
- APM_FUNC_TIMER_DISABLE
- APM_FUNC_TIMER_ENABLE
- APM_FUNC_TIMER_GET
- APM_FUNC_VERSION
- APM_HIBERNATION_RESUME
- APM_IDLE_SLOWS_CLOCK
- APM_IOC_STANDBY
- APM_IOC_SUSPEND
- APM_LOW
- APM_LOW_BATTERY
- APM_MAX_BATTERIES
- APM_MAX_EVENTS
- APM_MINOR_DEV
- APM_NORMAL_RESUME
- APM_NOT_CONNECTED
- APM_NOT_ENGAGED
- APM_NOT_PRESENT
- APM_NO_ERROR
- APM_NO_EVENTS
- APM_POWER_STATUS_CHANGE
- APM_RESUME_DISABLED
- APM_STANDBY_RESUME
- APM_STATE_BUSY
- APM_STATE_DISABLE
- APM_STATE_DISENGAGE
- APM_STATE_ENABLE
- APM_STATE_ENGAGE
- APM_STATE_OEM_DEV
- APM_STATE_OEM_SYS
- APM_STATE_OFF
- APM_STATE_READY
- APM_STATE_REJECT
- APM_STATE_STANDBY
- APM_STATE_SUSPEND
- APM_SUCCESS
- APM_SYS_STANDBY
- APM_SYS_SUSPEND
- APM_UNITS_MINS
- APM_UNITS_SECS
- APM_UNITS_UNKNOWN
- APM_UPDATE_TIME
- APM_USER_HIBERNATION
- APM_USER_STANDBY
- APM_USER_SUSPEND
- APM_ZERO_SEGS
- APN806_CLUSTER_NUM_MASK
- APN806_CLUSTER_NUM_OFFSET
- APN806_CPU1_MASK
- APN806_MAX_DIVIDER
- APOLLO_DISPLAY_IMG
- APOLLO_DN3000
- APOLLO_DN3010
- APOLLO_DN3500
- APOLLO_DN4000
- APOLLO_DN4500
- APOLLO_ERASE_DISPLAY
- APOLLO_INIT_DISPLAY
- APOLLO_INTR_SPREAD_BLOCKING_DURATION
- APOLLO_INTR_SPREAD_ENABLE
- APOLLO_INTR_SPREAD_USE_STANDBYWFI
- APOLLO_MOUSE_MINOR
- APOLLO_NR_CLK
- APOLLO_PLL_CON0
- APOLLO_PLL_CON1
- APOLLO_PLL_FREQ_DET
- APOLLO_PLL_LOCK
- APOLLO_PWR_CTRL
- APOLLO_PWR_CTRL2
- APOLLO_START_NEW_IMG
- APOLLO_STOP_IMG_DATA
- APOLLO_UNKNOWN
- APO_REG_GPIO_RW_SILICON_TUNER
- APO_REG_I2C_RW_CAN_TUNER
- APO_REG_I2C_RW_SILICON_TUNER
- APO_REG_RESET
- APO_REG_TRIGGER_OFSM
- APP0
- APP1_DL
- APP1_UL
- APP2_DL
- APP2_UL
- APPARMOR_COMPLAIN
- APPARMOR_ENFORCE
- APPARMOR_KILL
- APPARMOR_MODE_NAMES_MAX_INDEX
- APPARMOR_UNCONFINED
- APPEND_CMD
- APPEND_CMD_LEN
- APPEND_CMD_PTR
- APPEND_CMD_PTR_EXTLEN
- APPEND_CMD_PTR_LEN
- APPEND_CMD_PTR_TO_IMM
- APPEND_CMD_PTR_TO_IMM2
- APPEND_CMD_RAW_IMM
- APPEND_CMD_RAW_IMM2
- APPEND_CMD_RET
- APPEND_CRC
- APPEND_INO
- APPEND_MATH
- APPEND_MATH_IMM_u32
- APPEND_MATH_IMM_u64
- APPEND_NONE
- APPEND_PAD
- APPEND_SEQ_PTR_INTLEN
- APPEND_TAIL
- APPENV_MOBILE
- APPENV_PORTABLE
- APPENV_STATIC
- APPLDATA_ADD_TIMER
- APPLDATA_CPU_INTERVAL
- APPLDATA_DEL_TIMER
- APPLDATA_GEN_EVENT_REC
- APPLDATA_MAX_PROCS
- APPLDATA_MAX_REC_SIZE
- APPLDATA_MOD_TIMER
- APPLDATA_PROC_NAME_LENGTH
- APPLDATA_RECORD_MEM_ID
- APPLDATA_RECORD_NET_SUM_ID
- APPLDATA_RECORD_OS_ID
- APPLDATA_RECORD_PROC_ID
- APPLDATA_START_CONFIG_REC
- APPLDATA_START_INTERVAL_REC
- APPLDATA_STOP_REC
- APPLEARP_TYPE
- APPLEDISPLAY_DEVICE
- APPLESMC_CMD_PORT
- APPLESMC_DATA_PORT
- APPLESMC_GET_KEY_BY_INDEX_CMD
- APPLESMC_GET_KEY_TYPE_CMD
- APPLESMC_INPUT_FLAT
- APPLESMC_INPUT_FUZZ
- APPLESMC_MAX_DATA_LENGTH
- APPLESMC_MAX_WAIT
- APPLESMC_MIN_WAIT
- APPLESMC_NR_PORTS
- APPLESMC_POLL_INTERVAL
- APPLESMC_READ_CMD
- APPLESMC_RETRY_WAIT
- APPLESMC_WRITE_CMD
- APPLESPI_PACKET_SIZE
- APPLESPI_STATUS_SIZE
- APPLE_AUX_TYPE
- APPLE_FLAG_FKEY
- APPLE_HAS_FN
- APPLE_HIDDEV
- APPLE_IGNORE_HIDINPUT
- APPLE_IGNORE_MOUSE
- APPLE_INVERT_HWHEEL
- APPLE_MIGHTYMOUSE
- APPLE_NUMLOCK_EMULATION
- APPLE_PROPERTIES_PROTOCOL_GUID
- APPLE_RDESC_JIS
- APPLE_SONIC_PROM_BASE
- APPLE_SONIC_REGISTERS
- APPLE_VENDOR_ID
- APPLIED_RESERVED_QUEUE_IN_FW
- APPL_CAR_RESET_OVRD
- APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N
- APPL_CFG_BASE_ADDR
- APPL_CFG_BASE_ADDR_MASK
- APPL_CFG_IATU_DMA_BASE_ADDR
- APPL_CFG_IATU_DMA_BASE_ADDR_MASK
- APPL_CFG_MISC
- APPL_CFG_MISC_ARCACHE_MASK
- APPL_CFG_MISC_ARCACHE_SHIFT
- APPL_CFG_MISC_ARCACHE_VAL
- APPL_CFG_MISC_SLV_EP_MODE
- APPL_CFG_SLCG_OVERRIDE
- APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER
- APPL_CTRL
- APPL_CTRL_HW_HOT_RST_EN
- APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST
- APPL_CTRL_HW_HOT_RST_MODE_MASK
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT
- APPL_CTRL_LTSSM_EN
- APPL_CTRL_SYS_PRE_DET_STATE
- APPL_DEBUG
- APPL_DEBUG_LTSSM_STATE_MASK
- APPL_DEBUG_LTSSM_STATE_SHIFT
- APPL_DEBUG_PM_LINKST_IN_L0
- APPL_DEBUG_PM_LINKST_IN_L2_LAT
- APPL_DM_TYPE
- APPL_DM_TYPE_EP
- APPL_DM_TYPE_MASK
- APPL_DM_TYPE_RP
- APPL_INTR_EN_L0_0
- APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN
- APPL_INTR_EN_L0_0_INT_INT_EN
- APPL_INTR_EN_L0_0_LINK_STATE_INT_EN
- APPL_INTR_EN_L0_0_MSI_RCV_INT_EN
- APPL_INTR_EN_L0_0_SYS_INTR_EN
- APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN
- APPL_INTR_EN_L1_0_0
- APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN
- APPL_INTR_EN_L1_18
- APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT
- APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR
- APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR
- APPL_INTR_EN_L1_8_0
- APPL_INTR_EN_L1_8_AER_INT_EN
- APPL_INTR_EN_L1_8_AUTO_BW_INT_EN
- APPL_INTR_EN_L1_8_BW_MGT_INT_EN
- APPL_INTR_EN_L1_8_INTX_EN
- APPL_INTR_STATUS_L0
- APPL_INTR_STATUS_L0_CDM_REG_CHK_INT
- APPL_INTR_STATUS_L0_INT_INT
- APPL_INTR_STATUS_L0_LINK_STATE_INT
- APPL_INTR_STATUS_L1_0_0
- APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED
- APPL_INTR_STATUS_L1_1
- APPL_INTR_STATUS_L1_10
- APPL_INTR_STATUS_L1_11
- APPL_INTR_STATUS_L1_13
- APPL_INTR_STATUS_L1_14
- APPL_INTR_STATUS_L1_15
- APPL_INTR_STATUS_L1_17
- APPL_INTR_STATUS_L1_18
- APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT
- APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR
- APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR
- APPL_INTR_STATUS_L1_2
- APPL_INTR_STATUS_L1_3
- APPL_INTR_STATUS_L1_6
- APPL_INTR_STATUS_L1_7
- APPL_INTR_STATUS_L1_8_0
- APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS
- APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS
- APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK
- APPL_INTR_STATUS_L1_9
- APPL_LINK_STATUS
- APPL_LINK_STATUS_RDLH_LINK_UP
- APPL_LTR_MSG_1
- APPL_LTR_MSG_2
- APPL_LTR_MSG_2_LTR_MSG_REQ_STATE
- APPL_MSI_CTRL_2
- APPL_PINMUX
- APPL_PINMUX_CLKREQ_OUT_OVRD
- APPL_PINMUX_CLKREQ_OUT_OVRD_EN
- APPL_PINMUX_CLKREQ_OVERRIDE
- APPL_PINMUX_CLKREQ_OVERRIDE_EN
- APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE
- APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN
- APPL_PINMUX_PEX_RST
- APPL_PM_XMT_TURNOFF_STATE
- APPL_RADM_STATUS
- APPRAISE
- APPTAG_ERR
- APPTYPE_MIMD
- APPTYPE_UIOC
- APP_ADDR_SPACE_0
- APP_AIM
- APP_BASE_ID
- APP_BASSN
- APP_BUFFERED_IO
- APP_CFG_REQ
- APP_CHEYENNE
- APP_CHK_ERR
- APP_CMD
- APP_CPL_STATUS
- APP_CRC32
- APP_DIRECT_IO
- APP_DPTMGR
- APP_ENGINE
- APP_FCS
- APP_ICV
- APP_LTSSM_ENABLE
- APP_LTSSM_ENABLE_ID
- APP_MAPPED_IO
- APP_MIC
- APP_MSCDEX
- APP_NOVABACK
- APP_O
- APP_PARTITION_SIZE_KiB
- APP_PHYSTS
- APP_PLL_LCLK_CTL_REG
- APP_PLL_SCLK_CTL_REG
- APP_REQ_SEEN
- APP_RESP_SEEN
- APP_SYTOS
- APP_WRITE_IO
- APQ8096SG
- APQ8096V3
- APQ_MUX_NA
- APQ_MUX_adsp_ext
- APQ_MUX_audio_ref
- APQ_MUX_blsp_i2c1
- APQ_MUX_blsp_i2c10
- APQ_MUX_blsp_i2c11
- APQ_MUX_blsp_i2c12
- APQ_MUX_blsp_i2c2
- APQ_MUX_blsp_i2c3
- APQ_MUX_blsp_i2c4
- APQ_MUX_blsp_i2c5
- APQ_MUX_blsp_i2c6
- APQ_MUX_blsp_i2c7
- APQ_MUX_blsp_i2c8
- APQ_MUX_blsp_i2c9
- APQ_MUX_blsp_spi1
- APQ_MUX_blsp_spi10
- APQ_MUX_blsp_spi10_cs1
- APQ_MUX_blsp_spi10_cs2
- APQ_MUX_blsp_spi10_cs3
- APQ_MUX_blsp_spi11
- APQ_MUX_blsp_spi12
- APQ_MUX_blsp_spi1_cs1
- APQ_MUX_blsp_spi1_cs2
- APQ_MUX_blsp_spi1_cs3
- APQ_MUX_blsp_spi2
- APQ_MUX_blsp_spi3
- APQ_MUX_blsp_spi3_cs1
- APQ_MUX_blsp_spi3_cs2
- APQ_MUX_blsp_spi3_cs3
- APQ_MUX_blsp_spi4
- APQ_MUX_blsp_spi5
- APQ_MUX_blsp_spi6
- APQ_MUX_blsp_spi7
- APQ_MUX_blsp_spi8
- APQ_MUX_blsp_spi9
- APQ_MUX_blsp_uart1
- APQ_MUX_blsp_uart10
- APQ_MUX_blsp_uart11
- APQ_MUX_blsp_uart12
- APQ_MUX_blsp_uart2
- APQ_MUX_blsp_uart3
- APQ_MUX_blsp_uart4
- APQ_MUX_blsp_uart5
- APQ_MUX_blsp_uart6
- APQ_MUX_blsp_uart7
- APQ_MUX_blsp_uart8
- APQ_MUX_blsp_uart9
- APQ_MUX_blsp_uim1
- APQ_MUX_blsp_uim10
- APQ_MUX_blsp_uim11
- APQ_MUX_blsp_uim12
- APQ_MUX_blsp_uim2
- APQ_MUX_blsp_uim3
- APQ_MUX_blsp_uim4
- APQ_MUX_blsp_uim5
- APQ_MUX_blsp_uim6
- APQ_MUX_blsp_uim7
- APQ_MUX_blsp_uim8
- APQ_MUX_blsp_uim9
- APQ_MUX_cam_mclk
- APQ_MUX_cam_mclk0
- APQ_MUX_cam_mclk1
- APQ_MUX_cam_mclk2
- APQ_MUX_cam_mclk3
- APQ_MUX_cci_async
- APQ_MUX_cci_async_in0
- APQ_MUX_cci_i2c0
- APQ_MUX_cci_i2c1
- APQ_MUX_cci_timer0
- APQ_MUX_cci_timer1
- APQ_MUX_cci_timer2
- APQ_MUX_cci_timer3
- APQ_MUX_cci_timer4
- APQ_MUX_codec_mic_i2s
- APQ_MUX_codec_spkr_i2s
- APQ_MUX_edp_hpd
- APQ_MUX_gcc_gp1
- APQ_MUX_gcc_gp2
- APQ_MUX_gcc_gp3
- APQ_MUX_gcc_obt
- APQ_MUX_gcc_vtt
- APQ_MUX_gp0_clk
- APQ_MUX_gp1_clk
- APQ_MUX_gp_clk_0a
- APQ_MUX_gp_clk_0b
- APQ_MUX_gp_clk_1a
- APQ_MUX_gp_clk_1b
- APQ_MUX_gp_clk_2a
- APQ_MUX_gp_clk_2b
- APQ_MUX_gp_mn
- APQ_MUX_gp_pdm0
- APQ_MUX_gp_pdm1
- APQ_MUX_gp_pdm2
- APQ_MUX_gpio
- APQ_MUX_gsbi1
- APQ_MUX_gsbi2
- APQ_MUX_gsbi3
- APQ_MUX_gsbi4
- APQ_MUX_gsbi4_cam_i2c
- APQ_MUX_gsbi5
- APQ_MUX_gsbi5_spi_cs1
- APQ_MUX_gsbi5_spi_cs2
- APQ_MUX_gsbi5_spi_cs3
- APQ_MUX_gsbi6
- APQ_MUX_gsbi6_spi_cs1
- APQ_MUX_gsbi6_spi_cs2
- APQ_MUX_gsbi6_spi_cs3
- APQ_MUX_gsbi7
- APQ_MUX_gsbi7_spi_cs1
- APQ_MUX_gsbi7_spi_cs2
- APQ_MUX_gsbi7_spi_cs3
- APQ_MUX_gsbi_cam_i2c
- APQ_MUX_hdmi
- APQ_MUX_hdmi_cec
- APQ_MUX_hdmi_ddc
- APQ_MUX_hdmi_dtest
- APQ_MUX_hdmi_hpd
- APQ_MUX_hdmi_rcv
- APQ_MUX_hsic
- APQ_MUX_ldo_en
- APQ_MUX_ldo_update
- APQ_MUX_mdp_vsync
- APQ_MUX_mi2s
- APQ_MUX_pci_e0
- APQ_MUX_pci_e0_n
- APQ_MUX_pci_e0_rst
- APQ_MUX_pci_e1
- APQ_MUX_pci_e1_clkreq_n
- APQ_MUX_pci_e1_rst
- APQ_MUX_pci_e1_rst_n
- APQ_MUX_pri_mi2s
- APQ_MUX_ps_hold
- APQ_MUX_qua_mi2s
- APQ_MUX_riva_bt
- APQ_MUX_riva_fm
- APQ_MUX_riva_wlan
- APQ_MUX_sata_act
- APQ_MUX_sata_devsleep
- APQ_MUX_sata_devsleep_n
- APQ_MUX_sd_write
- APQ_MUX_sdc2
- APQ_MUX_sdc3
- APQ_MUX_sdc4
- APQ_MUX_sdc_emmc_mode
- APQ_MUX_sec_mi2s
- APQ_MUX_slimbus
- APQ_MUX_spdif_tx
- APQ_MUX_spkr_i2s
- APQ_MUX_spkr_i2s_ws
- APQ_MUX_spss_geni
- APQ_MUX_ter_mi2s
- APQ_MUX_tsif1
- APQ_MUX_tsif2
- APQ_MUX_uim
- APQ_MUX_uim_batt_alarm
- APQ_MUX_usb2_hsic
- APR
- APRINTK
- APRIV
- APRIV_MASK
- APRIV_SHIFT
- APROM_DN
- APROM_DT
- APROTNS
- APROTNS_MASK
- APROTNS_SHIFT
- APR_AP
- APR_BASIC_RSP_RESULT
- APR_BIT
- APR_DOMAIN_ADSP
- APR_DOMAIN_APPS
- APR_DOMAIN_MAX
- APR_DOMAIN_MODEM
- APR_DOMAIN_PC
- APR_DOMAIN_SIM
- APR_HDR_FIELD
- APR_HDR_FIELD_MT
- APR_HDR_FIELD_SIZE
- APR_HDR_FIELD_SIZE_BYTES
- APR_HDR_FIELD_VER
- APR_HDR_LEN
- APR_HDR_SIZE
- APR_MODULE_PREFIX
- APR_MSG_TYPE_CMD_RSP
- APR_MSG_TYPE_EVENT
- APR_MSG_TYPE_MAX
- APR_MSG_TYPE_NSEQ_CMD
- APR_MSG_TYPE_SEQ_CMD
- APR_NAME_SIZE
- APR_PKT_VER
- APR_RSP_ACCEPTED
- APR_SEQ_CMD_HDR_FIELD
- APR_SVC_ADM
- APR_SVC_ADSP_CORE
- APR_SVC_ADSP_CVP
- APR_SVC_ADSP_CVS
- APR_SVC_ADSP_MVM
- APR_SVC_AFE
- APR_SVC_ASM
- APR_SVC_LSM
- APR_SVC_MAJOR_VERSION
- APR_SVC_MAX
- APR_SVC_MINOR_VERSION
- APR_SVC_USM
- APR_SVC_VIDC
- APR_SVC_VPM
- APR_SVC_VSM
- APSDOFF
- APSDOFF_STATUS
- APSD_CTRL_OFF
- APSD_CTRL_OFF_STATUS
- APSK_16
- APSK_32
- APSR
- APSR_BIT
- APSR_CMSW
- APSR_DM
- APSR_DM_RDM
- APSR_DM_TDM
- APSR_MASK
- APSR_MEMS
- APSS_AHB_CLK_SRC
- APSS_TCU_CLK_SRC
- APS_FSMCO_ENABLE_POWERDOWN
- APS_FSMCO_HW_POWERDOWN
- APS_FSMCO_HW_SUSPEND
- APS_FSMCO_MAC_ENABLE
- APS_FSMCO_MAC_OFF
- APS_FSMCO_PCIE
- APS_FSMCO_PFM_ALDN
- APS_FSMCO_PFM_WOWL
- APS_FSMCO_SW_LPS
- APS_FSMCO_WLON_RESET
- APU
- APU1_FCH_ACPI_MMIO_BASE
- APU1_FCH_GPIO_BASE
- APU1_IOSIZE
- APU1_LEDOFF
- APU1_LEDON
- APU1_NUM_GPIO
- APU2_GPIO_LINE_LED1
- APU2_GPIO_LINE_LED2
- APU2_GPIO_LINE_LED3
- APU2_GPIO_LINE_MODESW
- APU2_GPIO_LINE_MPCIE2
- APU2_GPIO_LINE_MPCIE3
- APU2_GPIO_LINE_SIMSWAP
- APU2_GPIO_REG_LED1
- APU2_GPIO_REG_LED2
- APU2_GPIO_REG_LED3
- APU2_GPIO_REG_MODESW
- APU2_GPIO_REG_MPCIE2
- APU2_GPIO_REG_MPCIE3
- APU2_GPIO_REG_SIMSWAP
- APUOP
- APUOPFB
- APU_AHB_CLK
- APU_AHB_RESET
- APU_CMD_MASK
- APU_CMD_MASK_ACK
- APU_MASK
- APU_RA_MASK
- APU_ROM_SYNC1
- APU_ROM_SYNC2
- APU_RT_MASK
- APWRMGT
- AP_ADDR
- AP_BOOT
- AP_CLK
- AP_CONFIG_TIME
- AP_CONTROL_0
- AP_CONTROL_1
- AP_CONTROL_2
- AP_CONTROL_3A
- AP_DBF
- AP_DEAUTH_DELAY
- AP_DEBUG_H
- AP_DEEP_SLEEP
- AP_DEVICES
- AP_DEVICE_ID
- AP_DEVICE_ID_MATCH_CARD_TYPE
- AP_DEVICE_ID_MATCH_QUEUE_TYPE
- AP_DEVICE_TYPE_CEX2A
- AP_DEVICE_TYPE_CEX2C
- AP_DEVICE_TYPE_CEX3A
- AP_DEVICE_TYPE_CEX3C
- AP_DEVICE_TYPE_CEX4
- AP_DEVICE_TYPE_CEX5
- AP_DEVICE_TYPE_CEX6
- AP_DEVICE_TYPE_CEX7
- AP_DEVICE_TYPE_PCICA
- AP_DEVICE_TYPE_PCICC
- AP_DEVICE_TYPE_PCIXCC
- AP_DFS
- AP_DIAG_MEM_REQ
- AP_DISASSOC_DELAY
- AP_DISCOVERY_COMPLETE_EVENT_ID
- AP_DOMAINS
- AP_DRIVER_FLAG_DEFAULT
- AP_DUMP_ALL_TABLES
- AP_DUMP_TABLE_BY_ADDRESS
- AP_DUMP_TABLE_BY_FILE
- AP_DUMP_TABLE_BY_NAME
- AP_EVENT_POLL
- AP_EVENT_TIMEOUT
- AP_EXECUTE
- AP_FUNC_ACCEL
- AP_FUNC_APXA
- AP_FUNC_COPRO
- AP_FUNC_CRT4K
- AP_FUNC_EP11
- AP_FUNC_MEX4K
- AP_IDLE
- AP_INTR_DISABLED
- AP_INTR_ENABLED
- AP_IOBASE
- AP_IOCTLS
- AP_IPIMSG_DEC_DEINIT
- AP_IPIMSG_DEC_END
- AP_IPIMSG_DEC_INIT
- AP_IPIMSG_DEC_RESET
- AP_IPIMSG_DEC_START
- AP_IPIMSG_ENC_DEINIT
- AP_IPIMSG_ENC_ENCODE
- AP_IPIMSG_ENC_INIT
- AP_IPIMSG_ENC_SET_PARAM
- AP_IPIMSG_VENC_BASE
- AP_ISC
- AP_MAC_CMD_FLUSH
- AP_MAC_CMD_KICKALL
- AP_MAC_CMD_POLICY_ALLOW
- AP_MAC_CMD_POLICY_DENY
- AP_MAC_CMD_POLICY_OPEN
- AP_MAX_ACPI_FILES
- AP_MAX_ACTIONS
- AP_MAX_BC_BUFFER
- AP_MAX_INACTIVITY_SEC
- AP_MAX_NUM_STA
- AP_MDP_DEINIT
- AP_MDP_INIT
- AP_MDP_PROCESS
- AP_MKQID
- AP_NETWORK
- AP_OR_STATION_TABLE
- AP_OTHER_AP_ALL
- AP_OTHER_AP_EVEN_IBSS
- AP_OTHER_AP_SAME_SSID
- AP_OTHER_AP_SKIP_ALL
- AP_PHY0_ADDR_MASK
- AP_PHY1_ADDR_MASK
- AP_PHY1_DFLT
- AP_PHY2_ADDR_MASK
- AP_PHY2_DFLT
- AP_PHY3_ADDR_MASK
- AP_PHY3_DFLT
- AP_PHY4_ADDR_MASK
- AP_PHY4_DFLT
- AP_PHY5_ADDR_MASK
- AP_PHY5_DFLT
- AP_POLL_TIME
- AP_PRE_SUP1
- AP_PRE_SUP2
- AP_PRE_SUP3
- AP_PRE_SUP4
- AP_PRE_SUP5
- AP_PWR_DOWN
- AP_QID_CARD
- AP_QID_QUEUE
- AP_REG0_ADDR_MASK
- AP_REG0_EN
- AP_REG1_ADDR_MASK
- AP_REG1_EN
- AP_REG2_ADDR_MASK
- AP_REG2_EN
- AP_REG3_ADDR_MASK
- AP_REG3_EN
- AP_REG4_ADDR_MASK
- AP_REG4_EN
- AP_REG5_ADDR_MASK
- AP_REG5_EN
- AP_RESET
- AP_RESET_TIMEOUT
- AP_RESPONSE_BUSY
- AP_RESPONSE_CHECKSTOPPED
- AP_RESPONSE_DECONFIGURED
- AP_RESPONSE_INDEX_TOO_BIG
- AP_RESPONSE_INVALID_ADDRESS
- AP_RESPONSE_MESSAGE_TOO_BIG
- AP_RESPONSE_NORMAL
- AP_RESPONSE_NO_FIRST_PART
- AP_RESPONSE_NO_PENDING_REPLY
- AP_RESPONSE_OTHERWISE_CHANGED
- AP_RESPONSE_Q_FULL
- AP_RESPONSE_Q_NOT_AVAIL
- AP_RESPONSE_REQ_FAC_NOT_INST
- AP_RESPONSE_RESET_IN_PROGRESS
- AP_ROP_1
- AP_RX_CONTINUE
- AP_RX_CONTINUE_NOT_AUTHORIZED
- AP_RX_DROP
- AP_RX_EXIT
- AP_SETTINGS_EXTERNAL_AUTH_SUPPORT
- AP_SLEEP
- AP_SLEEP_MODE
- AP_STATE_BORKED
- AP_STATE_IDLE
- AP_STATE_QUEUE_FULL
- AP_STATE_REMOVE
- AP_STATE_RESET_START
- AP_STATE_RESET_WAIT
- AP_STATE_SETIRQ_WAIT
- AP_STATE_SUSPEND_WAIT
- AP_STATE_UNBOUND
- AP_STATE_WORKING
- AP_STATUS
- AP_SUPPORTED_OPTIONS
- AP_SUSPEND
- AP_TX_BUFFERED
- AP_TX_CONTINUE
- AP_TX_CONTINUE_NOT_AUTHORIZED
- AP_TX_DROP
- AP_TX_RETRY
- AP_UAPSD
- AP_UTILITY_NAME
- AP_VAL
- AP_VALUE
- AP_VALUE_BITS
- AP_VAL_ACTIVE
- AP_VAL_RD_CMD
- AP_WAIT_AGAIN
- AP_WAIT_INTERRUPT
- AP_WAIT_NONE
- AP_WAIT_TIMEOUT
- AP_WOWLAN_PAGE_NUM_8723B
- AP_WRITE_ENABLE
- AP_WakeUp
- APnBTR
- APnDPXR
- APnDPYR
- APnDSA0R
- APnDSA1R
- APnDSA2R
- APnDSXR
- APnDSYR
- APnMLR
- APnMR
- APnMR_BM_AD
- APnMR_BM_MD
- APnMR_DC
- APnMR_WAE
- APnMWR
- APnSPXR
- APnSPYR
- APnSWAPR
- APnWAMWR
- APnWASPR
- AQC111_USB_ETH_DEV
- AQCSFRC
- AQCSFRC_CSFA_DISSWFRC
- AQCSFRC_CSFA_FRCDIS
- AQCSFRC_CSFA_FRCHIGH
- AQCSFRC_CSFA_FRCLOW
- AQCSFRC_CSFA_MASK
- AQCSFRC_CSFB_DISSWFRC
- AQCSFRC_CSFB_FRCDIS
- AQCSFRC_CSFB_FRCHIGH
- AQCSFRC_CSFB_FRCLOW
- AQCSFRC_CSFB_MASK
- AQCTLA
- AQCTLB
- AQCTL_CAU_FRCHIGH
- AQCTL_CAU_FRCLOW
- AQCTL_CAU_FRCTOGGLE
- AQCTL_CAU_MASK
- AQCTL_CBU_FRCHIGH
- AQCTL_CBU_FRCLOW
- AQCTL_CBU_FRCTOGGLE
- AQCTL_CBU_MASK
- AQCTL_CHANA_POLINVERSED
- AQCTL_CHANA_POLNORMAL
- AQCTL_CHANB_POLINVERSED
- AQCTL_CHANB_POLNORMAL
- AQCTL_PRD_FRCHIGH
- AQCTL_PRD_FRCLOW
- AQCTL_PRD_FRCTOGGLE
- AQCTL_PRD_MASK
- AQCTL_ZRO_FRCHIGH
- AQCTL_ZRO_FRCLOW
- AQCTL_ZRO_FRCTOGGLE
- AQCTL_ZRO_MASK
- AQL_ENABLE
- AQMQ_ACTIVITY_STATX
- AQMQ_BADRX
- AQMQ_CMD_CNTX
- AQMQ_CMP_CNTX
- AQMQ_CMP_THRX
- AQMQ_DRBLX
- AQMQ_ENX
- AQMQ_NXT_CMDX
- AQMQ_QSZX
- AQMQ_TIMERX
- AQMQ_TIM_LDX
- AQM_ACTIVITY_STAT_HI
- AQM_ACTIVITY_STAT_LO
- AQM_BIST_STATUS
- AQM_CMD_INFX
- AQM_CMD_INF_THRX
- AQM_CTL
- AQM_DBELL_OVF_HI
- AQM_DBELL_OVF_HI_ENA_W1C
- AQM_DBELL_OVF_HI_ENA_W1S
- AQM_DBELL_OVF_HI_W1S
- AQM_DBELL_OVF_LO
- AQM_DBELL_OVF_LO_ENA_W1C
- AQM_DBELL_OVF_LO_ENA_W1S
- AQM_DBELL_OVF_LO_W1S
- AQM_DMA_RD_ERR_HI
- AQM_DMA_RD_ERR_HI_ENA_W1C
- AQM_DMA_RD_ERR_HI_ENA_W1S
- AQM_DMA_RD_ERR_HI_W1S
- AQM_DMA_RD_ERR_LO
- AQM_DMA_RD_ERR_LO_ENA_W1C
- AQM_DMA_RD_ERR_LO_ENA_W1S
- AQM_DMA_RD_ERR_LO_W1S
- AQM_ECC_CTL
- AQM_ECC_INT
- AQM_ECC_INT_ENA_W1C
- AQM_ECC_INT_ENA_W1S
- AQM_ECC_INT_W1S
- AQM_EXEC_ERR_HI
- AQM_EXEC_ERR_HI_ENA_W1C
- AQM_EXEC_ERR_HI_ENA_W1S
- AQM_EXEC_ERR_HI_W1S
- AQM_EXEC_ERR_LO
- AQM_EXEC_ERR_LO_ENA_W1C
- AQM_EXEC_ERR_LO_ENA_W1S
- AQM_EXEC_ERR_LO_W1S
- AQM_EXEC_NA_HI
- AQM_EXEC_NA_HI_ENA_W1C
- AQM_EXEC_NA_HI_ENA_W1S
- AQM_EXEC_NA_HI_W1S
- AQM_EXEC_NA_LO
- AQM_EXEC_NA_LO_ENA_W1C
- AQM_EXEC_NA_LO_ENA_W1S
- AQM_EXEC_NA_LO_W1S
- AQM_GRP_EXECMSK_HIX
- AQM_GRP_EXECMSK_LOX
- AQM_INT
- AQM_PERF_CNT
- AQM_PERF_CTL_HI
- AQM_PERF_CTL_LO
- AQM_Q_ALIGN_BYTES
- AQM_Q_CMD_PROCX
- AQM_TXQ_ENTRY_LEN
- AQM_VF_CMP_STATX
- AQR107_SGMII_STAT_SZ
- AQSFRC
- AQSFRC_RLDCSF_IMDT
- AQSFRC_RLDCSF_MASK
- AQSFRC_RLDCSF_PRD
- AQSFRC_RLDCSF_ZRO
- AQSFRC_RLDCSF_ZROPRD
- AQUANTIA_VENDOR_ID
- AQ_1G_CTRL
- AQ_ACCESS_MAC
- AQ_ADV_100M
- AQ_ADV_1G
- AQ_ADV_2G5
- AQ_ADV_5G
- AQ_ADV_MASK
- AQ_ANEG_STAT
- AQ_ASYM_PAUSE
- AQ_CFG_DRV_AUTHOR
- AQ_CFG_DRV_DESC
- AQ_CFG_DRV_NAME
- AQ_CFG_DRV_VERSION
- AQ_CFG_DRV_VERSION_SUFFIX
- AQ_CFG_FC_MODE
- AQ_CFG_FORCE_LEGACY_INT
- AQ_CFG_H
- AQ_CFG_INTERRUPT_MODERATION_AUTO
- AQ_CFG_INTERRUPT_MODERATION_OFF
- AQ_CFG_INTERRUPT_MODERATION_ON
- AQ_CFG_INTERRUPT_MODERATION_USEC_MAX
- AQ_CFG_IRQ_MASK
- AQ_CFG_IS_AUTONEG_DEF
- AQ_CFG_IS_LRO_DEF
- AQ_CFG_IS_POLLING_DEF
- AQ_CFG_IS_RSS_DEF
- AQ_CFG_LOCK_TRYS
- AQ_CFG_MTU_DEF
- AQ_CFG_NAPI_WEIGHT
- AQ_CFG_NUM_RSS_QUEUES_DEF
- AQ_CFG_PCI_FUNC_MSIX_IRQS
- AQ_CFG_PCI_FUNC_PORTS
- AQ_CFG_POLLING_TIMER_INTERVAL
- AQ_CFG_RESTART_DESC_THRES
- AQ_CFG_RSS_BASE_CPU_NUM_DEF
- AQ_CFG_RSS_HASHKEY_SIZE
- AQ_CFG_RSS_INDIRECTION_TABLE_MAX
- AQ_CFG_RXDS_DEF
- AQ_CFG_RX_FRAME_MAX
- AQ_CFG_RX_HDR_SIZE
- AQ_CFG_RX_PAGEORDER
- AQ_CFG_RX_REFILL_THRES
- AQ_CFG_SERVICE_TIMER_INTERVAL
- AQ_CFG_SKB_FRAGS_MAX
- AQ_CFG_SPEED_MSK
- AQ_CFG_TCS_DEF
- AQ_CFG_TCS_MAX
- AQ_CFG_TXDS_DEF
- AQ_CFG_TX_CLEAN_BUDGET
- AQ_CFG_TX_FRAME_MAX
- AQ_CFG_VECS_DEF
- AQ_CFG_VECS_MAX
- AQ_COMMON_H
- AQ_DEVICE_ID_0001
- AQ_DEVICE_ID_AQC100
- AQ_DEVICE_ID_AQC100S
- AQ_DEVICE_ID_AQC107
- AQ_DEVICE_ID_AQC107S
- AQ_DEVICE_ID_AQC108
- AQ_DEVICE_ID_AQC108S
- AQ_DEVICE_ID_AQC109
- AQ_DEVICE_ID_AQC109S
- AQ_DEVICE_ID_AQC111
- AQ_DEVICE_ID_AQC111S
- AQ_DEVICE_ID_AQC112
- AQ_DEVICE_ID_AQC112S
- AQ_DEVICE_ID_D100
- AQ_DEVICE_ID_D107
- AQ_DEVICE_ID_D108
- AQ_DEVICE_ID_D109
- AQ_DOWNSHIFT
- AQ_DRVINFO_H
- AQ_DSH_RETRIES_MASK
- AQ_DSH_RETRIES_SHIFT
- AQ_ETHTOOL_H
- AQ_FILTERS_H
- AQ_FLASH_PARAMETERS
- AQ_FW_REV
- AQ_FW_VERSION
- AQ_FW_VER_MAJOR
- AQ_FW_VER_MINOR
- AQ_FW_VER_REV
- AQ_HWREV_1
- AQ_HWREV_2
- AQ_HWREV_ANY
- AQ_HW_FLAG_CLOSING
- AQ_HW_FLAG_ERRORS
- AQ_HW_FLAG_ERR_HW
- AQ_HW_FLAG_ERR_UNPLUG
- AQ_HW_FLAG_RESETTING
- AQ_HW_FLAG_STARTED
- AQ_HW_FLAG_STOPPING
- AQ_HW_H
- AQ_HW_IRQ_INVALID
- AQ_HW_IRQ_LEGACY
- AQ_HW_IRQ_MSI
- AQ_HW_IRQ_MSIX
- AQ_HW_LINK_DOWN
- AQ_HW_MEDIA_TYPE_FIBRE
- AQ_HW_MEDIA_TYPE_TP
- AQ_HW_MULTICAST_ADDRESS_MAX
- AQ_HW_POWER_STATE_D0
- AQ_HW_POWER_STATE_D3
- AQ_HW_RXD_MULTIPLE
- AQ_HW_SERVICE_IRQS
- AQ_HW_SLEEP
- AQ_HW_TXD_MULTIPLE
- AQ_HW_UTILS_H
- AQ_IFLAG_GLOBAL
- AQ_IMASK_GLOBAL
- AQ_IMASK_PMA
- AQ_INT_SPEED_100M
- AQ_INT_SPEED_1G
- AQ_INT_SPEED_2_5G
- AQ_INT_SPEED_5G
- AQ_LINK_STAT
- AQ_LOWPOWER
- AQ_LOW_POWER
- AQ_LS_MASK
- AQ_MAIN_H
- AQ_MAX_MCAST
- AQ_MCAST_FILTER_SIZE
- AQ_NIC_FC_AUTO
- AQ_NIC_FC_FULL
- AQ_NIC_FC_OFF
- AQ_NIC_FC_RX
- AQ_NIC_FC_TX
- AQ_NIC_FLAGS_IS_NOT_READY
- AQ_NIC_FLAGS_IS_NOT_TX_READY
- AQ_NIC_FLAG_CLOSING
- AQ_NIC_FLAG_ERR_HW
- AQ_NIC_FLAG_ERR_UNPLUG
- AQ_NIC_FLAG_RESETTING
- AQ_NIC_FLAG_STARTED
- AQ_NIC_FLAG_STOPPING
- AQ_NIC_H
- AQ_NIC_LINK_DOWN
- AQ_NIC_RATE_100M
- AQ_NIC_RATE_10G
- AQ_NIC_RATE_1G
- AQ_NIC_RATE_2GS
- AQ_NIC_RATE_5G
- AQ_NIC_RATE_5GSR
- AQ_NIC_RATE_EEE_10G
- AQ_NIC_RATE_EEE_1G
- AQ_NIC_RATE_EEE_2GS
- AQ_NIC_RATE_EEE_5G
- AQ_NIC_TCVEC2RING
- AQ_NIC_WOL_ENABLED
- AQ_PAUSE
- AQ_PCI_FUNC_H
- AQ_PHY_OPS
- AQ_PHY_POWER
- AQ_PHY_POWER_EN
- AQ_PTR_MASK
- AQ_RESET
- AQ_RING_H
- AQ_RSS_H
- AQ_RX_DH_DESC_OFFSET_MASK
- AQ_RX_DH_DESC_OFFSET_SHIFT
- AQ_RX_DH_PKT_CNT_MASK
- AQ_RX_FIRST_LOC_FETHERT
- AQ_RX_FIRST_LOC_FL3L4
- AQ_RX_FIRST_LOC_FVLANID
- AQ_RX_HW_PAD
- AQ_RX_LAST_LOC_FETHERT
- AQ_RX_LAST_LOC_FL3L4
- AQ_RX_LAST_LOC_FVLANID
- AQ_RX_MAX_RXNFC_LOC
- AQ_RX_PD_DROP
- AQ_RX_PD_L3_ERR
- AQ_RX_PD_L3_IP
- AQ_RX_PD_L3_IP6
- AQ_RX_PD_L3_TYPE_MASK
- AQ_RX_PD_L4_ERR
- AQ_RX_PD_L4_TCP
- AQ_RX_PD_L4_TYPE_MASK
- AQ_RX_PD_L4_UDP
- AQ_RX_PD_LEN_MASK
- AQ_RX_PD_LEN_SHIFT
- AQ_RX_PD_RX_OK
- AQ_RX_PD_VLAN
- AQ_RX_PD_VLAN_SHIFT
- AQ_RX_QUEUE_NOT_ASSIGNED
- AQ_SDELTA
- AQ_SIZE
- AQ_SKB_ALIGN
- AQ_SPEED_MASK
- AQ_SPEED_SHIFT
- AQ_SUPPORT_FEATURE
- AQ_SUPPORT_HW_FEATURE
- AQ_SUPPORT_VLAN_FEATURE
- AQ_TX_DESC_DROP_PADD
- AQ_TX_DESC_LEN_MASK
- AQ_TX_DESC_MSS_MASK
- AQ_TX_DESC_MSS_SHIFT
- AQ_TX_DESC_VLAN
- AQ_TX_DESC_VLAN_MASK
- AQ_TX_DESC_VLAN_SHIFT
- AQ_USB_PHY_SET_TIMEOUT
- AQ_USB_SET_TIMEOUT
- AQ_UTILS_H
- AQ_VEC_H
- AQ_VEC_RX_ID
- AQ_VEC_TX_ID
- AQ_VLAN_MAX_FILTERS
- AQ_WOL
- AQ_WOL_CFG
- AQ_WOL_FLAG_MP
- AQ_XAUI_RX_CFG
- AQ_XAUI_TX_CFG
- AR
- AR1021_CMD
- AR1021_CMD_ENABLE_TOUCH
- AR1021_MAX_X
- AR1021_MAX_Y
- AR1021_TOCUH_PKG_SIZE
- AR2313_CLOCKCTL1_DOUBLER_MASK
- AR2313_CLOCKCTL1_MULTIPLIER_MASK
- AR2313_CLOCKCTL1_MULTIPLIER_SHIFT
- AR2313_CLOCKCTL1_PREDIVIDE_MASK
- AR2313_CLOCKCTL1_PREDIVIDE_SHIFT
- AR2315_AHB_ARB_CTL
- AR2315_AHB_ERR0
- AR2315_AHB_ERR1
- AR2315_AHB_ERR2
- AR2315_AHB_ERR3
- AR2315_AHB_ERR4
- AR2315_AHB_ERROR_DET
- AR2315_AHB_ERROR_OVR
- AR2315_AHB_ERROR_WDT
- AR2315_AMBACLK
- AR2315_AMBACLK_CLK_DIV_M
- AR2315_AMBACLK_CLK_DIV_S
- AR2315_AMBACLK_CLK_SEL_M
- AR2315_AMBACLK_CLK_SEL_S
- AR2315_ARB_CPU
- AR2315_ARB_ETHERNET
- AR2315_ARB_LOCAL
- AR2315_ARB_MPEGTS_RSVD
- AR2315_ARB_PCI
- AR2315_ARB_RETRY
- AR2315_ARB_WLAN
- AR2315_COLD_RESET
- AR2315_CONFIG_AHB
- AR2315_CONFIG_BIG
- AR2315_CONFIG_CPU
- AR2315_CONFIG_CPU_DRAM
- AR2315_CONFIG_CPU_MMR
- AR2315_CONFIG_CPU_PCI
- AR2315_CONFIG_ETHERNET
- AR2315_CONFIG_LOCAL
- AR2315_CONFIG_MEMCTL
- AR2315_CONFIG_MERGE
- AR2315_CONFIG_MPEGTS_RSVD
- AR2315_CONFIG_PCI
- AR2315_CONFIG_PCIAHB
- AR2315_CONFIG_PCIAHB_BRIDGE
- AR2315_CONFIG_SPI
- AR2315_CONFIG_WLAN
- AR2315_CPUCLK
- AR2315_CPUCLK_CLK_DIV_M
- AR2315_CPUCLK_CLK_DIV_S
- AR2315_CPUCLK_CLK_SEL_M
- AR2315_CPUCLK_CLK_SEL_S
- AR2315_DSL_SLEEP_CTL
- AR2315_DSL_SLEEP_DUR
- AR2315_ENDIAN_CTL
- AR2315_ENET0_BASE
- AR2315_GISR
- AR2315_GISR_ETHERNET
- AR2315_GISR_LOCALPCI
- AR2315_GISR_MISC
- AR2315_GISR_MPEGTS_RSVD
- AR2315_GISR_TIMER
- AR2315_GISR_WLAN0
- AR2315_GISR_WMACPOLL
- AR2315_IF_ALL
- AR2315_IF_CTL
- AR2315_IF_DISABLED
- AR2315_IF_LOCAL_HOST
- AR2315_IF_MASK
- AR2315_IF_PCI
- AR2315_IF_PCI_CLK_INPUT
- AR2315_IF_PCI_CLK_MASK
- AR2315_IF_PCI_CLK_OUTPUT_CLK
- AR2315_IF_PCI_CLK_OUTPUT_HIGH
- AR2315_IF_PCI_CLK_OUTPUT_LOW
- AR2315_IF_PCI_CLK_SHIFT
- AR2315_IF_PCI_HOST
- AR2315_IF_PCI_INTR
- AR2315_IF_TS_LOCAL
- AR2315_IMR
- AR2315_IRQ_ENET0
- AR2315_IRQ_LCBUS_PCI
- AR2315_IRQ_MISC
- AR2315_IRQ_WLAN0
- AR2315_IRQ_WLAN0_POLL
- AR2315_ISR
- AR2315_ISR_AHB
- AR2315_ISR_APB
- AR2315_ISR_GPIO
- AR2315_ISR_I2C_RSVD
- AR2315_ISR_IR_RSVD
- AR2315_ISR_SPI
- AR2315_ISR_TIMER
- AR2315_ISR_UART0
- AR2315_ISR_WD
- AR2315_LB1MS_MASK
- AR2315_LBCLK_EXT
- AR2315_LBCONF_16DATA
- AR2315_LBCONF_8CS
- AR2315_LBCONF_8DS
- AR2315_LBCONF_ADDT_MUX
- AR2315_LBCONF_ADR_OE
- AR2315_LBCONF_ADS
- AR2315_LBCONF_ADS_EN
- AR2315_LBCONF_CS0
- AR2315_LBCONF_CS1
- AR2315_LBCONF_DATA_OE
- AR2315_LBCONF_ENABLE
- AR2315_LBCONF_INT
- AR2315_LBCONF_INT_CTR0
- AR2315_LBCONF_INT_CTR1
- AR2315_LBCONF_INT_CTR2
- AR2315_LBCONF_INT_CTR3
- AR2315_LBCONF_INT_PULSE
- AR2315_LBCONF_MOT
- AR2315_LBCONF_OE
- AR2315_LBCONF_RDY
- AR2315_LBCONF_RDY_WAIT
- AR2315_LBCONF_SWAPDT
- AR2315_LBCONF_SYNC
- AR2315_LBCONF_WAIT
- AR2315_LBCONF_WE
- AR2315_LBM_MBOXRD_INTEN
- AR2315_LBM_MBOXWR_INTEN
- AR2315_LBM_PORTMUX
- AR2315_LBM_RX_INTEN
- AR2315_LBM_TIMEOUT_M
- AR2315_LBM_TIMEOUT_S
- AR2315_LBM_TXD_EN
- AR2315_LB_1MS
- AR2315_LB_CLKSEL
- AR2315_LB_CONFIG
- AR2315_LB_INT_EN
- AR2315_LB_INT_LB_ERR
- AR2315_LB_INT_LB_TIMEOUT
- AR2315_LB_INT_MASK
- AR2315_LB_INT_MBOX_RD
- AR2315_LB_INT_MBOX_WR
- AR2315_LB_INT_RX_DESC
- AR2315_LB_INT_RX_EOF
- AR2315_LB_INT_RX_ERR
- AR2315_LB_INT_RX_OK
- AR2315_LB_INT_STATUS
- AR2315_LB_INT_TX_DESC
- AR2315_LB_INT_TX_EOF
- AR2315_LB_INT_TX_ERR
- AR2315_LB_INT_TX_OK
- AR2315_LB_INT_TX_STARVE
- AR2315_LB_INT_TX_TRUNC
- AR2315_LB_MBOX
- AR2315_LB_MISCCFG
- AR2315_LB_RXEN
- AR2315_LB_RXTSOFF
- AR2315_LB_RX_CHAIN_DIS
- AR2315_LB_RX_CHAIN_EN
- AR2315_LB_RX_DESC_PTR
- AR2315_LB_TXEN_0
- AR2315_LB_TXEN_1
- AR2315_LB_TXEN_2
- AR2315_LB_TXEN_3
- AR2315_LB_TX_CHAIN_DIS
- AR2315_LB_TX_CHAIN_EN
- AR2315_LB_TX_DESC_PTR
- AR2315_LMB_DESCSWAP_EN
- AR2315_LOCAL_BASE
- AR2315_MEM_CFG
- AR2315_MEM_CFG_BANKADDR_BITS_M
- AR2315_MEM_CFG_BANKADDR_BITS_S
- AR2315_MEM_CFG_COL_WIDTH_M
- AR2315_MEM_CFG_COL_WIDTH_S
- AR2315_MEM_CFG_DATA_WIDTH_M
- AR2315_MEM_CFG_DATA_WIDTH_S
- AR2315_MEM_CFG_ROW_WIDTH_M
- AR2315_MEM_CFG_ROW_WIDTH_S
- AR2315_MEM_CTRL
- AR2315_MEM_REF
- AR2315_MISCCLK
- AR2315_MISCCLK_PLLBYPASS_EN
- AR2315_MISCCLK_PROCREFCLK
- AR2315_MISC_IRQ_AHB
- AR2315_MISC_IRQ_APB
- AR2315_MISC_IRQ_COUNT
- AR2315_MISC_IRQ_GPIO
- AR2315_MISC_IRQ_I2C_RSVD
- AR2315_MISC_IRQ_IR_RSVD
- AR2315_MISC_IRQ_SPI
- AR2315_MISC_IRQ_TIMER
- AR2315_MISC_IRQ_UART0
- AR2315_MISC_IRQ_WATCHDOG
- AR2315_NMI_CTL
- AR2315_NMI_EN
- AR2315_OCR
- AR2315_OCR_GPIO0_IRIN
- AR2315_OCR_GPIO1_IROUT
- AR2315_OCR_GPIO3_RXCLR
- AR2315_PCICACHE_DIS
- AR2315_PCICLK
- AR2315_PCICLK_DIV_M
- AR2315_PCICLK_DIV_S
- AR2315_PCICLK_INPUT_M
- AR2315_PCICLK_INPUT_S
- AR2315_PCICLK_IN_FREQ
- AR2315_PCICLK_IN_FREQ_DIV_10
- AR2315_PCICLK_IN_FREQ_DIV_6
- AR2315_PCICLK_IN_FREQ_DIV_8
- AR2315_PCICLK_PLLC_CLKC
- AR2315_PCICLK_PLLC_CLKM
- AR2315_PCICLK_PLLC_CLKM1
- AR2315_PCICLK_REF_CLK
- AR2315_PCIGRANT_EN
- AR2315_PCIGRANT_FRAME
- AR2315_PCIGRANT_GAP
- AR2315_PCIGRANT_IDLE
- AR2315_PCIMISC_CFG_SEL
- AR2315_PCIMISC_GIG_MASK
- AR2315_PCIMISC_RST_MODE
- AR2315_PCIMISC_TXD_EN
- AR2315_PCIRST_HIGH
- AR2315_PCIRST_INPUT
- AR2315_PCIRST_LOW
- AR2315_PCI_1MS_MASK
- AR2315_PCI_1MS_REG
- AR2315_PCI_BASE
- AR2315_PCI_CFG_SIZE
- AR2315_PCI_EXT_BASE
- AR2315_PCI_EXT_SIZE
- AR2315_PCI_HOST_DEVID
- AR2315_PCI_HOST_IN_DIS
- AR2315_PCI_HOST_IN_EN
- AR2315_PCI_HOST_IN_PTR
- AR2315_PCI_HOST_MBAR0
- AR2315_PCI_HOST_MBAR1
- AR2315_PCI_HOST_MBAR2
- AR2315_PCI_HOST_OUT_DIS
- AR2315_PCI_HOST_OUT_EN
- AR2315_PCI_HOST_OUT_PTR
- AR2315_PCI_HOST_SDRAM_BASEADDR
- AR2315_PCI_HOST_SLOT
- AR2315_PCI_IER
- AR2315_PCI_IER_DISABLE
- AR2315_PCI_IER_ENABLE
- AR2315_PCI_IMR
- AR2315_PCI_INT_ABORT
- AR2315_PCI_INT_DESCMASK
- AR2315_PCI_INT_EXT
- AR2315_PCI_INT_RX
- AR2315_PCI_INT_RXEOL
- AR2315_PCI_INT_RXERR
- AR2315_PCI_INT_RXOK
- AR2315_PCI_INT_TX
- AR2315_PCI_INT_TXEOL
- AR2315_PCI_INT_TXERR
- AR2315_PCI_INT_TXOK
- AR2315_PCI_INT_TXOOD
- AR2315_PCI_IN_DIS
- AR2315_PCI_IN_DIS0
- AR2315_PCI_IN_DIS1
- AR2315_PCI_IN_DIS2
- AR2315_PCI_IN_DIS3
- AR2315_PCI_IN_EN
- AR2315_PCI_IN_EN0
- AR2315_PCI_IN_EN1
- AR2315_PCI_IN_EN2
- AR2315_PCI_IN_EN3
- AR2315_PCI_IN_PTR
- AR2315_PCI_IRQ_ABORT
- AR2315_PCI_IRQ_COUNT
- AR2315_PCI_IRQ_EXT
- AR2315_PCI_ISR
- AR2315_PCI_MISC_CONFIG
- AR2315_PCI_OUT_DIS
- AR2315_PCI_OUT_DIS0
- AR2315_PCI_OUT_EN
- AR2315_PCI_OUT_EN0
- AR2315_PCI_OUT_PTR
- AR2315_PCI_OUT_TSTAMP
- AR2315_PCI_SIZE
- AR2315_PCI_UNCACHE_CFG
- AR2315_PERF0_ACTIVE
- AR2315_PERF0_DATAHIT
- AR2315_PERF0_DATAMISS
- AR2315_PERF0_INSTHIT
- AR2315_PERF0_INSTMISS
- AR2315_PERF0_WBHIT
- AR2315_PERF0_WBMISS
- AR2315_PERF1_EB_ARDY
- AR2315_PERF1_EB_AVALID
- AR2315_PERF1_EB_RDVAL
- AR2315_PERF1_EB_WDRDY
- AR2315_PERF1_VRADDR
- AR2315_PERF1_VWADDR
- AR2315_PERF1_VWDATA
- AR2315_PERFCNT0
- AR2315_PERFCNT1
- AR2315_PLLC_ADD_FDBACK_DIV_M
- AR2315_PLLC_ADD_FDBACK_DIV_S
- AR2315_PLLC_CLKC_DIV_M
- AR2315_PLLC_CLKC_DIV_S
- AR2315_PLLC_CLKM_DIV_M
- AR2315_PLLC_CLKM_DIV_S
- AR2315_PLLC_CTL
- AR2315_PLLC_FDBACK_DIV_M
- AR2315_PLLC_FDBACK_DIV_S
- AR2315_PLLC_REF_DIV_M
- AR2315_PLLC_REF_DIV_S
- AR2315_PLLV_CTL
- AR2315_PROCERR_HBURST
- AR2315_PROCERR_HBURST_S
- AR2315_PROCERR_HMAST
- AR2315_PROCERR_HMAST_CPU
- AR2315_PROCERR_HMAST_DFLT
- AR2315_PROCERR_HMAST_ENET
- AR2315_PROCERR_HMAST_LOCAL
- AR2315_PROCERR_HMAST_PCIENDPT
- AR2315_PROCERR_HMAST_PCITGT
- AR2315_PROCERR_HMAST_S
- AR2315_PROCERR_HMAST_WMAC
- AR2315_PROCERR_HSIZE
- AR2315_PROCERR_HSIZE_S
- AR2315_PROCERR_HTRANS
- AR2315_PROCERR_HTRANS_S
- AR2315_PROCERR_HWRITE
- AR2315_RELOAD
- AR2315_RESET
- AR2315_RESET_COLD_AHB
- AR2315_RESET_COLD_APB
- AR2315_RESET_COLD_CPU
- AR2315_RESET_COLD_CPUWARM
- AR2315_RESET_ENET0
- AR2315_RESET_EPHY0
- AR2315_RESET_I2C_RSVD
- AR2315_RESET_IR_RSVD
- AR2315_RESET_LOCAL
- AR2315_RESET_MEMCTL
- AR2315_RESET_MPEGTS_RSVD
- AR2315_RESET_PCIDMA
- AR2315_RESET_SPI
- AR2315_RESET_SYSTEM
- AR2315_RESET_UART0
- AR2315_RESET_WARM_WLAN0_BB
- AR2315_RESET_WARM_WLAN0_MAC
- AR2315_REV_CHIP
- AR2315_REV_MAJ
- AR2315_REV_MAJ_S
- AR2315_REV_MIN
- AR2315_REV_MIN_S
- AR2315_RST_BASE
- AR2315_RST_SIZE
- AR2315_SDRAMCTL_BASE
- AR2315_SDRAMCTL_SIZE
- AR2315_SPI_MMR_BASE
- AR2315_SPI_MMR_SIZE
- AR2315_SPI_READ_BASE
- AR2315_SPI_READ_SIZE
- AR2315_SREV
- AR2315_SYNCCLK
- AR2315_TIMER
- AR2315_UART0_BASE
- AR2315_WDT_CTRL
- AR2315_WDT_CTRL_IGNORE
- AR2315_WDT_CTRL_NMI
- AR2315_WDT_CTRL_RESET
- AR2315_WDT_TIMER
- AR2315_WLAN0_BASE
- AR2317_RESET_SYSTEM
- AR2427_DEVID_PCIE
- AR3
- AR5008_11NA_HT_DS_SHIFT
- AR5008_11NA_HT_SS_SHIFT
- AR5008_11NA_OFDM_SHIFT
- AR5008_11NG_HT_DS_SHIFT
- AR5008_11NG_HT_SS_SHIFT
- AR5008_11NG_OFDM_SHIFT
- AR5008_HT20_SHIFT
- AR5008_HT40_SHIFT
- AR5008_HT_DS_RATES
- AR5008_HT_SS_RATES
- AR5008_OFDM_RATES
- AR5312_AR2313_REV8
- AR5312_AR5312_REV2
- AR5312_AR5312_REV7
- AR5312_CLOCKCTL1
- AR5312_CLOCKCTL1_DOUBLER_MASK
- AR5312_CLOCKCTL1_MULTIPLIER_MASK
- AR5312_CLOCKCTL1_MULTIPLIER_SHIFT
- AR5312_CLOCKCTL1_PREDIVIDE_MASK
- AR5312_CLOCKCTL1_PREDIVIDE_SHIFT
- AR5312_DMA1
- AR5312_DMAADDR
- AR5312_ENABLE
- AR5312_ENABLE_ENET0
- AR5312_ENABLE_ENET1
- AR5312_ENABLE_UART_AND_WLAN1_PIO
- AR5312_ENABLE_WLAN0
- AR5312_ENABLE_WLAN1
- AR5312_ENABLE_WLAN1_DMA
- AR5312_ENET0_BASE
- AR5312_ENET1_BASE
- AR5312_FLASHCTL0
- AR5312_FLASHCTL1
- AR5312_FLASHCTL2
- AR5312_FLASHCTL_AC
- AR5312_FLASHCTL_AC_128K
- AR5312_FLASHCTL_AC_1M
- AR5312_FLASHCTL_AC_256K
- AR5312_FLASHCTL_AC_2M
- AR5312_FLASHCTL_AC_4M
- AR5312_FLASHCTL_AC_512K
- AR5312_FLASHCTL_AC_8M
- AR5312_FLASHCTL_AC_RES
- AR5312_FLASHCTL_AC_S
- AR5312_FLASHCTL_ATNR
- AR5312_FLASHCTL_ATR
- AR5312_FLASHCTL_ATR4
- AR5312_FLASHCTL_BASE
- AR5312_FLASHCTL_BM
- AR5312_FLASHCTL_BUSERR
- AR5312_FLASHCTL_E
- AR5312_FLASHCTL_IDCY
- AR5312_FLASHCTL_IDCY_S
- AR5312_FLASHCTL_MW
- AR5312_FLASHCTL_MW16
- AR5312_FLASHCTL_MW32
- AR5312_FLASHCTL_MW8
- AR5312_FLASHCTL_RBLE
- AR5312_FLASHCTL_SIZE
- AR5312_FLASHCTL_WP
- AR5312_FLASHCTL_WPERR
- AR5312_FLASHCTL_WST1
- AR5312_FLASHCTL_WST1_S
- AR5312_FLASHCTL_WST2
- AR5312_FLASHCTL_WST2_S
- AR5312_FLASH_BASE
- AR5312_FLASH_SIZE
- AR5312_GPIO_BASE
- AR5312_GPIO_SIZE
- AR5312_IMR
- AR5312_IRQ_ENET0
- AR5312_IRQ_ENET1
- AR5312_IRQ_MISC
- AR5312_IRQ_WLAN0
- AR5312_IRQ_WLAN1
- AR5312_ISR
- AR5312_ISR_AHBDMA
- AR5312_ISR_AHBPROC
- AR5312_ISR_GPIO
- AR5312_ISR_LOCAL
- AR5312_ISR_TIMER
- AR5312_ISR_UART0
- AR5312_ISR_UART0DMA
- AR5312_ISR_WD
- AR5312_MEM_CFG1
- AR5312_MEM_CFG1_AC0_M
- AR5312_MEM_CFG1_AC0_S
- AR5312_MEM_CFG1_AC1_M
- AR5312_MEM_CFG1_AC1_S
- AR5312_MISC_IRQ_AHB_DMA
- AR5312_MISC_IRQ_AHB_PROC
- AR5312_MISC_IRQ_COUNT
- AR5312_MISC_IRQ_GPIO
- AR5312_MISC_IRQ_LOCAL
- AR5312_MISC_IRQ_SPI
- AR5312_MISC_IRQ_TIMER
- AR5312_MISC_IRQ_UART0
- AR5312_MISC_IRQ_UART0_DMA
- AR5312_MISC_IRQ_WATCHDOG
- AR5312_PROC1
- AR5312_PROCADDR
- AR5312_RELOAD
- AR5312_RESET
- AR5312_RESET_APB
- AR5312_RESET_ENET0
- AR5312_RESET_ENET1
- AR5312_RESET_EPHY0
- AR5312_RESET_EPHY1
- AR5312_RESET_LOCAL_BUS
- AR5312_RESET_NMI
- AR5312_RESET_PROC
- AR5312_RESET_SYSTEM
- AR5312_RESET_UART0
- AR5312_RESET_WARM_PROC
- AR5312_RESET_WARM_WLAN0_BB
- AR5312_RESET_WARM_WLAN0_MAC
- AR5312_RESET_WARM_WLAN1_BB
- AR5312_RESET_WARM_WLAN1_MAC
- AR5312_RESET_WDOG
- AR5312_RESET_WLAN0
- AR5312_RESET_WLAN1
- AR5312_RESET_WMAC0_BITS
- AR5312_RESET_WMAC1_BITS
- AR5312_REV
- AR5312_REV_CHIP
- AR5312_REV_MAJ
- AR5312_REV_MAJ_AR2313
- AR5312_REV_MAJ_AR5312
- AR5312_REV_MAJ_S
- AR5312_REV_MIN
- AR5312_REV_MIN_DUAL
- AR5312_REV_MIN_S
- AR5312_REV_MIN_SINGLE
- AR5312_REV_WMAC_MAJ
- AR5312_REV_WMAC_MAJ_S
- AR5312_REV_WMAC_MIN
- AR5312_REV_WMAC_MIN_S
- AR5312_RST_BASE
- AR5312_RST_SIZE
- AR5312_SCRATCH
- AR5312_SDRAMCTL_BASE
- AR5312_SDRAMCTL_SIZE
- AR5312_TIMER
- AR5312_UART0_BASE
- AR5312_WDT_CTRL
- AR5312_WDT_CTRL_IGNORE
- AR5312_WDT_CTRL_NMI
- AR5312_WDT_CTRL_RESET
- AR5312_WDT_TIMER
- AR5312_WLAN0_BASE
- AR5312_WLAN1_BASE
- AR5416DESC
- AR5416DESC_CONST
- AR5416_AR9100_DEVID
- AR5416_BCHAN_UNUSED
- AR5416_DEVID_PCI
- AR5416_DEVID_PCIE
- AR5416_EEP4K_MAX_CHAINS
- AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
- AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
- AR5416_EEP4K_NUM_2G_CAL_PIERS
- AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
- AR5416_EEP4K_NUM_BAND_EDGES
- AR5416_EEP4K_NUM_CTLS
- AR5416_EEP4K_NUM_PD_GAINS
- AR5416_EEP4K_START_LOC
- AR5416_EEPMISC_BIG_ENDIAN
- AR5416_EEPROM_MAGIC
- AR5416_EEPROM_MAGIC_OFFSET
- AR5416_EEPROM_MAX
- AR5416_EEPROM_OFFSET
- AR5416_EEPROM_S
- AR5416_EEPROM_START_ADDR
- AR5416_EEP_MINOR_VER_16
- AR5416_EEP_MINOR_VER_17
- AR5416_EEP_MINOR_VER_19
- AR5416_EEP_MINOR_VER_2
- AR5416_EEP_MINOR_VER_20
- AR5416_EEP_MINOR_VER_21
- AR5416_EEP_MINOR_VER_22
- AR5416_EEP_MINOR_VER_3
- AR5416_EEP_MINOR_VER_7
- AR5416_EEP_MINOR_VER_9
- AR5416_EEP_NO_BACK_VER
- AR5416_EEP_RXGAIN_13DB_BACKOFF
- AR5416_EEP_RXGAIN_23DB_BACKOFF
- AR5416_EEP_RXGAIN_ORIG
- AR5416_EEP_TXGAIN_HIGH_POWER
- AR5416_EEP_TXGAIN_ORIGINAL
- AR5416_EEP_VER
- AR5416_EEP_VER_MAJOR_MASK
- AR5416_EEP_VER_MAJOR_SHIFT
- AR5416_EEP_VER_MINOR_MASK
- AR5416_MAGIC
- AR5416_MAX_CHAINS
- AR5416_MAX_NUM_TGT_PWRS
- AR5416_MAX_PWR_RANGE_IN_HALF_DB
- AR5416_MAX_RATE_POWER
- AR5416_MODAL_SPURS
- AR5416_NUM_2G_20_TARGET_POWERS
- AR5416_NUM_2G_40_TARGET_POWERS
- AR5416_NUM_2G_CAL_PIERS
- AR5416_NUM_2G_CCK_TARGET_POWERS
- AR5416_NUM_2G_CCK_TARGET_PWRS
- AR5416_NUM_2G_OFDM_TARGET_PWRS
- AR5416_NUM_5G_20_TARGET_POWERS
- AR5416_NUM_5G_40_TARGET_POWERS
- AR5416_NUM_5G_CAL_PIERS
- AR5416_NUM_5G_TARGET_PWRS
- AR5416_NUM_BAND_EDGES
- AR5416_NUM_CTLS
- AR5416_NUM_PDADC_VALUES
- AR5416_NUM_PD_GAINS
- AR5416_OPFLAGS_11A
- AR5416_OPFLAGS_11G
- AR5416_OPFLAGS_N_2G_HT20
- AR5416_OPFLAGS_N_2G_HT40
- AR5416_OPFLAGS_N_5G_HT20
- AR5416_OPFLAGS_N_5G_HT40
- AR5416_PD_GAINS_IN_MASK
- AR5416_PD_GAIN_ICEPTS
- AR5416_PWR_TABLE_OFFSET_DB
- AR5523_CMD_FLAG_MAGIC
- AR5523_CMD_FLAG_READ
- AR5523_CMD_ID
- AR5523_CMD_RX_PIPE
- AR5523_CMD_TIMEOUT
- AR5523_CMD_TX_PIPE
- AR5523_CONNECTED
- AR5523_DATA_ID
- AR5523_DATA_RX_PIPE
- AR5523_DATA_TIMEOUT
- AR5523_DATA_TX_PIPE
- AR5523_DEVICE_UG
- AR5523_DEVICE_UX
- AR5523_FIRMWARE_FILE
- AR5523_FLAG_ABG
- AR5523_FLAG_PRE_FIRMWARE
- AR5523_FLUSH_TIMEOUT
- AR5523_HW_UP
- AR5523_ID_BROADCAST
- AR5523_ID_BSS
- AR5523_MAX_FWBLOCK_SIZE
- AR5523_MAX_NRATES
- AR5523_MAX_RXCMDSZ
- AR5523_MAX_TXCMDSZ
- AR5523_MIN_RXBUFSZ
- AR5523_RX_DATA_COUNT
- AR5523_RX_DATA_REFILL_COUNT
- AR5523_SANE_RXBUFSZ
- AR5523_SUPPORTED_FILTERS
- AR5523_TX_DATA_COUNT
- AR5523_TX_DATA_RESTART_COUNT
- AR5523_TX_WD_TIMEOUT
- AR5523_USB_DISCONNECTED
- AR5523_WRITE_BLOCK
- AR5523_flags
- AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT
- AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210
- AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211
- AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S
- AR5K_2W_TX_DESC_CTL0_CLRDMASK
- AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID
- AR5K_2W_TX_DESC_CTL0_FRAME_LEN
- AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210
- AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S
- AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210
- AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S
- AR5K_2W_TX_DESC_CTL0_INTREQ
- AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210
- AR5K_2W_TX_DESC_CTL0_RTSENA
- AR5K_2W_TX_DESC_CTL0_VEOL_5211
- AR5K_2W_TX_DESC_CTL0_XMIT_RATE
- AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S
- AR5K_2W_TX_DESC_CTL1_BUF_LEN
- AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX
- AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210
- AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211
- AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S
- AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211
- AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S
- AR5K_2W_TX_DESC_CTL1_MORE
- AR5K_2W_TX_DESC_CTL1_NOACK_5211
- AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210
- AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT
- AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S
- AR5K_4W_TX_DESC_CTL0_CLRDMASK
- AR5K_4W_TX_DESC_CTL0_CTSENA
- AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID
- AR5K_4W_TX_DESC_CTL0_FRAME_LEN
- AR5K_4W_TX_DESC_CTL0_INTREQ
- AR5K_4W_TX_DESC_CTL0_RTSENA
- AR5K_4W_TX_DESC_CTL0_VEOL
- AR5K_4W_TX_DESC_CTL0_XMIT_POWER
- AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S
- AR5K_4W_TX_DESC_CTL1_BUF_LEN
- AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN
- AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S
- AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN
- AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S
- AR5K_4W_TX_DESC_CTL1_COMP_PROC
- AR5K_4W_TX_DESC_CTL1_COMP_PROC_S
- AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX
- AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S
- AR5K_4W_TX_DESC_CTL1_FRAME_TYPE
- AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S
- AR5K_4W_TX_DESC_CTL1_MORE
- AR5K_4W_TX_DESC_CTL1_NOACK
- AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN
- AR5K_4W_TX_DESC_CTL2_RTS_DURATION
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S
- AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE
- AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE0
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE1
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE2
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE3
- AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S
- AR5K_5210_RX_DESC_STATUS0_DATA_LEN
- AR5K_5210_RX_DESC_STATUS0_MORE
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL
- AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S
- AR5K_5210_RX_DESC_STATUS1_CRC_ERROR
- AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR
- AR5K_5210_RX_DESC_STATUS1_DONE
- AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210
- AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK
- AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS
- AR5K_5210_RX_DESC_STATUS1_KEY_INDEX
- AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S
- AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID
- AR5K_5210_RX_DESC_STATUS1_PHY_ERROR
- AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S
- AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP
- AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S
- AR5K_5212_RX_DESC_STATUS0_DATA_LEN
- AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR
- AR5K_5212_RX_DESC_STATUS0_MORE
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL
- AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S
- AR5K_5212_RX_DESC_STATUS1_CRC_ERROR
- AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR
- AR5K_5212_RX_DESC_STATUS1_DONE
- AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK
- AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS
- AR5K_5212_RX_DESC_STATUS1_KEY_INDEX
- AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S
- AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID
- AR5K_5212_RX_DESC_STATUS1_MIC_ERROR
- AR5K_5212_RX_DESC_STATUS1_PHY_ERROR
- AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE
- AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S
- AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP
- AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S
- AR5K_5414_CBCFG
- AR5K_5414_CBCFG_BUF_DIS
- AR5K_ACKSIFS
- AR5K_ACKSIFS_INC
- AR5K_ACK_FAIL
- AR5K_ACK_FAIL_5210
- AR5K_ACK_FAIL_5211
- AR5K_ADDAC_TEST
- AR5K_ADDAC_TEST_CAPTURE
- AR5K_ADDAC_TEST_LOOP_EN
- AR5K_ADDAC_TEST_LOOP_LEN
- AR5K_ADDAC_TEST_MSB
- AR5K_ADDAC_TEST_RXCONT
- AR5K_ADDAC_TEST_TRIG_PTY
- AR5K_ADDAC_TEST_TRIG_SEL
- AR5K_ADDAC_TEST_TST_ARM
- AR5K_ADDAC_TEST_TST_MODE
- AR5K_ADDAC_TEST_TXCONT
- AR5K_ADDAC_TEST_USE_U8
- AR5K_AGC_SETTLING
- AR5K_AGC_SETTLING_TURBO
- AR5K_ANTMODE_DEBUG
- AR5K_ANTMODE_DEFAULT
- AR5K_ANTMODE_FIXED_A
- AR5K_ANTMODE_FIXED_B
- AR5K_ANTMODE_MAX
- AR5K_ANTMODE_SECTOR_AP
- AR5K_ANTMODE_SECTOR_STA
- AR5K_ANTMODE_SINGLE_AP
- AR5K_ANT_CTL
- AR5K_ANT_MAX
- AR5K_ANT_SWTABLE_A
- AR5K_ANT_SWTABLE_B
- AR5K_AR2315_AHB_ARB_CTL
- AR5K_AR2315_AHB_ARB_CTL_WLAN
- AR5K_AR2315_BYTESWAP
- AR5K_AR2315_BYTESWAP_WMAC
- AR5K_AR2315_PCI_BASE
- AR5K_AR2315_RESET
- AR5K_AR2315_RESET_BB_WARM
- AR5K_AR2315_RESET_WMAC
- AR5K_AR5210
- AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM
- AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL
- AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY
- AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS
- AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL
- AR5K_AR5211
- AR5K_AR5211_TX_DESC_FRAME_TYPE_BEACON
- AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP
- AR5K_AR5212
- AR5K_AR5312_ENABLE
- AR5K_AR5312_ENABLE_WLAN0
- AR5K_AR5312_ENABLE_WLAN1
- AR5K_AR5312_RESET
- AR5K_AR5312_RESET_BB0_COLD
- AR5K_AR5312_RESET_BB0_WARM
- AR5K_AR5312_RESET_BB1_COLD
- AR5K_AR5312_RESET_BB1_WARM
- AR5K_AR5312_RESET_WMAC0
- AR5K_AR5312_RESET_WMAC1
- AR5K_ASSERT_ENTRY
- AR5K_BACKOFF
- AR5K_BACKOFF_CNT
- AR5K_BACKOFF_CW
- AR5K_BB_GAIN
- AR5K_BB_GAIN_BASE
- AR5K_BCR
- AR5K_BCR_ADHOC
- AR5K_BCR_AP
- AR5K_BCR_BCGET
- AR5K_BCR_BDMAE
- AR5K_BCR_TQ1FV
- AR5K_BCR_TQ1V
- AR5K_BEACON
- AR5K_BEACON_5210
- AR5K_BEACON_5211
- AR5K_BEACON_CNT
- AR5K_BEACON_CNT_5210
- AR5K_BEACON_CNT_5211
- AR5K_BEACON_ENA
- AR5K_BEACON_ENABLE
- AR5K_BEACON_PERIOD
- AR5K_BEACON_PERIOD_S
- AR5K_BEACON_RESET_TSF
- AR5K_BEACON_TIM
- AR5K_BEACON_TIM_S
- AR5K_BSR
- AR5K_BSR_ATIMDLY
- AR5K_BSR_BDLYDMA
- AR5K_BSR_BDLYSW
- AR5K_BSR_SNAPSHOTSVALID
- AR5K_BSR_SNPADHOC
- AR5K_BSR_SNPBDMAE
- AR5K_BSR_SNPTQ1FV
- AR5K_BSR_SNPTQ1V
- AR5K_BSR_SWBA_CNT
- AR5K_BSR_TXQ1F
- AR5K_BSS_ID0
- AR5K_BSS_ID1
- AR5K_BSS_ID1_AID
- AR5K_BSS_ID1_AID_S
- AR5K_BWMODE_10MHZ
- AR5K_BWMODE_40MHZ
- AR5K_BWMODE_5MHZ
- AR5K_BWMODE_DEFAULT
- AR5K_CALIBRATION_ANI
- AR5K_CALIBRATION_FULL
- AR5K_CALIBRATION_NF
- AR5K_CALIBRATION_SHORT
- AR5K_CCFG
- AR5K_CCFG_CCU
- AR5K_CCFG_CCU_CD_THRES
- AR5K_CCFG_CCU_CREDIT
- AR5K_CCFG_CCU_CUP_EN
- AR5K_CCFG_CCU_CUP_LCNT
- AR5K_CCFG_CCU_INIT
- AR5K_CCFG_CPC_EN
- AR5K_CCFG_WINDOW_SIZE
- AR5K_CCK_FIL_CNT
- AR5K_CFG
- AR5K_CFG_CLKGD
- AR5K_CFG_EEBS
- AR5K_CFG_IBSS
- AR5K_CFG_PCI_THRES
- AR5K_CFG_PCI_THRES_S
- AR5K_CFG_PHY_OK
- AR5K_CFG_SWRB
- AR5K_CFG_SWRD
- AR5K_CFG_SWRG
- AR5K_CFG_SWTB
- AR5K_CFG_SWTD
- AR5K_CFG_TXCNT
- AR5K_CFG_TXCNT_S
- AR5K_CFG_TXFSTAT
- AR5K_CFG_TXFSTRT
- AR5K_CFP_DUR
- AR5K_CFP_DUR_5210
- AR5K_CFP_DUR_5211
- AR5K_CFP_PERIOD
- AR5K_CFP_PERIOD_5210
- AR5K_CFP_PERIOD_5211
- AR5K_CLR_TMASK
- AR5K_CPC0
- AR5K_CPC1
- AR5K_CPC2
- AR5K_CPC3
- AR5K_CPCOVF
- AR5K_CR
- AR5K_CR_RXD
- AR5K_CR_RXE
- AR5K_CR_SWI
- AR5K_CR_TXD0
- AR5K_CR_TXD1
- AR5K_CR_TXE0
- AR5K_CR_TXE1
- AR5K_CTL_11A
- AR5K_CTL_11B
- AR5K_CTL_11G
- AR5K_CTL_2GHT20
- AR5K_CTL_2GHT40
- AR5K_CTL_5GHT20
- AR5K_CTL_5GHT40
- AR5K_CTL_MODE_M
- AR5K_CTL_TURBO
- AR5K_CTL_TURBOG
- AR5K_DB2RATE
- AR5K_DB2RATE_BASE
- AR5K_DCCFG
- AR5K_DCCFG_BCAST_EN
- AR5K_DCCFG_BYPASS_EN
- AR5K_DCCFG_GLOBAL_EN
- AR5K_DCCFG_MCAST_EN
- AR5K_DCM_ADDR
- AR5K_DCM_DATA
- AR5K_DCU_CHAN_TIME_BASE
- AR5K_DCU_CHAN_TIME_DUR
- AR5K_DCU_CHAN_TIME_DUR_S
- AR5K_DCU_CHAN_TIME_ENABLE
- AR5K_DCU_FP
- AR5K_DCU_FP_BURST_DCU_EN
- AR5K_DCU_FP_NOBURST_DCU_EN
- AR5K_DCU_FP_NOBURST_EN
- AR5K_DCU_GBL_IFS_EIFS
- AR5K_DCU_GBL_IFS_EIFS_M
- AR5K_DCU_GBL_IFS_MISC
- AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST
- AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY
- AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE
- AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS
- AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST
- AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC
- AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S
- AR5K_DCU_GBL_IFS_MISC_TURBO_MODE
- AR5K_DCU_GBL_IFS_MISC_USEC_DUR
- AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S
- AR5K_DCU_GBL_IFS_SIFS
- AR5K_DCU_GBL_IFS_SIFS_M
- AR5K_DCU_GBL_IFS_SLOT
- AR5K_DCU_GBL_IFS_SLOT_M
- AR5K_DCU_LCL_IFS_AIFS
- AR5K_DCU_LCL_IFS_AIFS_MAX
- AR5K_DCU_LCL_IFS_AIFS_S
- AR5K_DCU_LCL_IFS_BASE
- AR5K_DCU_LCL_IFS_CW_MAX
- AR5K_DCU_LCL_IFS_CW_MAX_S
- AR5K_DCU_LCL_IFS_CW_MIN
- AR5K_DCU_LCL_IFS_CW_MIN_S
- AR5K_DCU_MISC_ARBLOCK_CTL
- AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL
- AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM
- AR5K_DCU_MISC_ARBLOCK_CTL_NONE
- AR5K_DCU_MISC_ARBLOCK_CTL_S
- AR5K_DCU_MISC_ARBLOCK_IGNORE
- AR5K_DCU_MISC_BACKOFF
- AR5K_DCU_MISC_BACKOFF_FRAG
- AR5K_DCU_MISC_BACKOFF_PERSIST
- AR5K_DCU_MISC_BASE
- AR5K_DCU_MISC_BCN_ENABLE
- AR5K_DCU_MISC_BLOWN_IFS_POLICY
- AR5K_DCU_MISC_ETS_CW_POL
- AR5K_DCU_MISC_ETS_RTS_POL
- AR5K_DCU_MISC_FRAG_WAIT
- AR5K_DCU_MISC_FRMPRFTCH_ENABLE
- AR5K_DCU_MISC_HCFPOLL_ENABLE
- AR5K_DCU_MISC_POST_FR_BKOFF_DIS
- AR5K_DCU_MISC_SEQNUM_CTL
- AR5K_DCU_MISC_SEQ_NUM_INCR_DIS
- AR5K_DCU_MISC_VIRTCOL
- AR5K_DCU_MISC_VIRTCOL_IGNORE
- AR5K_DCU_MISC_VIRTCOL_NORMAL
- AR5K_DCU_MISC_VIRT_COLL_POLICY
- AR5K_DCU_QCUMASK_BASE
- AR5K_DCU_QCUMASK_M
- AR5K_DCU_RETRY_LMT_BASE
- AR5K_DCU_RETRY_LMT_RTS
- AR5K_DCU_RETRY_LMT_RTS_S
- AR5K_DCU_RETRY_LMT_STA_DATA
- AR5K_DCU_RETRY_LMT_STA_DATA_S
- AR5K_DCU_RETRY_LMT_STA_RTS
- AR5K_DCU_RETRY_LMT_STA_RTS_S
- AR5K_DCU_SEQNUM_BASE
- AR5K_DCU_SEQNUM_M
- AR5K_DCU_TXP
- AR5K_DCU_TXP_M
- AR5K_DCU_TXP_STATUS
- AR5K_DCU_TX_FILTER_0
- AR5K_DCU_TX_FILTER_0_BASE
- AR5K_DCU_TX_FILTER_1
- AR5K_DCU_TX_FILTER_1_BASE
- AR5K_DCU_TX_FILTER_CLR
- AR5K_DCU_TX_FILTER_SET
- AR5K_DEFAULT_ANTENNA
- AR5K_DESC_RX_CTL1_BUF_LEN
- AR5K_DESC_RX_CTL1_INTREQ
- AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES
- AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN
- AR5K_DESC_TX_STATUS0_FILTERED
- AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK
- AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT
- AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S
- AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP
- AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S
- AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT
- AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S
- AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211
- AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S
- AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH
- AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S
- AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212
- AR5K_DESC_TX_STATUS1_DONE
- AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212
- AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S
- AR5K_DESC_TX_STATUS1_SEQ_NUM
- AR5K_DESC_TX_STATUS1_SEQ_NUM_S
- AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212
- AR5K_DIAG_SW
- AR5K_DIAG_SW_5210
- AR5K_DIAG_SW_5211
- AR5K_DIAG_SW_CHANNEL_IDLE_HIGH
- AR5K_DIAG_SW_CHAN_INFO
- AR5K_DIAG_SW_CHAN_INFO_5210
- AR5K_DIAG_SW_CHAN_INFO_5211
- AR5K_DIAG_SW_CORR_FCS
- AR5K_DIAG_SW_CORR_FCS_5210
- AR5K_DIAG_SW_CORR_FCS_5211
- AR5K_DIAG_SW_DIS_ACK
- AR5K_DIAG_SW_DIS_CTS
- AR5K_DIAG_SW_DIS_DEC
- AR5K_DIAG_SW_DIS_ENC
- AR5K_DIAG_SW_DIS_RX
- AR5K_DIAG_SW_DIS_RX_5210
- AR5K_DIAG_SW_DIS_RX_5211
- AR5K_DIAG_SW_DIS_SEQ_INC_5210
- AR5K_DIAG_SW_DIS_TX_5210
- AR5K_DIAG_SW_DIS_WEP_ACK
- AR5K_DIAG_SW_ECO_ENABLE
- AR5K_DIAG_SW_EN_SCRAM_SEED
- AR5K_DIAG_SW_EN_SCRAM_SEED_5210
- AR5K_DIAG_SW_EN_SCRAM_SEED_5211
- AR5K_DIAG_SW_FRAME_NV0
- AR5K_DIAG_SW_FRAME_NV0_5210
- AR5K_DIAG_SW_FRAME_NV0_5211
- AR5K_DIAG_SW_IGNORE_CARR_SENSE
- AR5K_DIAG_SW_LOOP_BACK
- AR5K_DIAG_SW_LOOP_BACK_5210
- AR5K_DIAG_SW_LOOP_BACK_5211
- AR5K_DIAG_SW_OBSPT_M
- AR5K_DIAG_SW_OBSPT_S
- AR5K_DIAG_SW_PHEAR_ME
- AR5K_DIAG_SW_RX_CLEAR_HIGH
- AR5K_DIAG_SW_SCRAM_SEED_M
- AR5K_DIAG_SW_SCRAM_SEED_S
- AR5K_DIAG_SW_SCVRAM_SEED
- AR5K_DISABLE_QUEUE
- AR5K_DMASIZE_128B
- AR5K_DMASIZE_16B
- AR5K_DMASIZE_256B
- AR5K_DMASIZE_32B
- AR5K_DMASIZE_4B
- AR5K_DMASIZE_512B
- AR5K_DMASIZE_64B
- AR5K_DMASIZE_8B
- AR5K_EEPROM_5413_SPUR_CHAN_1
- AR5K_EEPROM_5413_SPUR_CHAN_2
- AR5K_EEPROM_AES_DIS
- AR5K_EEPROM_ANT_GAIN
- AR5K_EEPROM_ANT_GAIN_2GHZ
- AR5K_EEPROM_ANT_GAIN_5GHZ
- AR5K_EEPROM_ART_BUILD_NUM
- AR5K_EEPROM_BAND_2GHZ
- AR5K_EEPROM_BAND_5GHZ
- AR5K_EEPROM_BASE
- AR5K_EEPROM_BURST_DIS
- AR5K_EEPROM_CAL_DATA_START
- AR5K_EEPROM_CCK_OFDM_DELTA
- AR5K_EEPROM_CFG
- AR5K_EEPROM_CFG_CLK_RATE
- AR5K_EEPROM_CFG_CLK_RATE_156KHZ
- AR5K_EEPROM_CFG_CLK_RATE_312KHZ
- AR5K_EEPROM_CFG_CLK_RATE_625KHZ
- AR5K_EEPROM_CFG_CLK_RATE_S
- AR5K_EEPROM_CFG_LIND_EN
- AR5K_EEPROM_CFG_PROT_KEY
- AR5K_EEPROM_CFG_PROT_KEY_S
- AR5K_EEPROM_CFG_SIZE
- AR5K_EEPROM_CFG_SIZE_16KBIT
- AR5K_EEPROM_CFG_SIZE_4KBIT
- AR5K_EEPROM_CFG_SIZE_8KBIT
- AR5K_EEPROM_CFG_SIZE_AUTO
- AR5K_EEPROM_CFG_WR_WAIT_DIS
- AR5K_EEPROM_CHANNEL_DIS
- AR5K_EEPROM_CHANNEL_POWER
- AR5K_EEPROM_CHECKSUM
- AR5K_EEPROM_CMD
- AR5K_EEPROM_CMD_READ
- AR5K_EEPROM_CMD_RESET
- AR5K_EEPROM_CMD_WRITE
- AR5K_EEPROM_COMP_DIS
- AR5K_EEPROM_CTL
- AR5K_EEPROM_DATA
- AR5K_EEPROM_DATA_5210
- AR5K_EEPROM_DATA_5211
- AR5K_EEPROM_EARSTART
- AR5K_EEPROM_EAR_FILE_ID
- AR5K_EEPROM_EAR_FILE_VERSION
- AR5K_EEPROM_EEMAP
- AR5K_EEPROM_EEP_DELTA
- AR5K_EEPROM_EEP_FILE_VERSION
- AR5K_EEPROM_EEP_SCALE
- AR5K_EEPROM_FCC_MID_EN
- AR5K_EEPROM_FF_DIS
- AR5K_EEPROM_FREQ_M
- AR5K_EEPROM_GROUP1_OFFSET
- AR5K_EEPROM_GROUP2_OFFSET
- AR5K_EEPROM_GROUP3_OFFSET
- AR5K_EEPROM_GROUP4_OFFSET
- AR5K_EEPROM_GROUP5_OFFSET
- AR5K_EEPROM_GROUP6_OFFSET
- AR5K_EEPROM_GROUP7_OFFSET
- AR5K_EEPROM_GROUP8_OFFSET
- AR5K_EEPROM_GROUPS_START
- AR5K_EEPROM_HAS32KHZCRYSTAL
- AR5K_EEPROM_HAS32KHZCRYSTAL_OLD
- AR5K_EEPROM_HDR
- AR5K_EEPROM_HDR_11A
- AR5K_EEPROM_HDR_11B
- AR5K_EEPROM_HDR_11G
- AR5K_EEPROM_HDR_DEVICE
- AR5K_EEPROM_HDR_RFKILL
- AR5K_EEPROM_HDR_T_2GHZ_DIS
- AR5K_EEPROM_HDR_T_5GHZ_DBM
- AR5K_EEPROM_HDR_T_5GHZ_DIS
- AR5K_EEPROM_HDR_XR2_DIS
- AR5K_EEPROM_HDR_XR5_DIS
- AR5K_EEPROM_HEAVY_CLIP_EN
- AR5K_EEPROM_INFO
- AR5K_EEPROM_INFO_BASE
- AR5K_EEPROM_INFO_CKSUM
- AR5K_EEPROM_INFO_MAX
- AR5K_EEPROM_IS_HB63
- AR5K_EEPROM_I_GAIN
- AR5K_EEPROM_JAP_11A_NEW_EN
- AR5K_EEPROM_JAP_MID_EN
- AR5K_EEPROM_JAP_U1EVEN_EN
- AR5K_EEPROM_JAP_U1ODD_EN
- AR5K_EEPROM_JAP_U2_EN
- AR5K_EEPROM_KEY_CACHE_SIZE
- AR5K_EEPROM_MAGIC
- AR5K_EEPROM_MAGIC_VALUE
- AR5K_EEPROM_MASK_R0
- AR5K_EEPROM_MASK_R1
- AR5K_EEPROM_MAX_CHAN
- AR5K_EEPROM_MAX_CTLS
- AR5K_EEPROM_MAX_QCU
- AR5K_EEPROM_MISC0
- AR5K_EEPROM_MISC1
- AR5K_EEPROM_MISC2
- AR5K_EEPROM_MISC3
- AR5K_EEPROM_MISC4
- AR5K_EEPROM_MISC5
- AR5K_EEPROM_MISC6
- AR5K_EEPROM_MODES_11A
- AR5K_EEPROM_MODES_11B
- AR5K_EEPROM_MODES_11G
- AR5K_EEPROM_MODE_11A
- AR5K_EEPROM_MODE_11B
- AR5K_EEPROM_MODE_11G
- AR5K_EEPROM_NON_EDGE_M
- AR5K_EEPROM_NO_SPUR
- AR5K_EEPROM_N_2GHZ_CHAN
- AR5K_EEPROM_N_2GHZ_CHAN_2413
- AR5K_EEPROM_N_2GHZ_CHAN_MAX
- AR5K_EEPROM_N_5GHZ_CHAN
- AR5K_EEPROM_N_5GHZ_RATE_CHAN
- AR5K_EEPROM_N_CTLS
- AR5K_EEPROM_N_EDGES
- AR5K_EEPROM_N_FREQ_BANDS
- AR5K_EEPROM_N_INTERCEPTS
- AR5K_EEPROM_N_INTERCEPT_10_2GHZ
- AR5K_EEPROM_N_INTERCEPT_10_5GHZ
- AR5K_EEPROM_N_IQ_CAL
- AR5K_EEPROM_N_MODES
- AR5K_EEPROM_N_OBDB
- AR5K_EEPROM_N_PCDAC
- AR5K_EEPROM_N_PD_CURVES
- AR5K_EEPROM_N_PD_GAINS
- AR5K_EEPROM_N_PD_POINTS
- AR5K_EEPROM_N_PHASE_CAL
- AR5K_EEPROM_N_POWER_LOC_11B
- AR5K_EEPROM_N_POWER_LOC_11G
- AR5K_EEPROM_N_PWR_POINTS_5111
- AR5K_EEPROM_N_SPUR_CHANS
- AR5K_EEPROM_N_TEST_FREQ
- AR5K_EEPROM_N_XPD0_POINTS
- AR5K_EEPROM_N_XPD3_POINTS
- AR5K_EEPROM_OBDB0_2GHZ
- AR5K_EEPROM_OBDB1_2GHZ
- AR5K_EEPROM_OBDB_DIS
- AR5K_EEPROM_OFF
- AR5K_EEPROM_PCDAC_M
- AR5K_EEPROM_PCDAC_START
- AR5K_EEPROM_PCDAC_STEP
- AR5K_EEPROM_PCDAC_STOP
- AR5K_EEPROM_PCIE_OFFSET
- AR5K_EEPROM_PCIE_SERDES_SECTION
- AR5K_EEPROM_POWER_M
- AR5K_EEPROM_POWER_MAX
- AR5K_EEPROM_POWER_MIN
- AR5K_EEPROM_POWER_STEP
- AR5K_EEPROM_POWER_TABLE_SIZE
- AR5K_EEPROM_PROTECT
- AR5K_EEPROM_PROTECT_RD_0_31
- AR5K_EEPROM_PROTECT_RD_128_191
- AR5K_EEPROM_PROTECT_RD_192_207
- AR5K_EEPROM_PROTECT_RD_208_223
- AR5K_EEPROM_PROTECT_RD_224_239
- AR5K_EEPROM_PROTECT_RD_240_255
- AR5K_EEPROM_PROTECT_RD_32_63
- AR5K_EEPROM_PROTECT_RD_64_127
- AR5K_EEPROM_PROTECT_WR_0_31
- AR5K_EEPROM_PROTECT_WR_128_191
- AR5K_EEPROM_PROTECT_WR_192_207
- AR5K_EEPROM_PROTECT_WR_208_223
- AR5K_EEPROM_PROTECT_WR_224_239
- AR5K_EEPROM_PROTECT_WR_240_255
- AR5K_EEPROM_PROTECT_WR_32_63
- AR5K_EEPROM_PROTECT_WR_64_127
- AR5K_EEPROM_READ
- AR5K_EEPROM_READ_HDR
- AR5K_EEPROM_REG_DOMAIN
- AR5K_EEPROM_RFKILL
- AR5K_EEPROM_RFKILL_GPIO_SEL
- AR5K_EEPROM_RFKILL_GPIO_SEL_S
- AR5K_EEPROM_RFKILL_POLARITY
- AR5K_EEPROM_RFKILL_POLARITY_S
- AR5K_EEPROM_RX_CHAIN_DIS
- AR5K_EEPROM_SCALE_OC_DELTA
- AR5K_EEPROM_SIZE_ENDLOC_SHIFT
- AR5K_EEPROM_SIZE_LOWER
- AR5K_EEPROM_SIZE_UPPER
- AR5K_EEPROM_SIZE_UPPER_MASK
- AR5K_EEPROM_SIZE_UPPER_SHIFT
- AR5K_EEPROM_SPUR_CHAN_MASK
- AR5K_EEPROM_STATUS
- AR5K_EEPROM_STAT_5210
- AR5K_EEPROM_STAT_5211
- AR5K_EEPROM_STAT_RDDONE
- AR5K_EEPROM_STAT_RDERR
- AR5K_EEPROM_STAT_WRDONE
- AR5K_EEPROM_STAT_WRERR
- AR5K_EEPROM_TARGET_PWRSTART
- AR5K_EEPROM_TARGET_PWR_OFF_11A
- AR5K_EEPROM_TARGET_PWR_OFF_11B
- AR5K_EEPROM_TARGET_PWR_OFF_11G
- AR5K_EEPROM_TX_CHAIN_DIS
- AR5K_EEPROM_VERSION
- AR5K_EEPROM_VERSION_3_0
- AR5K_EEPROM_VERSION_3_1
- AR5K_EEPROM_VERSION_3_2
- AR5K_EEPROM_VERSION_3_3
- AR5K_EEPROM_VERSION_3_4
- AR5K_EEPROM_VERSION_4_0
- AR5K_EEPROM_VERSION_4_1
- AR5K_EEPROM_VERSION_4_2
- AR5K_EEPROM_VERSION_4_3
- AR5K_EEPROM_VERSION_4_4
- AR5K_EEPROM_VERSION_4_5
- AR5K_EEPROM_VERSION_4_6
- AR5K_EEPROM_VERSION_4_7
- AR5K_EEPROM_VERSION_4_9
- AR5K_EEPROM_VERSION_5_0
- AR5K_EEPROM_VERSION_5_1
- AR5K_EEPROM_VERSION_5_3
- AR5K_ENABLE_QUEUE
- AR5K_FCS_FAIL
- AR5K_FCS_FAIL_5210
- AR5K_FCS_FAIL_5211
- AR5K_FRAME_CTL_QOSM
- AR5K_GAIN_CCK_OFDM_GAIN_DELTA
- AR5K_GAIN_CCK_PROBE_CORR
- AR5K_GAIN_CHECK_ADJUST
- AR5K_GAIN_CRN_FIX_BITS_5111
- AR5K_GAIN_CRN_FIX_BITS_5112
- AR5K_GAIN_CRN_MAX_FIX_BITS
- AR5K_GAIN_DYN_ADJUST_HI_MARGIN
- AR5K_GAIN_DYN_ADJUST_LO_MARGIN
- AR5K_GAIN_STEP_COUNT
- AR5K_GPIOCR
- AR5K_GPIOCR_IN
- AR5K_GPIOCR_INT_ENA
- AR5K_GPIOCR_INT_SEL
- AR5K_GPIOCR_INT_SELH
- AR5K_GPIOCR_INT_SELL
- AR5K_GPIOCR_OUT
- AR5K_GPIOCR_OUT0
- AR5K_GPIOCR_OUT1
- AR5K_GPIODI
- AR5K_GPIODI_M
- AR5K_GPIODO
- AR5K_IER
- AR5K_IER_DISABLE
- AR5K_IER_ENABLE
- AR5K_IFS0
- AR5K_IFS0_DIFS
- AR5K_IFS0_DIFS_S
- AR5K_IFS0_SIFS
- AR5K_IFS0_SIFS_S
- AR5K_IFS1
- AR5K_IFS1_CS_EN
- AR5K_IFS1_CS_EN_S
- AR5K_IFS1_EIFS
- AR5K_IFS1_EIFS_S
- AR5K_IFS1_PIFS
- AR5K_IFS1_PIFS_S
- AR5K_IMR
- AR5K_IMR_BCNMISC
- AR5K_IMR_BMISS
- AR5K_IMR_BNR
- AR5K_IMR_BRSSI
- AR5K_IMR_DPERR
- AR5K_IMR_GPIO
- AR5K_IMR_HIUERR
- AR5K_IMR_MCABT
- AR5K_IMR_MIB
- AR5K_IMR_QCBRORN
- AR5K_IMR_QCBRURN
- AR5K_IMR_QTRIG
- AR5K_IMR_RXCHIRP
- AR5K_IMR_RXDESC
- AR5K_IMR_RXDOPPLER
- AR5K_IMR_RXEOL
- AR5K_IMR_RXERR
- AR5K_IMR_RXKCM
- AR5K_IMR_RXNOFRM
- AR5K_IMR_RXOK
- AR5K_IMR_RXORN
- AR5K_IMR_RXPHY
- AR5K_IMR_SSERR
- AR5K_IMR_SWBA
- AR5K_IMR_SWI
- AR5K_IMR_TIM
- AR5K_IMR_TXDESC
- AR5K_IMR_TXEOL
- AR5K_IMR_TXERR
- AR5K_IMR_TXNOFRM
- AR5K_IMR_TXOK
- AR5K_IMR_TXURN
- AR5K_INIT_CARR_SENSE_EN
- AR5K_INIT_CFG
- AR5K_INIT_CYCRSSI_THR1
- AR5K_INIT_OFDM_PLCP_BITS
- AR5K_INIT_OFDM_PREAMBLE_TIME_MIN
- AR5K_INIT_OFDM_PREAMPLE_TIME
- AR5K_INIT_OFDM_SYMBOL_TIME
- AR5K_INIT_RETRY_LONG
- AR5K_INIT_RETRY_SHORT
- AR5K_INIT_RX_LATENCY_5210
- AR5K_INIT_RX_LAT_MAX
- AR5K_INIT_SIFS_DEFAULT_A
- AR5K_INIT_SIFS_DEFAULT_BG
- AR5K_INIT_SIFS_HALF_RATE
- AR5K_INIT_SIFS_QUARTER_RATE
- AR5K_INIT_SIFS_TURBO
- AR5K_INIT_SLOT_TIME_B
- AR5K_INIT_SLOT_TIME_DEFAULT
- AR5K_INIT_SLOT_TIME_HALF_RATE
- AR5K_INIT_SLOT_TIME_QUARTER_RATE
- AR5K_INIT_SLOT_TIME_TURBO
- AR5K_INIT_TXF2TXD_START_DEFAULT
- AR5K_INIT_TXF2TXD_START_DELAY_10MHZ
- AR5K_INIT_TXF2TXD_START_DELAY_5MHZ
- AR5K_INIT_TX_LATENCY_5210
- AR5K_INIT_TX_LAT_A
- AR5K_INIT_TX_LAT_BG
- AR5K_INIT_TX_LAT_MIN
- AR5K_INI_READ
- AR5K_INI_WRITE
- AR5K_INTPEND
- AR5K_INTPEND_M
- AR5K_INT_BCN_TIMEOUT
- AR5K_INT_BMISS
- AR5K_INT_BNR
- AR5K_INT_BRSSI
- AR5K_INT_CAB_TIMEOUT
- AR5K_INT_COMMON
- AR5K_INT_DTIM
- AR5K_INT_DTIM_SYNC
- AR5K_INT_FATAL
- AR5K_INT_GLOBAL
- AR5K_INT_GPIO
- AR5K_INT_MIB
- AR5K_INT_NOCARD
- AR5K_INT_QCBRORN
- AR5K_INT_QCBRURN
- AR5K_INT_QTRIG
- AR5K_INT_RXDESC
- AR5K_INT_RXEOL
- AR5K_INT_RXERR
- AR5K_INT_RXKCM
- AR5K_INT_RXNOFRM
- AR5K_INT_RXOK
- AR5K_INT_RXORN
- AR5K_INT_RXPHY
- AR5K_INT_RX_ALL
- AR5K_INT_SWBA
- AR5K_INT_SWI
- AR5K_INT_TIM
- AR5K_INT_TXDESC
- AR5K_INT_TXEOL
- AR5K_INT_TXERR
- AR5K_INT_TXNOFRM
- AR5K_INT_TXOK
- AR5K_INT_TXURN
- AR5K_INT_TX_ALL
- AR5K_ISR
- AR5K_ISR_BCNMISC
- AR5K_ISR_BITS_FROM_SISRS
- AR5K_ISR_BMISS
- AR5K_ISR_BNR
- AR5K_ISR_BRSSI
- AR5K_ISR_DPERR
- AR5K_ISR_GPIO
- AR5K_ISR_HIUERR
- AR5K_ISR_MCABT
- AR5K_ISR_MIB
- AR5K_ISR_QCBRORN
- AR5K_ISR_QCBRURN
- AR5K_ISR_QTRIG
- AR5K_ISR_RXCHIRP
- AR5K_ISR_RXDESC
- AR5K_ISR_RXDOPPLER
- AR5K_ISR_RXEOL
- AR5K_ISR_RXERR
- AR5K_ISR_RXKCM
- AR5K_ISR_RXNOFRM
- AR5K_ISR_RXOK
- AR5K_ISR_RXORN
- AR5K_ISR_RXPHY
- AR5K_ISR_SSERR
- AR5K_ISR_SWBA
- AR5K_ISR_SWI
- AR5K_ISR_TIM
- AR5K_ISR_TXDESC
- AR5K_ISR_TXEOL
- AR5K_ISR_TXERR
- AR5K_ISR_TXNOFRM
- AR5K_ISR_TXOK
- AR5K_ISR_TXURN
- AR5K_KEYCACHE_SIZE
- AR5K_KEYTABLE_SIZE_5210
- AR5K_KEYTABLE_SIZE_5211
- AR5K_LAST_TSTP
- AR5K_LED_ASSOC
- AR5K_LED_AUTH
- AR5K_LED_INIT
- AR5K_LED_RUN
- AR5K_LED_SCAN
- AR5K_MAX_GPIO
- AR5K_MAX_RATES
- AR5K_MAX_RF_BANKS
- AR5K_MCAST_FILTER0
- AR5K_MCAST_FILTER0_5210
- AR5K_MCAST_FILTER0_5211
- AR5K_MCAST_FILTER1
- AR5K_MCAST_FILTER1_5210
- AR5K_MCAST_FILTER1_5211
- AR5K_MIBC
- AR5K_MIBC_CMC
- AR5K_MIBC_COW
- AR5K_MIBC_FMC
- AR5K_MIBC_MCS
- AR5K_MIC_QOS_CTL
- AR5K_MIC_QOS_CTL_MQ_EN
- AR5K_MIC_QOS_CTL_OFF
- AR5K_MIC_QOS_SEL
- AR5K_MIC_QOS_SEL_OFF
- AR5K_MISC
- AR5K_MISC_DMA_OBS_M
- AR5K_MISC_DMA_OBS_S
- AR5K_MISC_LED_BLINK
- AR5K_MISC_LED_DECAY
- AR5K_MISC_MAC_OBS_LSB_M
- AR5K_MISC_MAC_OBS_LSB_S
- AR5K_MISC_MAC_OBS_MSB_M
- AR5K_MISC_MAC_OBS_MSB_S
- AR5K_MISC_MISC_OBS_M
- AR5K_MISC_MISC_OBS_S
- AR5K_MISC_MODE
- AR5K_MISC_MODE_ACKSIFS_MEM
- AR5K_MISC_MODE_COMBINED_MIC
- AR5K_MISC_MODE_FBSSID_MATCH
- AR5K_MODE_11A
- AR5K_MODE_11B
- AR5K_MODE_11G
- AR5K_MODE_MAX
- AR5K_NAV
- AR5K_NAV_5210
- AR5K_NAV_5211
- AR5K_NODCU_RETRY_LMT
- AR5K_NODCU_RETRY_LMT_CW_MIN
- AR5K_NODCU_RETRY_LMT_CW_MIN_S
- AR5K_NODCU_RETRY_LMT_LG_RETRY
- AR5K_NODCU_RETRY_LMT_LG_RETRY_S
- AR5K_NODCU_RETRY_LMT_SH_RETRY
- AR5K_NODCU_RETRY_LMT_SH_RETRY_S
- AR5K_NODCU_RETRY_LMT_SLG_RETRY
- AR5K_NODCU_RETRY_LMT_SLG_RETRY_S
- AR5K_NODCU_RETRY_LMT_SSH_RETRY
- AR5K_NODCU_RETRY_LMT_SSH_RETRY_S
- AR5K_NOQCU_TXDP0
- AR5K_NOQCU_TXDP1
- AR5K_NUM_GPIO
- AR5K_NUM_TX_QUEUES
- AR5K_NUM_TX_QUEUES_NOQCU
- AR5K_OFDM_FIL_CNT
- AR5K_PCICFG
- AR5K_PCICFG_BUS_SEL
- AR5K_PCICFG_CBEFIX_DIS
- AR5K_PCICFG_CLKRUNEN
- AR5K_PCICFG_EEAE
- AR5K_PCICFG_EESIZE
- AR5K_PCICFG_EESIZE_16K
- AR5K_PCICFG_EESIZE_4K
- AR5K_PCICFG_EESIZE_8K
- AR5K_PCICFG_EESIZE_FAIL
- AR5K_PCICFG_EESIZE_S
- AR5K_PCICFG_LED
- AR5K_PCICFG_LEDBLINK
- AR5K_PCICFG_LEDBLINK_S
- AR5K_PCICFG_LEDMODE
- AR5K_PCICFG_LEDMODE_PROM
- AR5K_PCICFG_LEDMODE_PROP
- AR5K_PCICFG_LEDMODE_PWR
- AR5K_PCICFG_LEDMODE_RAND
- AR5K_PCICFG_LEDSLOW
- AR5K_PCICFG_LEDSTATE
- AR5K_PCICFG_LED_ASSOC
- AR5K_PCICFG_LED_BCTL
- AR5K_PCICFG_LED_NONE
- AR5K_PCICFG_LED_PEND
- AR5K_PCICFG_RETRY_FIX
- AR5K_PCICFG_SLEEP_CLOCK_EN
- AR5K_PCICFG_SLEEP_CLOCK_RATE
- AR5K_PCICFG_SLEEP_CLOCK_RATE_S
- AR5K_PCICFG_SL_INPEN
- AR5K_PCICFG_SL_INTEN
- AR5K_PCICFG_SPWR_DN
- AR5K_PCIE_PM_CTL
- AR5K_PCIE_PM_CTL_AUX_PWR_DET
- AR5K_PCIE_PM_CTL_L0_L0S_CLEAR
- AR5K_PCIE_PM_CTL_L0_L0S_EN
- AR5K_PCIE_PM_CTL_L1_WHEN_D2
- AR5K_PCIE_PM_CTL_LDRESET_EN
- AR5K_PCIE_PM_CTL_PME_CLEAR
- AR5K_PCIE_PM_CTL_PME_EN
- AR5K_PCIE_PM_CTL_PSM_D0
- AR5K_PCIE_PM_CTL_PSM_D1
- AR5K_PCIE_PM_CTL_PSM_D2
- AR5K_PCIE_PM_CTL_PSM_D3
- AR5K_PCIE_SERDES
- AR5K_PCIE_SERDES_RESET
- AR5K_PCIE_WAEN
- AR5K_PCU_MAX
- AR5K_PCU_MIN
- AR5K_PHY
- AR5K_PHYERR_CNT1
- AR5K_PHYERR_CNT1_MASK
- AR5K_PHYERR_CNT2
- AR5K_PHYERR_CNT2_MASK
- AR5K_PHY_ACT
- AR5K_PHY_ACT_DISABLE
- AR5K_PHY_ACT_ENABLE
- AR5K_PHY_ADCSAT
- AR5K_PHY_ADCSAT_ICNT
- AR5K_PHY_ADCSAT_ICNT_S
- AR5K_PHY_ADCSAT_THR
- AR5K_PHY_ADCSAT_THR_S
- AR5K_PHY_ADC_CTL
- AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
- AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S
- AR5K_PHY_ADC_CTL_INBUFGAIN_ON
- AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S
- AR5K_PHY_ADC_CTL_PWD_ADC_OFF
- AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF
- AR5K_PHY_ADC_CTL_PWD_DAC_OFF
- AR5K_PHY_ADC_TEST
- AR5K_PHY_ADC_TEST_I
- AR5K_PHY_ADC_TEST_Q
- AR5K_PHY_AGC
- AR5K_PHY_AGCCOARSE
- AR5K_PHY_AGCCOARSE_HI
- AR5K_PHY_AGCCOARSE_HI_S
- AR5K_PHY_AGCCOARSE_LO
- AR5K_PHY_AGCCOARSE_LO_S
- AR5K_PHY_AGCCTL
- AR5K_PHY_AGCCTL_CAL
- AR5K_PHY_AGCCTL_NF
- AR5K_PHY_AGCCTL_NF_EN
- AR5K_PHY_AGCCTL_NF_NOUPDATE
- AR5K_PHY_AGCCTL_OFDM_DIV_DIS
- AR5K_PHY_AGCTL_FLTR_CAL
- AR5K_PHY_AGC_DISABLE
- AR5K_PHY_ANT_CTL
- AR5K_PHY_ANT_CTL_HITUNE5
- AR5K_PHY_ANT_CTL_SECTORED_ANT
- AR5K_PHY_ANT_CTL_SWTABLE_IDLE
- AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S
- AR5K_PHY_ANT_CTL_TXRX_EN
- AR5K_PHY_ANT_SWITCH_TABLE_0
- AR5K_PHY_ANT_SWITCH_TABLE_1
- AR5K_PHY_BAD_TX_RATE
- AR5K_PHY_BASE
- AR5K_PHY_BIN_MASK2_1
- AR5K_PHY_BIN_MASK2_2
- AR5K_PHY_BIN_MASK2_3
- AR5K_PHY_BIN_MASK2_4
- AR5K_PHY_BIN_MASK2_4_MASK_4
- AR5K_PHY_BIN_MASK2_4_MASK_4_S
- AR5K_PHY_BIN_MASK_1
- AR5K_PHY_BIN_MASK_2
- AR5K_PHY_BIN_MASK_3
- AR5K_PHY_BIN_MASK_CTL
- AR5K_PHY_BIN_MASK_CTL_MASK_4
- AR5K_PHY_BIN_MASK_CTL_MASK_4_S
- AR5K_PHY_BIN_MASK_CTL_RATE
- AR5K_PHY_BIN_MASK_CTL_RATE_S
- AR5K_PHY_BLUETOOTH
- AR5K_PHY_CCKTXCTK_DAC_SCALE
- AR5K_PHY_CCKTXCTL
- AR5K_PHY_CCKTXCTL_JAPAN
- AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS
- AR5K_PHY_CCKTXCTL_WORLD
- AR5K_PHY_CCK_CROSSCORR
- AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR
- AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S
- AR5K_PHY_CCK_RX_CTL_4
- AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT
- AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S
- AR5K_PHY_CHAN_STATUS
- AR5K_PHY_CHAN_STATUS_BT_ACT
- AR5K_PHY_CHAN_STATUS_RX_CLR_MAC
- AR5K_PHY_CHAN_STATUS_RX_CLR_PAP
- AR5K_PHY_CHAN_STATUS_RX_CLR_RAW
- AR5K_PHY_CHIP_ID
- AR5K_PHY_CTL
- AR5K_PHY_CTL_GEN_SCRAMBLER
- AR5K_PHY_CTL_LATE_TX_SIG_SYM
- AR5K_PHY_CTL_LOW_FREQ_SLE_EN
- AR5K_PHY_CTL_RX_ANT_SEL
- AR5K_PHY_CTL_RX_ANT_STATIC
- AR5K_PHY_CTL_RX_DRAIN_RATE
- AR5K_PHY_CTL_TX_ANT_SEL
- AR5K_PHY_CTL_TX_ANT_STATIC
- AR5K_PHY_CURRENT_RSSI
- AR5K_PHY_DAC_TEST
- AR5K_PHY_DAC_TEST_I
- AR5K_PHY_DAC_TEST_Q
- AR5K_PHY_DAG_CCK_CTL
- AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR
- AR5K_PHY_DAG_CCK_CTL_RSSI_THR
- AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S
- AR5K_PHY_DESIRED_SIZE
- AR5K_PHY_DESIRED_SIZE_ADC
- AR5K_PHY_DESIRED_SIZE_ADC_S
- AR5K_PHY_DESIRED_SIZE_PGA
- AR5K_PHY_DESIRED_SIZE_PGA_S
- AR5K_PHY_DESIRED_SIZE_TOT
- AR5K_PHY_DESIRED_SIZE_TOT_S
- AR5K_PHY_ERR_FIL
- AR5K_PHY_ERR_FIL_CCK
- AR5K_PHY_ERR_FIL_OFDM
- AR5K_PHY_ERR_FIL_RADAR
- AR5K_PHY_FAST_ADC
- AR5K_PHY_FAST_ANT_DIV
- AR5K_PHY_FAST_ANT_DIV_EN
- AR5K_PHY_FRAME_CTL
- AR5K_PHY_FRAME_CTL_5210
- AR5K_PHY_FRAME_CTL_5211
- AR5K_PHY_FRAME_CTL_EMU
- AR5K_PHY_FRAME_CTL_EMU_S
- AR5K_PHY_FRAME_CTL_ILLLEN_ERR
- AR5K_PHY_FRAME_CTL_ILLRATE_ERR
- AR5K_PHY_FRAME_CTL_INI
- AR5K_PHY_FRAME_CTL_PARITY_ERR
- AR5K_PHY_FRAME_CTL_PREP_CHINFO
- AR5K_PHY_FRAME_CTL_SERVICE_ERR
- AR5K_PHY_FRAME_CTL_TIMING_ERR
- AR5K_PHY_FRAME_CTL_TXURN_ERR
- AR5K_PHY_FRAME_CTL_TX_CLIP
- AR5K_PHY_FRAME_CTL_TX_CLIP_S
- AR5K_PHY_FRAME_CTL_WIN_LEN
- AR5K_PHY_FRAME_CTL_WIN_LEN_S
- AR5K_PHY_GAIN
- AR5K_PHY_GAIN_2GHZ
- AR5K_PHY_GAIN_2GHZ_INI_5111
- AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
- AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S
- AR5K_PHY_GAIN_OFFSET
- AR5K_PHY_GAIN_OFFSET_RXTX_FLAG
- AR5K_PHY_GAIN_TXRX_ATTEN
- AR5K_PHY_GAIN_TXRX_ATTEN_S
- AR5K_PHY_GAIN_TXRX_RF_MAX
- AR5K_PHY_GAIN_TXRX_RF_MAX_S
- AR5K_PHY_HEAVY_CLIP_ENABLE
- AR5K_PHY_IQ
- AR5K_PHY_IQRES_CAL_CORR
- AR5K_PHY_IQRES_CAL_PWR_I
- AR5K_PHY_IQRES_CAL_PWR_Q
- AR5K_PHY_IQ_CAL_NUM_LOG_MAX
- AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S
- AR5K_PHY_IQ_CHAN_MASK_EN
- AR5K_PHY_IQ_CORR_ENABLE
- AR5K_PHY_IQ_CORR_Q_I_COFF
- AR5K_PHY_IQ_CORR_Q_I_COFF_S
- AR5K_PHY_IQ_CORR_Q_Q_COFF
- AR5K_PHY_IQ_CORR_Q_Q_COFF_S
- AR5K_PHY_IQ_EARLY_TRIG_THR
- AR5K_PHY_IQ_PILOT_MASK_EN
- AR5K_PHY_IQ_RUN
- AR5K_PHY_IQ_SPUR_FILT_EN
- AR5K_PHY_IQ_SPUR_RSSI_EN
- AR5K_PHY_IQ_USE_PT_DF
- AR5K_PHY_MAX_RX_LEN
- AR5K_PHY_MODE
- AR5K_PHY_MODE_FREQ
- AR5K_PHY_MODE_FREQ_2GHZ
- AR5K_PHY_MODE_FREQ_5GHZ
- AR5K_PHY_MODE_HALF_RATE
- AR5K_PHY_MODE_MOD
- AR5K_PHY_MODE_MOD_CCK
- AR5K_PHY_MODE_MOD_DYN
- AR5K_PHY_MODE_MOD_OFDM
- AR5K_PHY_MODE_QUARTER_RATE
- AR5K_PHY_MODE_RAD
- AR5K_PHY_MODE_RAD_RF5111
- AR5K_PHY_MODE_RAD_RF5112
- AR5K_PHY_MODE_XR
- AR5K_PHY_NF
- AR5K_PHY_NFTHRES
- AR5K_PHY_NF_M
- AR5K_PHY_NF_MINCCA_PWR
- AR5K_PHY_NF_MINCCA_PWR_S
- AR5K_PHY_NF_SVAL
- AR5K_PHY_NF_THRESH62
- AR5K_PHY_NF_THRESH62_S
- AR5K_PHY_OFDM_SELFCORR
- AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1
- AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN
- AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S
- AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3
- AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI
- AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR
- AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN
- AR5K_PHY_PAPD_I
- AR5K_PHY_PAPD_I_BASE
- AR5K_PHY_PAPD_PROBE
- AR5K_PHY_PAPD_PROBE_COMP_GAIN
- AR5K_PHY_PAPD_PROBE_GAINF
- AR5K_PHY_PAPD_PROBE_GAINF_S
- AR5K_PHY_PAPD_PROBE_INI_5111
- AR5K_PHY_PAPD_PROBE_INI_5112
- AR5K_PHY_PAPD_PROBE_PCDAC_BIAS
- AR5K_PHY_PAPD_PROBE_PREDIST_EN
- AR5K_PHY_PAPD_PROBE_SH_HI_PAR
- AR5K_PHY_PAPD_PROBE_TXPOWER
- AR5K_PHY_PAPD_PROBE_TXPOWER_S
- AR5K_PHY_PAPD_PROBE_TX_NEXT
- AR5K_PHY_PAPD_PROBE_TYPE
- AR5K_PHY_PAPD_PROBE_TYPE_CCK
- AR5K_PHY_PAPD_PROBE_TYPE_OFDM
- AR5K_PHY_PAPD_PROBE_TYPE_S
- AR5K_PHY_PAPD_PROBE_TYPE_XR
- AR5K_PHY_PA_CTL
- AR5K_PHY_PA_CTL_XPA_A_EN
- AR5K_PHY_PA_CTL_XPA_A_HI
- AR5K_PHY_PA_CTL_XPA_B_EN
- AR5K_PHY_PA_CTL_XPA_B_HI
- AR5K_PHY_PCDAC_TXPOWER
- AR5K_PHY_PCDAC_TXPOWER_BASE
- AR5K_PHY_PDADC_TXPOWER
- AR5K_PHY_PDADC_TXPOWER_BASE
- AR5K_PHY_PLL
- AR5K_PHY_PLL_20MHZ
- AR5K_PHY_PLL_40MHZ
- AR5K_PHY_PLL_40MHZ_5211
- AR5K_PHY_PLL_40MHZ_5212
- AR5K_PHY_PLL_40MHZ_5413
- AR5K_PHY_PLL_44MHZ
- AR5K_PHY_PLL_44MHZ_5211
- AR5K_PHY_PLL_44MHZ_5212
- AR5K_PHY_PLL_HALF_RATE
- AR5K_PHY_PLL_QUARTER_RATE
- AR5K_PHY_PLL_RF5111
- AR5K_PHY_PLL_RF5112
- AR5K_PHY_PTAT
- AR5K_PHY_RADAR
- AR5K_PHY_RADAR_DISABLE
- AR5K_PHY_RADAR_ENABLE
- AR5K_PHY_RADAR_FIRPWR_THR
- AR5K_PHY_RADAR_FIRPWR_THRS
- AR5K_PHY_RADAR_INBANDTHR
- AR5K_PHY_RADAR_INBANDTHR_S
- AR5K_PHY_RADAR_PHEIGHT_THR
- AR5K_PHY_RADAR_PHEIGHT_THR_S
- AR5K_PHY_RADAR_PRSSI_THR
- AR5K_PHY_RADAR_PRSSI_THR_S
- AR5K_PHY_RADAR_RSSI_THR
- AR5K_PHY_RADAR_RSSI_THR_S
- AR5K_PHY_RESTART
- AR5K_PHY_RESTART_DIV_GC
- AR5K_PHY_RESTART_DIV_GC_S
- AR5K_PHY_RFBUS_GRANT
- AR5K_PHY_RFBUS_GRANT_OK
- AR5K_PHY_RFBUS_REQ
- AR5K_PHY_RFBUS_REQ_REQUEST
- AR5K_PHY_RFSTG
- AR5K_PHY_RFSTG_DISABLE
- AR5K_PHY_RF_CTL2
- AR5K_PHY_RF_CTL2_TXF2TXD_START
- AR5K_PHY_RF_CTL2_TXF2TXD_START_S
- AR5K_PHY_RF_CTL3
- AR5K_PHY_RF_CTL3_TXE2XLNA_ON
- AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S
- AR5K_PHY_RF_CTL4
- AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF
- AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF
- AR5K_PHY_RF_CTL4_TXF2XPA_A_ON
- AR5K_PHY_RF_CTL4_TXF2XPA_B_ON
- AR5K_PHY_RX_DELAY
- AR5K_PHY_RX_DELAY_M
- AR5K_PHY_SCAL
- AR5K_PHY_SCAL_32MHZ
- AR5K_PHY_SCAL_32MHZ_2417
- AR5K_PHY_SCAL_32MHZ_5311
- AR5K_PHY_SCAL_32MHZ_HB63
- AR5K_PHY_SCLOCK
- AR5K_PHY_SCLOCK_32MHZ
- AR5K_PHY_SCR
- AR5K_PHY_SDELAY
- AR5K_PHY_SDELAY_32MHZ
- AR5K_PHY_SETTLING
- AR5K_PHY_SETTLING_AGC
- AR5K_PHY_SETTLING_AGC_S
- AR5K_PHY_SETTLING_SWITCH
- AR5K_PHY_SETTLING_SWITCH_S
- AR5K_PHY_SHIFT_2GHZ
- AR5K_PHY_SHIFT_5GHZ
- AR5K_PHY_SIG
- AR5K_PHY_SIGMA_DELTA
- AR5K_PHY_SIGMA_DELTA_ADC_CLIP
- AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S
- AR5K_PHY_SIGMA_DELTA_ADC_SEL
- AR5K_PHY_SIGMA_DELTA_ADC_SEL_S
- AR5K_PHY_SIGMA_DELTA_FILT1
- AR5K_PHY_SIGMA_DELTA_FILT1_S
- AR5K_PHY_SIGMA_DELTA_FILT2
- AR5K_PHY_SIGMA_DELTA_FILT2_S
- AR5K_PHY_SIG_FIRPWR
- AR5K_PHY_SIG_FIRPWR_S
- AR5K_PHY_SIG_FIRSTEP
- AR5K_PHY_SIG_FIRSTEP_S
- AR5K_PHY_SLMT
- AR5K_PHY_SLMT_32MHZ
- AR5K_PHY_SPENDING
- AR5K_PHY_SPUR_PWR
- AR5K_PHY_SPUR_PWR_FILT
- AR5K_PHY_SPUR_PWR_I
- AR5K_PHY_SPUR_PWR_Q
- AR5K_PHY_TIMING_10
- AR5K_PHY_TIMING_10_PILOT_MASK_2
- AR5K_PHY_TIMING_10_PILOT_MASK_2_S
- AR5K_PHY_TIMING_11
- AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE
- AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S
- AR5K_PHY_TIMING_11_SPUR_FREQ_SD
- AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S
- AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC
- AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR
- AR5K_PHY_TIMING_3
- AR5K_PHY_TIMING_3_DSC_EXP
- AR5K_PHY_TIMING_3_DSC_EXP_S
- AR5K_PHY_TIMING_3_DSC_MAN
- AR5K_PHY_TIMING_3_DSC_MAN_S
- AR5K_PHY_TIMING_7
- AR5K_PHY_TIMING_8
- AR5K_PHY_TIMING_8_PILOT_MASK_2
- AR5K_PHY_TIMING_8_PILOT_MASK_2_S
- AR5K_PHY_TIMING_9
- AR5K_PHY_TPC_RG1
- AR5K_PHY_TPC_RG1_NUM_PD_GAIN
- AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S
- AR5K_PHY_TPC_RG1_PDGAIN_1
- AR5K_PHY_TPC_RG1_PDGAIN_1_S
- AR5K_PHY_TPC_RG1_PDGAIN_2
- AR5K_PHY_TPC_RG1_PDGAIN_2_S
- AR5K_PHY_TPC_RG1_PDGAIN_3
- AR5K_PHY_TPC_RG1_PDGAIN_3_S
- AR5K_PHY_TPC_RG5
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4
- AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S
- AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
- AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S
- AR5K_PHY_TST1
- AR5K_PHY_TST1_TXHOLD
- AR5K_PHY_TST1_TXSRC_ALT
- AR5K_PHY_TST1_TXSRC_ALT_S
- AR5K_PHY_TST1_TXSRC_SRC
- AR5K_PHY_TST1_TXSRC_SRC_S
- AR5K_PHY_TST2
- AR5K_PHY_TST2_ADC_OBS_SEL
- AR5K_PHY_TST2_AGC_OBS_SEL_3
- AR5K_PHY_TST2_ALT_RFDATA
- AR5K_PHY_TST2_BBB_OBS_SEL
- AR5K_PHY_TST2_CBUS_MODE
- AR5K_PHY_TST2_CHANCOR_DUMP_EN
- AR5K_PHY_TST2_CLK32
- AR5K_PHY_TST2_EVEN_CHANCOR_DUMP
- AR5K_PHY_TST2_FORCE_AGC_CLR
- AR5K_PHY_TST2_MINI_OBS_EN
- AR5K_PHY_TST2_RFSILENT_EN
- AR5K_PHY_TST2_RX2_IS_RX5_INV
- AR5K_PHY_TST2_RX_CLR_SEL
- AR5K_PHY_TST2_SLOW_CLK160
- AR5K_PHY_TST2_TRIG
- AR5K_PHY_TST2_TRIG_SEL
- AR5K_PHY_TURBO
- AR5K_PHY_TURBO_MIMO
- AR5K_PHY_TURBO_MODE
- AR5K_PHY_TURBO_SHORT
- AR5K_PHY_TXPOWER_RATE1
- AR5K_PHY_TXPOWER_RATE2
- AR5K_PHY_TXPOWER_RATE3
- AR5K_PHY_TXPOWER_RATE4
- AR5K_PHY_TXPOWER_RATE_MAX
- AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE
- AR5K_PHY_TX_PWR_ADJ
- AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA
- AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S
- AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX
- AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S
- AR5K_PHY_WARM_RESET
- AR5K_PHY_WEAK_OFDM_HIGH_THR
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M1
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M2
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S
- AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S
- AR5K_PHY_WEAK_OFDM_LOW_THR
- AR5K_PHY_WEAK_OFDM_LOW_THR_M1
- AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S
- AR5K_PHY_WEAK_OFDM_LOW_THR_M2
- AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT
- AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S
- AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S
- AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN
- AR5K_PIMR
- AR5K_PISR
- AR5K_PKT_TYPE_ATIM
- AR5K_PKT_TYPE_BEACON
- AR5K_PKT_TYPE_NORMAL
- AR5K_PKT_TYPE_PIFS
- AR5K_PKT_TYPE_PROBE_RESP
- AR5K_PKT_TYPE_PSPOLL
- AR5K_PM_AUTO
- AR5K_PM_AWAKE
- AR5K_PM_FULL_SLEEP
- AR5K_PM_NETWORK_SLEEP
- AR5K_PM_UNDEFINED
- AR5K_PROFCNT_CYCLE
- AR5K_PROFCNT_RX
- AR5K_PROFCNT_RXCLR
- AR5K_PROFCNT_TX
- AR5K_PWRTABLE_LINEAR_PCDAC
- AR5K_PWRTABLE_PWR_TO_PCDAC
- AR5K_PWRTABLE_PWR_TO_PDADC
- AR5K_QCUDCU_CLKGT
- AR5K_QCUDCU_CLKGT_DCU
- AR5K_QCUDCU_CLKGT_QCU
- AR5K_QCU_CBB_ADDR
- AR5K_QCU_CBB_ADDR_S
- AR5K_QCU_CBB_SELECT
- AR5K_QCU_CBCFG
- AR5K_QCU_CBRCFG_BASE
- AR5K_QCU_CBRCFG_INTVAL
- AR5K_QCU_CBRCFG_INTVAL_S
- AR5K_QCU_CBRCFG_ORN_THRES
- AR5K_QCU_CBRCFG_ORN_THRES_S
- AR5K_QCU_GLOBAL_READ
- AR5K_QCU_GLOBAL_WRITE
- AR5K_QCU_MISC_BASE
- AR5K_QCU_MISC_BCN_ENABLE
- AR5K_QCU_MISC_CBREXP_BCN_DIS
- AR5K_QCU_MISC_CBREXP_DIS
- AR5K_QCU_MISC_CBR_RESET_CNT
- AR5K_QCU_MISC_CBR_THRES_ENABLE
- AR5K_QCU_MISC_DCU_CMP_EN
- AR5K_QCU_MISC_DCU_EARLY
- AR5K_QCU_MISC_FRSHED_ASAP
- AR5K_QCU_MISC_FRSHED_BCN_SENT_GT
- AR5K_QCU_MISC_FRSHED_CBR
- AR5K_QCU_MISC_FRSHED_DBA_GT
- AR5K_QCU_MISC_FRSHED_M
- AR5K_QCU_MISC_FRSHED_TIM_GT
- AR5K_QCU_MISC_ONESHOT_ENABLE
- AR5K_QCU_MISC_RDY_VEOL_POLICY
- AR5K_QCU_ONESHOTARM_CLEAR
- AR5K_QCU_ONESHOTARM_CLEAR_M
- AR5K_QCU_ONESHOTARM_SET
- AR5K_QCU_ONESHOTARM_SET_M
- AR5K_QCU_RDYTIMECFG_BASE
- AR5K_QCU_RDYTIMECFG_ENABLE
- AR5K_QCU_RDYTIMECFG_INTVAL
- AR5K_QCU_RDYTIMECFG_INTVAL_S
- AR5K_QCU_RDYTIMESHDN
- AR5K_QCU_RDYTIMESHDN_M
- AR5K_QCU_SLEEP_MASK
- AR5K_QCU_STS_BASE
- AR5K_QCU_STS_CBREXPCNT
- AR5K_QCU_STS_FRMPENDCNT
- AR5K_QCU_TXD
- AR5K_QCU_TXDP_BASE
- AR5K_QCU_TXE
- AR5K_QOS_NOACK
- AR5K_QOS_NOACK_2BIT_VALUES
- AR5K_QOS_NOACK_2BIT_VALUES_S
- AR5K_QOS_NOACK_BIT_OFFSET
- AR5K_QOS_NOACK_BIT_OFFSET_S
- AR5K_QOS_NOACK_BYTE_OFFSET
- AR5K_QOS_NOACK_BYTE_OFFSET_S
- AR5K_QUEUE_CBRCFG
- AR5K_QUEUE_DCU_SEQNUM
- AR5K_QUEUE_DFS_CHANNEL_TIME
- AR5K_QUEUE_DFS_LOCAL_IFS
- AR5K_QUEUE_DFS_MISC
- AR5K_QUEUE_DFS_RETRY_LIMIT
- AR5K_QUEUE_DISABLED
- AR5K_QUEUE_ENABLED
- AR5K_QUEUE_MISC
- AR5K_QUEUE_QCUMASK
- AR5K_QUEUE_RDYTIMECFG
- AR5K_QUEUE_REG
- AR5K_QUEUE_STATUS
- AR5K_QUEUE_TXDP
- AR5K_QUIET_CTL1
- AR5K_QUIET_CTL1_ACK_CTS_EN
- AR5K_QUIET_CTL1_NEXT_QT_TSF
- AR5K_QUIET_CTL1_NEXT_QT_TSF_S
- AR5K_QUIET_CTL1_QT_EN
- AR5K_QUIET_CTL2
- AR5K_QUIET_CTL2_QT_DUR
- AR5K_QUIET_CTL2_QT_DUR_S
- AR5K_QUIET_CTL2_QT_PER
- AR5K_QUIET_CTL2_QT_PER_S
- AR5K_Q_DISABLE_BITS
- AR5K_Q_ENABLE_BITS
- AR5K_RAC_PISR
- AR5K_RAC_SISR0
- AR5K_RAC_SISR1
- AR5K_RAC_SISR2
- AR5K_RAC_SISR3
- AR5K_RAC_SISR4
- AR5K_RATE2DB
- AR5K_RATE2DB_BASE
- AR5K_RATE_ACKSIFS
- AR5K_RATE_ACKSIFS_BASE
- AR5K_RATE_ACKSIFS_NORMAL
- AR5K_RATE_ACKSIFS_TURBO
- AR5K_RATE_DUR
- AR5K_RATE_DUR_BASE
- AR5K_REG_DISABLE_BITS
- AR5K_REG_ENABLE_BITS
- AR5K_REG_MASKED_BITS
- AR5K_REG_MS
- AR5K_REG_READ_Q
- AR5K_REG_SM
- AR5K_REG_WAIT
- AR5K_REG_WRITE_BITS
- AR5K_REG_WRITE_Q
- AR5K_RESET_CTL
- AR5K_RESET_CTL_BASEBAND
- AR5K_RESET_CTL_DMA
- AR5K_RESET_CTL_MAC
- AR5K_RESET_CTL_PCI
- AR5K_RESET_CTL_PCU
- AR5K_RESET_CTL_PHY
- AR5K_RETRY_CNT
- AR5K_RETRY_CNT_SLG
- AR5K_RETRY_CNT_SSH
- AR5K_RF2316
- AR5K_RF2316_DB_2GHZ
- AR5K_RF2316_OB_2GHZ
- AR5K_RF2316_RF_TURBO
- AR5K_RF2317
- AR5K_RF2413
- AR5K_RF2413_DB_2GHZ
- AR5K_RF2413_OB_2GHZ
- AR5K_RF2413_RF_TURBO
- AR5K_RF2425
- AR5K_RF2425_DB_2GHZ
- AR5K_RF2425_OB_2GHZ
- AR5K_RF2425_RF_TURBO
- AR5K_RF5110
- AR5K_RF5111
- AR5K_RF5111_DB_2GHZ
- AR5K_RF5111_DB_5GHZ
- AR5K_RF5111_GAIN_I
- AR5K_RF5111_MAX_TIME
- AR5K_RF5111_OB_2GHZ
- AR5K_RF5111_OB_5GHZ
- AR5K_RF5111_PLO_SEL
- AR5K_RF5111_PWD
- AR5K_RF5111_PWD_XPD
- AR5K_RF5111_RFGAIN_SEL
- AR5K_RF5111_RFGAIN_STEP
- AR5K_RF5111_RF_TURBO
- AR5K_RF5111_WAIT_I
- AR5K_RF5111_WAIT_S
- AR5K_RF5111_XPD_GAIN
- AR5K_RF5112
- AR5K_RF5112A_DB_2GHZ
- AR5K_RF5112A_DB_5GHZ
- AR5K_RF5112A_FIXED_BIAS_A
- AR5K_RF5112A_FIXED_BIAS_B
- AR5K_RF5112A_HIGH_VC_CP
- AR5K_RF5112A_LOW_VC_CP
- AR5K_RF5112A_MID_VC_CP
- AR5K_RF5112A_OB_2GHZ
- AR5K_RF5112A_OB_5GHZ
- AR5K_RF5112A_PAD2GND
- AR5K_RF5112A_PDGAINHI
- AR5K_RF5112A_PDGAINLO
- AR5K_RF5112A_PUSH_UP
- AR5K_RF5112A_PWD
- AR5K_RF5112A_XB2_LVL
- AR5K_RF5112A_XB5_LVL
- AR5K_RF5112A_XPD_SEL
- AR5K_RF5112X_GAIN_I
- AR5K_RF5112X_MIXGAIN_OVR
- AR5K_RF5112X_MIXGAIN_STEP
- AR5K_RF5112X_MIXVGA_OVR
- AR5K_RF5112X_PD_DELAY_A
- AR5K_RF5112X_PD_DELAY_B
- AR5K_RF5112X_PD_DELAY_XR
- AR5K_RF5112X_PD_PERIOD_A
- AR5K_RF5112X_PD_PERIOD_B
- AR5K_RF5112X_PD_PERIOD_XR
- AR5K_RF5112X_RF_TURBO
- AR5K_RF5112_DB_2GHZ
- AR5K_RF5112_DB_5GHZ
- AR5K_RF5112_FIXED_BIAS_A
- AR5K_RF5112_FIXED_BIAS_B
- AR5K_RF5112_OB_2GHZ
- AR5K_RF5112_OB_5GHZ
- AR5K_RF5112_PWD
- AR5K_RF5112_XPD_GAIN
- AR5K_RF5112_XPD_SEL
- AR5K_RF5413
- AR5K_RF5413_DB_2GHZ
- AR5K_RF5413_DB_5GHZ
- AR5K_RF5413_DERBY_CHAN_SEL_MODE
- AR5K_RF5413_OB_2GHZ
- AR5K_RF5413_OB_5GHZ
- AR5K_RF5413_PWD_ICLOBUF2G
- AR5K_RFCNT
- AR5K_RFCNT_M
- AR5K_RFCNT_RFCL
- AR5K_RFGAIN_ACTIVE
- AR5K_RFGAIN_INACTIVE
- AR5K_RFGAIN_NEED_CHANGE
- AR5K_RFGAIN_READ_REQUESTED
- AR5K_RF_BUFFER
- AR5K_RF_BUFFER_CONTROL_0
- AR5K_RF_BUFFER_CONTROL_1
- AR5K_RF_BUFFER_CONTROL_2
- AR5K_RF_BUFFER_CONTROL_3
- AR5K_RF_BUFFER_CONTROL_4
- AR5K_RF_BUFFER_CONTROL_5
- AR5K_RF_BUFFER_CONTROL_6
- AR5K_RF_DB_2GHZ
- AR5K_RF_DB_5GHZ
- AR5K_RF_DERBY_CHAN_SEL_MODE
- AR5K_RF_FIXED_BIAS_A
- AR5K_RF_FIXED_BIAS_B
- AR5K_RF_GAIN
- AR5K_RF_GAIN_BASE
- AR5K_RF_GAIN_I
- AR5K_RF_HIGH_VC_CP
- AR5K_RF_LOW_VC_CP
- AR5K_RF_MAX_TIME
- AR5K_RF_MID_VC_CP
- AR5K_RF_MIXGAIN_OVR
- AR5K_RF_MIXGAIN_STEP
- AR5K_RF_MIXVGA_OVR
- AR5K_RF_OB_2GHZ
- AR5K_RF_OB_5GHZ
- AR5K_RF_PAD2GND
- AR5K_RF_PD_DELAY_A
- AR5K_RF_PD_DELAY_B
- AR5K_RF_PD_DELAY_XR
- AR5K_RF_PD_GAIN_HI
- AR5K_RF_PD_GAIN_LO
- AR5K_RF_PD_PERIOD_A
- AR5K_RF_PD_PERIOD_B
- AR5K_RF_PD_PERIOD_XR
- AR5K_RF_PLO_SEL
- AR5K_RF_PUSH_UP
- AR5K_RF_PWD_130
- AR5K_RF_PWD_131
- AR5K_RF_PWD_132
- AR5K_RF_PWD_136
- AR5K_RF_PWD_137
- AR5K_RF_PWD_138
- AR5K_RF_PWD_166
- AR5K_RF_PWD_167
- AR5K_RF_PWD_84
- AR5K_RF_PWD_90
- AR5K_RF_PWD_ICLOBUF_2G
- AR5K_RF_PWD_XPD
- AR5K_RF_RFGAIN_SEL
- AR5K_RF_RFGAIN_STEP
- AR5K_RF_TURBO
- AR5K_RF_WAIT_I
- AR5K_RF_WAIT_S
- AR5K_RF_XB2_LVL
- AR5K_RF_XB5_LVL
- AR5K_RF_XPD_GAIN
- AR5K_RF_XPD_SEL
- AR5K_RPGTO
- AR5K_RPGTO_M
- AR5K_RSSI_EP_MULTIPLIER
- AR5K_RSSI_THR
- AR5K_RSSI_THR_BMISS
- AR5K_RSSI_THR_BMISS_5210
- AR5K_RSSI_THR_BMISS_5210_S
- AR5K_RSSI_THR_BMISS_5211
- AR5K_RSSI_THR_BMISS_5211_S
- AR5K_RSSI_THR_BMISS_S
- AR5K_RSSI_THR_M
- AR5K_RTSD0
- AR5K_RTSD0_12
- AR5K_RTSD0_12_S
- AR5K_RTSD0_18
- AR5K_RTSD0_18_S
- AR5K_RTSD0_6
- AR5K_RTSD0_6_S
- AR5K_RTSD0_9
- AR5K_RTSD0_9_S
- AR5K_RTSD1
- AR5K_RTSD1_24
- AR5K_RTSD1_24_S
- AR5K_RTSD1_36
- AR5K_RTSD1_36_S
- AR5K_RTSD1_48
- AR5K_RTSD1_48_S
- AR5K_RTSD1_54
- AR5K_RTSD1_54_S
- AR5K_RTS_FAIL
- AR5K_RTS_FAIL_5210
- AR5K_RTS_FAIL_5211
- AR5K_RTS_OK
- AR5K_RTS_OK_5210
- AR5K_RTS_OK_5211
- AR5K_RXCFG
- AR5K_RXCFG_DEF_ANTENNA
- AR5K_RXCFG_JUMBO_RXE
- AR5K_RXCFG_JUMBO_WRAP
- AR5K_RXCFG_SDMAMW
- AR5K_RXCFG_SDMAMW_S
- AR5K_RXCFG_SLE_ENTRY
- AR5K_RXCFG_ZLFDMA
- AR5K_RXDESC_INTREQ
- AR5K_RXDP
- AR5K_RXERR_CRC
- AR5K_RXERR_DECRYPT
- AR5K_RXERR_FIFO
- AR5K_RXERR_MIC
- AR5K_RXERR_PHY
- AR5K_RXJLA
- AR5K_RXKEYIX_INVALID
- AR5K_RXNOFRM
- AR5K_RXNOFRM_M
- AR5K_RX_FILTER
- AR5K_RX_FILTER_5210
- AR5K_RX_FILTER_5211
- AR5K_RX_FILTER_BCAST
- AR5K_RX_FILTER_BEACON
- AR5K_RX_FILTER_CONTROL
- AR5K_RX_FILTER_MCAST
- AR5K_RX_FILTER_PHYERR
- AR5K_RX_FILTER_PHYERR_5211
- AR5K_RX_FILTER_PHYERR_5212
- AR5K_RX_FILTER_PROBEREQ
- AR5K_RX_FILTER_PROM
- AR5K_RX_FILTER_RADARERR
- AR5K_RX_FILTER_RADARERR_5211
- AR5K_RX_FILTER_RADARERR_5212
- AR5K_RX_FILTER_UCAST
- AR5K_RX_FILTER_XRPOLL
- AR5K_RX_PHY_ERROR_CCK_HEADER_CRC
- AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL
- AR5K_RX_PHY_ERROR_CCK_RESTART
- AR5K_RX_PHY_ERROR_CCK_SERVICE
- AR5K_RX_PHY_ERROR_CCK_TIMING
- AR5K_RX_PHY_ERROR_LENGTH
- AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL
- AR5K_RX_PHY_ERROR_OFDM_POWER_DROP
- AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL
- AR5K_RX_PHY_ERROR_OFDM_RESTART
- AR5K_RX_PHY_ERROR_OFDM_SERVICE
- AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY
- AR5K_RX_PHY_ERROR_OFDM_TIMING
- AR5K_RX_PHY_ERROR_PARITY
- AR5K_RX_PHY_ERROR_RADAR
- AR5K_RX_PHY_ERROR_RATE
- AR5K_RX_PHY_ERROR_SERVICE
- AR5K_RX_PHY_ERROR_TIMING
- AR5K_RX_PHY_ERROR_TOR
- AR5K_RX_PHY_ERROR_UNDERRUN
- AR5K_SEQ_MASK
- AR5K_SET_SHORT_PREAMBLE
- AR5K_SFR
- AR5K_SFR_EN
- AR5K_SIMR0
- AR5K_SIMR0_QCU_TXDESC
- AR5K_SIMR0_QCU_TXDESC_S
- AR5K_SIMR0_QCU_TXOK
- AR5K_SIMR0_QCU_TXOK_S
- AR5K_SIMR1
- AR5K_SIMR1_QCU_TXEOL
- AR5K_SIMR1_QCU_TXEOL_S
- AR5K_SIMR1_QCU_TXERR
- AR5K_SIMR1_QCU_TXERR_S
- AR5K_SIMR2
- AR5K_SIMR2_BCN_TIMEOUT
- AR5K_SIMR2_CAB_END
- AR5K_SIMR2_CAB_TIMEOUT
- AR5K_SIMR2_DPERR
- AR5K_SIMR2_DTIM
- AR5K_SIMR2_DTIM_SYNC
- AR5K_SIMR2_MCABT
- AR5K_SIMR2_QCU_TXURN
- AR5K_SIMR2_QCU_TXURN_S
- AR5K_SIMR2_SSERR
- AR5K_SIMR2_TIM
- AR5K_SIMR2_TSFOOR
- AR5K_SIMR3
- AR5K_SIMR3_QCBRORN
- AR5K_SIMR3_QCBRORN_S
- AR5K_SIMR3_QCBRURN
- AR5K_SIMR3_QCBRURN_S
- AR5K_SIMR4
- AR5K_SIMR4_QTRIG
- AR5K_SIMR4_QTRIG_S
- AR5K_SISR0
- AR5K_SISR0_QCU_TXDESC
- AR5K_SISR0_QCU_TXDESC_S
- AR5K_SISR0_QCU_TXOK
- AR5K_SISR0_QCU_TXOK_S
- AR5K_SISR1
- AR5K_SISR1_QCU_TXEOL
- AR5K_SISR1_QCU_TXEOL_S
- AR5K_SISR1_QCU_TXERR
- AR5K_SISR1_QCU_TXERR_S
- AR5K_SISR2
- AR5K_SISR2_BCN_TIMEOUT
- AR5K_SISR2_CAB_END
- AR5K_SISR2_CAB_TIMEOUT
- AR5K_SISR2_DPERR
- AR5K_SISR2_DTIM
- AR5K_SISR2_DTIM_SYNC
- AR5K_SISR2_MCABT
- AR5K_SISR2_QCU_TXURN
- AR5K_SISR2_QCU_TXURN_S
- AR5K_SISR2_SSERR
- AR5K_SISR2_TIM
- AR5K_SISR2_TSFOOR
- AR5K_SISR3
- AR5K_SISR3_QCBRORN
- AR5K_SISR3_QCBRORN_S
- AR5K_SISR3_QCBRURN
- AR5K_SISR3_QCBRURN_S
- AR5K_SISR4
- AR5K_SISR4_QTRIG
- AR5K_SISR4_QTRIG_S
- AR5K_SLEEP0
- AR5K_SLEEP0_ASSUME_DTIM
- AR5K_SLEEP0_CABTO
- AR5K_SLEEP0_CABTO_S
- AR5K_SLEEP0_ENH_SLEEP_EN
- AR5K_SLEEP0_NEXT_DTIM
- AR5K_SLEEP0_NEXT_DTIM_S
- AR5K_SLEEP1
- AR5K_SLEEP1_BEACON_TO
- AR5K_SLEEP1_BEACON_TO_S
- AR5K_SLEEP1_NEXT_TIM
- AR5K_SLEEP1_NEXT_TIM_S
- AR5K_SLEEP2
- AR5K_SLEEP2_DTIM_PER
- AR5K_SLEEP2_DTIM_PER_S
- AR5K_SLEEP2_TIM_PER
- AR5K_SLEEP2_TIM_PER_S
- AR5K_SLEEP_CTL
- AR5K_SLEEP_CTL_DUR_TIM_POL
- AR5K_SLEEP_CTL_DUR_WRITE_POL
- AR5K_SLEEP_CTL_SLDUR
- AR5K_SLEEP_CTL_SLDUR_S
- AR5K_SLEEP_CTL_SLE
- AR5K_SLEEP_CTL_SLE_ALLOW
- AR5K_SLEEP_CTL_SLE_POL
- AR5K_SLEEP_CTL_SLE_S
- AR5K_SLEEP_CTL_SLE_SLP
- AR5K_SLEEP_CTL_SLE_UNITS
- AR5K_SLEEP_CTL_SLE_WAKE
- AR5K_SLOT_TIME
- AR5K_SLOT_TIME_20
- AR5K_SLOT_TIME_9
- AR5K_SLOT_TIME_MAX
- AR5K_SOFTLED_OFF
- AR5K_SOFTLED_ON
- AR5K_SOFTLED_PIN
- AR5K_SPUR_CHAN_WIDTH
- AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz
- AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz
- AR5K_SREV
- AR5K_SREV_AR2313_R8
- AR5K_SREV_AR2315_R6
- AR5K_SREV_AR2315_R7
- AR5K_SREV_AR2317_R1
- AR5K_SREV_AR2317_R2
- AR5K_SREV_AR2413
- AR5K_SREV_AR2414
- AR5K_SREV_AR2415
- AR5K_SREV_AR2417
- AR5K_SREV_AR2425
- AR5K_SREV_AR5210
- AR5K_SREV_AR5211
- AR5K_SREV_AR5212
- AR5K_SREV_AR5212_V4
- AR5K_SREV_AR5213
- AR5K_SREV_AR5213A
- AR5K_SREV_AR5311
- AR5K_SREV_AR5311A
- AR5K_SREV_AR5311B
- AR5K_SREV_AR5312_R2
- AR5K_SREV_AR5312_R7
- AR5K_SREV_AR5413
- AR5K_SREV_AR5414
- AR5K_SREV_AR5416
- AR5K_SREV_AR5418
- AR5K_SREV_AR5424
- AR5K_SREV_PHY_2413
- AR5K_SREV_PHY_2425
- AR5K_SREV_PHY_5211
- AR5K_SREV_PHY_5212
- AR5K_SREV_PHY_5212A
- AR5K_SREV_PHY_5212B
- AR5K_SREV_PHY_5413
- AR5K_SREV_RAD_2111
- AR5K_SREV_RAD_2112
- AR5K_SREV_RAD_2112A
- AR5K_SREV_RAD_2112B
- AR5K_SREV_RAD_2316
- AR5K_SREV_RAD_2317
- AR5K_SREV_RAD_2413
- AR5K_SREV_RAD_2425
- AR5K_SREV_RAD_5110
- AR5K_SREV_RAD_5111
- AR5K_SREV_RAD_5111A
- AR5K_SREV_RAD_5112
- AR5K_SREV_RAD_5112A
- AR5K_SREV_RAD_5112B
- AR5K_SREV_RAD_5133
- AR5K_SREV_RAD_5413
- AR5K_SREV_RAD_5424
- AR5K_SREV_REV
- AR5K_SREV_REV_S
- AR5K_SREV_UNKNOWN
- AR5K_SREV_VER
- AR5K_SREV_VER_S
- AR5K_STA_ID0
- AR5K_STA_ID0_ARRD_L32
- AR5K_STA_ID1
- AR5K_STA_ID1_ACKCTS_6MB
- AR5K_STA_ID1_ADDR_U16
- AR5K_STA_ID1_ADHOC
- AR5K_STA_ID1_ANTENNA_SETTINGS
- AR5K_STA_ID1_AP
- AR5K_STA_ID1_BASE_RATE_11B
- AR5K_STA_ID1_CBCIV_ENDIAN
- AR5K_STA_ID1_CRYPT_MIC_EN
- AR5K_STA_ID1_DEFAULT_ANTENNA
- AR5K_STA_ID1_DESC_ANTENNA
- AR5K_STA_ID1_KEYSRCH_MCAST
- AR5K_STA_ID1_KEYSRCH_MODE
- AR5K_STA_ID1_NO_KEYSRCH
- AR5K_STA_ID1_NO_PSPOLL
- AR5K_STA_ID1_PCF
- AR5K_STA_ID1_PCF_5210
- AR5K_STA_ID1_PCF_5211
- AR5K_STA_ID1_PRESERVE_SEQ_NUM
- AR5K_STA_ID1_PWR_SV
- AR5K_STA_ID1_RTS_DEF_ANTENNA
- AR5K_STA_ID1_SELFGEN_DEF_ANT
- AR5K_SWITCH_SETTLING
- AR5K_SWITCH_SETTLING_TURBO
- AR5K_TIMER0
- AR5K_TIMER0_5210
- AR5K_TIMER0_5211
- AR5K_TIMER1
- AR5K_TIMER1_5210
- AR5K_TIMER1_5211
- AR5K_TIMER2
- AR5K_TIMER2_5210
- AR5K_TIMER2_5211
- AR5K_TIMER3
- AR5K_TIMER3_5210
- AR5K_TIMER3_5211
- AR5K_TIME_OUT
- AR5K_TIME_OUT_ACK
- AR5K_TIME_OUT_ACK_S
- AR5K_TIME_OUT_CTS
- AR5K_TIME_OUT_CTS_S
- AR5K_TOPS
- AR5K_TOPS_M
- AR5K_TPC
- AR5K_TPC_ACK
- AR5K_TPC_ACK_S
- AR5K_TPC_CHIRP
- AR5K_TPC_CHIRP_S
- AR5K_TPC_CTS
- AR5K_TPC_CTS_S
- AR5K_TPC_DOPPLER
- AR5K_TPC_DOPPLER_S
- AR5K_TRIG_LVL
- AR5K_TSF_L32
- AR5K_TSF_L32_5210
- AR5K_TSF_L32_5211
- AR5K_TSF_PARM
- AR5K_TSF_PARM_INC
- AR5K_TSF_PARM_INC_S
- AR5K_TSF_THRES
- AR5K_TSF_U32
- AR5K_TSF_U32_5210
- AR5K_TSF_U32_5211
- AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF
- AR5K_TUNE_AIFS
- AR5K_TUNE_AIFS_11B
- AR5K_TUNE_AIFS_XR
- AR5K_TUNE_BEACON_INTERVAL
- AR5K_TUNE_BMISS_THRES
- AR5K_TUNE_CCA_MAX_GOOD_VALUE
- AR5K_TUNE_CWMAX
- AR5K_TUNE_CWMAX_11B
- AR5K_TUNE_CWMAX_XR
- AR5K_TUNE_CWMIN
- AR5K_TUNE_CWMIN_11B
- AR5K_TUNE_CWMIN_XR
- AR5K_TUNE_DEFAULT_TXPOWER
- AR5K_TUNE_DMA_BEACON_RESP
- AR5K_TUNE_MAX_TXPOWER
- AR5K_TUNE_MAX_TX_FIFO_THRES
- AR5K_TUNE_MIN_TX_FIFO_THRES
- AR5K_TUNE_NOISE_FLOOR
- AR5K_TUNE_REGISTER_DWELL_TIME
- AR5K_TUNE_REGISTER_TIMEOUT
- AR5K_TUNE_RSSI_THRES
- AR5K_TUNE_SW_BEACON_RESP
- AR5K_TUNE_TPC_TXPOWER
- AR5K_TXCFG
- AR5K_TXCFG_ADHOC_BCN_ATIM
- AR5K_TXCFG_ATIM_WINDOW_DEF_DIS
- AR5K_TXCFG_B_MODE
- AR5K_TXCFG_DCU_CACHING_DIS
- AR5K_TXCFG_DCU_DBL_BUF_DIS
- AR5K_TXCFG_DMASIZE
- AR5K_TXCFG_FRMPAD_DIS
- AR5K_TXCFG_JUMBO_DESC_EN
- AR5K_TXCFG_JUMBO_FRM_MODE
- AR5K_TXCFG_RDY_CBR_DIS
- AR5K_TXCFG_RTSRND
- AR5K_TXCFG_SDMAMR
- AR5K_TXCFG_SDMAMR_S
- AR5K_TXCFG_TXCONT_EN
- AR5K_TXCFG_TXFSTP
- AR5K_TXCFG_TXFULL
- AR5K_TXCFG_TXFULL_0B
- AR5K_TXCFG_TXFULL_128B
- AR5K_TXCFG_TXFULL_192B
- AR5K_TXCFG_TXFULL_256B
- AR5K_TXCFG_TXFULL_64B
- AR5K_TXCFG_TXFULL_S
- AR5K_TXDESC_CLRDMASK
- AR5K_TXDESC_CTSENA
- AR5K_TXDESC_INTREQ
- AR5K_TXDESC_NOACK
- AR5K_TXDESC_RTSENA
- AR5K_TXDESC_VEOL
- AR5K_TXEPOST
- AR5K_TXERR_FIFO
- AR5K_TXERR_FILT
- AR5K_TXERR_XRETRY
- AR5K_TXKEYIX_INVALID
- AR5K_TXNOFRM
- AR5K_TXNOFRM_M
- AR5K_TXNOFRM_QCU
- AR5K_TXNOFRM_QCU_S
- AR5K_TXPC
- AR5K_TXPC_ACK_M
- AR5K_TXPC_ACK_S
- AR5K_TXPC_CHIRP_M
- AR5K_TXPC_CHIRP_S
- AR5K_TXPC_CTS_M
- AR5K_TXPC_CTS_S
- AR5K_TXPC_DOPPLER
- AR5K_TXPC_DOPPLER_S
- AR5K_TXPOWER_CCK
- AR5K_TXPOWER_OFDM
- AR5K_TXQ_FLAG_BACKOFF_DISABLE
- AR5K_TXQ_FLAG_CBRORNINT_ENABLE
- AR5K_TXQ_FLAG_CBRURNINT_ENABLE
- AR5K_TXQ_FLAG_COMPRESSION_ENABLE
- AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
- AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS
- AR5K_TXQ_FLAG_QTRIGINT_ENABLE
- AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
- AR5K_TXQ_FLAG_TXDESCINT_ENABLE
- AR5K_TXQ_FLAG_TXEOLINT_ENABLE
- AR5K_TXQ_FLAG_TXERRINT_ENABLE
- AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE
- AR5K_TXQ_FLAG_TXOKINT_ENABLE
- AR5K_TXQ_FLAG_TXURNINT_ENABLE
- AR5K_TXSTAT_ALTRATE
- AR5K_TX_MASK0
- AR5K_TX_MASK1
- AR5K_TX_QUEUE_BEACON
- AR5K_TX_QUEUE_CAB
- AR5K_TX_QUEUE_DATA
- AR5K_TX_QUEUE_ID_BEACON
- AR5K_TX_QUEUE_ID_CAB
- AR5K_TX_QUEUE_ID_DATA_MAX
- AR5K_TX_QUEUE_ID_DATA_MIN
- AR5K_TX_QUEUE_ID_NOQCU_BEACON
- AR5K_TX_QUEUE_ID_NOQCU_DATA
- AR5K_TX_QUEUE_ID_UAPSD
- AR5K_TX_QUEUE_INACTIVE
- AR5K_TX_QUEUE_UAPSD
- AR5K_USEC
- AR5K_USEC_1
- AR5K_USEC_1_S
- AR5K_USEC_32
- AR5K_USEC_32_S
- AR5K_USEC_5210
- AR5K_USEC_5211
- AR5K_USEC_RX_LATENCY_5210
- AR5K_USEC_RX_LATENCY_5210_S
- AR5K_USEC_RX_LATENCY_5211
- AR5K_USEC_RX_LATENCY_5211_S
- AR5K_USEC_TX_LATENCY_5210
- AR5K_USEC_TX_LATENCY_5210_S
- AR5K_USEC_TX_LATENCY_5211
- AR5K_USEC_TX_LATENCY_5211_S
- AR5K_VERSION_MAC
- AR5K_VERSION_RAD
- AR5K_WME_AC_BE
- AR5K_WME_AC_BK
- AR5K_WME_AC_VI
- AR5K_WME_AC_VO
- AR5K_WOW_PAT_DATA
- AR5K_WOW_PAT_DATA_0_3_M
- AR5K_WOW_PAT_DATA_0_3_V
- AR5K_WOW_PAT_DATA_1_4_M
- AR5K_WOW_PAT_DATA_1_4_V
- AR5K_WOW_PAT_DATA_2_5_M
- AR5K_WOW_PAT_DATA_2_5_V
- AR5K_WOW_PAT_IDX
- AR5K_WOW_PCFG
- AR5K_WOW_PCFG_LONG_FRAME_POL
- AR5K_WOW_PCFG_PAT_0_EN
- AR5K_WOW_PCFG_PAT_1_EN
- AR5K_WOW_PCFG_PAT_2_EN
- AR5K_WOW_PCFG_PAT_3_EN
- AR5K_WOW_PCFG_PAT_4_EN
- AR5K_WOW_PCFG_PAT_5_EN
- AR5K_WOW_PCFG_PAT_MATCH_EN
- AR5K_WOW_PCFG_WOBMISS
- AR5K_XRCHIRP
- AR5K_XRCHIRP_GAP
- AR5K_XRCHIRP_SEND
- AR5K_XRDELAY
- AR5K_XRDELAY_CHIRP_DELAY_M
- AR5K_XRDELAY_CHIRP_DELAY_S
- AR5K_XRDELAY_SLOT_DELAY_M
- AR5K_XRDELAY_SLOT_DELAY_S
- AR5K_XRLAT_TX
- AR5K_XRMODE
- AR5K_XRMODE_FRAME_HOLD_M
- AR5K_XRMODE_FRAME_HOLD_S
- AR5K_XRMODE_POLL_SUBTYPE_M
- AR5K_XRMODE_POLL_SUBTYPE_S
- AR5K_XRMODE_POLL_TYPE_M
- AR5K_XRMODE_POLL_TYPE_S
- AR5K_XRMODE_POLL_WAIT_ALL
- AR5K_XRMODE_SIFS_DELAY
- AR5K_XRSTOMP
- AR5K_XRSTOMP_DATA
- AR5K_XRSTOMP_RSSI_THRES
- AR5K_XRSTOMP_RX
- AR5K_XRSTOMP_TX
- AR5K_XRSTOMP_TX_BSSID
- AR5K_XRSTOMP_TX_RSSI
- AR5K_XRTIMEOUT
- AR5K_XRTIMEOUT_CHIRP_M
- AR5K_XRTIMEOUT_CHIRP_S
- AR5K_XRTIMEOUT_POLL_M
- AR5K_XRTIMEOUT_POLL_S
- AR6003_BOARD_DATA_SZ
- AR6003_BOARD_EXT_DATA_SZ
- AR6003_BOARD_EXT_DATA_SZ_V2
- AR6003_CUST_DATA_SIZE
- AR6003_HW_1_0_VERSION
- AR6003_HW_2_0_BOARD_DATA_FILE
- AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE
- AR6003_HW_2_0_FIRMWARE_FILE
- AR6003_HW_2_0_FW_DIR
- AR6003_HW_2_0_OTP_FILE
- AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS
- AR6003_HW_2_0_PATCH_FILE
- AR6003_HW_2_0_TCMD_FIRMWARE_FILE
- AR6003_HW_2_0_VERSION
- AR6003_HW_2_1_1_BOARD_DATA_FILE
- AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE
- AR6003_HW_2_1_1_FIRMWARE_FILE
- AR6003_HW_2_1_1_FW_DIR
- AR6003_HW_2_1_1_OTP_FILE
- AR6003_HW_2_1_1_PATCH_FILE
- AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE
- AR6003_HW_2_1_1_TESTSCRIPT_FILE
- AR6003_HW_2_1_1_UTF_FIRMWARE_FILE
- AR6003_HW_2_1_1_VERSION
- AR6003_VTOP
- AR6004_BOARD_DATA_SZ
- AR6004_BOARD_EXT_DATA_SZ
- AR6004_HW_1_0_BOARD_DATA_FILE
- AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE
- AR6004_HW_1_0_FIRMWARE_FILE
- AR6004_HW_1_0_FW_DIR
- AR6004_HW_1_0_VERSION
- AR6004_HW_1_1_BOARD_DATA_FILE
- AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE
- AR6004_HW_1_1_FIRMWARE_FILE
- AR6004_HW_1_1_FW_DIR
- AR6004_HW_1_1_VERSION
- AR6004_HW_1_2_BOARD_DATA_FILE
- AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE
- AR6004_HW_1_2_FIRMWARE_FILE
- AR6004_HW_1_2_FW_DIR
- AR6004_HW_1_2_VERSION
- AR6004_HW_1_3_BOARD_DATA_FILE
- AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE
- AR6004_HW_1_3_FIRMWARE_FILE
- AR6004_HW_1_3_FW_DIR
- AR6004_HW_1_3_TCMD_FIRMWARE_FILE
- AR6004_HW_1_3_TESTSCRIPT_FILE
- AR6004_HW_1_3_UTF_FIRMWARE_FILE
- AR6004_HW_1_3_VERSION
- AR6004_HW_3_0_BOARD_DATA_FILE
- AR6004_HW_3_0_DEFAULT_BOARD_DATA_FILE
- AR6004_HW_3_0_FIRMWARE_FILE
- AR6004_HW_3_0_FW_DIR
- AR6004_HW_3_0_TCMD_FIRMWARE_FILE
- AR6004_HW_3_0_TESTSCRIPT_FILE
- AR6004_HW_3_0_UTF_FIRMWARE_FILE
- AR6004_HW_3_0_VERSION
- AR6004_VTOP
- AR7010_FIRMWARE_TEXT
- AR7010_GPIO_CLEAR
- AR7010_GPIO_FUNCTION
- AR7010_GPIO_IN
- AR7010_GPIO_INT
- AR7010_GPIO_INT_MASK
- AR7010_GPIO_INT_POLARITY
- AR7010_GPIO_INT_TYPE
- AR7010_GPIO_IN_VAL
- AR7010_GPIO_IN_VAL_S
- AR7010_GPIO_MASK
- AR7010_GPIO_OE
- AR7010_GPIO_OE_AS_INPUT
- AR7010_GPIO_OE_AS_OUTPUT
- AR7010_GPIO_OE_MASK
- AR7010_GPIO_OUT
- AR7010_GPIO_PENDING
- AR7010_GPIO_SET
- AR7010_NUM_GPIO
- AR7100
- AR71XX_AHB_DIV_MASK
- AR71XX_AHB_DIV_SHIFT
- AR71XX_APB_BASE
- AR71XX_BASE_FREQ
- AR71XX_CPU_DIV_MASK
- AR71XX_CPU_DIV_SHIFT
- AR71XX_DDR_CTRL_BASE
- AR71XX_DDR_CTRL_SIZE
- AR71XX_DDR_DIV_MASK
- AR71XX_DDR_DIV_SHIFT
- AR71XX_DDR_REG_FLUSH_GE0
- AR71XX_DDR_REG_FLUSH_GE1
- AR71XX_DDR_REG_FLUSH_PCI
- AR71XX_DDR_REG_FLUSH_USB
- AR71XX_DDR_REG_PCI_WIN0
- AR71XX_DDR_REG_PCI_WIN1
- AR71XX_DDR_REG_PCI_WIN2
- AR71XX_DDR_REG_PCI_WIN3
- AR71XX_DDR_REG_PCI_WIN4
- AR71XX_DDR_REG_PCI_WIN5
- AR71XX_DDR_REG_PCI_WIN6
- AR71XX_DDR_REG_PCI_WIN7
- AR71XX_EHCI_BASE
- AR71XX_EHCI_SIZE
- AR71XX_ETH0_PLL_SHIFT
- AR71XX_ETH1_PLL_SHIFT
- AR71XX_GE0_BASE
- AR71XX_GE0_SIZE
- AR71XX_GE1_BASE
- AR71XX_GE1_SIZE
- AR71XX_GPIO_BASE
- AR71XX_GPIO_COUNT
- AR71XX_GPIO_FUNC_SLIC_EN
- AR71XX_GPIO_FUNC_SPI_CS1_EN
- AR71XX_GPIO_FUNC_SPI_CS2_EN
- AR71XX_GPIO_FUNC_STEREO_EN
- AR71XX_GPIO_FUNC_UART_EN
- AR71XX_GPIO_FUNC_USB_CLK_EN
- AR71XX_GPIO_FUNC_USB_OC_EN
- AR71XX_GPIO_REG_CLEAR
- AR71XX_GPIO_REG_FUNC
- AR71XX_GPIO_REG_IN
- AR71XX_GPIO_REG_INT_ENABLE
- AR71XX_GPIO_REG_INT_MASK
- AR71XX_GPIO_REG_INT_MODE
- AR71XX_GPIO_REG_INT_PENDING
- AR71XX_GPIO_REG_INT_POLARITY
- AR71XX_GPIO_REG_INT_TYPE
- AR71XX_GPIO_REG_OE
- AR71XX_GPIO_REG_OUT
- AR71XX_GPIO_REG_SET
- AR71XX_GPIO_SIZE
- AR71XX_MII0_CTRL_IF_GMII
- AR71XX_MII0_CTRL_IF_MII
- AR71XX_MII0_CTRL_IF_RGMII
- AR71XX_MII0_CTRL_IF_RMII
- AR71XX_MII1_CTRL_IF_RGMII
- AR71XX_MII1_CTRL_IF_RMII
- AR71XX_MII_BASE
- AR71XX_MII_CTRL_IF_MASK
- AR71XX_MII_CTRL_SPEED_10
- AR71XX_MII_CTRL_SPEED_100
- AR71XX_MII_CTRL_SPEED_1000
- AR71XX_MII_CTRL_SPEED_MASK
- AR71XX_MII_CTRL_SPEED_SHIFT
- AR71XX_MII_REG_MII0_CTRL
- AR71XX_MII_REG_MII1_CTRL
- AR71XX_MII_SIZE
- AR71XX_OHCI_BASE
- AR71XX_OHCI_SIZE
- AR71XX_PCI_CFG_BASE
- AR71XX_PCI_CFG_CMD_READ
- AR71XX_PCI_CFG_CMD_WRITE
- AR71XX_PCI_CFG_SIZE
- AR71XX_PCI_CRP_CMD_READ
- AR71XX_PCI_CRP_CMD_WRITE
- AR71XX_PCI_INT_CORE
- AR71XX_PCI_INT_DEV0
- AR71XX_PCI_INT_DEV1
- AR71XX_PCI_INT_DEV2
- AR71XX_PCI_IRQ_COUNT
- AR71XX_PCI_MEM_BASE
- AR71XX_PCI_MEM_SIZE
- AR71XX_PCI_REG_AHB_ERR
- AR71XX_PCI_REG_AHB_ERR_ADDR
- AR71XX_PCI_REG_CFG_AD
- AR71XX_PCI_REG_CFG_CBE
- AR71XX_PCI_REG_CFG_RDDATA
- AR71XX_PCI_REG_CFG_WRDATA
- AR71XX_PCI_REG_CRP_AD_CBE
- AR71XX_PCI_REG_CRP_RDDATA
- AR71XX_PCI_REG_CRP_WRDATA
- AR71XX_PCI_REG_PCI_ERR
- AR71XX_PCI_REG_PCI_ERR_ADDR
- AR71XX_PCI_WIN0_OFFS
- AR71XX_PCI_WIN1_OFFS
- AR71XX_PCI_WIN2_OFFS
- AR71XX_PCI_WIN3_OFFS
- AR71XX_PCI_WIN4_OFFS
- AR71XX_PCI_WIN5_OFFS
- AR71XX_PCI_WIN6_OFFS
- AR71XX_PCI_WIN7_OFFS
- AR71XX_PLL_BASE
- AR71XX_PLL_FB_MASK
- AR71XX_PLL_FB_SHIFT
- AR71XX_PLL_REG_CPU_CONFIG
- AR71XX_PLL_REG_ETH0_INT_CLOCK
- AR71XX_PLL_REG_ETH1_INT_CLOCK
- AR71XX_PLL_REG_SEC_CONFIG
- AR71XX_PLL_SIZE
- AR71XX_RESET_BASE
- AR71XX_RESET_CPU_COLD
- AR71XX_RESET_CPU_NMI
- AR71XX_RESET_DDR
- AR71XX_RESET_DMA
- AR71XX_RESET_EXTERNAL
- AR71XX_RESET_FULL_CHIP
- AR71XX_RESET_GE0_MAC
- AR71XX_RESET_GE0_PHY
- AR71XX_RESET_GE1_MAC
- AR71XX_RESET_GE1_PHY
- AR71XX_RESET_PCI_BUS
- AR71XX_RESET_PCI_CORE
- AR71XX_RESET_REG_GLOBAL_INT_STATUS
- AR71XX_RESET_REG_MISC_INT_ENABLE
- AR71XX_RESET_REG_MISC_INT_STATUS
- AR71XX_RESET_REG_PCI_INT_ENABLE
- AR71XX_RESET_REG_PCI_INT_STATUS
- AR71XX_RESET_REG_PERFC0
- AR71XX_RESET_REG_PERFC1
- AR71XX_RESET_REG_PERFC_CTRL
- AR71XX_RESET_REG_RESET_MODULE
- AR71XX_RESET_REG_REV_ID
- AR71XX_RESET_REG_TIMER
- AR71XX_RESET_REG_TIMER_RELOAD
- AR71XX_RESET_REG_WDOG
- AR71XX_RESET_REG_WDOG_CTRL
- AR71XX_RESET_SIZE
- AR71XX_RESET_SLIC
- AR71XX_RESET_STEREO
- AR71XX_RESET_USBSUS_OVERRIDE
- AR71XX_RESET_USB_HOST
- AR71XX_RESET_USB_OHCI_DLL
- AR71XX_RESET_USB_PHY
- AR71XX_REV_ID_MINOR_AR7130
- AR71XX_REV_ID_MINOR_AR7141
- AR71XX_REV_ID_MINOR_AR7161
- AR71XX_REV_ID_MINOR_MASK
- AR71XX_REV_ID_REVISION_MASK
- AR71XX_REV_ID_REVISION_SHIFT
- AR71XX_SPI_BASE
- AR71XX_SPI_CTRL_DIV_MASK
- AR71XX_SPI_CTRL_RD
- AR71XX_SPI_FS_GPIO
- AR71XX_SPI_IOC_CLK
- AR71XX_SPI_IOC_CS
- AR71XX_SPI_IOC_CS0
- AR71XX_SPI_IOC_CS1
- AR71XX_SPI_IOC_CS2
- AR71XX_SPI_IOC_CS_ALL
- AR71XX_SPI_IOC_DO
- AR71XX_SPI_REG_CTRL
- AR71XX_SPI_REG_FS
- AR71XX_SPI_REG_IOC
- AR71XX_SPI_REG_RDS
- AR71XX_SPI_SIZE
- AR71XX_UART_BASE
- AR71XX_UART_SIZE
- AR71XX_USB_CTRL_BASE
- AR71XX_USB_CTRL_REG_CONFIG
- AR71XX_USB_CTRL_REG_FLADJ
- AR71XX_USB_CTRL_SIZE
- AR7240
- AR7240_BAR0_WAR_VALUE
- AR7240_GPIO_COUNT
- AR7240_OHCI_BASE
- AR7240_OHCI_SIZE
- AR7240_RESET_OHCI_DLL
- AR7240_RESET_USB_HOST
- AR7240_USB_CTRL_BASE
- AR7240_USB_CTRL_SIZE
- AR7241_GPIO_COUNT
- AR7242_PLL_REG_ETH0_INT_CLOCK
- AR724X_AHB_DIV_MASK
- AR724X_AHB_DIV_SHIFT
- AR724X_BASE_FREQ
- AR724X_DDR_DIV_MASK
- AR724X_DDR_DIV_SHIFT
- AR724X_DDR_REG_FLUSH_GE0
- AR724X_DDR_REG_FLUSH_GE1
- AR724X_DDR_REG_FLUSH_PCIE
- AR724X_DDR_REG_FLUSH_USB
- AR724X_EHCI_BASE
- AR724X_EHCI_SIZE
- AR724X_GPIO_FUNC_CLK_OBS1_EN
- AR724X_GPIO_FUNC_CLK_OBS2_EN
- AR724X_GPIO_FUNC_CLK_OBS3_EN
- AR724X_GPIO_FUNC_CLK_OBS4_EN
- AR724X_GPIO_FUNC_CLK_OBS5_EN
- AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN
- AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN
- AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN
- AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN
- AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN
- AR724X_GPIO_FUNC_GE0_MII_CLK_EN
- AR724X_GPIO_FUNC_JTAG_DISABLE
- AR724X_GPIO_FUNC_SPI_CS_EN1
- AR724X_GPIO_FUNC_SPI_CS_EN2
- AR724X_GPIO_FUNC_SPI_EN
- AR724X_GPIO_FUNC_UART_EN
- AR724X_GPIO_FUNC_UART_RTS_CTS_EN
- AR724X_PCI_APP_LTSSM_ENABLE
- AR724X_PCI_CFG_BASE
- AR724X_PCI_CFG_SIZE
- AR724X_PCI_CMD_INIT
- AR724X_PCI_CRP_BASE
- AR724X_PCI_CRP_SIZE
- AR724X_PCI_CTRL_BASE
- AR724X_PCI_CTRL_SIZE
- AR724X_PCI_INT_DEV0
- AR724X_PCI_IRQ_COUNT
- AR724X_PCI_MEM_BASE
- AR724X_PCI_MEM_SIZE
- AR724X_PCI_REG_APP
- AR724X_PCI_REG_INT_MASK
- AR724X_PCI_REG_INT_STATUS
- AR724X_PCI_REG_RESET
- AR724X_PCI_RESET_LINK_UP
- AR724X_PLL_FB_MASK
- AR724X_PLL_FB_SHIFT
- AR724X_PLL_REF_DIV_MASK
- AR724X_PLL_REF_DIV_SHIFT
- AR724X_PLL_REG_CPU_CONFIG
- AR724X_PLL_REG_PCIE_CONFIG
- AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS
- AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET
- AR724X_RESET_GE0_MDIO
- AR724X_RESET_GE1_MDIO
- AR724X_RESET_PCIE
- AR724X_RESET_PCIE_PHY
- AR724X_RESET_PCIE_PHY_SERIAL
- AR724X_RESET_REG_RESET_MODULE
- AR724X_RESET_USBSUS_OVERRIDE
- AR724X_RESET_USB_HOST
- AR724X_RESET_USB_PHY
- AR724X_REV_ID_REVISION_MASK
- AR7_AFE_CLOCK
- AR7_CHIP_7100
- AR7_CHIP_7200
- AR7_CHIP_7300
- AR7_CHIP_TITAN
- AR7_GPIO_DIR
- AR7_GPIO_ENABLE
- AR7_GPIO_INPUT
- AR7_GPIO_MAX
- AR7_GPIO_OUTPUT
- AR7_IRQ_UART0
- AR7_IRQ_UART1
- AR7_PARTS
- AR7_REF_CLOCK
- AR7_REGS_BASE
- AR7_REGS_CLOCKS
- AR7_REGS_DCL
- AR7_REGS_GPIO
- AR7_REGS_IRQ
- AR7_REGS_MAC0
- AR7_REGS_MAC1
- AR7_REGS_MDIO
- AR7_REGS_PINSEL
- AR7_REGS_POWER
- AR7_REGS_RESET
- AR7_REGS_UART0
- AR7_REGS_USB
- AR7_REGS_VLYNQ0
- AR7_REGS_VLYNQ1
- AR7_REGS_WDT
- AR7_RESET_BIT_CPMAC_HI
- AR7_RESET_BIT_CPMAC_LO
- AR7_RESET_BIT_EPHY
- AR7_RESET_BIT_MDIO
- AR7_RESET_PERIPHERAL
- AR7_RESET_SOFTWARE
- AR7_RESET_STATUS
- AR7_SDRAM_BASE
- AR7_WDT_HW_ENA
- AR7_XTAL_CLOCK
- AR9002_PHY_AGC_CONTROL
- AR9002_PHY_H
- AR9003TXC_CONST
- AR9003_AIC_H
- AR9003_EEPROM_H
- AR9003_MAC_H
- AR9003_MCI_H
- AR9003_PHY_AGC_CONTROL
- AR9003_PHY_H
- AR9003_RTT_H
- AR9130
- AR913X_AHB_DIV_MASK
- AR913X_AHB_DIV_SHIFT
- AR913X_DDR_DIV_MASK
- AR913X_DDR_DIV_SHIFT
- AR913X_DDR_REG_FLUSH_GE0
- AR913X_DDR_REG_FLUSH_GE1
- AR913X_DDR_REG_FLUSH_USB
- AR913X_DDR_REG_FLUSH_WMAC
- AR913X_EHCI_BASE
- AR913X_EHCI_SIZE
- AR913X_ETH0_PLL_SHIFT
- AR913X_ETH1_PLL_SHIFT
- AR913X_GPIO_COUNT
- AR913X_GPIO_FUNC_EXP_PORT_CS_EN
- AR913X_GPIO_FUNC_I2S0_EN
- AR913X_GPIO_FUNC_I2S1_EN
- AR913X_GPIO_FUNC_I2S_MCKEN
- AR913X_GPIO_FUNC_I2S_REFCLKEN
- AR913X_GPIO_FUNC_SLIC_EN
- AR913X_GPIO_FUNC_UART_EN
- AR913X_GPIO_FUNC_UART_RTSCTS_EN
- AR913X_GPIO_FUNC_USB_CLK_EN
- AR913X_GPIO_FUNC_WMAC_LED_EN
- AR913X_PLL_FB_MASK
- AR913X_PLL_FB_SHIFT
- AR913X_PLL_REG_CPU_CONFIG
- AR913X_PLL_REG_ETH0_INT_CLOCK
- AR913X_PLL_REG_ETH1_INT_CLOCK
- AR913X_PLL_REG_ETH_CONFIG
- AR913X_RESET_AMBA2WMAC
- AR913X_RESET_REG_GLOBAL_INT_STATUS
- AR913X_RESET_REG_PERFC0
- AR913X_RESET_REG_PERFC1
- AR913X_RESET_REG_PERF_CTRL
- AR913X_RESET_REG_RESET_MODULE
- AR913X_RESET_USBSUS_OVERRIDE
- AR913X_RESET_USB_HOST
- AR913X_RESET_USB_PHY
- AR913X_REV_ID_MINOR_AR9130
- AR913X_REV_ID_MINOR_AR9132
- AR913X_REV_ID_MINOR_MASK
- AR913X_REV_ID_REVISION_MASK
- AR913X_REV_ID_REVISION_SHIFT
- AR913X_WMAC_BASE
- AR913X_WMAC_SIZE
- AR9160_DEVID_PCI
- AR9170_BCN_CTRL_LOCK
- AR9170_BCN_CTRL_READY
- AR9170_CALCTL_EDGE_FLAGS
- AR9170_CAM_MAX_KEY_LENGTH
- AR9170_CAM_MAX_USER
- AR9170_DMA_TRIGGER_RXQ
- AR9170_DMA_TRIGGER_TXQ0
- AR9170_DMA_TRIGGER_TXQ1
- AR9170_DMA_TRIGGER_TXQ2
- AR9170_DMA_TRIGGER_TXQ3
- AR9170_DMA_TRIGGER_TXQ4
- AR9170_EEPROM_CLOCK_DIV_FAC
- AR9170_EEPROM_CLOCK_DIV_FAC_10MHZ
- AR9170_EEPROM_CLOCK_DIV_FAC_312KHZ
- AR9170_EEPROM_CLOCK_DIV_FAC_39KHZ
- AR9170_EEPROM_CLOCK_DIV_FAC_78KHZ
- AR9170_EEPROM_CLOCK_DIV_FAC_S
- AR9170_EEPROM_CLOCK_DIV_SOFT_RST
- AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS
- AR9170_EEPROM_REG_BASE
- AR9170_EEPROM_REG_CLOCK_DIV
- AR9170_EEPROM_REG_MODE
- AR9170_EEPROM_REG_WP_MAGIC1
- AR9170_EEPROM_REG_WP_MAGIC2
- AR9170_EEPROM_REG_WP_MAGIC3
- AR9170_EEPROM_REG_WRITE_PROTECT
- AR9170_EEPROM_START
- AR9170_EEPROM_WP_MAGIC1
- AR9170_EEPROM_WP_MAGIC2
- AR9170_EEPROM_WP_MAGIC3
- AR9170_EEPROM_WRITE_PROTECT_WP_SET
- AR9170_EEPROM_WRITE_PROTECT_WP_STATUS
- AR9170_ENC_ALG_AESCCMP
- AR9170_ENC_ALG_CENC
- AR9170_ENC_ALG_NONE
- AR9170_ENC_ALG_TKIP
- AR9170_ENC_ALG_WEP128
- AR9170_ENC_ALG_WEP256
- AR9170_ENC_ALG_WEP64
- AR9170_FORCE_CLKEN_CCK_MRC_MUX
- AR9170_GPIO_PORT_LED_0
- AR9170_GPIO_PORT_LED_1
- AR9170_GPIO_PORT_WPS_BUTTON_PRESSED
- AR9170_GPIO_REG_BASE
- AR9170_GPIO_REG_PORT_DATA
- AR9170_GPIO_REG_PORT_TYPE
- AR9170_INT_FLAG_ETHERNET_BIT
- AR9170_INT_FLAG_EXT_BIT
- AR9170_INT_FLAG_PTAB_BIT
- AR9170_INT_FLAG_SE_BIT
- AR9170_INT_FLAG_SW_BIT
- AR9170_INT_FLAG_TIMER_BIT
- AR9170_INT_FLAG_UART_BIT
- AR9170_INT_FLAG_USB_BIT
- AR9170_INT_FLAG_WLAN
- AR9170_INT_INT_IRQ_ENCODE
- AR9170_INT_REG_BASE
- AR9170_INT_REG_EXT_INT_CONTROL
- AR9170_INT_REG_FIQ_ENCODE
- AR9170_INT_REG_FIQ_MASK
- AR9170_INT_REG_FLAG
- AR9170_INT_REG_IRQ_MASK
- AR9170_INT_REG_PRIORITY1
- AR9170_INT_REG_PRIORITY2
- AR9170_INT_REG_PRIORITY3
- AR9170_INT_REG_SW_INT_CONTROL
- AR9170_INT_SW_INT_ENABLE
- AR9170_LED_MODE_CONN_STATE
- AR9170_LED_MODE_CONN_STATE_FORCE_OFF
- AR9170_LED_MODE_CONN_STATE_FORCE_ON
- AR9170_LED_MODE_CONN_STATE_IOFF_AON
- AR9170_LED_MODE_CONN_STATE_ION_AOFF
- AR9170_LED_MODE_CONN_STATE_S
- AR9170_LED_MODE_DISABLE_STATE
- AR9170_LED_MODE_FREQUENCY
- AR9170_LED_MODE_FREQUENCY_0_125HZ
- AR9170_LED_MODE_FREQUENCY_0_25HZ
- AR9170_LED_MODE_FREQUENCY_0_5HZ
- AR9170_LED_MODE_FREQUENCY_1HZ
- AR9170_LED_MODE_FREQUENCY_S
- AR9170_LED_MODE_MODE
- AR9170_LED_MODE_OFF_IN_PSM
- AR9170_LED_MODE_POWER_ON
- AR9170_LED_MODE_RESERVED
- AR9170_LED_MODE_RESERVED2
- AR9170_LED_MODE_TOFF_SCAN
- AR9170_LED_MODE_TOFF_SCAN_S
- AR9170_LED_MODE_TON_SCAN
- AR9170_LED_MODE_TON_SCAN_S
- AR9170_MAC_AMPDU_DENSITY
- AR9170_MAC_AMPDU_DENSITY_S
- AR9170_MAC_AMPDU_FACTOR
- AR9170_MAC_AMPDU_FACTOR_S
- AR9170_MAC_ATIM_PERIOD
- AR9170_MAC_ATIM_PERIOD_S
- AR9170_MAC_BACKOFF_CCA
- AR9170_MAC_BACKOFF_MD_READY
- AR9170_MAC_BACKOFF_RX_PE
- AR9170_MAC_BACKOFF_TX_PE
- AR9170_MAC_BACKOFF_TX_PEX
- AR9170_MAC_BCN_AP_MODE
- AR9170_MAC_BCN_DTIM
- AR9170_MAC_BCN_DTIM_S
- AR9170_MAC_BCN_HT1_BF_MCS
- AR9170_MAC_BCN_HT1_BF_MCS_S
- AR9170_MAC_BCN_HT1_BWC_20M_EXT
- AR9170_MAC_BCN_HT1_BWC_40M_DUP
- AR9170_MAC_BCN_HT1_BWC_40M_SHARED
- AR9170_MAC_BCN_HT1_CHAIN_MASK
- AR9170_MAC_BCN_HT1_CHAIN_MASK_S
- AR9170_MAC_BCN_HT1_GF_PMB
- AR9170_MAC_BCN_HT1_HT_EN
- AR9170_MAC_BCN_HT1_NUM_LFT
- AR9170_MAC_BCN_HT1_NUM_LFT_S
- AR9170_MAC_BCN_HT1_PWR_CTRL
- AR9170_MAC_BCN_HT1_PWR_CTRL_S
- AR9170_MAC_BCN_HT1_SP_EXP
- AR9170_MAC_BCN_HT1_TPC
- AR9170_MAC_BCN_HT1_TPC_S
- AR9170_MAC_BCN_HT1_TX_ANT0
- AR9170_MAC_BCN_HT1_TX_ANT1
- AR9170_MAC_BCN_HT1_TX_BF
- AR9170_MAC_BCN_HT2_ADV_COD
- AR9170_MAC_BCN_HT2_BW40
- AR9170_MAC_BCN_HT2_LEN
- AR9170_MAC_BCN_HT2_LEN_S
- AR9170_MAC_BCN_HT2_MCS
- AR9170_MAC_BCN_HT2_MCS_S
- AR9170_MAC_BCN_HT2_NSS
- AR9170_MAC_BCN_HT2_SGI
- AR9170_MAC_BCN_HT2_SMOOTHING
- AR9170_MAC_BCN_HT2_SS
- AR9170_MAC_BCN_HT2_STBC
- AR9170_MAC_BCN_HT2_STBC_S
- AR9170_MAC_BCN_IBSS_MODE
- AR9170_MAC_BCN_LENGTH_MAX
- AR9170_MAC_BCN_PERIOD
- AR9170_MAC_BCN_PERIOD_S
- AR9170_MAC_BCN_PWR_MGT
- AR9170_MAC_BCN_STA_PS
- AR9170_MAC_CAM_ADDR_WRITE
- AR9170_MAC_CAM_AP
- AR9170_MAC_CAM_AP_WDS
- AR9170_MAC_CAM_DEFAULTS
- AR9170_MAC_CAM_HOST_PENDING
- AR9170_MAC_CAM_IBSS
- AR9170_MAC_CAM_STA
- AR9170_MAC_CAM_STATE_READ_PENDING
- AR9170_MAC_CAM_STATE_WRITE_PENDING
- AR9170_MAC_ENCRYPTION_DEFAULTS
- AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE
- AR9170_MAC_ENCRYPTION_RX_SOFTWARE
- AR9170_MAC_FCS_FIFO_PROT
- AR9170_MAC_FCS_SWFCS
- AR9170_MAC_FTF_ACK
- AR9170_MAC_FTF_ASSOC_REQ
- AR9170_MAC_FTF_ASSOC_RESP
- AR9170_MAC_FTF_ATIM
- AR9170_MAC_FTF_AUTH
- AR9170_MAC_FTF_BA
- AR9170_MAC_FTF_BAR
- AR9170_MAC_FTF_BEACON
- AR9170_MAC_FTF_BIT13
- AR9170_MAC_FTF_BIT14
- AR9170_MAC_FTF_BIT15
- AR9170_MAC_FTF_BIT6
- AR9170_MAC_FTF_BIT7
- AR9170_MAC_FTF_CFE
- AR9170_MAC_FTF_CFE_ACK
- AR9170_MAC_FTF_CTS
- AR9170_MAC_FTF_DEASSOC
- AR9170_MAC_FTF_DEAUTH
- AR9170_MAC_FTF_DEFAULTS
- AR9170_MAC_FTF_MONITOR
- AR9170_MAC_FTF_PRB_REQ
- AR9170_MAC_FTF_PRB_RESP
- AR9170_MAC_FTF_PSPOLL
- AR9170_MAC_FTF_REASSOC_REQ
- AR9170_MAC_FTF_REASSOC_RESP
- AR9170_MAC_FTF_RTS
- AR9170_MAC_INT_ABORT
- AR9170_MAC_INT_ATIM
- AR9170_MAC_INT_CFG_BCN
- AR9170_MAC_INT_DECRY_NOUSER
- AR9170_MAC_INT_DTIM
- AR9170_MAC_INT_KEY_GEN
- AR9170_MAC_INT_MIMO_PS
- AR9170_MAC_INT_PRETBTT
- AR9170_MAC_INT_QOS
- AR9170_MAC_INT_QUIET_FRAME
- AR9170_MAC_INT_RADAR
- AR9170_MAC_INT_RETRY_FAIL
- AR9170_MAC_INT_RXC
- AR9170_MAC_INT_TXC
- AR9170_MAC_INT_WAKEUP
- AR9170_MAC_POWER_STATE_CTRL_RESET
- AR9170_MAC_PRETBTT
- AR9170_MAC_PRETBTT2
- AR9170_MAC_PRETBTT2_S
- AR9170_MAC_PRETBTT_S
- AR9170_MAC_REG_AC0_CW
- AR9170_MAC_REG_AC1_AC0_TXOP
- AR9170_MAC_REG_AC1_CW
- AR9170_MAC_REG_AC2_AC1_AC0_AIFS
- AR9170_MAC_REG_AC2_CW
- AR9170_MAC_REG_AC3_AC2_TXOP
- AR9170_MAC_REG_AC3_CW
- AR9170_MAC_REG_AC4_AC3_AC2_AIFS
- AR9170_MAC_REG_AC4_CW
- AR9170_MAC_REG_ACK_EXTENSION
- AR9170_MAC_REG_ACK_FC
- AR9170_MAC_REG_ACK_TABLE
- AR9170_MAC_REG_ACK_TPC
- AR9170_MAC_REG_AFTER_PNP
- AR9170_MAC_REG_AMPDU_COUNT
- AR9170_MAC_REG_AMPDU_DENSITY
- AR9170_MAC_REG_AMPDU_FACTOR
- AR9170_MAC_REG_AMPDU_RX_THRESH
- AR9170_MAC_REG_ATIM_WINDOW
- AR9170_MAC_REG_BACKOFF_PROTECT
- AR9170_MAC_REG_BACKOFF_STATUS
- AR9170_MAC_REG_BASE
- AR9170_MAC_REG_BASIC_RATE
- AR9170_MAC_REG_BCN_ADDR
- AR9170_MAC_REG_BCN_COUNT
- AR9170_MAC_REG_BCN_CTRL
- AR9170_MAC_REG_BCN_CURR_ADDR
- AR9170_MAC_REG_BCN_HT1
- AR9170_MAC_REG_BCN_HT2
- AR9170_MAC_REG_BCN_LENGTH
- AR9170_MAC_REG_BCN_PERIOD
- AR9170_MAC_REG_BCN_PLCP
- AR9170_MAC_REG_BCN_STATUS
- AR9170_MAC_REG_BSSID_H
- AR9170_MAC_REG_BSSID_L
- AR9170_MAC_REG_CAM_ADDR
- AR9170_MAC_REG_CAM_DATA0
- AR9170_MAC_REG_CAM_DATA1
- AR9170_MAC_REG_CAM_DATA2
- AR9170_MAC_REG_CAM_DATA3
- AR9170_MAC_REG_CAM_DBG0
- AR9170_MAC_REG_CAM_DBG1
- AR9170_MAC_REG_CAM_DBG2
- AR9170_MAC_REG_CAM_MODE
- AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H
- AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L
- AR9170_MAC_REG_CAM_RXKEY
- AR9170_MAC_REG_CAM_RX_ENC_TYPE
- AR9170_MAC_REG_CAM_RX_SERACH_HIT
- AR9170_MAC_REG_CAM_STATE
- AR9170_MAC_REG_CAM_TXKEY
- AR9170_MAC_REG_CAM_TX_ENC_TYPE
- AR9170_MAC_REG_CAM_TX_SERACH_HIT
- AR9170_MAC_REG_CFEND_QOSNULL_TPC
- AR9170_MAC_REG_CHANNEL_BUSY
- AR9170_MAC_REG_CONTENTION_POINT
- AR9170_MAC_REG_DMA_RXQ_ADDR
- AR9170_MAC_REG_DMA_RXQ_CURR_ADDR
- AR9170_MAC_REG_DMA_STATUS
- AR9170_MAC_REG_DMA_TRIGGER
- AR9170_MAC_REG_DMA_TXQ0Q1_LEN
- AR9170_MAC_REG_DMA_TXQ0_ADDR
- AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ1_ADDR
- AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ2Q3_LEN
- AR9170_MAC_REG_DMA_TXQ2_ADDR
- AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ3_ADDR
- AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ4_ADDR
- AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ4_LEN
- AR9170_MAC_REG_DMA_TXQX_ADDR_CURR
- AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR
- AR9170_MAC_REG_DMA_TXQX_LAST_ADDR
- AR9170_MAC_REG_DMA_TXQ_ADDR
- AR9170_MAC_REG_DMA_TXQ_CURR_ADDR
- AR9170_MAC_REG_DMA_TXQ_LAST_ADDR
- AR9170_MAC_REG_DMA_WLAN_STATUS
- AR9170_MAC_REG_DYNAMIC_SIFS_ACK
- AR9170_MAC_REG_EIFS_AND_SIFS
- AR9170_MAC_REG_ENCRYPTION
- AR9170_MAC_REG_EXT_BUSY
- AR9170_MAC_REG_FCS_SELECT
- AR9170_MAC_REG_FRAMETYPE_FILTER
- AR9170_MAC_REG_GROUP_HASH_TBL_H
- AR9170_MAC_REG_GROUP_HASH_TBL_L
- AR9170_MAC_REG_INT_CTRL
- AR9170_MAC_REG_MAC_ADDR_H
- AR9170_MAC_REG_MAC_ADDR_L
- AR9170_MAC_REG_MAC_POWER_STATE_CTRL
- AR9170_MAC_REG_MANDATORY_RATE
- AR9170_MAC_REG_MISC_680
- AR9170_MAC_REG_MISC_684
- AR9170_MAC_REG_MPDU_COUNT
- AR9170_MAC_REG_NAV_COUNT
- AR9170_MAC_REG_PC_REG_BASE
- AR9170_MAC_REG_POWER_STATE_CTRL
- AR9170_MAC_REG_PRETBTT
- AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA
- AR9170_MAC_REG_RETRY_MAX
- AR9170_MAC_REG_RTS_CTS_RATE
- AR9170_MAC_REG_RTS_CTS_TPC
- AR9170_MAC_REG_RX_CONTROL
- AR9170_MAC_REG_RX_CONTROL_1
- AR9170_MAC_REG_RX_CRC16
- AR9170_MAC_REG_RX_CRC32
- AR9170_MAC_REG_RX_DEL_MPDU
- AR9170_MAC_REG_RX_DROPPED_MPDU
- AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL
- AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI
- AR9170_MAC_REG_RX_MPDU
- AR9170_MAC_REG_RX_OVERRUN
- AR9170_MAC_REG_RX_PE_DELAY
- AR9170_MAC_REG_RX_PHY_CCK_ERROR
- AR9170_MAC_REG_RX_PHY_HT_ERROR
- AR9170_MAC_REG_RX_PHY_MISC_ERROR
- AR9170_MAC_REG_RX_PHY_OFDM_ERROR
- AR9170_MAC_REG_RX_PHY_TOTAL
- AR9170_MAC_REG_RX_PHY_XR_ERROR
- AR9170_MAC_REG_RX_THRESHOLD
- AR9170_MAC_REG_RX_TIMEOUT
- AR9170_MAC_REG_RX_TIMEOUT_COUNT
- AR9170_MAC_REG_RX_TOTAL
- AR9170_MAC_REG_SLOT_TIME
- AR9170_MAC_REG_SNIFFER
- AR9170_MAC_REG_TID_CFACK_CFEND_RATE
- AR9170_MAC_REG_TKIP_TSC
- AR9170_MAC_REG_TSF_H
- AR9170_MAC_REG_TSF_L
- AR9170_MAC_REG_TXOP_ACK_EXTENSION
- AR9170_MAC_REG_TXOP_ACK_INTERVAL
- AR9170_MAC_REG_TXOP_DURATION
- AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND
- AR9170_MAC_REG_TXRX_MPI
- AR9170_MAC_REG_TX_BLOCKACKS
- AR9170_MAC_REG_TX_COMPLETE
- AR9170_MAC_REG_TX_QOS_THRESHOLD
- AR9170_MAC_REG_TX_RETRY
- AR9170_MAC_REG_TX_TOTAL
- AR9170_MAC_REG_TX_UNDERRUN
- AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER
- AR9170_MAC_RX_CTRL_DEAGG
- AR9170_MAC_RX_CTRL_PASS_TO_HOST
- AR9170_MAC_RX_CTRL_SA_DA_SEARCH
- AR9170_MAC_RX_CTRL_SHORT_FILTER
- AR9170_MAC_SNIFFER_DEFAULTS
- AR9170_MAC_SNIFFER_ENABLE_PROMISC
- AR9170_MAC_TXRX_MPI_RX_MPI_MASK
- AR9170_MAC_TXRX_MPI_RX_TO_MASK
- AR9170_MAC_TXRX_MPI_TX_MPI_MASK
- AR9170_MAC_TXRX_MPI_TX_TO_MASK
- AR9170_MAC_VIRTUAL_CCA_ALL
- AR9170_MAC_VIRTUAL_CCA_Q0
- AR9170_MAC_VIRTUAL_CCA_Q1
- AR9170_MAC_VIRTUAL_CCA_Q2
- AR9170_MAC_VIRTUAL_CCA_Q3
- AR9170_MAC_VIRTUAL_CCA_Q4
- AR9170_MAX_ACKTABLE_ENTRIES
- AR9170_MAX_INT_SRC
- AR9170_MAX_VIRTUAL_MAC
- AR9170_MC_REG_BASE
- AR9170_MC_REG_FLASH_WAIT_STATE
- AR9170_NUM_LEDS
- AR9170_NUM_RX_URBS
- AR9170_NUM_RX_URBS_MUL
- AR9170_NUM_RX_URBS_POOL
- AR9170_NUM_TX_URBS
- AR9170_OPFLAG_2GHZ
- AR9170_OPFLAG_5GHZ
- AR9170_PHY_9285_ANT_DIV_ALT_GAINTB
- AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S
- AR9170_PHY_9285_ANT_DIV_ALT_LNACONF
- AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S
- AR9170_PHY_9285_ANT_DIV_CTL
- AR9170_PHY_9285_ANT_DIV_CTL_ALL
- AR9170_PHY_9285_ANT_DIV_CTL_S
- AR9170_PHY_9285_ANT_DIV_GAINTB_0
- AR9170_PHY_9285_ANT_DIV_GAINTB_1
- AR9170_PHY_9285_ANT_DIV_LNA1
- AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2
- AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2
- AR9170_PHY_9285_ANT_DIV_LNA2
- AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB
- AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S
- AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF
- AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S
- AR9170_PHY_ACTIVE_DIS
- AR9170_PHY_ACTIVE_EN
- AR9170_PHY_ADC_CTL_OFF_INBUFGAIN
- AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S
- AR9170_PHY_ADC_CTL_OFF_PWDADC
- AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP
- AR9170_PHY_ADC_CTL_OFF_PWDDAC
- AR9170_PHY_ADC_CTL_ON_INBUFGAIN
- AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S
- AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO
- AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC
- AR9170_PHY_AGC_CONTROL_CAL
- AR9170_PHY_AGC_CONTROL_ENABLE_NF
- AR9170_PHY_AGC_CONTROL_FLTR_CAL
- AR9170_PHY_AGC_CONTROL_NF
- AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF
- AR9170_PHY_AGC_CTL1_COARSE_HIGH
- AR9170_PHY_AGC_CTL1_COARSE_HIGH_S
- AR9170_PHY_AGC_CTL1_COARSE_LOW
- AR9170_PHY_AGC_CTL1_COARSE_LOW_S
- AR9170_PHY_ANALOG_SWAP_AB
- AR9170_PHY_ANALOG_SWAP_ALT_CHAIN
- AR9170_PHY_BIN_MASK2_4_MASK_4
- AR9170_PHY_BIN_MASK2_4_MASK_4_S
- AR9170_PHY_CALMODE_ADC_DC_INIT
- AR9170_PHY_CALMODE_ADC_DC_PER
- AR9170_PHY_CALMODE_ADC_GAIN
- AR9170_PHY_CALMODE_IQ
- AR9170_PHY_CCA_MIN_PWR
- AR9170_PHY_CCA_MIN_PWR_S
- AR9170_PHY_CCA_THRESH62
- AR9170_PHY_CCA_THRESH62_S
- AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME
- AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S
- AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
- AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S
- AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
- AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S
- AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT
- AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S
- AR9170_PHY_CCK_TX_CTRL_JAPAN
- AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK
- AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S
- AR9170_PHY_CH1_CCA_MIN_PWR
- AR9170_PHY_CH1_CCA_MIN_PWR_S
- AR9170_PHY_CH1_EXT_CCA_MIN_PWR
- AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S
- AR9170_PHY_CH2_CCA_MIN_PWR
- AR9170_PHY_CH2_CCA_MIN_PWR_S
- AR9170_PHY_CH2_EXT_CCA_MIN_PWR
- AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S
- AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT
- AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK
- AR9170_PHY_CHIP_ID_9160_REV_0
- AR9170_PHY_CHIP_ID_REV_0
- AR9170_PHY_CHIP_ID_REV_1
- AR9170_PHY_CL_CAL_ENABLE
- AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE
- AR9170_PHY_DESIRED_SZ_ADC
- AR9170_PHY_DESIRED_SZ_ADC_S
- AR9170_PHY_DESIRED_SZ_PGA
- AR9170_PHY_DESIRED_SZ_PGA_S
- AR9170_PHY_DESIRED_SZ_TOT_DES
- AR9170_PHY_DESIRED_SZ_TOT_DES_S
- AR9170_PHY_EXT_CCA_CYCPWR_THR1
- AR9170_PHY_EXT_CCA_CYCPWR_THR1_S
- AR9170_PHY_EXT_CCA_MIN_PWR
- AR9170_PHY_EXT_CCA_MIN_PWR_S
- AR9170_PHY_EXT_CCA_THRESH62
- AR9170_PHY_EXT_CCA_THRESH62_S
- AR9170_PHY_FIND_SIG_FIRPWR
- AR9170_PHY_FIND_SIG_FIRPWR_S
- AR9170_PHY_FIND_SIG_FIRSTEP
- AR9170_PHY_FIND_SIG_FIRSTEP_S
- AR9170_PHY_FORCE_XPA_CFG
- AR9170_PHY_FORCE_XPA_CFG_S
- AR9170_PHY_FRAME_CTL_TX_CLIP
- AR9170_PHY_FRAME_CTL_TX_CLIP_S
- AR9170_PHY_GAIN_2GHZ_BSW_ATTEN
- AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S
- AR9170_PHY_GAIN_2GHZ_BSW_MARGIN
- AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S
- AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN
- AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S
- AR9170_PHY_GAIN_2GHZ_XATTEN1_DB
- AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S
- AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN
- AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S
- AR9170_PHY_GAIN_2GHZ_XATTEN2_DB
- AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S
- AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN
- AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S
- AR9170_PHY_HALFGI_DSC_EXP
- AR9170_PHY_HALFGI_DSC_EXP_S
- AR9170_PHY_HALFGI_DSC_MAN
- AR9170_PHY_HALFGI_DSC_MAN_S
- AR9170_PHY_MODE_AR2133
- AR9170_PHY_MODE_AR5111
- AR9170_PHY_MODE_AR5112
- AR9170_PHY_MODE_ASYNCFIFO
- AR9170_PHY_MODE_CCK
- AR9170_PHY_MODE_DYNAMIC
- AR9170_PHY_MODE_DYN_CCK_DISABLE
- AR9170_PHY_MODE_OFDM
- AR9170_PHY_MODE_RF2GHZ
- AR9170_PHY_MODE_RF5GHZ
- AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE
- AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE
- AR9170_PHY_PLL_CTL_40
- AR9170_PHY_PLL_CTL_40_2133
- AR9170_PHY_PLL_CTL_40_5413
- AR9170_PHY_PLL_CTL_44
- AR9170_PHY_PLL_CTL_44_2133
- AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE
- AR9170_PHY_RADAR_0_ENA
- AR9170_PHY_RADAR_0_FFT_ENA
- AR9170_PHY_RADAR_0_FIRPWR
- AR9170_PHY_RADAR_0_FIRPWR_S
- AR9170_PHY_RADAR_0_HEIGHT
- AR9170_PHY_RADAR_0_HEIGHT_S
- AR9170_PHY_RADAR_0_INBAND
- AR9170_PHY_RADAR_0_INBAND_S
- AR9170_PHY_RADAR_0_PRSSI
- AR9170_PHY_RADAR_0_PRSSI_S
- AR9170_PHY_RADAR_0_RRSSI
- AR9170_PHY_RADAR_0_RRSSI_S
- AR9170_PHY_RADAR_1_BLOCK_CHECK
- AR9170_PHY_RADAR_1_MAXLEN
- AR9170_PHY_RADAR_1_MAXLEN_S
- AR9170_PHY_RADAR_1_MAX_RRSSI
- AR9170_PHY_RADAR_1_RELPWR_ENA
- AR9170_PHY_RADAR_1_RELPWR_THRESH
- AR9170_PHY_RADAR_1_RELPWR_THRESH_S
- AR9170_PHY_RADAR_1_RELSTEP_CHECK
- AR9170_PHY_RADAR_1_RELSTEP_THRESH
- AR9170_PHY_RADAR_1_RELSTEP_THRESH_S
- AR9170_PHY_RADAR_1_USE_FIR128
- AR9170_PHY_RADAR_EXT_ENA
- AR9170_PHY_REG
- AR9170_PHY_REG_ACTIVE
- AR9170_PHY_REG_ADC_CTL
- AR9170_PHY_REG_ADC_SERIAL_CTL
- AR9170_PHY_REG_AGC_CONTROL
- AR9170_PHY_REG_AGC_CTL1
- AR9170_PHY_REG_ANALOG_SWAP
- AR9170_PHY_REG_BASE
- AR9170_PHY_REG_BIN_MASK2_1
- AR9170_PHY_REG_BIN_MASK2_2
- AR9170_PHY_REG_BIN_MASK2_3
- AR9170_PHY_REG_BIN_MASK2_4
- AR9170_PHY_REG_BIN_MASK_1
- AR9170_PHY_REG_BIN_MASK_2
- AR9170_PHY_REG_BIN_MASK_3
- AR9170_PHY_REG_BLUETOOTH
- AR9170_PHY_REG_CALMODE
- AR9170_PHY_REG_CAL_CHAINMASK
- AR9170_PHY_REG_CAL_MEAS_0
- AR9170_PHY_REG_CAL_MEAS_1
- AR9170_PHY_REG_CAL_MEAS_2
- AR9170_PHY_REG_CAL_MEAS_3
- AR9170_PHY_REG_CCA
- AR9170_PHY_REG_CCA_THRESHOLD
- AR9170_PHY_REG_CCK_DETECT
- AR9170_PHY_REG_CCK_RXCTRL4
- AR9170_PHY_REG_CCK_TX_CTRL
- AR9170_PHY_REG_CH0_TX_PWRCTRL11
- AR9170_PHY_REG_CH1_CCA
- AR9170_PHY_REG_CH1_EXT_CCA
- AR9170_PHY_REG_CH1_TX_PWRCTRL11
- AR9170_PHY_REG_CH2_CCA
- AR9170_PHY_REG_CH2_EXT_CCA
- AR9170_PHY_REG_CHANNEL_MASK_01_30
- AR9170_PHY_REG_CHANNEL_MASK_31_60
- AR9170_PHY_REG_CHAN_INFO_GAIN
- AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF
- AR9170_PHY_REG_CHAN_INFO_MEMORY
- AR9170_PHY_REG_CHIP_ID
- AR9170_PHY_REG_CHIRP_DETECTED_XR
- AR9170_PHY_REG_CL_CAL_CTL
- AR9170_PHY_REG_CURRENT_RSSI
- AR9170_PHY_REG_DAG_CTRLCCK
- AR9170_PHY_REG_DESIRED_SZ
- AR9170_PHY_REG_EXT_CCA
- AR9170_PHY_REG_EXT_CCA0
- AR9170_PHY_REG_EXT_CCA0_THRESH62
- AR9170_PHY_REG_EXT_CCA0_THRESH62_S
- AR9170_PHY_REG_FIND_SIG
- AR9170_PHY_REG_FORCE_CLKEN_CCK
- AR9170_PHY_REG_FRAME_CTL
- AR9170_PHY_REG_GAIN_2GHZ
- AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2
- AR9170_PHY_REG_HALFGI
- AR9170_PHY_REG_HEADER_DETECT_XR
- AR9170_PHY_REG_HEAVY_CLIP_ENABLE
- AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS
- AR9170_PHY_REG_MASK2_M_00_15
- AR9170_PHY_REG_MASK2_M_16_30
- AR9170_PHY_REG_MASK2_M_31_45
- AR9170_PHY_REG_MASK2_P_15_01
- AR9170_PHY_REG_MASK2_P_30_16
- AR9170_PHY_REG_MASK2_P_45_31
- AR9170_PHY_REG_MASK2_P_61_45
- AR9170_PHY_REG_MASK_CTL
- AR9170_PHY_REG_MODE
- AR9170_PHY_REG_MULTICHAIN_GAIN_CTL
- AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR
- AR9170_PHY_REG_PILOT_MASK_01_30
- AR9170_PHY_REG_PILOT_MASK_31_60
- AR9170_PHY_REG_PLL_CTL
- AR9170_PHY_REG_POWER_TX_RATE1
- AR9170_PHY_REG_POWER_TX_RATE2
- AR9170_PHY_REG_POWER_TX_RATE3
- AR9170_PHY_REG_POWER_TX_RATE4
- AR9170_PHY_REG_POWER_TX_RATE5
- AR9170_PHY_REG_POWER_TX_RATE6
- AR9170_PHY_REG_POWER_TX_RATE7
- AR9170_PHY_REG_POWER_TX_RATE8
- AR9170_PHY_REG_POWER_TX_RATE9
- AR9170_PHY_REG_POWER_TX_RATE_MAX
- AR9170_PHY_REG_POWER_TX_SUB
- AR9170_PHY_REG_RADAR_0
- AR9170_PHY_REG_RADAR_1
- AR9170_PHY_REG_RADAR_EXT
- AR9170_PHY_REG_REFCLKDLY
- AR9170_PHY_REG_REFCLKPD
- AR9170_PHY_REG_RESTART
- AR9170_PHY_REG_RFBUS_GRANT
- AR9170_PHY_REG_RFBUS_REQ
- AR9170_PHY_REG_RF_CTL2
- AR9170_PHY_REG_RF_CTL3
- AR9170_PHY_REG_RF_CTL4
- AR9170_PHY_REG_RXGAIN
- AR9170_PHY_REG_RXGAIN_CHAIN_2
- AR9170_PHY_REG_RX_CHAINMASK
- AR9170_PHY_REG_RX_DELAY
- AR9170_PHY_REG_SCRM_SEQ_XR
- AR9170_PHY_REG_SEARCH_START_DELAY
- AR9170_PHY_REG_SETTLING
- AR9170_PHY_REG_SFCORR
- AR9170_PHY_REG_SFCORR_EXT
- AR9170_PHY_REG_SFCORR_LOW
- AR9170_PHY_REG_SIGMA_DELTA
- AR9170_PHY_REG_SLEEP_CTR_CONTROL
- AR9170_PHY_REG_SLEEP_CTR_LIMIT
- AR9170_PHY_REG_SLEEP_SCAL
- AR9170_PHY_REG_SPUR_REG
- AR9170_PHY_REG_SWITCH_CHAIN_0
- AR9170_PHY_REG_SWITCH_CHAIN_2
- AR9170_PHY_REG_SWITCH_COM
- AR9170_PHY_REG_TEST
- AR9170_PHY_REG_TEST2
- AR9170_PHY_REG_TIMING10
- AR9170_PHY_REG_TIMING11
- AR9170_PHY_REG_TIMING2
- AR9170_PHY_REG_TIMING3
- AR9170_PHY_REG_TIMING5
- AR9170_PHY_REG_TIMING7
- AR9170_PHY_REG_TIMING8
- AR9170_PHY_REG_TIMING9
- AR9170_PHY_REG_TIMING_CTRL4
- AR9170_PHY_REG_TPCRG1
- AR9170_PHY_REG_TPCRG5
- AR9170_PHY_REG_TSTDAC_CONST
- AR9170_PHY_REG_TURBO
- AR9170_PHY_REG_TX_GAIN_TBL1
- AR9170_PHY_REG_TX_PWRCTRL4
- AR9170_PHY_REG_TX_PWRCTRL6_0
- AR9170_PHY_REG_TX_PWRCTRL6_1
- AR9170_PHY_REG_TX_PWRCTRL7
- AR9170_PHY_REG_TX_PWRCTRL9
- AR9170_PHY_REG_VIT_MASK2_M_46_61
- AR9170_PHY_REG_XPA_CFG
- AR9170_PHY_RESTART_DIV_GC
- AR9170_PHY_RESTART_DIV_GC_S
- AR9170_PHY_RFBUS_GRANT_EN
- AR9170_PHY_RFBUS_REQ_EN
- AR9170_PHY_RF_CTL2_TX_END_DATA_START
- AR9170_PHY_RF_CTL2_TX_END_DATA_START_S
- AR9170_PHY_RF_CTL2_TX_END_PA_ON
- AR9170_PHY_RF_CTL2_TX_END_PA_ON_S
- AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON
- AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S
- AR9170_PHY_RF_CTL4_FRAME_XPAA_ON
- AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S
- AR9170_PHY_RF_CTL4_FRAME_XPAB_ON
- AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S
- AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF
- AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S
- AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF
- AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S
- AR9170_PHY_RIFS_INIT_DELAY
- AR9170_PHY_RXGAIN_TXRX_ATTEN
- AR9170_PHY_RXGAIN_TXRX_ATTEN_S
- AR9170_PHY_RXGAIN_TXRX_RF_MAX
- AR9170_PHY_RXGAIN_TXRX_RF_MAX_S
- AR9170_PHY_RX_DELAY_DELAY
- AR9170_PHY_SETTLING_SWITCH
- AR9170_PHY_SETTLING_SWITCH_S
- AR9170_PHY_SFCORR_EXT_M1_THRESH
- AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW
- AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S
- AR9170_PHY_SFCORR_EXT_M1_THRESH_S
- AR9170_PHY_SFCORR_EXT_M2_THRESH
- AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW
- AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S
- AR9170_PHY_SFCORR_EXT_M2_THRESH_S
- AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW
- AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S
- AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW
- AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S
- AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW
- AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S
- AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
- AR9170_PHY_SFCORR_M1_THRESH
- AR9170_PHY_SFCORR_M1_THRESH_S
- AR9170_PHY_SFCORR_M2COUNT_THR
- AR9170_PHY_SFCORR_M2COUNT_THR_S
- AR9170_PHY_SFCORR_M2_THRESH
- AR9170_PHY_SFCORR_M2_THRESH_S
- AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S
- AR9170_PHY_SIGMA_DELTA_ADC_CLIP
- AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S
- AR9170_PHY_SIGMA_DELTA_ADC_SEL
- AR9170_PHY_SIGMA_DELTA_ADC_SEL_S
- AR9170_PHY_SIGMA_DELTA_FILT1
- AR9170_PHY_SIGMA_DELTA_FILT1_S
- AR9170_PHY_SIGMA_DELTA_FILT2
- AR9170_PHY_SIGMA_DELTA_FILT2_S
- AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM
- AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
- AR9170_PHY_SPUR_REG_MASK_RATE_CNTL
- AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S
- AR9170_PHY_SPUR_REG_MASK_RATE_SELECT
- AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S
- AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH
- AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S
- AR9170_PHY_TEST_AGC_CLR
- AR9170_PHY_TEST_RFSILENT_BB
- AR9170_PHY_TIMING10_PILOT_MASK_2
- AR9170_PHY_TIMING10_PILOT_MASK_2_S
- AR9170_PHY_TIMING11_SPUR_DELTA_PHASE
- AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S
- AR9170_PHY_TIMING11_SPUR_FREQ_SD
- AR9170_PHY_TIMING11_SPUR_FREQ_SD_S
- AR9170_PHY_TIMING11_USE_SPUR_IN_AGC
- AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR
- AR9170_PHY_TIMING2_FORCE
- AR9170_PHY_TIMING2_FORCE_S
- AR9170_PHY_TIMING2_USE_FORCE
- AR9170_PHY_TIMING3_DSC_EXP
- AR9170_PHY_TIMING3_DSC_EXP_S
- AR9170_PHY_TIMING3_DSC_MAN
- AR9170_PHY_TIMING3_DSC_MAN_S
- AR9170_PHY_TIMING5_CYCPWR_THR1
- AR9170_PHY_TIMING5_CYCPWR_THR1_S
- AR9170_PHY_TIMING8_PILOT_MASK_2
- AR9170_PHY_TIMING8_PILOT_MASK_2_S
- AR9170_PHY_TIMING_CTRL4_DO_IQCAL
- AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
- AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
- AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
- AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
- AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX
- AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S
- AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE
- AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
- AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S
- AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
- AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S
- AR9170_PHY_TPCRG1_NUM_PD_GAIN
- AR9170_PHY_TPCRG1_NUM_PD_GAIN_S
- AR9170_PHY_TPCRG1_PD_CAL_ENABLE
- AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S
- AR9170_PHY_TPCRG1_PD_GAIN_1
- AR9170_PHY_TPCRG1_PD_GAIN_1_S
- AR9170_PHY_TPCRG1_PD_GAIN_2
- AR9170_PHY_TPCRG1_PD_GAIN_2_S
- AR9170_PHY_TPCRG1_PD_GAIN_3
- AR9170_PHY_TPCRG1_PD_GAIN_3_S
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4
- AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S
- AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP
- AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S
- AR9170_PHY_TURBO_FC_DYN2040_EN
- AR9170_PHY_TURBO_FC_DYN2040_EXT_CH
- AR9170_PHY_TURBO_FC_DYN2040_PRI_CH
- AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY
- AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO
- AR9170_PHY_TURBO_FC_HT_EN
- AR9170_PHY_TURBO_FC_SHORT_GI_40
- AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1
- AR9170_PHY_TURBO_FC_TURBO_MODE
- AR9170_PHY_TURBO_FC_TURBO_SHORT
- AR9170_PHY_TURBO_FC_WALSH
- AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP
- AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S
- AR9170_PHY_TX_DESIRED_SCALE_CCK
- AR9170_PHY_TX_DESIRED_SCALE_CCK_S
- AR9170_PHY_TX_GAIN
- AR9170_PHY_TX_GAIN_S
- AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
- AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S
- AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE
- AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S
- AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN
- AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S
- AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT
- AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S
- AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID
- AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S
- AR9170_PRAM_OFFSET
- AR9170_PRAM_SIZE
- AR9170_PTA_CTRL_16_BEAT_BURST
- AR9170_PTA_CTRL_4_BEAT_BURST
- AR9170_PTA_CTRL_8_BEAT_BURST
- AR9170_PTA_CTRL_LOOPBACK_MODE
- AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB
- AR9170_PTA_DMA_MODE_CTRL_RESET
- AR9170_PTA_INT_FLAG_CMD
- AR9170_PTA_INT_FLAG_DN
- AR9170_PTA_INT_FLAG_UP
- AR9170_PTA_REG_AHB_INT_ACK
- AR9170_PTA_REG_AHB_INT_FLAG
- AR9170_PTA_REG_AHB_INT_MASK
- AR9170_PTA_REG_AHB_SCRATCH1
- AR9170_PTA_REG_AHB_SCRATCH2
- AR9170_PTA_REG_AHB_SCRATCH3
- AR9170_PTA_REG_AHB_SCRATCH4
- AR9170_PTA_REG_BASE
- AR9170_PTA_REG_CMD
- AR9170_PTA_REG_CONTROL
- AR9170_PTA_REG_DMA_MODE_CTRL
- AR9170_PTA_REG_DMA_STATUS
- AR9170_PTA_REG_DN_CURR_ADDRH
- AR9170_PTA_REG_DN_CURR_ADDRL
- AR9170_PTA_REG_DN_DMA_ADDRH
- AR9170_PTA_REG_DN_DMA_ADDRL
- AR9170_PTA_REG_DN_DMA_TRIGGER
- AR9170_PTA_REG_DN_PEND_TIME
- AR9170_PTA_REG_INT_FLAG
- AR9170_PTA_REG_INT_MASK
- AR9170_PTA_REG_MEM_ADDR
- AR9170_PTA_REG_MEM_CTRL
- AR9170_PTA_REG_PARAM1
- AR9170_PTA_REG_PARAM2
- AR9170_PTA_REG_PARAM3
- AR9170_PTA_REG_RSP
- AR9170_PTA_REG_SHARE_MEM_CTRL
- AR9170_PTA_REG_STATUS1
- AR9170_PTA_REG_STATUS2
- AR9170_PTA_REG_STATUS3
- AR9170_PTA_REG_UP_CURR_ADDRH
- AR9170_PTA_REG_UP_CURR_ADDRL
- AR9170_PTA_REG_UP_DMA_ADDRH
- AR9170_PTA_REG_UP_DMA_ADDRL
- AR9170_PTA_REG_UP_DMA_TRIGGER
- AR9170_PTA_REG_UP_PEND_TIME
- AR9170_PWR_CLK_AHB_20_22MHZ
- AR9170_PWR_CLK_AHB_40MHZ
- AR9170_PWR_CLK_AHB_40_44MHZ
- AR9170_PWR_CLK_AHB_80_88MHZ
- AR9170_PWR_CLK_DAC_160_INV_DLY
- AR9170_PWR_PLL_ADDAC_DIV
- AR9170_PWR_PLL_ADDAC_DIV_S
- AR9170_PWR_REG_BASE
- AR9170_PWR_REG_CHIP_REVISION
- AR9170_PWR_REG_CLOCK_SEL
- AR9170_PWR_REG_PLL_ADDAC
- AR9170_PWR_REG_POWER_STATE
- AR9170_PWR_REG_RESET
- AR9170_PWR_REG_WATCH_DOG_MAGIC
- AR9170_PWR_RESET_ADDA_CLK_COLD_RESET
- AR9170_PWR_RESET_AHB_MASK
- AR9170_PWR_RESET_BB_COLD_RESET
- AR9170_PWR_RESET_BB_WARM_RESET
- AR9170_PWR_RESET_BRIDGE_MASK
- AR9170_PWR_RESET_COMMIT_RESET_MASK
- AR9170_PWR_RESET_DMA_MASK
- AR9170_PWR_RESET_PLL
- AR9170_PWR_RESET_USB_PLL
- AR9170_PWR_RESET_WLAN_MASK
- AR9170_RAND_MODE_FREE
- AR9170_RAND_MODE_MANUAL
- AR9170_RAND_REG_BASE
- AR9170_RAND_REG_MODE
- AR9170_RAND_REG_NUM
- AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR
- AR9170_REG_DAG_CTRLCCK_RSSI_THR
- AR9170_REG_DAG_CTRLCCK_RSSI_THR_S
- AR9170_RX_ENC_SOFTWARE
- AR9170_RX_ERROR_DECRYPT
- AR9170_RX_ERROR_FCS
- AR9170_RX_ERROR_MMIC
- AR9170_RX_ERROR_OVERRUN
- AR9170_RX_ERROR_PLCP
- AR9170_RX_ERROR_RXTO
- AR9170_RX_ERROR_WRONG_RA
- AR9170_RX_HEAD_LEN
- AR9170_RX_MACSTATUS_LEN
- AR9170_RX_PHYSTATUS_LEN
- AR9170_RX_PHY_RATE_CCK_11M
- AR9170_RX_PHY_RATE_CCK_1M
- AR9170_RX_PHY_RATE_CCK_2M
- AR9170_RX_PHY_RATE_CCK_5M
- AR9170_RX_STATUS_CONT_AGGR
- AR9170_RX_STATUS_GREENFIELD
- AR9170_RX_STATUS_MODULATION
- AR9170_RX_STATUS_MODULATION_CCK
- AR9170_RX_STATUS_MODULATION_DUPOFDM
- AR9170_RX_STATUS_MODULATION_HT
- AR9170_RX_STATUS_MODULATION_OFDM
- AR9170_RX_STATUS_MODULATION_S
- AR9170_RX_STATUS_MPDU
- AR9170_RX_STATUS_MPDU_FIRST
- AR9170_RX_STATUS_MPDU_LAST
- AR9170_RX_STATUS_MPDU_MIDDLE
- AR9170_RX_STATUS_MPDU_S
- AR9170_RX_STATUS_MPDU_SINGLE
- AR9170_RX_STATUS_SHORT_PREAMBLE
- AR9170_RX_STATUS_TOTAL_ERROR
- AR9170_RX_STREAM_MAX_SIZE
- AR9170_RX_STREAM_TAG
- AR9170_SPI_COMMAND_PORT0_CMD0
- AR9170_SPI_COMMAND_PORT0_CMD0_S
- AR9170_SPI_COMMAND_PORT0_CMD1
- AR9170_SPI_COMMAND_PORT0_CMD1_S
- AR9170_SPI_COMMAND_PORT0_CMD2
- AR9170_SPI_COMMAND_PORT0_CMD2_S
- AR9170_SPI_COMMAND_PORT0_CMD3
- AR9170_SPI_COMMAND_PORT0_CMD3_S
- AR9170_SPI_COMMAND_PORT1_CMD4
- AR9170_SPI_COMMAND_PORT1_CMD4_S
- AR9170_SPI_COMMAND_PORT1_CMD5
- AR9170_SPI_COMMAND_PORT1_CMD5_S
- AR9170_SPI_COMMAND_PORT1_CMD6
- AR9170_SPI_COMMAND_PORT1_CMD6_S
- AR9170_SPI_COMMAND_PORT1_CMD7
- AR9170_SPI_COMMAND_PORT1_CMD7_S
- AR9170_SPI_CONTROL0_BUSY
- AR9170_SPI_CONTROL0_CMD_ABORT
- AR9170_SPI_CONTROL0_CMD_GO
- AR9170_SPI_CONTROL0_CMD_LEN
- AR9170_SPI_CONTROL0_CMD_LEN_S
- AR9170_SPI_CONTROL0_PAGE_WR
- AR9170_SPI_CONTROL0_RD_LEN
- AR9170_SPI_CONTROL0_RD_LEN_S
- AR9170_SPI_CONTROL0_SEQ_RD
- AR9170_SPI_CONTROL1_DRIVE_SDO
- AR9170_SPI_CONTROL1_MODE_SEL
- AR9170_SPI_CONTROL1_MODE_SEL_S
- AR9170_SPI_CONTROL1_SCK_RATE
- AR9170_SPI_CONTROL1_WRITE_PROTECT
- AR9170_SPI_REG_BASE
- AR9170_SPI_REG_COMMAND_PORT0
- AR9170_SPI_REG_COMMAND_PORT1
- AR9170_SPI_REG_CONTROL0
- AR9170_SPI_REG_CONTROL1
- AR9170_SPI_REG_DATA_PORT
- AR9170_SPI_REG_PAGE_WRITE_LEN
- AR9170_SRAM_OFFSET
- AR9170_SRAM_SIZE
- AR9170_STREAM_LEN
- AR9170_TIMER_CTRL_DISABLE_CLOCK
- AR9170_TIMER_INT_TICK_TIMER
- AR9170_TIMER_INT_TIMER0
- AR9170_TIMER_INT_TIMER1
- AR9170_TIMER_INT_TIMER2
- AR9170_TIMER_INT_TIMER3
- AR9170_TIMER_INT_TIMER4
- AR9170_TIMER_REG_BASE
- AR9170_TIMER_REG_CLOCK_HIGH
- AR9170_TIMER_REG_CLOCK_LOW
- AR9170_TIMER_REG_CONTROL
- AR9170_TIMER_REG_INTERRUPT
- AR9170_TIMER_REG_TICK_TIMER
- AR9170_TIMER_REG_TIMER0
- AR9170_TIMER_REG_TIMER1
- AR9170_TIMER_REG_TIMER2
- AR9170_TIMER_REG_TIMER3
- AR9170_TIMER_REG_TIMER4
- AR9170_TIMER_REG_WATCH_DOG
- AR9170_TXQ0
- AR9170_TXQ1
- AR9170_TXQ2
- AR9170_TXQ3
- AR9170_TXQ_BE
- AR9170_TXQ_BK
- AR9170_TXQ_DEPTH
- AR9170_TXQ_SPECIAL
- AR9170_TXQ_VI
- AR9170_TXQ_VO
- AR9170_TXRX_PHY_RATE_HT_MCS0
- AR9170_TXRX_PHY_RATE_HT_MCS1
- AR9170_TXRX_PHY_RATE_HT_MCS10
- AR9170_TXRX_PHY_RATE_HT_MCS11
- AR9170_TXRX_PHY_RATE_HT_MCS12
- AR9170_TXRX_PHY_RATE_HT_MCS13
- AR9170_TXRX_PHY_RATE_HT_MCS14
- AR9170_TXRX_PHY_RATE_HT_MCS15
- AR9170_TXRX_PHY_RATE_HT_MCS2
- AR9170_TXRX_PHY_RATE_HT_MCS3
- AR9170_TXRX_PHY_RATE_HT_MCS4
- AR9170_TXRX_PHY_RATE_HT_MCS5
- AR9170_TXRX_PHY_RATE_HT_MCS6
- AR9170_TXRX_PHY_RATE_HT_MCS7
- AR9170_TXRX_PHY_RATE_HT_MCS8
- AR9170_TXRX_PHY_RATE_HT_MCS9
- AR9170_TXRX_PHY_RATE_OFDM_12M
- AR9170_TXRX_PHY_RATE_OFDM_18M
- AR9170_TXRX_PHY_RATE_OFDM_24M
- AR9170_TXRX_PHY_RATE_OFDM_36M
- AR9170_TXRX_PHY_RATE_OFDM_48M
- AR9170_TXRX_PHY_RATE_OFDM_54M
- AR9170_TXRX_PHY_RATE_OFDM_6M
- AR9170_TXRX_PHY_RATE_OFDM_9M
- AR9170_TX_HWDESC_LEN
- AR9170_TX_MAC_AGGR
- AR9170_TX_MAC_BACKOFF
- AR9170_TX_MAC_BURST
- AR9170_TX_MAC_DISABLE_TXOP
- AR9170_TX_MAC_ENCR_AES
- AR9170_TX_MAC_ENCR_CENC
- AR9170_TX_MAC_ENCR_NONE
- AR9170_TX_MAC_ENCR_RC4
- AR9170_TX_MAC_HW_DURATION
- AR9170_TX_MAC_IMM_BA
- AR9170_TX_MAC_MMIC
- AR9170_TX_MAC_NO_ACK
- AR9170_TX_MAC_PROT
- AR9170_TX_MAC_PROT_CTS
- AR9170_TX_MAC_PROT_RTS
- AR9170_TX_MAC_QOS
- AR9170_TX_MAC_QOS_S
- AR9170_TX_MAC_TXOP_RIFS
- AR9170_TX_PHY_BW
- AR9170_TX_PHY_BW_20MHZ
- AR9170_TX_PHY_BW_40MHZ
- AR9170_TX_PHY_BW_40MHZ_DUP
- AR9170_TX_PHY_BW_S
- AR9170_TX_PHY_GREENFIELD
- AR9170_TX_PHY_MCS
- AR9170_TX_PHY_MCS_S
- AR9170_TX_PHY_MOD_CCK
- AR9170_TX_PHY_MOD_HT
- AR9170_TX_PHY_MOD_OFDM
- AR9170_TX_PHY_RATE_CCK_11M
- AR9170_TX_PHY_RATE_CCK_1M
- AR9170_TX_PHY_RATE_CCK_2M
- AR9170_TX_PHY_RATE_CCK_5M
- AR9170_TX_PHY_SHORT_GI
- AR9170_TX_PHY_SHORT_PREAMBLE
- AR9170_TX_PHY_TXCHAIN
- AR9170_TX_PHY_TXCHAIN_1
- AR9170_TX_PHY_TXCHAIN_2
- AR9170_TX_PHY_TXCHAIN_S
- AR9170_TX_PHY_TX_HEAVY_CLIP
- AR9170_TX_PHY_TX_HEAVY_CLIP_S
- AR9170_TX_PHY_TX_PWR
- AR9170_TX_PHY_TX_PWR_S
- AR9170_TX_STREAM_TAG
- AR9170_UART_FIFO_CTRL_RESET_RX_FIFO
- AR9170_UART_FIFO_CTRL_RESET_TX_FIFO
- AR9170_UART_LINE_STS_RX_BREAK_IND
- AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN
- AR9170_UART_LINE_STS_RX_DATA_READY
- AR9170_UART_LINE_STS_TRANSMITTER_EMPTY
- AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY
- AR9170_UART_MODEM_CTRL_AUTO_CTR
- AR9170_UART_MODEM_CTRL_AUTO_RTS
- AR9170_UART_MODEM_CTRL_DTR_BIT
- AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK
- AR9170_UART_MODEM_CTRL_RTS_BIT
- AR9170_UART_MODEM_STS_CTS_CHANGE
- AR9170_UART_MODEM_STS_CTS_COMPL
- AR9170_UART_MODEM_STS_DCD_CHANGE
- AR9170_UART_MODEM_STS_DCD_COMPL
- AR9170_UART_MODEM_STS_DSR_CHANGE
- AR9170_UART_MODEM_STS_DSR_COMPL
- AR9170_UART_REG_BASE
- AR9170_UART_REG_DIVISOR_LSB
- AR9170_UART_REG_DIVISOR_MSB
- AR9170_UART_REG_FIFO_CONTROL
- AR9170_UART_REG_FIFO_COUNT
- AR9170_UART_REG_LINE_CONTROL
- AR9170_UART_REG_LINE_STATUS
- AR9170_UART_REG_MODEM_CONTROL
- AR9170_UART_REG_MODEM_STATUS
- AR9170_UART_REG_REMAINDER
- AR9170_UART_REG_RX_BUFFER
- AR9170_UART_REG_SCRATCH
- AR9170_UART_REG_TX_HOLDING
- AR9170_UART_REG_WORD_RX_BUFFER
- AR9170_UART_REG_WORD_TX_HOLDING
- AR9170_USB_CBUS_CTRL_BUFFER_END
- AR9170_USB_DEVICE_ADDRESS_CONFIGURE
- AR9170_USB_DMA_CTL_DOWN_STREAM
- AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE
- AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE
- AR9170_USB_DMA_CTL_HIGH_SPEED
- AR9170_USB_DMA_CTL_UP_PACKET_MODE
- AR9170_USB_DMA_CTL_UP_STREAM
- AR9170_USB_DMA_CTL_UP_STREAM_16K
- AR9170_USB_DMA_CTL_UP_STREAM_32K
- AR9170_USB_DMA_CTL_UP_STREAM_4K
- AR9170_USB_DMA_CTL_UP_STREAM_8K
- AR9170_USB_DMA_CTL_UP_STREAM_S
- AR9170_USB_DMA_STATUS_DN_IDLE
- AR9170_USB_DMA_STATUS_UP_IDLE
- AR9170_USB_EP_CMD
- AR9170_USB_EP_CMD_MAX
- AR9170_USB_EP_CTRL
- AR9170_USB_EP_CTRL_MAX
- AR9170_USB_EP_IN_STALL
- AR9170_USB_EP_IN_TOGGLE
- AR9170_USB_EP_IRQ
- AR9170_USB_EP_IRQ_MAX
- AR9170_USB_EP_OUT_STALL
- AR9170_USB_EP_OUT_TOGGLE
- AR9170_USB_EP_RX
- AR9170_USB_EP_RX_MAX
- AR9170_USB_EP_TX
- AR9170_USB_EP_TX_MAX
- AR9170_USB_INTR_DISABLE_IN_INT
- AR9170_USB_INTR_DISABLE_OUT_INT
- AR9170_USB_INTR_SRC0_ABORT
- AR9170_USB_INTR_SRC0_END
- AR9170_USB_INTR_SRC0_FAIL
- AR9170_USB_INTR_SRC0_IN
- AR9170_USB_INTR_SRC0_OUT
- AR9170_USB_INTR_SRC0_SETUP
- AR9170_USB_INTR_SRC7_ISO_SEQ_ABORT
- AR9170_USB_INTR_SRC7_ISO_SEQ_ERR
- AR9170_USB_INTR_SRC7_RX0BYTE
- AR9170_USB_INTR_SRC7_TX0BYTE
- AR9170_USB_INTR_SRC7_USB_RESET
- AR9170_USB_INTR_SRC7_USB_RESUME
- AR9170_USB_INTR_SRC7_USB_SUSPEND
- AR9170_USB_MAIN_CTRL_CHIP_ENABLE
- AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT
- AR9170_USB_MAIN_CTRL_GO_TO_SUSPEND
- AR9170_USB_MAIN_CTRL_HIGHSPEED
- AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP
- AR9170_USB_MAIN_CTRL_RESET
- AR9170_USB_NUM_EXTRA_EP
- AR9170_USB_REG_BASE
- AR9170_USB_REG_CBUS_CTRL
- AR9170_USB_REG_CX_CONFIG_STATUS
- AR9170_USB_REG_DEVICE_ADDRESS
- AR9170_USB_REG_DMA_CTL
- AR9170_USB_REG_DMA_STATUS
- AR9170_USB_REG_EP0_DATA
- AR9170_USB_REG_EP0_DATA1
- AR9170_USB_REG_EP0_DATA2
- AR9170_USB_REG_EP10_MAP
- AR9170_USB_REG_EP1_MAP
- AR9170_USB_REG_EP2_MAP
- AR9170_USB_REG_EP3_BYTE_COUNT_HIGH
- AR9170_USB_REG_EP3_BYTE_COUNT_LOW
- AR9170_USB_REG_EP3_DATA
- AR9170_USB_REG_EP3_MAP
- AR9170_USB_REG_EP4_BYTE_COUNT_HIGH
- AR9170_USB_REG_EP4_BYTE_COUNT_LOW
- AR9170_USB_REG_EP4_DATA
- AR9170_USB_REG_EP4_MAP
- AR9170_USB_REG_EP5_MAP
- AR9170_USB_REG_EP6_MAP
- AR9170_USB_REG_EP7_MAP
- AR9170_USB_REG_EP8_MAP
- AR9170_USB_REG_EP9_MAP
- AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH
- AR9170_USB_REG_EP_IN_MAX_SIZE_LOW
- AR9170_USB_REG_EP_MAP
- AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH
- AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW
- AR9170_USB_REG_FIFO0_CONFIG
- AR9170_USB_REG_FIFO0_MAP
- AR9170_USB_REG_FIFO1_CONFIG
- AR9170_USB_REG_FIFO1_MAP
- AR9170_USB_REG_FIFO2_CONFIG
- AR9170_USB_REG_FIFO2_MAP
- AR9170_USB_REG_FIFO3_CONFIG
- AR9170_USB_REG_FIFO3_MAP
- AR9170_USB_REG_FIFO4_CONFIG
- AR9170_USB_REG_FIFO4_MAP
- AR9170_USB_REG_FIFO5_CONFIG
- AR9170_USB_REG_FIFO5_MAP
- AR9170_USB_REG_FIFO6_CONFIG
- AR9170_USB_REG_FIFO6_MAP
- AR9170_USB_REG_FIFO7_CONFIG
- AR9170_USB_REG_FIFO7_MAP
- AR9170_USB_REG_FIFO8_CONFIG
- AR9170_USB_REG_FIFO8_MAP
- AR9170_USB_REG_FIFO9_CONFIG
- AR9170_USB_REG_FIFO9_MAP
- AR9170_USB_REG_FIFO_CONFIG
- AR9170_USB_REG_FIFO_MAP
- AR9170_USB_REG_FIFO_SIZE
- AR9170_USB_REG_IDLE_COUNT
- AR9170_USB_REG_INTR_GROUP
- AR9170_USB_REG_INTR_MASK_BYTE_0
- AR9170_USB_REG_INTR_MASK_BYTE_1
- AR9170_USB_REG_INTR_MASK_BYTE_2
- AR9170_USB_REG_INTR_MASK_BYTE_3
- AR9170_USB_REG_INTR_MASK_BYTE_4
- AR9170_USB_REG_INTR_MASK_BYTE_5
- AR9170_USB_REG_INTR_MASK_BYTE_6
- AR9170_USB_REG_INTR_MASK_BYTE_7
- AR9170_USB_REG_INTR_SOURCE_0
- AR9170_USB_REG_INTR_SOURCE_1
- AR9170_USB_REG_INTR_SOURCE_2
- AR9170_USB_REG_INTR_SOURCE_3
- AR9170_USB_REG_INTR_SOURCE_4
- AR9170_USB_REG_INTR_SOURCE_5
- AR9170_USB_REG_INTR_SOURCE_6
- AR9170_USB_REG_INTR_SOURCE_7
- AR9170_USB_REG_MAIN_CTRL
- AR9170_USB_REG_MAX_AGG_UPLOAD
- AR9170_USB_REG_PHY_TEST_SELECT
- AR9170_USB_REG_TEST
- AR9170_USB_REG_UPLOAD_TIME_CTL
- AR9170_USB_REG_WAKE_UP
- AR9170_USB_WAKE_UP_WAKE
- AR9271_AN_RF2G3_CCOMP
- AR9271_AN_RF2G3_CCOMP_S
- AR9271_AN_RF2G3_DB_1
- AR9271_AN_RF2G3_DB_1_S
- AR9271_AN_RF2G3_OB_cck
- AR9271_AN_RF2G3_OB_cck_S
- AR9271_AN_RF2G3_OB_psk
- AR9271_AN_RF2G3_OB_psk_S
- AR9271_AN_RF2G3_OB_qam
- AR9271_AN_RF2G3_OB_qam_S
- AR9271_AN_RF2G4_DB_2
- AR9271_AN_RF2G4_DB_2_S
- AR9271_AN_RF2G6_OFFS
- AR9271_AN_RF2G6_OFFS_S
- AR9271_CORE_CLOCK
- AR9271_FIRMWARE
- AR9271_FIRMWARE_TEXT
- AR9271_GATE_MAC_CTL
- AR9271_GPIO_IN_VAL
- AR9271_GPIO_IN_VAL_S
- AR9271_GPIO_MASK
- AR9271_NUM_GPIO
- AR9271_RADIO_RF_RST
- AR9271_RESET_POWER_DOWN_CONTROL
- AR9271_TARGET_BAUD_RATE
- AR9280_COEX2WIRE_SUBSYSID
- AR9280_DEVID_PCI
- AR9280_DEVID_PCIE
- AR9280_GPIO_MASK
- AR9280_NUM_GPIO
- AR9280_PHY_CCA_THRESH62
- AR9280_PHY_CCA_THRESH62_S
- AR9280_PHY_CH1_EXT_MINCCA_PWR
- AR9280_PHY_CH1_EXT_MINCCA_PWR_S
- AR9280_PHY_CH1_MINCCA_PWR
- AR9280_PHY_CH1_MINCCA_PWR_S
- AR9280_PHY_CURRENT_RSSI
- AR9280_PHY_EXT_MINCCA_PWR
- AR9280_PHY_EXT_MINCCA_PWR_S
- AR9280_PHY_MINCCA_PWR
- AR9280_PHY_MINCCA_PWR_S
- AR9280_PHY_RXGAIN_TXRX_ATTEN
- AR9280_PHY_RXGAIN_TXRX_ATTEN_S
- AR9280_PHY_RXGAIN_TXRX_MARGIN
- AR9280_PHY_RXGAIN_TXRX_MARGIN_S
- AR9280_TX_GAIN_TABLE_SIZE
- AR9280_USB
- AR9280_WA_DEFAULT
- AR9285_AN_RF2G1
- AR9285_AN_RF2G1_ENPACAL
- AR9285_AN_RF2G1_ENPACAL_S
- AR9285_AN_RF2G1_PDPADRV1
- AR9285_AN_RF2G1_PDPADRV1_S
- AR9285_AN_RF2G1_PDPADRV2
- AR9285_AN_RF2G1_PDPADRV2_S
- AR9285_AN_RF2G1_PDPAOUT
- AR9285_AN_RF2G1_PDPAOUT_S
- AR9285_AN_RF2G2
- AR9285_AN_RF2G2_OFFCAL
- AR9285_AN_RF2G2_OFFCAL_S
- AR9285_AN_RF2G3
- AR9285_AN_RF2G3_DB1_0
- AR9285_AN_RF2G3_DB1_0_S
- AR9285_AN_RF2G3_DB1_1
- AR9285_AN_RF2G3_DB1_1_S
- AR9285_AN_RF2G3_DB1_2
- AR9285_AN_RF2G3_DB1_2_S
- AR9285_AN_RF2G3_OB_0
- AR9285_AN_RF2G3_OB_0_S
- AR9285_AN_RF2G3_OB_1
- AR9285_AN_RF2G3_OB_1_S
- AR9285_AN_RF2G3_OB_2
- AR9285_AN_RF2G3_OB_2_S
- AR9285_AN_RF2G3_OB_3
- AR9285_AN_RF2G3_OB_3_S
- AR9285_AN_RF2G3_OB_4
- AR9285_AN_RF2G3_OB_4_S
- AR9285_AN_RF2G3_PDVCCOMP
- AR9285_AN_RF2G3_PDVCCOMP_S
- AR9285_AN_RF2G4
- AR9285_AN_RF2G4_DB1_3
- AR9285_AN_RF2G4_DB1_3_S
- AR9285_AN_RF2G4_DB1_4
- AR9285_AN_RF2G4_DB1_4_S
- AR9285_AN_RF2G4_DB2_0
- AR9285_AN_RF2G4_DB2_0_S
- AR9285_AN_RF2G4_DB2_1
- AR9285_AN_RF2G4_DB2_1_S
- AR9285_AN_RF2G4_DB2_2
- AR9285_AN_RF2G4_DB2_2_S
- AR9285_AN_RF2G4_DB2_3
- AR9285_AN_RF2G4_DB2_3_S
- AR9285_AN_RF2G4_DB2_4
- AR9285_AN_RF2G4_DB2_4_S
- AR9285_AN_RF2G6
- AR9285_AN_RF2G6_CCOMP
- AR9285_AN_RF2G6_CCOMP_S
- AR9285_AN_RF2G6_OFFS
- AR9285_AN_RF2G6_OFFS_S
- AR9285_AN_RF2G7
- AR9285_AN_RF2G7_PADRVGN2TAB0
- AR9285_AN_RF2G7_PADRVGN2TAB0_S
- AR9285_AN_RF2G7_PWDDB
- AR9285_AN_RF2G7_PWDDB_S
- AR9285_AN_RF2G8
- AR9285_AN_RF2G8_PADRVGN2TAB0
- AR9285_AN_RF2G8_PADRVGN2TAB0_S
- AR9285_AN_RF2G9
- AR9285_AN_RXTXBB1
- AR9285_AN_RXTXBB1_PDDACIF
- AR9285_AN_RXTXBB1_PDDACIF_S
- AR9285_AN_RXTXBB1_PDRXTXBB1
- AR9285_AN_RXTXBB1_PDRXTXBB1_S
- AR9285_AN_RXTXBB1_PDV2I
- AR9285_AN_RXTXBB1_PDV2I_S
- AR9285_AN_RXTXBB1_SPARE9
- AR9285_AN_RXTXBB1_SPARE9_S
- AR9285_AN_TOP2
- AR9285_AN_TOP3
- AR9285_AN_TOP3_PWDDAC
- AR9285_AN_TOP3_PWDDAC_S
- AR9285_AN_TOP3_XPABIAS_LVL
- AR9285_AN_TOP3_XPABIAS_LVL_S
- AR9285_AN_TOP4
- AR9285_AN_TOP4_DEFAULT
- AR9285_CLCAL_REDO_THRESH
- AR9285_DEVID_PCIE
- AR9285_GPIO_IN_VAL
- AR9285_GPIO_IN_VAL_S
- AR9285_GPIO_MASK
- AR9285_NUM_GPIO
- AR9285_RDEXT_DEFAULT
- AR9285_RF2G5
- AR9285_RF2G5_IC50TX
- AR9285_RF2G5_IC50TX_CLEAR
- AR9285_RF2G5_IC50TX_CLEAR_S
- AR9285_RF2G5_IC50TX_SET
- AR9285_RF2G5_IC50TX_XE_SET
- AR9285_WA_DEFAULT
- AR9287_ANT_16S
- AR9287_AN_RF2G3_CH0
- AR9287_AN_RF2G3_CH1
- AR9287_AN_RF2G3_DB1
- AR9287_AN_RF2G3_DB1_S
- AR9287_AN_RF2G3_DB2
- AR9287_AN_RF2G3_DB2_S
- AR9287_AN_RF2G3_OB_CCK
- AR9287_AN_RF2G3_OB_CCK_S
- AR9287_AN_RF2G3_OB_PAL_OFF
- AR9287_AN_RF2G3_OB_PAL_OFF_S
- AR9287_AN_RF2G3_OB_PSK
- AR9287_AN_RF2G3_OB_PSK_S
- AR9287_AN_RF2G3_OB_QAM
- AR9287_AN_RF2G3_OB_QAM_S
- AR9287_AN_TOP2
- AR9287_AN_TOP2_XPABIAS_LVL
- AR9287_AN_TOP2_XPABIAS_LVL_S
- AR9287_AN_TXPC0
- AR9287_AN_TXPC0_TXPCMODE
- AR9287_AN_TXPC0_TXPCMODE_ATBTEST
- AR9287_AN_TXPC0_TXPCMODE_NORMAL
- AR9287_AN_TXPC0_TXPCMODE_S
- AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
- AR9287_AN_TXPC0_TXPCMODE_TEST
- AR9287_CHECKSUM_LOCATION
- AR9287_DATA_SZ
- AR9287_DEVID_PCI
- AR9287_DEVID_PCIE
- AR9287_EEPMISC_WOW
- AR9287_EEP_MINOR_VER
- AR9287_EEP_MINOR_VER_1
- AR9287_EEP_MINOR_VER_2
- AR9287_EEP_MINOR_VER_3
- AR9287_EEP_MINOR_VER_b
- AR9287_EEP_NO_BACK_VER
- AR9287_EEP_START_LOC
- AR9287_EEP_VER
- AR9287_GPIO_IN_VAL
- AR9287_GPIO_IN_VAL_S
- AR9287_GPIO_MASK
- AR9287_HTC_EEP_START_LOC
- AR9287_MAX_CHAINS
- AR9287_NUM_2G_20_TARGET_POWERS
- AR9287_NUM_2G_40_TARGET_POWERS
- AR9287_NUM_2G_CAL_PIERS
- AR9287_NUM_2G_CCK_TARGET_POWERS
- AR9287_NUM_BAND_EDGES
- AR9287_NUM_CTLS
- AR9287_NUM_GPIO
- AR9287_PD_GAIN_ICEPTS
- AR9287_PWR_TABLE_OFFSET_DB
- AR9287_USB
- AR928X_GPIO_IN_VAL
- AR928X_GPIO_IN_VAL_S
- AR9300_11NA_HT_DS_SHIFT
- AR9300_11NA_HT_SS_SHIFT
- AR9300_11NA_HT_TS_SHIFT
- AR9300_11NA_OFDM_SHIFT
- AR9300_11NG_HT_DS_SHIFT
- AR9300_11NG_HT_SS_SHIFT
- AR9300_11NG_HT_TS_SHIFT
- AR9300_11NG_OFDM_SHIFT
- AR9300_ANT_16S
- AR9300_BASE_ADDR
- AR9300_BASE_ADDR_4K
- AR9300_BASE_ADDR_512
- AR9300_BT_WGHT
- AR9300_CUSTOMER_DATA_SIZE
- AR9300_DEVID_AR9330
- AR9300_DEVID_AR9340
- AR9300_DEVID_AR9462
- AR9300_DEVID_AR9485_PCIE
- AR9300_DEVID_AR953X
- AR9300_DEVID_AR9565
- AR9300_DEVID_AR9580
- AR9300_DEVID_PCIE
- AR9300_DEVID_QCA955X
- AR9300_DEVID_QCA956X
- AR9300_DFS_FIRPWR
- AR9300_EEPMISC_LITTLE_ENDIAN
- AR9300_EEPMISC_WOW
- AR9300_EEPROM_SIZE
- AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE
- AR9300_EEP_MINOR_VER
- AR9300_EEP_MINOR_VER_1
- AR9300_EEP_START_LOC
- AR9300_EEP_VER
- AR9300_EEP_VER_MINOR_MASK
- AR9300_EXT_LNA_CTL_GPIO_AR9485
- AR9300_FUTURE_MODAL_SZ
- AR9300_GPIO_IN_VAL
- AR9300_GPIO_IN_VAL_S
- AR9300_GPIO_MASK
- AR9300_HT_DS_RATES
- AR9300_HT_SS_RATES
- AR9300_HT_TS_RATES
- AR9300_MAX_CHAINS
- AR9300_NUM_2G_20_TARGET_POWERS
- AR9300_NUM_2G_40_TARGET_POWERS
- AR9300_NUM_2G_CAL_PIERS
- AR9300_NUM_2G_CCK_TARGET_POWERS
- AR9300_NUM_5G_20_TARGET_POWERS
- AR9300_NUM_5G_40_TARGET_POWERS
- AR9300_NUM_5G_CAL_PIERS
- AR9300_NUM_BAND_EDGES_2G
- AR9300_NUM_BAND_EDGES_5G
- AR9300_NUM_BT_WEIGHTS
- AR9300_NUM_CTLS_2G
- AR9300_NUM_CTLS_5G
- AR9300_NUM_GPIO
- AR9300_NUM_WLAN_WEIGHTS
- AR9300_OFDM_RATES
- AR9300_OTP_BASE
- AR9300_OTP_READ_DATA
- AR9300_OTP_STATUS
- AR9300_OTP_STATUS_ACCESS_BUSY
- AR9300_OTP_STATUS_SM_BUSY
- AR9300_OTP_STATUS_TYPE
- AR9300_OTP_STATUS_VALID
- AR9300_PAPRD_RATE_MASK
- AR9300_PAPRD_SCALE_1
- AR9300_PAPRD_SCALE_1_S
- AR9300_PAPRD_SCALE_2
- AR9300_PAPRD_SCALE_2_S
- AR9300_PWR_TABLE_OFFSET
- AR9300_SM_BASE
- AR9330
- AR9330_GPIO_MASK
- AR9330_NUM_GPIO
- AR933X_BOOTSTRAP_EEPBUSY
- AR933X_BOOTSTRAP_MDIO_GPIO_EN
- AR933X_BOOTSTRAP_REF_CLK_40
- AR933X_DDR_REG_FLUSH_GE0
- AR933X_DDR_REG_FLUSH_GE1
- AR933X_DDR_REG_FLUSH_USB
- AR933X_DDR_REG_FLUSH_WMAC
- AR933X_DUMMY_STATUS_RD
- AR933X_EHCI_BASE
- AR933X_EHCI_SIZE
- AR933X_ETH_CFG_GMII_GE0
- AR933X_ETH_CFG_MII_CNTL_SPEED
- AR933X_ETH_CFG_MII_GE0
- AR933X_ETH_CFG_MII_GE0_ERR_EN
- AR933X_ETH_CFG_MII_GE0_MASTER
- AR933X_ETH_CFG_MII_GE0_SLAVE
- AR933X_ETH_CFG_RGMII_GE0
- AR933X_ETH_CFG_RMII_GE0
- AR933X_ETH_CFG_RMII_GE0_SPD_10
- AR933X_ETH_CFG_RMII_GE0_SPD_100
- AR933X_ETH_CFG_SW_ACC_MSB_FIRST
- AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
- AR933X_ETH_CFG_SW_PHY_SWAP
- AR933X_GMAC_BASE
- AR933X_GMAC_REG_ETH_CFG
- AR933X_GMAC_SIZE
- AR933X_GPIO_COUNT
- AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN
- AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN
- AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN
- AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN
- AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN
- AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT
- AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL
- AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL
- AR933X_GPIO_FUNC_I2SO_22_18_EN
- AR933X_GPIO_FUNC_I2SO_EN
- AR933X_GPIO_FUNC_I2S_MCK_EN
- AR933X_GPIO_FUNC_JTAG_DISABLE
- AR933X_GPIO_FUNC_SPDIF2TCK
- AR933X_GPIO_FUNC_SPDIF_EN
- AR933X_GPIO_FUNC_SPI_CS_EN1
- AR933X_GPIO_FUNC_SPI_CS_EN2
- AR933X_GPIO_FUNC_SPI_EN
- AR933X_GPIO_FUNC_UART_EN
- AR933X_GPIO_FUNC_UART_RTS_CTS_EN
- AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK
- AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT
- AR933X_PLL_CLOCK_CTRL_BYPASS
- AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK
- AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT
- AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK
- AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT
- AR933X_PLL_CLOCK_CTRL_REG
- AR933X_PLL_CPU_CONFIG_NINT_MASK
- AR933X_PLL_CPU_CONFIG_NINT_SHIFT
- AR933X_PLL_CPU_CONFIG_OUTDIV_MASK
- AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT
- AR933X_PLL_CPU_CONFIG_REFDIV_MASK
- AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT
- AR933X_PLL_CPU_CONFIG_REG
- AR933X_RESET_GE0_MAC
- AR933X_RESET_GE0_MDIO
- AR933X_RESET_GE1_MAC
- AR933X_RESET_GE1_MDIO
- AR933X_RESET_REG_BOOTSTRAP
- AR933X_RESET_REG_RESET_MODULE
- AR933X_RESET_USBSUS_OVERRIDE
- AR933X_RESET_USB_HOST
- AR933X_RESET_USB_PHY
- AR933X_RESET_WMAC
- AR933X_REV_ID_REVISION_MASK
- AR933X_UART_BASE
- AR933X_UART_CLOCK_REG
- AR933X_UART_CLOCK_SCALE_M
- AR933X_UART_CLOCK_SCALE_S
- AR933X_UART_CLOCK_STEP_M
- AR933X_UART_CS_DMA_EN
- AR933X_UART_CS_FLOW_CTRL_M
- AR933X_UART_CS_FLOW_CTRL_S
- AR933X_UART_CS_HOST_INT
- AR933X_UART_CS_HOST_INT_EN
- AR933X_UART_CS_IF_MODE_DCE
- AR933X_UART_CS_IF_MODE_DTE
- AR933X_UART_CS_IF_MODE_M
- AR933X_UART_CS_IF_MODE_NONE
- AR933X_UART_CS_IF_MODE_S
- AR933X_UART_CS_PARITY_EVEN
- AR933X_UART_CS_PARITY_M
- AR933X_UART_CS_PARITY_NONE
- AR933X_UART_CS_PARITY_ODD
- AR933X_UART_CS_PARITY_S
- AR933X_UART_CS_REG
- AR933X_UART_CS_RX_BREAK
- AR933X_UART_CS_RX_BUSY
- AR933X_UART_CS_RX_READY_ORIDE
- AR933X_UART_CS_TX_BREAK
- AR933X_UART_CS_TX_BUSY
- AR933X_UART_CS_TX_READY
- AR933X_UART_CS_TX_READY_ORIDE
- AR933X_UART_DATA_REG
- AR933X_UART_DATA_RX_CSR
- AR933X_UART_DATA_TX_CSR
- AR933X_UART_DATA_TX_RX_MASK
- AR933X_UART_FIFO_SIZE
- AR933X_UART_INT_ALLINTS
- AR933X_UART_INT_EN_REG
- AR933X_UART_INT_REG
- AR933X_UART_INT_RX_BREAK_OFF
- AR933X_UART_INT_RX_BREAK_ON
- AR933X_UART_INT_RX_FRAMING_ERR
- AR933X_UART_INT_RX_FULL
- AR933X_UART_INT_RX_OFLOW_ERR
- AR933X_UART_INT_RX_PARITY_ERR
- AR933X_UART_INT_RX_VALID
- AR933X_UART_INT_TX_EMPTY
- AR933X_UART_INT_TX_OFLOW_ERR
- AR933X_UART_INT_TX_READY
- AR933X_UART_MAX_BAUD
- AR933X_UART_MAX_SCALE
- AR933X_UART_MAX_STEP
- AR933X_UART_MIN_BAUD
- AR933X_UART_REGS_SIZE
- AR933X_UART_SIZE
- AR933X_WMAC_BASE
- AR933X_WMAC_SIZE
- AR9340
- AR9340_GPIO_MASK
- AR9340_INTR_SYNC_LOCAL_TIMEOUT
- AR9340_NUM_GPIO
- AR934X_BOOTSTRAP_BOOT_FROM_SPI
- AR934X_BOOTSTRAP_DDR1
- AR934X_BOOTSTRAP_EJTAG_MODE
- AR934X_BOOTSTRAP_PCIE_RC
- AR934X_BOOTSTRAP_REF_CLK_40
- AR934X_BOOTSTRAP_SDRAM_DISABLED
- AR934X_BOOTSTRAP_SW_OPTION1
- AR934X_BOOTSTRAP_SW_OPTION2
- AR934X_BOOTSTRAP_SW_OPTION3
- AR934X_BOOTSTRAP_SW_OPTION4
- AR934X_BOOTSTRAP_SW_OPTION5
- AR934X_BOOTSTRAP_SW_OPTION6
- AR934X_BOOTSTRAP_SW_OPTION7
- AR934X_BOOTSTRAP_SW_OPTION8
- AR934X_BOOTSTRAP_USB_MODE_DEVICE
- AR934X_DDR_REG_FLUSH_GE0
- AR934X_DDR_REG_FLUSH_GE1
- AR934X_DDR_REG_FLUSH_PCIE
- AR934X_DDR_REG_FLUSH_USB
- AR934X_DDR_REG_FLUSH_WMAC
- AR934X_EHCI_BASE
- AR934X_EHCI_SIZE
- AR934X_ETH_CFG_GMII_GMAC0
- AR934X_ETH_CFG_MII_GMAC0
- AR934X_ETH_CFG_MII_GMAC0_ERR_EN
- AR934X_ETH_CFG_MII_GMAC0_MASTER
- AR934X_ETH_CFG_MII_GMAC0_SLAVE
- AR934X_ETH_CFG_RDV_DELAY
- AR934X_ETH_CFG_RDV_DELAY_MASK
- AR934X_ETH_CFG_RDV_DELAY_SHIFT
- AR934X_ETH_CFG_RGMII_GMAC0
- AR934X_ETH_CFG_RMII_GMAC0
- AR934X_ETH_CFG_RMII_GMAC0_MASTER
- AR934X_ETH_CFG_RXD_DELAY
- AR934X_ETH_CFG_RXD_DELAY_MASK
- AR934X_ETH_CFG_RXD_DELAY_SHIFT
- AR934X_ETH_CFG_SW_APB_ACCESS
- AR934X_ETH_CFG_SW_ONLY_MODE
- AR934X_ETH_CFG_SW_PHY_SWAP
- AR934X_GMAC_BASE
- AR934X_GMAC_REG_ETH_CFG
- AR934X_GMAC_SIZE
- AR934X_GPIO_COUNT
- AR934X_GPIO_FUNC_CLK_OBS0_EN
- AR934X_GPIO_FUNC_CLK_OBS1_EN
- AR934X_GPIO_FUNC_CLK_OBS2_EN
- AR934X_GPIO_FUNC_CLK_OBS3_EN
- AR934X_GPIO_FUNC_CLK_OBS4_EN
- AR934X_GPIO_FUNC_CLK_OBS5_EN
- AR934X_GPIO_FUNC_CLK_OBS6_EN
- AR934X_GPIO_FUNC_CLK_OBS7_EN
- AR934X_GPIO_FUNC_JTAG_DISABLE
- AR934X_GPIO_OUT_EXT_LNA0
- AR934X_GPIO_OUT_EXT_LNA1
- AR934X_GPIO_OUT_GPIO
- AR934X_GPIO_OUT_LED_LINK0
- AR934X_GPIO_OUT_LED_LINK1
- AR934X_GPIO_OUT_LED_LINK2
- AR934X_GPIO_OUT_LED_LINK3
- AR934X_GPIO_OUT_LED_LINK4
- AR934X_GPIO_OUT_SPI_CS1
- AR934X_GPIO_REG_FUNC
- AR934X_GPIO_REG_OUT_FUNC0
- AR934X_GPIO_REG_OUT_FUNC1
- AR934X_GPIO_REG_OUT_FUNC2
- AR934X_GPIO_REG_OUT_FUNC3
- AR934X_GPIO_REG_OUT_FUNC4
- AR934X_GPIO_REG_OUT_FUNC5
- AR934X_NFC_BASE
- AR934X_NFC_SIZE
- AR934X_PCIE_WMAC_INT_PCIE_ALL
- AR934X_PCIE_WMAC_INT_PCIE_RC
- AR934X_PCIE_WMAC_INT_PCIE_RC0
- AR934X_PCIE_WMAC_INT_PCIE_RC1
- AR934X_PCIE_WMAC_INT_PCIE_RC2
- AR934X_PCIE_WMAC_INT_PCIE_RC3
- AR934X_PCIE_WMAC_INT_WMAC_ALL
- AR934X_PCIE_WMAC_INT_WMAC_MISC
- AR934X_PCIE_WMAC_INT_WMAC_RXHP
- AR934X_PCIE_WMAC_INT_WMAC_RXLP
- AR934X_PCIE_WMAC_INT_WMAC_TX
- AR934X_PLL_CPU_CONFIG_NFRAC_MASK
- AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT
- AR934X_PLL_CPU_CONFIG_NINT_MASK
- AR934X_PLL_CPU_CONFIG_NINT_SHIFT
- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK
- AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT
- AR934X_PLL_CPU_CONFIG_REFDIV_MASK
- AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT
- AR934X_PLL_CPU_CONFIG_REG
- AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL
- AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS
- AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK
- AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT
- AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL
- AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS
- AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK
- AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT
- AR934X_PLL_CPU_DDR_CLK_CTRL_REG
- AR934X_PLL_DDR_CONFIG_NFRAC_MASK
- AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT
- AR934X_PLL_DDR_CONFIG_NINT_MASK
- AR934X_PLL_DDR_CONFIG_NINT_SHIFT
- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK
- AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT
- AR934X_PLL_DDR_CONFIG_REFDIV_MASK
- AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT
- AR934X_PLL_DDR_CONFIG_REG
- AR934X_PLL_ETH_XMII_CONTROL_REG
- AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
- AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
- AR934X_RESET_CHKSUM_ACC
- AR934X_RESET_CPU_COLD
- AR934X_RESET_CPU_NMI
- AR934X_RESET_DDR
- AR934X_RESET_ETH_SWITCH
- AR934X_RESET_ETH_SWITCH_ANALOG
- AR934X_RESET_EXTERNAL
- AR934X_RESET_FULL_CHIP
- AR934X_RESET_GE0_MAC
- AR934X_RESET_GE0_MDIO
- AR934X_RESET_GE1_MAC
- AR934X_RESET_GE1_MDIO
- AR934X_RESET_HDMA
- AR934X_RESET_HOST
- AR934X_RESET_HOST_DMA_INT
- AR934X_RESET_HOST_RESET_INT
- AR934X_RESET_I2S
- AR934X_RESET_LUT
- AR934X_RESET_MBOX
- AR934X_RESET_NANDF
- AR934X_RESET_PCIE
- AR934X_RESET_PCIE_EP
- AR934X_RESET_PCIE_EP_INT
- AR934X_RESET_PCIE_PHY
- AR934X_RESET_REG_BOOTSTRAP
- AR934X_RESET_REG_PCIE_WMAC_INT_STATUS
- AR934X_RESET_REG_RESET_MODULE
- AR934X_RESET_RTC
- AR934X_RESET_SLIC
- AR934X_RESET_UART1
- AR934X_RESET_USBSUS_OVERRIDE
- AR934X_RESET_USB_HOST
- AR934X_RESET_USB_PHY
- AR934X_RESET_USB_PHY_ANALOG
- AR934X_RESET_USB_PHY_PLL_PWD_EXT
- AR934X_REV_ID_REVISION_MASK
- AR934X_SRIF_BASE
- AR934X_SRIF_CPU_DPLL1_REG
- AR934X_SRIF_CPU_DPLL2_REG
- AR934X_SRIF_CPU_DPLL3_REG
- AR934X_SRIF_DDR_DPLL1_REG
- AR934X_SRIF_DDR_DPLL2_REG
- AR934X_SRIF_DDR_DPLL3_REG
- AR934X_SRIF_DPLL1_NFRAC_MASK
- AR934X_SRIF_DPLL1_NINT_MASK
- AR934X_SRIF_DPLL1_NINT_SHIFT
- AR934X_SRIF_DPLL1_REFDIV_MASK
- AR934X_SRIF_DPLL1_REFDIV_SHIFT
- AR934X_SRIF_DPLL2_LOCAL_PLL
- AR934X_SRIF_DPLL2_OUTDIV_MASK
- AR934X_SRIF_DPLL2_OUTDIV_SHIFT
- AR934X_SRIF_SIZE
- AR934X_WMAC_BASE
- AR934X_WMAC_SIZE
- AR9462_GPIO_MASK
- AR9462_NUM_GPIO
- AR9485_DEVID_AR1111
- AR9485_GPIO_MASK
- AR9485_NUM_GPIO
- AR9531_GPIO_MASK
- AR9531_NUM_GPIO
- AR9550_GPIO_MASK
- AR9550_NUM_GPIO
- AR9561_GPIO_MASK
- AR9561_NUM_GPIO
- AR9565_GPIO_MASK
- AR9565_NUM_GPIO
- AR9580_GPIO_MASK
- AR9580_NUM_GPIO
- ARAM_ACCESS
- ARAT_EXPIRED_INTRMSK
- ARAVALI2_CS
- ARAVALI2_PHYS
- ARAVALI_CS
- ARAVALI_PHYS
- ARB2_TIMEOUT
- ARBBISTDN
- ARBBISTEN
- ARBBISTFAIL
- ARBEL_COMPAT
- ARBEL_NATIVE
- ARBITER_CTR
- ARBITER_DETECTED
- ARBITER_SERR_MASK
- ARBITRARY_ADDR
- ARBITRARY_UNIT
- ARBITSTATUS
- ARBIT_CLEAR
- ARBIT_FAIL
- ARBIT_FLAG_CLEAR
- ARBIT_GO
- ARBIT_STATUS
- ARBIT_TIMEOUT_TIME
- ARBIT_WIN
- ARBLST
- ARB_ARM_ACK
- ARB_ARM_REQ
- ARB_CG_REQ
- ARB_CG_REQ_MASK
- ARB_CG_REQ_SHIFT
- ARB_CG_RESP
- ARB_CG_RESP_MASK
- ARB_CG_RESP_SHIFT
- ARB_CI_PARK
- ARB_CNTRL
- ARB_CONFIG_CFG_REG
- ARB_CONFIG_GNT_REG
- ARB_CONFIG_REG
- ARB_CORE_PARK
- ARB_DMA_PARK
- ARB_DMA_SLV_PARK
- ARB_ERR_CAP_ADDR
- ARB_ERR_CAP_CLEAR
- ARB_ERR_CAP_CLR
- ARB_ERR_CAP_HI_ADDR
- ARB_ERR_CAP_MASTER
- ARB_ERR_CAP_STATUS
- ARB_ERR_CAP_STATUS_TEA
- ARB_ERR_CAP_STATUS_TIMEOUT
- ARB_ERR_CAP_STATUS_VALID
- ARB_ERR_CAP_STATUS_WRITE
- ARB_EX_MEM_PARK
- ARB_GDEC_RD_CNTL
- ARB_GENERAL_BIT
- ARB_IF_WITH_HIGHEST_PRIORITY
- ARB_INT_MEM_PARK
- ARB_LCD_PARK
- ARB_LOCK_FLAG
- ARB_LOST
- ARB_MODE
- ARB_MODE_BWGTLB_DISABLE
- ARB_MODE_SWIZZLE_BDW
- ARB_MODE_SWIZZLE_IVB
- ARB_MODE_SWIZZLE_SNB
- ARB_OFF
- ARB_ON
- ARB_ON_OFF
- ARB_POP
- ARB_REG
- ARB_RFSH_CNTL
- ARB_RFSH_RATE
- ARB_RNUM_MAX
- ARB_ROUND_ROBIN_MODE
- ARB_TIMEOUT
- ARB_TIMER
- ARB_USB_PARK
- ARB_VOLUME
- ARC
- ARC2C0608
- ARC4
- ARC4_BLOCK_SIZE
- ARC4_MAX_KEY_SIZE
- ARC4_MIN_KEY_SIZE
- ARC4_STATE_SIZE
- ARCACHE_DEFAULT_VALUE
- ARCADIA_2ND_BRIDGE_IDSEL
- ARCADIA_HOST_BRIDGE_IDSEL
- ARCHE_PLATFORM_STATE_ACTIVE
- ARCHE_PLATFORM_STATE_FW_FLASHING
- ARCHE_PLATFORM_STATE_OFF
- ARCHE_PLATFORM_STATE_STANDBY
- ARCHIVE_MAGICNUMBER
- ARCH_APICTIMER_STOPS_ON_C3
- ARCH_ARM_MACH_OMAP2_HDQ1W_H
- ARCH_ARM_PLAT_OMAP4_ISS_H
- ARCH_CAP_IBRS_ALL
- ARCH_CAP_MDS_NO
- ARCH_CAP_PSCHANGE_MC_NO
- ARCH_CAP_RDCL_NO
- ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
- ARCH_CAP_SSB_NO
- ARCH_CAP_TAA_NO
- ARCH_CAP_TSX_CTRL_MSR
- ARCH_COLD_RESET
- ARCH_COMMAND_LINE_SIZE
- ARCH_DEFAULT_PKEY
- ARCH_DLINFO
- ARCH_DLINFO_CACHE_GEOMETRY
- ARCH_DLINFO_IA32
- ARCH_DLINFO_X32
- ARCH_DMA_MINALIGN
- ARCH_EFI_IRQ_FLAGS_MASK
- ARCH_FTRACE_SHIFT_STACK_TRACER
- ARCH_GENERIC_PCI_MMAP_RESOURCE
- ARCH_GET_CPUID
- ARCH_GET_FS
- ARCH_GET_GS
- ARCH_HAS_FLUSH_ANON_PAGE
- ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
- ARCH_HAS_HUGEPAGE_CLEAR_FLUSH
- ARCH_HAS_HUGE_PTE_TYPE
- ARCH_HAS_IOREMAP_WC
- ARCH_HAS_IOREMAP_WT
- ARCH_HAS_KIMAGE_ARCH
- ARCH_HAS_KMAP
- ARCH_HAS_NOCACHE_UACCESS
- ARCH_HAS_OWN_IRQ_REGS
- ARCH_HAS_POWER_INIT
- ARCH_HAS_PREFETCH
- ARCH_HAS_PREFETCHW
- ARCH_HAS_PREPARE_HUGEPAGE
- ARCH_HAS_READ_CURRENT_TIMER
- ARCH_HAS_RELATIVE_EXTABLE
- ARCH_HAS_SEARCH_EXTABLE
- ARCH_HAS_SETCLEAR_HUGE_PTE
- ARCH_HAS_SETUP_ADDITIONAL_PAGES
- ARCH_HAS_SOCKET_TYPES
- ARCH_HAS_SORT_EXTABLE
- ARCH_HAS_SPINLOCK_PREFETCH
- ARCH_HAS_SYSCALL_MATCH_SYM_NAME
- ARCH_HAS_TRANSLATE_MEM_PTR
- ARCH_HAS_USABLE_BUILTIN_POPCOUNT
- ARCH_HAS_USER_SINGLE_STEP_REPORT
- ARCH_HAS_VALID_PHYS_ADDR_RANGE
- ARCH_HAVE_DECOMP_PUTS
- ARCH_HAVE_EXTRA_ELF_NOTES
- ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
- ARCH_IRQ_DISABLED
- ARCH_IRQ_ENABLED
- ARCH_IRQ_INIT_FLAGS
- ARCH_IS_STACKGROW
- ARCH_KMALLOC_FLAGS
- ARCH_KMALLOC_MINALIGN
- ARCH_LOW_ADDRESS_LIMIT
- ARCH_MAP_VDSO_32
- ARCH_MAP_VDSO_64
- ARCH_MAP_VDSO_X32
- ARCH_MAX_REGS
- ARCH_MEMREMAP_PMEM
- ARCH_MIN_MMSTRUCT_ALIGN
- ARCH_MIN_TASKALIGN
- ARCH_MODULE_DEBUG
- ARCH_NEEDS_KMAP_HIGH_GET
- ARCH_NEEDS_WEAK_PER_CPU
- ARCH_NR_GPIOS
- ARCH_OFFSET
- ARCH_P4_CNTRVAL_BITS
- ARCH_P4_CNTRVAL_MASK
- ARCH_P4_MAX_CCCR
- ARCH_P4_MAX_ESCR
- ARCH_P4_RESERVED_ESCR
- ARCH_P4_TOTAL_ESCR
- ARCH_P4_UNFLAGGED_BIT
- ARCH_PACK_COMPAT_STATFS64
- ARCH_PACK_STATFS64
- ARCH_PANIC_TIMEOUT
- ARCH_PERFMON_BRANCH_MISSES_RETIRED
- ARCH_PERFMON_EVENTSEL_ANY
- ARCH_PERFMON_EVENTSEL_CMASK
- ARCH_PERFMON_EVENTSEL_EDGE
- ARCH_PERFMON_EVENTSEL_ENABLE
- ARCH_PERFMON_EVENTSEL_EVENT
- ARCH_PERFMON_EVENTSEL_INT
- ARCH_PERFMON_EVENTSEL_INV
- ARCH_PERFMON_EVENTSEL_OS
- ARCH_PERFMON_EVENTSEL_PIN_CONTROL
- ARCH_PERFMON_EVENTSEL_UMASK
- ARCH_PERFMON_EVENTSEL_USR
- ARCH_PERFMON_EVENTS_COUNT
- ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX
- ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT
- ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
- ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
- ARCH_PERF_BOOK3S_HV_EXITS_H
- ARCH_PERF_BOOK3S_HV_HCALLS_H
- ARCH_PERF_COMMON_H
- ARCH_PERF_REGS_H
- ARCH_PFN_OFFSET
- ARCH_PREV_KPROBE_SZ
- ARCH_PRNG_SEED_SIZE
- ARCH_REFILL_TICKS
- ARCH_REGS
- ARCH_RESET_TYPE
- ARCH_RNG_BUF_SIZE
- ARCH_RTC_LOCATION
- ARCH_S390
- ARCH_S390X
- ARCH_S390_KVM_S390_H
- ARCH_SET_CPUID
- ARCH_SET_FS
- ARCH_SET_GS
- ARCH_SHF_SMALL
- ARCH_SLAB_MINALIGN
- ARCH_STATIC_BRANCH
- ARCH_SUN4I_A10
- ARCH_SUN5I_A13
- ARCH_SUN6I_A31
- ARCH_SUPPORTS_FTRACE_OPS
- ARCH_TESTS_H
- ARCH_TIMER_CTRL_ENABLE
- ARCH_TIMER_CTRL_IT_MASK
- ARCH_TIMER_CTRL_IT_STAT
- ARCH_TIMER_EVT_STREAM_FREQ
- ARCH_TIMER_EVT_STREAM_PERIOD_US
- ARCH_TIMER_EVT_TRIGGER_MASK
- ARCH_TIMER_EVT_TRIGGER_SHIFT
- ARCH_TIMER_HYP_PPI
- ARCH_TIMER_IRQ
- ARCH_TIMER_MAX_TIMER_PPI
- ARCH_TIMER_MAX_TIMER_SPI
- ARCH_TIMER_MEM_MAX_FRAMES
- ARCH_TIMER_MEM_PHYS_ACCESS
- ARCH_TIMER_MEM_VIRT_ACCESS
- ARCH_TIMER_PHYS_ACCESS
- ARCH_TIMER_PHYS_NONSECURE_PPI
- ARCH_TIMER_PHYS_SECURE_PPI
- ARCH_TIMER_PHYS_SPI
- ARCH_TIMER_REG_CTRL
- ARCH_TIMER_REG_TVAL
- ARCH_TIMER_TYPE_CP15
- ARCH_TIMER_TYPE_MEM
- ARCH_TIMER_USR_PCT_ACCESS_EN
- ARCH_TIMER_USR_PT_ACCESS_EN
- ARCH_TIMER_USR_VCT_ACCESS_EN
- ARCH_TIMER_USR_VT_ACCESS_EN
- ARCH_TIMER_VIRT_ACCESS
- ARCH_TIMER_VIRT_EVT_EN
- ARCH_TIMER_VIRT_PPI
- ARCH_TIMER_VIRT_SPI
- ARCH_TRACE_CLOCKS
- ARCH_TRACE_IGNORE_COMPAT_SYSCALLS
- ARCH_VIPER_H
- ARCH_VM_PKEY_FLAGS
- ARCH_X86_CPU_H
- ARCH_X86_KERNEL_ACPI_RM_WAKEUP_H
- ARCH_X86_KVM_CPUID_H
- ARCH_X86_KVM_X86_H
- ARCH_X86_REALMODE_RM_REALMODE_H
- ARCH_ZONE_DMA_BITS
- ARCMSR_API_DATA_BUFLEN
- ARCMSR_ARC1214_ALL_INT_DISABLE
- ARCMSR_ARC1214_ALL_INT_ENABLE
- ARCMSR_ARC1214_CHIP_ID
- ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION
- ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY
- ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ
- ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK
- ARCMSR_ARC1214_INBOUND_DOORBELL
- ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH
- ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW
- ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER
- ARCMSR_ARC1214_INBOUND_MESSAGE0
- ARCMSR_ARC1214_INBOUND_MESSAGE1
- ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
- ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
- ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE
- ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS
- ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK
- ARCMSR_ARC1214_MESSAGE_RBUFFER
- ARCMSR_ARC1214_MESSAGE_RWBUFFER
- ARCMSR_ARC1214_MESSAGE_WBUFFER
- ARCMSR_ARC1214_OUTBOUND_DOORBELL
- ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE
- ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR
- ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE
- ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE
- ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH
- ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW
- ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER
- ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR
- ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER
- ARCMSR_ARC1214_OUTBOUND_MESSAGE0
- ARCMSR_ARC1214_OUTBOUND_MESSAGE1
- ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR
- ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE
- ARCMSR_ARC1214_RESET_REQUEST
- ARCMSR_ARC1214_SAMPLE_RESET
- ARCMSR_ARC1680_BUS_RESET
- ARCMSR_ARC1880_DiagWrite_ENABLE
- ARCMSR_ARC1880_RESET_ADAPTER
- ARCMSR_ARC1884_DiagWrite_ENABLE
- ARCMSR_ARC188X_RESET_ADAPTER
- ARCMSR_CCBPOST_FLAG_IAM_BIOS
- ARCMSR_CCBPOST_FLAG_SGL_BSIZE
- ARCMSR_CCBREPLY_FLAG_ERROR_MODE0
- ARCMSR_CCBREPLY_FLAG_ERROR_MODE1
- ARCMSR_CCBREPLY_FLAG_IAM_BIOS
- ARCMSR_CCB_ABORTED
- ARCMSR_CCB_DONE
- ARCMSR_CCB_ILLEGAL
- ARCMSR_CCB_START
- ARCMSR_CDB
- ARCMSR_CDB_FLAG_BIOS
- ARCMSR_CDB_FLAG_HEADQ
- ARCMSR_CDB_FLAG_ORDEREDQ
- ARCMSR_CDB_FLAG_SGL_BSIZE
- ARCMSR_CDB_FLAG_SIMPLEQ
- ARCMSR_CDB_FLAG_WRITE
- ARCMSR_CDB_SG_PAGE_LENGTH
- ARCMSR_DEFAULT_CMD_PERLUN
- ARCMSR_DEFAULT_OUTSTANDING_CMD
- ARCMSR_DEFAULT_SG_ENTRIES
- ARCMSR_DEV_ABORTED
- ARCMSR_DEV_CHECK_CONDITION
- ARCMSR_DEV_INIT_FAIL
- ARCMSR_DEV_SELECT_TIMEOUT
- ARCMSR_DOORBELL_HANDLE_INT
- ARCMSR_DOORBELL_INT_CLEAR_PATTERN
- ARCMSR_DRIVER_VERSION
- ARCMSR_DRV2IOP_CDB_POSTED
- ARCMSR_DRV2IOP_DATA_READ_OK
- ARCMSR_DRV2IOP_DATA_WRITE_OK
- ARCMSR_DRV2IOP_DOORBELL
- ARCMSR_DRV2IOP_DOORBELL_1203
- ARCMSR_DRV2IOP_DOORBELL_MASK
- ARCMSR_DRV2IOP_DOORBELL_MASK_1203
- ARCMSR_DRV2IOP_END_OF_INTERRUPT
- ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED
- ARCMSR_HBCMU_ALL_INTMASKENABLE
- ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK
- ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK
- ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE
- ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING
- ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR
- ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
- ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR
- ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
- ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE
- ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR
- ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK
- ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR
- ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK
- ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR
- ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK
- ARCMSR_HBCMU_SAS_ALL_INT
- ARCMSR_HBCMU_UTILITY_A_ISR
- ARCMSR_HBCMU_UTILITY_A_ISR_MASK
- ARCMSR_HBC_ISR_MAX_DONE_QUEUE
- ARCMSR_HBC_ISR_THROTTLING_LEVEL
- ARCMSR_HBEMU_ALL_INTMASKENABLE
- ARCMSR_HBEMU_DOORBELL_SYNC
- ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK
- ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK
- ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE
- ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
- ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
- ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE
- ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK
- ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR
- ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR
- ARCMSR_HOURS
- ARCMSR_INBOUND_DRIVER_DATA_READ_OK
- ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK
- ARCMSR_INBOUND_MESG0_ABORT_CMD
- ARCMSR_INBOUND_MESG0_CHK331PENDING
- ARCMSR_INBOUND_MESG0_FLUSH_CACHE
- ARCMSR_INBOUND_MESG0_GET_CONFIG
- ARCMSR_INBOUND_MESG0_NOP
- ARCMSR_INBOUND_MESG0_SET_CONFIG
- ARCMSR_INBOUND_MESG0_START_BGRB
- ARCMSR_INBOUND_MESG0_STOP_BGRB
- ARCMSR_INBOUND_MESG0_SYNC_TIMER
- ARCMSR_IOP2DRV_CDB_DONE
- ARCMSR_IOP2DRV_DATA_READ_OK
- ARCMSR_IOP2DRV_DATA_WRITE_OK
- ARCMSR_IOP2DRV_DOORBELL
- ARCMSR_IOP2DRV_DOORBELL_1203
- ARCMSR_IOP2DRV_DOORBELL_MASK
- ARCMSR_IOP2DRV_DOORBELL_MASK_1203
- ARCMSR_IOP2DRV_MESSAGE_CMD_DONE
- ARCMSR_MAX_ARC1214_DONEQUEUE
- ARCMSR_MAX_ARC1214_POSTQUEUE
- ARCMSR_MAX_CMD_PERLUN
- ARCMSR_MAX_FREECCB_NUM
- ARCMSR_MAX_HBB_POSTQUEUE
- ARCMSR_MAX_HBE_DONEQUEUE
- ARCMSR_MAX_OUTSTANDING_CMD
- ARCMSR_MAX_QBUFFER
- ARCMSR_MAX_TARGETID
- ARCMSR_MAX_TARGETLUN
- ARCMSR_MAX_XFER_LEN
- ARCMSR_MAX_XFER_SECTORS
- ARCMSR_MAX_XFER_SECTORS_B
- ARCMSR_MAX_XFER_SECTORS_C
- ARCMSR_MESSAGE_ABORT_CMD
- ARCMSR_MESSAGE_ACTIVE_EOI_MODE
- ARCMSR_MESSAGE_CLEAR_ALLQBUFFER
- ARCMSR_MESSAGE_CLEAR_RQBUFFER
- ARCMSR_MESSAGE_CLEAR_WQBUFFER
- ARCMSR_MESSAGE_FAIL
- ARCMSR_MESSAGE_FIRMWARE_OK
- ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE
- ARCMSR_MESSAGE_FLUSH_CACHE
- ARCMSR_MESSAGE_GET_CONFIG
- ARCMSR_MESSAGE_INT_CLEAR_PATTERN
- ARCMSR_MESSAGE_RBUFFER
- ARCMSR_MESSAGE_READ_RQBUFFER
- ARCMSR_MESSAGE_RETURNCODE_3F
- ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON
- ARCMSR_MESSAGE_RETURNCODE_ERROR
- ARCMSR_MESSAGE_RETURNCODE_OK
- ARCMSR_MESSAGE_RETURN_CODE_3F
- ARCMSR_MESSAGE_RWBUFFER
- ARCMSR_MESSAGE_SAY_GOODBYE
- ARCMSR_MESSAGE_SAY_HELLO
- ARCMSR_MESSAGE_SET_CONFIG
- ARCMSR_MESSAGE_SET_POST_WINDOW
- ARCMSR_MESSAGE_START_BGRB
- ARCMSR_MESSAGE_START_DRIVER_MODE
- ARCMSR_MESSAGE_STOP_BGRB
- ARCMSR_MESSAGE_SYNC_TIMER
- ARCMSR_MESSAGE_WBUFFER
- ARCMSR_MESSAGE_WRITE_WQBUFFER
- ARCMSR_MINUTES
- ARCMSR_MIN_CMD_PERLUN
- ARCMSR_MIN_OUTSTANDING_CMD
- ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE
- ARCMSR_MU_OUTBOUND_DOORBELL_INT
- ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE
- ARCMSR_MU_OUTBOUND_HANDLE_INT
- ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG
- ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG
- ARCMSR_MU_OUTBOUND_MESSAGE0_INT
- ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE
- ARCMSR_MU_OUTBOUND_MESSAGE1_INT
- ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE
- ARCMSR_MU_OUTBOUND_PCI_INT
- ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE
- ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
- ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE
- ARCMSR_OUTBOUND_IOP331_DATA_READ_OK
- ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
- ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK
- ARCMSR_RETRYCOUNT
- ARCMSR_SCSI_INITIATOR_ID
- ARCMSR_SIGNATURE_1884
- ARCMSR_SIGNATURE_GET_CONFIG
- ARCMSR_SIGNATURE_SET_CONFIG
- ARCMSR_SLEEPTIME
- ARCMST_NUM_MSIX_VECTORS
- ARCNET_ALEN
- ARCNET_DEBUG
- ARCNET_DEBUG_MAX
- ARCNET_LED_EVENT_OPEN
- ARCNET_LED_EVENT_RECON
- ARCNET_LED_EVENT_STOP
- ARCNET_LED_EVENT_TX
- ARCNET_LED_NAME_SZ
- ARCNET_TOTAL_SIZE
- ARCOFI_USE
- ARCOM2
- ARCPGU_CTRL_ENABLE_MASK
- ARCPGU_CTRL_HS_POL_MASK
- ARCPGU_CTRL_HS_POL_OFST
- ARCPGU_CTRL_VS_POL_MASK
- ARCPGU_CTRL_VS_POL_OFST
- ARCPGU_MODE_RGB888_MASK
- ARCPGU_REG_ACTIVE
- ARCPGU_REG_BUF0_ADDR
- ARCPGU_REG_CTRL
- ARCPGU_REG_FMT
- ARCPGU_REG_HSYNC
- ARCPGU_REG_ID
- ARCPGU_REG_START_SET
- ARCPGU_REG_STAT
- ARCPGU_REG_STRIDE
- ARCPGU_REG_VSYNC
- ARCPGU_STAT_BUSY_MASK
- ARCPMU_ATTR_GR_EVENTS
- ARCPMU_ATTR_GR_FORMATS
- ARCPMU_EVENT_NAME_LEN
- ARCPMU_NR_ATTR_GR
- ARCRW
- ARCSR0
- ARCSR0_AR_BBP_DATA0
- ARCSR0_AR_BBP_DATA1
- ARCSR0_AR_BBP_ID0
- ARCSR0_AR_BBP_ID1
- ARCSR1
- ARCSR1_AR_BBP_DATA2
- ARCSR1_AR_BBP_DATA3
- ARCSR1_AR_BBP_ID2
- ARCSR1_AR_BBP_ID3
- ARCSR2
- ARCSR2_LENGTH
- ARCSR2_LENGTH_LOW
- ARCSR2_SERVICE
- ARCSR2_SIGNAL
- ARCSR3
- ARCSR3_LENGTH
- ARCSR3_SERVICE
- ARCSR3_SIGNAL
- ARCSR4
- ARCSR4_LENGTH
- ARCSR4_SERVICE
- ARCSR4_SIGNAL
- ARCSR5
- ARCSR5_LENGTH
- ARCSR5_SERVICE
- ARCSR5_SIGNAL
- ARCS_SPB_ADDR
- ARCS_SPB_OFFSET
- ARCS_SPB_SIZE
- ARCTURUS_FEA_MAP
- ARCTURUS_PP_SMC_H
- ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL
- ARCTURUS_UMD_PSTATE_MCLK_LEVEL
- ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL
- ARCV2_IRQ_DEF_PRIO
- ARCVR_DTCT_EN
- ARCVR_DTCT_EVENT_SEL
- ARCXCNN_CMD
- ARCXCNN_CMD_BOOST
- ARCXCNN_CMD_EXT_COMP
- ARCXCNN_CMD_OVP_20V
- ARCXCNN_CMD_OVP_24V
- ARCXCNN_CMD_OVP_31V
- ARCXCNN_CMD_OVP_MASK
- ARCXCNN_CMD_OVP_XXV
- ARCXCNN_CMD_RESET
- ARCXCNN_CMD_STDBY
- ARCXCNN_COMP_CONFIG
- ARCXCNN_CONFIG
- ARCXCNN_DIMFREQ
- ARCXCNN_FADECTRL
- ARCXCNN_FILT_CONFIG
- ARCXCNN_ID_LSB
- ARCXCNN_ID_MSB
- ARCXCNN_ILED_CONFIG
- ARCXCNN_ILED_DIM_INT
- ARCXCNN_ILED_DIM_PWM
- ARCXCNN_IMAXTUNE
- ARCXCNN_LEDEN
- ARCXCNN_LEDEN_BITS
- ARCXCNN_LEDEN_ISETEXT
- ARCXCNN_LEDEN_LED1
- ARCXCNN_LEDEN_LED2
- ARCXCNN_LEDEN_LED3
- ARCXCNN_LEDEN_LED4
- ARCXCNN_LEDEN_LED5
- ARCXCNN_LEDEN_LED6
- ARCXCNN_LEDEN_MASK
- ARCXCNN_STATUS1
- ARCXCNN_STATUS2
- ARCXCNN_WLED_ISET_LSB
- ARCXCNN_WLED_ISET_LSB_SHIFT
- ARCXCNN_WLED_ISET_MSB
- ARC_ARC_PS2_ID
- ARC_AUX_DPFP_1H
- ARC_AUX_DPFP_1L
- ARC_AUX_DPFP_2H
- ARC_AUX_DPFP_2L
- ARC_AUX_DPFP_STAT
- ARC_AUX_FP_STAT
- ARC_AUX_SLC_FLDL
- ARC_AUX_SLC_IVDL
- ARC_BSWAP_TYPE
- ARC_CALL0
- ARC_CALL1
- ARC_CALL2
- ARC_CALL3
- ARC_CALL4
- ARC_CALL5
- ARC_CAN_10MBIT
- ARC_CCM_UNUSED_ADDR
- ARC_EMAC_H
- ARC_EMAC_NAPI_WEIGHT
- ARC_EZNPS_DP_PREV
- ARC_FAILURE
- ARC_FPU_NEXT
- ARC_FPU_PREV
- ARC_HDR_SIZE
- ARC_IO_COH_ENABLE_BIT
- ARC_IO_COH_PARTIAL_BIT
- ARC_IRQ_VECTOR_OFFSET
- ARC_IS_5MBIT
- ARC_JAL_INST
- ARC_MDIO_COMPLETE_POLL_COUNT
- ARC_PAGE_SHIFT
- ARC_PATH_MAX
- ARC_PERF_MAX_COUNTERS
- ARC_PERIPHERAL_BASE
- ARC_PS2_PORTS
- ARC_P_ARP
- ARC_P_ARP_RFC1051
- ARC_P_ATALK
- ARC_P_DATAPOINT_BOOT
- ARC_P_DATAPOINT_MOUNT
- ARC_P_ETHER
- ARC_P_IP
- ARC_P_IPV6
- ARC_P_IPX
- ARC_P_IP_RFC1051
- ARC_P_LANSOFT
- ARC_P_NOVELL_EC
- ARC_P_POWERLAN_BEACON
- ARC_P_POWERLAN_BEACON2
- ARC_P_RARP
- ARC_REG_AP_BCR
- ARC_REG_AUX_DCCM
- ARC_REG_AUX_ICCM
- ARC_REG_BARREL_BCR
- ARC_REG_BPU_BCR
- ARC_REG_CC_BUILD
- ARC_REG_CC_INDEX
- ARC_REG_CC_NAME0
- ARC_REG_CC_NAME1
- ARC_REG_CLUSTER_BCR
- ARC_REG_CRC_BCR
- ARC_REG_DCCM_BASE_BUILD
- ARC_REG_DCCM_BUILD
- ARC_REG_DC_BCR
- ARC_REG_DC_CTRL
- ARC_REG_DC_ENDR
- ARC_REG_DC_FLDL
- ARC_REG_DC_FLSH
- ARC_REG_DC_IVDC
- ARC_REG_DC_IVDL
- ARC_REG_DC_PTAG
- ARC_REG_DC_PTAG_HI
- ARC_REG_DC_STARTR
- ARC_REG_DPFP_BCR
- ARC_REG_D_UNCACH_BCR
- ARC_REG_ERP_BUILD
- ARC_REG_ERP_CTRL
- ARC_REG_FP_BCR
- ARC_REG_FP_V2_BCR
- ARC_REG_GFRC_BUILD
- ARC_REG_ICCM_BUILD
- ARC_REG_IC_BCR
- ARC_REG_IC_CTRL
- ARC_REG_IC_ENDR
- ARC_REG_IC_IVIC
- ARC_REG_IC_IVIL
- ARC_REG_IC_IVIR
- ARC_REG_IC_PTAG
- ARC_REG_IC_PTAG_HI
- ARC_REG_IO_COH_AP0_BASE
- ARC_REG_IO_COH_AP0_SIZE
- ARC_REG_IO_COH_ENABLE
- ARC_REG_IO_COH_PARTIAL
- ARC_REG_IRQ_BCR
- ARC_REG_ISA_CFG_BCR
- ARC_REG_LPB_BUILD
- ARC_REG_LPB_CTRL
- ARC_REG_MAC_BCR
- ARC_REG_MCIP_BCR
- ARC_REG_MCIP_CMD
- ARC_REG_MCIP_IDU_BCR
- ARC_REG_MCIP_READBACK
- ARC_REG_MCIP_WDATA
- ARC_REG_MICRO_ARCH_BCR
- ARC_REG_MIXMAX_BCR
- ARC_REG_MMU_BCR
- ARC_REG_MUL_BCR
- ARC_REG_NORM_BCR
- ARC_REG_PCT_BUILD
- ARC_REG_PCT_CONFIG
- ARC_REG_PCT_CONFIG_KERN
- ARC_REG_PCT_CONFIG_USER
- ARC_REG_PCT_CONTROL
- ARC_REG_PCT_CONTROL_CC
- ARC_REG_PCT_CONTROL_SN
- ARC_REG_PCT_COUNTH
- ARC_REG_PCT_COUNTL
- ARC_REG_PCT_INDEX
- ARC_REG_PCT_INT_ACT
- ARC_REG_PCT_INT_CNTH
- ARC_REG_PCT_INT_CNTL
- ARC_REG_PCT_INT_CTRL
- ARC_REG_PCT_SNAPH
- ARC_REG_PCT_SNAPL
- ARC_REG_PERIBASE_BCR
- ARC_REG_PID
- ARC_REG_RTT_BCR
- ARC_REG_SCRATCH_DATA0
- ARC_REG_SLC_BCR
- ARC_REG_SLC_CFG
- ARC_REG_SLC_CTRL
- ARC_REG_SLC_FLUSH
- ARC_REG_SLC_INVALIDATE
- ARC_REG_SLC_RGN_END
- ARC_REG_SLC_RGN_END1
- ARC_REG_SLC_RGN_START
- ARC_REG_SLC_RGN_START1
- ARC_REG_SMART_BCR
- ARC_REG_STATUS32
- ARC_REG_SWAP_BCR
- ARC_REG_TIMER0_CNT
- ARC_REG_TIMER0_CTRL
- ARC_REG_TIMER0_LIMIT
- ARC_REG_TIMER1_CNT
- ARC_REG_TIMER1_CTRL
- ARC_REG_TIMER1_LIMIT
- ARC_REG_TIMERS_BCR
- ARC_REG_TLBCOMMAND
- ARC_REG_TLBINDEX
- ARC_REG_TLBPD0
- ARC_REG_TLBPD1
- ARC_REG_TLBPD1HI
- ARC_REG_VECBASE_BCR
- ARC_REG_XY_MEM_BCR
- ARC_SERIAL_DEV_NAME
- ARC_SUCCESS
- ARC_TIMERN_MAX
- ARC_UART_TX_FIFO_SIZE
- ARC_UNCACHED_ADDR_SPACE
- ARC_me_imm32
- AREA5_WAIT_CTRL
- AREA_2M
- AREA_4K
- ARECA_RAID_GONE
- ARECA_RAID_GOOD
- ARECA_SATA_RAID
- AREF0
- AREF1
- AREF2
- AREF3
- AREF4
- AREF5
- AREF6
- AREF7
- AREF_COMMON
- AREF_DIFF
- AREF_GROUND
- AREF_OTHER
- AREG
- ARENA_MAX_SIZE
- ARENA_MIN_SIZE
- ARFR
- ARFR0
- ARFR1
- ARFR2
- ARFR3
- ARFR4
- ARFR5
- ARFR6
- ARFR7
- ARFS_HASH_SHIFT
- ARFS_HASH_SIZE
- ARFS_IPV4_TCP
- ARFS_IPV4_UDP
- ARFS_IPV6_TCP
- ARFS_IPV6_UDP
- ARFS_NUM_TYPES
- ARG
- ARG0
- ARG0_OFF
- ARG1
- ARG1_OFF
- ARG2
- ARG2_OFF
- ARG3
- ARG4
- ARG5
- ARG6
- ARGB1555
- ARGB16161616_10LSB
- ARGB16161616_10MSB
- ARGB16161616_12LSB
- ARGB16161616_12MSB
- ARGB16161616_FLOAT
- ARGB16161616_SNORM
- ARGB16161616_UNORM
- ARGB2101010
- ARGB4444
- ARGB8888
- ARGB8888_1X32
- ARGBASE
- ARGI_ACCESSFIELD_OP
- ARGI_ACQUIRE_OP
- ARGI_ADD_OP
- ARGI_ALIAS_OP
- ARGI_ANYTYPE
- ARGI_ARG0
- ARGI_ARG1
- ARGI_ARG2
- ARGI_ARG3
- ARGI_ARG4
- ARGI_ARG5
- ARGI_ARG6
- ARGI_BANK_FIELD_OP
- ARGI_BIT_AND_OP
- ARGI_BIT_NAND_OP
- ARGI_BIT_NOR_OP
- ARGI_BIT_NOT_OP
- ARGI_BIT_OR_OP
- ARGI_BIT_XOR_OP
- ARGI_BREAK_OP
- ARGI_BREAK_POINT_OP
- ARGI_BUFFER
- ARGI_BUFFER_OP
- ARGI_BUFFER_OR_STRING
- ARGI_BYTELIST_OP
- ARGI_BYTE_OP
- ARGI_COMMENT_OP
- ARGI_COMPLEXOBJ
- ARGI_COMPUTEDATA
- ARGI_CONCAT_OP
- ARGI_CONCAT_RES_OP
- ARGI_COND_REF_OF_OP
- ARGI_CONNECTFIELD_OP
- ARGI_CONTINUE_OP
- ARGI_COPY_OP
- ARGI_CREATE_BIT_FIELD_OP
- ARGI_CREATE_BYTE_FIELD_OP
- ARGI_CREATE_DWORD_FIELD_OP
- ARGI_CREATE_FIELD_OP
- ARGI_CREATE_QWORD_FIELD_OP
- ARGI_CREATE_WORD_FIELD_OP
- ARGI_DATAOBJECT
- ARGI_DATAREFOBJ
- ARGI_DATA_REGION_OP
- ARGI_DDBHANDLE
- ARGI_DEBUG_OP
- ARGI_DECREMENT_OP
- ARGI_DEREF_OF_OP
- ARGI_DEVICE_OP
- ARGI_DEVICE_REF
- ARGI_DIVIDE_OP
- ARGI_DWORD_OP
- ARGI_ELSE_OP
- ARGI_EVENT
- ARGI_EVENT_OP
- ARGI_EXTERNAL_OP
- ARGI_FATAL_OP
- ARGI_FIELD_OP
- ARGI_FIND_SET_LEFT_BIT_OP
- ARGI_FIND_SET_RIGHT_BIT_OP
- ARGI_FIXED_TARGET
- ARGI_FROM_BCD_OP
- ARGI_IF_OP
- ARGI_INCREMENT_OP
- ARGI_INDEX_FIELD_OP
- ARGI_INDEX_OP
- ARGI_INTEGER
- ARGI_INTEGER_REF
- ARGI_INVALID_OPCODE
- ARGI_LAND_OP
- ARGI_LEQUAL_OP
- ARGI_LGREATEREQUAL_OP
- ARGI_LGREATER_OP
- ARGI_LIST1
- ARGI_LIST2
- ARGI_LIST3
- ARGI_LIST4
- ARGI_LIST5
- ARGI_LIST6
- ARGI_LLESSEQUAL_OP
- ARGI_LLESS_OP
- ARGI_LNOTEQUAL_OP
- ARGI_LNOT_OP
- ARGI_LOAD_OP
- ARGI_LOAD_TABLE_OP
- ARGI_LOCAL0
- ARGI_LOCAL1
- ARGI_LOCAL2
- ARGI_LOCAL3
- ARGI_LOCAL4
- ARGI_LOCAL5
- ARGI_LOCAL6
- ARGI_LOCAL7
- ARGI_LOR_OP
- ARGI_MATCH_OP
- ARGI_METHODCALL_OP
- ARGI_METHOD_OP
- ARGI_MID_OP
- ARGI_MOD_OP
- ARGI_MULTIPLY_OP
- ARGI_MUTEX
- ARGI_MUTEX_OP
- ARGI_NAMEDFIELD_OP
- ARGI_NAMEPATH_OP
- ARGI_NAME_OP
- ARGI_NOOP_OP
- ARGI_NOTIFY_OP
- ARGI_OBJECT_REF
- ARGI_OBJECT_TYPE_OP
- ARGI_ONES_OP
- ARGI_ONE_OP
- ARGI_PACKAGE
- ARGI_PACKAGE_OP
- ARGI_POWER_RES_OP
- ARGI_PROCESSOR_OP
- ARGI_QWORD_OP
- ARGI_REFERENCE
- ARGI_REF_OF_OP
- ARGI_REF_OR_STRING
- ARGI_REGION_OP
- ARGI_REGION_OR_BUFFER
- ARGI_RELEASE_OP
- ARGI_RESERVEDFIELD_OP
- ARGI_RESET_OP
- ARGI_RETURN_OP
- ARGI_REVISION_OP
- ARGI_SCOPE_OP
- ARGI_SERIALFIELD_OP
- ARGI_SHIFT_LEFT_OP
- ARGI_SHIFT_RIGHT_OP
- ARGI_SIGNAL_OP
- ARGI_SIMPLE_TARGET
- ARGI_SIZE_OF_OP
- ARGI_SLEEP_OP
- ARGI_STALL_OP
- ARGI_STATICSTRING_OP
- ARGI_STORE_OP
- ARGI_STORE_TARGET
- ARGI_STRING
- ARGI_STRING_OP
- ARGI_SUBTRACT_OP
- ARGI_TARGETREF
- ARGI_THERMAL_ZONE_OP
- ARGI_TIMER_OP
- ARGI_TO_BCD_OP
- ARGI_TO_BUFFER_OP
- ARGI_TO_DEC_STR_OP
- ARGI_TO_HEX_STR_OP
- ARGI_TO_INTEGER_OP
- ARGI_TO_STRING_OP
- ARGI_UNLOAD_OP
- ARGI_VAR_PACKAGE_OP
- ARGI_WAIT_OP
- ARGI_WHILE_OP
- ARGI_WORD_OP
- ARGI_ZERO_OP
- ARGP_ACCESSFIELD_OP
- ARGP_ACQUIRE_OP
- ARGP_ADD_OP
- ARGP_ALIAS_OP
- ARGP_ARG0
- ARGP_ARG1
- ARGP_ARG2
- ARGP_ARG3
- ARGP_ARG4
- ARGP_ARG5
- ARGP_ARG6
- ARGP_BANK_FIELD_OP
- ARGP_BIT_AND_OP
- ARGP_BIT_NAND_OP
- ARGP_BIT_NOR_OP
- ARGP_BIT_NOT_OP
- ARGP_BIT_OR_OP
- ARGP_BIT_XOR_OP
- ARGP_BREAK_OP
- ARGP_BREAK_POINT_OP
- ARGP_BUFFER_OP
- ARGP_BYTEDATA
- ARGP_BYTELIST
- ARGP_BYTELIST_OP
- ARGP_BYTE_OP
- ARGP_CHARLIST
- ARGP_COMMENT
- ARGP_COMMENT_OP
- ARGP_CONCAT_OP
- ARGP_CONCAT_RES_OP
- ARGP_COND_REF_OF_OP
- ARGP_CONNECTFIELD_OP
- ARGP_CONTINUE_OP
- ARGP_COPY_OP
- ARGP_CREATE_BIT_FIELD_OP
- ARGP_CREATE_BYTE_FIELD_OP
- ARGP_CREATE_DWORD_FIELD_OP
- ARGP_CREATE_FIELD_OP
- ARGP_CREATE_QWORD_FIELD_OP
- ARGP_CREATE_WORD_FIELD_OP
- ARGP_DATAOBJ
- ARGP_DATAOBJLIST
- ARGP_DATA_REGION_OP
- ARGP_DEBUG_OP
- ARGP_DECREMENT_OP
- ARGP_DEREF_OF_OP
- ARGP_DEVICE_OP
- ARGP_DIVIDE_OP
- ARGP_DWORDDATA
- ARGP_DWORD_OP
- ARGP_ELSE_OP
- ARGP_EVENT_OP
- ARGP_EXTERNAL_OP
- ARGP_FATAL_OP
- ARGP_FIELDLIST
- ARGP_FIELD_OP
- ARGP_FIND_SET_LEFT_BIT_OP
- ARGP_FIND_SET_RIGHT_BIT_OP
- ARGP_FROM_BCD_OP
- ARGP_IF_OP
- ARGP_INCREMENT_OP
- ARGP_INDEX_FIELD_OP
- ARGP_INDEX_OP
- ARGP_LAND_OP
- ARGP_LEQUAL_OP
- ARGP_LGREATEREQUAL_OP
- ARGP_LGREATER_OP
- ARGP_LIST1
- ARGP_LIST2
- ARGP_LIST3
- ARGP_LIST4
- ARGP_LIST5
- ARGP_LIST6
- ARGP_LLESSEQUAL_OP
- ARGP_LLESS_OP
- ARGP_LNOTEQUAL_OP
- ARGP_LNOT_OP
- ARGP_LOAD_OP
- ARGP_LOAD_TABLE_OP
- ARGP_LOCAL0
- ARGP_LOCAL1
- ARGP_LOCAL2
- ARGP_LOCAL3
- ARGP_LOCAL4
- ARGP_LOCAL5
- ARGP_LOCAL6
- ARGP_LOCAL7
- ARGP_LOR_OP
- ARGP_MATCH_OP
- ARGP_MAX
- ARGP_METHODCALL_OP
- ARGP_METHOD_OP
- ARGP_MID_OP
- ARGP_MOD_OP
- ARGP_MULTIPLY_OP
- ARGP_MUTEX_OP
- ARGP_NAME
- ARGP_NAMEDFIELD_OP
- ARGP_NAMEPATH_OP
- ARGP_NAMESTRING
- ARGP_NAME_OP
- ARGP_NAME_OR_REF
- ARGP_NOOP_OP
- ARGP_NOTIFY_OP
- ARGP_OBJECT_TYPE_OP
- ARGP_OBJLIST
- ARGP_ONES_OP
- ARGP_ONE_OP
- ARGP_PACKAGE_OP
- ARGP_PKGLENGTH
- ARGP_POWER_RES_OP
- ARGP_PROCESSOR_OP
- ARGP_QWORDDATA
- ARGP_QWORD_OP
- ARGP_REF_OF_OP
- ARGP_REGION_OP
- ARGP_RELEASE_OP
- ARGP_RESERVEDFIELD_OP
- ARGP_RESET_OP
- ARGP_RETURN_OP
- ARGP_REVISION_OP
- ARGP_SCOPE_OP
- ARGP_SERIALFIELD_OP
- ARGP_SHIFT_LEFT_OP
- ARGP_SHIFT_RIGHT_OP
- ARGP_SIGNAL_OP
- ARGP_SIMPLENAME
- ARGP_SIZE_OF_OP
- ARGP_SLEEP_OP
- ARGP_STALL_OP
- ARGP_STATICSTRING_OP
- ARGP_STORE_OP
- ARGP_STRING_OP
- ARGP_SUBTRACT_OP
- ARGP_SUPERNAME
- ARGP_TARGET
- ARGP_TERMARG
- ARGP_TERMLIST
- ARGP_THERMAL_ZONE_OP
- ARGP_TIMER_OP
- ARGP_TO_BCD_OP
- ARGP_TO_BUFFER_OP
- ARGP_TO_DEC_STR_OP
- ARGP_TO_HEX_STR_OP
- ARGP_TO_INTEGER_OP
- ARGP_TO_STRING_OP
- ARGP_UNLOAD_OP
- ARGP_VAR_PACKAGE_OP
- ARGP_WAIT_OP
- ARGP_WHILE_OP
- ARGP_WORDDATA
- ARGP_WORD_OP
- ARGP_ZERO_OP
- ARGS
- ARGSTRING
- ARGTYPE
- ARG_1
- ARG_2
- ARG_3
- ARG_32
- ARG_4
- ARG_5
- ARG_6
- ARG_64
- ARG_ANYTHING
- ARG_COMPLETE
- ARG_CONN
- ARG_CONST_MAP_PTR
- ARG_CONST_SIZE
- ARG_CONST_SIZE_OR_ZERO
- ARG_COUNT_IS_MINIMUM
- ARG_DONTCARE
- ARG_FLAG_ARM
- ARG_FLAG_SUPPORTED
- ARG_FLAG_THUMB
- ARG_FLAG_UNSUPPORTED
- ARG_FOREVER
- ARG_KEYS
- ARG_MAX
- ARG_MESS_WITH_MSR_AT
- ARG_MESS_WITH_TM_AT
- ARG_MESS_WITH_TM_BEFORE
- ARG_NONE
- ARG_PTR_TO_CTX
- ARG_PTR_TO_INT
- ARG_PTR_TO_LONG
- ARG_PTR_TO_MAP_KEY
- ARG_PTR_TO_MAP_VALUE
- ARG_PTR_TO_MAP_VALUE_OR_NULL
- ARG_PTR_TO_MEM
- ARG_PTR_TO_MEM_OR_NULL
- ARG_PTR_TO_SOCKET
- ARG_PTR_TO_SOCK_COMMON
- ARG_PTR_TO_SPIN_LOCK
- ARG_PTR_TO_UNINIT_MAP_VALUE
- ARG_PTR_TO_UNINIT_MEM
- ARG_SEP
- ARG_TEST_NAME
- ARG_TEST_NUM
- ARG_TUPLE
- ARG_TYPE_END
- ARG_TYPE_MEM
- ARG_TYPE_PTR
- ARG_TYPE_REG
- ARG_TYPE_REG_MASKED
- ARG_TYPE_WIDTH
- ARG_VERBOSE
- ARG_VERIFIER_STATS
- ARIADNE_BOOTPROM
- ARIADNE_BOOTPROM_SIZE
- ARIADNE_LANCE
- ARIADNE_PIT
- ARIADNE_RAM
- ARIADNE_RAM_SIZE
- ARIES_TOUCHKEY_CMD_LED_OFF
- ARIES_TOUCHKEY_CMD_LED_ON
- ARITH
- ARITH_SHIFT
- ARITH_X
- ARIZONA_32KZ_MCLK1
- ARIZONA_32KZ_MCLK2
- ARIZONA_32KZ_NONE
- ARIZONA_44K1_RATE_MASK
- ARIZONA_48K_RATE_MASK
- ARIZONA_ACCDET_MODE_ADC
- ARIZONA_ACCDET_MODE_HPL
- ARIZONA_ACCDET_MODE_HPM
- ARIZONA_ACCDET_MODE_HPR
- ARIZONA_ACCDET_MODE_MASK
- ARIZONA_ACCDET_MODE_MIC
- ARIZONA_ACCDET_MODE_SHIFT
- ARIZONA_ACCDET_MODE_WIDTH
- ARIZONA_ACCDET_SRC
- ARIZONA_ACCDET_SRC_MASK
- ARIZONA_ACCDET_SRC_SHIFT
- ARIZONA_ACCDET_SRC_WIDTH
- ARIZONA_ACCESSORY_DETECT_MODE_1
- ARIZONA_ADC_DIGITAL_VOLUME_1L
- ARIZONA_ADC_DIGITAL_VOLUME_1R
- ARIZONA_ADC_DIGITAL_VOLUME_2L
- ARIZONA_ADC_DIGITAL_VOLUME_2R
- ARIZONA_ADC_DIGITAL_VOLUME_3L
- ARIZONA_ADC_DIGITAL_VOLUME_3R
- ARIZONA_ADC_DIGITAL_VOLUME_4L
- ARIZONA_ADC_DIGITAL_VOLUME_4R
- ARIZONA_ADC_OVERCLOCKED_STS
- ARIZONA_ADC_OVERCLOCKED_STS_MASK
- ARIZONA_ADC_OVERCLOCKED_STS_SHIFT
- ARIZONA_ADC_OVERCLOCKED_STS_WIDTH
- ARIZONA_ADC_UNDERCLOCKED_STS
- ARIZONA_ADC_UNDERCLOCKED_STS_MASK
- ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT
- ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH
- ARIZONA_ADDR_PD
- ARIZONA_ADDR_PD_MASK
- ARIZONA_ADDR_PD_SHIFT
- ARIZONA_ADDR_PD_WIDTH
- ARIZONA_ADSP2_1_OVERCLOCKED_STS
- ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK
- ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT
- ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH
- ARIZONA_ADSP2_IRQ0
- ARIZONA_AEC_COMP_COEFF_1
- ARIZONA_AEC_COMP_COEFF_1_MASK
- ARIZONA_AEC_COMP_COEFF_1_SHIFT
- ARIZONA_AEC_COMP_COEFF_1_WIDTH
- ARIZONA_AEC_COMP_COEFF_MASK
- ARIZONA_AEC_COMP_COEFF_SEL
- ARIZONA_AEC_COMP_COEFF_SEL_MASK
- ARIZONA_AEC_COMP_COEFF_SEL_SHIFT
- ARIZONA_AEC_COMP_COEFF_SEL_WIDTH
- ARIZONA_AEC_COMP_COEFF_SHIFT
- ARIZONA_AEC_COMP_COEFF_WIDTH
- ARIZONA_AEC_ENA_STS
- ARIZONA_AEC_ENA_STS_MASK
- ARIZONA_AEC_ENA_STS_SHIFT
- ARIZONA_AEC_ENA_STS_WIDTH
- ARIZONA_AEC_LOOPBACK_ENA
- ARIZONA_AEC_LOOPBACK_ENA_MASK
- ARIZONA_AEC_LOOPBACK_ENA_SHIFT
- ARIZONA_AEC_LOOPBACK_ENA_WIDTH
- ARIZONA_AEC_LOOPBACK_SRC_MASK
- ARIZONA_AEC_LOOPBACK_SRC_SHIFT
- ARIZONA_AEC_LOOPBACK_SRC_WIDTH
- ARIZONA_AIF1BCLK_PD
- ARIZONA_AIF1BCLK_PD_MASK
- ARIZONA_AIF1BCLK_PD_SHIFT
- ARIZONA_AIF1BCLK_PD_WIDTH
- ARIZONA_AIF1BCLK_PU
- ARIZONA_AIF1BCLK_PU_MASK
- ARIZONA_AIF1BCLK_PU_SHIFT
- ARIZONA_AIF1BCLK_PU_WIDTH
- ARIZONA_AIF1RX1_ENA
- ARIZONA_AIF1RX1_ENA_MASK
- ARIZONA_AIF1RX1_ENA_SHIFT
- ARIZONA_AIF1RX1_ENA_WIDTH
- ARIZONA_AIF1RX1_SLOT_MASK
- ARIZONA_AIF1RX1_SLOT_SHIFT
- ARIZONA_AIF1RX1_SLOT_WIDTH
- ARIZONA_AIF1RX2_ENA
- ARIZONA_AIF1RX2_ENA_MASK
- ARIZONA_AIF1RX2_ENA_SHIFT
- ARIZONA_AIF1RX2_ENA_WIDTH
- ARIZONA_AIF1RX2_SLOT_MASK
- ARIZONA_AIF1RX2_SLOT_SHIFT
- ARIZONA_AIF1RX2_SLOT_WIDTH
- ARIZONA_AIF1RX3_ENA
- ARIZONA_AIF1RX3_ENA_MASK
- ARIZONA_AIF1RX3_ENA_SHIFT
- ARIZONA_AIF1RX3_ENA_WIDTH
- ARIZONA_AIF1RX3_SLOT_MASK
- ARIZONA_AIF1RX3_SLOT_SHIFT
- ARIZONA_AIF1RX3_SLOT_WIDTH
- ARIZONA_AIF1RX4_ENA
- ARIZONA_AIF1RX4_ENA_MASK
- ARIZONA_AIF1RX4_ENA_SHIFT
- ARIZONA_AIF1RX4_ENA_WIDTH
- ARIZONA_AIF1RX4_SLOT_MASK
- ARIZONA_AIF1RX4_SLOT_SHIFT
- ARIZONA_AIF1RX4_SLOT_WIDTH
- ARIZONA_AIF1RX5_ENA
- ARIZONA_AIF1RX5_ENA_MASK
- ARIZONA_AIF1RX5_ENA_SHIFT
- ARIZONA_AIF1RX5_ENA_WIDTH
- ARIZONA_AIF1RX5_SLOT_MASK
- ARIZONA_AIF1RX5_SLOT_SHIFT
- ARIZONA_AIF1RX5_SLOT_WIDTH
- ARIZONA_AIF1RX6_ENA
- ARIZONA_AIF1RX6_ENA_MASK
- ARIZONA_AIF1RX6_ENA_SHIFT
- ARIZONA_AIF1RX6_ENA_WIDTH
- ARIZONA_AIF1RX6_SLOT_MASK
- ARIZONA_AIF1RX6_SLOT_SHIFT
- ARIZONA_AIF1RX6_SLOT_WIDTH
- ARIZONA_AIF1RX7_ENA
- ARIZONA_AIF1RX7_ENA_MASK
- ARIZONA_AIF1RX7_ENA_SHIFT
- ARIZONA_AIF1RX7_ENA_WIDTH
- ARIZONA_AIF1RX7_SLOT_MASK
- ARIZONA_AIF1RX7_SLOT_SHIFT
- ARIZONA_AIF1RX7_SLOT_WIDTH
- ARIZONA_AIF1RX8_ENA
- ARIZONA_AIF1RX8_ENA_MASK
- ARIZONA_AIF1RX8_ENA_SHIFT
- ARIZONA_AIF1RX8_ENA_WIDTH
- ARIZONA_AIF1RX8_SLOT_MASK
- ARIZONA_AIF1RX8_SLOT_SHIFT
- ARIZONA_AIF1RX8_SLOT_WIDTH
- ARIZONA_AIF1RXDAT_PD
- ARIZONA_AIF1RXDAT_PD_MASK
- ARIZONA_AIF1RXDAT_PD_SHIFT
- ARIZONA_AIF1RXDAT_PD_WIDTH
- ARIZONA_AIF1RXDAT_PU
- ARIZONA_AIF1RXDAT_PU_MASK
- ARIZONA_AIF1RXDAT_PU_SHIFT
- ARIZONA_AIF1RXDAT_PU_WIDTH
- ARIZONA_AIF1RXLRCLK_PD
- ARIZONA_AIF1RXLRCLK_PD_MASK
- ARIZONA_AIF1RXLRCLK_PD_SHIFT
- ARIZONA_AIF1RXLRCLK_PD_WIDTH
- ARIZONA_AIF1RXLRCLK_PU
- ARIZONA_AIF1RXLRCLK_PU_MASK
- ARIZONA_AIF1RXLRCLK_PU_SHIFT
- ARIZONA_AIF1RXLRCLK_PU_WIDTH
- ARIZONA_AIF1RX_BCPF_MASK
- ARIZONA_AIF1RX_BCPF_SHIFT
- ARIZONA_AIF1RX_BCPF_WIDTH
- ARIZONA_AIF1RX_LRCLK_FRC
- ARIZONA_AIF1RX_LRCLK_FRC_MASK
- ARIZONA_AIF1RX_LRCLK_FRC_SHIFT
- ARIZONA_AIF1RX_LRCLK_FRC_WIDTH
- ARIZONA_AIF1RX_LRCLK_INV
- ARIZONA_AIF1RX_LRCLK_INV_MASK
- ARIZONA_AIF1RX_LRCLK_INV_SHIFT
- ARIZONA_AIF1RX_LRCLK_INV_WIDTH
- ARIZONA_AIF1RX_LRCLK_MSTR
- ARIZONA_AIF1RX_LRCLK_MSTR_MASK
- ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF1RX_SLOT_LEN_MASK
- ARIZONA_AIF1RX_SLOT_LEN_SHIFT
- ARIZONA_AIF1RX_SLOT_LEN_WIDTH
- ARIZONA_AIF1RX_WL_MASK
- ARIZONA_AIF1RX_WL_SHIFT
- ARIZONA_AIF1RX_WL_WIDTH
- ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX1_ENA
- ARIZONA_AIF1TX1_ENA_MASK
- ARIZONA_AIF1TX1_ENA_SHIFT
- ARIZONA_AIF1TX1_ENA_WIDTH
- ARIZONA_AIF1TX1_SLOT_MASK
- ARIZONA_AIF1TX1_SLOT_SHIFT
- ARIZONA_AIF1TX1_SLOT_WIDTH
- ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX2_ENA
- ARIZONA_AIF1TX2_ENA_MASK
- ARIZONA_AIF1TX2_ENA_SHIFT
- ARIZONA_AIF1TX2_ENA_WIDTH
- ARIZONA_AIF1TX2_SLOT_MASK
- ARIZONA_AIF1TX2_SLOT_SHIFT
- ARIZONA_AIF1TX2_SLOT_WIDTH
- ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX3_ENA
- ARIZONA_AIF1TX3_ENA_MASK
- ARIZONA_AIF1TX3_ENA_SHIFT
- ARIZONA_AIF1TX3_ENA_WIDTH
- ARIZONA_AIF1TX3_SLOT_MASK
- ARIZONA_AIF1TX3_SLOT_SHIFT
- ARIZONA_AIF1TX3_SLOT_WIDTH
- ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX4_ENA
- ARIZONA_AIF1TX4_ENA_MASK
- ARIZONA_AIF1TX4_ENA_SHIFT
- ARIZONA_AIF1TX4_ENA_WIDTH
- ARIZONA_AIF1TX4_SLOT_MASK
- ARIZONA_AIF1TX4_SLOT_SHIFT
- ARIZONA_AIF1TX4_SLOT_WIDTH
- ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX5_ENA
- ARIZONA_AIF1TX5_ENA_MASK
- ARIZONA_AIF1TX5_ENA_SHIFT
- ARIZONA_AIF1TX5_ENA_WIDTH
- ARIZONA_AIF1TX5_SLOT_MASK
- ARIZONA_AIF1TX5_SLOT_SHIFT
- ARIZONA_AIF1TX5_SLOT_WIDTH
- ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX6_ENA
- ARIZONA_AIF1TX6_ENA_MASK
- ARIZONA_AIF1TX6_ENA_SHIFT
- ARIZONA_AIF1TX6_ENA_WIDTH
- ARIZONA_AIF1TX6_SLOT_MASK
- ARIZONA_AIF1TX6_SLOT_SHIFT
- ARIZONA_AIF1TX6_SLOT_WIDTH
- ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX7_ENA
- ARIZONA_AIF1TX7_ENA_MASK
- ARIZONA_AIF1TX7_ENA_SHIFT
- ARIZONA_AIF1TX7_ENA_WIDTH
- ARIZONA_AIF1TX7_SLOT_MASK
- ARIZONA_AIF1TX7_SLOT_SHIFT
- ARIZONA_AIF1TX7_SLOT_WIDTH
- ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE
- ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME
- ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE
- ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME
- ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE
- ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME
- ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE
- ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME
- ARIZONA_AIF1TX8_ENA
- ARIZONA_AIF1TX8_ENA_MASK
- ARIZONA_AIF1TX8_ENA_SHIFT
- ARIZONA_AIF1TX8_ENA_WIDTH
- ARIZONA_AIF1TX8_SLOT_MASK
- ARIZONA_AIF1TX8_SLOT_SHIFT
- ARIZONA_AIF1TX8_SLOT_WIDTH
- ARIZONA_AIF1TX_BCPF_MASK
- ARIZONA_AIF1TX_BCPF_SHIFT
- ARIZONA_AIF1TX_BCPF_WIDTH
- ARIZONA_AIF1TX_DAT_TRI
- ARIZONA_AIF1TX_DAT_TRI_MASK
- ARIZONA_AIF1TX_DAT_TRI_SHIFT
- ARIZONA_AIF1TX_DAT_TRI_WIDTH
- ARIZONA_AIF1TX_LRCLK_FRC
- ARIZONA_AIF1TX_LRCLK_FRC_MASK
- ARIZONA_AIF1TX_LRCLK_FRC_SHIFT
- ARIZONA_AIF1TX_LRCLK_FRC_WIDTH
- ARIZONA_AIF1TX_LRCLK_INV
- ARIZONA_AIF1TX_LRCLK_INV_MASK
- ARIZONA_AIF1TX_LRCLK_INV_SHIFT
- ARIZONA_AIF1TX_LRCLK_INV_WIDTH
- ARIZONA_AIF1TX_LRCLK_MSTR
- ARIZONA_AIF1TX_LRCLK_MSTR_MASK
- ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF1TX_LRCLK_SRC
- ARIZONA_AIF1TX_LRCLK_SRC_MASK
- ARIZONA_AIF1TX_LRCLK_SRC_SHIFT
- ARIZONA_AIF1TX_LRCLK_SRC_WIDTH
- ARIZONA_AIF1TX_SLOT_LEN_MASK
- ARIZONA_AIF1TX_SLOT_LEN_SHIFT
- ARIZONA_AIF1TX_SLOT_LEN_WIDTH
- ARIZONA_AIF1TX_WL_MASK
- ARIZONA_AIF1TX_WL_SHIFT
- ARIZONA_AIF1TX_WL_WIDTH
- ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS
- ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF1_BCLK_CTRL
- ARIZONA_AIF1_BCLK_FRC
- ARIZONA_AIF1_BCLK_FRC_MASK
- ARIZONA_AIF1_BCLK_FRC_SHIFT
- ARIZONA_AIF1_BCLK_FRC_WIDTH
- ARIZONA_AIF1_BCLK_FREQ_MASK
- ARIZONA_AIF1_BCLK_FREQ_SHIFT
- ARIZONA_AIF1_BCLK_FREQ_WIDTH
- ARIZONA_AIF1_BCLK_INV
- ARIZONA_AIF1_BCLK_INV_MASK
- ARIZONA_AIF1_BCLK_INV_SHIFT
- ARIZONA_AIF1_BCLK_INV_WIDTH
- ARIZONA_AIF1_BCLK_MSTR
- ARIZONA_AIF1_BCLK_MSTR_MASK
- ARIZONA_AIF1_BCLK_MSTR_SHIFT
- ARIZONA_AIF1_BCLK_MSTR_WIDTH
- ARIZONA_AIF1_ERR_EINT1
- ARIZONA_AIF1_ERR_EINT1_MASK
- ARIZONA_AIF1_ERR_EINT1_SHIFT
- ARIZONA_AIF1_ERR_EINT1_WIDTH
- ARIZONA_AIF1_ERR_EINT2
- ARIZONA_AIF1_ERR_EINT2_MASK
- ARIZONA_AIF1_ERR_EINT2_SHIFT
- ARIZONA_AIF1_ERR_EINT2_WIDTH
- ARIZONA_AIF1_ERR_STS
- ARIZONA_AIF1_ERR_STS_MASK
- ARIZONA_AIF1_ERR_STS_SHIFT
- ARIZONA_AIF1_ERR_STS_WIDTH
- ARIZONA_AIF1_FMT_MASK
- ARIZONA_AIF1_FMT_SHIFT
- ARIZONA_AIF1_FMT_WIDTH
- ARIZONA_AIF1_FORCE_WRITE
- ARIZONA_AIF1_FORMAT
- ARIZONA_AIF1_FRAME_CTRL_1
- ARIZONA_AIF1_FRAME_CTRL_10
- ARIZONA_AIF1_FRAME_CTRL_11
- ARIZONA_AIF1_FRAME_CTRL_12
- ARIZONA_AIF1_FRAME_CTRL_13
- ARIZONA_AIF1_FRAME_CTRL_14
- ARIZONA_AIF1_FRAME_CTRL_15
- ARIZONA_AIF1_FRAME_CTRL_16
- ARIZONA_AIF1_FRAME_CTRL_17
- ARIZONA_AIF1_FRAME_CTRL_18
- ARIZONA_AIF1_FRAME_CTRL_2
- ARIZONA_AIF1_FRAME_CTRL_3
- ARIZONA_AIF1_FRAME_CTRL_4
- ARIZONA_AIF1_FRAME_CTRL_5
- ARIZONA_AIF1_FRAME_CTRL_6
- ARIZONA_AIF1_FRAME_CTRL_7
- ARIZONA_AIF1_FRAME_CTRL_8
- ARIZONA_AIF1_FRAME_CTRL_9
- ARIZONA_AIF1_FRC_WR
- ARIZONA_AIF1_FRC_WR_MASK
- ARIZONA_AIF1_FRC_WR_SHIFT
- ARIZONA_AIF1_FRC_WR_WIDTH
- ARIZONA_AIF1_RATE_CTRL
- ARIZONA_AIF1_RATE_MASK
- ARIZONA_AIF1_RATE_SHIFT
- ARIZONA_AIF1_RATE_WIDTH
- ARIZONA_AIF1_RX_BCLK_RATE
- ARIZONA_AIF1_RX_ENABLES
- ARIZONA_AIF1_RX_PIN_CTRL
- ARIZONA_AIF1_SYNC_OVERCLOCKED_STS
- ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF1_TRI
- ARIZONA_AIF1_TRI_MASK
- ARIZONA_AIF1_TRI_SHIFT
- ARIZONA_AIF1_TRI_WIDTH
- ARIZONA_AIF1_TX_BCLK_RATE
- ARIZONA_AIF1_TX_ENABLES
- ARIZONA_AIF1_TX_PIN_CTRL
- ARIZONA_AIF1_UNDERCLOCKED_STS
- ARIZONA_AIF1_UNDERCLOCKED_STS_MASK
- ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT
- ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH
- ARIZONA_AIF2BCLK_PD
- ARIZONA_AIF2BCLK_PD_MASK
- ARIZONA_AIF2BCLK_PD_SHIFT
- ARIZONA_AIF2BCLK_PD_WIDTH
- ARIZONA_AIF2BCLK_PU
- ARIZONA_AIF2BCLK_PU_MASK
- ARIZONA_AIF2BCLK_PU_SHIFT
- ARIZONA_AIF2BCLK_PU_WIDTH
- ARIZONA_AIF2RX1_ENA
- ARIZONA_AIF2RX1_ENA_MASK
- ARIZONA_AIF2RX1_ENA_SHIFT
- ARIZONA_AIF2RX1_ENA_WIDTH
- ARIZONA_AIF2RX1_SLOT_MASK
- ARIZONA_AIF2RX1_SLOT_SHIFT
- ARIZONA_AIF2RX1_SLOT_WIDTH
- ARIZONA_AIF2RX2_ENA
- ARIZONA_AIF2RX2_ENA_MASK
- ARIZONA_AIF2RX2_ENA_SHIFT
- ARIZONA_AIF2RX2_ENA_WIDTH
- ARIZONA_AIF2RX2_SLOT_MASK
- ARIZONA_AIF2RX2_SLOT_SHIFT
- ARIZONA_AIF2RX2_SLOT_WIDTH
- ARIZONA_AIF2RX3_ENA
- ARIZONA_AIF2RX3_ENA_MASK
- ARIZONA_AIF2RX3_ENA_SHIFT
- ARIZONA_AIF2RX3_ENA_WIDTH
- ARIZONA_AIF2RX3_SLOT_MASK
- ARIZONA_AIF2RX3_SLOT_SHIFT
- ARIZONA_AIF2RX3_SLOT_WIDTH
- ARIZONA_AIF2RX4_ENA
- ARIZONA_AIF2RX4_ENA_MASK
- ARIZONA_AIF2RX4_ENA_SHIFT
- ARIZONA_AIF2RX4_ENA_WIDTH
- ARIZONA_AIF2RX4_SLOT_MASK
- ARIZONA_AIF2RX4_SLOT_SHIFT
- ARIZONA_AIF2RX4_SLOT_WIDTH
- ARIZONA_AIF2RX5_ENA
- ARIZONA_AIF2RX5_ENA_MASK
- ARIZONA_AIF2RX5_ENA_SHIFT
- ARIZONA_AIF2RX5_ENA_WIDTH
- ARIZONA_AIF2RX5_SLOT_MASK
- ARIZONA_AIF2RX5_SLOT_SHIFT
- ARIZONA_AIF2RX5_SLOT_WIDTH
- ARIZONA_AIF2RX6_ENA
- ARIZONA_AIF2RX6_ENA_MASK
- ARIZONA_AIF2RX6_ENA_SHIFT
- ARIZONA_AIF2RX6_ENA_WIDTH
- ARIZONA_AIF2RX6_SLOT_MASK
- ARIZONA_AIF2RX6_SLOT_SHIFT
- ARIZONA_AIF2RX6_SLOT_WIDTH
- ARIZONA_AIF2RXDAT_PD
- ARIZONA_AIF2RXDAT_PD_MASK
- ARIZONA_AIF2RXDAT_PD_SHIFT
- ARIZONA_AIF2RXDAT_PD_WIDTH
- ARIZONA_AIF2RXDAT_PU
- ARIZONA_AIF2RXDAT_PU_MASK
- ARIZONA_AIF2RXDAT_PU_SHIFT
- ARIZONA_AIF2RXDAT_PU_WIDTH
- ARIZONA_AIF2RXLRCLK_PD
- ARIZONA_AIF2RXLRCLK_PD_MASK
- ARIZONA_AIF2RXLRCLK_PD_SHIFT
- ARIZONA_AIF2RXLRCLK_PD_WIDTH
- ARIZONA_AIF2RXLRCLK_PU
- ARIZONA_AIF2RXLRCLK_PU_MASK
- ARIZONA_AIF2RXLRCLK_PU_SHIFT
- ARIZONA_AIF2RXLRCLK_PU_WIDTH
- ARIZONA_AIF2RX_BCPF_MASK
- ARIZONA_AIF2RX_BCPF_SHIFT
- ARIZONA_AIF2RX_BCPF_WIDTH
- ARIZONA_AIF2RX_LRCLK_FRC
- ARIZONA_AIF2RX_LRCLK_FRC_MASK
- ARIZONA_AIF2RX_LRCLK_FRC_SHIFT
- ARIZONA_AIF2RX_LRCLK_FRC_WIDTH
- ARIZONA_AIF2RX_LRCLK_INV
- ARIZONA_AIF2RX_LRCLK_INV_MASK
- ARIZONA_AIF2RX_LRCLK_INV_SHIFT
- ARIZONA_AIF2RX_LRCLK_INV_WIDTH
- ARIZONA_AIF2RX_LRCLK_MSTR
- ARIZONA_AIF2RX_LRCLK_MSTR_MASK
- ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF2RX_SLOT_LEN_MASK
- ARIZONA_AIF2RX_SLOT_LEN_SHIFT
- ARIZONA_AIF2RX_SLOT_LEN_WIDTH
- ARIZONA_AIF2RX_WL_MASK
- ARIZONA_AIF2RX_WL_SHIFT
- ARIZONA_AIF2RX_WL_WIDTH
- ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX1_ENA
- ARIZONA_AIF2TX1_ENA_MASK
- ARIZONA_AIF2TX1_ENA_SHIFT
- ARIZONA_AIF2TX1_ENA_WIDTH
- ARIZONA_AIF2TX1_SLOT_MASK
- ARIZONA_AIF2TX1_SLOT_SHIFT
- ARIZONA_AIF2TX1_SLOT_WIDTH
- ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX2_ENA
- ARIZONA_AIF2TX2_ENA_MASK
- ARIZONA_AIF2TX2_ENA_SHIFT
- ARIZONA_AIF2TX2_ENA_WIDTH
- ARIZONA_AIF2TX2_SLOT_MASK
- ARIZONA_AIF2TX2_SLOT_SHIFT
- ARIZONA_AIF2TX2_SLOT_WIDTH
- ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX3_ENA
- ARIZONA_AIF2TX3_ENA_MASK
- ARIZONA_AIF2TX3_ENA_SHIFT
- ARIZONA_AIF2TX3_ENA_WIDTH
- ARIZONA_AIF2TX3_SLOT_MASK
- ARIZONA_AIF2TX3_SLOT_SHIFT
- ARIZONA_AIF2TX3_SLOT_WIDTH
- ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX4_ENA
- ARIZONA_AIF2TX4_ENA_MASK
- ARIZONA_AIF2TX4_ENA_SHIFT
- ARIZONA_AIF2TX4_ENA_WIDTH
- ARIZONA_AIF2TX4_SLOT_MASK
- ARIZONA_AIF2TX4_SLOT_SHIFT
- ARIZONA_AIF2TX4_SLOT_WIDTH
- ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX5_ENA
- ARIZONA_AIF2TX5_ENA_MASK
- ARIZONA_AIF2TX5_ENA_SHIFT
- ARIZONA_AIF2TX5_ENA_WIDTH
- ARIZONA_AIF2TX5_SLOT_MASK
- ARIZONA_AIF2TX5_SLOT_SHIFT
- ARIZONA_AIF2TX5_SLOT_WIDTH
- ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE
- ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME
- ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE
- ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME
- ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE
- ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME
- ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE
- ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME
- ARIZONA_AIF2TX6_ENA
- ARIZONA_AIF2TX6_ENA_MASK
- ARIZONA_AIF2TX6_ENA_SHIFT
- ARIZONA_AIF2TX6_ENA_WIDTH
- ARIZONA_AIF2TX6_SLOT_MASK
- ARIZONA_AIF2TX6_SLOT_SHIFT
- ARIZONA_AIF2TX6_SLOT_WIDTH
- ARIZONA_AIF2TX_BCPF_MASK
- ARIZONA_AIF2TX_BCPF_SHIFT
- ARIZONA_AIF2TX_BCPF_WIDTH
- ARIZONA_AIF2TX_DAT_TRI
- ARIZONA_AIF2TX_DAT_TRI_MASK
- ARIZONA_AIF2TX_DAT_TRI_SHIFT
- ARIZONA_AIF2TX_DAT_TRI_WIDTH
- ARIZONA_AIF2TX_LRCLK_FRC
- ARIZONA_AIF2TX_LRCLK_FRC_MASK
- ARIZONA_AIF2TX_LRCLK_FRC_SHIFT
- ARIZONA_AIF2TX_LRCLK_FRC_WIDTH
- ARIZONA_AIF2TX_LRCLK_INV
- ARIZONA_AIF2TX_LRCLK_INV_MASK
- ARIZONA_AIF2TX_LRCLK_INV_SHIFT
- ARIZONA_AIF2TX_LRCLK_INV_WIDTH
- ARIZONA_AIF2TX_LRCLK_MSTR
- ARIZONA_AIF2TX_LRCLK_MSTR_MASK
- ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF2TX_LRCLK_SRC
- ARIZONA_AIF2TX_LRCLK_SRC_MASK
- ARIZONA_AIF2TX_LRCLK_SRC_SHIFT
- ARIZONA_AIF2TX_LRCLK_SRC_WIDTH
- ARIZONA_AIF2TX_SLOT_LEN_MASK
- ARIZONA_AIF2TX_SLOT_LEN_SHIFT
- ARIZONA_AIF2TX_SLOT_LEN_WIDTH
- ARIZONA_AIF2TX_WL_MASK
- ARIZONA_AIF2TX_WL_SHIFT
- ARIZONA_AIF2TX_WL_WIDTH
- ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS
- ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF2_BCLK_CTRL
- ARIZONA_AIF2_BCLK_FRC
- ARIZONA_AIF2_BCLK_FRC_MASK
- ARIZONA_AIF2_BCLK_FRC_SHIFT
- ARIZONA_AIF2_BCLK_FRC_WIDTH
- ARIZONA_AIF2_BCLK_FREQ_MASK
- ARIZONA_AIF2_BCLK_FREQ_SHIFT
- ARIZONA_AIF2_BCLK_FREQ_WIDTH
- ARIZONA_AIF2_BCLK_INV
- ARIZONA_AIF2_BCLK_INV_MASK
- ARIZONA_AIF2_BCLK_INV_SHIFT
- ARIZONA_AIF2_BCLK_INV_WIDTH
- ARIZONA_AIF2_BCLK_MSTR
- ARIZONA_AIF2_BCLK_MSTR_MASK
- ARIZONA_AIF2_BCLK_MSTR_SHIFT
- ARIZONA_AIF2_BCLK_MSTR_WIDTH
- ARIZONA_AIF2_ERR_EINT1
- ARIZONA_AIF2_ERR_EINT1_MASK
- ARIZONA_AIF2_ERR_EINT1_SHIFT
- ARIZONA_AIF2_ERR_EINT1_WIDTH
- ARIZONA_AIF2_ERR_EINT2
- ARIZONA_AIF2_ERR_EINT2_MASK
- ARIZONA_AIF2_ERR_EINT2_SHIFT
- ARIZONA_AIF2_ERR_EINT2_WIDTH
- ARIZONA_AIF2_ERR_STS
- ARIZONA_AIF2_ERR_STS_MASK
- ARIZONA_AIF2_ERR_STS_SHIFT
- ARIZONA_AIF2_ERR_STS_WIDTH
- ARIZONA_AIF2_FMT_MASK
- ARIZONA_AIF2_FMT_SHIFT
- ARIZONA_AIF2_FMT_WIDTH
- ARIZONA_AIF2_FORCE_WRITE
- ARIZONA_AIF2_FORMAT
- ARIZONA_AIF2_FRAME_CTRL_1
- ARIZONA_AIF2_FRAME_CTRL_11
- ARIZONA_AIF2_FRAME_CTRL_12
- ARIZONA_AIF2_FRAME_CTRL_13
- ARIZONA_AIF2_FRAME_CTRL_14
- ARIZONA_AIF2_FRAME_CTRL_15
- ARIZONA_AIF2_FRAME_CTRL_16
- ARIZONA_AIF2_FRAME_CTRL_2
- ARIZONA_AIF2_FRAME_CTRL_3
- ARIZONA_AIF2_FRAME_CTRL_4
- ARIZONA_AIF2_FRAME_CTRL_5
- ARIZONA_AIF2_FRAME_CTRL_6
- ARIZONA_AIF2_FRAME_CTRL_7
- ARIZONA_AIF2_FRAME_CTRL_8
- ARIZONA_AIF2_FRC_WR
- ARIZONA_AIF2_FRC_WR_MASK
- ARIZONA_AIF2_FRC_WR_SHIFT
- ARIZONA_AIF2_FRC_WR_WIDTH
- ARIZONA_AIF2_RATE_CTRL
- ARIZONA_AIF2_RATE_MASK
- ARIZONA_AIF2_RATE_SHIFT
- ARIZONA_AIF2_RATE_WIDTH
- ARIZONA_AIF2_RX_BCLK_RATE
- ARIZONA_AIF2_RX_ENABLES
- ARIZONA_AIF2_RX_PIN_CTRL
- ARIZONA_AIF2_SYNC_OVERCLOCKED_STS
- ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF2_TRI
- ARIZONA_AIF2_TRI_MASK
- ARIZONA_AIF2_TRI_SHIFT
- ARIZONA_AIF2_TRI_WIDTH
- ARIZONA_AIF2_TX_BCLK_RATE
- ARIZONA_AIF2_TX_ENABLES
- ARIZONA_AIF2_TX_PIN_CTRL
- ARIZONA_AIF2_UNDERCLOCKED_STS
- ARIZONA_AIF2_UNDERCLOCKED_STS_MASK
- ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT
- ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH
- ARIZONA_AIF3BCLK_PD
- ARIZONA_AIF3BCLK_PD_MASK
- ARIZONA_AIF3BCLK_PD_SHIFT
- ARIZONA_AIF3BCLK_PD_WIDTH
- ARIZONA_AIF3BCLK_PU
- ARIZONA_AIF3BCLK_PU_MASK
- ARIZONA_AIF3BCLK_PU_SHIFT
- ARIZONA_AIF3BCLK_PU_WIDTH
- ARIZONA_AIF3RX1_ENA
- ARIZONA_AIF3RX1_ENA_MASK
- ARIZONA_AIF3RX1_ENA_SHIFT
- ARIZONA_AIF3RX1_ENA_WIDTH
- ARIZONA_AIF3RX1_SLOT_MASK
- ARIZONA_AIF3RX1_SLOT_SHIFT
- ARIZONA_AIF3RX1_SLOT_WIDTH
- ARIZONA_AIF3RX2_ENA
- ARIZONA_AIF3RX2_ENA_MASK
- ARIZONA_AIF3RX2_ENA_SHIFT
- ARIZONA_AIF3RX2_ENA_WIDTH
- ARIZONA_AIF3RX2_SLOT_MASK
- ARIZONA_AIF3RX2_SLOT_SHIFT
- ARIZONA_AIF3RX2_SLOT_WIDTH
- ARIZONA_AIF3RXDAT_PD
- ARIZONA_AIF3RXDAT_PD_MASK
- ARIZONA_AIF3RXDAT_PD_SHIFT
- ARIZONA_AIF3RXDAT_PD_WIDTH
- ARIZONA_AIF3RXDAT_PU
- ARIZONA_AIF3RXDAT_PU_MASK
- ARIZONA_AIF3RXDAT_PU_SHIFT
- ARIZONA_AIF3RXDAT_PU_WIDTH
- ARIZONA_AIF3RXLRCLK_PD
- ARIZONA_AIF3RXLRCLK_PD_MASK
- ARIZONA_AIF3RXLRCLK_PD_SHIFT
- ARIZONA_AIF3RXLRCLK_PD_WIDTH
- ARIZONA_AIF3RXLRCLK_PU
- ARIZONA_AIF3RXLRCLK_PU_MASK
- ARIZONA_AIF3RXLRCLK_PU_SHIFT
- ARIZONA_AIF3RXLRCLK_PU_WIDTH
- ARIZONA_AIF3RX_BCPF_MASK
- ARIZONA_AIF3RX_BCPF_SHIFT
- ARIZONA_AIF3RX_BCPF_WIDTH
- ARIZONA_AIF3RX_LRCLK_FRC
- ARIZONA_AIF3RX_LRCLK_FRC_MASK
- ARIZONA_AIF3RX_LRCLK_FRC_SHIFT
- ARIZONA_AIF3RX_LRCLK_FRC_WIDTH
- ARIZONA_AIF3RX_LRCLK_INV
- ARIZONA_AIF3RX_LRCLK_INV_MASK
- ARIZONA_AIF3RX_LRCLK_INV_SHIFT
- ARIZONA_AIF3RX_LRCLK_INV_WIDTH
- ARIZONA_AIF3RX_LRCLK_MSTR
- ARIZONA_AIF3RX_LRCLK_MSTR_MASK
- ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF3RX_SLOT_LEN_MASK
- ARIZONA_AIF3RX_SLOT_LEN_SHIFT
- ARIZONA_AIF3RX_SLOT_LEN_WIDTH
- ARIZONA_AIF3RX_WL_MASK
- ARIZONA_AIF3RX_WL_SHIFT
- ARIZONA_AIF3RX_WL_WIDTH
- ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE
- ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME
- ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE
- ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME
- ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE
- ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME
- ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE
- ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME
- ARIZONA_AIF3TX1_ENA
- ARIZONA_AIF3TX1_ENA_MASK
- ARIZONA_AIF3TX1_ENA_SHIFT
- ARIZONA_AIF3TX1_ENA_WIDTH
- ARIZONA_AIF3TX1_SLOT_MASK
- ARIZONA_AIF3TX1_SLOT_SHIFT
- ARIZONA_AIF3TX1_SLOT_WIDTH
- ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE
- ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME
- ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE
- ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME
- ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE
- ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME
- ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE
- ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME
- ARIZONA_AIF3TX2_ENA
- ARIZONA_AIF3TX2_ENA_MASK
- ARIZONA_AIF3TX2_ENA_SHIFT
- ARIZONA_AIF3TX2_ENA_WIDTH
- ARIZONA_AIF3TX2_SLOT_MASK
- ARIZONA_AIF3TX2_SLOT_SHIFT
- ARIZONA_AIF3TX2_SLOT_WIDTH
- ARIZONA_AIF3TX_BCPF_MASK
- ARIZONA_AIF3TX_BCPF_SHIFT
- ARIZONA_AIF3TX_BCPF_WIDTH
- ARIZONA_AIF3TX_DAT_TRI
- ARIZONA_AIF3TX_DAT_TRI_MASK
- ARIZONA_AIF3TX_DAT_TRI_SHIFT
- ARIZONA_AIF3TX_DAT_TRI_WIDTH
- ARIZONA_AIF3TX_LRCLK_FRC
- ARIZONA_AIF3TX_LRCLK_FRC_MASK
- ARIZONA_AIF3TX_LRCLK_FRC_SHIFT
- ARIZONA_AIF3TX_LRCLK_FRC_WIDTH
- ARIZONA_AIF3TX_LRCLK_INV
- ARIZONA_AIF3TX_LRCLK_INV_MASK
- ARIZONA_AIF3TX_LRCLK_INV_SHIFT
- ARIZONA_AIF3TX_LRCLK_INV_WIDTH
- ARIZONA_AIF3TX_LRCLK_MSTR
- ARIZONA_AIF3TX_LRCLK_MSTR_MASK
- ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT
- ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH
- ARIZONA_AIF3TX_LRCLK_SRC
- ARIZONA_AIF3TX_LRCLK_SRC_MASK
- ARIZONA_AIF3TX_LRCLK_SRC_SHIFT
- ARIZONA_AIF3TX_LRCLK_SRC_WIDTH
- ARIZONA_AIF3TX_SLOT_LEN_MASK
- ARIZONA_AIF3TX_SLOT_LEN_SHIFT
- ARIZONA_AIF3TX_SLOT_LEN_WIDTH
- ARIZONA_AIF3TX_WL_MASK
- ARIZONA_AIF3TX_WL_SHIFT
- ARIZONA_AIF3TX_WL_WIDTH
- ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS
- ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF3_BCLK_CTRL
- ARIZONA_AIF3_BCLK_FRC
- ARIZONA_AIF3_BCLK_FRC_MASK
- ARIZONA_AIF3_BCLK_FRC_SHIFT
- ARIZONA_AIF3_BCLK_FRC_WIDTH
- ARIZONA_AIF3_BCLK_FREQ_MASK
- ARIZONA_AIF3_BCLK_FREQ_SHIFT
- ARIZONA_AIF3_BCLK_FREQ_WIDTH
- ARIZONA_AIF3_BCLK_INV
- ARIZONA_AIF3_BCLK_INV_MASK
- ARIZONA_AIF3_BCLK_INV_SHIFT
- ARIZONA_AIF3_BCLK_INV_WIDTH
- ARIZONA_AIF3_BCLK_MSTR
- ARIZONA_AIF3_BCLK_MSTR_MASK
- ARIZONA_AIF3_BCLK_MSTR_SHIFT
- ARIZONA_AIF3_BCLK_MSTR_WIDTH
- ARIZONA_AIF3_ERR_EINT1
- ARIZONA_AIF3_ERR_EINT1_MASK
- ARIZONA_AIF3_ERR_EINT1_SHIFT
- ARIZONA_AIF3_ERR_EINT1_WIDTH
- ARIZONA_AIF3_ERR_EINT2
- ARIZONA_AIF3_ERR_EINT2_MASK
- ARIZONA_AIF3_ERR_EINT2_SHIFT
- ARIZONA_AIF3_ERR_EINT2_WIDTH
- ARIZONA_AIF3_ERR_STS
- ARIZONA_AIF3_ERR_STS_MASK
- ARIZONA_AIF3_ERR_STS_SHIFT
- ARIZONA_AIF3_ERR_STS_WIDTH
- ARIZONA_AIF3_FMT_MASK
- ARIZONA_AIF3_FMT_SHIFT
- ARIZONA_AIF3_FMT_WIDTH
- ARIZONA_AIF3_FORCE_WRITE
- ARIZONA_AIF3_FORMAT
- ARIZONA_AIF3_FRAME_CTRL_1
- ARIZONA_AIF3_FRAME_CTRL_11
- ARIZONA_AIF3_FRAME_CTRL_12
- ARIZONA_AIF3_FRAME_CTRL_2
- ARIZONA_AIF3_FRAME_CTRL_3
- ARIZONA_AIF3_FRAME_CTRL_4
- ARIZONA_AIF3_FRC_WR
- ARIZONA_AIF3_FRC_WR_MASK
- ARIZONA_AIF3_FRC_WR_SHIFT
- ARIZONA_AIF3_FRC_WR_WIDTH
- ARIZONA_AIF3_RATE_CTRL
- ARIZONA_AIF3_RATE_MASK
- ARIZONA_AIF3_RATE_SHIFT
- ARIZONA_AIF3_RATE_WIDTH
- ARIZONA_AIF3_RX_BCLK_RATE
- ARIZONA_AIF3_RX_ENABLES
- ARIZONA_AIF3_RX_PIN_CTRL
- ARIZONA_AIF3_SYNC_OVERCLOCKED_STS
- ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK
- ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_AIF3_TRI
- ARIZONA_AIF3_TRI_MASK
- ARIZONA_AIF3_TRI_SHIFT
- ARIZONA_AIF3_TRI_WIDTH
- ARIZONA_AIF3_TX_BCLK_RATE
- ARIZONA_AIF3_TX_ENABLES
- ARIZONA_AIF3_TX_PIN_CTRL
- ARIZONA_AIF3_UNDERCLOCKED_STS
- ARIZONA_AIF3_UNDERCLOCKED_STS_MASK
- ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT
- ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH
- ARIZONA_AIF_BCLK_CTRL
- ARIZONA_AIF_FORCE_WRITE
- ARIZONA_AIF_FORMAT
- ARIZONA_AIF_FRAME_CTRL_1
- ARIZONA_AIF_FRAME_CTRL_10
- ARIZONA_AIF_FRAME_CTRL_11
- ARIZONA_AIF_FRAME_CTRL_12
- ARIZONA_AIF_FRAME_CTRL_13
- ARIZONA_AIF_FRAME_CTRL_14
- ARIZONA_AIF_FRAME_CTRL_15
- ARIZONA_AIF_FRAME_CTRL_16
- ARIZONA_AIF_FRAME_CTRL_17
- ARIZONA_AIF_FRAME_CTRL_18
- ARIZONA_AIF_FRAME_CTRL_2
- ARIZONA_AIF_FRAME_CTRL_3
- ARIZONA_AIF_FRAME_CTRL_4
- ARIZONA_AIF_FRAME_CTRL_5
- ARIZONA_AIF_FRAME_CTRL_6
- ARIZONA_AIF_FRAME_CTRL_7
- ARIZONA_AIF_FRAME_CTRL_8
- ARIZONA_AIF_FRAME_CTRL_9
- ARIZONA_AIF_RATE_CTRL
- ARIZONA_AIF_RX_BCLK_RATE
- ARIZONA_AIF_RX_ENABLES
- ARIZONA_AIF_RX_PIN_CTRL
- ARIZONA_AIF_TX_BCLK_RATE
- ARIZONA_AIF_TX_ENABLES
- ARIZONA_AIF_TX_PIN_CTRL
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7
- ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8
- ARIZONA_ANC_COEFF_END
- ARIZONA_ANC_COEFF_START
- ARIZONA_ANC_SRC
- ARIZONA_AOD_IRQ1
- ARIZONA_AOD_IRQ2
- ARIZONA_AOD_IRQ_INDEX
- ARIZONA_AOD_IRQ_MASK_IRQ1
- ARIZONA_AOD_IRQ_MASK_IRQ2
- ARIZONA_AOD_IRQ_RAW_STATUS
- ARIZONA_AOD_WKUP_AND_TRIG
- ARIZONA_ASRC1LMIX_INPUT_1_SOURCE
- ARIZONA_ASRC1L_ENA
- ARIZONA_ASRC1L_ENA_MASK
- ARIZONA_ASRC1L_ENA_SHIFT
- ARIZONA_ASRC1L_ENA_WIDTH
- ARIZONA_ASRC1RMIX_INPUT_1_SOURCE
- ARIZONA_ASRC1R_ENA
- ARIZONA_ASRC1R_ENA_MASK
- ARIZONA_ASRC1R_ENA_SHIFT
- ARIZONA_ASRC1R_ENA_WIDTH
- ARIZONA_ASRC1_LOCK_EINT1
- ARIZONA_ASRC1_LOCK_EINT1_MASK
- ARIZONA_ASRC1_LOCK_EINT1_SHIFT
- ARIZONA_ASRC1_LOCK_EINT1_WIDTH
- ARIZONA_ASRC1_LOCK_EINT2
- ARIZONA_ASRC1_LOCK_EINT2_MASK
- ARIZONA_ASRC1_LOCK_EINT2_SHIFT
- ARIZONA_ASRC1_LOCK_EINT2_WIDTH
- ARIZONA_ASRC1_LOCK_STS
- ARIZONA_ASRC1_LOCK_STS_MASK
- ARIZONA_ASRC1_LOCK_STS_SHIFT
- ARIZONA_ASRC1_LOCK_STS_WIDTH
- ARIZONA_ASRC2LMIX_INPUT_1_SOURCE
- ARIZONA_ASRC2L_ENA
- ARIZONA_ASRC2L_ENA_MASK
- ARIZONA_ASRC2L_ENA_SHIFT
- ARIZONA_ASRC2L_ENA_WIDTH
- ARIZONA_ASRC2RMIX_INPUT_1_SOURCE
- ARIZONA_ASRC2R_ENA
- ARIZONA_ASRC2R_ENA_MASK
- ARIZONA_ASRC2R_ENA_SHIFT
- ARIZONA_ASRC2R_ENA_WIDTH
- ARIZONA_ASRC2_LOCK_EINT1
- ARIZONA_ASRC2_LOCK_EINT1_MASK
- ARIZONA_ASRC2_LOCK_EINT1_SHIFT
- ARIZONA_ASRC2_LOCK_EINT1_WIDTH
- ARIZONA_ASRC2_LOCK_EINT2
- ARIZONA_ASRC2_LOCK_EINT2_MASK
- ARIZONA_ASRC2_LOCK_EINT2_SHIFT
- ARIZONA_ASRC2_LOCK_EINT2_WIDTH
- ARIZONA_ASRC2_LOCK_STS
- ARIZONA_ASRC2_LOCK_STS_MASK
- ARIZONA_ASRC2_LOCK_STS_SHIFT
- ARIZONA_ASRC2_LOCK_STS_WIDTH
- ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS
- ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK
- ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT
- ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH
- ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS
- ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK
- ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT
- ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH
- ARIZONA_ASRC_CFG_ERR_EINT1
- ARIZONA_ASRC_CFG_ERR_EINT1_MASK
- ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT
- ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH
- ARIZONA_ASRC_CFG_ERR_EINT2
- ARIZONA_ASRC_CFG_ERR_EINT2_MASK
- ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT
- ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH
- ARIZONA_ASRC_CFG_ERR_STS
- ARIZONA_ASRC_CFG_ERR_STS_MASK
- ARIZONA_ASRC_CFG_ERR_STS_SHIFT
- ARIZONA_ASRC_CFG_ERR_STS_WIDTH
- ARIZONA_ASRC_ENABLE
- ARIZONA_ASRC_RATE1
- ARIZONA_ASRC_RATE1_MASK
- ARIZONA_ASRC_RATE1_SHIFT
- ARIZONA_ASRC_RATE1_WIDTH
- ARIZONA_ASRC_RATE2
- ARIZONA_ASRC_RATE2_MASK
- ARIZONA_ASRC_RATE2_SHIFT
- ARIZONA_ASRC_RATE2_WIDTH
- ARIZONA_ASRC_STATUS
- ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS
- ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK
- ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT
- ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH
- ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS
- ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK
- ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT
- ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH
- ARIZONA_ASRC_UNDERCLOCKED_STS
- ARIZONA_ASRC_UNDERCLOCKED_STS_MASK
- ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT
- ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH
- ARIZONA_ASYNC_CLK_ENA
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT2
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_ASYNC_CLK_ENA_LOW_STS
- ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK
- ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT
- ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH
- ARIZONA_ASYNC_CLK_ENA_MASK
- ARIZONA_ASYNC_CLK_ENA_SHIFT
- ARIZONA_ASYNC_CLK_ENA_WIDTH
- ARIZONA_ASYNC_CLK_FREQ_MASK
- ARIZONA_ASYNC_CLK_FREQ_SHIFT
- ARIZONA_ASYNC_CLK_FREQ_WIDTH
- ARIZONA_ASYNC_CLK_SRC_MASK
- ARIZONA_ASYNC_CLK_SRC_SHIFT
- ARIZONA_ASYNC_CLK_SRC_WIDTH
- ARIZONA_ASYNC_CLOCK_1
- ARIZONA_ASYNC_SAMPLE_RATE_1
- ARIZONA_ASYNC_SAMPLE_RATE_1_MASK
- ARIZONA_ASYNC_SAMPLE_RATE_1_SHIFT
- ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS
- ARIZONA_ASYNC_SAMPLE_RATE_1_STS_MASK
- ARIZONA_ASYNC_SAMPLE_RATE_1_STS_SHIFT
- ARIZONA_ASYNC_SAMPLE_RATE_1_STS_WIDTH
- ARIZONA_ASYNC_SAMPLE_RATE_1_WIDTH
- ARIZONA_ASYNC_SAMPLE_RATE_2
- ARIZONA_ASYNC_SAMPLE_RATE_2_MASK
- ARIZONA_ASYNC_SAMPLE_RATE_2_SHIFT
- ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS
- ARIZONA_ASYNC_SAMPLE_RATE_2_STS_MASK
- ARIZONA_ASYNC_SAMPLE_RATE_2_STS_SHIFT
- ARIZONA_ASYNC_SAMPLE_RATE_2_STS_WIDTH
- ARIZONA_ASYNC_SAMPLE_RATE_2_WIDTH
- ARIZONA_BOOT_DONE_EINT1
- ARIZONA_BOOT_DONE_EINT1_MASK
- ARIZONA_BOOT_DONE_EINT1_SHIFT
- ARIZONA_BOOT_DONE_EINT1_WIDTH
- ARIZONA_BOOT_DONE_EINT2
- ARIZONA_BOOT_DONE_EINT2_MASK
- ARIZONA_BOOT_DONE_EINT2_SHIFT
- ARIZONA_BOOT_DONE_EINT2_WIDTH
- ARIZONA_BOOT_DONE_STS
- ARIZONA_BOOT_DONE_STS_MASK
- ARIZONA_BOOT_DONE_STS_SHIFT
- ARIZONA_BOOT_DONE_STS_WIDTH
- ARIZONA_CLKGEN_ERR_ASYNC_EINT1
- ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK
- ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT
- ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH
- ARIZONA_CLKGEN_ERR_ASYNC_EINT2
- ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK
- ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT
- ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH
- ARIZONA_CLKGEN_ERR_ASYNC_STS
- ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK
- ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT
- ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH
- ARIZONA_CLKGEN_ERR_EINT1
- ARIZONA_CLKGEN_ERR_EINT1_MASK
- ARIZONA_CLKGEN_ERR_EINT1_SHIFT
- ARIZONA_CLKGEN_ERR_EINT1_WIDTH
- ARIZONA_CLKGEN_ERR_EINT2
- ARIZONA_CLKGEN_ERR_EINT2_MASK
- ARIZONA_CLKGEN_ERR_EINT2_SHIFT
- ARIZONA_CLKGEN_ERR_EINT2_WIDTH
- ARIZONA_CLKGEN_ERR_STS
- ARIZONA_CLKGEN_ERR_STS_MASK
- ARIZONA_CLKGEN_ERR_STS_SHIFT
- ARIZONA_CLKGEN_ERR_STS_WIDTH
- ARIZONA_CLK_12MHZ
- ARIZONA_CLK_147MHZ
- ARIZONA_CLK_24MHZ
- ARIZONA_CLK_32K_ENA
- ARIZONA_CLK_32K_ENA_MASK
- ARIZONA_CLK_32K_ENA_SHIFT
- ARIZONA_CLK_32K_ENA_WIDTH
- ARIZONA_CLK_32K_SRC_MASK
- ARIZONA_CLK_32K_SRC_SHIFT
- ARIZONA_CLK_32K_SRC_WIDTH
- ARIZONA_CLK_49MHZ
- ARIZONA_CLK_6MHZ
- ARIZONA_CLK_73MHZ
- ARIZONA_CLK_98MHZ
- ARIZONA_CLK_ASYNCCLK
- ARIZONA_CLK_ASYNC_OPCLK
- ARIZONA_CLK_L_ENA_CLR
- ARIZONA_CLK_L_ENA_CLR_MASK
- ARIZONA_CLK_L_ENA_CLR_SHIFT
- ARIZONA_CLK_L_ENA_CLR_WIDTH
- ARIZONA_CLK_L_ENA_SET
- ARIZONA_CLK_L_ENA_SET_MASK
- ARIZONA_CLK_L_ENA_SET_SHIFT
- ARIZONA_CLK_L_ENA_SET_WIDTH
- ARIZONA_CLK_NG_ENA_CLR
- ARIZONA_CLK_NG_ENA_CLR_MASK
- ARIZONA_CLK_NG_ENA_CLR_SHIFT
- ARIZONA_CLK_NG_ENA_CLR_WIDTH
- ARIZONA_CLK_NG_ENA_SET
- ARIZONA_CLK_NG_ENA_SET_MASK
- ARIZONA_CLK_NG_ENA_SET_SHIFT
- ARIZONA_CLK_NG_ENA_SET_WIDTH
- ARIZONA_CLK_OPCLK
- ARIZONA_CLK_R_ENA_CLR
- ARIZONA_CLK_R_ENA_CLR_MASK
- ARIZONA_CLK_R_ENA_CLR_SHIFT
- ARIZONA_CLK_R_ENA_CLR_WIDTH
- ARIZONA_CLK_R_ENA_SET
- ARIZONA_CLK_R_ENA_SET_MASK
- ARIZONA_CLK_R_ENA_SET_SHIFT
- ARIZONA_CLK_R_ENA_SET_WIDTH
- ARIZONA_CLK_SRC_AIF1BCLK
- ARIZONA_CLK_SRC_AIF2BCLK
- ARIZONA_CLK_SRC_AIF3BCLK
- ARIZONA_CLK_SRC_FLL1
- ARIZONA_CLK_SRC_FLL2
- ARIZONA_CLK_SRC_MCLK1
- ARIZONA_CLK_SRC_MCLK2
- ARIZONA_CLK_SYSCLK
- ARIZONA_CLOCK_32K_1
- ARIZONA_CLOCK_CONTROL
- ARIZONA_COMFORT_NOISE_GENERATOR
- ARIZONA_CPMIC_BYPASS
- ARIZONA_CPMIC_BYPASS_MASK
- ARIZONA_CPMIC_BYPASS_SHIFT
- ARIZONA_CPMIC_BYPASS_WIDTH
- ARIZONA_CPMIC_DISCH
- ARIZONA_CPMIC_DISCH_MASK
- ARIZONA_CPMIC_DISCH_SHIFT
- ARIZONA_CPMIC_DISCH_WIDTH
- ARIZONA_CPMIC_ENA
- ARIZONA_CPMIC_ENA_MASK
- ARIZONA_CPMIC_ENA_SHIFT
- ARIZONA_CPMIC_ENA_WIDTH
- ARIZONA_CTRLIF_ERR_EINT1
- ARIZONA_CTRLIF_ERR_EINT1_MASK
- ARIZONA_CTRLIF_ERR_EINT1_SHIFT
- ARIZONA_CTRLIF_ERR_EINT1_WIDTH
- ARIZONA_CTRLIF_ERR_EINT2
- ARIZONA_CTRLIF_ERR_EINT2_MASK
- ARIZONA_CTRLIF_ERR_EINT2_SHIFT
- ARIZONA_CTRLIF_ERR_EINT2_WIDTH
- ARIZONA_CTRLIF_ERR_STS
- ARIZONA_CTRLIF_ERR_STS_MASK
- ARIZONA_CTRLIF_ERR_STS_SHIFT
- ARIZONA_CTRLIF_ERR_STS_WIDTH
- ARIZONA_CTRL_IF_I2C1_CFG_1
- ARIZONA_CTRL_IF_I2C1_CFG_2
- ARIZONA_CTRL_IF_I2C2_CFG_1
- ARIZONA_CTRL_IF_I2C2_CFG_2
- ARIZONA_CTRL_IF_SPI_CFG_1
- ARIZONA_CTRL_IF_STATUS_1
- ARIZONA_DAC_AEC_CONTROL_1
- ARIZONA_DAC_AEC_CONTROL_2
- ARIZONA_DAC_COMP_1
- ARIZONA_DAC_COMP_2
- ARIZONA_DAC_COMP_3
- ARIZONA_DAC_COMP_4
- ARIZONA_DAC_DIGITAL_VOLUME_1L
- ARIZONA_DAC_DIGITAL_VOLUME_1R
- ARIZONA_DAC_DIGITAL_VOLUME_2L
- ARIZONA_DAC_DIGITAL_VOLUME_2R
- ARIZONA_DAC_DIGITAL_VOLUME_3L
- ARIZONA_DAC_DIGITAL_VOLUME_3R
- ARIZONA_DAC_DIGITAL_VOLUME_4L
- ARIZONA_DAC_DIGITAL_VOLUME_4R
- ARIZONA_DAC_DIGITAL_VOLUME_5L
- ARIZONA_DAC_DIGITAL_VOLUME_5R
- ARIZONA_DAC_DIGITAL_VOLUME_6L
- ARIZONA_DAC_DIGITAL_VOLUME_6R
- ARIZONA_DAC_SYS_OVERCLOCKED_STS
- ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK
- ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT
- ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH
- ARIZONA_DAC_UNDERCLOCKED_STS
- ARIZONA_DAC_UNDERCLOCKED_STS_MASK
- ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT
- ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH
- ARIZONA_DAC_VOLUME_LIMIT_1L
- ARIZONA_DAC_VOLUME_LIMIT_1R
- ARIZONA_DAC_VOLUME_LIMIT_2L
- ARIZONA_DAC_VOLUME_LIMIT_2R
- ARIZONA_DAC_VOLUME_LIMIT_3L
- ARIZONA_DAC_VOLUME_LIMIT_3R
- ARIZONA_DAC_VOLUME_LIMIT_5L
- ARIZONA_DAC_VOLUME_LIMIT_5R
- ARIZONA_DAC_VOLUME_LIMIT_6L
- ARIZONA_DAC_VOLUME_LIMIT_6R
- ARIZONA_DAC_WARP_OVERCLOCKED_STS
- ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK
- ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT
- ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH
- ARIZONA_DCS_DAC_DONE_EINT1
- ARIZONA_DCS_DAC_DONE_EINT1_MASK
- ARIZONA_DCS_DAC_DONE_EINT1_SHIFT
- ARIZONA_DCS_DAC_DONE_EINT1_WIDTH
- ARIZONA_DCS_DAC_DONE_EINT2
- ARIZONA_DCS_DAC_DONE_EINT2_MASK
- ARIZONA_DCS_DAC_DONE_EINT2_SHIFT
- ARIZONA_DCS_DAC_DONE_EINT2_WIDTH
- ARIZONA_DCS_DAC_DONE_STS
- ARIZONA_DCS_DAC_DONE_STS_MASK
- ARIZONA_DCS_DAC_DONE_STS_SHIFT
- ARIZONA_DCS_DAC_DONE_STS_WIDTH
- ARIZONA_DCS_HP_DONE_EINT1
- ARIZONA_DCS_HP_DONE_EINT1_MASK
- ARIZONA_DCS_HP_DONE_EINT1_SHIFT
- ARIZONA_DCS_HP_DONE_EINT1_WIDTH
- ARIZONA_DCS_HP_DONE_EINT2
- ARIZONA_DCS_HP_DONE_EINT2_MASK
- ARIZONA_DCS_HP_DONE_EINT2_SHIFT
- ARIZONA_DCS_HP_DONE_EINT2_WIDTH
- ARIZONA_DCS_HP_DONE_STS
- ARIZONA_DCS_HP_DONE_STS_MASK
- ARIZONA_DCS_HP_DONE_STS_SHIFT
- ARIZONA_DCS_HP_DONE_STS_WIDTH
- ARIZONA_DEVICE_REVISION
- ARIZONA_DEVICE_REVISION_MASK
- ARIZONA_DEVICE_REVISION_SHIFT
- ARIZONA_DEVICE_REVISION_WIDTH
- ARIZONA_DMIC1L_CONTROL
- ARIZONA_DMIC1R_CONTROL
- ARIZONA_DMIC2L_CONTROL
- ARIZONA_DMIC2R_CONTROL
- ARIZONA_DMIC3L_CONTROL
- ARIZONA_DMIC3R_CONTROL
- ARIZONA_DMIC4L_CONTROL
- ARIZONA_DMIC4R_CONTROL
- ARIZONA_DMICDAT1_PD
- ARIZONA_DMICDAT1_PD_MASK
- ARIZONA_DMICDAT1_PD_SHIFT
- ARIZONA_DMICDAT1_PD_WIDTH
- ARIZONA_DMICDAT2_PD
- ARIZONA_DMICDAT2_PD_MASK
- ARIZONA_DMICDAT2_PD_SHIFT
- ARIZONA_DMICDAT2_PD_WIDTH
- ARIZONA_DMICDAT3_PD
- ARIZONA_DMICDAT3_PD_MASK
- ARIZONA_DMICDAT3_PD_SHIFT
- ARIZONA_DMICDAT3_PD_WIDTH
- ARIZONA_DMICDAT4_PD
- ARIZONA_DMICDAT4_PD_MASK
- ARIZONA_DMICDAT4_PD_SHIFT
- ARIZONA_DMICDAT4_PD_WIDTH
- ARIZONA_DMIC_MICBIAS1
- ARIZONA_DMIC_MICBIAS2
- ARIZONA_DMIC_MICBIAS3
- ARIZONA_DMIC_MICVDD
- ARIZONA_DRC1LMIX_INPUT_1_SOURCE
- ARIZONA_DRC1LMIX_INPUT_1_VOLUME
- ARIZONA_DRC1LMIX_INPUT_2_SOURCE
- ARIZONA_DRC1LMIX_INPUT_2_VOLUME
- ARIZONA_DRC1LMIX_INPUT_3_SOURCE
- ARIZONA_DRC1LMIX_INPUT_3_VOLUME
- ARIZONA_DRC1LMIX_INPUT_4_SOURCE
- ARIZONA_DRC1LMIX_INPUT_4_VOLUME
- ARIZONA_DRC1L_ENA
- ARIZONA_DRC1L_ENA_MASK
- ARIZONA_DRC1L_ENA_SHIFT
- ARIZONA_DRC1L_ENA_WIDTH
- ARIZONA_DRC1RMIX_INPUT_1_SOURCE
- ARIZONA_DRC1RMIX_INPUT_1_VOLUME
- ARIZONA_DRC1RMIX_INPUT_2_SOURCE
- ARIZONA_DRC1RMIX_INPUT_2_VOLUME
- ARIZONA_DRC1RMIX_INPUT_3_SOURCE
- ARIZONA_DRC1RMIX_INPUT_3_VOLUME
- ARIZONA_DRC1RMIX_INPUT_4_SOURCE
- ARIZONA_DRC1RMIX_INPUT_4_VOLUME
- ARIZONA_DRC1R_ENA
- ARIZONA_DRC1R_ENA_MASK
- ARIZONA_DRC1R_ENA_SHIFT
- ARIZONA_DRC1R_ENA_WIDTH
- ARIZONA_DRC1_ANTICLIP
- ARIZONA_DRC1_ANTICLIP_MASK
- ARIZONA_DRC1_ANTICLIP_SHIFT
- ARIZONA_DRC1_ANTICLIP_WIDTH
- ARIZONA_DRC1_ATK_MASK
- ARIZONA_DRC1_ATK_SHIFT
- ARIZONA_DRC1_ATK_WIDTH
- ARIZONA_DRC1_CTRL1
- ARIZONA_DRC1_CTRL2
- ARIZONA_DRC1_CTRL3
- ARIZONA_DRC1_CTRL4
- ARIZONA_DRC1_CTRL5
- ARIZONA_DRC1_DCY_MASK
- ARIZONA_DRC1_DCY_SHIFT
- ARIZONA_DRC1_DCY_WIDTH
- ARIZONA_DRC1_HI_COMP_MASK
- ARIZONA_DRC1_HI_COMP_SHIFT
- ARIZONA_DRC1_HI_COMP_WIDTH
- ARIZONA_DRC1_KNEE2_IP_MASK
- ARIZONA_DRC1_KNEE2_IP_SHIFT
- ARIZONA_DRC1_KNEE2_IP_WIDTH
- ARIZONA_DRC1_KNEE2_OP_ENA
- ARIZONA_DRC1_KNEE2_OP_ENA_MASK
- ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT
- ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH
- ARIZONA_DRC1_KNEE2_OP_MASK
- ARIZONA_DRC1_KNEE2_OP_SHIFT
- ARIZONA_DRC1_KNEE2_OP_WIDTH
- ARIZONA_DRC1_KNEE_IP_MASK
- ARIZONA_DRC1_KNEE_IP_SHIFT
- ARIZONA_DRC1_KNEE_IP_WIDTH
- ARIZONA_DRC1_KNEE_OP_MASK
- ARIZONA_DRC1_KNEE_OP_SHIFT
- ARIZONA_DRC1_KNEE_OP_WIDTH
- ARIZONA_DRC1_LO_COMP_MASK
- ARIZONA_DRC1_LO_COMP_SHIFT
- ARIZONA_DRC1_LO_COMP_WIDTH
- ARIZONA_DRC1_MAXGAIN_MASK
- ARIZONA_DRC1_MAXGAIN_SHIFT
- ARIZONA_DRC1_MAXGAIN_WIDTH
- ARIZONA_DRC1_MINGAIN_MASK
- ARIZONA_DRC1_MINGAIN_SHIFT
- ARIZONA_DRC1_MINGAIN_WIDTH
- ARIZONA_DRC1_NG_ENA
- ARIZONA_DRC1_NG_ENA_MASK
- ARIZONA_DRC1_NG_ENA_SHIFT
- ARIZONA_DRC1_NG_ENA_WIDTH
- ARIZONA_DRC1_NG_EXP_MASK
- ARIZONA_DRC1_NG_EXP_SHIFT
- ARIZONA_DRC1_NG_EXP_WIDTH
- ARIZONA_DRC1_NG_MINGAIN_MASK
- ARIZONA_DRC1_NG_MINGAIN_SHIFT
- ARIZONA_DRC1_NG_MINGAIN_WIDTH
- ARIZONA_DRC1_QR
- ARIZONA_DRC1_QR_DCY_MASK
- ARIZONA_DRC1_QR_DCY_SHIFT
- ARIZONA_DRC1_QR_DCY_WIDTH
- ARIZONA_DRC1_QR_MASK
- ARIZONA_DRC1_QR_SHIFT
- ARIZONA_DRC1_QR_THR_MASK
- ARIZONA_DRC1_QR_THR_SHIFT
- ARIZONA_DRC1_QR_THR_WIDTH
- ARIZONA_DRC1_QR_WIDTH
- ARIZONA_DRC1_SIG_DET
- ARIZONA_DRC1_SIG_DET_EINT1
- ARIZONA_DRC1_SIG_DET_EINT1_MASK
- ARIZONA_DRC1_SIG_DET_EINT1_SHIFT
- ARIZONA_DRC1_SIG_DET_EINT1_WIDTH
- ARIZONA_DRC1_SIG_DET_EINT2
- ARIZONA_DRC1_SIG_DET_EINT2_MASK
- ARIZONA_DRC1_SIG_DET_EINT2_SHIFT
- ARIZONA_DRC1_SIG_DET_EINT2_WIDTH
- ARIZONA_DRC1_SIG_DET_MASK
- ARIZONA_DRC1_SIG_DET_MODE
- ARIZONA_DRC1_SIG_DET_MODE_MASK
- ARIZONA_DRC1_SIG_DET_MODE_SHIFT
- ARIZONA_DRC1_SIG_DET_MODE_WIDTH
- ARIZONA_DRC1_SIG_DET_PK_MASK
- ARIZONA_DRC1_SIG_DET_PK_SHIFT
- ARIZONA_DRC1_SIG_DET_PK_WIDTH
- ARIZONA_DRC1_SIG_DET_RMS_MASK
- ARIZONA_DRC1_SIG_DET_RMS_SHIFT
- ARIZONA_DRC1_SIG_DET_RMS_WIDTH
- ARIZONA_DRC1_SIG_DET_SHIFT
- ARIZONA_DRC1_SIG_DET_STS
- ARIZONA_DRC1_SIG_DET_STS_MASK
- ARIZONA_DRC1_SIG_DET_STS_SHIFT
- ARIZONA_DRC1_SIG_DET_STS_WIDTH
- ARIZONA_DRC1_SIG_DET_WIDTH
- ARIZONA_DRC2LMIX_INPUT_1_SOURCE
- ARIZONA_DRC2LMIX_INPUT_1_VOLUME
- ARIZONA_DRC2LMIX_INPUT_2_SOURCE
- ARIZONA_DRC2LMIX_INPUT_2_VOLUME
- ARIZONA_DRC2LMIX_INPUT_3_SOURCE
- ARIZONA_DRC2LMIX_INPUT_3_VOLUME
- ARIZONA_DRC2LMIX_INPUT_4_SOURCE
- ARIZONA_DRC2LMIX_INPUT_4_VOLUME
- ARIZONA_DRC2L_ENA
- ARIZONA_DRC2L_ENA_MASK
- ARIZONA_DRC2L_ENA_SHIFT
- ARIZONA_DRC2L_ENA_WIDTH
- ARIZONA_DRC2RMIX_INPUT_1_SOURCE
- ARIZONA_DRC2RMIX_INPUT_1_VOLUME
- ARIZONA_DRC2RMIX_INPUT_2_SOURCE
- ARIZONA_DRC2RMIX_INPUT_2_VOLUME
- ARIZONA_DRC2RMIX_INPUT_3_SOURCE
- ARIZONA_DRC2RMIX_INPUT_3_VOLUME
- ARIZONA_DRC2RMIX_INPUT_4_SOURCE
- ARIZONA_DRC2RMIX_INPUT_4_VOLUME
- ARIZONA_DRC2R_ENA
- ARIZONA_DRC2R_ENA_MASK
- ARIZONA_DRC2R_ENA_SHIFT
- ARIZONA_DRC2R_ENA_WIDTH
- ARIZONA_DRC2_ANTICLIP
- ARIZONA_DRC2_ANTICLIP_MASK
- ARIZONA_DRC2_ANTICLIP_SHIFT
- ARIZONA_DRC2_ANTICLIP_WIDTH
- ARIZONA_DRC2_ATK_MASK
- ARIZONA_DRC2_ATK_SHIFT
- ARIZONA_DRC2_ATK_WIDTH
- ARIZONA_DRC2_CTRL1
- ARIZONA_DRC2_CTRL2
- ARIZONA_DRC2_CTRL3
- ARIZONA_DRC2_CTRL4
- ARIZONA_DRC2_CTRL5
- ARIZONA_DRC2_DCY_MASK
- ARIZONA_DRC2_DCY_SHIFT
- ARIZONA_DRC2_DCY_WIDTH
- ARIZONA_DRC2_HI_COMP_MASK
- ARIZONA_DRC2_HI_COMP_SHIFT
- ARIZONA_DRC2_HI_COMP_WIDTH
- ARIZONA_DRC2_KNEE2_IP_MASK
- ARIZONA_DRC2_KNEE2_IP_SHIFT
- ARIZONA_DRC2_KNEE2_IP_WIDTH
- ARIZONA_DRC2_KNEE2_OP_ENA
- ARIZONA_DRC2_KNEE2_OP_ENA_MASK
- ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT
- ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH
- ARIZONA_DRC2_KNEE2_OP_MASK
- ARIZONA_DRC2_KNEE2_OP_SHIFT
- ARIZONA_DRC2_KNEE2_OP_WIDTH
- ARIZONA_DRC2_KNEE_IP_MASK
- ARIZONA_DRC2_KNEE_IP_SHIFT
- ARIZONA_DRC2_KNEE_IP_WIDTH
- ARIZONA_DRC2_KNEE_OP_MASK
- ARIZONA_DRC2_KNEE_OP_SHIFT
- ARIZONA_DRC2_KNEE_OP_WIDTH
- ARIZONA_DRC2_LO_COMP_MASK
- ARIZONA_DRC2_LO_COMP_SHIFT
- ARIZONA_DRC2_LO_COMP_WIDTH
- ARIZONA_DRC2_MAXGAIN_MASK
- ARIZONA_DRC2_MAXGAIN_SHIFT
- ARIZONA_DRC2_MAXGAIN_WIDTH
- ARIZONA_DRC2_MINGAIN_MASK
- ARIZONA_DRC2_MINGAIN_SHIFT
- ARIZONA_DRC2_MINGAIN_WIDTH
- ARIZONA_DRC2_NG_ENA
- ARIZONA_DRC2_NG_ENA_MASK
- ARIZONA_DRC2_NG_ENA_SHIFT
- ARIZONA_DRC2_NG_ENA_WIDTH
- ARIZONA_DRC2_NG_EXP_MASK
- ARIZONA_DRC2_NG_EXP_SHIFT
- ARIZONA_DRC2_NG_EXP_WIDTH
- ARIZONA_DRC2_NG_MINGAIN_MASK
- ARIZONA_DRC2_NG_MINGAIN_SHIFT
- ARIZONA_DRC2_NG_MINGAIN_WIDTH
- ARIZONA_DRC2_QR
- ARIZONA_DRC2_QR_DCY_MASK
- ARIZONA_DRC2_QR_DCY_SHIFT
- ARIZONA_DRC2_QR_DCY_WIDTH
- ARIZONA_DRC2_QR_MASK
- ARIZONA_DRC2_QR_SHIFT
- ARIZONA_DRC2_QR_THR_MASK
- ARIZONA_DRC2_QR_THR_SHIFT
- ARIZONA_DRC2_QR_THR_WIDTH
- ARIZONA_DRC2_QR_WIDTH
- ARIZONA_DRC2_SIG_DET
- ARIZONA_DRC2_SIG_DET_EINT1
- ARIZONA_DRC2_SIG_DET_EINT1_MASK
- ARIZONA_DRC2_SIG_DET_EINT1_SHIFT
- ARIZONA_DRC2_SIG_DET_EINT1_WIDTH
- ARIZONA_DRC2_SIG_DET_EINT2
- ARIZONA_DRC2_SIG_DET_EINT2_MASK
- ARIZONA_DRC2_SIG_DET_EINT2_SHIFT
- ARIZONA_DRC2_SIG_DET_EINT2_WIDTH
- ARIZONA_DRC2_SIG_DET_MASK
- ARIZONA_DRC2_SIG_DET_MODE
- ARIZONA_DRC2_SIG_DET_MODE_MASK
- ARIZONA_DRC2_SIG_DET_MODE_SHIFT
- ARIZONA_DRC2_SIG_DET_MODE_WIDTH
- ARIZONA_DRC2_SIG_DET_PK_MASK
- ARIZONA_DRC2_SIG_DET_PK_SHIFT
- ARIZONA_DRC2_SIG_DET_PK_WIDTH
- ARIZONA_DRC2_SIG_DET_RMS_MASK
- ARIZONA_DRC2_SIG_DET_RMS_SHIFT
- ARIZONA_DRC2_SIG_DET_RMS_WIDTH
- ARIZONA_DRC2_SIG_DET_SHIFT
- ARIZONA_DRC2_SIG_DET_STS
- ARIZONA_DRC2_SIG_DET_STS_MASK
- ARIZONA_DRC2_SIG_DET_STS_SHIFT
- ARIZONA_DRC2_SIG_DET_STS_WIDTH
- ARIZONA_DRC2_SIG_DET_WIDTH
- ARIZONA_DRE1L_ENA
- ARIZONA_DRE1L_ENA_MASK
- ARIZONA_DRE1L_ENA_SHIFT
- ARIZONA_DRE1L_ENA_WIDTH
- ARIZONA_DRE1R_ENA
- ARIZONA_DRE1R_ENA_MASK
- ARIZONA_DRE1R_ENA_SHIFT
- ARIZONA_DRE1R_ENA_WIDTH
- ARIZONA_DRE2L_ENA
- ARIZONA_DRE2L_ENA_MASK
- ARIZONA_DRE2L_ENA_SHIFT
- ARIZONA_DRE2L_ENA_WIDTH
- ARIZONA_DRE2R_ENA
- ARIZONA_DRE2R_ENA_MASK
- ARIZONA_DRE2R_ENA_SHIFT
- ARIZONA_DRE2R_ENA_WIDTH
- ARIZONA_DRE3L_ENA
- ARIZONA_DRE3L_ENA_MASK
- ARIZONA_DRE3L_ENA_SHIFT
- ARIZONA_DRE3L_ENA_WIDTH
- ARIZONA_DRE3R_ENA
- ARIZONA_DRE3R_ENA_MASK
- ARIZONA_DRE3R_ENA_SHIFT
- ARIZONA_DRE3R_ENA_WIDTH
- ARIZONA_DRE_ALOG_VOL_DELAY_MASK
- ARIZONA_DRE_ALOG_VOL_DELAY_SHIFT
- ARIZONA_DRE_ALOG_VOL_DELAY_WIDTH
- ARIZONA_DRE_CONTROL_1
- ARIZONA_DRE_CONTROL_2
- ARIZONA_DRE_CONTROL_3
- ARIZONA_DRE_ENABLE
- ARIZONA_DRE_ENV_TC_FAST_MASK
- ARIZONA_DRE_ENV_TC_FAST_SHIFT
- ARIZONA_DRE_ENV_TC_FAST_WIDTH
- ARIZONA_DRE_GAIN_SHIFT_MASK
- ARIZONA_DRE_GAIN_SHIFT_SHIFT
- ARIZONA_DRE_GAIN_SHIFT_WIDTH
- ARIZONA_DRE_LOW_LEVEL_ABS_MASK
- ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT
- ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH
- ARIZONA_DRE_T_LOW_MASK
- ARIZONA_DRE_T_LOW_SHIFT
- ARIZONA_DRE_T_LOW_WIDTH
- ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE
- ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE
- ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE
- ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE
- ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE
- ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE
- ARIZONA_DSP1LMIX_INPUT_1_SOURCE
- ARIZONA_DSP1LMIX_INPUT_1_VOLUME
- ARIZONA_DSP1LMIX_INPUT_2_SOURCE
- ARIZONA_DSP1LMIX_INPUT_2_VOLUME
- ARIZONA_DSP1LMIX_INPUT_3_SOURCE
- ARIZONA_DSP1LMIX_INPUT_3_VOLUME
- ARIZONA_DSP1LMIX_INPUT_4_SOURCE
- ARIZONA_DSP1LMIX_INPUT_4_VOLUME
- ARIZONA_DSP1RMIX_INPUT_1_SOURCE
- ARIZONA_DSP1RMIX_INPUT_1_VOLUME
- ARIZONA_DSP1RMIX_INPUT_2_SOURCE
- ARIZONA_DSP1RMIX_INPUT_2_VOLUME
- ARIZONA_DSP1RMIX_INPUT_3_SOURCE
- ARIZONA_DSP1RMIX_INPUT_3_VOLUME
- ARIZONA_DSP1RMIX_INPUT_4_SOURCE
- ARIZONA_DSP1RMIX_INPUT_4_VOLUME
- ARIZONA_DSP1_CLK_SEL_MASK
- ARIZONA_DSP1_CLK_SEL_SHIFT
- ARIZONA_DSP1_CLK_SEL_WIDTH
- ARIZONA_DSP1_CLOCKING_1
- ARIZONA_DSP1_CONTROL_1
- ARIZONA_DSP1_CORE_ENA
- ARIZONA_DSP1_CORE_ENA_MASK
- ARIZONA_DSP1_CORE_ENA_SHIFT
- ARIZONA_DSP1_CORE_ENA_WIDTH
- ARIZONA_DSP1_EXTERNAL_START_SELECT_1
- ARIZONA_DSP1_MEM_ENA
- ARIZONA_DSP1_MEM_ENA_MASK
- ARIZONA_DSP1_MEM_ENA_SHIFT
- ARIZONA_DSP1_MEM_ENA_WIDTH
- ARIZONA_DSP1_PING_FULL
- ARIZONA_DSP1_PING_FULL_MASK
- ARIZONA_DSP1_PING_FULL_SHIFT
- ARIZONA_DSP1_PING_FULL_WIDTH
- ARIZONA_DSP1_PONG_FULL
- ARIZONA_DSP1_PONG_FULL_MASK
- ARIZONA_DSP1_PONG_FULL_SHIFT
- ARIZONA_DSP1_PONG_FULL_WIDTH
- ARIZONA_DSP1_RAM_RDY
- ARIZONA_DSP1_RAM_RDY_EINT1
- ARIZONA_DSP1_RAM_RDY_EINT1_MASK
- ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT
- ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH
- ARIZONA_DSP1_RAM_RDY_EINT2
- ARIZONA_DSP1_RAM_RDY_EINT2_MASK
- ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT
- ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH
- ARIZONA_DSP1_RAM_RDY_MASK
- ARIZONA_DSP1_RAM_RDY_SHIFT
- ARIZONA_DSP1_RAM_RDY_STS
- ARIZONA_DSP1_RAM_RDY_STS_MASK
- ARIZONA_DSP1_RAM_RDY_STS_SHIFT
- ARIZONA_DSP1_RAM_RDY_STS_WIDTH
- ARIZONA_DSP1_RAM_RDY_WIDTH
- ARIZONA_DSP1_RATE_MASK
- ARIZONA_DSP1_RATE_SHIFT
- ARIZONA_DSP1_RATE_WIDTH
- ARIZONA_DSP1_RDMA_BUFFER_1
- ARIZONA_DSP1_RDMA_BUFFER_2
- ARIZONA_DSP1_RDMA_BUFFER_3
- ARIZONA_DSP1_RDMA_BUFFER_4
- ARIZONA_DSP1_RDMA_BUFFER_5
- ARIZONA_DSP1_RDMA_BUFFER_6
- ARIZONA_DSP1_RDMA_CONFIG_1
- ARIZONA_DSP1_RDMA_OFFSET_1
- ARIZONA_DSP1_SCRATCH_0
- ARIZONA_DSP1_SCRATCH_1
- ARIZONA_DSP1_SCRATCH_2
- ARIZONA_DSP1_SCRATCH_3
- ARIZONA_DSP1_START
- ARIZONA_DSP1_START_MASK
- ARIZONA_DSP1_START_SHIFT
- ARIZONA_DSP1_START_WIDTH
- ARIZONA_DSP1_STATUS_1
- ARIZONA_DSP1_STATUS_2
- ARIZONA_DSP1_STATUS_3
- ARIZONA_DSP1_STATUS_4
- ARIZONA_DSP1_SYS_ENA
- ARIZONA_DSP1_SYS_ENA_MASK
- ARIZONA_DSP1_SYS_ENA_SHIFT
- ARIZONA_DSP1_SYS_ENA_WIDTH
- ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK
- ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT
- ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH
- ARIZONA_DSP1_WDMA_BUFFER_1
- ARIZONA_DSP1_WDMA_BUFFER_2
- ARIZONA_DSP1_WDMA_BUFFER_3
- ARIZONA_DSP1_WDMA_BUFFER_4
- ARIZONA_DSP1_WDMA_BUFFER_5
- ARIZONA_DSP1_WDMA_BUFFER_6
- ARIZONA_DSP1_WDMA_BUFFER_7
- ARIZONA_DSP1_WDMA_BUFFER_8
- ARIZONA_DSP1_WDMA_CONFIG_1
- ARIZONA_DSP1_WDMA_CONFIG_2
- ARIZONA_DSP1_WDMA_OFFSET_1
- ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE
- ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE
- ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE
- ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE
- ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE
- ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE
- ARIZONA_DSP2LMIX_INPUT_1_SOURCE
- ARIZONA_DSP2LMIX_INPUT_1_VOLUME
- ARIZONA_DSP2LMIX_INPUT_2_SOURCE
- ARIZONA_DSP2LMIX_INPUT_2_VOLUME
- ARIZONA_DSP2LMIX_INPUT_3_SOURCE
- ARIZONA_DSP2LMIX_INPUT_3_VOLUME
- ARIZONA_DSP2LMIX_INPUT_4_SOURCE
- ARIZONA_DSP2LMIX_INPUT_4_VOLUME
- ARIZONA_DSP2RMIX_INPUT_1_SOURCE
- ARIZONA_DSP2RMIX_INPUT_1_VOLUME
- ARIZONA_DSP2RMIX_INPUT_2_SOURCE
- ARIZONA_DSP2RMIX_INPUT_2_VOLUME
- ARIZONA_DSP2RMIX_INPUT_3_SOURCE
- ARIZONA_DSP2RMIX_INPUT_3_VOLUME
- ARIZONA_DSP2RMIX_INPUT_4_SOURCE
- ARIZONA_DSP2RMIX_INPUT_4_VOLUME
- ARIZONA_DSP2_CLOCKING_1
- ARIZONA_DSP2_CONTROL_1
- ARIZONA_DSP2_EXTERNAL_START_SELECT_1
- ARIZONA_DSP2_RAM_RDY_EINT1
- ARIZONA_DSP2_RAM_RDY_EINT1_MASK
- ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT
- ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH
- ARIZONA_DSP2_RDMA_BUFFER_1
- ARIZONA_DSP2_RDMA_BUFFER_2
- ARIZONA_DSP2_RDMA_BUFFER_3
- ARIZONA_DSP2_RDMA_BUFFER_4
- ARIZONA_DSP2_RDMA_BUFFER_5
- ARIZONA_DSP2_RDMA_BUFFER_6
- ARIZONA_DSP2_RDMA_CONFIG_1
- ARIZONA_DSP2_RDMA_OFFSET_1
- ARIZONA_DSP2_SCRATCH_0
- ARIZONA_DSP2_SCRATCH_1
- ARIZONA_DSP2_SCRATCH_2
- ARIZONA_DSP2_SCRATCH_3
- ARIZONA_DSP2_STATUS_1
- ARIZONA_DSP2_STATUS_2
- ARIZONA_DSP2_STATUS_3
- ARIZONA_DSP2_STATUS_4
- ARIZONA_DSP2_WDMA_BUFFER_1
- ARIZONA_DSP2_WDMA_BUFFER_2
- ARIZONA_DSP2_WDMA_BUFFER_3
- ARIZONA_DSP2_WDMA_BUFFER_4
- ARIZONA_DSP2_WDMA_BUFFER_5
- ARIZONA_DSP2_WDMA_BUFFER_6
- ARIZONA_DSP2_WDMA_BUFFER_7
- ARIZONA_DSP2_WDMA_BUFFER_8
- ARIZONA_DSP2_WDMA_CONFIG_1
- ARIZONA_DSP2_WDMA_CONFIG_2
- ARIZONA_DSP2_WDMA_OFFSET_1
- ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE
- ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE
- ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE
- ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE
- ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE
- ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE
- ARIZONA_DSP3LMIX_INPUT_1_SOURCE
- ARIZONA_DSP3LMIX_INPUT_1_VOLUME
- ARIZONA_DSP3LMIX_INPUT_2_SOURCE
- ARIZONA_DSP3LMIX_INPUT_2_VOLUME
- ARIZONA_DSP3LMIX_INPUT_3_SOURCE
- ARIZONA_DSP3LMIX_INPUT_3_VOLUME
- ARIZONA_DSP3LMIX_INPUT_4_SOURCE
- ARIZONA_DSP3LMIX_INPUT_4_VOLUME
- ARIZONA_DSP3RMIX_INPUT_1_SOURCE
- ARIZONA_DSP3RMIX_INPUT_1_VOLUME
- ARIZONA_DSP3RMIX_INPUT_2_SOURCE
- ARIZONA_DSP3RMIX_INPUT_2_VOLUME
- ARIZONA_DSP3RMIX_INPUT_3_SOURCE
- ARIZONA_DSP3RMIX_INPUT_3_VOLUME
- ARIZONA_DSP3RMIX_INPUT_4_SOURCE
- ARIZONA_DSP3RMIX_INPUT_4_VOLUME
- ARIZONA_DSP3_CLOCKING_1
- ARIZONA_DSP3_CONTROL_1
- ARIZONA_DSP3_EXTERNAL_START_SELECT_1
- ARIZONA_DSP3_RAM_RDY_EINT1
- ARIZONA_DSP3_RAM_RDY_EINT1_MASK
- ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT
- ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH
- ARIZONA_DSP3_RDMA_BUFFER_1
- ARIZONA_DSP3_RDMA_BUFFER_2
- ARIZONA_DSP3_RDMA_BUFFER_3
- ARIZONA_DSP3_RDMA_BUFFER_4
- ARIZONA_DSP3_RDMA_BUFFER_5
- ARIZONA_DSP3_RDMA_BUFFER_6
- ARIZONA_DSP3_RDMA_CONFIG_1
- ARIZONA_DSP3_RDMA_OFFSET_1
- ARIZONA_DSP3_SCRATCH_0
- ARIZONA_DSP3_SCRATCH_1
- ARIZONA_DSP3_SCRATCH_2
- ARIZONA_DSP3_SCRATCH_3
- ARIZONA_DSP3_STATUS_1
- ARIZONA_DSP3_STATUS_2
- ARIZONA_DSP3_STATUS_3
- ARIZONA_DSP3_STATUS_4
- ARIZONA_DSP3_WDMA_BUFFER_1
- ARIZONA_DSP3_WDMA_BUFFER_2
- ARIZONA_DSP3_WDMA_BUFFER_3
- ARIZONA_DSP3_WDMA_BUFFER_4
- ARIZONA_DSP3_WDMA_BUFFER_5
- ARIZONA_DSP3_WDMA_BUFFER_6
- ARIZONA_DSP3_WDMA_BUFFER_7
- ARIZONA_DSP3_WDMA_BUFFER_8
- ARIZONA_DSP3_WDMA_CONFIG_1
- ARIZONA_DSP3_WDMA_CONFIG_2
- ARIZONA_DSP3_WDMA_OFFSET_1
- ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE
- ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE
- ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE
- ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE
- ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE
- ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE
- ARIZONA_DSP4LMIX_INPUT_1_SOURCE
- ARIZONA_DSP4LMIX_INPUT_1_VOLUME
- ARIZONA_DSP4LMIX_INPUT_2_SOURCE
- ARIZONA_DSP4LMIX_INPUT_2_VOLUME
- ARIZONA_DSP4LMIX_INPUT_3_SOURCE
- ARIZONA_DSP4LMIX_INPUT_3_VOLUME
- ARIZONA_DSP4LMIX_INPUT_4_SOURCE
- ARIZONA_DSP4LMIX_INPUT_4_VOLUME
- ARIZONA_DSP4RMIX_INPUT_1_SOURCE
- ARIZONA_DSP4RMIX_INPUT_1_VOLUME
- ARIZONA_DSP4RMIX_INPUT_2_SOURCE
- ARIZONA_DSP4RMIX_INPUT_2_VOLUME
- ARIZONA_DSP4RMIX_INPUT_3_SOURCE
- ARIZONA_DSP4RMIX_INPUT_3_VOLUME
- ARIZONA_DSP4RMIX_INPUT_4_SOURCE
- ARIZONA_DSP4RMIX_INPUT_4_VOLUME
- ARIZONA_DSP4_CLOCKING_1
- ARIZONA_DSP4_CONTROL_1
- ARIZONA_DSP4_EXTERNAL_START_SELECT_1
- ARIZONA_DSP4_RAM_RDY_EINT1
- ARIZONA_DSP4_RAM_RDY_EINT1_MASK
- ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT
- ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH
- ARIZONA_DSP4_RDMA_BUFFER_1
- ARIZONA_DSP4_RDMA_BUFFER_2
- ARIZONA_DSP4_RDMA_BUFFER_3
- ARIZONA_DSP4_RDMA_BUFFER_4
- ARIZONA_DSP4_RDMA_BUFFER_5
- ARIZONA_DSP4_RDMA_BUFFER_6
- ARIZONA_DSP4_RDMA_CONFIG_1
- ARIZONA_DSP4_RDMA_OFFSET_1
- ARIZONA_DSP4_SCRATCH_0
- ARIZONA_DSP4_SCRATCH_1
- ARIZONA_DSP4_SCRATCH_2
- ARIZONA_DSP4_SCRATCH_3
- ARIZONA_DSP4_STATUS_1
- ARIZONA_DSP4_STATUS_2
- ARIZONA_DSP4_STATUS_3
- ARIZONA_DSP4_STATUS_4
- ARIZONA_DSP4_WDMA_BUFFER_1
- ARIZONA_DSP4_WDMA_BUFFER_2
- ARIZONA_DSP4_WDMA_BUFFER_3
- ARIZONA_DSP4_WDMA_BUFFER_4
- ARIZONA_DSP4_WDMA_BUFFER_5
- ARIZONA_DSP4_WDMA_BUFFER_6
- ARIZONA_DSP4_WDMA_BUFFER_7
- ARIZONA_DSP4_WDMA_BUFFER_8
- ARIZONA_DSP4_WDMA_CONFIG_1
- ARIZONA_DSP4_WDMA_CONFIG_2
- ARIZONA_DSP4_WDMA_OFFSET_1
- ARIZONA_DSP_AUX_ENUMS
- ARIZONA_DSP_IRQ1
- ARIZONA_DSP_IRQ1_EINT1
- ARIZONA_DSP_IRQ1_EINT1_MASK
- ARIZONA_DSP_IRQ1_EINT1_SHIFT
- ARIZONA_DSP_IRQ1_EINT1_WIDTH
- ARIZONA_DSP_IRQ1_EINT2
- ARIZONA_DSP_IRQ1_EINT2_MASK
- ARIZONA_DSP_IRQ1_EINT2_SHIFT
- ARIZONA_DSP_IRQ1_EINT2_WIDTH
- ARIZONA_DSP_IRQ1_MASK
- ARIZONA_DSP_IRQ1_SHIFT
- ARIZONA_DSP_IRQ1_STS
- ARIZONA_DSP_IRQ1_STS_MASK
- ARIZONA_DSP_IRQ1_STS_SHIFT
- ARIZONA_DSP_IRQ1_STS_WIDTH
- ARIZONA_DSP_IRQ1_WIDTH
- ARIZONA_DSP_IRQ2
- ARIZONA_DSP_IRQ2_EINT1
- ARIZONA_DSP_IRQ2_EINT1_MASK
- ARIZONA_DSP_IRQ2_EINT1_SHIFT
- ARIZONA_DSP_IRQ2_EINT1_WIDTH
- ARIZONA_DSP_IRQ2_EINT2
- ARIZONA_DSP_IRQ2_EINT2_MASK
- ARIZONA_DSP_IRQ2_EINT2_SHIFT
- ARIZONA_DSP_IRQ2_EINT2_WIDTH
- ARIZONA_DSP_IRQ2_MASK
- ARIZONA_DSP_IRQ2_SHIFT
- ARIZONA_DSP_IRQ2_STS
- ARIZONA_DSP_IRQ2_STS_MASK
- ARIZONA_DSP_IRQ2_STS_SHIFT
- ARIZONA_DSP_IRQ2_STS_WIDTH
- ARIZONA_DSP_IRQ2_WIDTH
- ARIZONA_DSP_IRQ3_EINT1
- ARIZONA_DSP_IRQ3_EINT1_MASK
- ARIZONA_DSP_IRQ3_EINT1_SHIFT
- ARIZONA_DSP_IRQ3_EINT1_WIDTH
- ARIZONA_DSP_IRQ4_EINT1
- ARIZONA_DSP_IRQ4_EINT1_MASK
- ARIZONA_DSP_IRQ4_EINT1_SHIFT
- ARIZONA_DSP_IRQ4_EINT1_WIDTH
- ARIZONA_DSP_IRQ5_EINT1
- ARIZONA_DSP_IRQ5_EINT1_MASK
- ARIZONA_DSP_IRQ5_EINT1_SHIFT
- ARIZONA_DSP_IRQ5_EINT1_WIDTH
- ARIZONA_DSP_IRQ6_EINT1
- ARIZONA_DSP_IRQ6_EINT1_MASK
- ARIZONA_DSP_IRQ6_EINT1_SHIFT
- ARIZONA_DSP_IRQ6_EINT1_WIDTH
- ARIZONA_DSP_IRQ7_EINT1
- ARIZONA_DSP_IRQ7_EINT1_MASK
- ARIZONA_DSP_IRQ7_EINT1_SHIFT
- ARIZONA_DSP_IRQ7_EINT1_WIDTH
- ARIZONA_DSP_IRQ8_EINT1
- ARIZONA_DSP_IRQ8_EINT1_MASK
- ARIZONA_DSP_IRQ8_EINT1_SHIFT
- ARIZONA_DSP_IRQ8_EINT1_WIDTH
- ARIZONA_DSP_ROUTES
- ARIZONA_DSP_SHARED_WR_COLL_EINT1
- ARIZONA_DSP_SHARED_WR_COLL_EINT1_MASK
- ARIZONA_DSP_SHARED_WR_COLL_EINT1_SHIFT
- ARIZONA_DSP_SHARED_WR_COLL_EINT1_WIDTH
- ARIZONA_DSP_SHARED_WR_COLL_EINT2
- ARIZONA_DSP_SHARED_WR_COLL_EINT2_MASK
- ARIZONA_DSP_SHARED_WR_COLL_EINT2_SHIFT
- ARIZONA_DSP_SHARED_WR_COLL_EINT2_WIDTH
- ARIZONA_DSP_SHARED_WR_COLL_STS
- ARIZONA_DSP_SHARED_WR_COLL_STS_MASK
- ARIZONA_DSP_SHARED_WR_COLL_STS_SHIFT
- ARIZONA_DSP_SHARED_WR_COLL_STS_WIDTH
- ARIZONA_DSP_STATUS
- ARIZONA_DSP_WIDGETS
- ARIZONA_DVFS_ADSP1_RQ
- ARIZONA_DVFS_SR1_RQ
- ARIZONA_DYNAMIC_FREQUENCY_SCALING_1
- ARIZONA_EDRE_ENABLE
- ARIZONA_EDRE_OUT1L_THR1_ENA
- ARIZONA_EDRE_OUT1L_THR1_ENA_MASK
- ARIZONA_EDRE_OUT1L_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT1L_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT1R_THR1_ENA
- ARIZONA_EDRE_OUT1R_THR1_ENA_MASK
- ARIZONA_EDRE_OUT1R_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT1R_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT2L_THR1_ENA
- ARIZONA_EDRE_OUT2L_THR1_ENA_MASK
- ARIZONA_EDRE_OUT2L_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT2L_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT2R_THR1_ENA
- ARIZONA_EDRE_OUT2R_THR1_ENA_MASK
- ARIZONA_EDRE_OUT2R_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT2R_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT3L_THR1_ENA
- ARIZONA_EDRE_OUT3L_THR1_ENA_MASK
- ARIZONA_EDRE_OUT3L_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT3L_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT3R_THR1_ENA
- ARIZONA_EDRE_OUT3R_THR1_ENA_MASK
- ARIZONA_EDRE_OUT3R_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT3R_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT4L_THR1_ENA
- ARIZONA_EDRE_OUT4L_THR1_ENA_MASK
- ARIZONA_EDRE_OUT4L_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT4L_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT4L_THR2_ENA
- ARIZONA_EDRE_OUT4L_THR2_ENA_MASK
- ARIZONA_EDRE_OUT4L_THR2_ENA_SHIFT
- ARIZONA_EDRE_OUT4L_THR2_ENA_WIDTH
- ARIZONA_EDRE_OUT4R_THR1_ENA
- ARIZONA_EDRE_OUT4R_THR1_ENA_MASK
- ARIZONA_EDRE_OUT4R_THR1_ENA_SHIFT
- ARIZONA_EDRE_OUT4R_THR1_ENA_WIDTH
- ARIZONA_EDRE_OUT4R_THR2_ENA
- ARIZONA_EDRE_OUT4R_THR2_ENA_MASK
- ARIZONA_EDRE_OUT4R_THR2_ENA_SHIFT
- ARIZONA_EDRE_OUT4R_THR2_ENA_WIDTH
- ARIZONA_EQ1MIX_INPUT_1_SOURCE
- ARIZONA_EQ1MIX_INPUT_1_VOLUME
- ARIZONA_EQ1MIX_INPUT_2_SOURCE
- ARIZONA_EQ1MIX_INPUT_2_VOLUME
- ARIZONA_EQ1MIX_INPUT_3_SOURCE
- ARIZONA_EQ1MIX_INPUT_3_VOLUME
- ARIZONA_EQ1MIX_INPUT_4_SOURCE
- ARIZONA_EQ1MIX_INPUT_4_VOLUME
- ARIZONA_EQ1_1
- ARIZONA_EQ1_10
- ARIZONA_EQ1_11
- ARIZONA_EQ1_12
- ARIZONA_EQ1_13
- ARIZONA_EQ1_14
- ARIZONA_EQ1_15
- ARIZONA_EQ1_16
- ARIZONA_EQ1_17
- ARIZONA_EQ1_18
- ARIZONA_EQ1_19
- ARIZONA_EQ1_2
- ARIZONA_EQ1_20
- ARIZONA_EQ1_21
- ARIZONA_EQ1_3
- ARIZONA_EQ1_4
- ARIZONA_EQ1_5
- ARIZONA_EQ1_6
- ARIZONA_EQ1_7
- ARIZONA_EQ1_8
- ARIZONA_EQ1_9
- ARIZONA_EQ1_B1_A_MASK
- ARIZONA_EQ1_B1_A_SHIFT
- ARIZONA_EQ1_B1_A_WIDTH
- ARIZONA_EQ1_B1_B_MASK
- ARIZONA_EQ1_B1_B_SHIFT
- ARIZONA_EQ1_B1_B_WIDTH
- ARIZONA_EQ1_B1_C_MASK
- ARIZONA_EQ1_B1_C_SHIFT
- ARIZONA_EQ1_B1_C_WIDTH
- ARIZONA_EQ1_B1_GAIN_MASK
- ARIZONA_EQ1_B1_GAIN_SHIFT
- ARIZONA_EQ1_B1_GAIN_WIDTH
- ARIZONA_EQ1_B1_MODE
- ARIZONA_EQ1_B1_MODE_MASK
- ARIZONA_EQ1_B1_MODE_SHIFT
- ARIZONA_EQ1_B1_MODE_WIDTH
- ARIZONA_EQ1_B1_PG_MASK
- ARIZONA_EQ1_B1_PG_SHIFT
- ARIZONA_EQ1_B1_PG_WIDTH
- ARIZONA_EQ1_B2_A_MASK
- ARIZONA_EQ1_B2_A_SHIFT
- ARIZONA_EQ1_B2_A_WIDTH
- ARIZONA_EQ1_B2_B_MASK
- ARIZONA_EQ1_B2_B_SHIFT
- ARIZONA_EQ1_B2_B_WIDTH
- ARIZONA_EQ1_B2_C_MASK
- ARIZONA_EQ1_B2_C_SHIFT
- ARIZONA_EQ1_B2_C_WIDTH
- ARIZONA_EQ1_B2_GAIN_MASK
- ARIZONA_EQ1_B2_GAIN_SHIFT
- ARIZONA_EQ1_B2_GAIN_WIDTH
- ARIZONA_EQ1_B2_PG_MASK
- ARIZONA_EQ1_B2_PG_SHIFT
- ARIZONA_EQ1_B2_PG_WIDTH
- ARIZONA_EQ1_B3_A_MASK
- ARIZONA_EQ1_B3_A_SHIFT
- ARIZONA_EQ1_B3_A_WIDTH
- ARIZONA_EQ1_B3_B_MASK
- ARIZONA_EQ1_B3_B_SHIFT
- ARIZONA_EQ1_B3_B_WIDTH
- ARIZONA_EQ1_B3_C_MASK
- ARIZONA_EQ1_B3_C_SHIFT
- ARIZONA_EQ1_B3_C_WIDTH
- ARIZONA_EQ1_B3_GAIN_MASK
- ARIZONA_EQ1_B3_GAIN_SHIFT
- ARIZONA_EQ1_B3_GAIN_WIDTH
- ARIZONA_EQ1_B3_PG_MASK
- ARIZONA_EQ1_B3_PG_SHIFT
- ARIZONA_EQ1_B3_PG_WIDTH
- ARIZONA_EQ1_B4_A_MASK
- ARIZONA_EQ1_B4_A_SHIFT
- ARIZONA_EQ1_B4_A_WIDTH
- ARIZONA_EQ1_B4_B_MASK
- ARIZONA_EQ1_B4_B_SHIFT
- ARIZONA_EQ1_B4_B_WIDTH
- ARIZONA_EQ1_B4_C_MASK
- ARIZONA_EQ1_B4_C_SHIFT
- ARIZONA_EQ1_B4_C_WIDTH
- ARIZONA_EQ1_B4_GAIN_MASK
- ARIZONA_EQ1_B4_GAIN_SHIFT
- ARIZONA_EQ1_B4_GAIN_WIDTH
- ARIZONA_EQ1_B4_PG_MASK
- ARIZONA_EQ1_B4_PG_SHIFT
- ARIZONA_EQ1_B4_PG_WIDTH
- ARIZONA_EQ1_B5_A_MASK
- ARIZONA_EQ1_B5_A_SHIFT
- ARIZONA_EQ1_B5_A_WIDTH
- ARIZONA_EQ1_B5_B_MASK
- ARIZONA_EQ1_B5_B_SHIFT
- ARIZONA_EQ1_B5_B_WIDTH
- ARIZONA_EQ1_B5_GAIN_MASK
- ARIZONA_EQ1_B5_GAIN_SHIFT
- ARIZONA_EQ1_B5_GAIN_WIDTH
- ARIZONA_EQ1_B5_PG_MASK
- ARIZONA_EQ1_B5_PG_SHIFT
- ARIZONA_EQ1_B5_PG_WIDTH
- ARIZONA_EQ1_ENA
- ARIZONA_EQ1_ENA_MASK
- ARIZONA_EQ1_ENA_SHIFT
- ARIZONA_EQ1_ENA_WIDTH
- ARIZONA_EQ2MIX_INPUT_1_SOURCE
- ARIZONA_EQ2MIX_INPUT_1_VOLUME
- ARIZONA_EQ2MIX_INPUT_2_SOURCE
- ARIZONA_EQ2MIX_INPUT_2_VOLUME
- ARIZONA_EQ2MIX_INPUT_3_SOURCE
- ARIZONA_EQ2MIX_INPUT_3_VOLUME
- ARIZONA_EQ2MIX_INPUT_4_SOURCE
- ARIZONA_EQ2MIX_INPUT_4_VOLUME
- ARIZONA_EQ2_1
- ARIZONA_EQ2_10
- ARIZONA_EQ2_11
- ARIZONA_EQ2_12
- ARIZONA_EQ2_13
- ARIZONA_EQ2_14
- ARIZONA_EQ2_15
- ARIZONA_EQ2_16
- ARIZONA_EQ2_17
- ARIZONA_EQ2_18
- ARIZONA_EQ2_19
- ARIZONA_EQ2_2
- ARIZONA_EQ2_20
- ARIZONA_EQ2_21
- ARIZONA_EQ2_3
- ARIZONA_EQ2_4
- ARIZONA_EQ2_5
- ARIZONA_EQ2_6
- ARIZONA_EQ2_7
- ARIZONA_EQ2_8
- ARIZONA_EQ2_9
- ARIZONA_EQ2_B1_A_MASK
- ARIZONA_EQ2_B1_A_SHIFT
- ARIZONA_EQ2_B1_A_WIDTH
- ARIZONA_EQ2_B1_B_MASK
- ARIZONA_EQ2_B1_B_SHIFT
- ARIZONA_EQ2_B1_B_WIDTH
- ARIZONA_EQ2_B1_C_MASK
- ARIZONA_EQ2_B1_C_SHIFT
- ARIZONA_EQ2_B1_C_WIDTH
- ARIZONA_EQ2_B1_GAIN_MASK
- ARIZONA_EQ2_B1_GAIN_SHIFT
- ARIZONA_EQ2_B1_GAIN_WIDTH
- ARIZONA_EQ2_B1_MODE
- ARIZONA_EQ2_B1_MODE_MASK
- ARIZONA_EQ2_B1_MODE_SHIFT
- ARIZONA_EQ2_B1_MODE_WIDTH
- ARIZONA_EQ2_B1_PG_MASK
- ARIZONA_EQ2_B1_PG_SHIFT
- ARIZONA_EQ2_B1_PG_WIDTH
- ARIZONA_EQ2_B2_A_MASK
- ARIZONA_EQ2_B2_A_SHIFT
- ARIZONA_EQ2_B2_A_WIDTH
- ARIZONA_EQ2_B2_B_MASK
- ARIZONA_EQ2_B2_B_SHIFT
- ARIZONA_EQ2_B2_B_WIDTH
- ARIZONA_EQ2_B2_C_MASK
- ARIZONA_EQ2_B2_C_SHIFT
- ARIZONA_EQ2_B2_C_WIDTH
- ARIZONA_EQ2_B2_GAIN_MASK
- ARIZONA_EQ2_B2_GAIN_SHIFT
- ARIZONA_EQ2_B2_GAIN_WIDTH
- ARIZONA_EQ2_B2_PG_MASK
- ARIZONA_EQ2_B2_PG_SHIFT
- ARIZONA_EQ2_B2_PG_WIDTH
- ARIZONA_EQ2_B3_A_MASK
- ARIZONA_EQ2_B3_A_SHIFT
- ARIZONA_EQ2_B3_A_WIDTH
- ARIZONA_EQ2_B3_B_MASK
- ARIZONA_EQ2_B3_B_SHIFT
- ARIZONA_EQ2_B3_B_WIDTH
- ARIZONA_EQ2_B3_C_MASK
- ARIZONA_EQ2_B3_C_SHIFT
- ARIZONA_EQ2_B3_C_WIDTH
- ARIZONA_EQ2_B3_GAIN_MASK
- ARIZONA_EQ2_B3_GAIN_SHIFT
- ARIZONA_EQ2_B3_GAIN_WIDTH
- ARIZONA_EQ2_B3_PG_MASK
- ARIZONA_EQ2_B3_PG_SHIFT
- ARIZONA_EQ2_B3_PG_WIDTH
- ARIZONA_EQ2_B4_A_MASK
- ARIZONA_EQ2_B4_A_SHIFT
- ARIZONA_EQ2_B4_A_WIDTH
- ARIZONA_EQ2_B4_B_MASK
- ARIZONA_EQ2_B4_B_SHIFT
- ARIZONA_EQ2_B4_B_WIDTH
- ARIZONA_EQ2_B4_C_MASK
- ARIZONA_EQ2_B4_C_SHIFT
- ARIZONA_EQ2_B4_C_WIDTH
- ARIZONA_EQ2_B4_GAIN_MASK
- ARIZONA_EQ2_B4_GAIN_SHIFT
- ARIZONA_EQ2_B4_GAIN_WIDTH
- ARIZONA_EQ2_B4_PG_MASK
- ARIZONA_EQ2_B4_PG_SHIFT
- ARIZONA_EQ2_B4_PG_WIDTH
- ARIZONA_EQ2_B5_A_MASK
- ARIZONA_EQ2_B5_A_SHIFT
- ARIZONA_EQ2_B5_A_WIDTH
- ARIZONA_EQ2_B5_B_MASK
- ARIZONA_EQ2_B5_B_SHIFT
- ARIZONA_EQ2_B5_B_WIDTH
- ARIZONA_EQ2_B5_GAIN_MASK
- ARIZONA_EQ2_B5_GAIN_SHIFT
- ARIZONA_EQ2_B5_GAIN_WIDTH
- ARIZONA_EQ2_B5_PG_MASK
- ARIZONA_EQ2_B5_PG_SHIFT
- ARIZONA_EQ2_B5_PG_WIDTH
- ARIZONA_EQ2_ENA
- ARIZONA_EQ2_ENA_MASK
- ARIZONA_EQ2_ENA_SHIFT
- ARIZONA_EQ2_ENA_WIDTH
- ARIZONA_EQ3MIX_INPUT_1_SOURCE
- ARIZONA_EQ3MIX_INPUT_1_VOLUME
- ARIZONA_EQ3MIX_INPUT_2_SOURCE
- ARIZONA_EQ3MIX_INPUT_2_VOLUME
- ARIZONA_EQ3MIX_INPUT_3_SOURCE
- ARIZONA_EQ3MIX_INPUT_3_VOLUME
- ARIZONA_EQ3MIX_INPUT_4_SOURCE
- ARIZONA_EQ3MIX_INPUT_4_VOLUME
- ARIZONA_EQ3_1
- ARIZONA_EQ3_10
- ARIZONA_EQ3_11
- ARIZONA_EQ3_12
- ARIZONA_EQ3_13
- ARIZONA_EQ3_14
- ARIZONA_EQ3_15
- ARIZONA_EQ3_16
- ARIZONA_EQ3_17
- ARIZONA_EQ3_18
- ARIZONA_EQ3_19
- ARIZONA_EQ3_2
- ARIZONA_EQ3_20
- ARIZONA_EQ3_21
- ARIZONA_EQ3_3
- ARIZONA_EQ3_4
- ARIZONA_EQ3_5
- ARIZONA_EQ3_6
- ARIZONA_EQ3_7
- ARIZONA_EQ3_8
- ARIZONA_EQ3_9
- ARIZONA_EQ3_B1_A_MASK
- ARIZONA_EQ3_B1_A_SHIFT
- ARIZONA_EQ3_B1_A_WIDTH
- ARIZONA_EQ3_B1_B_MASK
- ARIZONA_EQ3_B1_B_SHIFT
- ARIZONA_EQ3_B1_B_WIDTH
- ARIZONA_EQ3_B1_C_MASK
- ARIZONA_EQ3_B1_C_SHIFT
- ARIZONA_EQ3_B1_C_WIDTH
- ARIZONA_EQ3_B1_GAIN_MASK
- ARIZONA_EQ3_B1_GAIN_SHIFT
- ARIZONA_EQ3_B1_GAIN_WIDTH
- ARIZONA_EQ3_B1_MODE
- ARIZONA_EQ3_B1_MODE_MASK
- ARIZONA_EQ3_B1_MODE_SHIFT
- ARIZONA_EQ3_B1_MODE_WIDTH
- ARIZONA_EQ3_B1_PG_MASK
- ARIZONA_EQ3_B1_PG_SHIFT
- ARIZONA_EQ3_B1_PG_WIDTH
- ARIZONA_EQ3_B2_A_MASK
- ARIZONA_EQ3_B2_A_SHIFT
- ARIZONA_EQ3_B2_A_WIDTH
- ARIZONA_EQ3_B2_B_MASK
- ARIZONA_EQ3_B2_B_SHIFT
- ARIZONA_EQ3_B2_B_WIDTH
- ARIZONA_EQ3_B2_C_MASK
- ARIZONA_EQ3_B2_C_SHIFT
- ARIZONA_EQ3_B2_C_WIDTH
- ARIZONA_EQ3_B2_GAIN_MASK
- ARIZONA_EQ3_B2_GAIN_SHIFT
- ARIZONA_EQ3_B2_GAIN_WIDTH
- ARIZONA_EQ3_B2_PG_MASK
- ARIZONA_EQ3_B2_PG_SHIFT
- ARIZONA_EQ3_B2_PG_WIDTH
- ARIZONA_EQ3_B3_A_MASK
- ARIZONA_EQ3_B3_A_SHIFT
- ARIZONA_EQ3_B3_A_WIDTH
- ARIZONA_EQ3_B3_B_MASK
- ARIZONA_EQ3_B3_B_SHIFT
- ARIZONA_EQ3_B3_B_WIDTH
- ARIZONA_EQ3_B3_C_MASK
- ARIZONA_EQ3_B3_C_SHIFT
- ARIZONA_EQ3_B3_C_WIDTH
- ARIZONA_EQ3_B3_GAIN_MASK
- ARIZONA_EQ3_B3_GAIN_SHIFT
- ARIZONA_EQ3_B3_GAIN_WIDTH
- ARIZONA_EQ3_B3_PG_MASK
- ARIZONA_EQ3_B3_PG_SHIFT
- ARIZONA_EQ3_B3_PG_WIDTH
- ARIZONA_EQ3_B4_A_MASK
- ARIZONA_EQ3_B4_A_SHIFT
- ARIZONA_EQ3_B4_A_WIDTH
- ARIZONA_EQ3_B4_B_MASK
- ARIZONA_EQ3_B4_B_SHIFT
- ARIZONA_EQ3_B4_B_WIDTH
- ARIZONA_EQ3_B4_C_MASK
- ARIZONA_EQ3_B4_C_SHIFT
- ARIZONA_EQ3_B4_C_WIDTH
- ARIZONA_EQ3_B4_GAIN_MASK
- ARIZONA_EQ3_B4_GAIN_SHIFT
- ARIZONA_EQ3_B4_GAIN_WIDTH
- ARIZONA_EQ3_B4_PG_MASK
- ARIZONA_EQ3_B4_PG_SHIFT
- ARIZONA_EQ3_B4_PG_WIDTH
- ARIZONA_EQ3_B5_A_MASK
- ARIZONA_EQ3_B5_A_SHIFT
- ARIZONA_EQ3_B5_A_WIDTH
- ARIZONA_EQ3_B5_B_MASK
- ARIZONA_EQ3_B5_B_SHIFT
- ARIZONA_EQ3_B5_B_WIDTH
- ARIZONA_EQ3_B5_GAIN_MASK
- ARIZONA_EQ3_B5_GAIN_SHIFT
- ARIZONA_EQ3_B5_GAIN_WIDTH
- ARIZONA_EQ3_B5_PG_MASK
- ARIZONA_EQ3_B5_PG_SHIFT
- ARIZONA_EQ3_B5_PG_WIDTH
- ARIZONA_EQ3_ENA
- ARIZONA_EQ3_ENA_MASK
- ARIZONA_EQ3_ENA_SHIFT
- ARIZONA_EQ3_ENA_WIDTH
- ARIZONA_EQ4MIX_INPUT_1_SOURCE
- ARIZONA_EQ4MIX_INPUT_1_VOLUME
- ARIZONA_EQ4MIX_INPUT_2_SOURCE
- ARIZONA_EQ4MIX_INPUT_2_VOLUME
- ARIZONA_EQ4MIX_INPUT_3_SOURCE
- ARIZONA_EQ4MIX_INPUT_3_VOLUME
- ARIZONA_EQ4MIX_INPUT_4_SOURCE
- ARIZONA_EQ4MIX_INPUT_4_VOLUME
- ARIZONA_EQ4_1
- ARIZONA_EQ4_10
- ARIZONA_EQ4_11
- ARIZONA_EQ4_12
- ARIZONA_EQ4_13
- ARIZONA_EQ4_14
- ARIZONA_EQ4_15
- ARIZONA_EQ4_16
- ARIZONA_EQ4_17
- ARIZONA_EQ4_18
- ARIZONA_EQ4_19
- ARIZONA_EQ4_2
- ARIZONA_EQ4_20
- ARIZONA_EQ4_21
- ARIZONA_EQ4_3
- ARIZONA_EQ4_4
- ARIZONA_EQ4_5
- ARIZONA_EQ4_6
- ARIZONA_EQ4_7
- ARIZONA_EQ4_8
- ARIZONA_EQ4_9
- ARIZONA_EQ4_B1_A_MASK
- ARIZONA_EQ4_B1_A_SHIFT
- ARIZONA_EQ4_B1_A_WIDTH
- ARIZONA_EQ4_B1_B_MASK
- ARIZONA_EQ4_B1_B_SHIFT
- ARIZONA_EQ4_B1_B_WIDTH
- ARIZONA_EQ4_B1_C_MASK
- ARIZONA_EQ4_B1_C_SHIFT
- ARIZONA_EQ4_B1_C_WIDTH
- ARIZONA_EQ4_B1_GAIN_MASK
- ARIZONA_EQ4_B1_GAIN_SHIFT
- ARIZONA_EQ4_B1_GAIN_WIDTH
- ARIZONA_EQ4_B1_MODE
- ARIZONA_EQ4_B1_MODE_MASK
- ARIZONA_EQ4_B1_MODE_SHIFT
- ARIZONA_EQ4_B1_MODE_WIDTH
- ARIZONA_EQ4_B1_PG_MASK
- ARIZONA_EQ4_B1_PG_SHIFT
- ARIZONA_EQ4_B1_PG_WIDTH
- ARIZONA_EQ4_B2_A_MASK
- ARIZONA_EQ4_B2_A_SHIFT
- ARIZONA_EQ4_B2_A_WIDTH
- ARIZONA_EQ4_B2_B_MASK
- ARIZONA_EQ4_B2_B_SHIFT
- ARIZONA_EQ4_B2_B_WIDTH
- ARIZONA_EQ4_B2_C_MASK
- ARIZONA_EQ4_B2_C_SHIFT
- ARIZONA_EQ4_B2_C_WIDTH
- ARIZONA_EQ4_B2_GAIN_MASK
- ARIZONA_EQ4_B2_GAIN_SHIFT
- ARIZONA_EQ4_B2_GAIN_WIDTH
- ARIZONA_EQ4_B2_PG_MASK
- ARIZONA_EQ4_B2_PG_SHIFT
- ARIZONA_EQ4_B2_PG_WIDTH
- ARIZONA_EQ4_B3_A_MASK
- ARIZONA_EQ4_B3_A_SHIFT
- ARIZONA_EQ4_B3_A_WIDTH
- ARIZONA_EQ4_B3_B_MASK
- ARIZONA_EQ4_B3_B_SHIFT
- ARIZONA_EQ4_B3_B_WIDTH
- ARIZONA_EQ4_B3_C_MASK
- ARIZONA_EQ4_B3_C_SHIFT
- ARIZONA_EQ4_B3_C_WIDTH
- ARIZONA_EQ4_B3_GAIN_MASK
- ARIZONA_EQ4_B3_GAIN_SHIFT
- ARIZONA_EQ4_B3_GAIN_WIDTH
- ARIZONA_EQ4_B3_PG_MASK
- ARIZONA_EQ4_B3_PG_SHIFT
- ARIZONA_EQ4_B3_PG_WIDTH
- ARIZONA_EQ4_B4_A_MASK
- ARIZONA_EQ4_B4_A_SHIFT
- ARIZONA_EQ4_B4_A_WIDTH
- ARIZONA_EQ4_B4_B_MASK
- ARIZONA_EQ4_B4_B_SHIFT
- ARIZONA_EQ4_B4_B_WIDTH
- ARIZONA_EQ4_B4_C_MASK
- ARIZONA_EQ4_B4_C_SHIFT
- ARIZONA_EQ4_B4_C_WIDTH
- ARIZONA_EQ4_B4_GAIN_MASK
- ARIZONA_EQ4_B4_GAIN_SHIFT
- ARIZONA_EQ4_B4_GAIN_WIDTH
- ARIZONA_EQ4_B4_PG_MASK
- ARIZONA_EQ4_B4_PG_SHIFT
- ARIZONA_EQ4_B4_PG_WIDTH
- ARIZONA_EQ4_B5_A_MASK
- ARIZONA_EQ4_B5_A_SHIFT
- ARIZONA_EQ4_B5_A_WIDTH
- ARIZONA_EQ4_B5_B_MASK
- ARIZONA_EQ4_B5_B_SHIFT
- ARIZONA_EQ4_B5_B_WIDTH
- ARIZONA_EQ4_B5_GAIN_MASK
- ARIZONA_EQ4_B5_GAIN_SHIFT
- ARIZONA_EQ4_B5_GAIN_WIDTH
- ARIZONA_EQ4_B5_PG_MASK
- ARIZONA_EQ4_B5_PG_SHIFT
- ARIZONA_EQ4_B5_PG_WIDTH
- ARIZONA_EQ4_ENA
- ARIZONA_EQ4_ENA_MASK
- ARIZONA_EQ4_ENA_SHIFT
- ARIZONA_EQ4_ENA_WIDTH
- ARIZONA_EQ_CONTROL
- ARIZONA_EXT_NG_SEL_CLR
- ARIZONA_EXT_NG_SEL_CLR_MASK
- ARIZONA_EXT_NG_SEL_CLR_SHIFT
- ARIZONA_EXT_NG_SEL_CLR_WIDTH
- ARIZONA_EXT_NG_SEL_SET
- ARIZONA_EXT_NG_SEL_SET_MASK
- ARIZONA_EXT_NG_SEL_SET_SHIFT
- ARIZONA_EXT_NG_SEL_SET_WIDTH
- ARIZONA_FCL_ADC_REFORMATTER_CONTROL
- ARIZONA_FCL_COEFF_END
- ARIZONA_FCL_COEFF_START
- ARIZONA_FCL_FILTER_CONTROL
- ARIZONA_FCL_MIC_MODE_SEL
- ARIZONA_FCL_MIC_MODE_SEL_SHIFT
- ARIZONA_FCL_MIC_MODE_SEL_WIDTH
- ARIZONA_FCR_ADC_REFORMATTER_CONTROL
- ARIZONA_FCR_COEFF_END
- ARIZONA_FCR_COEFF_START
- ARIZONA_FCR_FILTER_CONTROL
- ARIZONA_FCR_MIC_MODE_SEL
- ARIZONA_FCR_MIC_MODE_SEL_SHIFT
- ARIZONA_FCR_MIC_MODE_SEL_WIDTH
- ARIZONA_FLL1_CLK_REF_DIV_MASK
- ARIZONA_FLL1_CLK_REF_DIV_SHIFT
- ARIZONA_FLL1_CLK_REF_DIV_WIDTH
- ARIZONA_FLL1_CLK_REF_SRC_MASK
- ARIZONA_FLL1_CLK_REF_SRC_SHIFT
- ARIZONA_FLL1_CLK_REF_SRC_WIDTH
- ARIZONA_FLL1_CLK_SYNC_DIV_MASK
- ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT
- ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH
- ARIZONA_FLL1_CLK_SYNC_SRC_MASK
- ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT
- ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH
- ARIZONA_FLL1_CLOCK_OK_EINT1
- ARIZONA_FLL1_CLOCK_OK_EINT1_MASK
- ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT
- ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH
- ARIZONA_FLL1_CLOCK_OK_EINT2
- ARIZONA_FLL1_CLOCK_OK_EINT2_MASK
- ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT
- ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH
- ARIZONA_FLL1_CLOCK_OK_STS
- ARIZONA_FLL1_CLOCK_OK_STS_MASK
- ARIZONA_FLL1_CLOCK_OK_STS_SHIFT
- ARIZONA_FLL1_CLOCK_OK_STS_WIDTH
- ARIZONA_FLL1_CONTROL_1
- ARIZONA_FLL1_CONTROL_2
- ARIZONA_FLL1_CONTROL_3
- ARIZONA_FLL1_CONTROL_4
- ARIZONA_FLL1_CONTROL_5
- ARIZONA_FLL1_CONTROL_6
- ARIZONA_FLL1_CONTROL_7
- ARIZONA_FLL1_CTRL_UPD
- ARIZONA_FLL1_CTRL_UPD_MASK
- ARIZONA_FLL1_CTRL_UPD_SHIFT
- ARIZONA_FLL1_CTRL_UPD_WIDTH
- ARIZONA_FLL1_ENA
- ARIZONA_FLL1_ENA_MASK
- ARIZONA_FLL1_ENA_SHIFT
- ARIZONA_FLL1_ENA_WIDTH
- ARIZONA_FLL1_FRATIO_MASK
- ARIZONA_FLL1_FRATIO_SHIFT
- ARIZONA_FLL1_FRATIO_WIDTH
- ARIZONA_FLL1_FRC_INTEG_UPD
- ARIZONA_FLL1_FRC_INTEG_UPD_MASK
- ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT
- ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH
- ARIZONA_FLL1_FRC_INTEG_VAL_MASK
- ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT
- ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH
- ARIZONA_FLL1_FREERUN
- ARIZONA_FLL1_FREERUN_MASK
- ARIZONA_FLL1_FREERUN_SHIFT
- ARIZONA_FLL1_FREERUN_WIDTH
- ARIZONA_FLL1_GAIN_MASK
- ARIZONA_FLL1_GAIN_SHIFT
- ARIZONA_FLL1_GAIN_WIDTH
- ARIZONA_FLL1_GPDIV_ENA
- ARIZONA_FLL1_GPDIV_ENA_MASK
- ARIZONA_FLL1_GPDIV_ENA_SHIFT
- ARIZONA_FLL1_GPDIV_ENA_WIDTH
- ARIZONA_FLL1_GPDIV_MASK
- ARIZONA_FLL1_GPDIV_SHIFT
- ARIZONA_FLL1_GPDIV_WIDTH
- ARIZONA_FLL1_GPIO_CLOCK
- ARIZONA_FLL1_LAMBDA_MASK
- ARIZONA_FLL1_LAMBDA_SHIFT
- ARIZONA_FLL1_LAMBDA_WIDTH
- ARIZONA_FLL1_LOCK_EINT1
- ARIZONA_FLL1_LOCK_EINT1_MASK
- ARIZONA_FLL1_LOCK_EINT1_SHIFT
- ARIZONA_FLL1_LOCK_EINT1_WIDTH
- ARIZONA_FLL1_LOCK_EINT2
- ARIZONA_FLL1_LOCK_EINT2_MASK
- ARIZONA_FLL1_LOCK_EINT2_SHIFT
- ARIZONA_FLL1_LOCK_EINT2_WIDTH
- ARIZONA_FLL1_LOCK_STS
- ARIZONA_FLL1_LOCK_STS_MASK
- ARIZONA_FLL1_LOCK_STS_SHIFT
- ARIZONA_FLL1_LOCK_STS_WIDTH
- ARIZONA_FLL1_LOOP_FILTER_TEST_1
- ARIZONA_FLL1_NCO_TEST_0
- ARIZONA_FLL1_N_MASK
- ARIZONA_FLL1_N_SHIFT
- ARIZONA_FLL1_N_WIDTH
- ARIZONA_FLL1_OUTDIV_MASK
- ARIZONA_FLL1_OUTDIV_SHIFT
- ARIZONA_FLL1_OUTDIV_WIDTH
- ARIZONA_FLL1_SPREAD_SPECTRUM
- ARIZONA_FLL1_SS_AMPL_MASK
- ARIZONA_FLL1_SS_AMPL_SHIFT
- ARIZONA_FLL1_SS_AMPL_WIDTH
- ARIZONA_FLL1_SS_FREQ_MASK
- ARIZONA_FLL1_SS_FREQ_SHIFT
- ARIZONA_FLL1_SS_FREQ_WIDTH
- ARIZONA_FLL1_SS_SEL_MASK
- ARIZONA_FLL1_SS_SEL_SHIFT
- ARIZONA_FLL1_SS_SEL_WIDTH
- ARIZONA_FLL1_SYNCHRONISER_1
- ARIZONA_FLL1_SYNCHRONISER_2
- ARIZONA_FLL1_SYNCHRONISER_3
- ARIZONA_FLL1_SYNCHRONISER_4
- ARIZONA_FLL1_SYNCHRONISER_5
- ARIZONA_FLL1_SYNCHRONISER_6
- ARIZONA_FLL1_SYNCHRONISER_7
- ARIZONA_FLL1_SYNC_BW
- ARIZONA_FLL1_SYNC_BW_MASK
- ARIZONA_FLL1_SYNC_BW_SHIFT
- ARIZONA_FLL1_SYNC_BW_WIDTH
- ARIZONA_FLL1_SYNC_ENA
- ARIZONA_FLL1_SYNC_ENA_MASK
- ARIZONA_FLL1_SYNC_ENA_SHIFT
- ARIZONA_FLL1_SYNC_ENA_WIDTH
- ARIZONA_FLL1_SYNC_FRATIO_MASK
- ARIZONA_FLL1_SYNC_FRATIO_SHIFT
- ARIZONA_FLL1_SYNC_FRATIO_WIDTH
- ARIZONA_FLL1_SYNC_GAIN_MASK
- ARIZONA_FLL1_SYNC_GAIN_SHIFT
- ARIZONA_FLL1_SYNC_GAIN_WIDTH
- ARIZONA_FLL1_SYNC_LAMBDA_MASK
- ARIZONA_FLL1_SYNC_LAMBDA_SHIFT
- ARIZONA_FLL1_SYNC_LAMBDA_WIDTH
- ARIZONA_FLL1_SYNC_N_MASK
- ARIZONA_FLL1_SYNC_N_SHIFT
- ARIZONA_FLL1_SYNC_N_WIDTH
- ARIZONA_FLL1_SYNC_THETA_MASK
- ARIZONA_FLL1_SYNC_THETA_SHIFT
- ARIZONA_FLL1_SYNC_THETA_WIDTH
- ARIZONA_FLL1_THETA_MASK
- ARIZONA_FLL1_THETA_SHIFT
- ARIZONA_FLL1_THETA_WIDTH
- ARIZONA_FLL2_CLK_REF_DIV_MASK
- ARIZONA_FLL2_CLK_REF_DIV_SHIFT
- ARIZONA_FLL2_CLK_REF_DIV_WIDTH
- ARIZONA_FLL2_CLK_REF_SRC_MASK
- ARIZONA_FLL2_CLK_REF_SRC_SHIFT
- ARIZONA_FLL2_CLK_REF_SRC_WIDTH
- ARIZONA_FLL2_CLK_SYNC_DIV_MASK
- ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT
- ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH
- ARIZONA_FLL2_CLK_SYNC_SRC_MASK
- ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT
- ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH
- ARIZONA_FLL2_CLOCK_OK_EINT1
- ARIZONA_FLL2_CLOCK_OK_EINT1_MASK
- ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT
- ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH
- ARIZONA_FLL2_CLOCK_OK_EINT2
- ARIZONA_FLL2_CLOCK_OK_EINT2_MASK
- ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT
- ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH
- ARIZONA_FLL2_CLOCK_OK_STS
- ARIZONA_FLL2_CLOCK_OK_STS_MASK
- ARIZONA_FLL2_CLOCK_OK_STS_SHIFT
- ARIZONA_FLL2_CLOCK_OK_STS_WIDTH
- ARIZONA_FLL2_CONTROL_1
- ARIZONA_FLL2_CONTROL_2
- ARIZONA_FLL2_CONTROL_3
- ARIZONA_FLL2_CONTROL_4
- ARIZONA_FLL2_CONTROL_5
- ARIZONA_FLL2_CONTROL_6
- ARIZONA_FLL2_CONTROL_7
- ARIZONA_FLL2_CTRL_UPD
- ARIZONA_FLL2_CTRL_UPD_MASK
- ARIZONA_FLL2_CTRL_UPD_SHIFT
- ARIZONA_FLL2_CTRL_UPD_WIDTH
- ARIZONA_FLL2_ENA
- ARIZONA_FLL2_ENA_MASK
- ARIZONA_FLL2_ENA_SHIFT
- ARIZONA_FLL2_ENA_WIDTH
- ARIZONA_FLL2_FRATIO_MASK
- ARIZONA_FLL2_FRATIO_SHIFT
- ARIZONA_FLL2_FRATIO_WIDTH
- ARIZONA_FLL2_FRC_INTEG_UPD
- ARIZONA_FLL2_FRC_INTEG_UPD_MASK
- ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT
- ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH
- ARIZONA_FLL2_FRC_INTEG_VAL_MASK
- ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT
- ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH
- ARIZONA_FLL2_FREERUN
- ARIZONA_FLL2_FREERUN_MASK
- ARIZONA_FLL2_FREERUN_SHIFT
- ARIZONA_FLL2_FREERUN_WIDTH
- ARIZONA_FLL2_GAIN_MASK
- ARIZONA_FLL2_GAIN_SHIFT
- ARIZONA_FLL2_GAIN_WIDTH
- ARIZONA_FLL2_GPDIV_ENA
- ARIZONA_FLL2_GPDIV_ENA_MASK
- ARIZONA_FLL2_GPDIV_ENA_SHIFT
- ARIZONA_FLL2_GPDIV_ENA_WIDTH
- ARIZONA_FLL2_GPDIV_MASK
- ARIZONA_FLL2_GPDIV_SHIFT
- ARIZONA_FLL2_GPDIV_WIDTH
- ARIZONA_FLL2_GPIO_CLOCK
- ARIZONA_FLL2_LAMBDA_MASK
- ARIZONA_FLL2_LAMBDA_SHIFT
- ARIZONA_FLL2_LAMBDA_WIDTH
- ARIZONA_FLL2_LOCK_EINT1
- ARIZONA_FLL2_LOCK_EINT1_MASK
- ARIZONA_FLL2_LOCK_EINT1_SHIFT
- ARIZONA_FLL2_LOCK_EINT1_WIDTH
- ARIZONA_FLL2_LOCK_EINT2
- ARIZONA_FLL2_LOCK_EINT2_MASK
- ARIZONA_FLL2_LOCK_EINT2_SHIFT
- ARIZONA_FLL2_LOCK_EINT2_WIDTH
- ARIZONA_FLL2_LOCK_STS
- ARIZONA_FLL2_LOCK_STS_MASK
- ARIZONA_FLL2_LOCK_STS_SHIFT
- ARIZONA_FLL2_LOCK_STS_WIDTH
- ARIZONA_FLL2_LOOP_FILTER_TEST_1
- ARIZONA_FLL2_NCO_TEST_0
- ARIZONA_FLL2_N_MASK
- ARIZONA_FLL2_N_SHIFT
- ARIZONA_FLL2_N_WIDTH
- ARIZONA_FLL2_OUTDIV_MASK
- ARIZONA_FLL2_OUTDIV_SHIFT
- ARIZONA_FLL2_OUTDIV_WIDTH
- ARIZONA_FLL2_SPREAD_SPECTRUM
- ARIZONA_FLL2_SS_AMPL_MASK
- ARIZONA_FLL2_SS_AMPL_SHIFT
- ARIZONA_FLL2_SS_AMPL_WIDTH
- ARIZONA_FLL2_SS_FREQ_MASK
- ARIZONA_FLL2_SS_FREQ_SHIFT
- ARIZONA_FLL2_SS_FREQ_WIDTH
- ARIZONA_FLL2_SS_SEL_MASK
- ARIZONA_FLL2_SS_SEL_SHIFT
- ARIZONA_FLL2_SS_SEL_WIDTH
- ARIZONA_FLL2_SYNCHRONISER_1
- ARIZONA_FLL2_SYNCHRONISER_2
- ARIZONA_FLL2_SYNCHRONISER_3
- ARIZONA_FLL2_SYNCHRONISER_4
- ARIZONA_FLL2_SYNCHRONISER_5
- ARIZONA_FLL2_SYNCHRONISER_6
- ARIZONA_FLL2_SYNCHRONISER_7
- ARIZONA_FLL2_SYNC_BW
- ARIZONA_FLL2_SYNC_BW_MASK
- ARIZONA_FLL2_SYNC_BW_SHIFT
- ARIZONA_FLL2_SYNC_BW_WIDTH
- ARIZONA_FLL2_SYNC_ENA
- ARIZONA_FLL2_SYNC_ENA_MASK
- ARIZONA_FLL2_SYNC_ENA_SHIFT
- ARIZONA_FLL2_SYNC_ENA_WIDTH
- ARIZONA_FLL2_SYNC_FRATIO_MASK
- ARIZONA_FLL2_SYNC_FRATIO_SHIFT
- ARIZONA_FLL2_SYNC_FRATIO_WIDTH
- ARIZONA_FLL2_SYNC_GAIN_MASK
- ARIZONA_FLL2_SYNC_GAIN_SHIFT
- ARIZONA_FLL2_SYNC_GAIN_WIDTH
- ARIZONA_FLL2_SYNC_LAMBDA_MASK
- ARIZONA_FLL2_SYNC_LAMBDA_SHIFT
- ARIZONA_FLL2_SYNC_LAMBDA_WIDTH
- ARIZONA_FLL2_SYNC_N_MASK
- ARIZONA_FLL2_SYNC_N_SHIFT
- ARIZONA_FLL2_SYNC_N_WIDTH
- ARIZONA_FLL2_SYNC_THETA_MASK
- ARIZONA_FLL2_SYNC_THETA_SHIFT
- ARIZONA_FLL2_SYNC_THETA_WIDTH
- ARIZONA_FLL2_THETA_MASK
- ARIZONA_FLL2_THETA_SHIFT
- ARIZONA_FLL2_THETA_WIDTH
- ARIZONA_FLL_MAX_FRATIO
- ARIZONA_FLL_MAX_FREF
- ARIZONA_FLL_MAX_OUTDIV
- ARIZONA_FLL_MAX_REFDIV
- ARIZONA_FLL_MIN_FVCO
- ARIZONA_FLL_MIN_OUTDIV
- ARIZONA_FLL_NAME_LEN
- ARIZONA_FLL_SRC_AIF1BCLK
- ARIZONA_FLL_SRC_AIF1LRCLK
- ARIZONA_FLL_SRC_AIF2BCLK
- ARIZONA_FLL_SRC_AIF2LRCLK
- ARIZONA_FLL_SRC_AIF3BCLK
- ARIZONA_FLL_SRC_AIF3LRCLK
- ARIZONA_FLL_SRC_FLL1
- ARIZONA_FLL_SRC_FLL2
- ARIZONA_FLL_SRC_MCLK1
- ARIZONA_FLL_SRC_MCLK2
- ARIZONA_FLL_SRC_NONE
- ARIZONA_FLL_SRC_SLIMCLK
- ARIZONA_FLL_VCO_CORNER
- ARIZONA_FMT_DSP_MODE_A
- ARIZONA_FMT_DSP_MODE_B
- ARIZONA_FMT_I2S_MODE
- ARIZONA_FMT_LEFT_JUSTIFIED_MODE
- ARIZONA_FRAMER_REF_GEAR_MASK
- ARIZONA_FRAMER_REF_GEAR_SHIFT
- ARIZONA_FRAMER_REF_GEAR_WIDTH
- ARIZONA_FRF_COEFF_1
- ARIZONA_FRF_COEFF_2
- ARIZONA_FRF_COEFF_3
- ARIZONA_FRF_COEFF_4
- ARIZONA_FX_CORE_OVERCLOCKED_STS
- ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK
- ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT
- ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH
- ARIZONA_FX_CTRL1
- ARIZONA_FX_CTRL2
- ARIZONA_FX_RATE_MASK
- ARIZONA_FX_RATE_SHIFT
- ARIZONA_FX_RATE_WIDTH
- ARIZONA_FX_STS_MASK
- ARIZONA_FX_STS_SHIFT
- ARIZONA_FX_STS_WIDTH
- ARIZONA_FX_UNDERCLOCKED_STS
- ARIZONA_FX_UNDERCLOCKED_STS_MASK
- ARIZONA_FX_UNDERCLOCKED_STS_SHIFT
- ARIZONA_FX_UNDERCLOCKED_STS_WIDTH
- ARIZONA_GAINMUX_CONTROLS
- ARIZONA_GP1_EINT1
- ARIZONA_GP1_EINT1_MASK
- ARIZONA_GP1_EINT1_SHIFT
- ARIZONA_GP1_EINT1_WIDTH
- ARIZONA_GP1_EINT2
- ARIZONA_GP1_EINT2_MASK
- ARIZONA_GP1_EINT2_SHIFT
- ARIZONA_GP1_EINT2_WIDTH
- ARIZONA_GP2_EINT1
- ARIZONA_GP2_EINT1_MASK
- ARIZONA_GP2_EINT1_SHIFT
- ARIZONA_GP2_EINT1_WIDTH
- ARIZONA_GP2_EINT2
- ARIZONA_GP2_EINT2_MASK
- ARIZONA_GP2_EINT2_SHIFT
- ARIZONA_GP2_EINT2_WIDTH
- ARIZONA_GP3_EINT1
- ARIZONA_GP3_EINT1_MASK
- ARIZONA_GP3_EINT1_SHIFT
- ARIZONA_GP3_EINT1_WIDTH
- ARIZONA_GP3_EINT2
- ARIZONA_GP3_EINT2_MASK
- ARIZONA_GP3_EINT2_SHIFT
- ARIZONA_GP3_EINT2_WIDTH
- ARIZONA_GP4_EINT1
- ARIZONA_GP4_EINT1_MASK
- ARIZONA_GP4_EINT1_SHIFT
- ARIZONA_GP4_EINT1_WIDTH
- ARIZONA_GP4_EINT2
- ARIZONA_GP4_EINT2_MASK
- ARIZONA_GP4_EINT2_SHIFT
- ARIZONA_GP4_EINT2_WIDTH
- ARIZONA_GP5_FALL_EINT1
- ARIZONA_GP5_FALL_EINT1_MASK
- ARIZONA_GP5_FALL_EINT1_SHIFT
- ARIZONA_GP5_FALL_EINT1_WIDTH
- ARIZONA_GP5_FALL_EINT2
- ARIZONA_GP5_FALL_EINT2_MASK
- ARIZONA_GP5_FALL_EINT2_SHIFT
- ARIZONA_GP5_FALL_EINT2_WIDTH
- ARIZONA_GP5_FALL_TRIG_STS
- ARIZONA_GP5_FALL_TRIG_STS_MASK
- ARIZONA_GP5_FALL_TRIG_STS_SHIFT
- ARIZONA_GP5_FALL_TRIG_STS_WIDTH
- ARIZONA_GP5_RISE_EINT1
- ARIZONA_GP5_RISE_EINT1_MASK
- ARIZONA_GP5_RISE_EINT1_SHIFT
- ARIZONA_GP5_RISE_EINT1_WIDTH
- ARIZONA_GP5_RISE_EINT2
- ARIZONA_GP5_RISE_EINT2_MASK
- ARIZONA_GP5_RISE_EINT2_SHIFT
- ARIZONA_GP5_RISE_EINT2_WIDTH
- ARIZONA_GP5_RISE_TRIG_STS
- ARIZONA_GP5_RISE_TRIG_STS_MASK
- ARIZONA_GP5_RISE_TRIG_STS_SHIFT
- ARIZONA_GP5_RISE_TRIG_STS_WIDTH
- ARIZONA_GP5_STS
- ARIZONA_GP5_STS_MASK
- ARIZONA_GP5_STS_SHIFT
- ARIZONA_GP5_STS_WIDTH
- ARIZONA_GPIO1_CTRL
- ARIZONA_GPIO2_CTRL
- ARIZONA_GPIO3_CTRL
- ARIZONA_GPIO4_CTRL
- ARIZONA_GPIO5_CTRL
- ARIZONA_GPIO_DEBOUNCE_CONFIG
- ARIZONA_GPN_DB
- ARIZONA_GPN_DB_MASK
- ARIZONA_GPN_DB_SHIFT
- ARIZONA_GPN_DB_WIDTH
- ARIZONA_GPN_DIR
- ARIZONA_GPN_DIR_MASK
- ARIZONA_GPN_DIR_SHIFT
- ARIZONA_GPN_DIR_WIDTH
- ARIZONA_GPN_FN_MASK
- ARIZONA_GPN_FN_SHIFT
- ARIZONA_GPN_FN_WIDTH
- ARIZONA_GPN_LVL
- ARIZONA_GPN_LVL_MASK
- ARIZONA_GPN_LVL_SHIFT
- ARIZONA_GPN_LVL_WIDTH
- ARIZONA_GPN_OP_CFG
- ARIZONA_GPN_OP_CFG_MASK
- ARIZONA_GPN_OP_CFG_SHIFT
- ARIZONA_GPN_OP_CFG_WIDTH
- ARIZONA_GPN_PD
- ARIZONA_GPN_PD_MASK
- ARIZONA_GPN_PD_SHIFT
- ARIZONA_GPN_PD_WIDTH
- ARIZONA_GPN_POL
- ARIZONA_GPN_POL_MASK
- ARIZONA_GPN_POL_SHIFT
- ARIZONA_GPN_POL_WIDTH
- ARIZONA_GPN_PU
- ARIZONA_GPN_PU_MASK
- ARIZONA_GPN_PU_SHIFT
- ARIZONA_GPN_PU_WIDTH
- ARIZONA_GPSW_CLAMP_DISABLED
- ARIZONA_GPSW_CLAMP_ENABLED
- ARIZONA_GPSW_CLOSED
- ARIZONA_GPSW_OPEN
- ARIZONA_GP_DBTIME_MASK
- ARIZONA_GP_DBTIME_SHIFT
- ARIZONA_GP_DBTIME_WIDTH
- ARIZONA_GP_DEFAULT
- ARIZONA_GP_FN_AIF1_CONFIG_ERROR
- ARIZONA_GP_FN_AIF2_CONFIG_ERROR
- ARIZONA_GP_FN_AIF3_CONFIG_ERROR
- ARIZONA_GP_FN_ASRC1_LOCK
- ARIZONA_GP_FN_ASRC2_LOCK
- ARIZONA_GP_FN_ASRC_CONFIG_ERROR
- ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS
- ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED
- ARIZONA_GP_FN_ASYNC_OPCLK
- ARIZONA_GP_FN_BOOT_DONE
- ARIZONA_GP_FN_CIF_ADDRESS_ERROR
- ARIZONA_GP_FN_DRC1_ANTICLIP
- ARIZONA_GP_FN_DRC1_DECAY
- ARIZONA_GP_FN_DRC1_NOISE
- ARIZONA_GP_FN_DRC1_QUICK_RELEASE
- ARIZONA_GP_FN_DRC1_SIGNAL_DETECT
- ARIZONA_GP_FN_DRC2_ANTICLIP
- ARIZONA_GP_FN_DRC2_DECAY
- ARIZONA_GP_FN_DRC2_NOISE
- ARIZONA_GP_FN_DRC2_QUICK_RELEASE
- ARIZONA_GP_FN_DRC2_SIGNAL_DETECT
- ARIZONA_GP_FN_DSP1_RAM_READY
- ARIZONA_GP_FN_DSP_IRQ1
- ARIZONA_GP_FN_DSP_IRQ2
- ARIZONA_GP_FN_FLL1_CLOCK_OK
- ARIZONA_GP_FN_FLL1_LOCK
- ARIZONA_GP_FN_FLL1_OUT
- ARIZONA_GP_FN_FLL2_CLOCK_OK
- ARIZONA_GP_FN_FLL2_LOCK
- ARIZONA_GP_FN_FLL2_OUT
- ARIZONA_GP_FN_GPIO
- ARIZONA_GP_FN_HEADPHONE_DET
- ARIZONA_GP_FN_IRQ1
- ARIZONA_GP_FN_IRQ2
- ARIZONA_GP_FN_MIC_DET
- ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE
- ARIZONA_GP_FN_OPCLK
- ARIZONA_GP_FN_OVERCLOCKED
- ARIZONA_GP_FN_PWM1
- ARIZONA_GP_FN_PWM2
- ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN
- ARIZONA_GP_FN_SPK_TEMP_WARNING
- ARIZONA_GP_FN_SYSCLK_ENA_STATUS
- ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED
- ARIZONA_GP_FN_TXLRCLK
- ARIZONA_GP_FN_UNDERCLOCKED
- ARIZONA_GP_FN_WSEQ_STATUS
- ARIZONA_GP_INPUT
- ARIZONA_GP_OUTPUT
- ARIZONA_GP_SWITCH_1
- ARIZONA_HAPTICS_CONTROL_1
- ARIZONA_HAPTICS_CONTROL_2
- ARIZONA_HAPTICS_PHASE_1_DURATION
- ARIZONA_HAPTICS_PHASE_1_INTENSITY
- ARIZONA_HAPTICS_PHASE_2_DURATION
- ARIZONA_HAPTICS_PHASE_2_INTENSITY
- ARIZONA_HAPTICS_PHASE_3_DURATION
- ARIZONA_HAPTICS_PHASE_3_INTENSITY
- ARIZONA_HAPTICS_STATUS
- ARIZONA_HAP_ACT
- ARIZONA_HAP_ACT_ERM
- ARIZONA_HAP_ACT_LRA
- ARIZONA_HAP_ACT_MASK
- ARIZONA_HAP_ACT_SHIFT
- ARIZONA_HAP_ACT_WIDTH
- ARIZONA_HAP_CTRL_MASK
- ARIZONA_HAP_CTRL_SHIFT
- ARIZONA_HAP_CTRL_WIDTH
- ARIZONA_HAP_RATE_MASK
- ARIZONA_HAP_RATE_SHIFT
- ARIZONA_HAP_RATE_WIDTH
- ARIZONA_HEADPHONE_DETECT_1
- ARIZONA_HEADPHONE_DETECT_2
- ARIZONA_HP1L_DONE_EINT1
- ARIZONA_HP1L_DONE_EINT1_MASK
- ARIZONA_HP1L_DONE_EINT1_SHIFT
- ARIZONA_HP1L_DONE_EINT1_WIDTH
- ARIZONA_HP1L_DONE_EINT2
- ARIZONA_HP1L_DONE_EINT2_MASK
- ARIZONA_HP1L_DONE_EINT2_SHIFT
- ARIZONA_HP1L_DONE_EINT2_WIDTH
- ARIZONA_HP1L_DONE_STS
- ARIZONA_HP1L_DONE_STS_MASK
- ARIZONA_HP1L_DONE_STS_SHIFT
- ARIZONA_HP1L_DONE_STS_WIDTH
- ARIZONA_HP1L_FLWR
- ARIZONA_HP1L_FLWR_MASK
- ARIZONA_HP1L_FLWR_SHIFT
- ARIZONA_HP1L_FLWR_WIDTH
- ARIZONA_HP1L_SC_NEG_EINT1
- ARIZONA_HP1L_SC_NEG_EINT1_MASK
- ARIZONA_HP1L_SC_NEG_EINT1_SHIFT
- ARIZONA_HP1L_SC_NEG_EINT1_WIDTH
- ARIZONA_HP1L_SC_NEG_EINT2
- ARIZONA_HP1L_SC_NEG_EINT2_MASK
- ARIZONA_HP1L_SC_NEG_EINT2_SHIFT
- ARIZONA_HP1L_SC_NEG_EINT2_WIDTH
- ARIZONA_HP1L_SC_NEG_STS
- ARIZONA_HP1L_SC_NEG_STS_MASK
- ARIZONA_HP1L_SC_NEG_STS_SHIFT
- ARIZONA_HP1L_SC_NEG_STS_WIDTH
- ARIZONA_HP1L_SC_POS_EINT1
- ARIZONA_HP1L_SC_POS_EINT1_MASK
- ARIZONA_HP1L_SC_POS_EINT1_SHIFT
- ARIZONA_HP1L_SC_POS_EINT1_WIDTH
- ARIZONA_HP1L_SC_POS_EINT2
- ARIZONA_HP1L_SC_POS_EINT2_MASK
- ARIZONA_HP1L_SC_POS_EINT2_SHIFT
- ARIZONA_HP1L_SC_POS_EINT2_WIDTH
- ARIZONA_HP1L_SC_POS_STS
- ARIZONA_HP1L_SC_POS_STS_MASK
- ARIZONA_HP1L_SC_POS_STS_SHIFT
- ARIZONA_HP1L_SC_POS_STS_WIDTH
- ARIZONA_HP1L_SHRTI
- ARIZONA_HP1L_SHRTI_MASK
- ARIZONA_HP1L_SHRTI_SHIFT
- ARIZONA_HP1L_SHRTI_WIDTH
- ARIZONA_HP1L_SHRTO
- ARIZONA_HP1L_SHRTO_MASK
- ARIZONA_HP1L_SHRTO_SHIFT
- ARIZONA_HP1L_SHRTO_WIDTH
- ARIZONA_HP1R_DONE_EINT1
- ARIZONA_HP1R_DONE_EINT1_MASK
- ARIZONA_HP1R_DONE_EINT1_SHIFT
- ARIZONA_HP1R_DONE_EINT1_WIDTH
- ARIZONA_HP1R_DONE_EINT2
- ARIZONA_HP1R_DONE_EINT2_MASK
- ARIZONA_HP1R_DONE_EINT2_SHIFT
- ARIZONA_HP1R_DONE_EINT2_WIDTH
- ARIZONA_HP1R_DONE_STS
- ARIZONA_HP1R_DONE_STS_MASK
- ARIZONA_HP1R_DONE_STS_SHIFT
- ARIZONA_HP1R_DONE_STS_WIDTH
- ARIZONA_HP1R_FLWR
- ARIZONA_HP1R_FLWR_MASK
- ARIZONA_HP1R_FLWR_SHIFT
- ARIZONA_HP1R_FLWR_WIDTH
- ARIZONA_HP1R_SC_NEG_EINT1
- ARIZONA_HP1R_SC_NEG_EINT1_MASK
- ARIZONA_HP1R_SC_NEG_EINT1_SHIFT
- ARIZONA_HP1R_SC_NEG_EINT1_WIDTH
- ARIZONA_HP1R_SC_NEG_EINT2
- ARIZONA_HP1R_SC_NEG_EINT2_MASK
- ARIZONA_HP1R_SC_NEG_EINT2_SHIFT
- ARIZONA_HP1R_SC_NEG_EINT2_WIDTH
- ARIZONA_HP1R_SC_NEG_STS
- ARIZONA_HP1R_SC_NEG_STS_MASK
- ARIZONA_HP1R_SC_NEG_STS_SHIFT
- ARIZONA_HP1R_SC_NEG_STS_WIDTH
- ARIZONA_HP1R_SC_POS_EINT1
- ARIZONA_HP1R_SC_POS_EINT1_MASK
- ARIZONA_HP1R_SC_POS_EINT1_SHIFT
- ARIZONA_HP1R_SC_POS_EINT1_WIDTH
- ARIZONA_HP1R_SC_POS_EINT2
- ARIZONA_HP1R_SC_POS_EINT2_MASK
- ARIZONA_HP1R_SC_POS_EINT2_SHIFT
- ARIZONA_HP1R_SC_POS_EINT2_WIDTH
- ARIZONA_HP1R_SC_POS_STS
- ARIZONA_HP1R_SC_POS_STS_MASK
- ARIZONA_HP1R_SC_POS_STS_SHIFT
- ARIZONA_HP1R_SC_POS_STS_WIDTH
- ARIZONA_HP1R_SHRTI
- ARIZONA_HP1R_SHRTI_MASK
- ARIZONA_HP1R_SHRTI_SHIFT
- ARIZONA_HP1R_SHRTI_WIDTH
- ARIZONA_HP1R_SHRTO
- ARIZONA_HP1R_SHRTO_MASK
- ARIZONA_HP1R_SHRTO_SHIFT
- ARIZONA_HP1R_SHRTO_WIDTH
- ARIZONA_HP1_SC_ENA
- ARIZONA_HP1_SC_ENA_MASK
- ARIZONA_HP1_SC_ENA_SHIFT
- ARIZONA_HP1_SC_ENA_WIDTH
- ARIZONA_HP1_SHORT_CIRCUIT_CTRL
- ARIZONA_HP1_TST_CAP_SEL_MASK
- ARIZONA_HP1_TST_CAP_SEL_SHIFT
- ARIZONA_HP1_TST_CAP_SEL_WIDTH
- ARIZONA_HP2L_DONE_EINT1
- ARIZONA_HP2L_DONE_EINT1_MASK
- ARIZONA_HP2L_DONE_EINT1_SHIFT
- ARIZONA_HP2L_DONE_EINT1_WIDTH
- ARIZONA_HP2L_DONE_EINT2
- ARIZONA_HP2L_DONE_EINT2_MASK
- ARIZONA_HP2L_DONE_EINT2_SHIFT
- ARIZONA_HP2L_DONE_EINT2_WIDTH
- ARIZONA_HP2L_DONE_STS
- ARIZONA_HP2L_DONE_STS_MASK
- ARIZONA_HP2L_DONE_STS_SHIFT
- ARIZONA_HP2L_DONE_STS_WIDTH
- ARIZONA_HP2L_SC_NEG_EINT1
- ARIZONA_HP2L_SC_NEG_EINT1_MASK
- ARIZONA_HP2L_SC_NEG_EINT1_SHIFT
- ARIZONA_HP2L_SC_NEG_EINT1_WIDTH
- ARIZONA_HP2L_SC_NEG_EINT2
- ARIZONA_HP2L_SC_NEG_EINT2_MASK
- ARIZONA_HP2L_SC_NEG_EINT2_SHIFT
- ARIZONA_HP2L_SC_NEG_EINT2_WIDTH
- ARIZONA_HP2L_SC_NEG_STS
- ARIZONA_HP2L_SC_NEG_STS_MASK
- ARIZONA_HP2L_SC_NEG_STS_SHIFT
- ARIZONA_HP2L_SC_NEG_STS_WIDTH
- ARIZONA_HP2L_SC_POS_EINT1
- ARIZONA_HP2L_SC_POS_EINT1_MASK
- ARIZONA_HP2L_SC_POS_EINT1_SHIFT
- ARIZONA_HP2L_SC_POS_EINT1_WIDTH
- ARIZONA_HP2L_SC_POS_EINT2
- ARIZONA_HP2L_SC_POS_EINT2_MASK
- ARIZONA_HP2L_SC_POS_EINT2_SHIFT
- ARIZONA_HP2L_SC_POS_EINT2_WIDTH
- ARIZONA_HP2L_SC_POS_STS
- ARIZONA_HP2L_SC_POS_STS_MASK
- ARIZONA_HP2L_SC_POS_STS_SHIFT
- ARIZONA_HP2L_SC_POS_STS_WIDTH
- ARIZONA_HP2R_DONE_EINT1
- ARIZONA_HP2R_DONE_EINT1_MASK
- ARIZONA_HP2R_DONE_EINT1_SHIFT
- ARIZONA_HP2R_DONE_EINT1_WIDTH
- ARIZONA_HP2R_DONE_EINT2
- ARIZONA_HP2R_DONE_EINT2_MASK
- ARIZONA_HP2R_DONE_EINT2_SHIFT
- ARIZONA_HP2R_DONE_EINT2_WIDTH
- ARIZONA_HP2R_DONE_STS
- ARIZONA_HP2R_DONE_STS_MASK
- ARIZONA_HP2R_DONE_STS_SHIFT
- ARIZONA_HP2R_DONE_STS_WIDTH
- ARIZONA_HP2R_SC_NEG_EINT1
- ARIZONA_HP2R_SC_NEG_EINT1_MASK
- ARIZONA_HP2R_SC_NEG_EINT1_SHIFT
- ARIZONA_HP2R_SC_NEG_EINT1_WIDTH
- ARIZONA_HP2R_SC_NEG_EINT2
- ARIZONA_HP2R_SC_NEG_EINT2_MASK
- ARIZONA_HP2R_SC_NEG_EINT2_SHIFT
- ARIZONA_HP2R_SC_NEG_EINT2_WIDTH
- ARIZONA_HP2R_SC_NEG_STS
- ARIZONA_HP2R_SC_NEG_STS_MASK
- ARIZONA_HP2R_SC_NEG_STS_SHIFT
- ARIZONA_HP2R_SC_NEG_STS_WIDTH
- ARIZONA_HP2R_SC_POS_EINT1
- ARIZONA_HP2R_SC_POS_EINT1_MASK
- ARIZONA_HP2R_SC_POS_EINT1_SHIFT
- ARIZONA_HP2R_SC_POS_EINT1_WIDTH
- ARIZONA_HP2R_SC_POS_EINT2
- ARIZONA_HP2R_SC_POS_EINT2_MASK
- ARIZONA_HP2R_SC_POS_EINT2_SHIFT
- ARIZONA_HP2R_SC_POS_EINT2_WIDTH
- ARIZONA_HP2R_SC_POS_STS
- ARIZONA_HP2R_SC_POS_STS_MASK
- ARIZONA_HP2R_SC_POS_STS_SHIFT
- ARIZONA_HP2R_SC_POS_STS_WIDTH
- ARIZONA_HP2_SC_ENA
- ARIZONA_HP2_SC_ENA_MASK
- ARIZONA_HP2_SC_ENA_SHIFT
- ARIZONA_HP2_SC_ENA_WIDTH
- ARIZONA_HP2_SHORT_CIRCUIT_CTRL
- ARIZONA_HP3L_DONE_EINT1
- ARIZONA_HP3L_DONE_EINT1_MASK
- ARIZONA_HP3L_DONE_EINT1_SHIFT
- ARIZONA_HP3L_DONE_EINT1_WIDTH
- ARIZONA_HP3L_DONE_EINT2
- ARIZONA_HP3L_DONE_EINT2_MASK
- ARIZONA_HP3L_DONE_EINT2_SHIFT
- ARIZONA_HP3L_DONE_EINT2_WIDTH
- ARIZONA_HP3L_DONE_STS
- ARIZONA_HP3L_DONE_STS_MASK
- ARIZONA_HP3L_DONE_STS_SHIFT
- ARIZONA_HP3L_DONE_STS_WIDTH
- ARIZONA_HP3L_SC_NEG_EINT1
- ARIZONA_HP3L_SC_NEG_EINT1_MASK
- ARIZONA_HP3L_SC_NEG_EINT1_SHIFT
- ARIZONA_HP3L_SC_NEG_EINT1_WIDTH
- ARIZONA_HP3L_SC_NEG_EINT2
- ARIZONA_HP3L_SC_NEG_EINT2_MASK
- ARIZONA_HP3L_SC_NEG_EINT2_SHIFT
- ARIZONA_HP3L_SC_NEG_EINT2_WIDTH
- ARIZONA_HP3L_SC_NEG_STS
- ARIZONA_HP3L_SC_NEG_STS_MASK
- ARIZONA_HP3L_SC_NEG_STS_SHIFT
- ARIZONA_HP3L_SC_NEG_STS_WIDTH
- ARIZONA_HP3L_SC_POS_EINT1
- ARIZONA_HP3L_SC_POS_EINT1_MASK
- ARIZONA_HP3L_SC_POS_EINT1_SHIFT
- ARIZONA_HP3L_SC_POS_EINT1_WIDTH
- ARIZONA_HP3L_SC_POS_EINT2
- ARIZONA_HP3L_SC_POS_EINT2_MASK
- ARIZONA_HP3L_SC_POS_EINT2_SHIFT
- ARIZONA_HP3L_SC_POS_EINT2_WIDTH
- ARIZONA_HP3L_SC_POS_STS
- ARIZONA_HP3L_SC_POS_STS_MASK
- ARIZONA_HP3L_SC_POS_STS_SHIFT
- ARIZONA_HP3L_SC_POS_STS_WIDTH
- ARIZONA_HP3R_DONE_EINT1
- ARIZONA_HP3R_DONE_EINT1_MASK
- ARIZONA_HP3R_DONE_EINT1_SHIFT
- ARIZONA_HP3R_DONE_EINT1_WIDTH
- ARIZONA_HP3R_DONE_EINT2
- ARIZONA_HP3R_DONE_EINT2_MASK
- ARIZONA_HP3R_DONE_EINT2_SHIFT
- ARIZONA_HP3R_DONE_EINT2_WIDTH
- ARIZONA_HP3R_DONE_STS
- ARIZONA_HP3R_DONE_STS_MASK
- ARIZONA_HP3R_DONE_STS_SHIFT
- ARIZONA_HP3R_DONE_STS_WIDTH
- ARIZONA_HP3R_SC_NEG_EINT1
- ARIZONA_HP3R_SC_NEG_EINT1_MASK
- ARIZONA_HP3R_SC_NEG_EINT1_SHIFT
- ARIZONA_HP3R_SC_NEG_EINT1_WIDTH
- ARIZONA_HP3R_SC_NEG_EINT2
- ARIZONA_HP3R_SC_NEG_EINT2_MASK
- ARIZONA_HP3R_SC_NEG_EINT2_SHIFT
- ARIZONA_HP3R_SC_NEG_EINT2_WIDTH
- ARIZONA_HP3R_SC_NEG_STS
- ARIZONA_HP3R_SC_NEG_STS_MASK
- ARIZONA_HP3R_SC_NEG_STS_SHIFT
- ARIZONA_HP3R_SC_NEG_STS_WIDTH
- ARIZONA_HP3R_SC_POS_EINT1
- ARIZONA_HP3R_SC_POS_EINT1_MASK
- ARIZONA_HP3R_SC_POS_EINT1_SHIFT
- ARIZONA_HP3R_SC_POS_EINT1_WIDTH
- ARIZONA_HP3R_SC_POS_EINT2
- ARIZONA_HP3R_SC_POS_EINT2_MASK
- ARIZONA_HP3R_SC_POS_EINT2_SHIFT
- ARIZONA_HP3R_SC_POS_EINT2_WIDTH
- ARIZONA_HP3R_SC_POS_STS
- ARIZONA_HP3R_SC_POS_STS_MASK
- ARIZONA_HP3R_SC_POS_STS_SHIFT
- ARIZONA_HP3R_SC_POS_STS_WIDTH
- ARIZONA_HP3_SC_ENA
- ARIZONA_HP3_SC_ENA_MASK
- ARIZONA_HP3_SC_ENA_SHIFT
- ARIZONA_HP3_SC_ENA_WIDTH
- ARIZONA_HP3_SHORT_CIRCUIT_CTRL
- ARIZONA_HPDET_B_RANGE_MAX
- ARIZONA_HPDET_EINT1
- ARIZONA_HPDET_EINT1_MASK
- ARIZONA_HPDET_EINT1_SHIFT
- ARIZONA_HPDET_EINT1_WIDTH
- ARIZONA_HPDET_EINT2
- ARIZONA_HPDET_EINT2_MASK
- ARIZONA_HPDET_EINT2_SHIFT
- ARIZONA_HPDET_EINT2_WIDTH
- ARIZONA_HPDET_MAX
- ARIZONA_HPDET_STS
- ARIZONA_HPDET_STS_MASK
- ARIZONA_HPDET_STS_SHIFT
- ARIZONA_HPDET_STS_WIDTH
- ARIZONA_HPDET_WAIT_COUNT
- ARIZONA_HPDET_WAIT_DELAY_MS
- ARIZONA_HPF_CONTROL
- ARIZONA_HPLP1MIX_INPUT_1_SOURCE
- ARIZONA_HPLP1MIX_INPUT_1_VOLUME
- ARIZONA_HPLP1MIX_INPUT_2_SOURCE
- ARIZONA_HPLP1MIX_INPUT_2_VOLUME
- ARIZONA_HPLP1MIX_INPUT_3_SOURCE
- ARIZONA_HPLP1MIX_INPUT_3_VOLUME
- ARIZONA_HPLP1MIX_INPUT_4_SOURCE
- ARIZONA_HPLP1MIX_INPUT_4_VOLUME
- ARIZONA_HPLP2MIX_INPUT_1_SOURCE
- ARIZONA_HPLP2MIX_INPUT_1_VOLUME
- ARIZONA_HPLP2MIX_INPUT_2_SOURCE
- ARIZONA_HPLP2MIX_INPUT_2_VOLUME
- ARIZONA_HPLP2MIX_INPUT_3_SOURCE
- ARIZONA_HPLP2MIX_INPUT_3_VOLUME
- ARIZONA_HPLP2MIX_INPUT_4_SOURCE
- ARIZONA_HPLP2MIX_INPUT_4_VOLUME
- ARIZONA_HPLP3MIX_INPUT_1_SOURCE
- ARIZONA_HPLP3MIX_INPUT_1_VOLUME
- ARIZONA_HPLP3MIX_INPUT_2_SOURCE
- ARIZONA_HPLP3MIX_INPUT_2_VOLUME
- ARIZONA_HPLP3MIX_INPUT_3_SOURCE
- ARIZONA_HPLP3MIX_INPUT_3_VOLUME
- ARIZONA_HPLP3MIX_INPUT_4_SOURCE
- ARIZONA_HPLP3MIX_INPUT_4_VOLUME
- ARIZONA_HPLP4MIX_INPUT_1_SOURCE
- ARIZONA_HPLP4MIX_INPUT_1_VOLUME
- ARIZONA_HPLP4MIX_INPUT_2_SOURCE
- ARIZONA_HPLP4MIX_INPUT_2_VOLUME
- ARIZONA_HPLP4MIX_INPUT_3_SOURCE
- ARIZONA_HPLP4MIX_INPUT_3_VOLUME
- ARIZONA_HPLP4MIX_INPUT_4_SOURCE
- ARIZONA_HPLP4MIX_INPUT_4_VOLUME
- ARIZONA_HPLPF1_1
- ARIZONA_HPLPF1_2
- ARIZONA_HPLPF2_1
- ARIZONA_HPLPF2_2
- ARIZONA_HPLPF3_1
- ARIZONA_HPLPF3_2
- ARIZONA_HPLPF4_1
- ARIZONA_HPLPF4_2
- ARIZONA_HP_CLK_DIV_MASK
- ARIZONA_HP_CLK_DIV_SHIFT
- ARIZONA_HP_CLK_DIV_WIDTH
- ARIZONA_HP_CTRL_1L
- ARIZONA_HP_CTRL_1R
- ARIZONA_HP_DACVAL
- ARIZONA_HP_DONE
- ARIZONA_HP_DONE_B
- ARIZONA_HP_DONE_B_MASK
- ARIZONA_HP_DONE_B_SHIFT
- ARIZONA_HP_DONE_B_WIDTH
- ARIZONA_HP_DONE_MASK
- ARIZONA_HP_DONE_SHIFT
- ARIZONA_HP_DONE_WIDTH
- ARIZONA_HP_HOLDTIME_MASK
- ARIZONA_HP_HOLDTIME_SHIFT
- ARIZONA_HP_HOLDTIME_WIDTH
- ARIZONA_HP_IDAC_STEER
- ARIZONA_HP_IDAC_STEER_MASK
- ARIZONA_HP_IDAC_STEER_SHIFT
- ARIZONA_HP_IDAC_STEER_WIDTH
- ARIZONA_HP_IMPEDANCE_RANGE_MASK
- ARIZONA_HP_IMPEDANCE_RANGE_SHIFT
- ARIZONA_HP_IMPEDANCE_RANGE_WIDTH
- ARIZONA_HP_LVL_B_MASK
- ARIZONA_HP_LVL_B_SHIFT
- ARIZONA_HP_LVL_B_WIDTH
- ARIZONA_HP_LVL_MASK
- ARIZONA_HP_LVL_SHIFT
- ARIZONA_HP_LVL_WIDTH
- ARIZONA_HP_POLL
- ARIZONA_HP_POLL_MASK
- ARIZONA_HP_POLL_SHIFT
- ARIZONA_HP_POLL_WIDTH
- ARIZONA_HP_RATE
- ARIZONA_HP_RATE_MASK
- ARIZONA_HP_RATE_SHIFT
- ARIZONA_HP_RATE_WIDTH
- ARIZONA_HP_STEP_SIZE
- ARIZONA_HP_STEP_SIZE_MASK
- ARIZONA_HP_STEP_SIZE_SHIFT
- ARIZONA_HP_STEP_SIZE_WIDTH
- ARIZONA_HP_TEST_CTRL_1
- ARIZONA_HP_TEST_CTRL_13
- ARIZONA_I2C1_AUTO_INC_MASK
- ARIZONA_I2C1_AUTO_INC_SHIFT
- ARIZONA_I2C1_AUTO_INC_WIDTH
- ARIZONA_I2C1_BUSY
- ARIZONA_I2C1_BUSY_MASK
- ARIZONA_I2C1_BUSY_SHIFT
- ARIZONA_I2C1_BUSY_WIDTH
- ARIZONA_IM_AIF1_ERR_EINT1
- ARIZONA_IM_AIF1_ERR_EINT1_MASK
- ARIZONA_IM_AIF1_ERR_EINT1_SHIFT
- ARIZONA_IM_AIF1_ERR_EINT1_WIDTH
- ARIZONA_IM_AIF1_ERR_EINT2
- ARIZONA_IM_AIF1_ERR_EINT2_MASK
- ARIZONA_IM_AIF1_ERR_EINT2_SHIFT
- ARIZONA_IM_AIF1_ERR_EINT2_WIDTH
- ARIZONA_IM_AIF2_ERR_EINT1
- ARIZONA_IM_AIF2_ERR_EINT1_MASK
- ARIZONA_IM_AIF2_ERR_EINT1_SHIFT
- ARIZONA_IM_AIF2_ERR_EINT1_WIDTH
- ARIZONA_IM_AIF2_ERR_EINT2
- ARIZONA_IM_AIF2_ERR_EINT2_MASK
- ARIZONA_IM_AIF2_ERR_EINT2_SHIFT
- ARIZONA_IM_AIF2_ERR_EINT2_WIDTH
- ARIZONA_IM_AIF3_ERR_EINT1
- ARIZONA_IM_AIF3_ERR_EINT1_MASK
- ARIZONA_IM_AIF3_ERR_EINT1_SHIFT
- ARIZONA_IM_AIF3_ERR_EINT1_WIDTH
- ARIZONA_IM_AIF3_ERR_EINT2
- ARIZONA_IM_AIF3_ERR_EINT2_MASK
- ARIZONA_IM_AIF3_ERR_EINT2_SHIFT
- ARIZONA_IM_AIF3_ERR_EINT2_WIDTH
- ARIZONA_IM_ASRC1_LOCK_EINT1
- ARIZONA_IM_ASRC1_LOCK_EINT1_MASK
- ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT
- ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH
- ARIZONA_IM_ASRC1_LOCK_EINT2
- ARIZONA_IM_ASRC1_LOCK_EINT2_MASK
- ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT
- ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH
- ARIZONA_IM_ASRC2_LOCK_EINT1
- ARIZONA_IM_ASRC2_LOCK_EINT1_MASK
- ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT
- ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH
- ARIZONA_IM_ASRC2_LOCK_EINT2
- ARIZONA_IM_ASRC2_LOCK_EINT2_MASK
- ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT
- ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH
- ARIZONA_IM_ASRC_CFG_ERR_EINT1
- ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK
- ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT
- ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH
- ARIZONA_IM_ASRC_CFG_ERR_EINT2
- ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK
- ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT
- ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_IM_BOOT_DONE_EINT1
- ARIZONA_IM_BOOT_DONE_EINT1_MASK
- ARIZONA_IM_BOOT_DONE_EINT1_SHIFT
- ARIZONA_IM_BOOT_DONE_EINT1_WIDTH
- ARIZONA_IM_BOOT_DONE_EINT2
- ARIZONA_IM_BOOT_DONE_EINT2_MASK
- ARIZONA_IM_BOOT_DONE_EINT2_SHIFT
- ARIZONA_IM_BOOT_DONE_EINT2_WIDTH
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT
- ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH
- ARIZONA_IM_CLKGEN_ERR_EINT1
- ARIZONA_IM_CLKGEN_ERR_EINT1_MASK
- ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT
- ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH
- ARIZONA_IM_CLKGEN_ERR_EINT2
- ARIZONA_IM_CLKGEN_ERR_EINT2_MASK
- ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT
- ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH
- ARIZONA_IM_CTRLIF_ERR_EINT1
- ARIZONA_IM_CTRLIF_ERR_EINT1_MASK
- ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT
- ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH
- ARIZONA_IM_CTRLIF_ERR_EINT2
- ARIZONA_IM_CTRLIF_ERR_EINT2_MASK
- ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT
- ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH
- ARIZONA_IM_DCS_DAC_DONE_EINT1
- ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK
- ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT
- ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH
- ARIZONA_IM_DCS_DAC_DONE_EINT2
- ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK
- ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT
- ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH
- ARIZONA_IM_DCS_HP_DONE_EINT1
- ARIZONA_IM_DCS_HP_DONE_EINT1_MASK
- ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT
- ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH
- ARIZONA_IM_DCS_HP_DONE_EINT2
- ARIZONA_IM_DCS_HP_DONE_EINT2_MASK
- ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT
- ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH
- ARIZONA_IM_DRC1_SIG_DET_EINT1
- ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK
- ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT
- ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH
- ARIZONA_IM_DRC1_SIG_DET_EINT2
- ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK
- ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT
- ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH
- ARIZONA_IM_DRC2_SIG_DET_EINT1
- ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK
- ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT
- ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH
- ARIZONA_IM_DRC2_SIG_DET_EINT2
- ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK
- ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT
- ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH
- ARIZONA_IM_DSP1_RAM_RDY_EINT1
- ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK
- ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT
- ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH
- ARIZONA_IM_DSP1_RAM_RDY_EINT2
- ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK
- ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT
- ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH
- ARIZONA_IM_DSP_IRQ1_EINT1
- ARIZONA_IM_DSP_IRQ1_EINT1_MASK
- ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT
- ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH
- ARIZONA_IM_DSP_IRQ1_EINT2
- ARIZONA_IM_DSP_IRQ1_EINT2_MASK
- ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT
- ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH
- ARIZONA_IM_DSP_IRQ2_EINT1
- ARIZONA_IM_DSP_IRQ2_EINT1_MASK
- ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT
- ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH
- ARIZONA_IM_DSP_IRQ2_EINT2
- ARIZONA_IM_DSP_IRQ2_EINT2_MASK
- ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT
- ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_MASK
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_SHIFT
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_WIDTH
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_MASK
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_SHIFT
- ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_WIDTH
- ARIZONA_IM_FLL1_CLOCK_OK_EINT1
- ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK
- ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT
- ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH
- ARIZONA_IM_FLL1_CLOCK_OK_EINT2
- ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK
- ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT
- ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH
- ARIZONA_IM_FLL1_LOCK_EINT1
- ARIZONA_IM_FLL1_LOCK_EINT1_MASK
- ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT
- ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH
- ARIZONA_IM_FLL1_LOCK_EINT2
- ARIZONA_IM_FLL1_LOCK_EINT2_MASK
- ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT
- ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH
- ARIZONA_IM_FLL2_CLOCK_OK_EINT1
- ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK
- ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT
- ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH
- ARIZONA_IM_FLL2_CLOCK_OK_EINT2
- ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK
- ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT
- ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH
- ARIZONA_IM_FLL2_LOCK_EINT1
- ARIZONA_IM_FLL2_LOCK_EINT1_MASK
- ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT
- ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH
- ARIZONA_IM_FLL2_LOCK_EINT2
- ARIZONA_IM_FLL2_LOCK_EINT2_MASK
- ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT
- ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH
- ARIZONA_IM_GP1_EINT1
- ARIZONA_IM_GP1_EINT1_MASK
- ARIZONA_IM_GP1_EINT1_SHIFT
- ARIZONA_IM_GP1_EINT1_WIDTH
- ARIZONA_IM_GP1_EINT2
- ARIZONA_IM_GP1_EINT2_MASK
- ARIZONA_IM_GP1_EINT2_SHIFT
- ARIZONA_IM_GP1_EINT2_WIDTH
- ARIZONA_IM_GP2_EINT1
- ARIZONA_IM_GP2_EINT1_MASK
- ARIZONA_IM_GP2_EINT1_SHIFT
- ARIZONA_IM_GP2_EINT1_WIDTH
- ARIZONA_IM_GP2_EINT2
- ARIZONA_IM_GP2_EINT2_MASK
- ARIZONA_IM_GP2_EINT2_SHIFT
- ARIZONA_IM_GP2_EINT2_WIDTH
- ARIZONA_IM_GP3_EINT1
- ARIZONA_IM_GP3_EINT1_MASK
- ARIZONA_IM_GP3_EINT1_SHIFT
- ARIZONA_IM_GP3_EINT1_WIDTH
- ARIZONA_IM_GP3_EINT2
- ARIZONA_IM_GP3_EINT2_MASK
- ARIZONA_IM_GP3_EINT2_SHIFT
- ARIZONA_IM_GP3_EINT2_WIDTH
- ARIZONA_IM_GP4_EINT1
- ARIZONA_IM_GP4_EINT1_MASK
- ARIZONA_IM_GP4_EINT1_SHIFT
- ARIZONA_IM_GP4_EINT1_WIDTH
- ARIZONA_IM_GP4_EINT2
- ARIZONA_IM_GP4_EINT2_MASK
- ARIZONA_IM_GP4_EINT2_SHIFT
- ARIZONA_IM_GP4_EINT2_WIDTH
- ARIZONA_IM_GP5_FALL_EINT1
- ARIZONA_IM_GP5_FALL_EINT1_MASK
- ARIZONA_IM_GP5_FALL_EINT1_SHIFT
- ARIZONA_IM_GP5_FALL_EINT1_WIDTH
- ARIZONA_IM_GP5_FALL_EINT2
- ARIZONA_IM_GP5_FALL_EINT2_MASK
- ARIZONA_IM_GP5_FALL_EINT2_SHIFT
- ARIZONA_IM_GP5_FALL_EINT2_WIDTH
- ARIZONA_IM_GP5_RISE_EINT1
- ARIZONA_IM_GP5_RISE_EINT1_MASK
- ARIZONA_IM_GP5_RISE_EINT1_SHIFT
- ARIZONA_IM_GP5_RISE_EINT1_WIDTH
- ARIZONA_IM_GP5_RISE_EINT2
- ARIZONA_IM_GP5_RISE_EINT2_MASK
- ARIZONA_IM_GP5_RISE_EINT2_SHIFT
- ARIZONA_IM_GP5_RISE_EINT2_WIDTH
- ARIZONA_IM_HP1L_DONE_EINT1
- ARIZONA_IM_HP1L_DONE_EINT1_MASK
- ARIZONA_IM_HP1L_DONE_EINT1_SHIFT
- ARIZONA_IM_HP1L_DONE_EINT1_WIDTH
- ARIZONA_IM_HP1L_DONE_EINT2
- ARIZONA_IM_HP1L_DONE_EINT2_MASK
- ARIZONA_IM_HP1L_DONE_EINT2_SHIFT
- ARIZONA_IM_HP1L_DONE_EINT2_WIDTH
- ARIZONA_IM_HP1L_SC_NEG_EINT1
- ARIZONA_IM_HP1L_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP1L_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP1L_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP1L_SC_NEG_EINT2
- ARIZONA_IM_HP1L_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP1L_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP1L_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP1L_SC_POS_EINT1
- ARIZONA_IM_HP1L_SC_POS_EINT1_MASK
- ARIZONA_IM_HP1L_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP1L_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP1L_SC_POS_EINT2
- ARIZONA_IM_HP1L_SC_POS_EINT2_MASK
- ARIZONA_IM_HP1L_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP1L_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HP1R_DONE_EINT1
- ARIZONA_IM_HP1R_DONE_EINT1_MASK
- ARIZONA_IM_HP1R_DONE_EINT1_SHIFT
- ARIZONA_IM_HP1R_DONE_EINT1_WIDTH
- ARIZONA_IM_HP1R_DONE_EINT2
- ARIZONA_IM_HP1R_DONE_EINT2_MASK
- ARIZONA_IM_HP1R_DONE_EINT2_SHIFT
- ARIZONA_IM_HP1R_DONE_EINT2_WIDTH
- ARIZONA_IM_HP1R_SC_NEG_EINT1
- ARIZONA_IM_HP1R_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP1R_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP1R_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP1R_SC_NEG_EINT2
- ARIZONA_IM_HP1R_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP1R_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP1R_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP1R_SC_POS_EINT1
- ARIZONA_IM_HP1R_SC_POS_EINT1_MASK
- ARIZONA_IM_HP1R_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP1R_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP1R_SC_POS_EINT2
- ARIZONA_IM_HP1R_SC_POS_EINT2_MASK
- ARIZONA_IM_HP1R_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP1R_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HP2L_DONE_EINT1
- ARIZONA_IM_HP2L_DONE_EINT1_MASK
- ARIZONA_IM_HP2L_DONE_EINT1_SHIFT
- ARIZONA_IM_HP2L_DONE_EINT1_WIDTH
- ARIZONA_IM_HP2L_DONE_EINT2
- ARIZONA_IM_HP2L_DONE_EINT2_MASK
- ARIZONA_IM_HP2L_DONE_EINT2_SHIFT
- ARIZONA_IM_HP2L_DONE_EINT2_WIDTH
- ARIZONA_IM_HP2L_SC_NEG_EINT1
- ARIZONA_IM_HP2L_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP2L_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP2L_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP2L_SC_NEG_EINT2
- ARIZONA_IM_HP2L_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP2L_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP2L_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP2L_SC_POS_EINT1
- ARIZONA_IM_HP2L_SC_POS_EINT1_MASK
- ARIZONA_IM_HP2L_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP2L_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP2L_SC_POS_EINT2
- ARIZONA_IM_HP2L_SC_POS_EINT2_MASK
- ARIZONA_IM_HP2L_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP2L_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HP2R_DONE_EINT1
- ARIZONA_IM_HP2R_DONE_EINT1_MASK
- ARIZONA_IM_HP2R_DONE_EINT1_SHIFT
- ARIZONA_IM_HP2R_DONE_EINT1_WIDTH
- ARIZONA_IM_HP2R_DONE_EINT2
- ARIZONA_IM_HP2R_DONE_EINT2_MASK
- ARIZONA_IM_HP2R_DONE_EINT2_SHIFT
- ARIZONA_IM_HP2R_DONE_EINT2_WIDTH
- ARIZONA_IM_HP2R_SC_NEG_EINT1
- ARIZONA_IM_HP2R_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP2R_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP2R_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP2R_SC_NEG_EINT2
- ARIZONA_IM_HP2R_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP2R_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP2R_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP2R_SC_POS_EINT1
- ARIZONA_IM_HP2R_SC_POS_EINT1_MASK
- ARIZONA_IM_HP2R_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP2R_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP2R_SC_POS_EINT2
- ARIZONA_IM_HP2R_SC_POS_EINT2_MASK
- ARIZONA_IM_HP2R_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP2R_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HP3L_DONE_EINT1
- ARIZONA_IM_HP3L_DONE_EINT1_MASK
- ARIZONA_IM_HP3L_DONE_EINT1_SHIFT
- ARIZONA_IM_HP3L_DONE_EINT1_WIDTH
- ARIZONA_IM_HP3L_DONE_EINT2
- ARIZONA_IM_HP3L_DONE_EINT2_MASK
- ARIZONA_IM_HP3L_DONE_EINT2_SHIFT
- ARIZONA_IM_HP3L_DONE_EINT2_WIDTH
- ARIZONA_IM_HP3L_SC_NEG_EINT1
- ARIZONA_IM_HP3L_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP3L_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP3L_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP3L_SC_NEG_EINT2
- ARIZONA_IM_HP3L_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP3L_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP3L_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP3L_SC_POS_EINT1
- ARIZONA_IM_HP3L_SC_POS_EINT1_MASK
- ARIZONA_IM_HP3L_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP3L_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP3L_SC_POS_EINT2
- ARIZONA_IM_HP3L_SC_POS_EINT2_MASK
- ARIZONA_IM_HP3L_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP3L_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HP3R_DONE_EINT1
- ARIZONA_IM_HP3R_DONE_EINT1_MASK
- ARIZONA_IM_HP3R_DONE_EINT1_SHIFT
- ARIZONA_IM_HP3R_DONE_EINT1_WIDTH
- ARIZONA_IM_HP3R_DONE_EINT2
- ARIZONA_IM_HP3R_DONE_EINT2_MASK
- ARIZONA_IM_HP3R_DONE_EINT2_SHIFT
- ARIZONA_IM_HP3R_DONE_EINT2_WIDTH
- ARIZONA_IM_HP3R_SC_NEG_EINT1
- ARIZONA_IM_HP3R_SC_NEG_EINT1_MASK
- ARIZONA_IM_HP3R_SC_NEG_EINT1_SHIFT
- ARIZONA_IM_HP3R_SC_NEG_EINT1_WIDTH
- ARIZONA_IM_HP3R_SC_NEG_EINT2
- ARIZONA_IM_HP3R_SC_NEG_EINT2_MASK
- ARIZONA_IM_HP3R_SC_NEG_EINT2_SHIFT
- ARIZONA_IM_HP3R_SC_NEG_EINT2_WIDTH
- ARIZONA_IM_HP3R_SC_POS_EINT1
- ARIZONA_IM_HP3R_SC_POS_EINT1_MASK
- ARIZONA_IM_HP3R_SC_POS_EINT1_SHIFT
- ARIZONA_IM_HP3R_SC_POS_EINT1_WIDTH
- ARIZONA_IM_HP3R_SC_POS_EINT2
- ARIZONA_IM_HP3R_SC_POS_EINT2_MASK
- ARIZONA_IM_HP3R_SC_POS_EINT2_SHIFT
- ARIZONA_IM_HP3R_SC_POS_EINT2_WIDTH
- ARIZONA_IM_HPDET_EINT1
- ARIZONA_IM_HPDET_EINT1_MASK
- ARIZONA_IM_HPDET_EINT1_SHIFT
- ARIZONA_IM_HPDET_EINT1_WIDTH
- ARIZONA_IM_HPDET_EINT2
- ARIZONA_IM_HPDET_EINT2_MASK
- ARIZONA_IM_HPDET_EINT2_SHIFT
- ARIZONA_IM_HPDET_EINT2_WIDTH
- ARIZONA_IM_IRQ1
- ARIZONA_IM_IRQ1_MASK
- ARIZONA_IM_IRQ1_SHIFT
- ARIZONA_IM_IRQ1_WIDTH
- ARIZONA_IM_IRQ2
- ARIZONA_IM_IRQ2_MASK
- ARIZONA_IM_IRQ2_SHIFT
- ARIZONA_IM_IRQ2_WIDTH
- ARIZONA_IM_ISRC1_CFG_ERR_EINT1
- ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK
- ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT
- ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH
- ARIZONA_IM_ISRC1_CFG_ERR_EINT2
- ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK
- ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT
- ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH
- ARIZONA_IM_ISRC2_CFG_ERR_EINT1
- ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK
- ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT
- ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH
- ARIZONA_IM_ISRC2_CFG_ERR_EINT2
- ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK
- ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT
- ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH
- ARIZONA_IM_JD1_FALL_EINT1
- ARIZONA_IM_JD1_FALL_EINT1_MASK
- ARIZONA_IM_JD1_FALL_EINT1_SHIFT
- ARIZONA_IM_JD1_FALL_EINT1_WIDTH
- ARIZONA_IM_JD1_FALL_EINT2
- ARIZONA_IM_JD1_FALL_EINT2_MASK
- ARIZONA_IM_JD1_FALL_EINT2_SHIFT
- ARIZONA_IM_JD1_FALL_EINT2_WIDTH
- ARIZONA_IM_JD1_RISE_EINT1
- ARIZONA_IM_JD1_RISE_EINT1_MASK
- ARIZONA_IM_JD1_RISE_EINT1_SHIFT
- ARIZONA_IM_JD1_RISE_EINT1_WIDTH
- ARIZONA_IM_JD1_RISE_EINT2
- ARIZONA_IM_JD1_RISE_EINT2_MASK
- ARIZONA_IM_JD1_RISE_EINT2_SHIFT
- ARIZONA_IM_JD1_RISE_EINT2_WIDTH
- ARIZONA_IM_JD2_FALL_EINT1
- ARIZONA_IM_JD2_FALL_EINT1_MASK
- ARIZONA_IM_JD2_FALL_EINT1_SHIFT
- ARIZONA_IM_JD2_FALL_EINT1_WIDTH
- ARIZONA_IM_JD2_FALL_EINT2
- ARIZONA_IM_JD2_FALL_EINT2_MASK
- ARIZONA_IM_JD2_FALL_EINT2_SHIFT
- ARIZONA_IM_JD2_FALL_EINT2_WIDTH
- ARIZONA_IM_JD2_RISE_EINT1
- ARIZONA_IM_JD2_RISE_EINT1_MASK
- ARIZONA_IM_JD2_RISE_EINT1_SHIFT
- ARIZONA_IM_JD2_RISE_EINT1_WIDTH
- ARIZONA_IM_JD2_RISE_EINT2
- ARIZONA_IM_JD2_RISE_EINT2_MASK
- ARIZONA_IM_JD2_RISE_EINT2_SHIFT
- ARIZONA_IM_JD2_RISE_EINT2_WIDTH
- ARIZONA_IM_MICDET_EINT1
- ARIZONA_IM_MICDET_EINT1_MASK
- ARIZONA_IM_MICDET_EINT1_SHIFT
- ARIZONA_IM_MICDET_EINT1_WIDTH
- ARIZONA_IM_MICDET_EINT2
- ARIZONA_IM_MICDET_EINT2_MASK
- ARIZONA_IM_MICDET_EINT2_SHIFT
- ARIZONA_IM_MICDET_EINT2_WIDTH
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT
- ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH
- ARIZONA_IM_OVERCLOCKED_EINT1
- ARIZONA_IM_OVERCLOCKED_EINT1_MASK
- ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT
- ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH
- ARIZONA_IM_OVERCLOCKED_EINT2
- ARIZONA_IM_OVERCLOCKED_EINT2_MASK
- ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT
- ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH
- ARIZONA_IM_SPK1L_SHORT_EINT1
- ARIZONA_IM_SPK1L_SHORT_EINT1_MASK
- ARIZONA_IM_SPK1L_SHORT_EINT1_SHIFT
- ARIZONA_IM_SPK1L_SHORT_EINT1_WIDTH
- ARIZONA_IM_SPK1L_SHORT_EINT2
- ARIZONA_IM_SPK1L_SHORT_EINT2_MASK
- ARIZONA_IM_SPK1L_SHORT_EINT2_SHIFT
- ARIZONA_IM_SPK1L_SHORT_EINT2_WIDTH
- ARIZONA_IM_SPK1R_SHORT_EINT1
- ARIZONA_IM_SPK1R_SHORT_EINT1_MASK
- ARIZONA_IM_SPK1R_SHORT_EINT1_SHIFT
- ARIZONA_IM_SPK1R_SHORT_EINT1_WIDTH
- ARIZONA_IM_SPK1R_SHORT_EINT2
- ARIZONA_IM_SPK1R_SHORT_EINT2_MASK
- ARIZONA_IM_SPK1R_SHORT_EINT2_SHIFT
- ARIZONA_IM_SPK1R_SHORT_EINT2_WIDTH
- ARIZONA_IM_SPK_OVERHEAT_EINT1
- ARIZONA_IM_SPK_OVERHEAT_EINT1_MASK
- ARIZONA_IM_SPK_OVERHEAT_EINT1_SHIFT
- ARIZONA_IM_SPK_OVERHEAT_EINT1_WIDTH
- ARIZONA_IM_SPK_OVERHEAT_EINT2
- ARIZONA_IM_SPK_OVERHEAT_EINT2_MASK
- ARIZONA_IM_SPK_OVERHEAT_EINT2_SHIFT
- ARIZONA_IM_SPK_OVERHEAT_EINT2_WIDTH
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_MASK
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_SHIFT
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_WIDTH
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_MASK
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_SHIFT
- ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_WIDTH
- ARIZONA_IM_SPK_SHUTDOWN_EINT1
- ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK
- ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT
- ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH
- ARIZONA_IM_SPK_SHUTDOWN_EINT2
- ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK
- ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT
- ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT1
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT2
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_IM_UNDERCLOCKED_EINT1
- ARIZONA_IM_UNDERCLOCKED_EINT1_MASK
- ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT
- ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH
- ARIZONA_IM_UNDERCLOCKED_EINT2
- ARIZONA_IM_UNDERCLOCKED_EINT2_MASK
- ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT
- ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH
- ARIZONA_IM_WSEQ_DONE_EINT1
- ARIZONA_IM_WSEQ_DONE_EINT1_MASK
- ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT
- ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH
- ARIZONA_IM_WSEQ_DONE_EINT2
- ARIZONA_IM_WSEQ_DONE_EINT2_MASK
- ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT
- ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH
- ARIZONA_IN1L_CONTROL
- ARIZONA_IN1L_DIG_VOL_MASK
- ARIZONA_IN1L_DIG_VOL_SHIFT
- ARIZONA_IN1L_DIG_VOL_WIDTH
- ARIZONA_IN1L_ENA
- ARIZONA_IN1L_ENA_MASK
- ARIZONA_IN1L_ENA_SHIFT
- ARIZONA_IN1L_ENA_WIDTH
- ARIZONA_IN1L_HPF_MASK
- ARIZONA_IN1L_HPF_SHIFT
- ARIZONA_IN1L_HPF_WIDTH
- ARIZONA_IN1L_MUTE
- ARIZONA_IN1L_MUTE_MASK
- ARIZONA_IN1L_MUTE_SHIFT
- ARIZONA_IN1L_MUTE_WIDTH
- ARIZONA_IN1L_PGA_VOL_MASK
- ARIZONA_IN1L_PGA_VOL_SHIFT
- ARIZONA_IN1L_PGA_VOL_WIDTH
- ARIZONA_IN1L_SRC_MASK
- ARIZONA_IN1L_SRC_SE_MASK
- ARIZONA_IN1L_SRC_SE_SHIFT
- ARIZONA_IN1L_SRC_SE_WIDTH
- ARIZONA_IN1L_SRC_SHIFT
- ARIZONA_IN1L_SRC_WIDTH
- ARIZONA_IN1R_CONTROL
- ARIZONA_IN1R_DIG_VOL_MASK
- ARIZONA_IN1R_DIG_VOL_SHIFT
- ARIZONA_IN1R_DIG_VOL_WIDTH
- ARIZONA_IN1R_ENA
- ARIZONA_IN1R_ENA_MASK
- ARIZONA_IN1R_ENA_SHIFT
- ARIZONA_IN1R_ENA_WIDTH
- ARIZONA_IN1R_HPF_MASK
- ARIZONA_IN1R_HPF_SHIFT
- ARIZONA_IN1R_HPF_WIDTH
- ARIZONA_IN1R_MUTE
- ARIZONA_IN1R_MUTE_MASK
- ARIZONA_IN1R_MUTE_SHIFT
- ARIZONA_IN1R_MUTE_WIDTH
- ARIZONA_IN1R_PGA_VOL_MASK
- ARIZONA_IN1R_PGA_VOL_SHIFT
- ARIZONA_IN1R_PGA_VOL_WIDTH
- ARIZONA_IN1R_SRC_MASK
- ARIZONA_IN1R_SRC_SE_MASK
- ARIZONA_IN1R_SRC_SE_SHIFT
- ARIZONA_IN1R_SRC_SE_WIDTH
- ARIZONA_IN1R_SRC_SHIFT
- ARIZONA_IN1R_SRC_WIDTH
- ARIZONA_IN1_DMICL_DLY_MASK
- ARIZONA_IN1_DMICL_DLY_SHIFT
- ARIZONA_IN1_DMICL_DLY_WIDTH
- ARIZONA_IN1_DMICR_DLY_MASK
- ARIZONA_IN1_DMICR_DLY_SHIFT
- ARIZONA_IN1_DMICR_DLY_WIDTH
- ARIZONA_IN1_DMIC_SUP_MASK
- ARIZONA_IN1_DMIC_SUP_SHIFT
- ARIZONA_IN1_DMIC_SUP_WIDTH
- ARIZONA_IN1_MODE_MASK
- ARIZONA_IN1_MODE_SHIFT
- ARIZONA_IN1_MODE_WIDTH
- ARIZONA_IN1_OSR_MASK
- ARIZONA_IN1_OSR_SHIFT
- ARIZONA_IN1_OSR_WIDTH
- ARIZONA_IN1_SINGLE_ENDED_MASK
- ARIZONA_IN1_SINGLE_ENDED_SHIFT
- ARIZONA_IN1_SINGLE_ENDED_WIDTH
- ARIZONA_IN2L_CONTROL
- ARIZONA_IN2L_DIG_VOL_MASK
- ARIZONA_IN2L_DIG_VOL_SHIFT
- ARIZONA_IN2L_DIG_VOL_WIDTH
- ARIZONA_IN2L_ENA
- ARIZONA_IN2L_ENA_MASK
- ARIZONA_IN2L_ENA_SHIFT
- ARIZONA_IN2L_ENA_WIDTH
- ARIZONA_IN2L_HPF_MASK
- ARIZONA_IN2L_HPF_SHIFT
- ARIZONA_IN2L_HPF_WIDTH
- ARIZONA_IN2L_MUTE
- ARIZONA_IN2L_MUTE_MASK
- ARIZONA_IN2L_MUTE_SHIFT
- ARIZONA_IN2L_MUTE_WIDTH
- ARIZONA_IN2L_PGA_VOL_MASK
- ARIZONA_IN2L_PGA_VOL_SHIFT
- ARIZONA_IN2L_PGA_VOL_WIDTH
- ARIZONA_IN2L_SRC_MASK
- ARIZONA_IN2L_SRC_SE_MASK
- ARIZONA_IN2L_SRC_SE_SHIFT
- ARIZONA_IN2L_SRC_SE_WIDTH
- ARIZONA_IN2L_SRC_SHIFT
- ARIZONA_IN2L_SRC_WIDTH
- ARIZONA_IN2R_CONTROL
- ARIZONA_IN2R_DIG_VOL_MASK
- ARIZONA_IN2R_DIG_VOL_SHIFT
- ARIZONA_IN2R_DIG_VOL_WIDTH
- ARIZONA_IN2R_ENA
- ARIZONA_IN2R_ENA_MASK
- ARIZONA_IN2R_ENA_SHIFT
- ARIZONA_IN2R_ENA_WIDTH
- ARIZONA_IN2R_HPF_MASK
- ARIZONA_IN2R_HPF_SHIFT
- ARIZONA_IN2R_HPF_WIDTH
- ARIZONA_IN2R_MUTE
- ARIZONA_IN2R_MUTE_MASK
- ARIZONA_IN2R_MUTE_SHIFT
- ARIZONA_IN2R_MUTE_WIDTH
- ARIZONA_IN2R_PGA_VOL_MASK
- ARIZONA_IN2R_PGA_VOL_SHIFT
- ARIZONA_IN2R_PGA_VOL_WIDTH
- ARIZONA_IN2_DMICL_DLY_MASK
- ARIZONA_IN2_DMICL_DLY_SHIFT
- ARIZONA_IN2_DMICL_DLY_WIDTH
- ARIZONA_IN2_DMICR_DLY_MASK
- ARIZONA_IN2_DMICR_DLY_SHIFT
- ARIZONA_IN2_DMICR_DLY_WIDTH
- ARIZONA_IN2_DMIC_SUP_MASK
- ARIZONA_IN2_DMIC_SUP_SHIFT
- ARIZONA_IN2_DMIC_SUP_WIDTH
- ARIZONA_IN2_MODE_MASK
- ARIZONA_IN2_MODE_SHIFT
- ARIZONA_IN2_MODE_WIDTH
- ARIZONA_IN2_OSR_MASK
- ARIZONA_IN2_OSR_SHIFT
- ARIZONA_IN2_OSR_WIDTH
- ARIZONA_IN2_SINGLE_ENDED_MASK
- ARIZONA_IN2_SINGLE_ENDED_SHIFT
- ARIZONA_IN2_SINGLE_ENDED_WIDTH
- ARIZONA_IN3L_CONTROL
- ARIZONA_IN3L_DIG_VOL_MASK
- ARIZONA_IN3L_DIG_VOL_SHIFT
- ARIZONA_IN3L_DIG_VOL_WIDTH
- ARIZONA_IN3L_ENA
- ARIZONA_IN3L_ENA_MASK
- ARIZONA_IN3L_ENA_SHIFT
- ARIZONA_IN3L_ENA_WIDTH
- ARIZONA_IN3L_HPF_MASK
- ARIZONA_IN3L_HPF_SHIFT
- ARIZONA_IN3L_HPF_WIDTH
- ARIZONA_IN3L_MUTE
- ARIZONA_IN3L_MUTE_MASK
- ARIZONA_IN3L_MUTE_SHIFT
- ARIZONA_IN3L_MUTE_WIDTH
- ARIZONA_IN3L_PGA_VOL_MASK
- ARIZONA_IN3L_PGA_VOL_SHIFT
- ARIZONA_IN3L_PGA_VOL_WIDTH
- ARIZONA_IN3R_CONTROL
- ARIZONA_IN3R_DIG_VOL_MASK
- ARIZONA_IN3R_DIG_VOL_SHIFT
- ARIZONA_IN3R_DIG_VOL_WIDTH
- ARIZONA_IN3R_ENA
- ARIZONA_IN3R_ENA_MASK
- ARIZONA_IN3R_ENA_SHIFT
- ARIZONA_IN3R_ENA_WIDTH
- ARIZONA_IN3R_HPF_MASK
- ARIZONA_IN3R_HPF_SHIFT
- ARIZONA_IN3R_HPF_WIDTH
- ARIZONA_IN3R_MUTE
- ARIZONA_IN3R_MUTE_MASK
- ARIZONA_IN3R_MUTE_SHIFT
- ARIZONA_IN3R_MUTE_WIDTH
- ARIZONA_IN3R_PGA_VOL_MASK
- ARIZONA_IN3R_PGA_VOL_SHIFT
- ARIZONA_IN3R_PGA_VOL_WIDTH
- ARIZONA_IN3_DMICL_DLY_MASK
- ARIZONA_IN3_DMICL_DLY_SHIFT
- ARIZONA_IN3_DMICL_DLY_WIDTH
- ARIZONA_IN3_DMICR_DLY_MASK
- ARIZONA_IN3_DMICR_DLY_SHIFT
- ARIZONA_IN3_DMICR_DLY_WIDTH
- ARIZONA_IN3_DMIC_SUP_MASK
- ARIZONA_IN3_DMIC_SUP_SHIFT
- ARIZONA_IN3_DMIC_SUP_WIDTH
- ARIZONA_IN3_MODE_MASK
- ARIZONA_IN3_MODE_SHIFT
- ARIZONA_IN3_MODE_WIDTH
- ARIZONA_IN3_OSR_MASK
- ARIZONA_IN3_OSR_SHIFT
- ARIZONA_IN3_OSR_WIDTH
- ARIZONA_IN3_SINGLE_ENDED_MASK
- ARIZONA_IN3_SINGLE_ENDED_SHIFT
- ARIZONA_IN3_SINGLE_ENDED_WIDTH
- ARIZONA_IN4L_CONTROL
- ARIZONA_IN4L_DIG_VOL_MASK
- ARIZONA_IN4L_DIG_VOL_SHIFT
- ARIZONA_IN4L_DIG_VOL_WIDTH
- ARIZONA_IN4L_DMIC_DLY_MASK
- ARIZONA_IN4L_DMIC_DLY_SHIFT
- ARIZONA_IN4L_DMIC_DLY_WIDTH
- ARIZONA_IN4L_ENA
- ARIZONA_IN4L_ENA_MASK
- ARIZONA_IN4L_ENA_SHIFT
- ARIZONA_IN4L_ENA_WIDTH
- ARIZONA_IN4L_HPF_MASK
- ARIZONA_IN4L_HPF_SHIFT
- ARIZONA_IN4L_HPF_WIDTH
- ARIZONA_IN4L_MUTE
- ARIZONA_IN4L_MUTE_MASK
- ARIZONA_IN4L_MUTE_SHIFT
- ARIZONA_IN4L_MUTE_WIDTH
- ARIZONA_IN4R_CONTROL
- ARIZONA_IN4R_DIG_VOL_MASK
- ARIZONA_IN4R_DIG_VOL_SHIFT
- ARIZONA_IN4R_DIG_VOL_WIDTH
- ARIZONA_IN4R_DMIC_DLY_MASK
- ARIZONA_IN4R_DMIC_DLY_SHIFT
- ARIZONA_IN4R_DMIC_DLY_WIDTH
- ARIZONA_IN4R_ENA
- ARIZONA_IN4R_ENA_MASK
- ARIZONA_IN4R_ENA_SHIFT
- ARIZONA_IN4R_ENA_WIDTH
- ARIZONA_IN4R_HPF_MASK
- ARIZONA_IN4R_HPF_SHIFT
- ARIZONA_IN4R_HPF_WIDTH
- ARIZONA_IN4R_MUTE
- ARIZONA_IN4R_MUTE_MASK
- ARIZONA_IN4R_MUTE_SHIFT
- ARIZONA_IN4R_MUTE_WIDTH
- ARIZONA_IN4_DMIC_SUP_MASK
- ARIZONA_IN4_DMIC_SUP_SHIFT
- ARIZONA_IN4_DMIC_SUP_WIDTH
- ARIZONA_IN4_OSR_MASK
- ARIZONA_IN4_OSR_SHIFT
- ARIZONA_IN4_OSR_WIDTH
- ARIZONA_INMODE_DIFF
- ARIZONA_INMODE_DMIC
- ARIZONA_INMODE_SE
- ARIZONA_INPUT_ENABLES
- ARIZONA_INPUT_ENABLES_STATUS
- ARIZONA_INPUT_RATE
- ARIZONA_INPUT_VOLUME_RAMP
- ARIZONA_INTERRUPT_CONTROL
- ARIZONA_INTERRUPT_RAW_STATUS_2
- ARIZONA_INTERRUPT_RAW_STATUS_3
- ARIZONA_INTERRUPT_RAW_STATUS_4
- ARIZONA_INTERRUPT_RAW_STATUS_5
- ARIZONA_INTERRUPT_RAW_STATUS_6
- ARIZONA_INTERRUPT_RAW_STATUS_7
- ARIZONA_INTERRUPT_RAW_STATUS_8
- ARIZONA_INTERRUPT_RAW_STATUS_9
- ARIZONA_INTERRUPT_STATUS_1
- ARIZONA_INTERRUPT_STATUS_1_MASK
- ARIZONA_INTERRUPT_STATUS_2
- ARIZONA_INTERRUPT_STATUS_2_MASK
- ARIZONA_INTERRUPT_STATUS_3
- ARIZONA_INTERRUPT_STATUS_3_MASK
- ARIZONA_INTERRUPT_STATUS_4
- ARIZONA_INTERRUPT_STATUS_4_MASK
- ARIZONA_INTERRUPT_STATUS_5
- ARIZONA_INTERRUPT_STATUS_5_MASK
- ARIZONA_INTERRUPT_STATUS_6
- ARIZONA_INTERRUPT_STATUS_6_MASK
- ARIZONA_IN_HPF_CUT_MASK
- ARIZONA_IN_HPF_CUT_SHIFT
- ARIZONA_IN_HPF_CUT_WIDTH
- ARIZONA_IN_RATE_MASK
- ARIZONA_IN_RATE_SHIFT
- ARIZONA_IN_RATE_WIDTH
- ARIZONA_IN_RXANCL_SEL_MASK
- ARIZONA_IN_RXANCL_SEL_SHIFT
- ARIZONA_IN_RXANCL_SEL_WIDTH
- ARIZONA_IN_RXANCR_SEL_MASK
- ARIZONA_IN_RXANCR_SEL_SHIFT
- ARIZONA_IN_RXANCR_SEL_WIDTH
- ARIZONA_IN_VD_RAMP_MASK
- ARIZONA_IN_VD_RAMP_SHIFT
- ARIZONA_IN_VD_RAMP_WIDTH
- ARIZONA_IN_VI_RAMP_MASK
- ARIZONA_IN_VI_RAMP_SHIFT
- ARIZONA_IN_VI_RAMP_WIDTH
- ARIZONA_IN_VU
- ARIZONA_IN_VU_MASK
- ARIZONA_IN_VU_SHIFT
- ARIZONA_IN_VU_WIDTH
- ARIZONA_IRQ1_STS
- ARIZONA_IRQ1_STS_MASK
- ARIZONA_IRQ1_STS_SHIFT
- ARIZONA_IRQ1_STS_WIDTH
- ARIZONA_IRQ2_CONTROL
- ARIZONA_IRQ2_STATUS_1
- ARIZONA_IRQ2_STATUS_1_MASK
- ARIZONA_IRQ2_STATUS_2
- ARIZONA_IRQ2_STATUS_2_MASK
- ARIZONA_IRQ2_STATUS_3
- ARIZONA_IRQ2_STATUS_3_MASK
- ARIZONA_IRQ2_STATUS_4
- ARIZONA_IRQ2_STATUS_4_MASK
- ARIZONA_IRQ2_STATUS_5
- ARIZONA_IRQ2_STATUS_5_MASK
- ARIZONA_IRQ2_STATUS_6
- ARIZONA_IRQ2_STATUS_6_MASK
- ARIZONA_IRQ2_STS
- ARIZONA_IRQ2_STS_MASK
- ARIZONA_IRQ2_STS_SHIFT
- ARIZONA_IRQ2_STS_WIDTH
- ARIZONA_IRQ_AIF1_ERR
- ARIZONA_IRQ_AIF2_ERR
- ARIZONA_IRQ_AIF3_ERR
- ARIZONA_IRQ_ASRC1_LOCK
- ARIZONA_IRQ_ASRC2_LOCK
- ARIZONA_IRQ_ASRC_CFG_ERR
- ARIZONA_IRQ_ASYNC_CLK_ENA_LOW
- ARIZONA_IRQ_BOOT_DONE
- ARIZONA_IRQ_CLKGEN_ERR
- ARIZONA_IRQ_CLKGEN_ERR_ASYNC
- ARIZONA_IRQ_CTRLIF_ERR
- ARIZONA_IRQ_CTRL_1
- ARIZONA_IRQ_DCS_DAC_DONE
- ARIZONA_IRQ_DCS_HP_DONE
- ARIZONA_IRQ_DRC1_SIG_DET
- ARIZONA_IRQ_DRC2_SIG_DET
- ARIZONA_IRQ_DSP1_RAM_RDY
- ARIZONA_IRQ_DSP2_RAM_RDY
- ARIZONA_IRQ_DSP3_RAM_RDY
- ARIZONA_IRQ_DSP4_RAM_RDY
- ARIZONA_IRQ_DSP_IRQ1
- ARIZONA_IRQ_DSP_IRQ2
- ARIZONA_IRQ_DSP_IRQ3
- ARIZONA_IRQ_DSP_IRQ4
- ARIZONA_IRQ_DSP_IRQ5
- ARIZONA_IRQ_DSP_IRQ6
- ARIZONA_IRQ_DSP_IRQ7
- ARIZONA_IRQ_DSP_IRQ8
- ARIZONA_IRQ_DSP_SHARED_WR_COLL
- ARIZONA_IRQ_FLL1_CLOCK_OK
- ARIZONA_IRQ_FLL1_LOCK
- ARIZONA_IRQ_FLL2_CLOCK_OK
- ARIZONA_IRQ_FLL2_LOCK
- ARIZONA_IRQ_GP1
- ARIZONA_IRQ_GP2
- ARIZONA_IRQ_GP3
- ARIZONA_IRQ_GP4
- ARIZONA_IRQ_GP5_FALL
- ARIZONA_IRQ_GP5_RISE
- ARIZONA_IRQ_HP1L_DONE
- ARIZONA_IRQ_HP1L_SC_NEG
- ARIZONA_IRQ_HP1L_SC_POS
- ARIZONA_IRQ_HP1R_DONE
- ARIZONA_IRQ_HP1R_SC_NEG
- ARIZONA_IRQ_HP1R_SC_POS
- ARIZONA_IRQ_HP2L_DONE
- ARIZONA_IRQ_HP2L_SC_NEG
- ARIZONA_IRQ_HP2L_SC_POS
- ARIZONA_IRQ_HP2R_DONE
- ARIZONA_IRQ_HP2R_SC_NEG
- ARIZONA_IRQ_HP2R_SC_POS
- ARIZONA_IRQ_HP3L_DONE
- ARIZONA_IRQ_HP3L_SC_NEG
- ARIZONA_IRQ_HP3L_SC_POS
- ARIZONA_IRQ_HP3R_DONE
- ARIZONA_IRQ_HP3R_SC_NEG
- ARIZONA_IRQ_HP3R_SC_POS
- ARIZONA_IRQ_HPDET
- ARIZONA_IRQ_ISRC1_CFG_ERR
- ARIZONA_IRQ_ISRC2_CFG_ERR
- ARIZONA_IRQ_ISRC3_CFG_ERR
- ARIZONA_IRQ_JD_FALL
- ARIZONA_IRQ_JD_RISE
- ARIZONA_IRQ_MICDET
- ARIZONA_IRQ_MICD_CLAMP_FALL
- ARIZONA_IRQ_MICD_CLAMP_RISE
- ARIZONA_IRQ_MIXER_DROPPED_SAMPLES
- ARIZONA_IRQ_OP_CFG
- ARIZONA_IRQ_OP_CFG_MASK
- ARIZONA_IRQ_OP_CFG_SHIFT
- ARIZONA_IRQ_OP_CFG_WIDTH
- ARIZONA_IRQ_OVERCLOCKED
- ARIZONA_IRQ_PIN_STATUS
- ARIZONA_IRQ_POL
- ARIZONA_IRQ_POL_MASK
- ARIZONA_IRQ_POL_SHIFT
- ARIZONA_IRQ_POL_WIDTH
- ARIZONA_IRQ_SPK1L_SHORT
- ARIZONA_IRQ_SPK1R_SHORT
- ARIZONA_IRQ_SPK_OVERHEAT
- ARIZONA_IRQ_SPK_OVERHEAT_WARN
- ARIZONA_IRQ_SPK_SHUTDOWN
- ARIZONA_IRQ_SYSCLK_ENA_LOW
- ARIZONA_IRQ_UNDERCLOCKED
- ARIZONA_IRQ_WSEQ_DONE
- ARIZONA_ISOLATE_DCVDD1
- ARIZONA_ISOLATE_DCVDD1_MASK
- ARIZONA_ISOLATE_DCVDD1_SHIFT
- ARIZONA_ISOLATE_DCVDD1_WIDTH
- ARIZONA_ISOLATION_CONTROL
- ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC1_CFG_ERR_EINT1
- ARIZONA_ISRC1_CFG_ERR_EINT1_MASK
- ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT
- ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH
- ARIZONA_ISRC1_CFG_ERR_EINT2
- ARIZONA_ISRC1_CFG_ERR_EINT2_MASK
- ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT
- ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH
- ARIZONA_ISRC1_CFG_ERR_STS
- ARIZONA_ISRC1_CFG_ERR_STS_MASK
- ARIZONA_ISRC1_CFG_ERR_STS_SHIFT
- ARIZONA_ISRC1_CFG_ERR_STS_WIDTH
- ARIZONA_ISRC1_CLK_SEL_MASK
- ARIZONA_ISRC1_CLK_SEL_SHIFT
- ARIZONA_ISRC1_CLK_SEL_WIDTH
- ARIZONA_ISRC1_DEC0_ENA
- ARIZONA_ISRC1_DEC0_ENA_MASK
- ARIZONA_ISRC1_DEC0_ENA_SHIFT
- ARIZONA_ISRC1_DEC0_ENA_WIDTH
- ARIZONA_ISRC1_DEC1_ENA
- ARIZONA_ISRC1_DEC1_ENA_MASK
- ARIZONA_ISRC1_DEC1_ENA_SHIFT
- ARIZONA_ISRC1_DEC1_ENA_WIDTH
- ARIZONA_ISRC1_DEC2_ENA
- ARIZONA_ISRC1_DEC2_ENA_MASK
- ARIZONA_ISRC1_DEC2_ENA_SHIFT
- ARIZONA_ISRC1_DEC2_ENA_WIDTH
- ARIZONA_ISRC1_DEC3_ENA
- ARIZONA_ISRC1_DEC3_ENA_MASK
- ARIZONA_ISRC1_DEC3_ENA_SHIFT
- ARIZONA_ISRC1_DEC3_ENA_WIDTH
- ARIZONA_ISRC1_FSH_MASK
- ARIZONA_ISRC1_FSH_SHIFT
- ARIZONA_ISRC1_FSH_WIDTH
- ARIZONA_ISRC1_FSL_MASK
- ARIZONA_ISRC1_FSL_SHIFT
- ARIZONA_ISRC1_FSL_WIDTH
- ARIZONA_ISRC1_INT0_ENA
- ARIZONA_ISRC1_INT0_ENA_MASK
- ARIZONA_ISRC1_INT0_ENA_SHIFT
- ARIZONA_ISRC1_INT0_ENA_WIDTH
- ARIZONA_ISRC1_INT1_ENA
- ARIZONA_ISRC1_INT1_ENA_MASK
- ARIZONA_ISRC1_INT1_ENA_SHIFT
- ARIZONA_ISRC1_INT1_ENA_WIDTH
- ARIZONA_ISRC1_INT2_ENA
- ARIZONA_ISRC1_INT2_ENA_MASK
- ARIZONA_ISRC1_INT2_ENA_SHIFT
- ARIZONA_ISRC1_INT2_ENA_WIDTH
- ARIZONA_ISRC1_INT3_ENA
- ARIZONA_ISRC1_INT3_ENA_MASK
- ARIZONA_ISRC1_INT3_ENA_SHIFT
- ARIZONA_ISRC1_INT3_ENA_WIDTH
- ARIZONA_ISRC1_NOTCH_ENA
- ARIZONA_ISRC1_NOTCH_ENA_MASK
- ARIZONA_ISRC1_NOTCH_ENA_SHIFT
- ARIZONA_ISRC1_NOTCH_ENA_WIDTH
- ARIZONA_ISRC1_OVERCLOCKED_STS
- ARIZONA_ISRC1_OVERCLOCKED_STS_MASK
- ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT
- ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH
- ARIZONA_ISRC1_UNDERCLOCKED_STS
- ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK
- ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT
- ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH
- ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC2_CFG_ERR_EINT1
- ARIZONA_ISRC2_CFG_ERR_EINT1_MASK
- ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT
- ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH
- ARIZONA_ISRC2_CFG_ERR_EINT2
- ARIZONA_ISRC2_CFG_ERR_EINT2_MASK
- ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT
- ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH
- ARIZONA_ISRC2_CFG_ERR_STS
- ARIZONA_ISRC2_CFG_ERR_STS_MASK
- ARIZONA_ISRC2_CFG_ERR_STS_SHIFT
- ARIZONA_ISRC2_CFG_ERR_STS_WIDTH
- ARIZONA_ISRC2_CLK_SEL_MASK
- ARIZONA_ISRC2_CLK_SEL_SHIFT
- ARIZONA_ISRC2_CLK_SEL_WIDTH
- ARIZONA_ISRC2_DEC0_ENA
- ARIZONA_ISRC2_DEC0_ENA_MASK
- ARIZONA_ISRC2_DEC0_ENA_SHIFT
- ARIZONA_ISRC2_DEC0_ENA_WIDTH
- ARIZONA_ISRC2_DEC1_ENA
- ARIZONA_ISRC2_DEC1_ENA_MASK
- ARIZONA_ISRC2_DEC1_ENA_SHIFT
- ARIZONA_ISRC2_DEC1_ENA_WIDTH
- ARIZONA_ISRC2_DEC2_ENA
- ARIZONA_ISRC2_DEC2_ENA_MASK
- ARIZONA_ISRC2_DEC2_ENA_SHIFT
- ARIZONA_ISRC2_DEC2_ENA_WIDTH
- ARIZONA_ISRC2_DEC3_ENA
- ARIZONA_ISRC2_DEC3_ENA_MASK
- ARIZONA_ISRC2_DEC3_ENA_SHIFT
- ARIZONA_ISRC2_DEC3_ENA_WIDTH
- ARIZONA_ISRC2_FSH_MASK
- ARIZONA_ISRC2_FSH_SHIFT
- ARIZONA_ISRC2_FSH_WIDTH
- ARIZONA_ISRC2_FSL_MASK
- ARIZONA_ISRC2_FSL_SHIFT
- ARIZONA_ISRC2_FSL_WIDTH
- ARIZONA_ISRC2_INT0_ENA
- ARIZONA_ISRC2_INT0_ENA_MASK
- ARIZONA_ISRC2_INT0_ENA_SHIFT
- ARIZONA_ISRC2_INT0_ENA_WIDTH
- ARIZONA_ISRC2_INT1_ENA
- ARIZONA_ISRC2_INT1_ENA_MASK
- ARIZONA_ISRC2_INT1_ENA_SHIFT
- ARIZONA_ISRC2_INT1_ENA_WIDTH
- ARIZONA_ISRC2_INT2_ENA
- ARIZONA_ISRC2_INT2_ENA_MASK
- ARIZONA_ISRC2_INT2_ENA_SHIFT
- ARIZONA_ISRC2_INT2_ENA_WIDTH
- ARIZONA_ISRC2_INT3_ENA
- ARIZONA_ISRC2_INT3_ENA_MASK
- ARIZONA_ISRC2_INT3_ENA_SHIFT
- ARIZONA_ISRC2_INT3_ENA_WIDTH
- ARIZONA_ISRC2_NOTCH_ENA
- ARIZONA_ISRC2_NOTCH_ENA_MASK
- ARIZONA_ISRC2_NOTCH_ENA_SHIFT
- ARIZONA_ISRC2_NOTCH_ENA_WIDTH
- ARIZONA_ISRC2_OVERCLOCKED_STS
- ARIZONA_ISRC2_OVERCLOCKED_STS_MASK
- ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT
- ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH
- ARIZONA_ISRC2_UNDERCLOCKED_STS
- ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK
- ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT
- ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH
- ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE
- ARIZONA_ISRC3_CLK_SEL_MASK
- ARIZONA_ISRC3_CLK_SEL_SHIFT
- ARIZONA_ISRC3_CLK_SEL_WIDTH
- ARIZONA_ISRC3_DEC0_ENA
- ARIZONA_ISRC3_DEC0_ENA_MASK
- ARIZONA_ISRC3_DEC0_ENA_SHIFT
- ARIZONA_ISRC3_DEC0_ENA_WIDTH
- ARIZONA_ISRC3_DEC1_ENA
- ARIZONA_ISRC3_DEC1_ENA_MASK
- ARIZONA_ISRC3_DEC1_ENA_SHIFT
- ARIZONA_ISRC3_DEC1_ENA_WIDTH
- ARIZONA_ISRC3_DEC2_ENA
- ARIZONA_ISRC3_DEC2_ENA_MASK
- ARIZONA_ISRC3_DEC2_ENA_SHIFT
- ARIZONA_ISRC3_DEC2_ENA_WIDTH
- ARIZONA_ISRC3_DEC3_ENA
- ARIZONA_ISRC3_DEC3_ENA_MASK
- ARIZONA_ISRC3_DEC3_ENA_SHIFT
- ARIZONA_ISRC3_DEC3_ENA_WIDTH
- ARIZONA_ISRC3_FSH_MASK
- ARIZONA_ISRC3_FSH_SHIFT
- ARIZONA_ISRC3_FSH_WIDTH
- ARIZONA_ISRC3_FSL_MASK
- ARIZONA_ISRC3_FSL_SHIFT
- ARIZONA_ISRC3_FSL_WIDTH
- ARIZONA_ISRC3_INT0_ENA
- ARIZONA_ISRC3_INT0_ENA_MASK
- ARIZONA_ISRC3_INT0_ENA_SHIFT
- ARIZONA_ISRC3_INT0_ENA_WIDTH
- ARIZONA_ISRC3_INT1_ENA
- ARIZONA_ISRC3_INT1_ENA_MASK
- ARIZONA_ISRC3_INT1_ENA_SHIFT
- ARIZONA_ISRC3_INT1_ENA_WIDTH
- ARIZONA_ISRC3_INT2_ENA
- ARIZONA_ISRC3_INT2_ENA_MASK
- ARIZONA_ISRC3_INT2_ENA_SHIFT
- ARIZONA_ISRC3_INT2_ENA_WIDTH
- ARIZONA_ISRC3_INT3_ENA
- ARIZONA_ISRC3_INT3_ENA_MASK
- ARIZONA_ISRC3_INT3_ENA_SHIFT
- ARIZONA_ISRC3_INT3_ENA_WIDTH
- ARIZONA_ISRC3_NOTCH_ENA
- ARIZONA_ISRC3_NOTCH_ENA_MASK
- ARIZONA_ISRC3_NOTCH_ENA_SHIFT
- ARIZONA_ISRC3_NOTCH_ENA_WIDTH
- ARIZONA_ISRC3_OVERCLOCKED_STS
- ARIZONA_ISRC3_OVERCLOCKED_STS_MASK
- ARIZONA_ISRC3_OVERCLOCKED_STS_SHIFT
- ARIZONA_ISRC3_OVERCLOCKED_STS_WIDTH
- ARIZONA_ISRC3_UNDERCLOCKED_STS
- ARIZONA_ISRC3_UNDERCLOCKED_STS_MASK
- ARIZONA_ISRC3_UNDERCLOCKED_STS_SHIFT
- ARIZONA_ISRC3_UNDERCLOCKED_STS_WIDTH
- ARIZONA_ISRC_1_CTRL_1
- ARIZONA_ISRC_1_CTRL_2
- ARIZONA_ISRC_1_CTRL_3
- ARIZONA_ISRC_2_CTRL_1
- ARIZONA_ISRC_2_CTRL_2
- ARIZONA_ISRC_2_CTRL_3
- ARIZONA_ISRC_3_CTRL_1
- ARIZONA_ISRC_3_CTRL_2
- ARIZONA_ISRC_3_CTRL_3
- ARIZONA_JACK_DETECT_ANALOGUE
- ARIZONA_JACK_DETECT_DEBOUNCE
- ARIZONA_JD1_DB
- ARIZONA_JD1_DB_MASK
- ARIZONA_JD1_DB_SHIFT
- ARIZONA_JD1_DB_WIDTH
- ARIZONA_JD1_ENA
- ARIZONA_JD1_ENA_MASK
- ARIZONA_JD1_ENA_SHIFT
- ARIZONA_JD1_ENA_WIDTH
- ARIZONA_JD1_FALL_EINT1
- ARIZONA_JD1_FALL_EINT1_MASK
- ARIZONA_JD1_FALL_EINT1_SHIFT
- ARIZONA_JD1_FALL_EINT1_WIDTH
- ARIZONA_JD1_FALL_EINT2
- ARIZONA_JD1_FALL_EINT2_MASK
- ARIZONA_JD1_FALL_EINT2_SHIFT
- ARIZONA_JD1_FALL_EINT2_WIDTH
- ARIZONA_JD1_FALL_TRIG_STS
- ARIZONA_JD1_FALL_TRIG_STS_MASK
- ARIZONA_JD1_FALL_TRIG_STS_SHIFT
- ARIZONA_JD1_FALL_TRIG_STS_WIDTH
- ARIZONA_JD1_RISE_EINT1
- ARIZONA_JD1_RISE_EINT1_MASK
- ARIZONA_JD1_RISE_EINT1_SHIFT
- ARIZONA_JD1_RISE_EINT1_WIDTH
- ARIZONA_JD1_RISE_EINT2
- ARIZONA_JD1_RISE_EINT2_MASK
- ARIZONA_JD1_RISE_EINT2_SHIFT
- ARIZONA_JD1_RISE_EINT2_WIDTH
- ARIZONA_JD1_RISE_TRIG_STS
- ARIZONA_JD1_RISE_TRIG_STS_MASK
- ARIZONA_JD1_RISE_TRIG_STS_SHIFT
- ARIZONA_JD1_RISE_TRIG_STS_WIDTH
- ARIZONA_JD1_STS
- ARIZONA_JD1_STS_MASK
- ARIZONA_JD1_STS_SHIFT
- ARIZONA_JD1_STS_WIDTH
- ARIZONA_JD2_DB
- ARIZONA_JD2_DB_MASK
- ARIZONA_JD2_DB_SHIFT
- ARIZONA_JD2_DB_WIDTH
- ARIZONA_JD2_ENA
- ARIZONA_JD2_ENA_MASK
- ARIZONA_JD2_ENA_SHIFT
- ARIZONA_JD2_ENA_WIDTH
- ARIZONA_JD2_FALL_EINT1
- ARIZONA_JD2_FALL_EINT1_MASK
- ARIZONA_JD2_FALL_EINT1_SHIFT
- ARIZONA_JD2_FALL_EINT1_WIDTH
- ARIZONA_JD2_FALL_EINT2
- ARIZONA_JD2_FALL_EINT2_MASK
- ARIZONA_JD2_FALL_EINT2_SHIFT
- ARIZONA_JD2_FALL_EINT2_WIDTH
- ARIZONA_JD2_FALL_TRIG_STS
- ARIZONA_JD2_FALL_TRIG_STS_MASK
- ARIZONA_JD2_FALL_TRIG_STS_SHIFT
- ARIZONA_JD2_FALL_TRIG_STS_WIDTH
- ARIZONA_JD2_RISE_EINT1
- ARIZONA_JD2_RISE_EINT1_MASK
- ARIZONA_JD2_RISE_EINT1_SHIFT
- ARIZONA_JD2_RISE_EINT1_WIDTH
- ARIZONA_JD2_RISE_EINT2
- ARIZONA_JD2_RISE_EINT2_MASK
- ARIZONA_JD2_RISE_EINT2_SHIFT
- ARIZONA_JD2_RISE_EINT2_WIDTH
- ARIZONA_JD2_RISE_TRIG_STS
- ARIZONA_JD2_RISE_TRIG_STS_MASK
- ARIZONA_JD2_RISE_TRIG_STS_SHIFT
- ARIZONA_JD2_RISE_TRIG_STS_WIDTH
- ARIZONA_JD2_STS
- ARIZONA_JD2_STS_MASK
- ARIZONA_JD2_STS_SHIFT
- ARIZONA_JD2_STS_WIDTH
- ARIZONA_LDO1ENA_PD
- ARIZONA_LDO1ENA_PD_MASK
- ARIZONA_LDO1ENA_PD_SHIFT
- ARIZONA_LDO1ENA_PD_WIDTH
- ARIZONA_LDO1_BYPASS
- ARIZONA_LDO1_BYPASS_MASK
- ARIZONA_LDO1_BYPASS_SHIFT
- ARIZONA_LDO1_BYPASS_WIDTH
- ARIZONA_LDO1_CONTROL_1
- ARIZONA_LDO1_CONTROL_2
- ARIZONA_LDO1_DISCH
- ARIZONA_LDO1_DISCH_MASK
- ARIZONA_LDO1_DISCH_SHIFT
- ARIZONA_LDO1_DISCH_WIDTH
- ARIZONA_LDO1_ENA
- ARIZONA_LDO1_ENA_MASK
- ARIZONA_LDO1_ENA_SHIFT
- ARIZONA_LDO1_ENA_WIDTH
- ARIZONA_LDO1_FAST
- ARIZONA_LDO1_FAST_MASK
- ARIZONA_LDO1_FAST_SHIFT
- ARIZONA_LDO1_FAST_WIDTH
- ARIZONA_LDO1_H
- ARIZONA_LDO1_HI_PWR
- ARIZONA_LDO1_HI_PWR_SHIFT
- ARIZONA_LDO1_HI_PWR_WIDTH
- ARIZONA_LDO1_VSEL_MASK
- ARIZONA_LDO1_VSEL_SHIFT
- ARIZONA_LDO1_VSEL_WIDTH
- ARIZONA_LDO2_BYPASS
- ARIZONA_LDO2_BYPASS_MASK
- ARIZONA_LDO2_BYPASS_SHIFT
- ARIZONA_LDO2_BYPASS_WIDTH
- ARIZONA_LDO2_CONTROL_1
- ARIZONA_LDO2_DISCH
- ARIZONA_LDO2_DISCH_MASK
- ARIZONA_LDO2_DISCH_SHIFT
- ARIZONA_LDO2_DISCH_WIDTH
- ARIZONA_LDO2_ENA
- ARIZONA_LDO2_ENA_MASK
- ARIZONA_LDO2_ENA_SHIFT
- ARIZONA_LDO2_ENA_WIDTH
- ARIZONA_LDO2_FAST
- ARIZONA_LDO2_FAST_MASK
- ARIZONA_LDO2_FAST_SHIFT
- ARIZONA_LDO2_FAST_WIDTH
- ARIZONA_LDO2_VSEL_MASK
- ARIZONA_LDO2_VSEL_SHIFT
- ARIZONA_LDO2_VSEL_WIDTH
- ARIZONA_LHPF1_COEFF_MASK
- ARIZONA_LHPF1_COEFF_SHIFT
- ARIZONA_LHPF1_COEFF_WIDTH
- ARIZONA_LHPF1_ENA
- ARIZONA_LHPF1_ENA_MASK
- ARIZONA_LHPF1_ENA_SHIFT
- ARIZONA_LHPF1_ENA_WIDTH
- ARIZONA_LHPF1_MODE
- ARIZONA_LHPF1_MODE_MASK
- ARIZONA_LHPF1_MODE_SHIFT
- ARIZONA_LHPF1_MODE_WIDTH
- ARIZONA_LHPF2_COEFF_MASK
- ARIZONA_LHPF2_COEFF_SHIFT
- ARIZONA_LHPF2_COEFF_WIDTH
- ARIZONA_LHPF2_ENA
- ARIZONA_LHPF2_ENA_MASK
- ARIZONA_LHPF2_ENA_SHIFT
- ARIZONA_LHPF2_ENA_WIDTH
- ARIZONA_LHPF2_MODE
- ARIZONA_LHPF2_MODE_MASK
- ARIZONA_LHPF2_MODE_SHIFT
- ARIZONA_LHPF2_MODE_WIDTH
- ARIZONA_LHPF3_COEFF_MASK
- ARIZONA_LHPF3_COEFF_SHIFT
- ARIZONA_LHPF3_COEFF_WIDTH
- ARIZONA_LHPF3_ENA
- ARIZONA_LHPF3_ENA_MASK
- ARIZONA_LHPF3_ENA_SHIFT
- ARIZONA_LHPF3_ENA_WIDTH
- ARIZONA_LHPF3_MODE
- ARIZONA_LHPF3_MODE_MASK
- ARIZONA_LHPF3_MODE_SHIFT
- ARIZONA_LHPF3_MODE_WIDTH
- ARIZONA_LHPF4_COEFF_MASK
- ARIZONA_LHPF4_COEFF_SHIFT
- ARIZONA_LHPF4_COEFF_WIDTH
- ARIZONA_LHPF4_ENA
- ARIZONA_LHPF4_ENA_MASK
- ARIZONA_LHPF4_ENA_SHIFT
- ARIZONA_LHPF4_ENA_WIDTH
- ARIZONA_LHPF4_MODE
- ARIZONA_LHPF4_MODE_MASK
- ARIZONA_LHPF4_MODE_SHIFT
- ARIZONA_LHPF4_MODE_WIDTH
- ARIZONA_LHPF_CONTROL
- ARIZONA_LOAD_DEFAULTS
- ARIZONA_LOAD_DEFAULTS_MASK
- ARIZONA_LOAD_DEFAULTS_SHIFT
- ARIZONA_LOAD_DEFAULTS_WIDTH
- ARIZONA_LRA_FREQ_MASK
- ARIZONA_LRA_FREQ_SHIFT
- ARIZONA_LRA_FREQ_WIDTH
- ARIZONA_LRCLK_SRC_MASK
- ARIZONA_LRCLK_SRC_SHIFT
- ARIZONA_LRCLK_SRC_WIDTH
- ARIZONA_MAIN_IRQ_INDEX
- ARIZONA_MAX_ADSP
- ARIZONA_MAX_AIF
- ARIZONA_MAX_CORE_SUPPLIES
- ARIZONA_MAX_DAI
- ARIZONA_MAX_GPIO
- ARIZONA_MAX_INPUT
- ARIZONA_MAX_MICBIAS
- ARIZONA_MAX_MICD_RANGE
- ARIZONA_MAX_OUTPUT
- ARIZONA_MAX_PDM_SPK
- ARIZONA_MCLK1
- ARIZONA_MCLK1_PD
- ARIZONA_MCLK1_PD_MASK
- ARIZONA_MCLK1_PD_SHIFT
- ARIZONA_MCLK1_PD_WIDTH
- ARIZONA_MCLK2
- ARIZONA_MCLK2_PD
- ARIZONA_MCLK2_PD_MASK
- ARIZONA_MCLK2_PD_SHIFT
- ARIZONA_MCLK2_PD_WIDTH
- ARIZONA_MICB1_BYPASS
- ARIZONA_MICB1_BYPASS_MASK
- ARIZONA_MICB1_BYPASS_SHIFT
- ARIZONA_MICB1_BYPASS_WIDTH
- ARIZONA_MICB1_DISCH
- ARIZONA_MICB1_DISCH_MASK
- ARIZONA_MICB1_DISCH_SHIFT
- ARIZONA_MICB1_DISCH_WIDTH
- ARIZONA_MICB1_ENA
- ARIZONA_MICB1_ENA_MASK
- ARIZONA_MICB1_ENA_SHIFT
- ARIZONA_MICB1_ENA_WIDTH
- ARIZONA_MICB1_EXT_CAP
- ARIZONA_MICB1_EXT_CAP_MASK
- ARIZONA_MICB1_EXT_CAP_SHIFT
- ARIZONA_MICB1_EXT_CAP_WIDTH
- ARIZONA_MICB1_FAST
- ARIZONA_MICB1_FAST_MASK
- ARIZONA_MICB1_FAST_SHIFT
- ARIZONA_MICB1_FAST_WIDTH
- ARIZONA_MICB1_LVL_MASK
- ARIZONA_MICB1_LVL_SHIFT
- ARIZONA_MICB1_LVL_WIDTH
- ARIZONA_MICB1_RATE
- ARIZONA_MICB1_RATE_MASK
- ARIZONA_MICB1_RATE_SHIFT
- ARIZONA_MICB1_RATE_WIDTH
- ARIZONA_MICB2_BYPASS
- ARIZONA_MICB2_BYPASS_MASK
- ARIZONA_MICB2_BYPASS_SHIFT
- ARIZONA_MICB2_BYPASS_WIDTH
- ARIZONA_MICB2_DISCH
- ARIZONA_MICB2_DISCH_MASK
- ARIZONA_MICB2_DISCH_SHIFT
- ARIZONA_MICB2_DISCH_WIDTH
- ARIZONA_MICB2_ENA
- ARIZONA_MICB2_ENA_MASK
- ARIZONA_MICB2_ENA_SHIFT
- ARIZONA_MICB2_ENA_WIDTH
- ARIZONA_MICB2_EXT_CAP
- ARIZONA_MICB2_EXT_CAP_MASK
- ARIZONA_MICB2_EXT_CAP_SHIFT
- ARIZONA_MICB2_EXT_CAP_WIDTH
- ARIZONA_MICB2_FAST
- ARIZONA_MICB2_FAST_MASK
- ARIZONA_MICB2_FAST_SHIFT
- ARIZONA_MICB2_FAST_WIDTH
- ARIZONA_MICB2_LVL_MASK
- ARIZONA_MICB2_LVL_SHIFT
- ARIZONA_MICB2_LVL_WIDTH
- ARIZONA_MICB2_RATE
- ARIZONA_MICB2_RATE_MASK
- ARIZONA_MICB2_RATE_SHIFT
- ARIZONA_MICB2_RATE_WIDTH
- ARIZONA_MICB3_BYPASS
- ARIZONA_MICB3_BYPASS_MASK
- ARIZONA_MICB3_BYPASS_SHIFT
- ARIZONA_MICB3_BYPASS_WIDTH
- ARIZONA_MICB3_DISCH
- ARIZONA_MICB3_DISCH_MASK
- ARIZONA_MICB3_DISCH_SHIFT
- ARIZONA_MICB3_DISCH_WIDTH
- ARIZONA_MICB3_ENA
- ARIZONA_MICB3_ENA_MASK
- ARIZONA_MICB3_ENA_SHIFT
- ARIZONA_MICB3_ENA_WIDTH
- ARIZONA_MICB3_EXT_CAP
- ARIZONA_MICB3_EXT_CAP_MASK
- ARIZONA_MICB3_EXT_CAP_SHIFT
- ARIZONA_MICB3_EXT_CAP_WIDTH
- ARIZONA_MICB3_FAST
- ARIZONA_MICB3_FAST_MASK
- ARIZONA_MICB3_FAST_SHIFT
- ARIZONA_MICB3_FAST_WIDTH
- ARIZONA_MICB3_LVL_MASK
- ARIZONA_MICB3_LVL_SHIFT
- ARIZONA_MICB3_LVL_WIDTH
- ARIZONA_MICB3_RATE
- ARIZONA_MICB3_RATE_MASK
- ARIZONA_MICB3_RATE_SHIFT
- ARIZONA_MICB3_RATE_WIDTH
- ARIZONA_MICDET_ADCVAL_DIFF_MASK
- ARIZONA_MICDET_ADCVAL_DIFF_SHIFT
- ARIZONA_MICDET_ADCVAL_DIFF_WIDTH
- ARIZONA_MICDET_ADCVAL_MASK
- ARIZONA_MICDET_ADCVAL_SHIFT
- ARIZONA_MICDET_ADCVAL_WIDTH
- ARIZONA_MICDET_EINT1
- ARIZONA_MICDET_EINT1_MASK
- ARIZONA_MICDET_EINT1_SHIFT
- ARIZONA_MICDET_EINT1_WIDTH
- ARIZONA_MICDET_EINT2
- ARIZONA_MICDET_EINT2_MASK
- ARIZONA_MICDET_EINT2_SHIFT
- ARIZONA_MICDET_EINT2_WIDTH
- ARIZONA_MICDET_STS
- ARIZONA_MICDET_STS_MASK
- ARIZONA_MICDET_STS_SHIFT
- ARIZONA_MICDET_STS_WIDTH
- ARIZONA_MICD_BIAS_SRC_MASK
- ARIZONA_MICD_BIAS_SRC_SHIFT
- ARIZONA_MICD_BIAS_SRC_WIDTH
- ARIZONA_MICD_BIAS_STARTTIME_MASK
- ARIZONA_MICD_BIAS_STARTTIME_SHIFT
- ARIZONA_MICD_BIAS_STARTTIME_WIDTH
- ARIZONA_MICD_CLAMP_CONTROL
- ARIZONA_MICD_CLAMP_DB
- ARIZONA_MICD_CLAMP_DB_MASK
- ARIZONA_MICD_CLAMP_DB_SHIFT
- ARIZONA_MICD_CLAMP_DB_WIDTH
- ARIZONA_MICD_CLAMP_FALL_EINT1
- ARIZONA_MICD_CLAMP_FALL_EINT1_MASK
- ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT
- ARIZONA_MICD_CLAMP_FALL_EINT2
- ARIZONA_MICD_CLAMP_FALL_EINT2_MASK
- ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT
- ARIZONA_MICD_CLAMP_FALL_TRIG_STS
- ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK
- ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT
- ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH
- ARIZONA_MICD_CLAMP_MODE_JDH
- ARIZONA_MICD_CLAMP_MODE_JDH_GP5H
- ARIZONA_MICD_CLAMP_MODE_JDL
- ARIZONA_MICD_CLAMP_MODE_JDL_GP5H
- ARIZONA_MICD_CLAMP_MODE_MASK
- ARIZONA_MICD_CLAMP_MODE_SHIFT
- ARIZONA_MICD_CLAMP_MODE_WIDTH
- ARIZONA_MICD_CLAMP_RISE_EINT1
- ARIZONA_MICD_CLAMP_RISE_EINT1_MASK
- ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT
- ARIZONA_MICD_CLAMP_RISE_EINT2
- ARIZONA_MICD_CLAMP_RISE_EINT2_MASK
- ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT
- ARIZONA_MICD_CLAMP_RISE_TRIG_STS
- ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK
- ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT
- ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH
- ARIZONA_MICD_CLAMP_STS
- ARIZONA_MICD_CLAMP_STS_MASK
- ARIZONA_MICD_CLAMP_STS_SHIFT
- ARIZONA_MICD_CLAMP_STS_WIDTH
- ARIZONA_MICD_DBTIME
- ARIZONA_MICD_DBTIME_MASK
- ARIZONA_MICD_DBTIME_SHIFT
- ARIZONA_MICD_DBTIME_WIDTH
- ARIZONA_MICD_ENA
- ARIZONA_MICD_ENA_MASK
- ARIZONA_MICD_ENA_SHIFT
- ARIZONA_MICD_ENA_WIDTH
- ARIZONA_MICD_LVL_0
- ARIZONA_MICD_LVL_1
- ARIZONA_MICD_LVL_2
- ARIZONA_MICD_LVL_3
- ARIZONA_MICD_LVL_4
- ARIZONA_MICD_LVL_5
- ARIZONA_MICD_LVL_6
- ARIZONA_MICD_LVL_7
- ARIZONA_MICD_LVL_8
- ARIZONA_MICD_LVL_MASK
- ARIZONA_MICD_LVL_SEL_MASK
- ARIZONA_MICD_LVL_SEL_SHIFT
- ARIZONA_MICD_LVL_SEL_WIDTH
- ARIZONA_MICD_LVL_SHIFT
- ARIZONA_MICD_LVL_WIDTH
- ARIZONA_MICD_PD
- ARIZONA_MICD_PD_MASK
- ARIZONA_MICD_PD_SHIFT
- ARIZONA_MICD_PD_WIDTH
- ARIZONA_MICD_RATE_MASK
- ARIZONA_MICD_RATE_SHIFT
- ARIZONA_MICD_RATE_WIDTH
- ARIZONA_MICD_STS
- ARIZONA_MICD_STS_MASK
- ARIZONA_MICD_STS_SHIFT
- ARIZONA_MICD_STS_WIDTH
- ARIZONA_MICD_TIME_128MS
- ARIZONA_MICD_TIME_16MS
- ARIZONA_MICD_TIME_1MS
- ARIZONA_MICD_TIME_250US
- ARIZONA_MICD_TIME_256MS
- ARIZONA_MICD_TIME_2MS
- ARIZONA_MICD_TIME_32MS
- ARIZONA_MICD_TIME_4MS
- ARIZONA_MICD_TIME_500US
- ARIZONA_MICD_TIME_512MS
- ARIZONA_MICD_TIME_64MS
- ARIZONA_MICD_TIME_8MS
- ARIZONA_MICD_TIME_CONTINUOUS
- ARIZONA_MICD_VALID
- ARIZONA_MICD_VALID_MASK
- ARIZONA_MICD_VALID_SHIFT
- ARIZONA_MICD_VALID_WIDTH
- ARIZONA_MICMIX_INPUT_1_SOURCE
- ARIZONA_MICMIX_INPUT_1_VOLUME
- ARIZONA_MICMIX_INPUT_2_SOURCE
- ARIZONA_MICMIX_INPUT_2_VOLUME
- ARIZONA_MICMIX_INPUT_3_SOURCE
- ARIZONA_MICMIX_INPUT_3_VOLUME
- ARIZONA_MICMIX_INPUT_4_SOURCE
- ARIZONA_MICMIX_INPUT_4_VOLUME
- ARIZONA_MICMUTE_MIX_ENA
- ARIZONA_MICMUTE_MIX_ENA_MASK
- ARIZONA_MICMUTE_MIX_ENA_SHIFT
- ARIZONA_MICMUTE_MIX_ENA_WIDTH
- ARIZONA_MICMUTE_RATE_MASK
- ARIZONA_MICMUTE_RATE_SHIFT
- ARIZONA_MICMUTE_RATE_WIDTH
- ARIZONA_MICSUPP_H
- ARIZONA_MIC_BIAS_CTRL_1
- ARIZONA_MIC_BIAS_CTRL_2
- ARIZONA_MIC_BIAS_CTRL_3
- ARIZONA_MIC_CHARGE_PUMP_1
- ARIZONA_MIC_DETECT_1
- ARIZONA_MIC_DETECT_2
- ARIZONA_MIC_DETECT_3
- ARIZONA_MIC_DETECT_4
- ARIZONA_MIC_DETECT_LEVEL_1
- ARIZONA_MIC_DETECT_LEVEL_2
- ARIZONA_MIC_DETECT_LEVEL_3
- ARIZONA_MIC_DETECT_LEVEL_4
- ARIZONA_MIC_NOISE_MIX_CONTROL_1
- ARIZONA_MISC_PAD_CTRL_1
- ARIZONA_MISC_PAD_CTRL_10
- ARIZONA_MISC_PAD_CTRL_11
- ARIZONA_MISC_PAD_CTRL_12
- ARIZONA_MISC_PAD_CTRL_13
- ARIZONA_MISC_PAD_CTRL_14
- ARIZONA_MISC_PAD_CTRL_15
- ARIZONA_MISC_PAD_CTRL_16
- ARIZONA_MISC_PAD_CTRL_17
- ARIZONA_MISC_PAD_CTRL_18
- ARIZONA_MISC_PAD_CTRL_2
- ARIZONA_MISC_PAD_CTRL_3
- ARIZONA_MISC_PAD_CTRL_4
- ARIZONA_MISC_PAD_CTRL_5
- ARIZONA_MISC_PAD_CTRL_6
- ARIZONA_MISC_PAD_CTRL_7
- ARIZONA_MISC_PAD_CTRL_8
- ARIZONA_MISC_PAD_CTRL_9
- ARIZONA_MIXER_CONTROLS
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT2
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT
- ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH
- ARIZONA_MIXER_DROPPED_SAMPLE_STS
- ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK
- ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT
- ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH
- ARIZONA_MIXER_ENUMS
- ARIZONA_MIXER_INPUT_ROUTES
- ARIZONA_MIXER_OVERCLOCKED_STS
- ARIZONA_MIXER_OVERCLOCKED_STS_MASK
- ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT
- ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH
- ARIZONA_MIXER_ROUTES
- ARIZONA_MIXER_UNDERCLOCKED_STS
- ARIZONA_MIXER_UNDERCLOCKED_STS_MASK
- ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT
- ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH
- ARIZONA_MIXER_VOL_MASK
- ARIZONA_MIXER_VOL_SHIFT
- ARIZONA_MIXER_VOL_WIDTH
- ARIZONA_MIXER_WIDGETS
- ARIZONA_MUX
- ARIZONA_MUX_CTL_DECL
- ARIZONA_MUX_ENUMS
- ARIZONA_MUX_ENUM_DECL
- ARIZONA_MUX_ROUTES
- ARIZONA_MUX_WIDGETS
- ARIZONA_NGATE_ENA
- ARIZONA_NGATE_ENA_MASK
- ARIZONA_NGATE_ENA_SHIFT
- ARIZONA_NGATE_ENA_WIDTH
- ARIZONA_NGATE_HOLD_MASK
- ARIZONA_NGATE_HOLD_SHIFT
- ARIZONA_NGATE_HOLD_WIDTH
- ARIZONA_NGATE_THR_MASK
- ARIZONA_NGATE_THR_SHIFT
- ARIZONA_NGATE_THR_WIDTH
- ARIZONA_NOISEMIX_INPUT_1_SOURCE
- ARIZONA_NOISEMIX_INPUT_1_VOLUME
- ARIZONA_NOISEMIX_INPUT_2_SOURCE
- ARIZONA_NOISEMIX_INPUT_2_VOLUME
- ARIZONA_NOISEMIX_INPUT_3_SOURCE
- ARIZONA_NOISEMIX_INPUT_3_VOLUME
- ARIZONA_NOISEMIX_INPUT_4_SOURCE
- ARIZONA_NOISEMIX_INPUT_4_VOLUME
- ARIZONA_NOISE_GATE_CONTROL
- ARIZONA_NOISE_GATE_SELECT_1L
- ARIZONA_NOISE_GATE_SELECT_1R
- ARIZONA_NOISE_GATE_SELECT_2L
- ARIZONA_NOISE_GATE_SELECT_2R
- ARIZONA_NOISE_GATE_SELECT_3L
- ARIZONA_NOISE_GATE_SELECT_3R
- ARIZONA_NOISE_GATE_SELECT_4L
- ARIZONA_NOISE_GATE_SELECT_4R
- ARIZONA_NOISE_GATE_SELECT_5L
- ARIZONA_NOISE_GATE_SELECT_5R
- ARIZONA_NOISE_GATE_SELECT_6L
- ARIZONA_NOISE_GATE_SELECT_6R
- ARIZONA_NOISE_GEN_ENA
- ARIZONA_NOISE_GEN_ENA_MASK
- ARIZONA_NOISE_GEN_ENA_SHIFT
- ARIZONA_NOISE_GEN_ENA_WIDTH
- ARIZONA_NOISE_GEN_GAIN_MASK
- ARIZONA_NOISE_GEN_GAIN_SHIFT
- ARIZONA_NOISE_GEN_GAIN_WIDTH
- ARIZONA_NOISE_GEN_RATE_MASK
- ARIZONA_NOISE_GEN_RATE_SHIFT
- ARIZONA_NOISE_GEN_RATE_WIDTH
- ARIZONA_NOTIFY_VOICE_TRIGGER
- ARIZONA_NUM_IRQ
- ARIZONA_NUM_MCLK
- ARIZONA_NUM_MICD_BUTTON_LEVELS
- ARIZONA_NUM_MIXER_INPUTS
- ARIZONA_ONESHOT_STS
- ARIZONA_ONESHOT_STS_MASK
- ARIZONA_ONESHOT_STS_SHIFT
- ARIZONA_ONESHOT_STS_WIDTH
- ARIZONA_ONESHOT_TRIG
- ARIZONA_ONESHOT_TRIG_MASK
- ARIZONA_ONESHOT_TRIG_SHIFT
- ARIZONA_ONESHOT_TRIG_WIDTH
- ARIZONA_OPCLK_ASYNC_DIV_MASK
- ARIZONA_OPCLK_ASYNC_DIV_SHIFT
- ARIZONA_OPCLK_ASYNC_DIV_WIDTH
- ARIZONA_OPCLK_ASYNC_ENA
- ARIZONA_OPCLK_ASYNC_ENA_MASK
- ARIZONA_OPCLK_ASYNC_ENA_SHIFT
- ARIZONA_OPCLK_ASYNC_ENA_WIDTH
- ARIZONA_OPCLK_ASYNC_SEL_MASK
- ARIZONA_OPCLK_ASYNC_SEL_SHIFT
- ARIZONA_OPCLK_ASYNC_SEL_WIDTH
- ARIZONA_OPCLK_DIV_MASK
- ARIZONA_OPCLK_DIV_SHIFT
- ARIZONA_OPCLK_DIV_WIDTH
- ARIZONA_OPCLK_ENA
- ARIZONA_OPCLK_ENA_MASK
- ARIZONA_OPCLK_ENA_SHIFT
- ARIZONA_OPCLK_ENA_WIDTH
- ARIZONA_OPCLK_SEL_MASK
- ARIZONA_OPCLK_SEL_SHIFT
- ARIZONA_OPCLK_SEL_WIDTH
- ARIZONA_OUT1LMIX_INPUT_1_SOURCE
- ARIZONA_OUT1LMIX_INPUT_1_VOLUME
- ARIZONA_OUT1LMIX_INPUT_2_SOURCE
- ARIZONA_OUT1LMIX_INPUT_2_VOLUME
- ARIZONA_OUT1LMIX_INPUT_3_SOURCE
- ARIZONA_OUT1LMIX_INPUT_3_VOLUME
- ARIZONA_OUT1LMIX_INPUT_4_SOURCE
- ARIZONA_OUT1LMIX_INPUT_4_VOLUME
- ARIZONA_OUT1L_ANC_SRC_MASK
- ARIZONA_OUT1L_ANC_SRC_SHIFT
- ARIZONA_OUT1L_ANC_SRC_WIDTH
- ARIZONA_OUT1L_ENA
- ARIZONA_OUT1L_ENA_MASK
- ARIZONA_OUT1L_ENA_SHIFT
- ARIZONA_OUT1L_ENA_WIDTH
- ARIZONA_OUT1L_MUTE
- ARIZONA_OUT1L_MUTE_MASK
- ARIZONA_OUT1L_MUTE_SHIFT
- ARIZONA_OUT1L_MUTE_WIDTH
- ARIZONA_OUT1L_NGATE_SRC_MASK
- ARIZONA_OUT1L_NGATE_SRC_SHIFT
- ARIZONA_OUT1L_NGATE_SRC_WIDTH
- ARIZONA_OUT1L_PGA_VOL_MASK
- ARIZONA_OUT1L_PGA_VOL_SHIFT
- ARIZONA_OUT1L_PGA_VOL_WIDTH
- ARIZONA_OUT1L_VOL_LIM_MASK
- ARIZONA_OUT1L_VOL_LIM_SHIFT
- ARIZONA_OUT1L_VOL_LIM_WIDTH
- ARIZONA_OUT1L_VOL_MASK
- ARIZONA_OUT1L_VOL_SHIFT
- ARIZONA_OUT1L_VOL_WIDTH
- ARIZONA_OUT1RMIX_INPUT_1_SOURCE
- ARIZONA_OUT1RMIX_INPUT_1_VOLUME
- ARIZONA_OUT1RMIX_INPUT_2_SOURCE
- ARIZONA_OUT1RMIX_INPUT_2_VOLUME
- ARIZONA_OUT1RMIX_INPUT_3_SOURCE
- ARIZONA_OUT1RMIX_INPUT_3_VOLUME
- ARIZONA_OUT1RMIX_INPUT_4_SOURCE
- ARIZONA_OUT1RMIX_INPUT_4_VOLUME
- ARIZONA_OUT1R_ANC_SRC_MASK
- ARIZONA_OUT1R_ANC_SRC_SHIFT
- ARIZONA_OUT1R_ANC_SRC_WIDTH
- ARIZONA_OUT1R_ENA
- ARIZONA_OUT1R_ENA_MASK
- ARIZONA_OUT1R_ENA_SHIFT
- ARIZONA_OUT1R_ENA_WIDTH
- ARIZONA_OUT1R_MUTE
- ARIZONA_OUT1R_MUTE_MASK
- ARIZONA_OUT1R_MUTE_SHIFT
- ARIZONA_OUT1R_MUTE_WIDTH
- ARIZONA_OUT1R_NGATE_SRC_MASK
- ARIZONA_OUT1R_NGATE_SRC_SHIFT
- ARIZONA_OUT1R_NGATE_SRC_WIDTH
- ARIZONA_OUT1R_PGA_VOL_MASK
- ARIZONA_OUT1R_PGA_VOL_SHIFT
- ARIZONA_OUT1R_PGA_VOL_WIDTH
- ARIZONA_OUT1R_VOL_LIM_MASK
- ARIZONA_OUT1R_VOL_LIM_SHIFT
- ARIZONA_OUT1R_VOL_LIM_WIDTH
- ARIZONA_OUT1R_VOL_MASK
- ARIZONA_OUT1R_VOL_SHIFT
- ARIZONA_OUT1R_VOL_WIDTH
- ARIZONA_OUT1_LP_MODE
- ARIZONA_OUT1_LP_MODE_MASK
- ARIZONA_OUT1_LP_MODE_SHIFT
- ARIZONA_OUT1_LP_MODE_WIDTH
- ARIZONA_OUT1_MONO
- ARIZONA_OUT1_MONO_MASK
- ARIZONA_OUT1_MONO_SHIFT
- ARIZONA_OUT1_MONO_WIDTH
- ARIZONA_OUT1_OSR
- ARIZONA_OUT1_OSR_MASK
- ARIZONA_OUT1_OSR_SHIFT
- ARIZONA_OUT1_OSR_WIDTH
- ARIZONA_OUT2LMIX_INPUT_1_SOURCE
- ARIZONA_OUT2LMIX_INPUT_1_VOLUME
- ARIZONA_OUT2LMIX_INPUT_2_SOURCE
- ARIZONA_OUT2LMIX_INPUT_2_VOLUME
- ARIZONA_OUT2LMIX_INPUT_3_SOURCE
- ARIZONA_OUT2LMIX_INPUT_3_VOLUME
- ARIZONA_OUT2LMIX_INPUT_4_SOURCE
- ARIZONA_OUT2LMIX_INPUT_4_VOLUME
- ARIZONA_OUT2L_ANC_SRC_MASK
- ARIZONA_OUT2L_ANC_SRC_SHIFT
- ARIZONA_OUT2L_ANC_SRC_WIDTH
- ARIZONA_OUT2L_ENA
- ARIZONA_OUT2L_ENA_MASK
- ARIZONA_OUT2L_ENA_SHIFT
- ARIZONA_OUT2L_ENA_WIDTH
- ARIZONA_OUT2L_MUTE
- ARIZONA_OUT2L_MUTE_MASK
- ARIZONA_OUT2L_MUTE_SHIFT
- ARIZONA_OUT2L_MUTE_WIDTH
- ARIZONA_OUT2L_NGATE_SRC_MASK
- ARIZONA_OUT2L_NGATE_SRC_SHIFT
- ARIZONA_OUT2L_NGATE_SRC_WIDTH
- ARIZONA_OUT2L_PGA_VOL_MASK
- ARIZONA_OUT2L_PGA_VOL_SHIFT
- ARIZONA_OUT2L_PGA_VOL_WIDTH
- ARIZONA_OUT2L_VOL_LIM_MASK
- ARIZONA_OUT2L_VOL_LIM_SHIFT
- ARIZONA_OUT2L_VOL_LIM_WIDTH
- ARIZONA_OUT2L_VOL_MASK
- ARIZONA_OUT2L_VOL_SHIFT
- ARIZONA_OUT2L_VOL_WIDTH
- ARIZONA_OUT2RMIX_INPUT_1_SOURCE
- ARIZONA_OUT2RMIX_INPUT_1_VOLUME
- ARIZONA_OUT2RMIX_INPUT_2_SOURCE
- ARIZONA_OUT2RMIX_INPUT_2_VOLUME
- ARIZONA_OUT2RMIX_INPUT_3_SOURCE
- ARIZONA_OUT2RMIX_INPUT_3_VOLUME
- ARIZONA_OUT2RMIX_INPUT_4_SOURCE
- ARIZONA_OUT2RMIX_INPUT_4_VOLUME
- ARIZONA_OUT2R_ANC_SRC_MASK
- ARIZONA_OUT2R_ANC_SRC_SHIFT
- ARIZONA_OUT2R_ANC_SRC_WIDTH
- ARIZONA_OUT2R_ENA
- ARIZONA_OUT2R_ENA_MASK
- ARIZONA_OUT2R_ENA_SHIFT
- ARIZONA_OUT2R_ENA_WIDTH
- ARIZONA_OUT2R_MUTE
- ARIZONA_OUT2R_MUTE_MASK
- ARIZONA_OUT2R_MUTE_SHIFT
- ARIZONA_OUT2R_MUTE_WIDTH
- ARIZONA_OUT2R_NGATE_SRC_MASK
- ARIZONA_OUT2R_NGATE_SRC_SHIFT
- ARIZONA_OUT2R_NGATE_SRC_WIDTH
- ARIZONA_OUT2R_PGA_VOL_MASK
- ARIZONA_OUT2R_PGA_VOL_SHIFT
- ARIZONA_OUT2R_PGA_VOL_WIDTH
- ARIZONA_OUT2R_VOL_LIM_MASK
- ARIZONA_OUT2R_VOL_LIM_SHIFT
- ARIZONA_OUT2R_VOL_LIM_WIDTH
- ARIZONA_OUT2R_VOL_MASK
- ARIZONA_OUT2R_VOL_SHIFT
- ARIZONA_OUT2R_VOL_WIDTH
- ARIZONA_OUT2_LP_MODE
- ARIZONA_OUT2_LP_MODE_MASK
- ARIZONA_OUT2_LP_MODE_SHIFT
- ARIZONA_OUT2_LP_MODE_WIDTH
- ARIZONA_OUT2_MONO
- ARIZONA_OUT2_MONO_MASK
- ARIZONA_OUT2_MONO_SHIFT
- ARIZONA_OUT2_MONO_WIDTH
- ARIZONA_OUT2_OSR
- ARIZONA_OUT2_OSR_MASK
- ARIZONA_OUT2_OSR_SHIFT
- ARIZONA_OUT2_OSR_WIDTH
- ARIZONA_OUT3LMIX_INPUT_1_SOURCE
- ARIZONA_OUT3LMIX_INPUT_1_VOLUME
- ARIZONA_OUT3LMIX_INPUT_2_SOURCE
- ARIZONA_OUT3LMIX_INPUT_2_VOLUME
- ARIZONA_OUT3LMIX_INPUT_3_SOURCE
- ARIZONA_OUT3LMIX_INPUT_3_VOLUME
- ARIZONA_OUT3LMIX_INPUT_4_SOURCE
- ARIZONA_OUT3LMIX_INPUT_4_VOLUME
- ARIZONA_OUT3L_ANC_SRC_MASK
- ARIZONA_OUT3L_ANC_SRC_SHIFT
- ARIZONA_OUT3L_ANC_SRC_WIDTH
- ARIZONA_OUT3L_ENA
- ARIZONA_OUT3L_ENA_MASK
- ARIZONA_OUT3L_ENA_SHIFT
- ARIZONA_OUT3L_ENA_WIDTH
- ARIZONA_OUT3L_MUTE
- ARIZONA_OUT3L_MUTE_MASK
- ARIZONA_OUT3L_MUTE_SHIFT
- ARIZONA_OUT3L_MUTE_WIDTH
- ARIZONA_OUT3L_PGA_VOL_MASK
- ARIZONA_OUT3L_PGA_VOL_SHIFT
- ARIZONA_OUT3L_PGA_VOL_WIDTH
- ARIZONA_OUT3L_VOL_LIM_MASK
- ARIZONA_OUT3L_VOL_LIM_SHIFT
- ARIZONA_OUT3L_VOL_LIM_WIDTH
- ARIZONA_OUT3L_VOL_MASK
- ARIZONA_OUT3L_VOL_SHIFT
- ARIZONA_OUT3L_VOL_WIDTH
- ARIZONA_OUT3RMIX_INPUT_1_SOURCE
- ARIZONA_OUT3RMIX_INPUT_1_VOLUME
- ARIZONA_OUT3RMIX_INPUT_2_SOURCE
- ARIZONA_OUT3RMIX_INPUT_2_VOLUME
- ARIZONA_OUT3RMIX_INPUT_3_SOURCE
- ARIZONA_OUT3RMIX_INPUT_3_VOLUME
- ARIZONA_OUT3RMIX_INPUT_4_SOURCE
- ARIZONA_OUT3RMIX_INPUT_4_VOLUME
- ARIZONA_OUT3R_ANC_SRC_MASK
- ARIZONA_OUT3R_ANC_SRC_SHIFT
- ARIZONA_OUT3R_ANC_SRC_WIDTH
- ARIZONA_OUT3R_ENA
- ARIZONA_OUT3R_ENA_MASK
- ARIZONA_OUT3R_ENA_SHIFT
- ARIZONA_OUT3R_ENA_WIDTH
- ARIZONA_OUT3R_MUTE
- ARIZONA_OUT3R_MUTE_MASK
- ARIZONA_OUT3R_MUTE_SHIFT
- ARIZONA_OUT3R_MUTE_WIDTH
- ARIZONA_OUT3R_PGA_VOL_MASK
- ARIZONA_OUT3R_PGA_VOL_SHIFT
- ARIZONA_OUT3R_PGA_VOL_WIDTH
- ARIZONA_OUT3R_VOL_LIM_MASK
- ARIZONA_OUT3R_VOL_LIM_SHIFT
- ARIZONA_OUT3R_VOL_LIM_WIDTH
- ARIZONA_OUT3R_VOL_MASK
- ARIZONA_OUT3R_VOL_SHIFT
- ARIZONA_OUT3R_VOL_WIDTH
- ARIZONA_OUT3_LP_MODE
- ARIZONA_OUT3_LP_MODE_MASK
- ARIZONA_OUT3_LP_MODE_SHIFT
- ARIZONA_OUT3_LP_MODE_WIDTH
- ARIZONA_OUT3_MONO
- ARIZONA_OUT3_MONO_MASK
- ARIZONA_OUT3_MONO_SHIFT
- ARIZONA_OUT3_MONO_WIDTH
- ARIZONA_OUT3_NGATE_SRC_MASK
- ARIZONA_OUT3_NGATE_SRC_SHIFT
- ARIZONA_OUT3_NGATE_SRC_WIDTH
- ARIZONA_OUT3_OSR
- ARIZONA_OUT3_OSR_MASK
- ARIZONA_OUT3_OSR_SHIFT
- ARIZONA_OUT3_OSR_WIDTH
- ARIZONA_OUT4LMIX_INPUT_1_SOURCE
- ARIZONA_OUT4LMIX_INPUT_1_VOLUME
- ARIZONA_OUT4LMIX_INPUT_2_SOURCE
- ARIZONA_OUT4LMIX_INPUT_2_VOLUME
- ARIZONA_OUT4LMIX_INPUT_3_SOURCE
- ARIZONA_OUT4LMIX_INPUT_3_VOLUME
- ARIZONA_OUT4LMIX_INPUT_4_SOURCE
- ARIZONA_OUT4LMIX_INPUT_4_VOLUME
- ARIZONA_OUT4L_ANC_SRC_MASK
- ARIZONA_OUT4L_ANC_SRC_SHIFT
- ARIZONA_OUT4L_ANC_SRC_WIDTH
- ARIZONA_OUT4L_ENA
- ARIZONA_OUT4L_ENA_MASK
- ARIZONA_OUT4L_ENA_SHIFT
- ARIZONA_OUT4L_ENA_STS
- ARIZONA_OUT4L_ENA_STS_MASK
- ARIZONA_OUT4L_ENA_STS_SHIFT
- ARIZONA_OUT4L_ENA_STS_WIDTH
- ARIZONA_OUT4L_ENA_WIDTH
- ARIZONA_OUT4L_MUTE
- ARIZONA_OUT4L_MUTE_MASK
- ARIZONA_OUT4L_MUTE_SHIFT
- ARIZONA_OUT4L_MUTE_WIDTH
- ARIZONA_OUT4L_NGATE_SRC_MASK
- ARIZONA_OUT4L_NGATE_SRC_SHIFT
- ARIZONA_OUT4L_NGATE_SRC_WIDTH
- ARIZONA_OUT4L_VOL_LIM_MASK
- ARIZONA_OUT4L_VOL_LIM_SHIFT
- ARIZONA_OUT4L_VOL_LIM_WIDTH
- ARIZONA_OUT4L_VOL_MASK
- ARIZONA_OUT4L_VOL_SHIFT
- ARIZONA_OUT4L_VOL_WIDTH
- ARIZONA_OUT4RMIX_INPUT_1_SOURCE
- ARIZONA_OUT4RMIX_INPUT_1_VOLUME
- ARIZONA_OUT4RMIX_INPUT_2_SOURCE
- ARIZONA_OUT4RMIX_INPUT_2_VOLUME
- ARIZONA_OUT4RMIX_INPUT_3_SOURCE
- ARIZONA_OUT4RMIX_INPUT_3_VOLUME
- ARIZONA_OUT4RMIX_INPUT_4_SOURCE
- ARIZONA_OUT4RMIX_INPUT_4_VOLUME
- ARIZONA_OUT4R_ANC_SRC_MASK
- ARIZONA_OUT4R_ANC_SRC_SHIFT
- ARIZONA_OUT4R_ANC_SRC_WIDTH
- ARIZONA_OUT4R_ENA
- ARIZONA_OUT4R_ENA_MASK
- ARIZONA_OUT4R_ENA_SHIFT
- ARIZONA_OUT4R_ENA_STS
- ARIZONA_OUT4R_ENA_STS_MASK
- ARIZONA_OUT4R_ENA_STS_SHIFT
- ARIZONA_OUT4R_ENA_STS_WIDTH
- ARIZONA_OUT4R_ENA_WIDTH
- ARIZONA_OUT4R_MUTE
- ARIZONA_OUT4R_MUTE_MASK
- ARIZONA_OUT4R_MUTE_SHIFT
- ARIZONA_OUT4R_MUTE_WIDTH
- ARIZONA_OUT4R_NGATE_SRC_MASK
- ARIZONA_OUT4R_NGATE_SRC_SHIFT
- ARIZONA_OUT4R_NGATE_SRC_WIDTH
- ARIZONA_OUT4R_VOL_LIM_MASK
- ARIZONA_OUT4R_VOL_LIM_SHIFT
- ARIZONA_OUT4R_VOL_LIM_WIDTH
- ARIZONA_OUT4R_VOL_MASK
- ARIZONA_OUT4R_VOL_SHIFT
- ARIZONA_OUT4R_VOL_WIDTH
- ARIZONA_OUT4_OSR
- ARIZONA_OUT4_OSR_MASK
- ARIZONA_OUT4_OSR_SHIFT
- ARIZONA_OUT4_OSR_WIDTH
- ARIZONA_OUT5LMIX_INPUT_1_SOURCE
- ARIZONA_OUT5LMIX_INPUT_1_VOLUME
- ARIZONA_OUT5LMIX_INPUT_2_SOURCE
- ARIZONA_OUT5LMIX_INPUT_2_VOLUME
- ARIZONA_OUT5LMIX_INPUT_3_SOURCE
- ARIZONA_OUT5LMIX_INPUT_3_VOLUME
- ARIZONA_OUT5LMIX_INPUT_4_SOURCE
- ARIZONA_OUT5LMIX_INPUT_4_VOLUME
- ARIZONA_OUT5L_ANC_SRC_MASK
- ARIZONA_OUT5L_ANC_SRC_SHIFT
- ARIZONA_OUT5L_ANC_SRC_WIDTH
- ARIZONA_OUT5L_ENA
- ARIZONA_OUT5L_ENA_MASK
- ARIZONA_OUT5L_ENA_SHIFT
- ARIZONA_OUT5L_ENA_STS
- ARIZONA_OUT5L_ENA_STS_MASK
- ARIZONA_OUT5L_ENA_STS_SHIFT
- ARIZONA_OUT5L_ENA_STS_WIDTH
- ARIZONA_OUT5L_ENA_WIDTH
- ARIZONA_OUT5L_MUTE
- ARIZONA_OUT5L_MUTE_MASK
- ARIZONA_OUT5L_MUTE_SHIFT
- ARIZONA_OUT5L_MUTE_WIDTH
- ARIZONA_OUT5L_NGATE_SRC_MASK
- ARIZONA_OUT5L_NGATE_SRC_SHIFT
- ARIZONA_OUT5L_NGATE_SRC_WIDTH
- ARIZONA_OUT5L_VOL_LIM_MASK
- ARIZONA_OUT5L_VOL_LIM_SHIFT
- ARIZONA_OUT5L_VOL_LIM_WIDTH
- ARIZONA_OUT5L_VOL_MASK
- ARIZONA_OUT5L_VOL_SHIFT
- ARIZONA_OUT5L_VOL_WIDTH
- ARIZONA_OUT5RMIX_INPUT_1_SOURCE
- ARIZONA_OUT5RMIX_INPUT_1_VOLUME
- ARIZONA_OUT5RMIX_INPUT_2_SOURCE
- ARIZONA_OUT5RMIX_INPUT_2_VOLUME
- ARIZONA_OUT5RMIX_INPUT_3_SOURCE
- ARIZONA_OUT5RMIX_INPUT_3_VOLUME
- ARIZONA_OUT5RMIX_INPUT_4_SOURCE
- ARIZONA_OUT5RMIX_INPUT_4_VOLUME
- ARIZONA_OUT5R_ANC_SRC_MASK
- ARIZONA_OUT5R_ANC_SRC_SHIFT
- ARIZONA_OUT5R_ANC_SRC_WIDTH
- ARIZONA_OUT5R_ENA
- ARIZONA_OUT5R_ENA_MASK
- ARIZONA_OUT5R_ENA_SHIFT
- ARIZONA_OUT5R_ENA_STS
- ARIZONA_OUT5R_ENA_STS_MASK
- ARIZONA_OUT5R_ENA_STS_SHIFT
- ARIZONA_OUT5R_ENA_STS_WIDTH
- ARIZONA_OUT5R_ENA_WIDTH
- ARIZONA_OUT5R_MUTE
- ARIZONA_OUT5R_MUTE_MASK
- ARIZONA_OUT5R_MUTE_SHIFT
- ARIZONA_OUT5R_MUTE_WIDTH
- ARIZONA_OUT5R_NGATE_SRC_MASK
- ARIZONA_OUT5R_NGATE_SRC_SHIFT
- ARIZONA_OUT5R_NGATE_SRC_WIDTH
- ARIZONA_OUT5R_VOL_LIM_MASK
- ARIZONA_OUT5R_VOL_LIM_SHIFT
- ARIZONA_OUT5R_VOL_LIM_WIDTH
- ARIZONA_OUT5R_VOL_MASK
- ARIZONA_OUT5R_VOL_SHIFT
- ARIZONA_OUT5R_VOL_WIDTH
- ARIZONA_OUT5_OSR
- ARIZONA_OUT5_OSR_MASK
- ARIZONA_OUT5_OSR_SHIFT
- ARIZONA_OUT5_OSR_WIDTH
- ARIZONA_OUT6LMIX_INPUT_1_SOURCE
- ARIZONA_OUT6LMIX_INPUT_1_VOLUME
- ARIZONA_OUT6LMIX_INPUT_2_SOURCE
- ARIZONA_OUT6LMIX_INPUT_2_VOLUME
- ARIZONA_OUT6LMIX_INPUT_3_SOURCE
- ARIZONA_OUT6LMIX_INPUT_3_VOLUME
- ARIZONA_OUT6LMIX_INPUT_4_SOURCE
- ARIZONA_OUT6LMIX_INPUT_4_VOLUME
- ARIZONA_OUT6L_ANC_SRC_MASK
- ARIZONA_OUT6L_ANC_SRC_SHIFT
- ARIZONA_OUT6L_ANC_SRC_WIDTH
- ARIZONA_OUT6L_ENA
- ARIZONA_OUT6L_ENA_MASK
- ARIZONA_OUT6L_ENA_SHIFT
- ARIZONA_OUT6L_ENA_STS
- ARIZONA_OUT6L_ENA_STS_MASK
- ARIZONA_OUT6L_ENA_STS_SHIFT
- ARIZONA_OUT6L_ENA_STS_WIDTH
- ARIZONA_OUT6L_ENA_WIDTH
- ARIZONA_OUT6L_MUTE
- ARIZONA_OUT6L_MUTE_MASK
- ARIZONA_OUT6L_MUTE_SHIFT
- ARIZONA_OUT6L_MUTE_WIDTH
- ARIZONA_OUT6L_NGATE_SRC_MASK
- ARIZONA_OUT6L_NGATE_SRC_SHIFT
- ARIZONA_OUT6L_NGATE_SRC_WIDTH
- ARIZONA_OUT6L_VOL_LIM_MASK
- ARIZONA_OUT6L_VOL_LIM_SHIFT
- ARIZONA_OUT6L_VOL_LIM_WIDTH
- ARIZONA_OUT6L_VOL_MASK
- ARIZONA_OUT6L_VOL_SHIFT
- ARIZONA_OUT6L_VOL_WIDTH
- ARIZONA_OUT6RMIX_INPUT_1_SOURCE
- ARIZONA_OUT6RMIX_INPUT_1_VOLUME
- ARIZONA_OUT6RMIX_INPUT_2_SOURCE
- ARIZONA_OUT6RMIX_INPUT_2_VOLUME
- ARIZONA_OUT6RMIX_INPUT_3_SOURCE
- ARIZONA_OUT6RMIX_INPUT_3_VOLUME
- ARIZONA_OUT6RMIX_INPUT_4_SOURCE
- ARIZONA_OUT6RMIX_INPUT_4_VOLUME
- ARIZONA_OUT6R_ANC_SRC_MASK
- ARIZONA_OUT6R_ANC_SRC_SHIFT
- ARIZONA_OUT6R_ANC_SRC_WIDTH
- ARIZONA_OUT6R_ENA
- ARIZONA_OUT6R_ENA_MASK
- ARIZONA_OUT6R_ENA_SHIFT
- ARIZONA_OUT6R_ENA_STS
- ARIZONA_OUT6R_ENA_STS_MASK
- ARIZONA_OUT6R_ENA_STS_SHIFT
- ARIZONA_OUT6R_ENA_STS_WIDTH
- ARIZONA_OUT6R_ENA_WIDTH
- ARIZONA_OUT6R_MUTE
- ARIZONA_OUT6R_MUTE_MASK
- ARIZONA_OUT6R_MUTE_SHIFT
- ARIZONA_OUT6R_MUTE_WIDTH
- ARIZONA_OUT6R_NGATE_SRC_MASK
- ARIZONA_OUT6R_NGATE_SRC_SHIFT
- ARIZONA_OUT6R_NGATE_SRC_WIDTH
- ARIZONA_OUT6R_VOL_LIM_MASK
- ARIZONA_OUT6R_VOL_LIM_SHIFT
- ARIZONA_OUT6R_VOL_LIM_WIDTH
- ARIZONA_OUT6R_VOL_MASK
- ARIZONA_OUT6R_VOL_SHIFT
- ARIZONA_OUT6R_VOL_WIDTH
- ARIZONA_OUT6_OSR
- ARIZONA_OUT6_OSR_MASK
- ARIZONA_OUT6_OSR_SHIFT
- ARIZONA_OUT6_OSR_WIDTH
- ARIZONA_OUTPUT_ASYNC_CLOCK
- ARIZONA_OUTPUT_ENABLES_1
- ARIZONA_OUTPUT_PATH_CONFIG_1L
- ARIZONA_OUTPUT_PATH_CONFIG_1R
- ARIZONA_OUTPUT_PATH_CONFIG_2L
- ARIZONA_OUTPUT_PATH_CONFIG_2R
- ARIZONA_OUTPUT_PATH_CONFIG_3L
- ARIZONA_OUTPUT_PATH_CONFIG_3R
- ARIZONA_OUTPUT_PATH_CONFIG_4L
- ARIZONA_OUTPUT_PATH_CONFIG_4R
- ARIZONA_OUTPUT_PATH_CONFIG_5L
- ARIZONA_OUTPUT_PATH_CONFIG_5R
- ARIZONA_OUTPUT_PATH_CONFIG_6L
- ARIZONA_OUTPUT_PATH_CONFIG_6R
- ARIZONA_OUTPUT_RATE_1
- ARIZONA_OUTPUT_STATUS_1
- ARIZONA_OUTPUT_SYSTEM_CLOCK
- ARIZONA_OUTPUT_VOLUME_RAMP
- ARIZONA_OUT_COMP_COEFF_1
- ARIZONA_OUT_COMP_COEFF_1_MASK
- ARIZONA_OUT_COMP_COEFF_1_SHIFT
- ARIZONA_OUT_COMP_COEFF_1_WIDTH
- ARIZONA_OUT_COMP_COEFF_MASK
- ARIZONA_OUT_COMP_COEFF_SEL
- ARIZONA_OUT_COMP_COEFF_SEL_MASK
- ARIZONA_OUT_COMP_COEFF_SEL_SHIFT
- ARIZONA_OUT_COMP_COEFF_SEL_WIDTH
- ARIZONA_OUT_COMP_COEFF_SHIFT
- ARIZONA_OUT_COMP_COEFF_WIDTH
- ARIZONA_OUT_RATE_MASK
- ARIZONA_OUT_RATE_SHIFT
- ARIZONA_OUT_RATE_WIDTH
- ARIZONA_OUT_VD_RAMP_MASK
- ARIZONA_OUT_VD_RAMP_SHIFT
- ARIZONA_OUT_VD_RAMP_WIDTH
- ARIZONA_OUT_VI_RAMP_MASK
- ARIZONA_OUT_VI_RAMP_SHIFT
- ARIZONA_OUT_VI_RAMP_WIDTH
- ARIZONA_OUT_VOLUME_4L
- ARIZONA_OUT_VOLUME_4R
- ARIZONA_OUT_VU
- ARIZONA_OUT_VU_MASK
- ARIZONA_OUT_VU_SHIFT
- ARIZONA_OUT_VU_WIDTH
- ARIZONA_OVERCLOCKED_EINT1
- ARIZONA_OVERCLOCKED_EINT1_MASK
- ARIZONA_OVERCLOCKED_EINT1_SHIFT
- ARIZONA_OVERCLOCKED_EINT1_WIDTH
- ARIZONA_OVERCLOCKED_EINT2
- ARIZONA_OVERCLOCKED_EINT2_MASK
- ARIZONA_OVERCLOCKED_EINT2_SHIFT
- ARIZONA_OVERCLOCKED_EINT2_WIDTH
- ARIZONA_OVERCLOCKED_STS
- ARIZONA_OVERCLOCKED_STS_MASK
- ARIZONA_OVERCLOCKED_STS_SHIFT
- ARIZONA_OVERCLOCKED_STS_WIDTH
- ARIZONA_PAD_CTRL_OVERCLOCKED_STS
- ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK
- ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT
- ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH
- ARIZONA_PDM_SPK1_CTRL_1
- ARIZONA_PDM_SPK1_CTRL_2
- ARIZONA_PDM_SPK2_CTRL_1
- ARIZONA_PDM_SPK2_CTRL_2
- ARIZONA_PHASE1_DURATION_MASK
- ARIZONA_PHASE1_DURATION_SHIFT
- ARIZONA_PHASE1_DURATION_WIDTH
- ARIZONA_PHASE1_INTENSITY_MASK
- ARIZONA_PHASE1_INTENSITY_SHIFT
- ARIZONA_PHASE1_INTENSITY_WIDTH
- ARIZONA_PHASE2_DURATION_MASK
- ARIZONA_PHASE2_DURATION_SHIFT
- ARIZONA_PHASE2_DURATION_WIDTH
- ARIZONA_PHASE2_INTENSITY_MASK
- ARIZONA_PHASE2_INTENSITY_SHIFT
- ARIZONA_PHASE2_INTENSITY_WIDTH
- ARIZONA_PHASE3_DURATION_MASK
- ARIZONA_PHASE3_DURATION_SHIFT
- ARIZONA_PHASE3_DURATION_WIDTH
- ARIZONA_PHASE3_INTENSITY_MASK
- ARIZONA_PHASE3_INTENSITY_SHIFT
- ARIZONA_PHASE3_INTENSITY_WIDTH
- ARIZONA_PWM1MIX_INPUT_1_SOURCE
- ARIZONA_PWM1MIX_INPUT_1_VOLUME
- ARIZONA_PWM1MIX_INPUT_2_SOURCE
- ARIZONA_PWM1MIX_INPUT_2_VOLUME
- ARIZONA_PWM1MIX_INPUT_3_SOURCE
- ARIZONA_PWM1MIX_INPUT_3_VOLUME
- ARIZONA_PWM1MIX_INPUT_4_SOURCE
- ARIZONA_PWM1MIX_INPUT_4_VOLUME
- ARIZONA_PWM1_ENA
- ARIZONA_PWM1_ENA_MASK
- ARIZONA_PWM1_ENA_SHIFT
- ARIZONA_PWM1_ENA_WIDTH
- ARIZONA_PWM1_LVL_MASK
- ARIZONA_PWM1_LVL_SHIFT
- ARIZONA_PWM1_LVL_WIDTH
- ARIZONA_PWM1_OVD
- ARIZONA_PWM1_OVD_MASK
- ARIZONA_PWM1_OVD_SHIFT
- ARIZONA_PWM1_OVD_WIDTH
- ARIZONA_PWM2MIX_INPUT_1_SOURCE
- ARIZONA_PWM2MIX_INPUT_1_VOLUME
- ARIZONA_PWM2MIX_INPUT_2_SOURCE
- ARIZONA_PWM2MIX_INPUT_2_VOLUME
- ARIZONA_PWM2MIX_INPUT_3_SOURCE
- ARIZONA_PWM2MIX_INPUT_3_VOLUME
- ARIZONA_PWM2MIX_INPUT_4_SOURCE
- ARIZONA_PWM2MIX_INPUT_4_VOLUME
- ARIZONA_PWM2_ENA
- ARIZONA_PWM2_ENA_MASK
- ARIZONA_PWM2_ENA_SHIFT
- ARIZONA_PWM2_ENA_WIDTH
- ARIZONA_PWM2_LVL_MASK
- ARIZONA_PWM2_LVL_SHIFT
- ARIZONA_PWM2_LVL_WIDTH
- ARIZONA_PWM2_OVD
- ARIZONA_PWM2_OVD_MASK
- ARIZONA_PWM2_OVD_SHIFT
- ARIZONA_PWM2_OVD_WIDTH
- ARIZONA_PWM_CLK_SEL_MASK
- ARIZONA_PWM_CLK_SEL_SHIFT
- ARIZONA_PWM_CLK_SEL_WIDTH
- ARIZONA_PWM_DRIVE_1
- ARIZONA_PWM_DRIVE_2
- ARIZONA_PWM_DRIVE_3
- ARIZONA_PWM_OVERCLOCKED_STS
- ARIZONA_PWM_OVERCLOCKED_STS_MASK
- ARIZONA_PWM_OVERCLOCKED_STS_SHIFT
- ARIZONA_PWM_OVERCLOCKED_STS_WIDTH
- ARIZONA_PWM_RATE_MASK
- ARIZONA_PWM_RATE_SHIFT
- ARIZONA_PWM_RATE_WIDTH
- ARIZONA_RATE_ENUM_SIZE
- ARIZONA_RATE_ESTIMATOR_1
- ARIZONA_RATE_ESTIMATOR_2
- ARIZONA_RATE_ESTIMATOR_3
- ARIZONA_RATE_ESTIMATOR_4
- ARIZONA_RATE_ESTIMATOR_5
- ARIZONA_RATE_EST_ENA
- ARIZONA_RATE_EST_ENA_MASK
- ARIZONA_RATE_EST_ENA_SHIFT
- ARIZONA_RATE_EST_ENA_WIDTH
- ARIZONA_RATE_MASK
- ARIZONA_RAW_OUTPUT_STATUS_1
- ARIZONA_REG_POLL_DELAY_US
- ARIZONA_RMV_SHRT_HP1L
- ARIZONA_RMV_SHRT_HP1L_MASK
- ARIZONA_RMV_SHRT_HP1L_SHIFT
- ARIZONA_RMV_SHRT_HP1L_WIDTH
- ARIZONA_RMV_SHRT_HP1R
- ARIZONA_RMV_SHRT_HP1R_MASK
- ARIZONA_RMV_SHRT_HP1R_SHIFT
- ARIZONA_RMV_SHRT_HP1R_WIDTH
- ARIZONA_RSTB_PU
- ARIZONA_RSTB_PU_MASK
- ARIZONA_RSTB_PU_SHIFT
- ARIZONA_RSTB_PU_WIDTH
- ARIZONA_SAMPLE_RATE_1
- ARIZONA_SAMPLE_RATE_1_MASK
- ARIZONA_SAMPLE_RATE_1_SHIFT
- ARIZONA_SAMPLE_RATE_1_STATUS
- ARIZONA_SAMPLE_RATE_1_STS_MASK
- ARIZONA_SAMPLE_RATE_1_STS_SHIFT
- ARIZONA_SAMPLE_RATE_1_STS_WIDTH
- ARIZONA_SAMPLE_RATE_1_WIDTH
- ARIZONA_SAMPLE_RATE_2
- ARIZONA_SAMPLE_RATE_2_MASK
- ARIZONA_SAMPLE_RATE_2_SHIFT
- ARIZONA_SAMPLE_RATE_2_STATUS
- ARIZONA_SAMPLE_RATE_2_STS_MASK
- ARIZONA_SAMPLE_RATE_2_STS_SHIFT
- ARIZONA_SAMPLE_RATE_2_STS_WIDTH
- ARIZONA_SAMPLE_RATE_2_WIDTH
- ARIZONA_SAMPLE_RATE_3
- ARIZONA_SAMPLE_RATE_3_MASK
- ARIZONA_SAMPLE_RATE_3_SHIFT
- ARIZONA_SAMPLE_RATE_3_STATUS
- ARIZONA_SAMPLE_RATE_3_STS_MASK
- ARIZONA_SAMPLE_RATE_3_STS_SHIFT
- ARIZONA_SAMPLE_RATE_3_STS_WIDTH
- ARIZONA_SAMPLE_RATE_3_WIDTH
- ARIZONA_SAMPLE_RATE_DETECT_A_MASK
- ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT
- ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH
- ARIZONA_SAMPLE_RATE_DETECT_B_MASK
- ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT
- ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH
- ARIZONA_SAMPLE_RATE_DETECT_C_MASK
- ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT
- ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH
- ARIZONA_SAMPLE_RATE_DETECT_D_MASK
- ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT
- ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH
- ARIZONA_SAMPLE_RATE_ENUM_SIZE
- ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1
- ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2
- ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3
- ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4
- ARIZONA_SEQUENCE_CONTROL
- ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS
- ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK
- ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_SLIMBUS_FRAMER_REF_GEAR
- ARIZONA_SLIMBUS_RATES_1
- ARIZONA_SLIMBUS_RATES_2
- ARIZONA_SLIMBUS_RATES_3
- ARIZONA_SLIMBUS_RATES_4
- ARIZONA_SLIMBUS_RATES_5
- ARIZONA_SLIMBUS_RATES_6
- ARIZONA_SLIMBUS_RATES_7
- ARIZONA_SLIMBUS_RATES_8
- ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE
- ARIZONA_SLIMBUS_RX_PORT_STATUS
- ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS
- ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK
- ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT
- ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH
- ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS
- ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK
- ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT
- ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH
- ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE
- ARIZONA_SLIMBUS_TX_PORT_STATUS
- ARIZONA_SLIMCLK_SRC
- ARIZONA_SLIMCLK_SRC_MASK
- ARIZONA_SLIMCLK_SRC_SHIFT
- ARIZONA_SLIMCLK_SRC_WIDTH
- ARIZONA_SLIMRX1_ENA
- ARIZONA_SLIMRX1_ENA_MASK
- ARIZONA_SLIMRX1_ENA_SHIFT
- ARIZONA_SLIMRX1_ENA_WIDTH
- ARIZONA_SLIMRX1_PORT_STS
- ARIZONA_SLIMRX1_PORT_STS_MASK
- ARIZONA_SLIMRX1_PORT_STS_SHIFT
- ARIZONA_SLIMRX1_PORT_STS_WIDTH
- ARIZONA_SLIMRX1_RATE_MASK
- ARIZONA_SLIMRX1_RATE_SHIFT
- ARIZONA_SLIMRX1_RATE_WIDTH
- ARIZONA_SLIMRX2_ENA
- ARIZONA_SLIMRX2_ENA_MASK
- ARIZONA_SLIMRX2_ENA_SHIFT
- ARIZONA_SLIMRX2_ENA_WIDTH
- ARIZONA_SLIMRX2_PORT_STS
- ARIZONA_SLIMRX2_PORT_STS_MASK
- ARIZONA_SLIMRX2_PORT_STS_SHIFT
- ARIZONA_SLIMRX2_PORT_STS_WIDTH
- ARIZONA_SLIMRX2_RATE_MASK
- ARIZONA_SLIMRX2_RATE_SHIFT
- ARIZONA_SLIMRX2_RATE_WIDTH
- ARIZONA_SLIMRX3_ENA
- ARIZONA_SLIMRX3_ENA_MASK
- ARIZONA_SLIMRX3_ENA_SHIFT
- ARIZONA_SLIMRX3_ENA_WIDTH
- ARIZONA_SLIMRX3_PORT_STS
- ARIZONA_SLIMRX3_PORT_STS_MASK
- ARIZONA_SLIMRX3_PORT_STS_SHIFT
- ARIZONA_SLIMRX3_PORT_STS_WIDTH
- ARIZONA_SLIMRX3_RATE_MASK
- ARIZONA_SLIMRX3_RATE_SHIFT
- ARIZONA_SLIMRX3_RATE_WIDTH
- ARIZONA_SLIMRX4_ENA
- ARIZONA_SLIMRX4_ENA_MASK
- ARIZONA_SLIMRX4_ENA_SHIFT
- ARIZONA_SLIMRX4_ENA_WIDTH
- ARIZONA_SLIMRX4_PORT_STS
- ARIZONA_SLIMRX4_PORT_STS_MASK
- ARIZONA_SLIMRX4_PORT_STS_SHIFT
- ARIZONA_SLIMRX4_PORT_STS_WIDTH
- ARIZONA_SLIMRX4_RATE_MASK
- ARIZONA_SLIMRX4_RATE_SHIFT
- ARIZONA_SLIMRX4_RATE_WIDTH
- ARIZONA_SLIMRX5_ENA
- ARIZONA_SLIMRX5_ENA_MASK
- ARIZONA_SLIMRX5_ENA_SHIFT
- ARIZONA_SLIMRX5_ENA_WIDTH
- ARIZONA_SLIMRX5_PORT_STS
- ARIZONA_SLIMRX5_PORT_STS_MASK
- ARIZONA_SLIMRX5_PORT_STS_SHIFT
- ARIZONA_SLIMRX5_PORT_STS_WIDTH
- ARIZONA_SLIMRX5_RATE_MASK
- ARIZONA_SLIMRX5_RATE_SHIFT
- ARIZONA_SLIMRX5_RATE_WIDTH
- ARIZONA_SLIMRX6_ENA
- ARIZONA_SLIMRX6_ENA_MASK
- ARIZONA_SLIMRX6_ENA_SHIFT
- ARIZONA_SLIMRX6_ENA_WIDTH
- ARIZONA_SLIMRX6_PORT_STS
- ARIZONA_SLIMRX6_PORT_STS_MASK
- ARIZONA_SLIMRX6_PORT_STS_SHIFT
- ARIZONA_SLIMRX6_PORT_STS_WIDTH
- ARIZONA_SLIMRX6_RATE_MASK
- ARIZONA_SLIMRX6_RATE_SHIFT
- ARIZONA_SLIMRX6_RATE_WIDTH
- ARIZONA_SLIMRX7_ENA
- ARIZONA_SLIMRX7_ENA_MASK
- ARIZONA_SLIMRX7_ENA_SHIFT
- ARIZONA_SLIMRX7_ENA_WIDTH
- ARIZONA_SLIMRX7_PORT_STS
- ARIZONA_SLIMRX7_PORT_STS_MASK
- ARIZONA_SLIMRX7_PORT_STS_SHIFT
- ARIZONA_SLIMRX7_PORT_STS_WIDTH
- ARIZONA_SLIMRX7_RATE_MASK
- ARIZONA_SLIMRX7_RATE_SHIFT
- ARIZONA_SLIMRX7_RATE_WIDTH
- ARIZONA_SLIMRX8_ENA
- ARIZONA_SLIMRX8_ENA_MASK
- ARIZONA_SLIMRX8_ENA_SHIFT
- ARIZONA_SLIMRX8_ENA_WIDTH
- ARIZONA_SLIMRX8_PORT_STS
- ARIZONA_SLIMRX8_PORT_STS_MASK
- ARIZONA_SLIMRX8_PORT_STS_SHIFT
- ARIZONA_SLIMRX8_PORT_STS_WIDTH
- ARIZONA_SLIMRX8_RATE_MASK
- ARIZONA_SLIMRX8_RATE_SHIFT
- ARIZONA_SLIMRX8_RATE_WIDTH
- ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX1_ENA
- ARIZONA_SLIMTX1_ENA_MASK
- ARIZONA_SLIMTX1_ENA_SHIFT
- ARIZONA_SLIMTX1_ENA_WIDTH
- ARIZONA_SLIMTX1_PORT_STS
- ARIZONA_SLIMTX1_PORT_STS_MASK
- ARIZONA_SLIMTX1_PORT_STS_SHIFT
- ARIZONA_SLIMTX1_PORT_STS_WIDTH
- ARIZONA_SLIMTX1_RATE_MASK
- ARIZONA_SLIMTX1_RATE_SHIFT
- ARIZONA_SLIMTX1_RATE_WIDTH
- ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX2_ENA
- ARIZONA_SLIMTX2_ENA_MASK
- ARIZONA_SLIMTX2_ENA_SHIFT
- ARIZONA_SLIMTX2_ENA_WIDTH
- ARIZONA_SLIMTX2_PORT_STS
- ARIZONA_SLIMTX2_PORT_STS_MASK
- ARIZONA_SLIMTX2_PORT_STS_SHIFT
- ARIZONA_SLIMTX2_PORT_STS_WIDTH
- ARIZONA_SLIMTX2_RATE_MASK
- ARIZONA_SLIMTX2_RATE_SHIFT
- ARIZONA_SLIMTX2_RATE_WIDTH
- ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX3_ENA
- ARIZONA_SLIMTX3_ENA_MASK
- ARIZONA_SLIMTX3_ENA_SHIFT
- ARIZONA_SLIMTX3_ENA_WIDTH
- ARIZONA_SLIMTX3_PORT_STS
- ARIZONA_SLIMTX3_PORT_STS_MASK
- ARIZONA_SLIMTX3_PORT_STS_SHIFT
- ARIZONA_SLIMTX3_PORT_STS_WIDTH
- ARIZONA_SLIMTX3_RATE_MASK
- ARIZONA_SLIMTX3_RATE_SHIFT
- ARIZONA_SLIMTX3_RATE_WIDTH
- ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX4_ENA
- ARIZONA_SLIMTX4_ENA_MASK
- ARIZONA_SLIMTX4_ENA_SHIFT
- ARIZONA_SLIMTX4_ENA_WIDTH
- ARIZONA_SLIMTX4_PORT_STS
- ARIZONA_SLIMTX4_PORT_STS_MASK
- ARIZONA_SLIMTX4_PORT_STS_SHIFT
- ARIZONA_SLIMTX4_PORT_STS_WIDTH
- ARIZONA_SLIMTX4_RATE_MASK
- ARIZONA_SLIMTX4_RATE_SHIFT
- ARIZONA_SLIMTX4_RATE_WIDTH
- ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX5_ENA
- ARIZONA_SLIMTX5_ENA_MASK
- ARIZONA_SLIMTX5_ENA_SHIFT
- ARIZONA_SLIMTX5_ENA_WIDTH
- ARIZONA_SLIMTX5_PORT_STS
- ARIZONA_SLIMTX5_PORT_STS_MASK
- ARIZONA_SLIMTX5_PORT_STS_SHIFT
- ARIZONA_SLIMTX5_PORT_STS_WIDTH
- ARIZONA_SLIMTX5_RATE_MASK
- ARIZONA_SLIMTX5_RATE_SHIFT
- ARIZONA_SLIMTX5_RATE_WIDTH
- ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX6_ENA
- ARIZONA_SLIMTX6_ENA_MASK
- ARIZONA_SLIMTX6_ENA_SHIFT
- ARIZONA_SLIMTX6_ENA_WIDTH
- ARIZONA_SLIMTX6_PORT_STS
- ARIZONA_SLIMTX6_PORT_STS_MASK
- ARIZONA_SLIMTX6_PORT_STS_SHIFT
- ARIZONA_SLIMTX6_PORT_STS_WIDTH
- ARIZONA_SLIMTX6_RATE_MASK
- ARIZONA_SLIMTX6_RATE_SHIFT
- ARIZONA_SLIMTX6_RATE_WIDTH
- ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX7_ENA
- ARIZONA_SLIMTX7_ENA_MASK
- ARIZONA_SLIMTX7_ENA_SHIFT
- ARIZONA_SLIMTX7_ENA_WIDTH
- ARIZONA_SLIMTX7_PORT_STS
- ARIZONA_SLIMTX7_PORT_STS_MASK
- ARIZONA_SLIMTX7_PORT_STS_SHIFT
- ARIZONA_SLIMTX7_PORT_STS_WIDTH
- ARIZONA_SLIMTX7_RATE_MASK
- ARIZONA_SLIMTX7_RATE_SHIFT
- ARIZONA_SLIMTX7_RATE_WIDTH
- ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE
- ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME
- ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE
- ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME
- ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE
- ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME
- ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE
- ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME
- ARIZONA_SLIMTX8_ENA
- ARIZONA_SLIMTX8_ENA_MASK
- ARIZONA_SLIMTX8_ENA_SHIFT
- ARIZONA_SLIMTX8_ENA_WIDTH
- ARIZONA_SLIMTX8_PORT_STS
- ARIZONA_SLIMTX8_PORT_STS_MASK
- ARIZONA_SLIMTX8_PORT_STS_SHIFT
- ARIZONA_SLIMTX8_PORT_STS_WIDTH
- ARIZONA_SLIMTX8_RATE_MASK
- ARIZONA_SLIMTX8_RATE_SHIFT
- ARIZONA_SLIMTX8_RATE_WIDTH
- ARIZONA_SOFTWARE_RESET
- ARIZONA_SPARE_TRIGGERS
- ARIZONA_SPD1_CATCODE_MASK
- ARIZONA_SPD1_CATCODE_SHIFT
- ARIZONA_SPD1_CATCODE_WIDTH
- ARIZONA_SPD1_CHNUM1_MASK
- ARIZONA_SPD1_CHNUM1_SHIFT
- ARIZONA_SPD1_CHNUM1_WIDTH
- ARIZONA_SPD1_CHNUM2_MASK
- ARIZONA_SPD1_CHNUM2_SHIFT
- ARIZONA_SPD1_CHNUM2_WIDTH
- ARIZONA_SPD1_CHSTMODE_MASK
- ARIZONA_SPD1_CHSTMODE_SHIFT
- ARIZONA_SPD1_CHSTMODE_WIDTH
- ARIZONA_SPD1_CLKACU_MASK
- ARIZONA_SPD1_CLKACU_SHIFT
- ARIZONA_SPD1_CLKACU_WIDTH
- ARIZONA_SPD1_CS31_30_MASK
- ARIZONA_SPD1_CS31_30_SHIFT
- ARIZONA_SPD1_CS31_30_WIDTH
- ARIZONA_SPD1_ENA
- ARIZONA_SPD1_ENA_MASK
- ARIZONA_SPD1_ENA_SHIFT
- ARIZONA_SPD1_ENA_WIDTH
- ARIZONA_SPD1_FREQ_MASK
- ARIZONA_SPD1_FREQ_SHIFT
- ARIZONA_SPD1_FREQ_WIDTH
- ARIZONA_SPD1_MAXWL
- ARIZONA_SPD1_MAXWL_MASK
- ARIZONA_SPD1_MAXWL_SHIFT
- ARIZONA_SPD1_MAXWL_WIDTH
- ARIZONA_SPD1_NOAUDIO
- ARIZONA_SPD1_NOAUDIO_MASK
- ARIZONA_SPD1_NOAUDIO_SHIFT
- ARIZONA_SPD1_NOAUDIO_WIDTH
- ARIZONA_SPD1_NOCOPY
- ARIZONA_SPD1_NOCOPY_MASK
- ARIZONA_SPD1_NOCOPY_SHIFT
- ARIZONA_SPD1_NOCOPY_WIDTH
- ARIZONA_SPD1_ORGSAMP_MASK
- ARIZONA_SPD1_ORGSAMP_SHIFT
- ARIZONA_SPD1_ORGSAMP_WIDTH
- ARIZONA_SPD1_PREEMPH_MASK
- ARIZONA_SPD1_PREEMPH_SHIFT
- ARIZONA_SPD1_PREEMPH_WIDTH
- ARIZONA_SPD1_PRO
- ARIZONA_SPD1_PRO_MASK
- ARIZONA_SPD1_PRO_SHIFT
- ARIZONA_SPD1_PRO_WIDTH
- ARIZONA_SPD1_RATE_MASK
- ARIZONA_SPD1_RATE_SHIFT
- ARIZONA_SPD1_RATE_WIDTH
- ARIZONA_SPD1_SRCNUM_MASK
- ARIZONA_SPD1_SRCNUM_SHIFT
- ARIZONA_SPD1_SRCNUM_WIDTH
- ARIZONA_SPD1_TXWL_MASK
- ARIZONA_SPD1_TXWL_SHIFT
- ARIZONA_SPD1_TXWL_WIDTH
- ARIZONA_SPD1_TX_CHANNEL_STATUS_1
- ARIZONA_SPD1_TX_CHANNEL_STATUS_2
- ARIZONA_SPD1_TX_CHANNEL_STATUS_3
- ARIZONA_SPD1_TX_CONTROL
- ARIZONA_SPD1_VAL1
- ARIZONA_SPD1_VAL1_MASK
- ARIZONA_SPD1_VAL1_SHIFT
- ARIZONA_SPD1_VAL1_WIDTH
- ARIZONA_SPD1_VAL2
- ARIZONA_SPD1_VAL2_MASK
- ARIZONA_SPD1_VAL2_SHIFT
- ARIZONA_SPD1_VAL2_WIDTH
- ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE
- ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME
- ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE
- ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME
- ARIZONA_SPDIF_OVERCLOCKED_STS
- ARIZONA_SPDIF_OVERCLOCKED_STS_MASK
- ARIZONA_SPDIF_OVERCLOCKED_STS_SHIFT
- ARIZONA_SPDIF_OVERCLOCKED_STS_WIDTH
- ARIZONA_SPI_4WIRE
- ARIZONA_SPI_4WIRE_MASK
- ARIZONA_SPI_4WIRE_SHIFT
- ARIZONA_SPI_4WIRE_WIDTH
- ARIZONA_SPI_AUTO_INC_MASK
- ARIZONA_SPI_AUTO_INC_SHIFT
- ARIZONA_SPI_AUTO_INC_WIDTH
- ARIZONA_SPI_BUSY
- ARIZONA_SPI_BUSY_MASK
- ARIZONA_SPI_BUSY_SHIFT
- ARIZONA_SPI_BUSY_WIDTH
- ARIZONA_SPI_CFG
- ARIZONA_SPI_CFG_MASK
- ARIZONA_SPI_CFG_SHIFT
- ARIZONA_SPI_CFG_WIDTH
- ARIZONA_SPK1L_MUTE
- ARIZONA_SPK1L_MUTE_MASK
- ARIZONA_SPK1L_MUTE_SHIFT
- ARIZONA_SPK1L_MUTE_WIDTH
- ARIZONA_SPK1L_SHORT_EINT1
- ARIZONA_SPK1L_SHORT_EINT1_MASK
- ARIZONA_SPK1L_SHORT_EINT1_SHIFT
- ARIZONA_SPK1L_SHORT_EINT1_WIDTH
- ARIZONA_SPK1L_SHORT_EINT2
- ARIZONA_SPK1L_SHORT_EINT2_MASK
- ARIZONA_SPK1L_SHORT_EINT2_SHIFT
- ARIZONA_SPK1L_SHORT_EINT2_WIDTH
- ARIZONA_SPK1L_SHORT_STS
- ARIZONA_SPK1L_SHORT_STS_MASK
- ARIZONA_SPK1L_SHORT_STS_SHIFT
- ARIZONA_SPK1L_SHORT_STS_WIDTH
- ARIZONA_SPK1R_MUTE
- ARIZONA_SPK1R_MUTE_MASK
- ARIZONA_SPK1R_MUTE_SHIFT
- ARIZONA_SPK1R_MUTE_WIDTH
- ARIZONA_SPK1R_SHORT_EINT1
- ARIZONA_SPK1R_SHORT_EINT1_MASK
- ARIZONA_SPK1R_SHORT_EINT1_SHIFT
- ARIZONA_SPK1R_SHORT_EINT1_WIDTH
- ARIZONA_SPK1R_SHORT_EINT2
- ARIZONA_SPK1R_SHORT_EINT2_MASK
- ARIZONA_SPK1R_SHORT_EINT2_SHIFT
- ARIZONA_SPK1R_SHORT_EINT2_WIDTH
- ARIZONA_SPK1R_SHORT_STS
- ARIZONA_SPK1R_SHORT_STS_MASK
- ARIZONA_SPK1R_SHORT_STS_SHIFT
- ARIZONA_SPK1R_SHORT_STS_WIDTH
- ARIZONA_SPK1_FMT
- ARIZONA_SPK1_FMT_MASK
- ARIZONA_SPK1_FMT_SHIFT
- ARIZONA_SPK1_FMT_WIDTH
- ARIZONA_SPK1_MUTE_ENDIAN
- ARIZONA_SPK1_MUTE_ENDIAN_MASK
- ARIZONA_SPK1_MUTE_ENDIAN_SHIFT
- ARIZONA_SPK1_MUTE_ENDIAN_WIDTH
- ARIZONA_SPK1_MUTE_SEQ1_MASK
- ARIZONA_SPK1_MUTE_SEQ1_SHIFT
- ARIZONA_SPK1_MUTE_SEQ1_WIDTH
- ARIZONA_SPK2L_MUTE
- ARIZONA_SPK2L_MUTE_MASK
- ARIZONA_SPK2L_MUTE_SHIFT
- ARIZONA_SPK2L_MUTE_WIDTH
- ARIZONA_SPK2R_MUTE
- ARIZONA_SPK2R_MUTE_MASK
- ARIZONA_SPK2R_MUTE_SHIFT
- ARIZONA_SPK2R_MUTE_WIDTH
- ARIZONA_SPK2_FMT
- ARIZONA_SPK2_FMT_MASK
- ARIZONA_SPK2_FMT_SHIFT
- ARIZONA_SPK2_FMT_WIDTH
- ARIZONA_SPK2_MUTE_ENDIAN
- ARIZONA_SPK2_MUTE_ENDIAN_MASK
- ARIZONA_SPK2_MUTE_ENDIAN_SHIFT
- ARIZONA_SPK2_MUTE_ENDIAN_WIDTH
- ARIZONA_SPK2_MUTE_SEQ_MASK
- ARIZONA_SPK2_MUTE_SEQ_SHIFT
- ARIZONA_SPK2_MUTE_SEQ_WIDTH
- ARIZONA_SPK_CTRL_2
- ARIZONA_SPK_CTRL_3
- ARIZONA_SPK_OVERHEAT_EINT1
- ARIZONA_SPK_OVERHEAT_EINT1_MASK
- ARIZONA_SPK_OVERHEAT_EINT1_SHIFT
- ARIZONA_SPK_OVERHEAT_EINT1_WIDTH
- ARIZONA_SPK_OVERHEAT_EINT2
- ARIZONA_SPK_OVERHEAT_EINT2_MASK
- ARIZONA_SPK_OVERHEAT_EINT2_SHIFT
- ARIZONA_SPK_OVERHEAT_EINT2_WIDTH
- ARIZONA_SPK_OVERHEAT_STS
- ARIZONA_SPK_OVERHEAT_STS_MASK
- ARIZONA_SPK_OVERHEAT_STS_SHIFT
- ARIZONA_SPK_OVERHEAT_STS_WIDTH
- ARIZONA_SPK_OVERHEAT_WARN_EINT1
- ARIZONA_SPK_OVERHEAT_WARN_EINT1_MASK
- ARIZONA_SPK_OVERHEAT_WARN_EINT1_SHIFT
- ARIZONA_SPK_OVERHEAT_WARN_EINT1_WIDTH
- ARIZONA_SPK_OVERHEAT_WARN_EINT2
- ARIZONA_SPK_OVERHEAT_WARN_EINT2_MASK
- ARIZONA_SPK_OVERHEAT_WARN_EINT2_SHIFT
- ARIZONA_SPK_OVERHEAT_WARN_EINT2_WIDTH
- ARIZONA_SPK_OVERHEAT_WARN_STS
- ARIZONA_SPK_OVERHEAT_WARN_STS_MASK
- ARIZONA_SPK_OVERHEAT_WARN_STS_SHIFT
- ARIZONA_SPK_OVERHEAT_WARN_STS_WIDTH
- ARIZONA_SPK_SHUTDOWN_EINT1
- ARIZONA_SPK_SHUTDOWN_EINT1_MASK
- ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT
- ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH
- ARIZONA_SPK_SHUTDOWN_EINT2
- ARIZONA_SPK_SHUTDOWN_EINT2_MASK
- ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT
- ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH
- ARIZONA_SPK_SHUTDOWN_STS
- ARIZONA_SPK_SHUTDOWN_STS_MASK
- ARIZONA_SPK_SHUTDOWN_STS_SHIFT
- ARIZONA_SPK_SHUTDOWN_STS_WIDTH
- ARIZONA_SUBSYS_MAX_FREQ
- ARIZONA_SUBSYS_MAX_FREQ_SHIFT
- ARIZONA_SUBSYS_MAX_FREQ_WIDTH
- ARIZONA_SW1_MODE_MASK
- ARIZONA_SW1_MODE_SHIFT
- ARIZONA_SW1_MODE_WIDTH
- ARIZONA_SW_RST_DEV_ID1_MASK
- ARIZONA_SW_RST_DEV_ID1_SHIFT
- ARIZONA_SW_RST_DEV_ID1_WIDTH
- ARIZONA_SYSCLK_ENA
- ARIZONA_SYSCLK_ENA_LOW_EINT1
- ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK
- ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_SYSCLK_ENA_LOW_EINT2
- ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK
- ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_SYSCLK_ENA_LOW_STS
- ARIZONA_SYSCLK_ENA_LOW_STS_MASK
- ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT
- ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH
- ARIZONA_SYSCLK_ENA_MASK
- ARIZONA_SYSCLK_ENA_SHIFT
- ARIZONA_SYSCLK_ENA_WIDTH
- ARIZONA_SYSCLK_FRAC
- ARIZONA_SYSCLK_FRAC_MASK
- ARIZONA_SYSCLK_FRAC_SHIFT
- ARIZONA_SYSCLK_FRAC_WIDTH
- ARIZONA_SYSCLK_FREQ_MASK
- ARIZONA_SYSCLK_FREQ_SHIFT
- ARIZONA_SYSCLK_FREQ_WIDTH
- ARIZONA_SYSCLK_SRC_MASK
- ARIZONA_SYSCLK_SRC_SHIFT
- ARIZONA_SYSCLK_SRC_WIDTH
- ARIZONA_SYSTEM_CLOCK_1
- ARIZONA_TONE1_ENA
- ARIZONA_TONE1_ENA_MASK
- ARIZONA_TONE1_ENA_SHIFT
- ARIZONA_TONE1_ENA_WIDTH
- ARIZONA_TONE1_LVL_0_MASK
- ARIZONA_TONE1_LVL_0_SHIFT
- ARIZONA_TONE1_LVL_0_WIDTH
- ARIZONA_TONE1_LVL_MASK
- ARIZONA_TONE1_LVL_SHIFT
- ARIZONA_TONE1_LVL_WIDTH
- ARIZONA_TONE1_OVD
- ARIZONA_TONE1_OVD_MASK
- ARIZONA_TONE1_OVD_SHIFT
- ARIZONA_TONE1_OVD_WIDTH
- ARIZONA_TONE2_ENA
- ARIZONA_TONE2_ENA_MASK
- ARIZONA_TONE2_ENA_SHIFT
- ARIZONA_TONE2_ENA_WIDTH
- ARIZONA_TONE2_LVL_0_MASK
- ARIZONA_TONE2_LVL_0_SHIFT
- ARIZONA_TONE2_LVL_0_WIDTH
- ARIZONA_TONE2_LVL_MASK
- ARIZONA_TONE2_LVL_SHIFT
- ARIZONA_TONE2_LVL_WIDTH
- ARIZONA_TONE2_OVD
- ARIZONA_TONE2_OVD_MASK
- ARIZONA_TONE2_OVD_SHIFT
- ARIZONA_TONE2_OVD_WIDTH
- ARIZONA_TONE_GENERATOR_1
- ARIZONA_TONE_GENERATOR_2
- ARIZONA_TONE_GENERATOR_3
- ARIZONA_TONE_GENERATOR_4
- ARIZONA_TONE_GENERATOR_5
- ARIZONA_TONE_OFFSET_MASK
- ARIZONA_TONE_OFFSET_SHIFT
- ARIZONA_TONE_OFFSET_WIDTH
- ARIZONA_TONE_RATE_MASK
- ARIZONA_TONE_RATE_SHIFT
- ARIZONA_TONE_RATE_WIDTH
- ARIZONA_TRIG_ON_STARTUP
- ARIZONA_TRIG_ON_STARTUP_MASK
- ARIZONA_TRIG_ON_STARTUP_SHIFT
- ARIZONA_TRIG_ON_STARTUP_WIDTH
- ARIZONA_TST_CAP_CLAMP
- ARIZONA_TST_CAP_DEFAULT
- ARIZONA_UNDERCLOCKED_EINT1
- ARIZONA_UNDERCLOCKED_EINT1_MASK
- ARIZONA_UNDERCLOCKED_EINT1_SHIFT
- ARIZONA_UNDERCLOCKED_EINT1_WIDTH
- ARIZONA_UNDERCLOCKED_EINT2
- ARIZONA_UNDERCLOCKED_EINT2_MASK
- ARIZONA_UNDERCLOCKED_EINT2_SHIFT
- ARIZONA_UNDERCLOCKED_EINT2_WIDTH
- ARIZONA_UNDERCLOCKED_STS
- ARIZONA_UNDERCLOCKED_STS_MASK
- ARIZONA_UNDERCLOCKED_STS_SHIFT
- ARIZONA_UNDERCLOCKED_STS_WIDTH
- ARIZONA_V2_AIF1_ERR_EINT1
- ARIZONA_V2_AIF1_ERR_EINT1_MASK
- ARIZONA_V2_AIF1_ERR_EINT1_SHIFT
- ARIZONA_V2_AIF1_ERR_EINT1_WIDTH
- ARIZONA_V2_AIF1_ERR_EINT2
- ARIZONA_V2_AIF1_ERR_EINT2_MASK
- ARIZONA_V2_AIF1_ERR_EINT2_SHIFT
- ARIZONA_V2_AIF1_ERR_EINT2_WIDTH
- ARIZONA_V2_AIF2_ERR_EINT1
- ARIZONA_V2_AIF2_ERR_EINT1_MASK
- ARIZONA_V2_AIF2_ERR_EINT1_SHIFT
- ARIZONA_V2_AIF2_ERR_EINT1_WIDTH
- ARIZONA_V2_AIF2_ERR_EINT2
- ARIZONA_V2_AIF2_ERR_EINT2_MASK
- ARIZONA_V2_AIF2_ERR_EINT2_SHIFT
- ARIZONA_V2_AIF2_ERR_EINT2_WIDTH
- ARIZONA_V2_AIF3_ERR_EINT1
- ARIZONA_V2_AIF3_ERR_EINT1_MASK
- ARIZONA_V2_AIF3_ERR_EINT1_SHIFT
- ARIZONA_V2_AIF3_ERR_EINT1_WIDTH
- ARIZONA_V2_AIF3_ERR_EINT2
- ARIZONA_V2_AIF3_ERR_EINT2_MASK
- ARIZONA_V2_AIF3_ERR_EINT2_SHIFT
- ARIZONA_V2_AIF3_ERR_EINT2_WIDTH
- ARIZONA_V2_ASRC_CFG_ERR_EINT1
- ARIZONA_V2_ASRC_CFG_ERR_EINT1_MASK
- ARIZONA_V2_ASRC_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_ASRC_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_ASRC_CFG_ERR_EINT2
- ARIZONA_V2_ASRC_CFG_ERR_EINT2_MASK
- ARIZONA_V2_ASRC_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_ASRC_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_MASK
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_MASK
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_V2_CTRLIF_ERR_EINT1
- ARIZONA_V2_CTRLIF_ERR_EINT1_MASK
- ARIZONA_V2_CTRLIF_ERR_EINT1_SHIFT
- ARIZONA_V2_CTRLIF_ERR_EINT1_WIDTH
- ARIZONA_V2_CTRLIF_ERR_EINT2
- ARIZONA_V2_CTRLIF_ERR_EINT2_MASK
- ARIZONA_V2_CTRLIF_ERR_EINT2_SHIFT
- ARIZONA_V2_CTRLIF_ERR_EINT2_WIDTH
- ARIZONA_V2_DAC_COMP_1
- ARIZONA_V2_DAC_COMP_2
- ARIZONA_V2_IM_AIF1_ERR_EINT1
- ARIZONA_V2_IM_AIF1_ERR_EINT1_MASK
- ARIZONA_V2_IM_AIF1_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_AIF1_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_AIF1_ERR_EINT2
- ARIZONA_V2_IM_AIF1_ERR_EINT2_MASK
- ARIZONA_V2_IM_AIF1_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_AIF1_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_AIF2_ERR_EINT1
- ARIZONA_V2_IM_AIF2_ERR_EINT1_MASK
- ARIZONA_V2_IM_AIF2_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_AIF2_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_AIF2_ERR_EINT2
- ARIZONA_V2_IM_AIF2_ERR_EINT2_MASK
- ARIZONA_V2_IM_AIF2_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_AIF2_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_AIF3_ERR_EINT1
- ARIZONA_V2_IM_AIF3_ERR_EINT1_MASK
- ARIZONA_V2_IM_AIF3_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_AIF3_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_AIF3_ERR_EINT2
- ARIZONA_V2_IM_AIF3_ERR_EINT2_MASK
- ARIZONA_V2_IM_AIF3_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_AIF3_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_MASK
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_MASK
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_V2_IM_CTRLIF_ERR_EINT1
- ARIZONA_V2_IM_CTRLIF_ERR_EINT1_MASK
- ARIZONA_V2_IM_CTRLIF_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_CTRLIF_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_CTRLIF_ERR_EINT2
- ARIZONA_V2_IM_CTRLIF_ERR_EINT2_MASK
- ARIZONA_V2_IM_CTRLIF_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_CTRLIF_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_MASK
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_MASK
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_MASK
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_MASK
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_MASK
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_MASK
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT
- ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_MASK
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_MASK
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_V2_ISRC1_CFG_ERR_EINT1
- ARIZONA_V2_ISRC1_CFG_ERR_EINT1_MASK
- ARIZONA_V2_ISRC1_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_ISRC1_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_ISRC1_CFG_ERR_EINT2
- ARIZONA_V2_ISRC1_CFG_ERR_EINT2_MASK
- ARIZONA_V2_ISRC1_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_ISRC1_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_ISRC2_CFG_ERR_EINT1
- ARIZONA_V2_ISRC2_CFG_ERR_EINT1_MASK
- ARIZONA_V2_ISRC2_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_ISRC2_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_ISRC2_CFG_ERR_EINT2
- ARIZONA_V2_ISRC2_CFG_ERR_EINT2_MASK
- ARIZONA_V2_ISRC2_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_ISRC2_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_ISRC3_CFG_ERR_EINT1
- ARIZONA_V2_ISRC3_CFG_ERR_EINT1_MASK
- ARIZONA_V2_ISRC3_CFG_ERR_EINT1_SHIFT
- ARIZONA_V2_ISRC3_CFG_ERR_EINT1_WIDTH
- ARIZONA_V2_ISRC3_CFG_ERR_EINT2
- ARIZONA_V2_ISRC3_CFG_ERR_EINT2_MASK
- ARIZONA_V2_ISRC3_CFG_ERR_EINT2_SHIFT
- ARIZONA_V2_ISRC3_CFG_ERR_EINT2_WIDTH
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_MASK
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_SHIFT
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_WIDTH
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_MASK
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_SHIFT
- ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_WIDTH
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT1
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_MASK
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_SHIFT
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_WIDTH
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT2
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_MASK
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_SHIFT
- ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_WIDTH
- ARIZONA_WAKE_CONTROL
- ARIZONA_WKUP_GP5_FALL
- ARIZONA_WKUP_GP5_FALL_MASK
- ARIZONA_WKUP_GP5_FALL_SHIFT
- ARIZONA_WKUP_GP5_FALL_WIDTH
- ARIZONA_WKUP_GP5_RISE
- ARIZONA_WKUP_GP5_RISE_MASK
- ARIZONA_WKUP_GP5_RISE_SHIFT
- ARIZONA_WKUP_GP5_RISE_WIDTH
- ARIZONA_WKUP_JD1_FALL
- ARIZONA_WKUP_JD1_FALL_MASK
- ARIZONA_WKUP_JD1_FALL_SHIFT
- ARIZONA_WKUP_JD1_FALL_WIDTH
- ARIZONA_WKUP_JD1_RISE
- ARIZONA_WKUP_JD1_RISE_MASK
- ARIZONA_WKUP_JD1_RISE_SHIFT
- ARIZONA_WKUP_JD1_RISE_WIDTH
- ARIZONA_WKUP_JD2_FALL
- ARIZONA_WKUP_JD2_FALL_MASK
- ARIZONA_WKUP_JD2_FALL_SHIFT
- ARIZONA_WKUP_JD2_FALL_WIDTH
- ARIZONA_WKUP_JD2_RISE
- ARIZONA_WKUP_JD2_RISE_MASK
- ARIZONA_WKUP_JD2_RISE_SHIFT
- ARIZONA_WKUP_JD2_RISE_WIDTH
- ARIZONA_WKUP_MICD_CLAMP_FALL
- ARIZONA_WKUP_MICD_CLAMP_FALL_MASK
- ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT
- ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH
- ARIZONA_WKUP_MICD_CLAMP_RISE
- ARIZONA_WKUP_MICD_CLAMP_RISE_MASK
- ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT
- ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH
- ARIZONA_WRITE_SEQUENCER_CTRL_0
- ARIZONA_WRITE_SEQUENCER_CTRL_1
- ARIZONA_WRITE_SEQUENCER_CTRL_2
- ARIZONA_WRITE_SEQUENCER_CTRL_3
- ARIZONA_WRITE_SEQUENCER_PROM
- ARIZONA_WSEQ_ABORT
- ARIZONA_WSEQ_ABORT_MASK
- ARIZONA_WSEQ_ABORT_SHIFT
- ARIZONA_WSEQ_ABORT_WIDTH
- ARIZONA_WSEQ_BUSY
- ARIZONA_WSEQ_BUSY_MASK
- ARIZONA_WSEQ_BUSY_SHIFT
- ARIZONA_WSEQ_BUSY_WIDTH
- ARIZONA_WSEQ_CURRENT_INDEX_MASK
- ARIZONA_WSEQ_CURRENT_INDEX_SHIFT
- ARIZONA_WSEQ_CURRENT_INDEX_WIDTH
- ARIZONA_WSEQ_DONE_EINT1
- ARIZONA_WSEQ_DONE_EINT1_MASK
- ARIZONA_WSEQ_DONE_EINT1_SHIFT
- ARIZONA_WSEQ_DONE_EINT1_WIDTH
- ARIZONA_WSEQ_DONE_EINT2
- ARIZONA_WSEQ_DONE_EINT2_MASK
- ARIZONA_WSEQ_DONE_EINT2_SHIFT
- ARIZONA_WSEQ_DONE_EINT2_WIDTH
- ARIZONA_WSEQ_DONE_STS
- ARIZONA_WSEQ_DONE_STS_MASK
- ARIZONA_WSEQ_DONE_STS_SHIFT
- ARIZONA_WSEQ_DONE_STS_WIDTH
- ARIZONA_WSEQ_ENA
- ARIZONA_WSEQ_ENA_GP5_FALL
- ARIZONA_WSEQ_ENA_GP5_FALL_MASK
- ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT
- ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH
- ARIZONA_WSEQ_ENA_GP5_RISE
- ARIZONA_WSEQ_ENA_GP5_RISE_MASK
- ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT
- ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH
- ARIZONA_WSEQ_ENA_JD1_FALL
- ARIZONA_WSEQ_ENA_JD1_FALL_MASK
- ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT
- ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH
- ARIZONA_WSEQ_ENA_JD1_RISE
- ARIZONA_WSEQ_ENA_JD1_RISE_MASK
- ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT
- ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH
- ARIZONA_WSEQ_ENA_JD2_FALL
- ARIZONA_WSEQ_ENA_JD2_FALL_MASK
- ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT
- ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH
- ARIZONA_WSEQ_ENA_JD2_RISE
- ARIZONA_WSEQ_ENA_JD2_RISE_MASK
- ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT
- ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH
- ARIZONA_WSEQ_ENA_MASK
- ARIZONA_WSEQ_ENA_SHIFT
- ARIZONA_WSEQ_ENA_WIDTH
- ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK
- ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK
- ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK
- ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK
- ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK
- ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK
- ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_LOAD_MEM
- ARIZONA_WSEQ_LOAD_MEM_MASK
- ARIZONA_WSEQ_LOAD_MEM_SHIFT
- ARIZONA_WSEQ_LOAD_MEM_WIDTH
- ARIZONA_WSEQ_OTP_WRITE
- ARIZONA_WSEQ_OTP_WRITE_MASK
- ARIZONA_WSEQ_OTP_WRITE_SHIFT
- ARIZONA_WSEQ_OTP_WRITE_WIDTH
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT
- ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH
- ARIZONA_WSEQ_START
- ARIZONA_WSEQ_START_INDEX_MASK
- ARIZONA_WSEQ_START_INDEX_SHIFT
- ARIZONA_WSEQ_START_INDEX_WIDTH
- ARIZONA_WSEQ_START_MASK
- ARIZONA_WSEQ_START_SHIFT
- ARIZONA_WSEQ_START_WIDTH
- ARIZONA_WS_TRG1
- ARIZONA_WS_TRG1_MASK
- ARIZONA_WS_TRG1_SHIFT
- ARIZONA_WS_TRG1_WIDTH
- ARIZONA_WS_TRG2
- ARIZONA_WS_TRG2_MASK
- ARIZONA_WS_TRG2_SHIFT
- ARIZONA_WS_TRG2_WIDTH
- ARIZONA_WS_TRG3
- ARIZONA_WS_TRG3_MASK
- ARIZONA_WS_TRG3_SHIFT
- ARIZONA_WS_TRG3_WIDTH
- ARIZONA_WS_TRG4
- ARIZONA_WS_TRG4_MASK
- ARIZONA_WS_TRG4_SHIFT
- ARIZONA_WS_TRG4_WIDTH
- ARIZONA_WS_TRG5
- ARIZONA_WS_TRG5_MASK
- ARIZONA_WS_TRG5_SHIFT
- ARIZONA_WS_TRG5_WIDTH
- ARIZONA_WS_TRG6
- ARIZONA_WS_TRG6_MASK
- ARIZONA_WS_TRG6_SHIFT
- ARIZONA_WS_TRG6_WIDTH
- ARIZONA_WS_TRG7
- ARIZONA_WS_TRG7_MASK
- ARIZONA_WS_TRG7_SHIFT
- ARIZONA_WS_TRG7_WIDTH
- ARIZONA_WS_TRG8
- ARIZONA_WS_TRG8_MASK
- ARIZONA_WS_TRG8_SHIFT
- ARIZONA_WS_TRG8_WIDTH
- ARK_TIMEOUT
- ARLA_VTBL_CMD_CLEAR
- ARLA_VTBL_CMD_READ
- ARLA_VTBL_CMD_WRITE
- ARLA_VTBL_STDN
- ARLTBL_AGE
- ARLTBL_AGE_25
- ARLTBL_DATA_PORT_ID_MASK
- ARLTBL_DATA_PORT_ID_MASK_25
- ARLTBL_DATA_PORT_ID_S_25
- ARLTBL_IVL_SVL_SELECT
- ARLTBL_MAC_MASK
- ARLTBL_RW
- ARLTBL_START_DONE
- ARLTBL_STATIC
- ARLTBL_STATIC_25
- ARLTBL_TC
- ARLTBL_VALID
- ARLTBL_VALID_25
- ARLTBL_VID_MASK
- ARLTBL_VID_MASK_25
- ARLTBL_VID_S
- ARL_ADDR_MASK
- ARL_SRCH_STDN
- ARL_SRCH_VLID
- ARM
- ARM2LBUS_FIFO0
- ARM2LBUS_FIFO1
- ARM2LBUS_FIFO10
- ARM2LBUS_FIFO11
- ARM2LBUS_FIFO12
- ARM2LBUS_FIFO13
- ARM2LBUS_FIFO14
- ARM2LBUS_FIFO15
- ARM2LBUS_FIFO2
- ARM2LBUS_FIFO3
- ARM2LBUS_FIFO4
- ARM2LBUS_FIFO5
- ARM2LBUS_FIFO6
- ARM2LBUS_FIFO7
- ARM2LBUS_FIFO8
- ARM2LBUS_FIFO9
- ARM2LBUS_FIFO_DIRECT
- ARM64_ALT_PAN_NOT_UAO
- ARM64_BP_HARDEN_NOT_REQUIRED
- ARM64_BP_HARDEN_UNKNOWN
- ARM64_BP_HARDEN_WA_NEEDED
- ARM64_CB_PATCH
- ARM64_CORE_REG
- ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE
- ARM64_CPUCAP_LOCAL_CPU_ERRATUM
- ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU
- ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU
- ARM64_CPUCAP_SCOPE_BOOT_CPU
- ARM64_CPUCAP_SCOPE_LOCAL_CPU
- ARM64_CPUCAP_SCOPE_MASK
- ARM64_CPUCAP_SCOPE_SYSTEM
- ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE
- ARM64_CPUCAP_SYSTEM_FEATURE
- ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
- ARM64_FTR_BITS
- ARM64_FTR_END
- ARM64_FTR_REG
- ARM64_HARDEN_BRANCH_PREDICTOR
- ARM64_HARDEN_EL2_VECTORS
- ARM64_HAS_32BIT_EL0
- ARM64_HAS_ADDRESS_AUTH_ARCH
- ARM64_HAS_ADDRESS_AUTH_IMP_DEF
- ARM64_HAS_CACHE_DIC
- ARM64_HAS_CACHE_IDC
- ARM64_HAS_CNP
- ARM64_HAS_CRC32
- ARM64_HAS_DCPODP
- ARM64_HAS_DCPOP
- ARM64_HAS_GENERIC_AUTH_ARCH
- ARM64_HAS_GENERIC_AUTH_IMP_DEF
- ARM64_HAS_IRQ_PRIO_MASKING
- ARM64_HAS_LSE_ATOMICS
- ARM64_HAS_NO_FPSIMD
- ARM64_HAS_NO_HW_PREFETCH
- ARM64_HAS_PAN
- ARM64_HAS_RAS_EXTN
- ARM64_HAS_SB
- ARM64_HAS_STAGE2_FWB
- ARM64_HAS_SYSREG_GIC_CPUIF
- ARM64_HAS_UAO
- ARM64_HAS_VIRT_HOST_EXTN
- ARM64_HW_DBM
- ARM64_HW_PGTABLE_LEVELS
- ARM64_HW_PGTABLE_LEVEL_SHIFT
- ARM64_IMAGE_FLAG_BE
- ARM64_IMAGE_FLAG_BE_MASK
- ARM64_IMAGE_FLAG_BE_SHIFT
- ARM64_IMAGE_FLAG_LE
- ARM64_IMAGE_FLAG_PAGE_SIZE_16K
- ARM64_IMAGE_FLAG_PAGE_SIZE_4K
- ARM64_IMAGE_FLAG_PAGE_SIZE_64K
- ARM64_IMAGE_FLAG_PAGE_SIZE_MASK
- ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT
- ARM64_IMAGE_FLAG_PHYS_BASE
- ARM64_IMAGE_FLAG_PHYS_BASE_MASK
- ARM64_IMAGE_FLAG_PHYS_BASE_SHIFT
- ARM64_IMAGE_MAGIC
- ARM64_LPI_IS_RETENTION_STATE
- ARM64_LSE_ATOMIC_INSN
- ARM64_MEMSTART_ALIGN
- ARM64_MEMSTART_SHIFT
- ARM64_MISMATCHED_CACHE_TYPE
- ARM64_NCAPS
- ARM64_NPATCHABLE
- ARM64_SSBD
- ARM64_SSBD_FORCE_DISABLE
- ARM64_SSBD_FORCE_ENABLE
- ARM64_SSBD_KERNEL
- ARM64_SSBD_MITIGATED
- ARM64_SSBD_UNKNOWN
- ARM64_SSBS
- ARM64_SVE
- ARM64_SWAPPER_USES_SECTION_MAPS
- ARM64_SYS_REG
- ARM64_SYS_REG_SHIFT_MASK
- ARM64_TCR_EPD0
- ARM64_TCR_EPD1
- ARM64_TCR_IPS
- ARM64_TCR_IRGN0
- ARM64_TCR_ORGN0
- ARM64_TCR_SH0
- ARM64_TCR_T0SZ
- ARM64_TCR_TBI0
- ARM64_TCR_TG0
- ARM64_UNMAP_KERNEL_AT_EL0
- ARM64_VDSO
- ARM64_VDSO32
- ARM64_VTTBR_X
- ARM64_WORKAROUND_1165522
- ARM64_WORKAROUND_1418040
- ARM64_WORKAROUND_1463225
- ARM64_WORKAROUND_1542419
- ARM64_WORKAROUND_834220
- ARM64_WORKAROUND_843419
- ARM64_WORKAROUND_845719
- ARM64_WORKAROUND_858921
- ARM64_WORKAROUND_CAVIUM_23154
- ARM64_WORKAROUND_CAVIUM_27456
- ARM64_WORKAROUND_CAVIUM_30115
- ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
- ARM64_WORKAROUND_CAVIUM_TX2_219_TVM
- ARM64_WORKAROUND_CLEAN_CACHE
- ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE
- ARM64_WORKAROUND_QCOM_FALKOR_E1003
- ARM64_WORKAROUND_REPEAT_TLBI
- ARMADA8K_PCIE_MAX_LANES
- ARMADA_3700_SOC_PAD_1_8V
- ARMADA_3700_SOC_PAD_3_3V
- ARMADA_370_A1_REV
- ARMADA_370_CRYPT0_ENG_ATTR
- ARMADA_370_CRYPT0_ENG_TARGET
- ARMADA_370_DEV_ID
- ARMADA_370_XP_CPU_INTACK_OFFS
- ARMADA_370_XP_INT_CAUSE_PERF
- ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS
- ARMADA_370_XP_INT_CLEAR_MASK_OFFS
- ARMADA_370_XP_INT_CONTROL
- ARMADA_370_XP_INT_FABRIC_MASK_OFFS
- ARMADA_370_XP_INT_IRQ_FIQ_MASK
- ARMADA_370_XP_INT_SET_ENABLE_OFFS
- ARMADA_370_XP_INT_SET_MASK_OFFS
- ARMADA_370_XP_INT_SOURCE_CPU_MASK
- ARMADA_370_XP_INT_SOURCE_CTL
- ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS
- ARMADA_370_XP_IN_DRBEL_MSK_OFFS
- ARMADA_370_XP_MAX_PER_CPU_IRQS
- ARMADA_370_XP_SW_TRIG_INT_OFFS
- ARMADA_375_A0_REV
- ARMADA_375_CRYPT0_ENG_ATTR
- ARMADA_375_CRYPT0_ENG_TARGET
- ARMADA_375_DEV_ID
- ARMADA_375_PPI_CAUSE
- ARMADA_375_Z1_REV
- ARMADA_37XX_AVS_CTL0
- ARMADA_37XX_AVS_CTL2
- ARMADA_37XX_AVS_ENABLE
- ARMADA_37XX_AVS_HIGH_VDD_LIMIT
- ARMADA_37XX_AVS_LOW_VDD_EN
- ARMADA_37XX_AVS_LOW_VDD_LIMIT
- ARMADA_37XX_AVS_VDD_MASK
- ARMADA_37XX_AVS_VSET
- ARMADA_37XX_DVFS_LOAD_0
- ARMADA_37XX_DVFS_LOAD_1
- ARMADA_37XX_DVFS_LOAD_2
- ARMADA_37XX_DVFS_LOAD_3
- ARMADA_37XX_NB_CLK_SEL_EN
- ARMADA_37XX_NB_CLK_SEL_MASK
- ARMADA_37XX_NB_CLK_SEL_OFF
- ARMADA_37XX_NB_CLK_SEL_TBG
- ARMADA_37XX_NB_CONFIG_SHIFT
- ARMADA_37XX_NB_CPU_LOAD
- ARMADA_37XX_NB_CPU_LOAD_MASK
- ARMADA_37XX_NB_DFS_EN
- ARMADA_37XX_NB_DIV_EN
- ARMADA_37XX_NB_DYN_MOD
- ARMADA_37XX_NB_L0L1
- ARMADA_37XX_NB_L2L3
- ARMADA_37XX_NB_TBG_DIV_MASK
- ARMADA_37XX_NB_TBG_DIV_OFF
- ARMADA_37XX_NB_TBG_EN
- ARMADA_37XX_NB_TBG_SEL_MASK
- ARMADA_37XX_NB_TBG_SEL_OFF
- ARMADA_37XX_NB_VDD_EN
- ARMADA_37XX_NB_VDD_SEL_MASK
- ARMADA_37XX_NB_VDD_SEL_OFF
- ARMADA_380_DEV_ID
- ARMADA_385_DEV_ID
- ARMADA_388_DEV_ID
- ARMADA_38x_A0_REV
- ARMADA_38x_Z1_REV
- ARMADA_ACC_FIRST_SHIFT
- ARMADA_ACC_NEXT_SHIFT
- ARMADA_BADR_SKEW_SHIFT
- ARMADA_CRTC_H
- ARMADA_DEBUGFS_ENTRIES
- ARMADA_DEV_WIDTH_SHIFT
- ARMADA_DRM_H
- ARMADA_FB_H
- ARMADA_GEM_H
- ARMADA_HW_H
- ARMADA_IOCTL
- ARMADA_IOCTLP_H
- ARMADA_IOCTL_PROTO
- ARMADA_PIC_NR_GPIOS
- ARMADA_PLANE_H
- ARMADA_RD_HOLD_SHIFT
- ARMADA_RD_SETUP_SHIFT
- ARMADA_READ_PARAM_OFFSET
- ARMADA_SPI
- ARMADA_SPI_CLK_PRESCALE_MASK
- ARMADA_SYNC_ENABLE_SHIFT
- ARMADA_TRACE_H
- ARMADA_WRITE_PARAM_OFFSET
- ARMADA_WR_HIGH_SHIFT
- ARMADA_WR_LOW_SHIFT
- ARMADA_XP_CFB_CFG_REG_OFFSET
- ARMADA_XP_CFB_CTL_REG_OFFSET
- ARMADA_XP_MAX_CPUS
- ARMADILLO5X0_RTC_GPIO
- ARMCLK
- ARMCLKB
- ARMCLKL
- ARMCLK_STOPCTRL
- ARMCLK_STOPCTRL_KFC
- ARMCP_IF_H
- ARMCP_MAX_SENSORS
- ARMCP_PACKET_CURRENT_GET
- ARMCP_PACKET_DISABLE_PCI_ACCESS
- ARMCP_PACKET_EEPROM_DATA_GET
- ARMCP_PACKET_ENABLE_PCI_ACCESS
- ARMCP_PACKET_FAN_SPEED_GET
- ARMCP_PACKET_FENCE_VAL
- ARMCP_PACKET_FLASH_PROGRAM_REMOVED
- ARMCP_PACKET_FREQUENCY_CURR_GET
- ARMCP_PACKET_FREQUENCY_GET
- ARMCP_PACKET_FREQUENCY_SET
- ARMCP_PACKET_I2C_RD
- ARMCP_PACKET_I2C_WR
- ARMCP_PACKET_INFO_GET
- ARMCP_PACKET_LED_SET
- ARMCP_PACKET_MAX_POWER_GET
- ARMCP_PACKET_MAX_POWER_SET
- ARMCP_PACKET_PWM_GET
- ARMCP_PACKET_PWM_SET
- ARMCP_PACKET_TEMPERATURE_GET
- ARMCP_PACKET_TEST
- ARMCP_PACKET_UNMASK_RAZWI_IRQ
- ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY
- ARMCP_PACKET_VOLTAGE_GET
- ARMCP_PKT_CTL_OPCODE_MASK
- ARMCP_PKT_CTL_OPCODE_SHIFT
- ARMCP_PKT_CTL_RC_MASK
- ARMCP_PKT_CTL_RC_SHIFT
- ARMCR4_BANKIDX
- ARMCR4_BANKINFO
- ARMCR4_BANKPDA
- ARMCR4_BCMA_IOCTL_CPUHALT
- ARMCR4_BSZ_MASK
- ARMCR4_BSZ_MULT
- ARMCR4_CAP
- ARMCR4_TCBANB_MASK
- ARMCR4_TCBANB_SHIFT
- ARMCR4_TCBBNB_MASK
- ARMCR4_TCBBNB_SHIFT
- ARMCSR_BASE
- ARMCSR_SIZE
- ARMDIV
- ARMPMU_ATTR_GROUP_COMMON
- ARMPMU_ATTR_GROUP_EVENTS
- ARMPMU_ATTR_GROUP_FORMATS
- ARMPMU_EVT_64BIT
- ARMPMU_MAX_HWEVENTS
- ARMPMU_NR_ATTR_GROUPS
- ARMREGU1VALTO_ERR
- ARMREGU2VALTO_ERR
- ARMV6MPCORE_PERFCTR_BR_EXEC
- ARMV6MPCORE_PERFCTR_BR_MISPREDICT
- ARMV6MPCORE_PERFCTR_BR_NOTPREDICT
- ARMV6MPCORE_PERFCTR_CPU_CYCLES
- ARMV6MPCORE_PERFCTR_DCACHE_EVICTION
- ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS
- ARMV6MPCORE_PERFCTR_DCACHE_RDMISS
- ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS
- ARMV6MPCORE_PERFCTR_DCACHE_WRMISS
- ARMV6MPCORE_PERFCTR_DDEP_STALL
- ARMV6MPCORE_PERFCTR_DTLB_MISS
- ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS
- ARMV6MPCORE_PERFCTR_IBUF_STALL
- ARMV6MPCORE_PERFCTR_ICACHE_MISS
- ARMV6MPCORE_PERFCTR_INSTR_EXEC
- ARMV6MPCORE_PERFCTR_ITLB_MISS
- ARMV6MPCORE_PERFCTR_LSU_FULL_STALL
- ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS
- ARMV6MPCORE_PERFCTR_SW_PC_CHANGE
- ARMV6MPCORE_PERFCTR_WBUF_DRAINED
- ARMV6_COUNTER0
- ARMV6_COUNTER1
- ARMV6_CYCLE_COUNTER
- ARMV6_PERFCTR_BR_EXEC
- ARMV6_PERFCTR_BR_MISPREDICT
- ARMV6_PERFCTR_CPU_CYCLES
- ARMV6_PERFCTR_DCACHE_ACCESS
- ARMV6_PERFCTR_DCACHE_HIT
- ARMV6_PERFCTR_DCACHE_MISS
- ARMV6_PERFCTR_DCACHE_WBACK
- ARMV6_PERFCTR_DDEP_STALL
- ARMV6_PERFCTR_DTLB_MISS
- ARMV6_PERFCTR_EXPL_D_ACCESS
- ARMV6_PERFCTR_IBUF_STALL
- ARMV6_PERFCTR_ICACHE_MISS
- ARMV6_PERFCTR_INSTR_EXEC
- ARMV6_PERFCTR_ITLB_MISS
- ARMV6_PERFCTR_LSU_FULL_STALL
- ARMV6_PERFCTR_MAIN_TLB_MISS
- ARMV6_PERFCTR_NOP
- ARMV6_PERFCTR_SW_PC_CHANGE
- ARMV6_PERFCTR_WBUF_DRAINED
- ARMV6_PMCR_CCOUNT_DIV
- ARMV6_PMCR_CCOUNT_IEN
- ARMV6_PMCR_CCOUNT_OVERFLOW
- ARMV6_PMCR_CCOUNT_RESET
- ARMV6_PMCR_COUNT0_IEN
- ARMV6_PMCR_COUNT0_OVERFLOW
- ARMV6_PMCR_COUNT1_IEN
- ARMV6_PMCR_COUNT1_OVERFLOW
- ARMV6_PMCR_CTR01_RESET
- ARMV6_PMCR_ENABLE
- ARMV6_PMCR_EVT_COUNT0_MASK
- ARMV6_PMCR_EVT_COUNT0_SHIFT
- ARMV6_PMCR_EVT_COUNT1_MASK
- ARMV6_PMCR_EVT_COUNT1_SHIFT
- ARMV6_PMCR_OVERFLOWED_MASK
- ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ
- ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE
- ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ
- ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE
- ARMV7_A12_PERFCTR_PC_WRITE_SPEC
- ARMV7_A12_PERFCTR_PF_TLB_REFILL
- ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ
- ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE
- ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ
- ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE
- ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ
- ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE
- ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ
- ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE
- ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ
- ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE
- ARMV7_A15_PERFCTR_PC_WRITE_SPEC
- ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
- ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
- ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS
- ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
- ARMV7_A8_PERFCTR_L2_CACHE_REFILL
- ARMV7_A8_PERFCTR_STALL_ISIDE
- ARMV7_A9_PERFCTR_INSTR_CORE_RENAME
- ARMV7_A9_PERFCTR_STALL_DISPATCH
- ARMV7_A9_PERFCTR_STALL_ICACHE
- ARMV7_COUNTER_MASK
- ARMV7_EVENT_ATTR
- ARMV7_EVENT_ATTR_RESOLVE
- ARMV7_EVTYPE_EVENT
- ARMV7_EVTYPE_MASK
- ARMV7_EXCLUDE_PL1
- ARMV7_EXCLUDE_USER
- ARMV7_FLAG_MASK
- ARMV7_IDX_COUNTER0
- ARMV7_IDX_COUNTER_LAST
- ARMV7_IDX_CYCLE_COUNTER
- ARMV7_IDX_TO_COUNTER
- ARMV7_INCLUDE_HYP
- ARMV7_MAX_COUNTERS
- ARMV7_OVERFLOWED_MASK
- ARMV7_PERFCTR_BUS_ACCESS
- ARMV7_PERFCTR_BUS_CYCLES
- ARMV7_PERFCTR_CID_WRITE
- ARMV7_PERFCTR_CLOCK_CYCLES
- ARMV7_PERFCTR_CPU_CYCLES
- ARMV7_PERFCTR_DTLB_REFILL
- ARMV7_PERFCTR_EXC_EXECUTED
- ARMV7_PERFCTR_EXC_TAKEN
- ARMV7_PERFCTR_INSTR_EXECUTED
- ARMV7_PERFCTR_INSTR_SPEC
- ARMV7_PERFCTR_ITLB_REFILL
- ARMV7_PERFCTR_L1_DCACHE_ACCESS
- ARMV7_PERFCTR_L1_DCACHE_REFILL
- ARMV7_PERFCTR_L1_DCACHE_WB
- ARMV7_PERFCTR_L1_ICACHE_ACCESS
- ARMV7_PERFCTR_L1_ICACHE_REFILL
- ARMV7_PERFCTR_L2_CACHE_ACCESS
- ARMV7_PERFCTR_L2_CACHE_REFILL
- ARMV7_PERFCTR_L2_CACHE_WB
- ARMV7_PERFCTR_MEM_ACCESS
- ARMV7_PERFCTR_MEM_ERROR
- ARMV7_PERFCTR_MEM_READ
- ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS
- ARMV7_PERFCTR_MEM_WRITE
- ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
- ARMV7_PERFCTR_PC_BRANCH_PRED
- ARMV7_PERFCTR_PC_IMM_BRANCH
- ARMV7_PERFCTR_PC_PROC_RETURN
- ARMV7_PERFCTR_PC_WRITE
- ARMV7_PERFCTR_PMNC_SW_INCR
- ARMV7_PERFCTR_TTBR_WRITE
- ARMV7_PMNC_C
- ARMV7_PMNC_D
- ARMV7_PMNC_DP
- ARMV7_PMNC_E
- ARMV7_PMNC_MASK
- ARMV7_PMNC_N_MASK
- ARMV7_PMNC_N_SHIFT
- ARMV7_PMNC_P
- ARMV7_PMNC_X
- ARMV7_SDER_SUNIDEN
- ARMV8_A53_PERFCTR_PREF_LINEFILL
- ARMV8_EVENT_ATTR
- ARMV8_IDX_COUNTER0
- ARMV8_IDX_COUNTER_LAST
- ARMV8_IDX_CYCLE_COUNTER
- ARMV8_IDX_TO_COUNTER
- ARMV8_IMPDEF_PERFCTR_ASE_SPEC
- ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC
- ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC
- ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED
- ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR
- ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC
- ARMV8_IMPDEF_PERFCTR_DMB_SPEC
- ARMV8_IMPDEF_PERFCTR_DP_SPEC
- ARMV8_IMPDEF_PERFCTR_DSB_SPEC
- ARMV8_IMPDEF_PERFCTR_EXC_DABORT
- ARMV8_IMPDEF_PERFCTR_EXC_FIQ
- ARMV8_IMPDEF_PERFCTR_EXC_HVC
- ARMV8_IMPDEF_PERFCTR_EXC_IRQ
- ARMV8_IMPDEF_PERFCTR_EXC_PABORT
- ARMV8_IMPDEF_PERFCTR_EXC_SMC
- ARMV8_IMPDEF_PERFCTR_EXC_SVC
- ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT
- ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ
- ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ
- ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER
- ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT
- ARMV8_IMPDEF_PERFCTR_EXC_UNDEF
- ARMV8_IMPDEF_PERFCTR_ISB_SPEC
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM
- ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR
- ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD
- ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD
- ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR
- ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM
- ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR
- ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD
- ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD
- ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR
- ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM
- ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR
- ARMV8_IMPDEF_PERFCTR_LDREX_SPEC
- ARMV8_IMPDEF_PERFCTR_LDST_SPEC
- ARMV8_IMPDEF_PERFCTR_LD_SPEC
- ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD
- ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR
- ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC
- ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC
- ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC
- ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC
- ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC
- ARMV8_IMPDEF_PERFCTR_STREX_SPEC
- ARMV8_IMPDEF_PERFCTR_ST_SPEC
- ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC
- ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC
- ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC
- ARMV8_IMPDEF_PERFCTR_VFP_SPEC
- ARMV8_PMUV3_EXT_COMMON_EVENT_BASE
- ARMV8_PMUV3_MAX_COMMON_EVENTS
- ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED
- ARMV8_PMUV3_PERFCTR_BR_MIS_PRED
- ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED
- ARMV8_PMUV3_PERFCTR_BR_PRED
- ARMV8_PMUV3_PERFCTR_BR_RETIRED
- ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED
- ARMV8_PMUV3_PERFCTR_BUS_ACCESS
- ARMV8_PMUV3_PERFCTR_BUS_CYCLES
- ARMV8_PMUV3_PERFCTR_CHAIN
- ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED
- ARMV8_PMUV3_PERFCTR_CPU_CYCLES
- ARMV8_PMUV3_PERFCTR_DTLB_WALK
- ARMV8_PMUV3_PERFCTR_EXC_RETURN
- ARMV8_PMUV3_PERFCTR_EXC_TAKEN
- ARMV8_PMUV3_PERFCTR_INST_RETIRED
- ARMV8_PMUV3_PERFCTR_INST_SPEC
- ARMV8_PMUV3_PERFCTR_ITLB_WALK
- ARMV8_PMUV3_PERFCTR_L1D_CACHE
- ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE
- ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL
- ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB
- ARMV8_PMUV3_PERFCTR_L1D_TLB
- ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL
- ARMV8_PMUV3_PERFCTR_L1I_CACHE
- ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL
- ARMV8_PMUV3_PERFCTR_L1I_TLB
- ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL
- ARMV8_PMUV3_PERFCTR_L2D_CACHE
- ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE
- ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL
- ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB
- ARMV8_PMUV3_PERFCTR_L2D_TLB
- ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL
- ARMV8_PMUV3_PERFCTR_L2I_CACHE
- ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL
- ARMV8_PMUV3_PERFCTR_L2I_TLB
- ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL
- ARMV8_PMUV3_PERFCTR_L3D_CACHE
- ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE
- ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL
- ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB
- ARMV8_PMUV3_PERFCTR_LD_RETIRED
- ARMV8_PMUV3_PERFCTR_LL_CACHE
- ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS
- ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD
- ARMV8_PMUV3_PERFCTR_LL_CACHE_RD
- ARMV8_PMUV3_PERFCTR_MEMORY_ERROR
- ARMV8_PMUV3_PERFCTR_MEM_ACCESS
- ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED
- ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS
- ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD
- ARMV8_PMUV3_PERFCTR_STALL_BACKEND
- ARMV8_PMUV3_PERFCTR_STALL_FRONTEND
- ARMV8_PMUV3_PERFCTR_ST_RETIRED
- ARMV8_PMUV3_PERFCTR_SW_INCR
- ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED
- ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED
- ARMV8_PMU_COUNTER_MASK
- ARMV8_PMU_CYCLE_IDX
- ARMV8_PMU_EVTYPE_EVENT
- ARMV8_PMU_EVTYPE_MASK
- ARMV8_PMU_EXCLUDE_EL0
- ARMV8_PMU_EXCLUDE_EL1
- ARMV8_PMU_INCLUDE_EL2
- ARMV8_PMU_MAX_COUNTERS
- ARMV8_PMU_MAX_COUNTER_PAIRS
- ARMV8_PMU_OVERFLOWED_MASK
- ARMV8_PMU_OVSR_MASK
- ARMV8_PMU_PDEV_NAME
- ARMV8_PMU_PMCR_C
- ARMV8_PMU_PMCR_D
- ARMV8_PMU_PMCR_DP
- ARMV8_PMU_PMCR_E
- ARMV8_PMU_PMCR_LC
- ARMV8_PMU_PMCR_MASK
- ARMV8_PMU_PMCR_N_MASK
- ARMV8_PMU_PMCR_N_SHIFT
- ARMV8_PMU_PMCR_P
- ARMV8_PMU_PMCR_X
- ARMV8_PMU_USERENR_CR
- ARMV8_PMU_USERENR_EN
- ARMV8_PMU_USERENR_ER
- ARMV8_PMU_USERENR_MASK
- ARMV8_PMU_USERENR_SW
- ARMV8_SPE_PDEV_NAME
- ARMV8_SPE_PERFCTR_SAMPLE_COLLISION
- ARMV8_SPE_PERFCTR_SAMPLE_FEED
- ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE
- ARMV8_SPE_PERFCTR_SAMPLE_POP
- ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST
- ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS
- ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS
- ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS
- ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS
- ARMWFI_ER
- ARMWFI_ERR
- ARM_0_MAIL0
- ARM_0_MAIL1
- ARM_100_OPP
- ARM_32_LPAE_S1
- ARM_32_LPAE_S2
- ARM_32_LPAE_TCR_EAE
- ARM_50_OPP
- ARM_64_LPAE_S1
- ARM_64_LPAE_S2
- ARM_64_LPAE_S2_TCR_RES1
- ARM_ABORT_PENDING
- ARM_ADC_I
- ARM_ADC_R
- ARM_ADDS_I
- ARM_ADDS_R
- ARM_ADD_I
- ARM_ADD_R
- ARM_ANDS_R
- ARM_AND_I
- ARM_AND_R
- ARM_ASR_I
- ARM_ASR_R
- ARM_B
- ARM_BASE_BCR
- ARM_BASE_BVR
- ARM_BASE_WCR
- ARM_BASE_WVR
- ARM_BE8
- ARM_BIC_I
- ARM_BIC_R
- ARM_BLX_R
- ARM_BREAKPOINT_EXECUTE
- ARM_BREAKPOINT_LEN_1
- ARM_BREAKPOINT_LEN_2
- ARM_BREAKPOINT_LEN_3
- ARM_BREAKPOINT_LEN_4
- ARM_BREAKPOINT_LEN_5
- ARM_BREAKPOINT_LEN_6
- ARM_BREAKPOINT_LEN_7
- ARM_BREAKPOINT_LEN_8
- ARM_BREAKPOINT_LOAD
- ARM_BREAKPOINT_PRIV
- ARM_BREAKPOINT_STORE
- ARM_BREAKPOINT_USER
- ARM_BX
- ARM_CKCTL
- ARM_CMP_I
- ARM_CMP_R
- ARM_CONDS
- ARM_COND_AL
- ARM_COND_CC
- ARM_COND_CS
- ARM_COND_EQ
- ARM_COND_GE
- ARM_COND_GT
- ARM_COND_HI
- ARM_COND_HS
- ARM_COND_LE
- ARM_COND_LO
- ARM_COND_LS
- ARM_COND_LT
- ARM_COND_MI
- ARM_COND_NE
- ARM_COND_PL
- ARM_COND_VC
- ARM_COND_VS
- ARM_CONTROL
- ARM_CP15_REG32
- ARM_CP15_REG64
- ARM_CP15_REG_SHIFT_MASK
- ARM_CPUIDLE_WFI_STATE
- ARM_CPUIDLE_WFI_STATE_PWR
- ARM_CPU_DISCARD
- ARM_CPU_IMP_APM
- ARM_CPU_IMP_ARM
- ARM_CPU_IMP_BRCM
- ARM_CPU_IMP_CAVIUM
- ARM_CPU_IMP_DEC
- ARM_CPU_IMP_FUJITSU
- ARM_CPU_IMP_HISI
- ARM_CPU_IMP_INTEL
- ARM_CPU_IMP_NVIDIA
- ARM_CPU_IMP_QCOM
- ARM_CPU_KEEP
- ARM_CPU_PART_AEM_V8
- ARM_CPU_PART_ARM1136
- ARM_CPU_PART_ARM1156
- ARM_CPU_PART_ARM1176
- ARM_CPU_PART_ARM11MPCORE
- ARM_CPU_PART_BRAHMA_B15
- ARM_CPU_PART_BRAHMA_B53
- ARM_CPU_PART_CORTEX_A12
- ARM_CPU_PART_CORTEX_A15
- ARM_CPU_PART_CORTEX_A17
- ARM_CPU_PART_CORTEX_A35
- ARM_CPU_PART_CORTEX_A5
- ARM_CPU_PART_CORTEX_A53
- ARM_CPU_PART_CORTEX_A55
- ARM_CPU_PART_CORTEX_A57
- ARM_CPU_PART_CORTEX_A7
- ARM_CPU_PART_CORTEX_A72
- ARM_CPU_PART_CORTEX_A73
- ARM_CPU_PART_CORTEX_A75
- ARM_CPU_PART_CORTEX_A76
- ARM_CPU_PART_CORTEX_A8
- ARM_CPU_PART_CORTEX_A9
- ARM_CPU_PART_FOUNDATION
- ARM_CPU_PART_MASK
- ARM_CPU_PART_NEOVERSE_N1
- ARM_CPU_PART_SA1100
- ARM_CPU_PART_SA1110
- ARM_CPU_PART_SCORPION
- ARM_CPU_REV_SA1110_A0
- ARM_CPU_REV_SA1110_B0
- ARM_CPU_REV_SA1110_B1
- ARM_CPU_REV_SA1110_B2
- ARM_CPU_REV_SA1110_B4
- ARM_CPU_XSCALE_ARCH_MASK
- ARM_CPU_XSCALE_ARCH_V1
- ARM_CPU_XSCALE_ARCH_V2
- ARM_CPU_XSCALE_ARCH_V3
- ARM_ClearIrq
- ARM_ClearMailBox
- ARM_DBG_READ
- ARM_DBG_WRITE
- ARM_DEBUG_ARCH_RESERVED
- ARM_DEBUG_ARCH_V6
- ARM_DEBUG_ARCH_V6_1
- ARM_DEBUG_ARCH_V7_1
- ARM_DEBUG_ARCH_V7_ECP14
- ARM_DEBUG_ARCH_V7_MM
- ARM_DEBUG_ARCH_V8
- ARM_DISCARD
- ARM_DIV2_ORDER
- ARM_DIV_BODY
- ARM_DSCR_HDBGEN
- ARM_DSCR_MDBGEN
- ARM_DSCR_MOE
- ARM_EMA_CTRL
- ARM_EMA_STATUS
- ARM_EN
- ARM_ENDPROC
- ARM_ENTRY
- ARM_ENTRY_ASYNC_WATCHPOINT
- ARM_ENTRY_BREAKPOINT
- ARM_ENTRY_SYNC_WATCHPOINT
- ARM_EOR_I
- ARM_EOR_R
- ARM_EWUPCT
- ARM_EXCEPTION_CODE
- ARM_EXCEPTION_DATA_ABORT
- ARM_EXCEPTION_EL1_SERROR
- ARM_EXCEPTION_FIQ
- ARM_EXCEPTION_HVC
- ARM_EXCEPTION_HYP_GONE
- ARM_EXCEPTION_IL
- ARM_EXCEPTION_IRQ
- ARM_EXCEPTION_IS_TRAP
- ARM_EXCEPTION_PREF_ABORT
- ARM_EXCEPTION_RESET
- ARM_EXCEPTION_SOFTWARE
- ARM_EXCEPTION_TRAP
- ARM_EXCEPTION_UNDEFINED
- ARM_EXIT_DISCARD
- ARM_EXIT_KEEP
- ARM_EXIT_WITH_ABORT_BIT
- ARM_EXIT_WITH_SERROR_BIT
- ARM_EXTCLK
- ARM_FP
- ARM_FSR_ACCESS_MASK
- ARM_GPC
- ARM_IDLECT1
- ARM_IDLECT1_ASM_OFFSET
- ARM_IDLECT2
- ARM_IDLECT2_ASM_OFFSET
- ARM_IDLECT3
- ARM_INST_ADC_I
- ARM_INST_ADC_R
- ARM_INST_ADDS_I
- ARM_INST_ADDS_R
- ARM_INST_ADD_I
- ARM_INST_ADD_R
- ARM_INST_ANDS_R
- ARM_INST_AND_I
- ARM_INST_AND_R
- ARM_INST_B
- ARM_INST_BIC_I
- ARM_INST_BIC_R
- ARM_INST_BLX_R
- ARM_INST_BX
- ARM_INST_CMP_I
- ARM_INST_CMP_R
- ARM_INST_EOR_I
- ARM_INST_EOR_R
- ARM_INST_LDM
- ARM_INST_LDM_IA
- ARM_INST_LDRB_I
- ARM_INST_LDRB_R
- ARM_INST_LDRD_I
- ARM_INST_LDRH_I
- ARM_INST_LDRH_R
- ARM_INST_LDR_I
- ARM_INST_LDR_R
- ARM_INST_LDST__IMM12
- ARM_INST_LDST__U
- ARM_INST_LSL_I
- ARM_INST_LSL_R
- ARM_INST_LSR_I
- ARM_INST_LSR_R
- ARM_INST_MLS
- ARM_INST_MOVS_R
- ARM_INST_MOVT
- ARM_INST_MOVW
- ARM_INST_MOV_I
- ARM_INST_MOV_R
- ARM_INST_MUL
- ARM_INST_ORRS_R
- ARM_INST_ORR_I
- ARM_INST_ORR_R
- ARM_INST_POP
- ARM_INST_PUSH
- ARM_INST_REV
- ARM_INST_REV16
- ARM_INST_RSBS_I
- ARM_INST_RSB_I
- ARM_INST_RSB_R
- ARM_INST_RSC_I
- ARM_INST_SBCS_R
- ARM_INST_SBC_I
- ARM_INST_SBC_R
- ARM_INST_STRB_I
- ARM_INST_STRD_I
- ARM_INST_STRH_I
- ARM_INST_STR_I
- ARM_INST_SUBS_I
- ARM_INST_SUBS_R
- ARM_INST_SUB_I
- ARM_INST_SUB_R
- ARM_INST_TST_I
- ARM_INST_TST_R
- ARM_INST_UDF
- ARM_INST_UDIV
- ARM_INST_UMULL
- ARM_INST_UXTH
- ARM_IP
- ARM_IRQ_LINE
- ARM_KERNEL_STEP_ACTIVE
- ARM_KERNEL_STEP_NONE
- ARM_KERNEL_STEP_SUSPEND
- ARM_LDM
- ARM_LDM_IA
- ARM_LDRB_I
- ARM_LDRB_R
- ARM_LDRD_I
- ARM_LDRH_I
- ARM_LDRH_R
- ARM_LDR_I
- ARM_LDR_R
- ARM_LDR_R_SI
- ARM_LE
- ARM_LPAE_BLOCK_SIZE
- ARM_LPAE_GRANULE
- ARM_LPAE_LVL_IDX
- ARM_LPAE_LVL_SHIFT
- ARM_LPAE_MAIR_ATTR_DEVICE
- ARM_LPAE_MAIR_ATTR_IDX_CACHE
- ARM_LPAE_MAIR_ATTR_IDX_DEV
- ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
- ARM_LPAE_MAIR_ATTR_IDX_NC
- ARM_LPAE_MAIR_ATTR_INC_OWBRWA
- ARM_LPAE_MAIR_ATTR_MASK
- ARM_LPAE_MAIR_ATTR_NC
- ARM_LPAE_MAIR_ATTR_SHIFT
- ARM_LPAE_MAIR_ATTR_WBRWA
- ARM_LPAE_MAX_ADDR_BITS
- ARM_LPAE_MAX_LEVELS
- ARM_LPAE_PAGES_PER_PGD
- ARM_LPAE_PGD_IDX
- ARM_LPAE_PTE_ADDR_MASK
- ARM_LPAE_PTE_AF
- ARM_LPAE_PTE_AP_RDONLY
- ARM_LPAE_PTE_AP_UNPRIV
- ARM_LPAE_PTE_ATTRINDX_SHIFT
- ARM_LPAE_PTE_ATTR_HI_MASK
- ARM_LPAE_PTE_ATTR_LO_MASK
- ARM_LPAE_PTE_ATTR_MASK
- ARM_LPAE_PTE_HAP_FAULT
- ARM_LPAE_PTE_HAP_READ
- ARM_LPAE_PTE_HAP_WRITE
- ARM_LPAE_PTE_MEMATTR_DEV
- ARM_LPAE_PTE_MEMATTR_NC
- ARM_LPAE_PTE_MEMATTR_OIWB
- ARM_LPAE_PTE_NS
- ARM_LPAE_PTE_NSTABLE
- ARM_LPAE_PTE_SH_IS
- ARM_LPAE_PTE_SH_NS
- ARM_LPAE_PTE_SH_OS
- ARM_LPAE_PTE_SW_SYNC
- ARM_LPAE_PTE_TYPE_BLOCK
- ARM_LPAE_PTE_TYPE_MASK
- ARM_LPAE_PTE_TYPE_PAGE
- ARM_LPAE_PTE_TYPE_SHIFT
- ARM_LPAE_PTE_TYPE_TABLE
- ARM_LPAE_PTE_VALID
- ARM_LPAE_PTE_XN
- ARM_LPAE_PTE_nG
- ARM_LPAE_S2_MAX_CONCAT_PAGES
- ARM_LPAE_START_LVL
- ARM_LPAE_TCR_EPD1
- ARM_LPAE_TCR_IPS_MASK
- ARM_LPAE_TCR_IPS_SHIFT
- ARM_LPAE_TCR_IRGN0_SHIFT
- ARM_LPAE_TCR_ORGN0_SHIFT
- ARM_LPAE_TCR_PS_32_BIT
- ARM_LPAE_TCR_PS_36_BIT
- ARM_LPAE_TCR_PS_40_BIT
- ARM_LPAE_TCR_PS_42_BIT
- ARM_LPAE_TCR_PS_44_BIT
- ARM_LPAE_TCR_PS_48_BIT
- ARM_LPAE_TCR_PS_52_BIT
- ARM_LPAE_TCR_PS_MASK
- ARM_LPAE_TCR_PS_SHIFT
- ARM_LPAE_TCR_RGN_MASK
- ARM_LPAE_TCR_RGN_NC
- ARM_LPAE_TCR_RGN_WB
- ARM_LPAE_TCR_RGN_WBWA
- ARM_LPAE_TCR_RGN_WT
- ARM_LPAE_TCR_SH0_MASK
- ARM_LPAE_TCR_SH0_SHIFT
- ARM_LPAE_TCR_SH_IS
- ARM_LPAE_TCR_SH_NS
- ARM_LPAE_TCR_SH_OS
- ARM_LPAE_TCR_SL0_MASK
- ARM_LPAE_TCR_SL0_SHIFT
- ARM_LPAE_TCR_SZ_MASK
- ARM_LPAE_TCR_T0SZ_SHIFT
- ARM_LPAE_TCR_TG0_16K
- ARM_LPAE_TCR_TG0_4K
- ARM_LPAE_TCR_TG0_64K
- ARM_LR
- ARM_LSL_I
- ARM_LSL_R
- ARM_LSR_I
- ARM_LSR_R
- ARM_Lock
- ARM_MALI_LPAE
- ARM_MALI_LPAE_MEMATTR_IMP_DEF
- ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
- ARM_MALI_LPAE_TTBR_ADRMODE_TABLE
- ARM_MALI_LPAE_TTBR_READ_INNER
- ARM_MALI_LPAE_TTBR_SHARE_OUTER
- ARM_MAX_BRP
- ARM_MAX_FREQ100OPP
- ARM_MAX_HBP_SLOTS
- ARM_MAX_OPP
- ARM_MAX_WRP
- ARM_MC_IHAVEDATAIRQEN
- ARM_MLS
- ARM_MMU500
- ARM_MMU500_ACR_CACHE_LOCK
- ARM_MMU500_ACR_S2CRB_TLBEN
- ARM_MMU500_ACR_SMTNMB_TLBEN
- ARM_MMU500_ACTLR_CPRE
- ARM_MMU_DISCARD
- ARM_MMU_KEEP
- ARM_MOD_BODY
- ARM_MOVS_R
- ARM_MOVT
- ARM_MOVW
- ARM_MOV_I
- ARM_MOV_R
- ARM_MOV_SI
- ARM_MOV_SR
- ARM_MS_EMPTY
- ARM_MS_FULL
- ARM_MUL
- ARM_NEON_L2
- ARM_NO_CHANGE
- ARM_OK
- ARM_OP2_BCR
- ARM_OP2_BVR
- ARM_OP2_WCR
- ARM_OP2_WVR
- ARM_OPCODE_CONDITION_UNCOND
- ARM_OPCODE_CONDTEST_FAIL
- ARM_OPCODE_CONDTEST_PASS
- ARM_OPCODE_CONDTEST_UNCOND
- ARM_OPP_INIT
- ARM_ORIG_r0
- ARM_ORRS_R
- ARM_ORRS_SI
- ARM_ORRS_SR
- ARM_ORR_I
- ARM_ORR_R
- ARM_ORR_SI
- ARM_ORR_SR
- ARM_OSLSR_OSLM0
- ARM_PACKET_SIZE
- ARM_PC
- ARM_PLAT_SCHED_CLOCK_H
- ARM_PLL
- ARM_PLL_FID_CH0_SLOW_CLK
- ARM_PLL_FID_CH1_FAST_CLK
- ARM_PLL_FID_CRYSTAL_CLK
- ARM_PLL_FID_SYS_CLK
- ARM_PMU_PROBE
- ARM_PMU_XSCALE_MASK
- ARM_POP
- ARM_PUSH
- ARM_PWR_CONTROL
- ARM_PWR_CONTROL_BASE
- ARM_R0
- ARM_R1
- ARM_R10
- ARM_R2
- ARM_R3
- ARM_R4
- ARM_R5
- ARM_R6
- ARM_R7
- ARM_R8
- ARM_R9
- ARM_REG_PC
- ARM_RESET_REGISTER
- ARM_RESTORE
- ARM_REV
- ARM_REV16
- ARM_RSBS_I
- ARM_RSB_I
- ARM_RSB_R
- ARM_RSC_I
- ARM_RSTCT1
- ARM_RSTCT2
- ARM_ResetMailBox
- ARM_SAVE
- ARM_SBCS_R
- ARM_SBC_I
- ARM_SBC_R
- ARM_SEC_CORE
- ARM_SEC_DEVEXIT
- ARM_SEC_DEVINIT
- ARM_SEC_EXIT
- ARM_SEC_HOT
- ARM_SEC_INIT
- ARM_SEC_MAX
- ARM_SEC_UNLIKELY
- ARM_SERROR_PENDING
- ARM_SETDPLL
- ARM_SHOW
- ARM_SLEEP_SAVE_ARM_CKCTL
- ARM_SLEEP_SAVE_ARM_EWUPCT
- ARM_SLEEP_SAVE_ARM_IDLECT1
- ARM_SLEEP_SAVE_ARM_IDLECT2
- ARM_SLEEP_SAVE_ARM_IDLECT3
- ARM_SLEEP_SAVE_ARM_RSTCT1
- ARM_SLEEP_SAVE_ARM_RSTCT2
- ARM_SLEEP_SAVE_ARM_SYSST
- ARM_SLEEP_SAVE_SIZE
- ARM_SLEEP_SAVE_START
- ARM_SMCCC_ARCH_FEATURES_FUNC_ID
- ARM_SMCCC_ARCH_WORKAROUND_1
- ARM_SMCCC_ARCH_WORKAROUND_2
- ARM_SMCCC_CALL_CONV_SHIFT
- ARM_SMCCC_CALL_VAL
- ARM_SMCCC_FAST_CALL
- ARM_SMCCC_FUNC_MASK
- ARM_SMCCC_FUNC_NUM
- ARM_SMCCC_IS_64
- ARM_SMCCC_IS_FAST_CALL
- ARM_SMCCC_OWNER_ARCH
- ARM_SMCCC_OWNER_CPU
- ARM_SMCCC_OWNER_MASK
- ARM_SMCCC_OWNER_NUM
- ARM_SMCCC_OWNER_OEM
- ARM_SMCCC_OWNER_SHIFT
- ARM_SMCCC_OWNER_SIP
- ARM_SMCCC_OWNER_STANDARD
- ARM_SMCCC_OWNER_TRUSTED_APP
- ARM_SMCCC_OWNER_TRUSTED_APP_END
- ARM_SMCCC_OWNER_TRUSTED_OS
- ARM_SMCCC_OWNER_TRUSTED_OS_END
- ARM_SMCCC_QUIRK_NONE
- ARM_SMCCC_QUIRK_QCOM_A6
- ARM_SMCCC_SMC_32
- ARM_SMCCC_SMC_64
- ARM_SMCCC_STD_CALL
- ARM_SMCCC_TYPE_SHIFT
- ARM_SMCCC_VERSION_1_0
- ARM_SMCCC_VERSION_1_1
- ARM_SMCCC_VERSION_FUNC_ID
- ARM_SMMU_CB
- ARM_SMMU_CB_ACTLR
- ARM_SMMU_CB_ATS1PR
- ARM_SMMU_CB_ATSR
- ARM_SMMU_CB_CONTEXTIDR
- ARM_SMMU_CB_FAR
- ARM_SMMU_CB_FSR
- ARM_SMMU_CB_FSYNR0
- ARM_SMMU_CB_PAR
- ARM_SMMU_CB_RESUME
- ARM_SMMU_CB_S1_MAIR0
- ARM_SMMU_CB_S1_MAIR1
- ARM_SMMU_CB_S1_TLBIASID
- ARM_SMMU_CB_S1_TLBIVA
- ARM_SMMU_CB_S1_TLBIVAL
- ARM_SMMU_CB_S2_TLBIIPAS2
- ARM_SMMU_CB_S2_TLBIIPAS2L
- ARM_SMMU_CB_SCTLR
- ARM_SMMU_CB_TCR
- ARM_SMMU_CB_TCR2
- ARM_SMMU_CB_TLBSTATUS
- ARM_SMMU_CB_TLBSYNC
- ARM_SMMU_CB_TTBR0
- ARM_SMMU_CB_TTBR1
- ARM_SMMU_CMDQ_BASE
- ARM_SMMU_CMDQ_CONS
- ARM_SMMU_CMDQ_PROD
- ARM_SMMU_CR0
- ARM_SMMU_CR0ACK
- ARM_SMMU_CR1
- ARM_SMMU_CR2
- ARM_SMMU_CTX_FMT_AARCH32_L
- ARM_SMMU_CTX_FMT_AARCH32_S
- ARM_SMMU_CTX_FMT_AARCH64
- ARM_SMMU_CTX_FMT_NONE
- ARM_SMMU_DOMAIN_BYPASS
- ARM_SMMU_DOMAIN_NESTED
- ARM_SMMU_DOMAIN_S1
- ARM_SMMU_DOMAIN_S2
- ARM_SMMU_EVTQ_BASE
- ARM_SMMU_EVTQ_CONS
- ARM_SMMU_EVTQ_IRQ_CFG0
- ARM_SMMU_EVTQ_IRQ_CFG1
- ARM_SMMU_EVTQ_IRQ_CFG2
- ARM_SMMU_EVTQ_PROD
- ARM_SMMU_FEAT_2_LVL_CDTAB
- ARM_SMMU_FEAT_2_LVL_STRTAB
- ARM_SMMU_FEAT_ATS
- ARM_SMMU_FEAT_COHERENCY
- ARM_SMMU_FEAT_COHERENT_WALK
- ARM_SMMU_FEAT_EXIDS
- ARM_SMMU_FEAT_FMT_AARCH32_L
- ARM_SMMU_FEAT_FMT_AARCH32_S
- ARM_SMMU_FEAT_FMT_AARCH64_16K
- ARM_SMMU_FEAT_FMT_AARCH64_4K
- ARM_SMMU_FEAT_FMT_AARCH64_64K
- ARM_SMMU_FEAT_HYP
- ARM_SMMU_FEAT_MSI
- ARM_SMMU_FEAT_PRI
- ARM_SMMU_FEAT_SEV
- ARM_SMMU_FEAT_STALLS
- ARM_SMMU_FEAT_STALL_FORCE
- ARM_SMMU_FEAT_STREAM_MATCH
- ARM_SMMU_FEAT_TRANS_NESTED
- ARM_SMMU_FEAT_TRANS_OPS
- ARM_SMMU_FEAT_TRANS_S1
- ARM_SMMU_FEAT_TRANS_S2
- ARM_SMMU_FEAT_TT_BE
- ARM_SMMU_FEAT_TT_LE
- ARM_SMMU_FEAT_VAX
- ARM_SMMU_FEAT_VMID16
- ARM_SMMU_GBPA
- ARM_SMMU_GERROR
- ARM_SMMU_GERRORN
- ARM_SMMU_GERROR_IRQ_CFG0
- ARM_SMMU_GERROR_IRQ_CFG1
- ARM_SMMU_GERROR_IRQ_CFG2
- ARM_SMMU_GR0
- ARM_SMMU_GR0_ID0
- ARM_SMMU_GR0_ID1
- ARM_SMMU_GR0_ID2
- ARM_SMMU_GR0_ID3
- ARM_SMMU_GR0_ID4
- ARM_SMMU_GR0_ID5
- ARM_SMMU_GR0_ID6
- ARM_SMMU_GR0_ID7
- ARM_SMMU_GR0_S2CR
- ARM_SMMU_GR0_SMR
- ARM_SMMU_GR0_TLBIALLH
- ARM_SMMU_GR0_TLBIALLNSNH
- ARM_SMMU_GR0_TLBIVMID
- ARM_SMMU_GR0_sACR
- ARM_SMMU_GR0_sCR0
- ARM_SMMU_GR0_sGFSR
- ARM_SMMU_GR0_sGFSYNR0
- ARM_SMMU_GR0_sGFSYNR1
- ARM_SMMU_GR0_sGFSYNR2
- ARM_SMMU_GR0_sTLBGSTATUS
- ARM_SMMU_GR0_sTLBGSYNC
- ARM_SMMU_GR1
- ARM_SMMU_GR1_CBA2R
- ARM_SMMU_GR1_CBAR
- ARM_SMMU_GR1_CBFRSYNRA
- ARM_SMMU_IDR0
- ARM_SMMU_IDR1
- ARM_SMMU_IDR5
- ARM_SMMU_IRQ_CTRL
- ARM_SMMU_IRQ_CTRLACK
- ARM_SMMU_MATCH_DATA
- ARM_SMMU_MAX_ASIDS
- ARM_SMMU_MAX_CBS
- ARM_SMMU_MAX_MSIS
- ARM_SMMU_MAX_VMIDS
- ARM_SMMU_MEMATTR_DEVICE_nGnRE
- ARM_SMMU_MEMATTR_OIWB
- ARM_SMMU_OPT_PAGE0_REGS_ONLY
- ARM_SMMU_OPT_SKIP_PREFETCH
- ARM_SMMU_POLL_SPIN_COUNT
- ARM_SMMU_POLL_TIMEOUT_US
- ARM_SMMU_PRIQ_BASE
- ARM_SMMU_PRIQ_CONS
- ARM_SMMU_PRIQ_IRQ_CFG0
- ARM_SMMU_PRIQ_IRQ_CFG1
- ARM_SMMU_PRIQ_IRQ_CFG2
- ARM_SMMU_PRIQ_PROD
- ARM_SMMU_SH_ISH
- ARM_SMMU_SH_NSH
- ARM_SMMU_SH_OSH
- ARM_SMMU_STRTAB_BASE
- ARM_SMMU_STRTAB_BASE_CFG
- ARM_SMMU_TCR2CD
- ARM_SMMU_V1
- ARM_SMMU_V1_64K
- ARM_SMMU_V2
- ARM_SP
- ARM_SPE_ADDRESS
- ARM_SPE_AUXTRACE_PRIV_MAX
- ARM_SPE_AUXTRACE_PRIV_SIZE
- ARM_SPE_BAD
- ARM_SPE_BAD_PACKET
- ARM_SPE_BUF_PAD_BYTE
- ARM_SPE_CONTEXT
- ARM_SPE_COUNTER
- ARM_SPE_DATA_SOURCE
- ARM_SPE_END
- ARM_SPE_EVENTS
- ARM_SPE_NEED_MORE_BYTES
- ARM_SPE_OP_TYPE
- ARM_SPE_PAD
- ARM_SPE_PER_CPU_MMAPS
- ARM_SPE_PKT_DESC_MAX
- ARM_SPE_PMU_NAME
- ARM_SPE_PMU_TYPE
- ARM_SPE_TIMESTAMP
- ARM_STRB_I
- ARM_STRD_I
- ARM_STRH_I
- ARM_STR_I
- ARM_SUBS_I
- ARM_SUBS_R
- ARM_SUB_I
- ARM_SUB_R
- ARM_SYSST
- ARM_SYSST_ARM_WDRST_SHIFT
- ARM_SYSST_EXT_RST_SHIFT
- ARM_SYSST_GLOB_SWRST_SHIFT
- ARM_SYSST_POR_SHIFT
- ARM_TCM
- ARM_TEXT
- ARM_TRACECLK_MARK
- ARM_TRACECTL_MARK
- ARM_TRACEDATA_0_MARK
- ARM_TRACEDATA_10_MARK
- ARM_TRACEDATA_11_MARK
- ARM_TRACEDATA_12_MARK
- ARM_TRACEDATA_13_MARK
- ARM_TRACEDATA_14_MARK
- ARM_TRACEDATA_15_MARK
- ARM_TRACEDATA_1_MARK
- ARM_TRACEDATA_2_MARK
- ARM_TRACEDATA_3_MARK
- ARM_TRACEDATA_4_MARK
- ARM_TRACEDATA_5_MARK
- ARM_TRACEDATA_6_MARK
- ARM_TRACEDATA_7_MARK
- ARM_TRACEDATA_8_MARK
- ARM_TRACEDATA_9_MARK
- ARM_TRACE_MASK
- ARM_TRANSFER
- ARM_TST_I
- ARM_TST_R
- ARM_UDIV
- ARM_UMULL
- ARM_UNWIND_SECTIONS
- ARM_UX500_PM_H
- ARM_UXTH
- ARM_V7S
- ARM_V7S_ADDR_BITS
- ARM_V7S_ATTR_AP0
- ARM_V7S_ATTR_AP1
- ARM_V7S_ATTR_AP2
- ARM_V7S_ATTR_B
- ARM_V7S_ATTR_C
- ARM_V7S_ATTR_MASK
- ARM_V7S_ATTR_MTK_PA_BIT32
- ARM_V7S_ATTR_MTK_PA_BIT33
- ARM_V7S_ATTR_NG
- ARM_V7S_ATTR_NS_SECTION
- ARM_V7S_ATTR_NS_TABLE
- ARM_V7S_ATTR_S
- ARM_V7S_ATTR_SHIFT
- ARM_V7S_ATTR_TEX
- ARM_V7S_ATTR_XN
- ARM_V7S_BLOCK_SIZE
- ARM_V7S_CONT_PAGES
- ARM_V7S_CONT_PAGE_TEX_MASK
- ARM_V7S_CONT_PAGE_TEX_SHIFT
- ARM_V7S_CONT_PAGE_XN_SHIFT
- ARM_V7S_CONT_SECTION
- ARM_V7S_LVL_IDX
- ARM_V7S_LVL_MASK
- ARM_V7S_LVL_SHIFT
- ARM_V7S_NMRR_IR
- ARM_V7S_NMRR_OR
- ARM_V7S_PRRR_DS0
- ARM_V7S_PRRR_DS1
- ARM_V7S_PRRR_NOS
- ARM_V7S_PRRR_NS0
- ARM_V7S_PRRR_NS1
- ARM_V7S_PRRR_TR
- ARM_V7S_PRRR_TYPE_DEVICE
- ARM_V7S_PRRR_TYPE_NORMAL
- ARM_V7S_PTES_PER_LVL
- ARM_V7S_PTE_AF
- ARM_V7S_PTE_AP_RDONLY
- ARM_V7S_PTE_AP_UNPRIV
- ARM_V7S_PTE_IS_TABLE
- ARM_V7S_PTE_IS_VALID
- ARM_V7S_PTE_TYPE_CONT_PAGE
- ARM_V7S_PTE_TYPE_PAGE
- ARM_V7S_PTE_TYPE_TABLE
- ARM_V7S_RGN_NC
- ARM_V7S_RGN_WB
- ARM_V7S_RGN_WBWA
- ARM_V7S_RGN_WT
- ARM_V7S_TABLE_GFP_DMA
- ARM_V7S_TABLE_MASK
- ARM_V7S_TABLE_SHIFT
- ARM_V7S_TABLE_SIZE
- ARM_V7S_TABLE_SLAB_FLAGS
- ARM_V7S_TCR_PD1
- ARM_V7S_TEX_MASK
- ARM_V7S_TEX_SHIFT
- ARM_V7S_TTBR_IRGN_ATTR
- ARM_V7S_TTBR_NOS
- ARM_V7S_TTBR_ORGN_ATTR
- ARM_V7S_TTBR_S
- ARM_VECTORS
- ARM_VFPREGS_SIZE
- ARM_VIDEO_RANGE_FULL
- ARM_VIDEO_RANGE_LIMITED
- ARM_WAIT_DIV_396M
- ARM_WAIT_DIV_792M
- ARM_WAIT_DIV_996M
- ARM_WAIT_FREE
- ARM_WAIT_OSD
- ARM_WAIT_SHAKE
- ARM_WAKEUP_MODEM
- ARM_cpsr
- ARM_fp
- ARM_ip
- ARM_lr
- ARM_pc
- ARM_r0
- ARM_r1
- ARM_r10
- ARM_r2
- ARM_r3
- ARM_r4
- ARM_r5
- ARM_r6
- ARM_r7
- ARM_r8
- ARM_r9
- ARM_sp
- AROFFSET
- ARP2BREAK0
- ARP2BREAK1
- ARP2BREAK2
- ARP2BREAK3
- ARP2BREAKADR01
- ARP2BREAKADR23
- ARP2CIOPERR
- ARP2CTL
- ARP2HALTC
- ARP2HALTCODE
- ARP2ILLOPC
- ARP2INT
- ARP2INTCTL
- ARP2INTEN
- ARP2PERR
- ARP2RESET
- ARP2WAITTO
- ARPC_INVALID
- ARPC_IN_SIZE_MAX
- ARPC_NO_MEMORY
- ARPC_OUT_SIZE_MAX
- ARPC_SUCCESS
- ARPC_TIMEOUT
- ARPC_TYPE_CPORT_CLEAR
- ARPC_TYPE_CPORT_CONNECTED
- ARPC_TYPE_CPORT_FLUSH
- ARPC_TYPE_CPORT_QUIESCE
- ARPC_TYPE_CPORT_SHUTDOWN
- ARPC_UNKNOWN_ERROR
- ARPHRD_6LOWPAN
- ARPHRD_ADAPT
- ARPHRD_APPLETLK
- ARPHRD_ARCNET
- ARPHRD_ASH
- ARPHRD_ATM
- ARPHRD_AX25
- ARPHRD_BIF
- ARPHRD_CAIF
- ARPHRD_CAN
- ARPHRD_CHAOS
- ARPHRD_CISCO
- ARPHRD_CSLIP
- ARPHRD_CSLIP6
- ARPHRD_DDCMP
- ARPHRD_DLCI
- ARPHRD_ECONET
- ARPHRD_EETHER
- ARPHRD_ETHER
- ARPHRD_EUI64
- ARPHRD_FCAL
- ARPHRD_FCFABRIC
- ARPHRD_FCPL
- ARPHRD_FCPP
- ARPHRD_FDDI
- ARPHRD_FRAD
- ARPHRD_HDLC
- ARPHRD_HIPPI
- ARPHRD_HWX25
- ARPHRD_IEEE1394
- ARPHRD_IEEE802
- ARPHRD_IEEE80211
- ARPHRD_IEEE80211_PRISM
- ARPHRD_IEEE80211_RADIOTAP
- ARPHRD_IEEE802154
- ARPHRD_IEEE802154_MONITOR
- ARPHRD_IEEE802_TR
- ARPHRD_INFINIBAND
- ARPHRD_IP6GRE
- ARPHRD_IPDDP
- ARPHRD_IPGRE
- ARPHRD_IRDA
- ARPHRD_LAPB
- ARPHRD_LOCALTLK
- ARPHRD_LOOPBACK
- ARPHRD_METRICOM
- ARPHRD_MYTYPE
- ARPHRD_NETLINK
- ARPHRD_NETROM
- ARPHRD_NONE
- ARPHRD_PHONET
- ARPHRD_PHONET_PIPE
- ARPHRD_PIMREG
- ARPHRD_PPP
- ARPHRD_PRONET
- ARPHRD_RAWHDLC
- ARPHRD_RAWIP
- ARPHRD_ROSE
- ARPHRD_RSRVD
- ARPHRD_SIT
- ARPHRD_SKIP
- ARPHRD_SLIP
- ARPHRD_SLIP6
- ARPHRD_TUNNEL
- ARPHRD_TUNNEL6
- ARPHRD_VOID
- ARPHRD_VSOCKMON
- ARPHRD_X25
- ARPOL_MAX_ENTRIES
- ARPOP_InREPLY
- ARPOP_InREQUEST
- ARPOP_NAK
- ARPOP_REPLY
- ARPOP_REQUEST
- ARPOP_RREPLY
- ARPOP_RREQUEST
- ARPRESP_PG
- ARPT_BASE_CTL
- ARPT_CONTINUE
- ARPT_DEV_ADDR_LEN_MAX
- ARPT_ENTRY_INIT
- ARPT_ENTRY_ITERATE
- ARPT_ERROR_INIT
- ARPT_ERROR_TARGET
- ARPT_FUNCTION_MAXNAMELEN
- ARPT_F_MASK
- ARPT_INV_ARPHLN
- ARPT_INV_ARPHRD
- ARPT_INV_ARPOP
- ARPT_INV_ARPPRO
- ARPT_INV_MASK
- ARPT_INV_SRCDEVADDR
- ARPT_INV_SRCIP
- ARPT_INV_TGTDEVADDR
- ARPT_INV_TGTIP
- ARPT_INV_VIA_IN
- ARPT_INV_VIA_OUT
- ARPT_MANGLE_ADDR_LEN_MAX
- ARPT_MANGLE_MASK
- ARPT_MANGLE_SDEV
- ARPT_MANGLE_SIP
- ARPT_MANGLE_TDEV
- ARPT_MANGLE_TIP
- ARPT_RETURN
- ARPT_SO_GET_ENTRIES
- ARPT_SO_GET_INFO
- ARPT_SO_GET_MAX
- ARPT_SO_GET_REVISION_TARGET
- ARPT_SO_SET_ADD_COUNTERS
- ARPT_SO_SET_MAX
- ARPT_SO_SET_REPLACE
- ARPT_STANDARD_INIT
- ARPT_STANDARD_TARGET
- ARPT_TABLE_MAXNAMELEN
- ARP_FILTER_MAX_BUF_SIZE
- ARP_REQ_DELAY
- ARP_SPA
- ARP_TPA
- ARQB_CMD_MOVE
- ARQOS_ARCACHE_CFG
- ARRAY16_OPF
- ARRAY32_OPF
- ARRAY8_OPF
- ARRAYS_CASE
- ARRAYS_CASE_COMMON
- ARRAYS_DATA
- ARRAYS_ERR_CASE
- ARRAY_1D
- ARRAY_1D_TILED_THICK
- ARRAY_1D_TILED_THIN1
- ARRAY_2D
- ARRAY_2D_ALT_COLOR
- ARRAY_2D_ALT_DEPTH
- ARRAY_2D_COLOR
- ARRAY_2D_DEPTH
- ARRAY_2D_TILED_THICK
- ARRAY_2D_TILED_THIN1
- ARRAY_2D_TILED_XTHICK
- ARRAY_3D
- ARRAY_3D_SLICE
- ARRAY_3D_SLICE_COLOR
- ARRAY_3D_TILED_THICK
- ARRAY_3D_TILED_THIN1
- ARRAY_3D_TILED_XTHICK
- ARRAY_AND_SIZE
- ARRAY_CMD
- ARRAY_COLOR_TILE
- ARRAY_CREATE_FLAG_MASK
- ARRAY_DEPTH_TILE
- ARRAY_DRV_LIST
- ARRAY_DRV_LIST2
- ARRAY_END
- ARRAY_FULL
- ARRAY_INFO
- ARRAY_LABEL_LEN
- ARRAY_LEN
- ARRAY_LINEAR
- ARRAY_LINEAR_ALIGNED
- ARRAY_LINEAR_GENERAL
- ARRAY_LOOKUP
- ARRAY_MODE
- ARRAY_NO_EXIST
- ARRAY_PRT_2D_TILED_THICK
- ARRAY_PRT_2D_TILED_THIN1
- ARRAY_PRT_3D_TILED_THICK
- ARRAY_PRT_3D_TILED_THIN1
- ARRAY_PRT_TILED_THICK
- ARRAY_PRT_TILED_THIN1
- ARRAY_SIZE
- ARRAY_TILED
- ARRIA10
- ARROFFSET
- ARR_REG_RD
- ARR_REG_WR
- ARSR
- ARSR_GPR
- ARSR_HWR
- ARSR_LPMR
- ARSR_WDT
- ARSTR
- ARSTR_ARST
- ARSTR_BIT
- ARST_BUS_NIU
- ARST_DMAC
- ARST_DSP_EDAP_NIU
- ARST_DSP_EDP_NIU
- ARST_DSP_EDP_PERF
- ARST_DSP_EPP_NIU
- ARST_DSP_EPP_PERF
- ARST_GMAC
- ARST_IEP
- ARST_INTMEM
- ARST_ISP_NIU
- ARST_PERIPH_NIU
- ARST_RGA
- ARST_RKVDEC
- ARST_RKVDEC_NIU
- ARST_RKVENC
- ARST_RKVENC_NIU
- ARST_STRC_SYS_AD
- ARST_VIO0_NIU
- ARST_VIO1_NIU
- ARST_VIP0
- ARST_VIP1
- ARST_VIP2
- ARST_VIP3
- ARST_VOP
- ARST_VPU
- ARST_VPU_NIU
- ARS_BUSY
- ARS_CANCEL
- ARS_EXT_STATUS_SHIFT
- ARS_FAILED
- ARS_POLL
- ARS_REQ_LONG
- ARS_REQ_SHORT
- ARS_STATUS_MASK
- ARS_VALID
- ARTCSR0
- ARTCSR0_ACK_CTS_11MBS
- ARTCSR0_ACK_CTS_1MBS
- ARTCSR0_ACK_CTS_2MBS
- ARTCSR0_ACK_CTS_5_5MBS
- ARTCSR1
- ARTCSR1_ACK_CTS_12MBS
- ARTCSR1_ACK_CTS_18MBS
- ARTCSR1_ACK_CTS_6MBS
- ARTCSR1_ACK_CTS_9MBS
- ARTCSR2
- ARTCSR2_ACK_CTS_24MBS
- ARTCSR2_ACK_CTS_36MBS
- ARTCSR2_ACK_CTS_48MBS
- ARTCSR2_ACK_CTS_54MBS
- ARTIFICIAL_LIMIT
- ARTIM0
- ARTIM23
- ARTIST_CMAP0
- ARTIST_ENABLE_DISABLE_DISPLAY
- ARTPEC6
- ARTPEC6_CLK_CPU
- ARTPEC6_CLK_CPU_PERIPH
- ARTPEC6_CLK_DBG_PCLK
- ARTPEC6_CLK_DMA_ACLK
- ARTPEC6_CLK_ETH_ACLK
- ARTPEC6_CLK_FRACDIV_IN
- ARTPEC6_CLK_I2C
- ARTPEC6_CLK_I2S0_CLK
- ARTPEC6_CLK_I2S1_CLK
- ARTPEC6_CLK_I2S_HST
- ARTPEC6_CLK_NAND_CLKA
- ARTPEC6_CLK_NAND_CLKB
- ARTPEC6_CLK_NUMCLOCKS
- ARTPEC6_CLK_PTP_REF
- ARTPEC6_CLK_SD_IMCLK
- ARTPEC6_CLK_SD_PCLK
- ARTPEC6_CLK_SPI_PCLK
- ARTPEC6_CLK_SPI_SSPCLK
- ARTPEC6_CLK_SYS_TIMER
- ARTPEC6_CLK_UART_PCLK
- ARTPEC6_CLK_UART_REFCLK
- ARTPEC6_CONFIG_0
- ARTPEC6_CONFIG_1
- ARTPEC6_CONFIG_2
- ARTPEC6_CONFIG_3
- ARTPEC6_CRYPTO
- ARTPEC6_CRYPTO_CIPHER_AES_CBC
- ARTPEC6_CRYPTO_CIPHER_AES_CTR
- ARTPEC6_CRYPTO_CIPHER_AES_ECB
- ARTPEC6_CRYPTO_CIPHER_AES_XTS
- ARTPEC6_CRYPTO_HASH_SHA1
- ARTPEC6_CRYPTO_HASH_SHA256
- ARTPEC6_CRYPTO_PREPARE_HASH_NO_START
- ARTPEC6_CRYPTO_PREPARE_HASH_START
- ARTPEC6_DMACFG_REGNUM
- ARTPEC6_DMACFG_UARTS_BURST
- ARTPEC6_DRIVE_4mA
- ARTPEC6_DRIVE_4mA_SET
- ARTPEC6_DRIVE_6mA
- ARTPEC6_DRIVE_6mA_SET
- ARTPEC6_DRIVE_8mA
- ARTPEC6_DRIVE_8mA_SET
- ARTPEC6_DRIVE_9mA
- ARTPEC6_DRIVE_9mA_SET
- ARTPEC6_LAST_PIN
- ARTPEC6_MAX_MUXABLE
- ARTPEC6_PINMUX_DRV_MASK
- ARTPEC6_PINMUX_DRV_SHIFT
- ARTPEC6_PINMUX_SEL_MASK
- ARTPEC6_PINMUX_SEL_SHIFT
- ARTPEC6_PINMUX_UDC0_MASK
- ARTPEC6_PINMUX_UDC0_SHIFT
- ARTPEC6_PINMUX_UDC1_MASK
- ARTPEC6_PINMUX_UDC1_SHIFT
- ARTPEC7
- ARTPEC7_CRYPTO
- ARTPEC_CACHE_LINE_MAX
- ARTTIM0
- ARTTIM1
- ARTTIM23
- ARTTIM23_DIS_RA2
- ARTTIM23_DIS_RA3
- ARTTIM23_IDE23INTR
- ARTTIM23_INTR_CH1
- ART_CK
- ART_CPUID_LEAF
- ART_MASTER_PKGLEN_MAX
- ART_MIN_DENOMINATOR
- ARUBA_GB_ADDR_CONFIG_GOLDEN
- ARUBA_RLC_UCODE_SIZE
- ARUSER_M_CFG_ENABLE
- ARVO_COMMAND_ACTUAL_PROFILE
- ARVO_COMMAND_BUTTON
- ARVO_COMMAND_INFO
- ARVO_COMMAND_KEY_MASK
- ARVO_COMMAND_MODE_KEY
- ARVO_ROCCAT_REPORT_ACTION_PRESS
- ARVO_ROCCAT_REPORT_ACTION_RELEASE
- ARVO_SPECIAL_REPORT_EVENT_ACTION_PRESS
- ARVO_SPECIAL_REPORT_EVENT_ACTION_RELEASE
- ARVO_SPECIAL_REPORT_EVENT_MASK_ACTION
- ARVO_SPECIAL_REPORT_EVENT_MASK_BUTTON
- ARX
- ARXCTL_EN
- ARY
- AR_2040
- AR_2040_0
- AR_2040_1
- AR_2040_2
- AR_2040_3
- AR_2040_JOINED_RX_CLEAR
- AR_2040_MODE
- AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
- AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE
- AR_A
- AR_ACCESSED
- AR_ACK_FAIL
- AR_ADHOC_MCAST_KEYID_ENABLE
- AR_AES_MUTE_MASK0
- AR_AES_MUTE_MASK0_FC
- AR_AES_MUTE_MASK0_QOS
- AR_AES_MUTE_MASK0_QOS_S
- AR_AES_MUTE_MASK1
- AR_AES_MUTE_MASK1_FC_MGMT
- AR_AES_MUTE_MASK1_FC_MGMT_S
- AR_AES_MUTE_MASK1_SEQ
- AR_AES_MUTE_MASK1_SEQ_S
- AR_AGC1_BASE
- AR_AGC2_BASE
- AR_AGC3_BASE
- AR_AGC_BASE
- AR_AGG_WEP_ENABLE
- AR_AGG_WEP_ENABLE_FIX
- AR_AHB_BUF_WR_EN
- AR_AHB_CACHELINE_RD_EN
- AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
- AR_AHB_CUSTOM_BURST_EN
- AR_AHB_CUSTOM_BURST_EN_S
- AR_AHB_EXACT_RD_EN
- AR_AHB_EXACT_WR_EN
- AR_AHB_MODE
- AR_AHB_PAGE_SIZE_1K
- AR_AHB_PAGE_SIZE_2K
- AR_AHB_PAGE_SIZE_4K
- AR_AHB_PREFETCH_RD_EN
- AR_ANT_DIV_CTRL_ALL
- AR_ANT_DIV_CTRL_ALL_S
- AR_ANT_DIV_ENABLE
- AR_ANT_DIV_ENABLE_S
- AR_AN_RF2G1_CH0
- AR_AN_RF2G1_CH0_DB
- AR_AN_RF2G1_CH0_DB_S
- AR_AN_RF2G1_CH0_OB
- AR_AN_RF2G1_CH0_OB_S
- AR_AN_RF2G1_CH1
- AR_AN_RF2G1_CH1_DB
- AR_AN_RF2G1_CH1_DB_S
- AR_AN_RF2G1_CH1_OB
- AR_AN_RF2G1_CH1_OB_S
- AR_AN_RF5G1_CH0
- AR_AN_RF5G1_CH0_DB5
- AR_AN_RF5G1_CH0_DB5_S
- AR_AN_RF5G1_CH0_OB5
- AR_AN_RF5G1_CH0_OB5_S
- AR_AN_RF5G1_CH1
- AR_AN_RF5G1_CH1_DB5
- AR_AN_RF5G1_CH1_DB5_S
- AR_AN_RF5G1_CH1_OB5
- AR_AN_RF5G1_CH1_OB5_S
- AR_AN_SYNTH9
- AR_AN_SYNTH9_REFDIVA
- AR_AN_SYNTH9_REFDIVA_S
- AR_AN_TOP1
- AR_AN_TOP1_DACIPMODE
- AR_AN_TOP1_DACIPMODE_S
- AR_AN_TOP2
- AR_AN_TOP2_LOCALBIAS
- AR_AN_TOP2_LOCALBIAS_S
- AR_AN_TOP2_PWDCLKIND
- AR_AN_TOP2_PWDCLKIND_S
- AR_AN_TOP2_XPABIAS_LVL
- AR_AN_TOP2_XPABIAS_LVL_S
- AR_AVL
- AR_AggrLen
- AR_AggrLen_S
- AR_BASE_FREQ_2GHZ
- AR_BASE_FREQ_5GHZ
- AR_BBB_BASE
- AR_BCN_RSSI_AVE
- AR_BCN_RSSI_AVE_MASK
- AR_BEACON_CNT
- AR_BEACON_PERIOD
- AR_BSSMSKL
- AR_BSSMSKU
- AR_BSS_ID0
- AR_BSS_ID1
- AR_BSS_ID1_AID
- AR_BSS_ID1_AID_S
- AR_BSS_ID1_U16
- AR_BTCOEX_BT_WGHT
- AR_BTCOEX_BT_WGHT_S
- AR_BTCOEX_CTRL
- AR_BTCOEX_CTRL2
- AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE
- AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S
- AR_BTCOEX_CTRL2_GPIO_OBS_SEL
- AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S
- AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL
- AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S
- AR_BTCOEX_CTRL2_RX_DEWEIGHT
- AR_BTCOEX_CTRL2_RX_DEWEIGHT_S
- AR_BTCOEX_CTRL2_TXPWR_THRESH
- AR_BTCOEX_CTRL2_TXPWR_THRESH_S
- AR_BTCOEX_CTRL2_TX_CHAIN_MASK
- AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S
- AR_BTCOEX_CTRL3
- AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT
- AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S
- AR_BTCOEX_CTRL_1_CHAIN_ACK
- AR_BTCOEX_CTRL_1_CHAIN_ACK_S
- AR_BTCOEX_CTRL_1_CHAIN_BCN
- AR_BTCOEX_CTRL_1_CHAIN_BCN_S
- AR_BTCOEX_CTRL_AGGR_THRESH
- AR_BTCOEX_CTRL_AGGR_THRESH_S
- AR_BTCOEX_CTRL_AR9462_MODE
- AR_BTCOEX_CTRL_AR9462_MODE_S
- AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL
- AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S
- AR_BTCOEX_CTRL_LNA_SHARED
- AR_BTCOEX_CTRL_LNA_SHARED_S
- AR_BTCOEX_CTRL_MCI_MODE_EN
- AR_BTCOEX_CTRL_MCI_MODE_EN_S
- AR_BTCOEX_CTRL_NUM_ANTENNAS
- AR_BTCOEX_CTRL_NUM_ANTENNAS_S
- AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN
- AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S
- AR_BTCOEX_CTRL_PA_SHARED
- AR_BTCOEX_CTRL_PA_SHARED_S
- AR_BTCOEX_CTRL_REDUCE_TXPWR
- AR_BTCOEX_CTRL_REDUCE_TXPWR_S
- AR_BTCOEX_CTRL_RX_CHAIN_MASK
- AR_BTCOEX_CTRL_RX_CHAIN_MASK_S
- AR_BTCOEX_CTRL_SPDT_ENABLE
- AR_BTCOEX_CTRL_SPDT_ENABLE_10
- AR_BTCOEX_CTRL_SPDT_ENABLE_10_S
- AR_BTCOEX_CTRL_SPDT_ENABLE_S
- AR_BTCOEX_CTRL_SPDT_POLARITY
- AR_BTCOEX_CTRL_SPDT_POLARITY_S
- AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN
- AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S
- AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT
- AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S
- AR_BTCOEX_CTRL_WAIT_BA_MARGIN
- AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S
- AR_BTCOEX_CTRL_WBTIMER_EN
- AR_BTCOEX_CTRL_WBTIMER_EN_S
- AR_BTCOEX_DBG
- AR_BTCOEX_MAX_RFGAIN
- AR_BTCOEX_MAX_TXPWR
- AR_BTCOEX_RC
- AR_BTCOEX_RFGAIN_CTRL
- AR_BTCOEX_WBTIMER
- AR_BTCOEX_WL_LNA
- AR_BTCOEX_WL_LNADIV
- AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ
- AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S
- AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD
- AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S
- AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT
- AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S
- AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE
- AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S
- AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY
- AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S
- AR_BTCOEX_WL_LNADIV_FORCE_ON
- AR_BTCOEX_WL_LNADIV_FORCE_ON_S
- AR_BTCOEX_WL_LNADIV_MODE
- AR_BTCOEX_WL_LNADIV_MODE_OPTION
- AR_BTCOEX_WL_LNADIV_MODE_OPTION_S
- AR_BTCOEX_WL_LNADIV_MODE_S
- AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD
- AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S
- AR_BTCOEX_WL_LNA_TIMEOUT
- AR_BTCOEX_WL_LNA_TIMEOUT_S
- AR_BTCOEX_WL_WEIGHTS0
- AR_BTCOEX_WL_WEIGHTS1
- AR_BTCOEX_WL_WEIGHTS2
- AR_BTCOEX_WL_WEIGHTS3
- AR_BTCOEX_WL_WGHT
- AR_BTCOEX_WL_WGHT_S
- AR_BT_AGC_SATURATION_CNT_ENABLE
- AR_BT_AGC_SATURATION_CNT_ENABLE_S
- AR_BT_ALLOW_CONCURRENT_ACCESS
- AR_BT_ALLOW_CONCURRENT_ACCESS_S
- AR_BT_BCN_MISS_CNT
- AR_BT_BCN_MISS_CNT_S
- AR_BT_BCN_MISS_THRESH
- AR_BT_BCN_MISS_THRESH_S
- AR_BT_COEX_BT_WEIGHTS
- AR_BT_COEX_MODE
- AR_BT_COEX_MODE2
- AR_BT_COEX_MODE3
- AR_BT_COEX_WEIGHT
- AR_BT_COEX_WGHT
- AR_BT_COEX_WL_WEIGHTS0
- AR_BT_COEX_WL_WEIGHTS1
- AR_BT_DISABLE_BT_ANT
- AR_BT_DISABLE_BT_ANT_S
- AR_BT_FIRST_SLOT_TIME
- AR_BT_FIRST_SLOT_TIME_S
- AR_BT_HOLD_RX_CLEAR
- AR_BT_HOLD_RX_CLEAR_S
- AR_BT_INTERRUPT_ENABLE
- AR_BT_INTERRUPT_ENABLE_S
- AR_BT_MODE
- AR_BT_MODE_S
- AR_BT_PHY_ERR_BT_COLL_ENABLE
- AR_BT_PHY_ERR_BT_COLL_ENABLE_S
- AR_BT_PRIORITY_TIME
- AR_BT_PRIORITY_TIME_S
- AR_BT_PROTECT_BT_AFTER_WAKEUP
- AR_BT_PROTECT_BT_AFTER_WAKEUP_S
- AR_BT_QCU_THRESH
- AR_BT_QCU_THRESH_S
- AR_BT_QUIET
- AR_BT_QUIET_2_WIRE
- AR_BT_QUIET_2_WIRE_S
- AR_BT_QUIET_S
- AR_BT_RS_DISCARD_EXTEND
- AR_BT_RS_DISCARD_EXTEND_S
- AR_BT_RX_CLEAR_POLARITY
- AR_BT_RX_CLEAR_POLARITY_S
- AR_BT_TIME_EXTEND
- AR_BT_TIME_EXTEND_S
- AR_BT_TSF_BT_ACTIVE_CTRL
- AR_BT_TSF_BT_ACTIVE_CTRL_S
- AR_BT_TSF_BT_PRIORITY_CTRL
- AR_BT_TSF_BT_PRIORITY_CTRL_S
- AR_BT_TXSTATE_EXTEND
- AR_BT_TXSTATE_EXTEND_S
- AR_BT_TX_FRAME_EXTEND
- AR_BT_TX_FRAME_EXTEND_S
- AR_BT_WL_ACTIVE_MODE
- AR_BT_WL_ACTIVE_MODE_S
- AR_BT_WL_ACTIVE_TIME
- AR_BT_WL_ACTIVE_TIME_S
- AR_BT_WL_QC_TIME
- AR_BT_WL_QC_TIME_S
- AR_BT_WL_TXRX_SEPARATE
- AR_BT_WL_TXRX_SEPARATE_S
- AR_BUFFERS
- AR_BUFFERS_MIN
- AR_BUFFER_SIZE
- AR_BaBitmapHigh
- AR_BaBitmapLow
- AR_BufLen
- AR_BufLen_S
- AR_BurstDur
- AR_BurstDur_S
- AR_CCCNT
- AR_CFG
- AR_CFG_AP_ADHOC_INDICATION
- AR_CFG_CLK_GATE_DIS
- AR_CFG_EEBS
- AR_CFG_HALT_ACK
- AR_CFG_HALT_REQ
- AR_CFG_LED
- AR_CFG_LED_ASSOC_ACTIVE
- AR_CFG_LED_ASSOC_CTL
- AR_CFG_LED_ASSOC_CTL_S
- AR_CFG_LED_ASSOC_NONE
- AR_CFG_LED_ASSOC_PENDING
- AR_CFG_LED_BLINK_SLOW
- AR_CFG_LED_BLINK_SLOW_S
- AR_CFG_LED_BLINK_THRESH_SEL
- AR_CFG_LED_BLINK_THRESH_SEL_S
- AR_CFG_LED_MODE_NETWORK_OFF
- AR_CFG_LED_MODE_NETWORK_ON
- AR_CFG_LED_MODE_POWER_OFF
- AR_CFG_LED_MODE_POWER_ON
- AR_CFG_LED_MODE_PROP
- AR_CFG_LED_MODE_RAND
- AR_CFG_LED_MODE_RPROP
- AR_CFG_LED_MODE_SEL
- AR_CFG_LED_MODE_SEL_S
- AR_CFG_LED_MODE_SPLIT
- AR_CFG_LED_NETWORK
- AR_CFG_LED_NETWORK_S
- AR_CFG_LED_POWER
- AR_CFG_LED_POWER_S
- AR_CFG_PCI_MASTER_REQ_Q_THRESH
- AR_CFG_PCI_MASTER_REQ_Q_THRESH_S
- AR_CFG_PHOK
- AR_CFG_SCLK_1MHZ
- AR_CFG_SCLK_32KHZ
- AR_CFG_SCLK_32MHZ
- AR_CFG_SCLK_4MHZ
- AR_CFG_SCLK_RATE_IND
- AR_CFG_SCLK_RATE_IND_S
- AR_CFG_SWRB
- AR_CFG_SWRD
- AR_CFG_SWRG
- AR_CFG_SWTB
- AR_CFG_SWTD
- AR_CFP_VAL
- AR_CH0_BB_DPLL1
- AR_CH0_BB_DPLL1_NFRAC
- AR_CH0_BB_DPLL1_NFRAC_S
- AR_CH0_BB_DPLL1_NINI
- AR_CH0_BB_DPLL1_NINI_S
- AR_CH0_BB_DPLL1_REFDIV
- AR_CH0_BB_DPLL1_REFDIV_S
- AR_CH0_BB_DPLL2
- AR_CH0_BB_DPLL2_EN_NEGTRIG
- AR_CH0_BB_DPLL2_EN_NEGTRIG_S
- AR_CH0_BB_DPLL2_LOCAL_PLL
- AR_CH0_BB_DPLL2_LOCAL_PLL_S
- AR_CH0_BB_DPLL2_OUTDIV
- AR_CH0_BB_DPLL2_OUTDIV_S
- AR_CH0_BB_DPLL2_PLL_PWD
- AR_CH0_BB_DPLL2_PLL_PWD_S
- AR_CH0_BB_DPLL3
- AR_CH0_BB_DPLL3_PHASE_SHIFT
- AR_CH0_BB_DPLL3_PHASE_SHIFT_S
- AR_CH0_DDR_DPLL2
- AR_CH0_DDR_DPLL3
- AR_CH0_DPLL2_KD
- AR_CH0_DPLL2_KD_S
- AR_CH0_DPLL2_KI
- AR_CH0_DPLL2_KI_S
- AR_CH0_DPLL3_PHASE_SHIFT
- AR_CH0_DPLL3_PHASE_SHIFT_S
- AR_CH0_THERM
- AR_CH0_THERM_LOCAL
- AR_CH0_THERM_SAR_ADC_OUT
- AR_CH0_THERM_SAR_ADC_OUT_S
- AR_CH0_THERM_START
- AR_CH0_THERM_XPABIASLVL_MSB
- AR_CH0_THERM_XPABIASLVL_MSB_S
- AR_CH0_THERM_XPASHORT2GND
- AR_CH0_THERM_XPASHORT2GND_S
- AR_CH0_TOP
- AR_CH0_TOP2
- AR_CH0_TOP2_XPABIASLVL
- AR_CH0_TOP2_XPABIASLVL_S
- AR_CH0_TOP_XPABIASLVL
- AR_CH0_TOP_XPABIASLVL_S
- AR_CH0_XTAL
- AR_CH0_XTAL_CAPINDAC
- AR_CH0_XTAL_CAPINDAC_S
- AR_CH0_XTAL_CAPOUTDAC
- AR_CH0_XTAL_CAPOUTDAC_S
- AR_CHAN1_BASE
- AR_CHAN2_BASE
- AR_CHAN_BASE
- AR_CLASS
- AR_CLR_KA_INTERRUPT
- AR_CLR_MAC_INTERRUPT
- AR_CR
- AR_CRCErr
- AR_CR_RXD
- AR_CR_RXE
- AR_CR_SWI
- AR_CST
- AR_CST_TIMEOUT_COUNTER
- AR_CST_TIMEOUT_LIMIT
- AR_CST_TIMEOUT_LIMIT_S
- AR_CTSEnable
- AR_ChainSel0
- AR_ChainSel0_S
- AR_ChainSel1
- AR_ChainSel1_S
- AR_ChainSel2
- AR_ChainSel2_S
- AR_ChainSel3
- AR_ChainSel3_S
- AR_ClrDestMask
- AR_CorruptFCS
- AR_CtrlStat
- AR_CtrlStat_S
- AR_D0_CHNTIME
- AR_D0_LCL_IFS
- AR_D0_MISC
- AR_D0_QCUMASK
- AR_D0_RETRY_LIMIT
- AR_D1_CHNTIME
- AR_D1_LCL_IFS
- AR_D1_MISC
- AR_D1_QCUMASK
- AR_D1_RETRY_LIMIT
- AR_D2_CHNTIME
- AR_D2_LCL_IFS
- AR_D2_MISC
- AR_D2_QCUMASK
- AR_D2_RETRY_LIMIT
- AR_D3_CHNTIME
- AR_D3_LCL_IFS
- AR_D3_MISC
- AR_D3_QCUMASK
- AR_D3_RETRY_LIMIT
- AR_D4_CHNTIME
- AR_D4_LCL_IFS
- AR_D4_MISC
- AR_D4_QCUMASK
- AR_D4_RETRY_LIMIT
- AR_D5_CHNTIME
- AR_D5_LCL_IFS
- AR_D5_MISC
- AR_D5_QCUMASK
- AR_D5_RETRY_LIMIT
- AR_D6_CHNTIME
- AR_D6_LCL_IFS
- AR_D6_MISC
- AR_D6_QCUMASK
- AR_D6_RETRY_LIMIT
- AR_D7_CHNTIME
- AR_D7_LCL_IFS
- AR_D7_MISC
- AR_D7_QCUMASK
- AR_D7_RETRY_LIMIT
- AR_D8_CHNTIME
- AR_D8_LCL_IFS
- AR_D8_MISC
- AR_D8_QCUMASK
- AR_D8_RETRY_LIMIT
- AR_D9_CHNTIME
- AR_D9_LCL_IFS
- AR_D9_MISC
- AR_D9_QCUMASK
- AR_D9_RETRY_LIMIT
- AR_DATABUF_SIZE
- AR_DATABUF_SIZE_MASK
- AR_DB
- AR_DBA_TIMER_EN
- AR_DCHNTIME
- AR_DCU_0
- AR_DCU_1
- AR_DCU_2
- AR_DCU_3
- AR_DCU_4
- AR_DCU_5
- AR_DCU_6
- AR_DCU_7
- AR_DCU_8
- AR_DCU_9
- AR_DC_AP_STA_EN
- AR_DC_TSF2_ENABLE
- AR_DEF_ANTENNA
- AR_DEVID_7010
- AR_DIAG_ACK_DIS
- AR_DIAG_CACHE_ACK
- AR_DIAG_CHAN_INFO
- AR_DIAG_CORR_FCS
- AR_DIAG_CTS_DIS
- AR_DIAG_DECRYPT_DIS
- AR_DIAG_DUAL_CHAIN_INFO
- AR_DIAG_EIFS_CTRL_ENA
- AR_DIAG_ENCRYPT_DIS
- AR_DIAG_FORCE_CH_IDLE_HIGH
- AR_DIAG_FORCE_RX_CLEAR
- AR_DIAG_FRAME_NV0
- AR_DIAG_IGNORE_VIRT_CS
- AR_DIAG_LOOP_BACK
- AR_DIAG_OBS_PT_SEL1
- AR_DIAG_OBS_PT_SEL1_S
- AR_DIAG_OBS_PT_SEL2
- AR_DIAG_OBS_PT_SEL2_S
- AR_DIAG_RX_ABORT
- AR_DIAG_RX_CLEAR_CTL_LOW
- AR_DIAG_RX_CLEAR_EXT_LOW
- AR_DIAG_RX_DIS
- AR_DIAG_SATURATE_CYCLE_CNT
- AR_DIAG_SCRAM_SEED
- AR_DIAG_SCRAM_SEED_S
- AR_DIAG_SW
- AR_DIRECT_CONNECT
- AR_DLCL_IFS
- AR_DMADBG_0
- AR_DMADBG_1
- AR_DMADBG_2
- AR_DMADBG_3
- AR_DMADBG_4
- AR_DMADBG_5
- AR_DMADBG_6
- AR_DMADBG_7
- AR_DMASIZE_128B
- AR_DMASIZE_16B
- AR_DMASIZE_256B
- AR_DMASIZE_32B
- AR_DMASIZE_4B
- AR_DMASIZE_512B
- AR_DMASIZE_64B
- AR_DMASIZE_8B
- AR_DMA_BEACON_PERIOD
- AR_DMISC
- AR_DPL0
- AR_DPL3
- AR_DPL_MASK
- AR_DQCUMASK
- AR_DRETRY_LIMIT
- AR_DTIM_PERIOD
- AR_DTIM_TIMER_EN
- AR_D_CHNTIME_DUR
- AR_D_CHNTIME_DUR_S
- AR_D_CHNTIME_EN
- AR_D_CHNTIME_RESV0
- AR_D_FPCTL
- AR_D_FPCTL_BURST_PREFETCH
- AR_D_FPCTL_BURST_PREFETCH_S
- AR_D_FPCTL_DCU
- AR_D_FPCTL_DCU_S
- AR_D_FPCTL_PREFETCH_EN
- AR_D_GBL_IFS_EIFS
- AR_D_GBL_IFS_EIFS_ASYNC_FIFO
- AR_D_GBL_IFS_EIFS_M
- AR_D_GBL_IFS_EIFS_RESV0
- AR_D_GBL_IFS_MISC
- AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY
- AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND
- AR_D_GBL_IFS_MISC_IGNORE_BACKOFF
- AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL
- AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS
- AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN
- AR_D_GBL_IFS_MISC_TURBO_MODE
- AR_D_GBL_IFS_MISC_USEC_DURATION
- AR_D_GBL_IFS_SIFS
- AR_D_GBL_IFS_SIFS_M
- AR_D_GBL_IFS_SIFS_RESV0
- AR_D_GBL_IFS_SLOT
- AR_D_GBL_IFS_SLOT_M
- AR_D_GBL_IFS_SLOT_RESV0
- AR_D_LCL_IFS_AIFS
- AR_D_LCL_IFS_AIFS_S
- AR_D_LCL_IFS_CWMAX
- AR_D_LCL_IFS_CWMAX_S
- AR_D_LCL_IFS_CWMIN
- AR_D_LCL_IFS_CWMIN_S
- AR_D_LCL_IFS_RESV0
- AR_D_MISC_ARB_LOCKOUT_CNTRL
- AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
- AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR
- AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE
- AR_D_MISC_ARB_LOCKOUT_CNTRL_S
- AR_D_MISC_ARB_LOCKOUT_IGNORE
- AR_D_MISC_BEACON_USE
- AR_D_MISC_BKOFF_THRESH
- AR_D_MISC_BLOWN_IFS_RETRY_EN
- AR_D_MISC_CW_BKOFF_EN
- AR_D_MISC_CW_RESET_EN
- AR_D_MISC_FRAG_BKOFF_EN
- AR_D_MISC_FRAG_WAIT_EN
- AR_D_MISC_POST_FR_BKOFF_DIS
- AR_D_MISC_RESV0
- AR_D_MISC_RETRY_CNT_RESET_EN
- AR_D_MISC_SEQ_NUM_INCR_DIS
- AR_D_MISC_VIR_COL_HANDLING
- AR_D_MISC_VIR_COL_HANDLING_DEFAULT
- AR_D_MISC_VIR_COL_HANDLING_IGNORE
- AR_D_MISC_VIR_COL_HANDLING_S
- AR_D_MISC_VIT_COL_CW_BKOFF_EN
- AR_D_QCUMASK
- AR_D_QCUMASK_RESV0
- AR_D_RETRY_LIMIT_FR_SH
- AR_D_RETRY_LIMIT_FR_SH_S
- AR_D_RETRY_LIMIT_RESV0
- AR_D_RETRY_LIMIT_STA_LG
- AR_D_RETRY_LIMIT_STA_LG_S
- AR_D_RETRY_LIMIT_STA_SH
- AR_D_RETRY_LIMIT_STA_SH_S
- AR_D_SEQNUM
- AR_D_TXBLK_BASE
- AR_D_TXBLK_WRITE_BITMASK
- AR_D_TXBLK_WRITE_BITMASK_S
- AR_D_TXBLK_WRITE_COMMAND
- AR_D_TXBLK_WRITE_COMMAND_S
- AR_D_TXBLK_WRITE_DCU
- AR_D_TXBLK_WRITE_DCU_S
- AR_D_TXBLK_WRITE_SLICE
- AR_D_TXBLK_WRITE_SLICE_S
- AR_D_TXPSE
- AR_D_TXPSE_CTRL
- AR_D_TXPSE_RESV0
- AR_D_TXPSE_RESV1
- AR_D_TXPSE_STATUS
- AR_D_TXSLOTMASK
- AR_D_TXSLOTMASK_NUM
- AR_DataFailCnt
- AR_DataFailCnt_S
- AR_DataLen
- AR_DecryptBusyErr
- AR_DecryptCRCErr
- AR_DescCfgErr
- AR_DescId
- AR_DescId_S
- AR_DestIdx
- AR_DestIdxValid
- AR_DestIdx_S
- AR_DurUpdateEna
- AR_EEPROM
- AR_EEPROM_ABSENT
- AR_EEPROM_CORRUPT
- AR_EEPROM_EEPCAP_AES_DIS
- AR_EEPROM_EEPCAP_BURST_DIS
- AR_EEPROM_EEPCAP_COMPRESS_DIS
- AR_EEPROM_EEPCAP_FASTFRAME_DIS
- AR_EEPROM_EEPCAP_HEAVY_CLIP_EN
- AR_EEPROM_EEPCAP_KC_ENTRIES
- AR_EEPROM_EEPCAP_KC_ENTRIES_S
- AR_EEPROM_EEPCAP_MAXQCU
- AR_EEPROM_EEPCAP_MAXQCU_S
- AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
- AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
- AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
- AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0
- AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
- AR_EEPROM_EEREGCAP_EN_KK_U1_ODD
- AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0
- AR_EEPROM_EEREGCAP_EN_KK_U2
- AR_EEPROM_MODAL_SPURS
- AR_EEPROM_PROT_MASK
- AR_EEPROM_PROT_MASK_S
- AR_EEPROM_STATUS_DATA
- AR_EEPROM_STATUS_DATA_ABSENT_ACCESS
- AR_EEPROM_STATUS_DATA_BUSY
- AR_EEPROM_STATUS_DATA_BUSY_ACCESS
- AR_EEPROM_STATUS_DATA_PROT_ACCESS
- AR_EEPROM_STATUS_DATA_VAL
- AR_EEPROM_STATUS_DATA_VAL_S
- AR_ENB
- AR_ENT_OTP
- AR_ENT_OTP_49GHZ_DISABLE
- AR_ENT_OTP_CHAIN2_DISABLE
- AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
- AR_EXTRCCNT
- AR_EncrType
- AR_EncrType_S
- AR_ExcessiveRetries
- AR_ExtAndCtl
- AR_ExtOnly
- AR_FAILED
- AR_FAST_DIV_ENABLE
- AR_FAST_DIV_ENABLE_S
- AR_FCS_FAIL
- AR_FIFOUnderrun
- AR_FILT_CCK
- AR_FILT_CCK_COUNT
- AR_FILT_OFDM
- AR_FILT_OFDM_COUNT
- AR_FIRST_NDP_TIMER
- AR_FTRIG
- AR_FTRIG_128B
- AR_FTRIG_192B
- AR_FTRIG_256B
- AR_FTRIG_512B
- AR_FTRIG_64B
- AR_FTRIG_IMMED
- AR_FTRIG_S
- AR_Filtered
- AR_FinalTxIdx
- AR_FinalTxIdx_S
- AR_FrameLen
- AR_FrameType
- AR_FrameType_S
- AR_FrmXmitOK
- AR_G
- AR_GATED_CLKS
- AR_GATED_CLKS_REG
- AR_GATED_CLKS_RX
- AR_GATED_CLKS_TX
- AR_GENTMR_BIT
- AR_GEN_TIMERS
- AR_GEN_TIMERS2_MODE_ENABLE_MASK
- AR_GEN_TIMER_BANK_1_LEN
- AR_GI
- AR_GI0
- AR_GI1
- AR_GI2
- AR_GI3
- AR_GLB_BASE
- AR_GLB_DS_JTAG_DISABLE
- AR_GLB_DS_JTAG_DISABLE_S
- AR_GLB_GPIO_CONTROL
- AR_GLB_SCRATCH
- AR_GLB_STATUS
- AR_GLB_SWREG_DISCONT_EN_BT_WLAN
- AR_GLB_SWREG_DISCONT_MODE
- AR_GLB_WLAN_UART_INTF_EN
- AR_GLB_WLAN_UART_INTF_EN_S
- AR_GPIOD_MASK
- AR_GPIO_IN
- AR_GPIO_INPUT_EN_VAL
- AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB
- AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S
- AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF
- AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S
- AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF
- AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S
- AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB
- AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S
- AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF
- AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S
- AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
- AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S
- AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF
- AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S
- AR_GPIO_INPUT_MUX1
- AR_GPIO_INPUT_MUX1_BT_ACTIVE
- AR_GPIO_INPUT_MUX1_BT_ACTIVE_S
- AR_GPIO_INPUT_MUX1_BT_PRIORITY
- AR_GPIO_INPUT_MUX1_BT_PRIORITY_S
- AR_GPIO_INPUT_MUX2
- AR_GPIO_INPUT_MUX2_CLK25
- AR_GPIO_INPUT_MUX2_CLK25_S
- AR_GPIO_INPUT_MUX2_RFSILENT
- AR_GPIO_INPUT_MUX2_RFSILENT_S
- AR_GPIO_INPUT_MUX2_RTC_RESET
- AR_GPIO_INPUT_MUX2_RTC_RESET_S
- AR_GPIO_INTR_POL
- AR_GPIO_INTR_POL_VAL
- AR_GPIO_INTR_POL_VAL_S
- AR_GPIO_IN_OUT
- AR_GPIO_IN_VAL
- AR_GPIO_IN_VAL_S
- AR_GPIO_JTAG_DISABLE
- AR_GPIO_MASK
- AR_GPIO_OE_OUT
- AR_GPIO_OE_OUT_DRV
- AR_GPIO_OE_OUT_DRV_ALL
- AR_GPIO_OE_OUT_DRV_HI
- AR_GPIO_OE_OUT_DRV_LOW
- AR_GPIO_OE_OUT_DRV_NO
- AR_GPIO_OUTPUT_MUX1
- AR_GPIO_OUTPUT_MUX2
- AR_GPIO_OUTPUT_MUX3
- AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX
- AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX
- AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED
- AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED
- AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK
- AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA
- AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK
- AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA
- AR_GPIO_OUTPUT_MUX_AS_OUTPUT
- AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED
- AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED
- AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA
- AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE
- AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL
- AR_GPIO_OUTPUT_MUX_AS_TX_FRAME
- AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX
- AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX
- AR_GPIO_PDPU
- AR_GPIO_RTC_RESET_OVERRIDE_ENABLE
- AR_GTTM
- AR_GTTM_CST_USEC
- AR_GTTM_IGNORE_IDLE
- AR_GTTM_RESET_IDLE
- AR_GTTM_USEC
- AR_GTXTO
- AR_GTXTO_TIMEOUT_COUNTER
- AR_GTXTO_TIMEOUT_LIMIT
- AR_GTXTO_TIMEOUT_LIMIT_S
- AR_HCF_PERIOD
- AR_HCF_TIMER_EN
- AR_HOST_TIMEOUT
- AR_HOST_TIMEOUT_APB_CNTR
- AR_HOST_TIMEOUT_APB_CNTR_S
- AR_HOST_TIMEOUT_LCL_CNTR
- AR_HOST_TIMEOUT_LCL_CNTR_S
- AR_HP_RXDP
- AR_HW_WOW_DISABLE
- AR_IER
- AR_IER_DISABLE
- AR_IER_ENABLE
- AR_IMR
- AR_IMR_BCNMISC
- AR_IMR_BMISS
- AR_IMR_BNR
- AR_IMR_BRSSI
- AR_IMR_GENTMR
- AR_IMR_MIB
- AR_IMR_QCBROVF
- AR_IMR_QCBRURN
- AR_IMR_QTRIG
- AR_IMR_RXCHIRP
- AR_IMR_RXDESC
- AR_IMR_RXEOL
- AR_IMR_RXERR
- AR_IMR_RXINTM
- AR_IMR_RXKCM
- AR_IMR_RXMINTR
- AR_IMR_RXNOPKT
- AR_IMR_RXOK
- AR_IMR_RXOK_HP
- AR_IMR_RXOK_LP
- AR_IMR_RXORN
- AR_IMR_RXPHY
- AR_IMR_S0
- AR_IMR_S0_QCU_TXDESC
- AR_IMR_S0_QCU_TXDESC_S
- AR_IMR_S0_QCU_TXOK
- AR_IMR_S0_QCU_TXOK_S
- AR_IMR_S1
- AR_IMR_S1_QCU_TXEOL
- AR_IMR_S1_QCU_TXEOL_S
- AR_IMR_S1_QCU_TXERR
- AR_IMR_S1_QCU_TXERR_S
- AR_IMR_S2
- AR_IMR_S2_BB_WATCHDOG
- AR_IMR_S2_BCNTO
- AR_IMR_S2_CABEND
- AR_IMR_S2_CABTO
- AR_IMR_S2_CST
- AR_IMR_S2_DTIM
- AR_IMR_S2_DTIMSYNC
- AR_IMR_S2_GTT
- AR_IMR_S2_QCU_TXURN
- AR_IMR_S2_QCU_TXURN_S
- AR_IMR_S2_TIM
- AR_IMR_S2_TSFOOR
- AR_IMR_S3
- AR_IMR_S3_QCU_QCBROVF
- AR_IMR_S3_QCU_QCBRURN
- AR_IMR_S3_QCU_QCBRURN_S
- AR_IMR_S4
- AR_IMR_S4_QCU_QTRIG
- AR_IMR_S4_RESV0
- AR_IMR_S5
- AR_IMR_S5_DTIM_TIMER
- AR_IMR_S5_GENTIMER_THRESH
- AR_IMR_S5_GENTIMER_THRESH_S
- AR_IMR_S5_GENTIMER_TRIG
- AR_IMR_S5_GENTIMER_TRIG_S
- AR_IMR_S5_TIMER_THRESH
- AR_IMR_S5_TIMER_TRIG
- AR_IMR_S5_TIM_TIMER
- AR_IMR_SWBA
- AR_IMR_SWI
- AR_IMR_TIM
- AR_IMR_TXDESC
- AR_IMR_TXEOL
- AR_IMR_TXERR
- AR_IMR_TXINTM
- AR_IMR_TXMINTR
- AR_IMR_TXNOPKT
- AR_IMR_TXOK
- AR_IMR_TXURN
- AR_INPUT_STATE
- AR_INTCFG
- AR_INTCFG_MSI_RXINTM
- AR_INTCFG_MSI_RXMINTR
- AR_INTCFG_MSI_RXOK
- AR_INTCFG_MSI_TXINTM
- AR_INTCFG_MSI_TXMINTR
- AR_INTCFG_MSI_TXOK
- AR_INTR_ASYNC_CAUSE
- AR_INTR_ASYNC_CAUSE_CLR
- AR_INTR_ASYNC_CAUSE_MCI
- AR_INTR_ASYNC_ENABLE
- AR_INTR_ASYNC_ENABLE_GPIO
- AR_INTR_ASYNC_ENABLE_GPIO_S
- AR_INTR_ASYNC_ENABLE_MCI
- AR_INTR_ASYNC_ENABLE_MCI_S
- AR_INTR_ASYNC_MASK
- AR_INTR_ASYNC_MASK_GPIO
- AR_INTR_ASYNC_MASK_GPIO_S
- AR_INTR_ASYNC_MASK_MCI
- AR_INTR_ASYNC_MASK_MCI_S
- AR_INTR_ASYNC_USED
- AR_INTR_EEP_PROT_ACCESS
- AR_INTR_MAC_ASLEEP
- AR_INTR_MAC_AWAKE
- AR_INTR_MAC_IRQ
- AR_INTR_PRIO_ASYNC_ENABLE
- AR_INTR_PRIO_ASYNC_MASK
- AR_INTR_PRIO_RXHP
- AR_INTR_PRIO_RXLP
- AR_INTR_PRIO_SYNC_ENABLE
- AR_INTR_PRIO_SYNC_MASK
- AR_INTR_PRIO_TX
- AR_INTR_RTC_IRQ
- AR_INTR_SPURIOUS
- AR_INTR_SYNC_ALL
- AR_INTR_SYNC_APB_TIMEOUT
- AR_INTR_SYNC_CAUSE
- AR_INTR_SYNC_CAUSE_CLR
- AR_INTR_SYNC_DEFAULT
- AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS
- AR_INTR_SYNC_ENABLE
- AR_INTR_SYNC_ENABLE_GPIO
- AR_INTR_SYNC_ENABLE_GPIO_S
- AR_INTR_SYNC_HOST1_FATAL
- AR_INTR_SYNC_HOST1_PERR
- AR_INTR_SYNC_LOCAL_TIMEOUT
- AR_INTR_SYNC_MAC_ASLEEP
- AR_INTR_SYNC_MAC_AWAKE
- AR_INTR_SYNC_MAC_IRQ
- AR_INTR_SYNC_MAC_SLEEP_ACCESS
- AR_INTR_SYNC_MASK
- AR_INTR_SYNC_MASK_GPIO
- AR_INTR_SYNC_MASK_GPIO_S
- AR_INTR_SYNC_PCI_MODE_CONFLICT
- AR_INTR_SYNC_PM_ACCESS
- AR_INTR_SYNC_RADM_CPL_DLLP_ABORT
- AR_INTR_SYNC_RADM_CPL_ECRC_ERR
- AR_INTR_SYNC_RADM_CPL_EP
- AR_INTR_SYNC_RADM_CPL_TIMEOUT
- AR_INTR_SYNC_RADM_CPL_TLP_ABORT
- AR_INTR_SYNC_RTC_IRQ
- AR_INTR_SYNC_SPURIOUS
- AR_INTR_SYNC_TRCV_FIFO_PERR
- AR_ISR
- AR_ISR_BCNMISC
- AR_ISR_BMISS
- AR_ISR_BNR
- AR_ISR_BRSSI
- AR_ISR_GENTMR
- AR_ISR_HP_RXOK
- AR_ISR_LP_RXOK
- AR_ISR_MIB
- AR_ISR_QCBROVF
- AR_ISR_QCBRURN
- AR_ISR_QTRIG
- AR_ISR_RAC
- AR_ISR_RXCHIRP
- AR_ISR_RXDESC
- AR_ISR_RXEOL
- AR_ISR_RXERR
- AR_ISR_RXINTM
- AR_ISR_RXKCM
- AR_ISR_RXMINTR
- AR_ISR_RXNOPKT
- AR_ISR_RXOK
- AR_ISR_RXORN
- AR_ISR_RXPHY
- AR_ISR_S0
- AR_ISR_S0_QCU_TXDESC
- AR_ISR_S0_QCU_TXDESC_S
- AR_ISR_S0_QCU_TXOK
- AR_ISR_S0_QCU_TXOK_S
- AR_ISR_S0_S
- AR_ISR_S1
- AR_ISR_S1_QCU_TXEOL
- AR_ISR_S1_QCU_TXEOL_S
- AR_ISR_S1_QCU_TXERR
- AR_ISR_S1_QCU_TXERR_S
- AR_ISR_S1_S
- AR_ISR_S2
- AR_ISR_S2_BB_WATCHDOG
- AR_ISR_S2_BCNTO
- AR_ISR_S2_CABEND
- AR_ISR_S2_CABTO
- AR_ISR_S2_CST
- AR_ISR_S2_DTIM
- AR_ISR_S2_DTIMSYNC
- AR_ISR_S2_GTT
- AR_ISR_S2_QCU_TXURN
- AR_ISR_S2_S
- AR_ISR_S2_TBTT_TIME
- AR_ISR_S2_TIM
- AR_ISR_S2_TSFOOR
- AR_ISR_S3
- AR_ISR_S3_QCU_QCBROVF
- AR_ISR_S3_QCU_QCBRURN
- AR_ISR_S3_S
- AR_ISR_S4
- AR_ISR_S4_QCU_QTRIG
- AR_ISR_S4_RESV0
- AR_ISR_S4_S
- AR_ISR_S5
- AR_ISR_S5_DTIM_TIMER
- AR_ISR_S5_GENTIMER_THRESH
- AR_ISR_S5_GENTIMER_THRESH_S
- AR_ISR_S5_GENTIMER_TRIG
- AR_ISR_S5_GENTIMER_TRIG_S
- AR_ISR_S5_S
- AR_ISR_S5_TIMER_THRESH
- AR_ISR_S5_TIMER_TRIG
- AR_ISR_S5_TIM_TIMER
- AR_ISR_SWBA
- AR_ISR_SWI
- AR_ISR_TIM
- AR_ISR_TXDESC
- AR_ISR_TXEOL
- AR_ISR_TXERR
- AR_ISR_TXINTM
- AR_ISR_TXMINTR
- AR_ISR_TXNOPKT
- AR_ISR_TXOK
- AR_ISR_TXURN
- AR_InsertTS
- AR_IsAggr
- AR_KEYTABLE
- AR_KEYTABLE_0
- AR_KEYTABLE_ANT
- AR_KEYTABLE_KEY0
- AR_KEYTABLE_KEY1
- AR_KEYTABLE_KEY2
- AR_KEYTABLE_KEY3
- AR_KEYTABLE_KEY4
- AR_KEYTABLE_MAC0
- AR_KEYTABLE_MAC1
- AR_KEYTABLE_SIZE
- AR_KEYTABLE_TYPE
- AR_KEYTABLE_TYPE_104
- AR_KEYTABLE_TYPE_128
- AR_KEYTABLE_TYPE_40
- AR_KEYTABLE_TYPE_AES
- AR_KEYTABLE_TYPE_CCM
- AR_KEYTABLE_TYPE_CLR
- AR_KEYTABLE_TYPE_TKIP
- AR_KEYTABLE_VALID
- AR_KEY_CACHE_SIZE
- AR_KEY_TYPE
- AR_KeyIdx
- AR_KeyIdx_S
- AR_KeyMiss
- AR_L
- AR_LAST_TSTP
- AR_LDPC
- AR_LP_RXDP
- AR_LowRxChain
- AR_MACMISC
- AR_MACMISC_DMA_OBS
- AR_MACMISC_DMA_OBS_LINE_0
- AR_MACMISC_DMA_OBS_LINE_1
- AR_MACMISC_DMA_OBS_LINE_2
- AR_MACMISC_DMA_OBS_LINE_3
- AR_MACMISC_DMA_OBS_LINE_4
- AR_MACMISC_DMA_OBS_LINE_5
- AR_MACMISC_DMA_OBS_LINE_6
- AR_MACMISC_DMA_OBS_LINE_7
- AR_MACMISC_DMA_OBS_LINE_8
- AR_MACMISC_DMA_OBS_S
- AR_MACMISC_MISC_OBS
- AR_MACMISC_MISC_OBS_BUS_1
- AR_MACMISC_MISC_OBS_BUS_LSB
- AR_MACMISC_MISC_OBS_BUS_LSB_S
- AR_MACMISC_MISC_OBS_BUS_MSB
- AR_MACMISC_MISC_OBS_BUS_MSB_S
- AR_MACMISC_MISC_OBS_S
- AR_MACMISC_PCI_EXT_FORCE
- AR_MAC_PCU_ASYNC_FIFO_REG3
- AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
- AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
- AR_MAC_PCU_GEN_TIMER_TSF_SEL
- AR_MAC_PCU_LOGIC_ANALYZER
- AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
- AR_MAC_PCU_WOW4
- AR_MAC_SLEEP
- AR_MAC_SLEEP_MAC_ASLEEP
- AR_MAC_SLEEP_MAC_AWAKE
- AR_MAX_CFP_DUR
- AR_MCAST_FIL0
- AR_MCAST_FIL1
- AR_MCAST_FILTER_MAC_ADDR_SIZE
- AR_MCI_BT_PRI
- AR_MCI_BT_PRI0
- AR_MCI_BT_PRI1
- AR_MCI_BT_PRI2
- AR_MCI_BT_PRI3
- AR_MCI_COEX_WL_WEIGHTS
- AR_MCI_COMMAND0
- AR_MCI_COMMAND0_DISABLE_TIMESTAMP
- AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S
- AR_MCI_COMMAND0_HEADER
- AR_MCI_COMMAND0_HEADER_S
- AR_MCI_COMMAND0_LEN
- AR_MCI_COMMAND0_LEN_S
- AR_MCI_COMMAND1
- AR_MCI_COMMAND2
- AR_MCI_COMMAND2_RESET_REQ_WAKEUP
- AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S
- AR_MCI_COMMAND2_RESET_RX
- AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES
- AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S
- AR_MCI_COMMAND2_RESET_RX_S
- AR_MCI_COMMAND2_RESET_TX
- AR_MCI_COMMAND2_RESET_TX_S
- AR_MCI_CONT_PRIORITY
- AR_MCI_CONT_PRIORITY_S
- AR_MCI_CONT_RSSI_POWER
- AR_MCI_CONT_RSSI_POWER_S
- AR_MCI_CONT_STATUS
- AR_MCI_CONT_TXRX
- AR_MCI_CONT_TXRX_S
- AR_MCI_CPU_INT
- AR_MCI_DBG_CNT_CTRL
- AR_MCI_DBG_CNT_CTRL_BT_LINKID
- AR_MCI_DBG_CNT_CTRL_BT_LINKID_S
- AR_MCI_DBG_CNT_CTRL_ENABLE
- AR_MCI_DBG_CNT_CTRL_ENABLE_S
- AR_MCI_GAIN
- AR_MCI_GPM_0
- AR_MCI_GPM_1
- AR_MCI_GPM_BUF_LEN
- AR_MCI_GPM_BUF_LEN_S
- AR_MCI_GPM_WRITE_PTR
- AR_MCI_GPM_WRITE_PTR_S
- AR_MCI_HW_SCHD_TBL_CTL
- AR_MCI_HW_SCHD_TBL_D0
- AR_MCI_HW_SCHD_TBL_D1
- AR_MCI_HW_SCHD_TBL_D2
- AR_MCI_HW_SCHD_TBL_D3
- AR_MCI_INTERRUPT_BB_AIC_IRQ
- AR_MCI_INTERRUPT_BB_AIC_IRQ_S
- AR_MCI_INTERRUPT_BT_FREQ
- AR_MCI_INTERRUPT_BT_FREQ_S
- AR_MCI_INTERRUPT_BT_PRI
- AR_MCI_INTERRUPT_BT_PRI_S
- AR_MCI_INTERRUPT_BT_PRI_THRESH
- AR_MCI_INTERRUPT_BT_PRI_THRESH_S
- AR_MCI_INTERRUPT_BT_STOMP
- AR_MCI_INTERRUPT_BT_STOMP_S
- AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT
- AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S
- AR_MCI_INTERRUPT_CPU_INT_MSG
- AR_MCI_INTERRUPT_CPU_INT_MSG_S
- AR_MCI_INTERRUPT_DEFAULT
- AR_MCI_INTERRUPT_EN
- AR_MCI_INTERRUPT_MSG_FAIL_MASK
- AR_MCI_INTERRUPT_RAW
- AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE
- AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S
- AR_MCI_INTERRUPT_RX_CKSUM_FAIL
- AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S
- AR_MCI_INTERRUPT_RX_HW_MSG_FAIL
- AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S
- AR_MCI_INTERRUPT_RX_HW_MSG_MASK
- AR_MCI_INTERRUPT_RX_INVALID_HDR
- AR_MCI_INTERRUPT_RX_INVALID_HDR_S
- AR_MCI_INTERRUPT_RX_MSG
- AR_MCI_INTERRUPT_RX_MSG_CONT_INFO
- AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S
- AR_MCI_INTERRUPT_RX_MSG_CONT_NACK
- AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S
- AR_MCI_INTERRUPT_RX_MSG_CONT_RST
- AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S
- AR_MCI_INTERRUPT_RX_MSG_CPU_INT
- AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S
- AR_MCI_INTERRUPT_RX_MSG_DEFAULT
- AR_MCI_INTERRUPT_RX_MSG_EN
- AR_MCI_INTERRUPT_RX_MSG_GPM
- AR_MCI_INTERRUPT_RX_MSG_GPM_S
- AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL
- AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S
- AR_MCI_INTERRUPT_RX_MSG_LNA_INFO
- AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S
- AR_MCI_INTERRUPT_RX_MSG_RAW
- AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET
- AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S
- AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE
- AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S
- AR_MCI_INTERRUPT_RX_MSG_S
- AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO
- AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S
- AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING
- AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S
- AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING
- AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S
- AR_MCI_INTERRUPT_RX_SW_MSG_FAIL
- AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S
- AR_MCI_INTERRUPT_SW_MSG_DONE
- AR_MCI_INTERRUPT_SW_MSG_DONE_S
- AR_MCI_INTERRUPT_TX_HW_MSG_FAIL
- AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S
- AR_MCI_INTERRUPT_TX_SW_MSG_FAIL
- AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S
- AR_MCI_LAST_HW_MSG_BDY
- AR_MCI_LAST_HW_MSG_HDR
- AR_MCI_MAXGAIN
- AR_MCI_MISC
- AR_MCI_MISC_HW_FIX_EN
- AR_MCI_MISC_HW_FIX_EN_S
- AR_MCI_MSG_ATTRIBUTES_TABLE
- AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM
- AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S
- AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR
- AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S
- AR_MCI_REMOTE_CPU_INT
- AR_MCI_REMOTE_CPU_INT_EN
- AR_MCI_RX_CTRL
- AR_MCI_RX_LAST_SCHD_MSG_INDEX
- AR_MCI_RX_LAST_SCHD_MSG_INDEX_S
- AR_MCI_RX_MCI_CLK_REQ
- AR_MCI_RX_MCI_CLK_REQ_S
- AR_MCI_RX_REMOTE_SLEEP
- AR_MCI_RX_REMOTE_SLEEP_S
- AR_MCI_RX_STATUS
- AR_MCI_SCHD_TABLE_0
- AR_MCI_SCHD_TABLE_1
- AR_MCI_SCHD_TABLE_2
- AR_MCI_SCHD_TABLE_2_HW_BASED
- AR_MCI_SCHD_TABLE_2_HW_BASED_S
- AR_MCI_SCHD_TABLE_2_MEM_BASED
- AR_MCI_SCHD_TABLE_2_MEM_BASED_S
- AR_MCI_TX_CTRL
- AR_MCI_TX_CTRL_CLK_DIV
- AR_MCI_TX_CTRL_CLK_DIV_S
- AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE
- AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S
- AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ
- AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S
- AR_MCI_TX_CTRL_GAIN_UPDATE_NUM
- AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S
- AR_MCI_TX_PAYLOAD0
- AR_MCI_TX_PAYLOAD1
- AR_MCI_TX_PAYLOAD2
- AR_MCI_TX_PAYLOAD3
- AR_MCI_WBTIMER1
- AR_MCI_WBTIMER2
- AR_MCI_WBTIMER3
- AR_MCI_WBTIMER4
- AR_MCI_WL_FREQ0
- AR_MCI_WL_FREQ1
- AR_MCI_WL_FREQ2
- AR_MIBC
- AR_MIBCNT_INTRMASK
- AR_MIBC_CMC
- AR_MIBC_COW
- AR_MIBC_FMC
- AR_MIBC_MCS
- AR_MIC_QOS_CONTROL
- AR_MIC_QOS_SELECT
- AR_MIRT
- AR_MIRT_VAL
- AR_MIRT_VAL_S
- AR_MRC_BASE
- AR_MichaelErr
- AR_MoreAggr
- AR_NAV
- AR_NDP2_PERIOD
- AR_NDP2_TIMER_MODE
- AR_NDP_PERIOD
- AR_NDP_TIMER_EN
- AR_NEXT_CFP
- AR_NEXT_DMA_BEACON_ALERT
- AR_NEXT_DTIM
- AR_NEXT_HCF
- AR_NEXT_NDP2_TIMER
- AR_NEXT_NDP_TIMER
- AR_NEXT_QUIET_TIMER
- AR_NEXT_SWBA
- AR_NEXT_TBTT_TIMER
- AR_NEXT_TIM
- AR_NO_SPUR
- AR_NUM_DCU
- AR_NUM_GPIO
- AR_NUM_QCU
- AR_NoAck
- AR_Not_Sounding
- AR_NumDelim
- AR_NumDelim_S
- AR_OBS
- AR_OBS_BUS_1
- AR_OBS_BUS_1_CHAN_IDLE
- AR_OBS_BUS_1_PCU
- AR_OBS_BUS_1_QUIET_TIME
- AR_OBS_BUS_1_RX_BEACON
- AR_OBS_BUS_1_RX_CLEAR
- AR_OBS_BUS_1_RX_END
- AR_OBS_BUS_1_RX_FILTER
- AR_OBS_BUS_1_RX_FRAME
- AR_OBS_BUS_1_RX_STATE
- AR_OBS_BUS_1_RX_STATE_S
- AR_OBS_BUS_1_RX_WEP
- AR_OBS_BUS_1_TX_FRAME
- AR_OBS_BUS_1_TX_HCF
- AR_OBS_BUS_1_TX_HOLD
- AR_OBS_BUS_1_TX_STATE
- AR_OBS_BUS_1_TX_STATE_S
- AR_OBS_BUS_1_WEP_STATE
- AR_OBS_BUS_1_WEP_STATE_S
- AR_OBS_BUS_CTRL
- AR_OBS_BUS_SEL_1
- AR_OBS_BUS_SEL_2
- AR_OBS_BUS_SEL_3
- AR_OBS_BUS_SEL_4
- AR_OBS_BUS_SEL_5
- AR_P
- AR_PAPRDChainMask
- AR_PAPRDChainMask_S
- AR_PARAM_SRC_OFFSET
- AR_PCIE_CDR_PWRSAVE_ON_D0
- AR_PCIE_CDR_PWRSAVE_ON_D3
- AR_PCIE_MSI
- AR_PCIE_MSI_ENABLE
- AR_PCIE_MSI_HW_DBI_WR_EN
- AR_PCIE_MSI_HW_INT_PENDING_ADDR
- AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64
- AR_PCIE_PHY_REG3
- AR_PCIE_PLL_PWRSAVE_CONTROL
- AR_PCIE_PLL_PWRSAVE_ON_D0
- AR_PCIE_PLL_PWRSAVE_ON_D3
- AR_PCIE_PM_CTRL
- AR_PCIE_PM_CTRL_ENA
- AR_PCIE_SERDES
- AR_PCIE_SERDES2
- AR_PCU_ALWAYS_PERFORM_KEYSEARCH
- AR_PCU_BT_ANT_PREVENT_RX
- AR_PCU_BT_ANT_PREVENT_RX_S
- AR_PCU_BUG_12306_FIX_ENA
- AR_PCU_CCK_SIFS_MODE
- AR_PCU_CLEAR_BA_VALID
- AR_PCU_CLEAR_VMF
- AR_PCU_FORCE_BSSID_MATCH
- AR_PCU_FORCE_QUIET_COLL
- AR_PCU_MIC_NEW_LOC_ENA
- AR_PCU_MISC
- AR_PCU_MISC_MODE2
- AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE
- AR_PCU_MISC_MODE2_CFP_IGNORE
- AR_PCU_MISC_MODE2_ENABLE_AGGWEP
- AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION
- AR_PCU_MISC_MODE2_HWWAR1
- AR_PCU_MISC_MODE2_HWWAR2
- AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
- AR_PCU_MISC_MODE2_MGMT_QOS
- AR_PCU_MISC_MODE2_MGMT_QOS_S
- AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
- AR_PCU_MISC_MODE2_RESERVED
- AR_PCU_MISC_MODE2_RESERVED2
- AR_PCU_MISC_MODE3
- AR_PCU_MISS_BCN_IN_SLEEP
- AR_PCU_RX_ANT_UPDT
- AR_PCU_TBTT_PROTECT
- AR_PCU_TXBUF_CTRL
- AR_PCU_TXBUF_CTRL_SIZE_MASK
- AR_PCU_TXBUF_CTRL_USABLE_SIZE
- AR_PCU_TXOP_TBTT_LIMIT_ENA
- AR_PCU_TX_ADD_TSF
- AR_PHY
- AR_PHYErr
- AR_PHYErrCode
- AR_PHYErrCode_S
- AR_PHY_20_40_DET_THR
- AR_PHY_65NM_BASE
- AR_PHY_65NM_CH0_BB1
- AR_PHY_65NM_CH0_BB2
- AR_PHY_65NM_CH0_BB3
- AR_PHY_65NM_CH0_BIAS1
- AR_PHY_65NM_CH0_BIAS2
- AR_PHY_65NM_CH0_BIAS4
- AR_PHY_65NM_CH0_RXTX2
- AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK
- AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S
- AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK
- AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S
- AR_PHY_65NM_CH0_RXTX4
- AR_PHY_65NM_CH0_RXTX4_THERM_ON
- AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR
- AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S
- AR_PHY_65NM_CH0_RXTX4_THERM_ON_S
- AR_PHY_65NM_CH0_SYNTH12
- AR_PHY_65NM_CH0_SYNTH12_VREFMUL3
- AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S
- AR_PHY_65NM_CH0_SYNTH4
- AR_PHY_65NM_CH0_SYNTH7
- AR_PHY_65NM_CH0_TXRF3
- AR_PHY_65NM_CH0_TXRF3_CAPDIV2G
- AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S
- AR_PHY_65NM_CH1_BB1
- AR_PHY_65NM_CH1_BB2
- AR_PHY_65NM_CH1_BB3
- AR_PHY_65NM_CH1_RXTX2
- AR_PHY_65NM_CH1_RXTX4
- AR_PHY_65NM_CH2_BB1
- AR_PHY_65NM_CH2_BB2
- AR_PHY_65NM_CH2_BB3
- AR_PHY_65NM_CH2_RXTX2
- AR_PHY_65NM_CH2_RXTX4
- AR_PHY_65NM_RXRF_AGC
- AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR
- AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR
- AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR
- AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR
- AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR
- AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR
- AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR_S
- AR_PHY_65NM_RXRF_AGC_AGC_OUT
- AR_PHY_65NM_RXRF_AGC_AGC_OUT_S
- AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE
- AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE_S
- AR_PHY_65NM_RXRF_GAINSTAGES
- AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR
- AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_S
- AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR
- AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_S
- AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC
- AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC_S
- AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE
- AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE_S
- AR_PHY_65NM_RXTX2
- AR_PHY_65NM_RXTX2_RXON
- AR_PHY_65NM_RXTX2_RXON_OVR
- AR_PHY_65NM_RXTX2_RXON_OVR_S
- AR_PHY_65NM_RXTX2_RXON_S
- AR_PHY_65NM_RXTX4_XLNA_BIAS
- AR_PHY_65NM_RXTX4_XLNA_BIAS_S
- AR_PHY_9285_ANT_DIV_ALT_GAINTB
- AR_PHY_9285_ANT_DIV_ALT_GAINTB_S
- AR_PHY_9285_ANT_DIV_ALT_LNACONF
- AR_PHY_9285_ANT_DIV_ALT_LNACONF_S
- AR_PHY_9285_ANT_DIV_CTL
- AR_PHY_9285_ANT_DIV_CTL_ALL
- AR_PHY_9285_ANT_DIV_CTL_S
- AR_PHY_9285_ANT_DIV_GAINTB_0
- AR_PHY_9285_ANT_DIV_GAINTB_1
- AR_PHY_9285_ANT_DIV_MAIN_GAINTB
- AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S
- AR_PHY_9285_ANT_DIV_MAIN_LNACONF
- AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S
- AR_PHY_9285_FAST_DIV_BIAS
- AR_PHY_9285_FAST_DIV_BIAS_S
- AR_PHY_ACTIVE
- AR_PHY_ACTIVE_DIS
- AR_PHY_ACTIVE_EN
- AR_PHY_ADC_CTL
- AR_PHY_ADC_CTL_OFF_INBUFGAIN
- AR_PHY_ADC_CTL_OFF_INBUFGAIN_S
- AR_PHY_ADC_CTL_OFF_PWDADC
- AR_PHY_ADC_CTL_OFF_PWDBANDGAP
- AR_PHY_ADC_CTL_OFF_PWDDAC
- AR_PHY_ADC_CTL_ON_INBUFGAIN
- AR_PHY_ADC_CTL_ON_INBUFGAIN_S
- AR_PHY_ADC_GAIN_DC_CORR_0
- AR_PHY_ADC_GAIN_DC_CORR_0_9300_10
- AR_PHY_ADC_GAIN_DC_CORR_1
- AR_PHY_ADC_GAIN_DC_CORR_2
- AR_PHY_ADC_SERIAL_CTL
- AR_PHY_ADDAC_CLK_SEL
- AR_PHY_ADDAC_PARACTL_OFF_PWDADC
- AR_PHY_ADDAC_PARA_CTL
- AR_PHY_AGC
- AR_PHY_AGC_COARSE_HIGH
- AR_PHY_AGC_COARSE_HIGH_S
- AR_PHY_AGC_COARSE_LOW
- AR_PHY_AGC_COARSE_LOW_S
- AR_PHY_AGC_COARSE_PWR_CONST
- AR_PHY_AGC_COARSE_PWR_CONST_S
- AR_PHY_AGC_CONTROL
- AR_PHY_AGC_CONTROL_CAL
- AR_PHY_AGC_CONTROL_CLC_SUCCESS
- AR_PHY_AGC_CONTROL_ENABLE_NF
- AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS
- AR_PHY_AGC_CONTROL_FLTR_CAL
- AR_PHY_AGC_CONTROL_NF
- AR_PHY_AGC_CONTROL_NO_UPDATE_NF
- AR_PHY_AGC_CONTROL_OFFSET_CAL
- AR_PHY_AGC_CONTROL_PKDET_CAL
- AR_PHY_AGC_CONTROL_YCOK_MAX
- AR_PHY_AGC_CONTROL_YCOK_MAX_S
- AR_PHY_AGC_CTL1
- AR_PHY_AGC_CTL1_COARSE_HIGH
- AR_PHY_AGC_CTL1_COARSE_HIGH_S
- AR_PHY_AGC_CTL1_COARSE_LOW
- AR_PHY_AGC_CTL1_COARSE_LOW_S
- AR_PHY_AGC_QUICK_DROP
- AR_PHY_AGC_QUICK_DROP_S
- AR_PHY_AIC_BTTX_PWR_THR
- AR_PHY_AIC_BTTX_PWR_THR_S
- AR_PHY_AIC_BT_IDLE_CFG
- AR_PHY_AIC_BT_IDLE_CFG_S
- AR_PHY_AIC_CAL_ACTIVE
- AR_PHY_AIC_CAL_ACTIVE_S
- AR_PHY_AIC_CAL_AIC_SM
- AR_PHY_AIC_CAL_AIC_SM_S
- AR_PHY_AIC_CAL_ANT_ISO_EST
- AR_PHY_AIC_CAL_ANT_ISO_EST_S
- AR_PHY_AIC_CAL_BT_REF_DELAY
- AR_PHY_AIC_CAL_BT_REF_DELAY_S
- AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR
- AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S
- AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR
- AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S
- AR_PHY_AIC_CAL_CH_VALID_RESET
- AR_PHY_AIC_CAL_CH_VALID_RESET_S
- AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF
- AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S
- AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO
- AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S
- AR_PHY_AIC_CAL_COM_ATT_DB_FIXED
- AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S
- AR_PHY_AIC_CAL_CONV_CHECK_FACTOR
- AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S
- AR_PHY_AIC_CAL_DONE
- AR_PHY_AIC_CAL_DONE_S
- AR_PHY_AIC_CAL_ENABLE
- AR_PHY_AIC_CAL_ENABLE_S
- AR_PHY_AIC_CAL_HOP_COUNT
- AR_PHY_AIC_CAL_HOP_COUNT_S
- AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING
- AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S
- AR_PHY_AIC_CAL_MAX_HOP_COUNT
- AR_PHY_AIC_CAL_MAX_HOP_COUNT_S
- AR_PHY_AIC_CAL_MIN_VALID_COUNT
- AR_PHY_AIC_CAL_MIN_VALID_COUNT_S
- AR_PHY_AIC_CAL_PERF_CHECK_FACTOR
- AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S
- AR_PHY_AIC_CAL_PWR_EST_LONG
- AR_PHY_AIC_CAL_PWR_EST_LONG_S
- AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO
- AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S
- AR_PHY_AIC_CAL_ROT_IDX_CORR
- AR_PHY_AIC_CAL_ROT_IDX_CORR_S
- AR_PHY_AIC_CAL_STEP_SIZE_CORR
- AR_PHY_AIC_CAL_STEP_SIZE_CORR_S
- AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX
- AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S
- AR_PHY_AIC_CAL_SYNTH_SETTLING
- AR_PHY_AIC_CAL_SYNTH_SETTLING_S
- AR_PHY_AIC_CAL_SYNTH_TOGGLE
- AR_PHY_AIC_CAL_SYNTH_TOGGLE_S
- AR_PHY_AIC_CAL_TARGET_MAG_SETTING
- AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S
- AR_PHY_AIC_CAL_VALID_COUNT
- AR_PHY_AIC_CAL_VALID_COUNT_S
- AR_PHY_AIC_CTRL_0_B0
- AR_PHY_AIC_CTRL_0_B1
- AR_PHY_AIC_CTRL_1_B0
- AR_PHY_AIC_CTRL_1_B1
- AR_PHY_AIC_CTRL_2_B0
- AR_PHY_AIC_CTRL_3_B0
- AR_PHY_AIC_CTRL_4_B0
- AR_PHY_AIC_CTRL_4_B1
- AR_PHY_AIC_ENABLE
- AR_PHY_AIC_ENABLE_S
- AR_PHY_AIC_F_WLAN
- AR_PHY_AIC_F_WLAN_S
- AR_PHY_AIC_MEAS_COUNT
- AR_PHY_AIC_MEAS_COUNT_S
- AR_PHY_AIC_MEAS_MAG_MIN
- AR_PHY_AIC_MEAS_MAG_MIN_S
- AR_PHY_AIC_MON_ACTIVE
- AR_PHY_AIC_MON_ACTIVE_S
- AR_PHY_AIC_MON_DONE
- AR_PHY_AIC_MON_DONE_S
- AR_PHY_AIC_MON_ENABLE
- AR_PHY_AIC_MON_ENABLE_S
- AR_PHY_AIC_MON_HOP_COUNT
- AR_PHY_AIC_MON_HOP_COUNT_S
- AR_PHY_AIC_MON_MAX_HOP_COUNT
- AR_PHY_AIC_MON_MAX_HOP_COUNT_S
- AR_PHY_AIC_MON_MIN_STALE_COUNT
- AR_PHY_AIC_MON_MIN_STALE_COUNT_S
- AR_PHY_AIC_MON_PD_TALLY_SCALING
- AR_PHY_AIC_MON_PD_TALLY_SCALING_S
- AR_PHY_AIC_MON_PERF_THR
- AR_PHY_AIC_MON_PERF_THR_S
- AR_PHY_AIC_MON_PWR_EST_LONG
- AR_PHY_AIC_MON_PWR_EST_LONG_S
- AR_PHY_AIC_MON_STALE_COUNT
- AR_PHY_AIC_MON_STALE_COUNT_S
- AR_PHY_AIC_RADIO_DELAY
- AR_PHY_AIC_RADIO_DELAY_S
- AR_PHY_AIC_ROT_IDX_COUNT_MAX
- AR_PHY_AIC_ROT_IDX_COUNT_MAX_S
- AR_PHY_AIC_RSSI_MAX
- AR_PHY_AIC_RSSI_MAX_S
- AR_PHY_AIC_RSSI_MIN
- AR_PHY_AIC_RSSI_MIN_S
- AR_PHY_AIC_SM
- AR_PHY_AIC_SM_S
- AR_PHY_AIC_SRAM_ADDR_B0
- AR_PHY_AIC_SRAM_ADDR_B1
- AR_PHY_AIC_SRAM_COM_ATT_6DB
- AR_PHY_AIC_SRAM_COM_ATT_6DB_S
- AR_PHY_AIC_SRAM_DATA_B0
- AR_PHY_AIC_SRAM_DATA_B1
- AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB
- AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S
- AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB
- AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S
- AR_PHY_AIC_SRAM_VALID
- AR_PHY_AIC_SRAM_VALID_S
- AR_PHY_AIC_SRAM_VGA_DIR_SIGN
- AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S
- AR_PHY_AIC_SRAM_VGA_QUAD_SIGN
- AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S
- AR_PHY_AIC_STAT_0_B0
- AR_PHY_AIC_STAT_0_B1
- AR_PHY_AIC_STAT_1_B0
- AR_PHY_AIC_STAT_1_B1
- AR_PHY_AIC_STAT_2_B0
- AR_PHY_AIC_STAT_2_B1
- AR_PHY_AIC_STDBY_COM_ATT_DB
- AR_PHY_AIC_STDBY_COM_ATT_DB_S
- AR_PHY_AIC_STDBY_COND
- AR_PHY_AIC_STDBY_COND_S
- AR_PHY_AIC_STDBY_ROT_ATT_DB
- AR_PHY_AIC_STDBY_ROT_ATT_DB_S
- AR_PHY_ANALOG_SWAP
- AR_PHY_ANT_DIV_ALT_GAINTB
- AR_PHY_ANT_DIV_ALT_GAINTB_S
- AR_PHY_ANT_DIV_ALT_LNACONF
- AR_PHY_ANT_DIV_ALT_LNACONF_S
- AR_PHY_ANT_DIV_LNADIV
- AR_PHY_ANT_DIV_LNADIV_S
- AR_PHY_ANT_DIV_MAIN_GAINTB
- AR_PHY_ANT_DIV_MAIN_GAINTB_S
- AR_PHY_ANT_DIV_MAIN_LNACONF
- AR_PHY_ANT_DIV_MAIN_LNACONF_S
- AR_PHY_ANT_FAST_DIV_BIAS
- AR_PHY_ANT_FAST_DIV_BIAS_S
- AR_PHY_ANT_SW_RX_PROT
- AR_PHY_ANT_SW_RX_PROT_S
- AR_PHY_BASE
- AR_PHY_BB_THERM_ADC_1
- AR_PHY_BB_THERM_ADC_1_INIT_THERM
- AR_PHY_BB_THERM_ADC_1_INIT_THERM_S
- AR_PHY_BB_THERM_ADC_3
- AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET
- AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S
- AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN
- AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S
- AR_PHY_BB_THERM_ADC_4
- AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE
- AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S
- AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE
- AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S
- AR_PHY_BIN_MASK2_1
- AR_PHY_BIN_MASK2_2
- AR_PHY_BIN_MASK2_3
- AR_PHY_BIN_MASK2_4
- AR_PHY_BIN_MASK2_4_MASK_4
- AR_PHY_BIN_MASK2_4_MASK_4_S
- AR_PHY_BIN_MASK_1
- AR_PHY_BIN_MASK_2
- AR_PHY_BIN_MASK_3
- AR_PHY_BLUETOOTH
- AR_PHY_BT_COEX_4
- AR_PHY_BT_COEX_5
- AR_PHY_CALIBRATED_GAINS_0
- AR_PHY_CALIBRATED_GAINS_0_S
- AR_PHY_CALMODE
- AR_PHY_CALMODE_ADC_DC_INIT
- AR_PHY_CALMODE_ADC_DC_PER
- AR_PHY_CALMODE_ADC_GAIN
- AR_PHY_CALMODE_IQ
- AR_PHY_CAL_CHAINMASK
- AR_PHY_CAL_MEAS_0
- AR_PHY_CAL_MEAS_0_9300_10
- AR_PHY_CAL_MEAS_1
- AR_PHY_CAL_MEAS_1_9300_10
- AR_PHY_CAL_MEAS_2
- AR_PHY_CAL_MEAS_2_9300_10
- AR_PHY_CAL_MEAS_3
- AR_PHY_CAL_MEAS_3_9300_10
- AR_PHY_CCA
- AR_PHY_CCA_0
- AR_PHY_CCA_1
- AR_PHY_CCA_2
- AR_PHY_CCA_CTRL_0
- AR_PHY_CCA_CTRL_1
- AR_PHY_CCA_CTRL_2
- AR_PHY_CCA_FILTERWINDOW_LENGTH
- AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ
- AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ
- AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ
- AR_PHY_CCA_NOM_VAL_2GHZ
- AR_PHY_CCA_NOM_VAL_5416_2GHZ
- AR_PHY_CCA_NOM_VAL_5416_5GHZ
- AR_PHY_CCA_NOM_VAL_9271_2GHZ
- AR_PHY_CCA_NOM_VAL_9280_2GHZ
- AR_PHY_CCA_NOM_VAL_9280_5GHZ
- AR_PHY_CCA_NOM_VAL_9285_2GHZ
- AR_PHY_CCA_NOM_VAL_9287_2GHZ
- AR_PHY_CCA_NOM_VAL_9300_2GHZ
- AR_PHY_CCA_NOM_VAL_9300_5GHZ
- AR_PHY_CCA_NOM_VAL_9330_2GHZ
- AR_PHY_CCA_NOM_VAL_9462_2GHZ
- AR_PHY_CCA_NOM_VAL_9462_5GHZ
- AR_PHY_CCA_THRESH62
- AR_PHY_CCA_THRESH62_S
- AR_PHY_CCK_DETECT
- AR_PHY_CCK_DETECT_ANT_SWITCH_TIME
- AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S
- AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
- AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S
- AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
- AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S
- AR_PHY_CCK_RXCTRL4
- AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT
- AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S
- AR_PHY_CCK_SPUR_MIT
- AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ
- AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S
- AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE
- AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S
- AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR
- AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S
- AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT
- AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S
- AR_PHY_CCK_TX_CTRL
- AR_PHY_CCK_TX_CTRL_JAPAN
- AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK
- AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S
- AR_PHY_CH0_TX_PWRCTRL11
- AR_PHY_CH0_TX_PWRCTRL12
- AR_PHY_CH0_TX_PWRCTRL13
- AR_PHY_CH1_CCA
- AR_PHY_CH1_EXT_CCA
- AR_PHY_CH1_EXT_MINCCA_PWR
- AR_PHY_CH1_EXT_MINCCA_PWR_S
- AR_PHY_CH1_MINCCA_PWR
- AR_PHY_CH1_MINCCA_PWR_S
- AR_PHY_CH1_TX_PWRCTRL11
- AR_PHY_CH2_CCA
- AR_PHY_CH2_EXT_CCA
- AR_PHY_CH2_EXT_MINCCA_PWR
- AR_PHY_CH2_EXT_MINCCA_PWR_S
- AR_PHY_CH2_MINCCA_PWR
- AR_PHY_CH2_MINCCA_PWR_S
- AR_PHY_CHAIN_OFFSET
- AR_PHY_CHANNEL_MASK_01_30
- AR_PHY_CHANNEL_MASK_31_60
- AR_PHY_CHANNEL_STATUS_RX_CLEAR
- AR_PHY_CHAN_INFO_GAIN
- AR_PHY_CHAN_INFO_GAIN_0
- AR_PHY_CHAN_INFO_GAIN_1
- AR_PHY_CHAN_INFO_GAIN_2
- AR_PHY_CHAN_INFO_GAIN_DIFF
- AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK
- AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT
- AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT
- AR_PHY_CHAN_INFO_MEMORY
- AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK
- AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ
- AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S
- AR_PHY_CHAN_INFO_TAB_0
- AR_PHY_CHAN_INFO_TAB_1
- AR_PHY_CHAN_INFO_TAB_2
- AR_PHY_CHAN_INFO_TAB_S2_READ
- AR_PHY_CHAN_INFO_TAB_S2_READ_S
- AR_PHY_CHAN_SPUR_MASK
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B
- AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S
- AR_PHY_CHAN_STATUS
- AR_PHY_CHIP_ID
- AR_PHY_CHIP_ID_9160_REV_0
- AR_PHY_CHIP_ID_REV_0
- AR_PHY_CHIP_ID_REV_1
- AR_PHY_CHIRP_DETECTED_XR
- AR_PHY_CHNINFO_FINETIM
- AR_PHY_CHNINFO_GAINDIFF
- AR_PHY_CHNINFO_NOISEPWR
- AR_PHY_CH_EXT_MINCCA_PWR
- AR_PHY_CH_EXT_MINCCA_PWR_S
- AR_PHY_CH_MINCCA_PWR
- AR_PHY_CH_MINCCA_PWR_S
- AR_PHY_CLC_I0
- AR_PHY_CLC_I0_S
- AR_PHY_CLC_Q0
- AR_PHY_CLC_Q0_S
- AR_PHY_CLC_TBL1
- AR_PHY_CL_CAL_CTL
- AR_PHY_CL_CAL_ENABLE
- AR_PHY_CL_TAB_0
- AR_PHY_CL_TAB_1
- AR_PHY_CL_TAB_2
- AR_PHY_CL_TAB_CL_GAIN_MOD
- AR_PHY_CL_TAB_CL_GAIN_MOD_S
- AR_PHY_COUNTMAX
- AR_PHY_CURRENT_RSSI
- AR_PHY_D2_CHIP_ID
- AR_PHY_DAG_CTRLCCK
- AR_PHY_DAG_CTRLCCK_EN_RSSI_THR
- AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S
- AR_PHY_DAG_CTRLCCK_RSSI_THR
- AR_PHY_DAG_CTRLCCK_RSSI_THR_S
- AR_PHY_DC_RESTART_DIS
- AR_PHY_DESIRED_SZ
- AR_PHY_DESIRED_SZ_ADC
- AR_PHY_DESIRED_SZ_ADC_S
- AR_PHY_DESIRED_SZ_PGA
- AR_PHY_DESIRED_SZ_PGA_S
- AR_PHY_DESIRED_SZ_TOT_DES
- AR_PHY_DESIRED_SZ_TOT_DES_S
- AR_PHY_DFT_TONE_CTL_0
- AR_PHY_DFT_TONE_CTL_1
- AR_PHY_DFT_TONE_CTL_2
- AR_PHY_ECO_CTRL
- AR_PHY_ERR
- AR_PHY_ERR_1
- AR_PHY_ERR_1_COUNT
- AR_PHY_ERR_2
- AR_PHY_ERR_2_COUNT
- AR_PHY_ERR_3
- AR_PHY_ERR_3_COUNT
- AR_PHY_ERR_CCK_TIMING
- AR_PHY_ERR_DCHIRP
- AR_PHY_ERR_EIFS_MASK
- AR_PHY_ERR_MASK_1
- AR_PHY_ERR_MASK_2
- AR_PHY_ERR_MASK_3
- AR_PHY_ERR_OFDM_TIMING
- AR_PHY_ERR_RADAR
- AR_PHY_EXTCHN_PWRTHR1
- AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX
- AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S
- AR_PHY_EXT_ATTEN_CTL
- AR_PHY_EXT_ATTEN_CTL_0
- AR_PHY_EXT_ATTEN_CTL_1
- AR_PHY_EXT_ATTEN_CTL_2
- AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN
- AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S
- AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN
- AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S
- AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN
- AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S
- AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
- AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S
- AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
- AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S
- AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB
- AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S
- AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN
- AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S
- AR_PHY_EXT_CCA
- AR_PHY_EXT_CCA0
- AR_PHY_EXT_CCA0_THRESH62
- AR_PHY_EXT_CCA0_THRESH62_1
- AR_PHY_EXT_CCA0_THRESH62_1_S
- AR_PHY_EXT_CCA0_THRESH62_S
- AR_PHY_EXT_CCA_1
- AR_PHY_EXT_CCA_2
- AR_PHY_EXT_CCA_CYCPWR_THR1
- AR_PHY_EXT_CCA_CYCPWR_THR1_S
- AR_PHY_EXT_CCA_THRESH62
- AR_PHY_EXT_CCA_THRESH62_S
- AR_PHY_EXT_CHN_WIN
- AR_PHY_EXT_CYCPWR_THR1
- AR_PHY_EXT_CYCPWR_THR1_S
- AR_PHY_EXT_MINCCA_PWR
- AR_PHY_EXT_MINCCA_PWR_S
- AR_PHY_EXT_TIMING5_CYCPWR_THR1
- AR_PHY_EXT_TIMING5_CYCPWR_THR1_S
- AR_PHY_FCAL20_CAP_STATUS_0
- AR_PHY_FCAL20_CAP_STATUS_0_S
- AR_PHY_FCAL_1
- AR_PHY_FCAL_2_0
- AR_PHY_FCAL_2_1
- AR_PHY_FCAL_2_2
- AR_PHY_FC_DYN2040_EN
- AR_PHY_FC_DYN2040_EXT_CH
- AR_PHY_FC_DYN2040_PRI_CH
- AR_PHY_FC_DYN2040_PRI_ONLY
- AR_PHY_FC_ENABLE_DAC_FIFO
- AR_PHY_FC_HT_EN
- AR_PHY_FC_SHORT_GI_40
- AR_PHY_FC_SINGLE_HT_LTF1
- AR_PHY_FC_TURBO_MODE
- AR_PHY_FC_TURBO_SHORT
- AR_PHY_FC_WALSH
- AR_PHY_FIND_SIG
- AR_PHY_FIND_SIG_FIRPWR
- AR_PHY_FIND_SIG_FIRPWR_S
- AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT
- AR_PHY_FIND_SIG_FIRSTEP
- AR_PHY_FIND_SIG_FIRSTEP_LOW
- AR_PHY_FIND_SIG_FIRSTEP_LOW_S
- AR_PHY_FIND_SIG_FIRSTEP_S
- AR_PHY_FIND_SIG_LOW
- AR_PHY_FIND_SIG_LOW_FIRPWR
- AR_PHY_FIND_SIG_LOW_FIRPWR_S
- AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT
- AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
- AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S
- AR_PHY_FIND_SIG_LOW_RELSTEP
- AR_PHY_FIND_SIG_LOW_RELSTEP_S
- AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT
- AR_PHY_FIND_SIG_RELPWR
- AR_PHY_FIND_SIG_RELPWR_S
- AR_PHY_FIND_SIG_RELPWR_SIGN_BIT
- AR_PHY_FIND_SIG_RELSTEP
- AR_PHY_FIND_SIG_RELSTEP_S
- AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT
- AR_PHY_FLC_PWR_THRESH
- AR_PHY_FLC_PWR_THRESH_S
- AR_PHY_FORCEMAX_GAINS_0
- AR_PHY_FORCEMAX_GAINS_1
- AR_PHY_FORCEMAX_GAINS_2
- AR_PHY_FORCE_CLKEN_CCK
- AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
- AR_PHY_FORCE_XPA_CFG
- AR_PHY_FORCE_XPA_CFG_S
- AR_PHY_FRAME_CTL
- AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW
- AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S
- AR_PHY_FRAME_CTL_TX_CLIP
- AR_PHY_FRAME_CTL_TX_CLIP_S
- AR_PHY_GAINS_MINOFF0
- AR_PHY_GAIN_2GHZ
- AR_PHY_GAIN_2GHZ_BSW_ATTEN
- AR_PHY_GAIN_2GHZ_BSW_ATTEN_S
- AR_PHY_GAIN_2GHZ_BSW_MARGIN
- AR_PHY_GAIN_2GHZ_BSW_MARGIN_S
- AR_PHY_GAIN_2GHZ_RXTX_MARGIN
- AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S
- AR_PHY_GAIN_2GHZ_XATTEN1_DB
- AR_PHY_GAIN_2GHZ_XATTEN1_DB_S
- AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
- AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S
- AR_PHY_GAIN_2GHZ_XATTEN2_DB
- AR_PHY_GAIN_2GHZ_XATTEN2_DB_S
- AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
- AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S
- AR_PHY_GC_DYN2040_EN
- AR_PHY_GC_DYN2040_EXT_CH
- AR_PHY_GC_DYN2040_PRI_CH
- AR_PHY_GC_DYN2040_PRI_CH_S
- AR_PHY_GC_DYN2040_PRI_ONLY
- AR_PHY_GC_ENABLE_DAC_FIFO
- AR_PHY_GC_GF_DETECT_EN
- AR_PHY_GC_HT_EN
- AR_PHY_GC_SHORT_GI_40
- AR_PHY_GC_SINGLE_HT_LTF1
- AR_PHY_GC_TURBO_MODE
- AR_PHY_GC_TURBO_SHORT
- AR_PHY_GC_WALSH
- AR_PHY_GEN_CTRL
- AR_PHY_GLB_CONTROL
- AR_PHY_HALFGI
- AR_PHY_HALFGI_DSC_EXP
- AR_PHY_HALFGI_DSC_EXP_S
- AR_PHY_HALFGI_DSC_MAN
- AR_PHY_HALFGI_DSC_MAN_S
- AR_PHY_HEADER_DETECT_XR
- AR_PHY_HEAVYCLIP_1
- AR_PHY_HEAVYCLIP_2
- AR_PHY_HEAVYCLIP_20
- AR_PHY_HEAVYCLIP_3
- AR_PHY_HEAVYCLIP_4
- AR_PHY_HEAVYCLIP_40
- AR_PHY_HEAVYCLIP_5
- AR_PHY_HEAVYCLIP_CTL
- AR_PHY_HEAVY_CLIP_ENABLE
- AR_PHY_HEAVY_CLIP_FACTOR_RIFS
- AR_PHY_ILLEGAL_TXRATE
- AR_PHY_IQCORR_CTRL_CCK
- AR_PHY_IQ_ADC_MEAS_0_B0
- AR_PHY_IQ_ADC_MEAS_0_B0_9300_10
- AR_PHY_IQ_ADC_MEAS_1_B0
- AR_PHY_IQ_ADC_MEAS_1_B0_9300_10
- AR_PHY_IQ_ADC_MEAS_2_B0
- AR_PHY_IQ_ADC_MEAS_2_B0_9300_10
- AR_PHY_IQ_ADC_MEAS_3_B0
- AR_PHY_IQ_ADC_MEAS_3_B0_9300_10
- AR_PHY_LDPC_CNTL1
- AR_PHY_LDPC_CNTL2
- AR_PHY_LNAGAIN_LONG_SHIFT
- AR_PHY_LNAGAIN_LONG_SHIFT_S
- AR_PHY_MAC_CLK_MODE
- AR_PHY_MANRXGAIN_LONG_SHIFT
- AR_PHY_MANRXGAIN_LONG_SHIFT_S
- AR_PHY_MASK2_M_00_15
- AR_PHY_MASK2_M_16_30
- AR_PHY_MASK2_M_31_45
- AR_PHY_MASK2_P_15_01
- AR_PHY_MASK2_P_30_16
- AR_PHY_MASK2_P_45_31
- AR_PHY_MASK2_P_61_45
- AR_PHY_MASK_CTL
- AR_PHY_MAX_RX_LEN
- AR_PHY_MC_GAIN_CTRL
- AR_PHY_MINCCA_PWR
- AR_PHY_MINCCA_PWR_S
- AR_PHY_MISC_PA_CTL
- AR_PHY_ML_CNTL_1
- AR_PHY_ML_CNTL_2
- AR_PHY_MODE
- AR_PHY_MODE_AR2133
- AR_PHY_MODE_AR5111
- AR_PHY_MODE_AR5112
- AR_PHY_MODE_ASYNCFIFO
- AR_PHY_MODE_CCK
- AR_PHY_MODE_DYNAMIC
- AR_PHY_MODE_DYNAMIC_S
- AR_PHY_MODE_DYN_CCK_DISABLE
- AR_PHY_MODE_HALF
- AR_PHY_MODE_OFDM
- AR_PHY_MODE_QUARTER
- AR_PHY_MODE_RF2GHZ
- AR_PHY_MODE_RF5GHZ
- AR_PHY_MODE_SVD_HALF
- AR_PHY_MRC_CCK_CTRL
- AR_PHY_MRC_CCK_ENABLE
- AR_PHY_MRC_CCK_ENABLE_S
- AR_PHY_MRC_CCK_MUX_REG
- AR_PHY_MRC_CCK_MUX_REG_S
- AR_PHY_MULTICHAIN_CTRL
- AR_PHY_MULTICHAIN_GAIN_CTL
- AR_PHY_MXRGAIN_LONG_SHIFT
- AR_PHY_MXRGAIN_LONG_SHIFT_S
- AR_PHY_M_SLEEP
- AR_PHY_NEW_ADC_DC_GAIN_CORR
- AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10
- AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE
- AR_PHY_NEW_ADC_GAIN_CORR_ENABLE
- AR_PHY_ONLY_CTL
- AR_PHY_ONLY_WARMRESET
- AR_PHY_PAPRD_AM2AM
- AR_PHY_PAPRD_AM2AM_MASK
- AR_PHY_PAPRD_AM2AM_MASK_S
- AR_PHY_PAPRD_AM2PM
- AR_PHY_PAPRD_AM2PM_MASK
- AR_PHY_PAPRD_AM2PM_MASK_S
- AR_PHY_PAPRD_CTRL0_B0
- AR_PHY_PAPRD_CTRL0_B1
- AR_PHY_PAPRD_CTRL0_B2
- AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE
- AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S
- AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH
- AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S
- AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK
- AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA
- AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S
- AR_PHY_PAPRD_CTRL1_B0
- AR_PHY_PAPRD_CTRL1_B1
- AR_PHY_PAPRD_CTRL1_B2
- AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT
- AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S
- AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL
- AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S
- AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK
- AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S
- AR_PHY_PAPRD_HT40
- AR_PHY_PAPRD_HT40_MASK
- AR_PHY_PAPRD_HT40_MASK_S
- AR_PHY_PAPRD_MEM_TAB_B0
- AR_PHY_PAPRD_MEM_TAB_B1
- AR_PHY_PAPRD_MEM_TAB_B2
- AR_PHY_PAPRD_PRE_POST_SCALE_0_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_1_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_2_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_3_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_4_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_5_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_6_B0
- AR_PHY_PAPRD_PRE_POST_SCALE_7_B0
- AR_PHY_PAPRD_PRE_POST_SCALING
- AR_PHY_PAPRD_PRE_POST_SCALING_S
- AR_PHY_PAPRD_TRAINER_CNTL1
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE
- AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S
- AR_PHY_PAPRD_TRAINER_CNTL2
- AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN
- AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S
- AR_PHY_PAPRD_TRAINER_CNTL3
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP
- AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S
- AR_PHY_PAPRD_TRAINER_CNTL4
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA
- AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S
- AR_PHY_PAPRD_TRAINER_STAT1
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE
- AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S
- AR_PHY_PAPRD_TRAINER_STAT2
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL
- AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S
- AR_PHY_PAPRD_TRAINER_STAT3
- AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT
- AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S
- AR_PHY_PARALLEL_CAL_ENABLE
- AR_PHY_PA_GAIN123_B0
- AR_PHY_PA_GAIN123_B1
- AR_PHY_PA_GAIN123_B2
- AR_PHY_PA_GAIN123_PA_GAIN1
- AR_PHY_PA_GAIN123_PA_GAIN1_S
- AR_PHY_PDADC_TAB
- AR_PHY_PDADC_TAB_0
- AR_PHY_PDADC_TAB_1
- AR_PHY_PEAK_DET_CTRL_1
- AR_PHY_PEAK_DET_CTRL_2
- AR_PHY_PERCHAIN_CSD
- AR_PHY_PILOT_MASK_01_30
- AR_PHY_PILOT_MASK_31_60
- AR_PHY_PILOT_SPUR_MASK
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B
- AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S
- AR_PHY_PLL_CONTROL
- AR_PHY_PLL_CTL
- AR_PHY_PLL_CTL_40
- AR_PHY_PLL_CTL_40_2133
- AR_PHY_PLL_CTL_40_5413
- AR_PHY_PLL_CTL_44
- AR_PHY_PLL_CTL_44_2133
- AR_PHY_PLL_MODE
- AR_PHY_PMU1
- AR_PHY_PMU1_PWD
- AR_PHY_PMU1_PWD_S
- AR_PHY_PMU2
- AR_PHY_PMU2_PGM
- AR_PHY_PMU2_PGM_S
- AR_PHY_POWERTX_RATE5
- AR_PHY_POWERTX_RATE5_POWERTXHT20_0
- AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S
- AR_PHY_POWERTX_RATE6
- AR_PHY_POWERTX_RATE6_POWERTXHT20_5
- AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S
- AR_PHY_POWERTX_RATE8
- AR_PHY_POWERTX_RATE8_POWERTXHT40_5
- AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S
- AR_PHY_POWER_TX_RATE
- AR_PHY_POWER_TX_RATE1
- AR_PHY_POWER_TX_RATE2
- AR_PHY_POWER_TX_RATE3
- AR_PHY_POWER_TX_RATE4
- AR_PHY_POWER_TX_RATE5
- AR_PHY_POWER_TX_RATE6
- AR_PHY_POWER_TX_RATE7
- AR_PHY_POWER_TX_RATE8
- AR_PHY_POWER_TX_RATE9
- AR_PHY_POWER_TX_RATE_MAX
- AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE
- AR_PHY_POWER_TX_SUB
- AR_PHY_PWRTX_MAX
- AR_PHY_RADAR_0
- AR_PHY_RADAR_0_ENA
- AR_PHY_RADAR_0_FFT_ENA
- AR_PHY_RADAR_0_FIRPWR
- AR_PHY_RADAR_0_FIRPWR_S
- AR_PHY_RADAR_0_HEIGHT
- AR_PHY_RADAR_0_HEIGHT_S
- AR_PHY_RADAR_0_INBAND
- AR_PHY_RADAR_0_INBAND_S
- AR_PHY_RADAR_0_PRSSI
- AR_PHY_RADAR_0_PRSSI_S
- AR_PHY_RADAR_0_RRSSI
- AR_PHY_RADAR_0_RRSSI_S
- AR_PHY_RADAR_1
- AR_PHY_RADAR_1_BLOCK_CHECK
- AR_PHY_RADAR_1_MAXLEN
- AR_PHY_RADAR_1_MAXLEN_S
- AR_PHY_RADAR_1_MAX_RRSSI
- AR_PHY_RADAR_1_RELPWR_ENA
- AR_PHY_RADAR_1_RELPWR_THRESH
- AR_PHY_RADAR_1_RELPWR_THRESH_S
- AR_PHY_RADAR_1_RELSTEP_CHECK
- AR_PHY_RADAR_1_RELSTEP_THRESH
- AR_PHY_RADAR_1_RELSTEP_THRESH_S
- AR_PHY_RADAR_1_USE_FIR128
- AR_PHY_RADAR_BW_FILTER
- AR_PHY_RADAR_DC_PWR_THRESH
- AR_PHY_RADAR_DC_PWR_THRESH_S
- AR_PHY_RADAR_EXT
- AR_PHY_RADAR_EXT_ENA
- AR_PHY_RADAR_LB_DC_CAP
- AR_PHY_RADAR_LB_DC_CAP_S
- AR_PHY_REFCLKDLY
- AR_PHY_REFCLKPD
- AR_PHY_RESTART
- AR_PHY_RESTART_DIV_GC
- AR_PHY_RESTART_DIV_GC_S
- AR_PHY_RESTART_ENA
- AR_PHY_RESTART_ENABLE_DIV_M2FLAG
- AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S
- AR_PHY_RFBUS_GRANT
- AR_PHY_RFBUS_GRANT_EN
- AR_PHY_RFBUS_REQ
- AR_PHY_RFBUS_REQ_EN
- AR_PHY_RF_CTL2
- AR_PHY_RF_CTL3
- AR_PHY_RF_CTL4
- AR_PHY_RF_CTL4_FRAME_XPAA_ON
- AR_PHY_RF_CTL4_FRAME_XPAA_ON_S
- AR_PHY_RF_CTL4_FRAME_XPAB_ON
- AR_PHY_RF_CTL4_FRAME_XPAB_ON_S
- AR_PHY_RF_CTL4_TX_END_XPAA_OFF
- AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S
- AR_PHY_RF_CTL4_TX_END_XPAB_OFF
- AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S
- AR_PHY_RIFS
- AR_PHY_RIFS_INIT_DELAY
- AR_PHY_RIFS_SRCH
- AR_PHY_RSSI_0
- AR_PHY_RSSI_1
- AR_PHY_RSSI_2
- AR_PHY_RSSI_3
- AR_PHY_RTT_CTRL
- AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION
- AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S
- AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE
- AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S
- AR_PHY_RTT_CTRL_RESTORE_MASK
- AR_PHY_RTT_CTRL_RESTORE_MASK_S
- AR_PHY_RTT_SW_RTT_TABLE_ACCESS
- AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S
- AR_PHY_RTT_SW_RTT_TABLE_ADDR
- AR_PHY_RTT_SW_RTT_TABLE_ADDR_S
- AR_PHY_RTT_SW_RTT_TABLE_DATA
- AR_PHY_RTT_SW_RTT_TABLE_DATA_S
- AR_PHY_RTT_SW_RTT_TABLE_WRITE
- AR_PHY_RTT_SW_RTT_TABLE_WRITE_S
- AR_PHY_RTT_TABLE_SW_INTF_1_B
- AR_PHY_RTT_TABLE_SW_INTF_B
- AR_PHY_RX1DB_BIQUAD_LONG_SHIFT
- AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S
- AR_PHY_RX6DB_BIQUAD_LONG_SHIFT
- AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S
- AR_PHY_RXGAIN
- AR_PHY_RXGAIN_TXRX_ATTEN
- AR_PHY_RXGAIN_TXRX_ATTEN_S
- AR_PHY_RXGAIN_TXRX_RF_MAX
- AR_PHY_RXGAIN_TXRX_RF_MAX_S
- AR_PHY_RX_CHAINMASK
- AR_PHY_RX_CLR_DELAY
- AR_PHY_RX_DELAY
- AR_PHY_RX_DELAY_DELAY
- AR_PHY_RX_GAIN_BOUNDS_1
- AR_PHY_RX_GAIN_BOUNDS_2
- AR_PHY_RX_IQCAL_CORR_B0
- AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN
- AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S
- AR_PHY_RX_IQCAL_CORR_B1
- AR_PHY_RX_IQCAL_CORR_B2
- AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE
- AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF
- AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S
- AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF
- AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S
- AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF
- AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S
- AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF
- AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S
- AR_PHY_RX_OCGAIN
- AR_PHY_RX_OCGAIN_2
- AR_PHY_SCFIR_GAIN_LONG_SHIFT
- AR_PHY_SCFIR_GAIN_LONG_SHIFT_S
- AR_PHY_SCRAMBLER_SEED
- AR_PHY_SCRM_SEQ_XR
- AR_PHY_SEARCH_START_DELAY
- AR_PHY_SEL_EXTERNAL_RADIO
- AR_PHY_SEL_INTERNAL_ADDAC
- AR_PHY_SETTLING
- AR_PHY_SETTLING_SWITCH
- AR_PHY_SETTLING_SWITCH_S
- AR_PHY_SFCORR
- AR_PHY_SFCORR_EXT
- AR_PHY_SFCORR_EXT_M1_THRESH
- AR_PHY_SFCORR_EXT_M1_THRESH_LOW
- AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S
- AR_PHY_SFCORR_EXT_M1_THRESH_S
- AR_PHY_SFCORR_EXT_M2_THRESH
- AR_PHY_SFCORR_EXT_M2_THRESH_LOW
- AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S
- AR_PHY_SFCORR_EXT_M2_THRESH_S
- AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
- AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S
- AR_PHY_SFCORR_LOW
- AR_PHY_SFCORR_LOW_M1_THRESH_LOW
- AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S
- AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
- AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S
- AR_PHY_SFCORR_LOW_M2_THRESH_LOW
- AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S
- AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
- AR_PHY_SFCORR_M1_THRESH
- AR_PHY_SFCORR_M1_THRESH_S
- AR_PHY_SFCORR_M2COUNT_THR
- AR_PHY_SFCORR_M2COUNT_THR_S
- AR_PHY_SFCORR_M2_THRESH
- AR_PHY_SFCORR_M2_THRESH_S
- AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
- AR_PHY_SGI_DELTA
- AR_PHY_SGI_DSC_EXP
- AR_PHY_SGI_DSC_EXP_S
- AR_PHY_SGI_DSC_MAN
- AR_PHY_SGI_DSC_MAN_S
- AR_PHY_SIGMA_DELTA
- AR_PHY_SIGMA_DELTA_ADC_CLIP
- AR_PHY_SIGMA_DELTA_ADC_CLIP_S
- AR_PHY_SIGMA_DELTA_ADC_SEL
- AR_PHY_SIGMA_DELTA_ADC_SEL_S
- AR_PHY_SIGMA_DELTA_FILT1
- AR_PHY_SIGMA_DELTA_FILT1_S
- AR_PHY_SIGMA_DELTA_FILT2
- AR_PHY_SIGMA_DELTA_FILT2_S
- AR_PHY_SLEEP_CTR_CONTROL
- AR_PHY_SLEEP_CTR_LIMIT
- AR_PHY_SLEEP_SCAL
- AR_PHY_SPECTRAL_SCAN
- AR_PHY_SPECTRAL_SCAN_ACTIVE
- AR_PHY_SPECTRAL_SCAN_ACTIVE_S
- AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT
- AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S
- AR_PHY_SPECTRAL_SCAN_COUNT
- AR_PHY_SPECTRAL_SCAN_COUNT_KIWI
- AR_PHY_SPECTRAL_SCAN_COUNT_KIWI_S
- AR_PHY_SPECTRAL_SCAN_COUNT_S
- AR_PHY_SPECTRAL_SCAN_ENA
- AR_PHY_SPECTRAL_SCAN_ENABLE
- AR_PHY_SPECTRAL_SCAN_ENABLE_S
- AR_PHY_SPECTRAL_SCAN_ENA_S
- AR_PHY_SPECTRAL_SCAN_FFT_PERIOD
- AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S
- AR_PHY_SPECTRAL_SCAN_PERIOD
- AR_PHY_SPECTRAL_SCAN_PERIOD_S
- AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT
- AR_PHY_SPECTRAL_SCAN_PRIORITY
- AR_PHY_SPECTRAL_SCAN_PRIORITY_S
- AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT
- AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI
- AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S
- AR_PHY_SPECTRAL_SCAN_USE_ERR5
- AR_PHY_SPECTRAL_SCAN_USE_ERR5_S
- AR_PHY_SPUR_CCK_REP0
- AR_PHY_SPUR_CCK_REP_1
- AR_PHY_SPUR_MASK_A
- AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
- AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S
- AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
- AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S
- AR_PHY_SPUR_MASK_B
- AR_PHY_SPUR_REG
- AR_PHY_SPUR_REG_ENABLE_MASK_PPM
- AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S
- AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
- AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S
- AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
- AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
- AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S
- AR_PHY_SPUR_REG_MASK_RATE_CNTL
- AR_PHY_SPUR_REG_MASK_RATE_CNTL_S
- AR_PHY_SPUR_REG_MASK_RATE_SELECT
- AR_PHY_SPUR_REG_MASK_RATE_SELECT_S
- AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
- AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S
- AR_PHY_SPUR_REPORT_0
- AR_PHY_SPUR_REPORT_1
- AR_PHY_SPUR_REPORT_2
- AR_PHY_SWAP_ALT_CHAIN
- AR_PHY_SWITCH_CHAIN
- AR_PHY_SWITCH_CHAIN_0
- AR_PHY_SWITCH_CHAIN_1
- AR_PHY_SWITCH_CHAIN_2
- AR_PHY_SWITCH_COM
- AR_PHY_SWITCH_COM_2
- AR_PHY_SYNTH4_LONG_SHIFT_SELECT
- AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S
- AR_PHY_SYNTH_CONTROL
- AR_PHY_TEST
- AR_PHY_TEST2
- AR_PHY_TEST_BBB_OBS_SEL
- AR_PHY_TEST_BBB_OBS_SEL_S
- AR_PHY_TEST_CHAIN_SEL
- AR_PHY_TEST_CHAIN_SEL_S
- AR_PHY_TEST_CTL_DEBUGPORT_SEL
- AR_PHY_TEST_CTL_DEBUGPORT_SEL_S
- AR_PHY_TEST_CTL_RX_OBS_SEL
- AR_PHY_TEST_CTL_RX_OBS_SEL_S
- AR_PHY_TEST_CTL_STATUS
- AR_PHY_TEST_CTL_TSTADC_EN
- AR_PHY_TEST_CTL_TSTADC_EN_S
- AR_PHY_TEST_CTL_TSTDAC_EN
- AR_PHY_TEST_CTL_TSTDAC_EN_S
- AR_PHY_TEST_CTL_TX_OBS_MUX_SEL
- AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S
- AR_PHY_TEST_CTL_TX_OBS_SEL
- AR_PHY_TEST_CTL_TX_OBS_SEL_S
- AR_PHY_TEST_RX_OBS_SEL_BIT5
- AR_PHY_TEST_RX_OBS_SEL_BIT5_S
- AR_PHY_TIMING1
- AR_PHY_TIMING10
- AR_PHY_TIMING10_PILOT_MASK_2
- AR_PHY_TIMING10_PILOT_MASK_2_S
- AR_PHY_TIMING11
- AR_PHY_TIMING11_SPUR_DELTA_PHASE
- AR_PHY_TIMING11_SPUR_DELTA_PHASE_S
- AR_PHY_TIMING11_SPUR_FREQ_SD
- AR_PHY_TIMING11_SPUR_FREQ_SD_S
- AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
- AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S
- AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
- AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S
- AR_PHY_TIMING11_USE_SPUR_IN_AGC
- AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR
- AR_PHY_TIMING2
- AR_PHY_TIMING2_FORCE_PPM_VAL
- AR_PHY_TIMING2_USE_FORCE_PPM
- AR_PHY_TIMING3
- AR_PHY_TIMING3_DSC_EXP
- AR_PHY_TIMING3_DSC_EXP_S
- AR_PHY_TIMING3_DSC_MAN
- AR_PHY_TIMING3_DSC_MAN_S
- AR_PHY_TIMING4
- AR_PHY_TIMING4_DO_CAL
- AR_PHY_TIMING4_ENABLE_CHAN_MASK
- AR_PHY_TIMING4_ENABLE_CHAN_MASK_S
- AR_PHY_TIMING4_ENABLE_PILOT_MASK
- AR_PHY_TIMING4_ENABLE_PILOT_MASK_S
- AR_PHY_TIMING4_ENABLE_SPUR_FILTER
- AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S
- AR_PHY_TIMING4_ENABLE_SPUR_RSSI
- AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S
- AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX
- AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S
- AR_PHY_TIMING5
- AR_PHY_TIMING5_CYCPWR_THR1
- AR_PHY_TIMING5_CYCPWR_THR1A
- AR_PHY_TIMING5_CYCPWR_THR1A_S
- AR_PHY_TIMING5_CYCPWR_THR1_ENABLE
- AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S
- AR_PHY_TIMING5_CYCPWR_THR1_S
- AR_PHY_TIMING5_RSSI_THR1A
- AR_PHY_TIMING5_RSSI_THR1A_ENA
- AR_PHY_TIMING5_RSSI_THR1A_S
- AR_PHY_TIMING6
- AR_PHY_TIMING7
- AR_PHY_TIMING8
- AR_PHY_TIMING8_PILOT_MASK_2
- AR_PHY_TIMING8_PILOT_MASK_2_S
- AR_PHY_TIMING9
- AR_PHY_TIMING_3A
- AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT
- AR_PHY_TIMING_CTRL4
- AR_PHY_TIMING_CTRL4_DO_CAL
- AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
- AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
- AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
- AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
- AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX
- AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S
- AR_PHY_TIMING_CTRL4_IQCORR_ENABLE
- AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
- AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S
- AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
- AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S
- AR_PHY_TPCGR1_FORCED_DAC_GAIN
- AR_PHY_TPCGR1_FORCED_DAC_GAIN_S
- AR_PHY_TPCGR1_FORCE_DAC_GAIN
- AR_PHY_TPCRG1
- AR_PHY_TPCRG1_NUM_PD_GAIN
- AR_PHY_TPCRG1_NUM_PD_GAIN_S
- AR_PHY_TPCRG1_PD_CAL_ENABLE
- AR_PHY_TPCRG1_PD_CAL_ENABLE_S
- AR_PHY_TPCRG1_PD_GAIN_1
- AR_PHY_TPCRG1_PD_GAIN_1_S
- AR_PHY_TPCRG1_PD_GAIN_2
- AR_PHY_TPCRG1_PD_GAIN_2_S
- AR_PHY_TPCRG1_PD_GAIN_3
- AR_PHY_TPCRG1_PD_GAIN_3_S
- AR_PHY_TPCRG5
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4
- AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S
- AR_PHY_TPCRG5_PD_GAIN_OVERLAP
- AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S
- AR_PHY_TPC_1
- AR_PHY_TPC_11_B0
- AR_PHY_TPC_11_B1
- AR_PHY_TPC_11_B2
- AR_PHY_TPC_11_OLPC_GAIN_DELTA
- AR_PHY_TPC_11_OLPC_GAIN_DELTA_S
- AR_PHY_TPC_12
- AR_PHY_TPC_12_DESIRED_SCALE_HT40_5
- AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S
- AR_PHY_TPC_18
- AR_PHY_TPC_18_THERM_CAL_VALUE
- AR_PHY_TPC_18_THERM_CAL_VALUE_S
- AR_PHY_TPC_18_VOLT_CAL_VALUE
- AR_PHY_TPC_18_VOLT_CAL_VALUE_S
- AR_PHY_TPC_19
- AR_PHY_TPC_19_ALPHA_THERM
- AR_PHY_TPC_19_ALPHA_THERM_S
- AR_PHY_TPC_19_ALPHA_VOLT
- AR_PHY_TPC_19_ALPHA_VOLT_S
- AR_PHY_TPC_19_B1
- AR_PHY_TPC_19_B1_ALPHA_THERM
- AR_PHY_TPC_19_B1_ALPHA_THERM_S
- AR_PHY_TPC_19_B2
- AR_PHY_TPC_1_FORCED_DAC_GAIN
- AR_PHY_TPC_1_FORCED_DAC_GAIN_S
- AR_PHY_TPC_1_FORCE_DAC_GAIN
- AR_PHY_TPC_1_FORCE_DAC_GAIN_S
- AR_PHY_TPC_4_B0
- AR_PHY_TPC_4_B1
- AR_PHY_TPC_4_B2
- AR_PHY_TPC_5_B0
- AR_PHY_TPC_5_B1
- AR_PHY_TPC_5_B2
- AR_PHY_TPC_6_B0
- AR_PHY_TPC_6_B1
- AR_PHY_TPC_6_B2
- AR_PHY_TPC_6_ERROR_EST_MODE
- AR_PHY_TPC_6_ERROR_EST_MODE_S
- AR_PHY_TPC_OLPC_GAIN_DELTA
- AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON
- AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S
- AR_PHY_TPC_OLPC_GAIN_DELTA_S
- AR_PHY_TSTDAC
- AR_PHY_TSTDAC_CONST
- AR_PHY_TST_ADC
- AR_PHY_TST_DAC_CONST
- AR_PHY_TURBO
- AR_PHY_TXGAIN_FORCE
- AR_PHY_TXGAIN_FORCED_PADVGNRA
- AR_PHY_TXGAIN_FORCED_PADVGNRA_S
- AR_PHY_TXGAIN_FORCED_PADVGNRB
- AR_PHY_TXGAIN_FORCED_PADVGNRB_S
- AR_PHY_TXGAIN_FORCED_PADVGNRD
- AR_PHY_TXGAIN_FORCED_PADVGNRD_S
- AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN
- AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S
- AR_PHY_TXGAIN_FORCED_TXMXRGAIN
- AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S
- AR_PHY_TXGAIN_FORCE_S
- AR_PHY_TXGAIN_TABLE
- AR_PHY_TXPWRADJ
- AR_PHY_TXPWRADJ_CCK_GAIN_DELTA
- AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S
- AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX
- AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S
- AR_PHY_TX_CRC
- AR_PHY_TX_DESIRED_SCALE_CCK
- AR_PHY_TX_DESIRED_SCALE_CCK_S
- AR_PHY_TX_END_DATA_START
- AR_PHY_TX_END_DATA_START_S
- AR_PHY_TX_END_PA_ON
- AR_PHY_TX_END_PA_ON_S
- AR_PHY_TX_END_TO_A2_RX_ON
- AR_PHY_TX_END_TO_A2_RX_ON_S
- AR_PHY_TX_END_TO_ADC_ON
- AR_PHY_TX_END_TO_ADC_ON_S
- AR_PHY_TX_FORCED_GAIN
- AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL
- AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND
- AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S
- AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN
- AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S
- AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN
- AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S
- AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN
- AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S
- AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN
- AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S
- AR_PHY_TX_GAIN
- AR_PHY_TX_GAIN_CLC
- AR_PHY_TX_GAIN_CLC_S
- AR_PHY_TX_GAIN_S
- AR_PHY_TX_GAIN_TBL1
- AR_PHY_TX_IQCAL_CONTROL_0
- AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL
- AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S
- AR_PHY_TX_IQCAL_CONTROL_1
- AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT
- AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S
- AR_PHY_TX_IQCAL_CONTROL_3
- AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN
- AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S
- AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE
- AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S
- AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE
- AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S
- AR_PHY_TX_IQCAL_CORR_COEFF_B0
- AR_PHY_TX_IQCAL_CORR_COEFF_B1
- AR_PHY_TX_IQCAL_CORR_COEFF_B2
- AR_PHY_TX_IQCAL_START
- AR_PHY_TX_IQCAL_START_DO_CAL
- AR_PHY_TX_IQCAL_START_DO_CAL_S
- AR_PHY_TX_IQCAL_STATUS_B0
- AR_PHY_TX_IQCAL_STATUS_B1
- AR_PHY_TX_IQCAL_STATUS_B2
- AR_PHY_TX_IQCAL_STATUS_B2_FAILED
- AR_PHY_TX_IQCAL_STATUS_FAILED
- AR_PHY_TX_PHASE_RAMP_0
- AR_PHY_TX_PHASE_RAMP_0_9300_10
- AR_PHY_TX_PHASE_RAMP_1
- AR_PHY_TX_PHASE_RAMP_2
- AR_PHY_TX_PWRCTRL10
- AR_PHY_TX_PWRCTRL4
- AR_PHY_TX_PWRCTRL6_0
- AR_PHY_TX_PWRCTRL6_1
- AR_PHY_TX_PWRCTRL7
- AR_PHY_TX_PWRCTRL8
- AR_PHY_TX_PWRCTRL9
- AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
- AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S
- AR_PHY_TX_PWRCTRL_ERR_EST_MODE
- AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S
- AR_PHY_TX_PWRCTRL_INIT_TX_GAIN
- AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S
- AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP
- AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S
- AR_PHY_TX_PWRCTRL_PD_AVG_OUT
- AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S
- AR_PHY_TX_PWRCTRL_PD_AVG_VALID
- AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S
- AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX
- AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S
- AR_PHY_VGAGAIN_LONG_SHIFT
- AR_PHY_VGAGAIN_LONG_SHIFT_S
- AR_PHY_VIT_MASK2_M_46_61
- AR_PHY_WATCHDOG_AGC_SM
- AR_PHY_WATCHDOG_AGC_SM_S
- AR_PHY_WATCHDOG_CNTL2_MASK
- AR_PHY_WATCHDOG_CTL
- AR_PHY_WATCHDOG_CTL_1
- AR_PHY_WATCHDOG_CTL_2
- AR_PHY_WATCHDOG_DET_HANG
- AR_PHY_WATCHDOG_DET_HANG_S
- AR_PHY_WATCHDOG_IDLE_ENABLE
- AR_PHY_WATCHDOG_IDLE_MASK
- AR_PHY_WATCHDOG_INFO
- AR_PHY_WATCHDOG_INFO_S
- AR_PHY_WATCHDOG_IRQ_ENABLE
- AR_PHY_WATCHDOG_NON_IDLE_ENABLE
- AR_PHY_WATCHDOG_NON_IDLE_MASK
- AR_PHY_WATCHDOG_RADAR_SM
- AR_PHY_WATCHDOG_RADAR_SM_S
- AR_PHY_WATCHDOG_RST_ENABLE
- AR_PHY_WATCHDOG_RX_CCK_SM
- AR_PHY_WATCHDOG_RX_CCK_SM_S
- AR_PHY_WATCHDOG_RX_OFDM_SM
- AR_PHY_WATCHDOG_RX_OFDM_SM_S
- AR_PHY_WATCHDOG_SRCH_SM
- AR_PHY_WATCHDOG_SRCH_SM_S
- AR_PHY_WATCHDOG_STATUS
- AR_PHY_WATCHDOG_STATUS_CLR
- AR_PHY_WATCHDOG_TX_CCK_SM
- AR_PHY_WATCHDOG_TX_CCK_SM_S
- AR_PHY_WATCHDOG_TX_OFDM_SM
- AR_PHY_WATCHDOG_TX_OFDM_SM_S
- AR_PHY_XPA_CFG
- AR_PHY_XPA_TIMING_CTL
- AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON
- AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S
- AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON
- AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S
- AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF
- AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S
- AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF
- AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S
- AR_PMCTRL_AUX_PWR_DET
- AR_PMCTRL_D3COLD_VAUX
- AR_PMCTRL_HOST_PME_EN
- AR_PMCTRL_PWR_PM_CTRL_ENA
- AR_PMCTRL_PWR_STATE_D0
- AR_PMCTRL_PWR_STATE_D1D3
- AR_PMCTRL_PWR_STATE_D1D3_REAL
- AR_PMCTRL_PWR_STATE_MASK
- AR_PMCTRL_WOW_PME_CLR
- AR_PM_STATE
- AR_PM_STATE_PME_D3COLD_VAUX
- AR_PTS_PITCH
- AR_PacketDur0
- AR_PacketDur0_S
- AR_PacketDur1
- AR_PacketDur1_S
- AR_PacketDur2
- AR_PacketDur2_S
- AR_PacketDur3
- AR_PacketDur3_S
- AR_PadDelim
- AR_PadDelim_S
- AR_Parallel40
- AR_Parallel40_S
- AR_PostDelimCRCErr
- AR_PowerMgmt
- AR_PreDelimCRCErr
- AR_Q0_CBRCFG
- AR_Q0_MISC
- AR_Q0_RDYTIMECFG
- AR_Q0_STS
- AR_Q0_TXDP
- AR_Q1_CBRCFG
- AR_Q1_MISC
- AR_Q1_RDYTIMECFG
- AR_Q1_STS
- AR_Q1_TXDP
- AR_Q2_CBRCFG
- AR_Q2_MISC
- AR_Q2_RDYTIMECFG
- AR_Q2_STS
- AR_Q2_TXDP
- AR_Q3_CBRCFG
- AR_Q3_MISC
- AR_Q3_RDYTIMECFG
- AR_Q3_STS
- AR_Q3_TXDP
- AR_Q4_CBRCFG
- AR_Q4_MISC
- AR_Q4_RDYTIMECFG
- AR_Q4_STS
- AR_Q4_TXDP
- AR_Q5_CBRCFG
- AR_Q5_MISC
- AR_Q5_RDYTIMECFG
- AR_Q5_STS
- AR_Q5_TXDP
- AR_Q6_CBRCFG
- AR_Q6_MISC
- AR_Q6_RDYTIMECFG
- AR_Q6_STS
- AR_Q6_TXDP
- AR_Q7_CBRCFG
- AR_Q7_MISC
- AR_Q7_RDYTIMECFG
- AR_Q7_STS
- AR_Q7_TXDP
- AR_Q8_CBRCFG
- AR_Q8_MISC
- AR_Q8_RDYTIMECFG
- AR_Q8_STS
- AR_Q8_TXDP
- AR_Q9_CBRCFG
- AR_Q9_MISC
- AR_Q9_RDYTIMECFG
- AR_Q9_STS
- AR_Q9_TXDP
- AR_QCBRCFG
- AR_QCU_0
- AR_QCU_1
- AR_QCU_2
- AR_QCU_3
- AR_QCU_4
- AR_QCU_5
- AR_QCU_6
- AR_QCU_7
- AR_QCU_8
- AR_QCU_9
- AR_QMISC
- AR_QOS_NO_ACK
- AR_QOS_NO_ACK_BIT_OFF
- AR_QOS_NO_ACK_BIT_OFF_S
- AR_QOS_NO_ACK_BYTE_OFF
- AR_QOS_NO_ACK_BYTE_OFF_S
- AR_QOS_NO_ACK_TWO_BIT
- AR_QOS_NO_ACK_TWO_BIT_S
- AR_QRDYTIMECFG
- AR_QSTS
- AR_QTXDP
- AR_QUIET1
- AR_QUIET1_NEXT_QUIET_M
- AR_QUIET1_NEXT_QUIET_S
- AR_QUIET1_QUIET_ACK_CTS_ENABLE
- AR_QUIET1_QUIET_ACK_CTS_ENABLE_S
- AR_QUIET1_QUIET_ENABLE
- AR_QUIET2
- AR_QUIET2_QUIET_DUR
- AR_QUIET2_QUIET_DUR_S
- AR_QUIET2_QUIET_PERIOD_M
- AR_QUIET2_QUIET_PERIOD_S
- AR_QUIET_PERIOD
- AR_QUIET_TIMER_EN
- AR_Q_CBRCFG_INTERVAL
- AR_Q_CBRCFG_INTERVAL_S
- AR_Q_CBRCFG_OVF_THRESH
- AR_Q_CBRCFG_OVF_THRESH_S
- AR_Q_DESC_CRCCHK
- AR_Q_DESC_CRCCHK_EN
- AR_Q_MISC_BEACON_USE
- AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
- AR_Q_MISC_CBR_INCR_DIS0
- AR_Q_MISC_CBR_INCR_DIS1
- AR_Q_MISC_DCU_EARLY_TERM_REQ
- AR_Q_MISC_FSP
- AR_Q_MISC_FSP_ASAP
- AR_Q_MISC_FSP_BEACON_RCVD_GATED
- AR_Q_MISC_FSP_BEACON_SENT_GATED
- AR_Q_MISC_FSP_CBR
- AR_Q_MISC_FSP_DBA_GATED
- AR_Q_MISC_FSP_TIM_GATED
- AR_Q_MISC_ONE_SHOT_EN
- AR_Q_MISC_RDYTIME_EXP_POLICY
- AR_Q_MISC_RESET_CBR_EXP_CTR
- AR_Q_MISC_RESV0
- AR_Q_ONESHOTARM_CC
- AR_Q_ONESHOTARM_CC_M
- AR_Q_ONESHOTARM_CC_RESV0
- AR_Q_ONESHOTARM_SC
- AR_Q_ONESHOTARM_SC_M
- AR_Q_ONESHOTARM_SC_RESV0
- AR_Q_RDYTIMECFG_DURATION
- AR_Q_RDYTIMECFG_DURATION_S
- AR_Q_RDYTIMECFG_EN
- AR_Q_RDYTIMESHDN
- AR_Q_RDYTIMESHDN_M
- AR_Q_STATUS_RING_END
- AR_Q_STATUS_RING_START
- AR_Q_STS_CBR_EXP_CNT
- AR_Q_STS_PEND_FR_CNT
- AR_Q_STS_RESV0
- AR_Q_STS_RESV1
- AR_Q_TXD
- AR_Q_TXD_M
- AR_Q_TXE
- AR_Q_TXE_M
- AR_RAD2122_SREV_MAJOR
- AR_RAD2133_SREV_MAJOR
- AR_RAD5122_SREV_MAJOR
- AR_RAD5133_SREV_MAJOR
- AR_RADIO_SREV_MAJOR
- AR_RATE_DURATION
- AR_RATE_DURATION_0
- AR_RATE_DURATION_31
- AR_RATE_DURATION_32
- AR_RC
- AR_RCCNT
- AR_RC_AHB
- AR_RC_APB
- AR_RC_HOSTIF
- AR_REG
- AR_RESET_CONTROL
- AR_RESET_TSF
- AR_RESET_TSF2_ONCE
- AR_RESET_TSF_ONCE
- AR_RESET_VALUE_MASK
- AR_RFCNT
- AR_RIMT
- AR_RIMT_FIRST
- AR_RIMT_FIRST_S
- AR_RIMT_LAST
- AR_RIMT_LAST_S
- AR_RPCNT
- AR_RPCNT_MASK
- AR_RPGTO
- AR_RPGTO_MASK
- AR_RSSI_BCN_RSSI_RST
- AR_RSSI_BCN_WEIGHT
- AR_RSSI_BCN_WEIGHT_S
- AR_RSSI_THR
- AR_RSSI_THR_BM_THR
- AR_RSSI_THR_BM_THR_S
- AR_RSSI_THR_MASK
- AR_RSVD_KEYTABLE_ENTRIES
- AR_RTC_9160_PLL_CLKSEL
- AR_RTC_9160_PLL_CLKSEL_S
- AR_RTC_9160_PLL_DIV
- AR_RTC_9160_PLL_DIV_S
- AR_RTC_9160_PLL_REFDIV
- AR_RTC_9160_PLL_REFDIV_S
- AR_RTC_9300_PLL_BYPASS
- AR_RTC_9300_PLL_CLKSEL
- AR_RTC_9300_PLL_CLKSEL_S
- AR_RTC_9300_PLL_DIV
- AR_RTC_9300_PLL_DIV_S
- AR_RTC_9300_PLL_REFDIV
- AR_RTC_9300_PLL_REFDIV_S
- AR_RTC_9300_SOC_PLL_BYPASS
- AR_RTC_9300_SOC_PLL_CLKSEL
- AR_RTC_9300_SOC_PLL_CLKSEL_S
- AR_RTC_9300_SOC_PLL_DIV_FRAC
- AR_RTC_9300_SOC_PLL_DIV_FRAC_S
- AR_RTC_9300_SOC_PLL_DIV_INT
- AR_RTC_9300_SOC_PLL_DIV_INT_S
- AR_RTC_9300_SOC_PLL_REFDIV
- AR_RTC_9300_SOC_PLL_REFDIV_S
- AR_RTC_BASE
- AR_RTC_DERIVED_CLK
- AR_RTC_DERIVED_CLK_PERIOD
- AR_RTC_DERIVED_CLK_PERIOD_S
- AR_RTC_FORCE_DERIVED_CLK
- AR_RTC_FORCE_SWREG_PRD
- AR_RTC_FORCE_WAKE
- AR_RTC_FORCE_WAKE_EN
- AR_RTC_FORCE_WAKE_ON_INT
- AR_RTC_INTR_CAUSE
- AR_RTC_INTR_ENABLE
- AR_RTC_INTR_MASK
- AR_RTC_KEEP_AWAKE
- AR_RTC_PLL_BYPASS
- AR_RTC_PLL_CLKSEL
- AR_RTC_PLL_CLKSEL_S
- AR_RTC_PLL_CONTROL
- AR_RTC_PLL_CONTROL2
- AR_RTC_PLL_DIV
- AR_RTC_PLL_DIV2
- AR_RTC_PLL_DIV_S
- AR_RTC_PLL_NOPWD
- AR_RTC_PLL_NOPWD_S
- AR_RTC_PLL_REFDIV_5
- AR_RTC_PM_STATUS_M
- AR_RTC_RC
- AR_RTC_RC_COLD_RESET
- AR_RTC_RC_M
- AR_RTC_RC_MAC_COLD
- AR_RTC_RC_MAC_WARM
- AR_RTC_RC_WARM_RESET
- AR_RTC_REG_CONTROL0
- AR_RTC_REG_CONTROL1
- AR_RTC_REG_CONTROL1_SWREG_PROGRAM
- AR_RTC_RESET
- AR_RTC_RESET_EN
- AR_RTC_SLEEP_CLK
- AR_RTC_STATUS
- AR_RTC_STATUS_M
- AR_RTC_STATUS_ON
- AR_RTC_STATUS_SHUTDOWN
- AR_RTC_STATUS_SLEEP
- AR_RTC_STATUS_WAKEUP
- AR_RTC_XTAL_CONTROL
- AR_RTSCTSQual0
- AR_RTSCTSQual1
- AR_RTSCTSQual2
- AR_RTSCTSQual3
- AR_RTSCTSRate
- AR_RTSCTSRate_S
- AR_RTSEnable
- AR_RTSFailCnt
- AR_RTSFailCnt_S
- AR_RTS_FAIL
- AR_RTS_OK
- AR_RXBP_THRESH
- AR_RXBP_THRESH_HP
- AR_RXBP_THRESH_HP_S
- AR_RXBP_THRESH_LP
- AR_RXBP_THRESH_LP_S
- AR_RXCFG
- AR_RXCFG_CHIRP
- AR_RXCFG_DMASZ_128B
- AR_RXCFG_DMASZ_16B
- AR_RXCFG_DMASZ_256B
- AR_RXCFG_DMASZ_32B
- AR_RXCFG_DMASZ_4B
- AR_RXCFG_DMASZ_512B
- AR_RXCFG_DMASZ_64B
- AR_RXCFG_DMASZ_8B
- AR_RXCFG_DMASZ_MASK
- AR_RXCFG_ZLFDMA
- AR_RXDP
- AR_RXFIFO_CFG
- AR_RXNPTO
- AR_RXNPTO_MASK
- AR_RX_FILTER
- AR_RcvTimestamp
- AR_RxAggr
- AR_RxAntenna
- AR_RxAntenna_S
- AR_RxCTLRsvd00
- AR_RxCtlRsvd00
- AR_RxCtlRsvd01
- AR_RxDone
- AR_RxEVM0
- AR_RxEVM1
- AR_RxEVM2
- AR_RxFirstAggr
- AR_RxFrameOK
- AR_RxIntrReq
- AR_RxKeyIdxValid
- AR_RxMore
- AR_RxMoreAggr
- AR_RxRSSIAnt00
- AR_RxRSSIAnt00_S
- AR_RxRSSIAnt01
- AR_RxRSSIAnt01_S
- AR_RxRSSIAnt02
- AR_RxRSSIAnt02_S
- AR_RxRSSIAnt10
- AR_RxRSSIAnt10_S
- AR_RxRSSIAnt11
- AR_RxRSSIAnt11_S
- AR_RxRSSIAnt12
- AR_RxRSSIAnt12_S
- AR_RxRSSICombined
- AR_RxRSSICombined_S
- AR_RxRate
- AR_RxRate_S
- AR_RxStatusRsvd00
- AR_RxStatusRsvd10
- AR_RxStatusRsvd30
- AR_RxStatusRsvd70
- AR_RxStatusRsvd71
- AR_S
- AR_SELFGEN_MASK
- AR_SEQ_MASK
- AR_SLEEP1
- AR_SLEEP1_ASSUME_DTIM
- AR_SLEEP1_CAB_TIMEOUT
- AR_SLEEP1_CAB_TIMEOUT_S
- AR_SLEEP2
- AR_SLEEP2_BEACON_TIMEOUT
- AR_SLEEP2_BEACON_TIMEOUT_S
- AR_SLOT_BLOCK_SIZE
- AR_SLOT_SIZE
- AR_SLP32_ENA
- AR_SLP32_HALF_CLK_LATENCY
- AR_SLP32_INC
- AR_SLP32_MODE
- AR_SLP32_TSF_WRITE_STATUS
- AR_SLP32_TST_INC
- AR_SLP32_WAKE
- AR_SLP32_WAKE_XTL_TIME
- AR_SLP_CNT
- AR_SLP_CYCLE_CNT
- AR_SLP_MIB_CLEAR
- AR_SLP_MIB_CTRL
- AR_SLP_MIB_PENDING
- AR_SM1_BASE
- AR_SM2_BASE
- AR_SM_BASE
- AR_SPUR_FEEQ_BOUND_HT20
- AR_SPUR_FEEQ_BOUND_HT40
- AR_SREV
- AR_SREV_5416
- AR_SREV_5416_22_OR_LATER
- AR_SREV_9003_PCOEM
- AR_SREV_9100
- AR_SREV_9100_OR_LATER
- AR_SREV_9160
- AR_SREV_9160_10_OR_LATER
- AR_SREV_9160_11
- AR_SREV_9271
- AR_SREV_9271_10
- AR_SREV_9271_11
- AR_SREV_9280
- AR_SREV_9280_20
- AR_SREV_9280_20_OR_LATER
- AR_SREV_9285
- AR_SREV_9285E_20
- AR_SREV_9285_12_OR_LATER
- AR_SREV_9287
- AR_SREV_9287_11
- AR_SREV_9287_11_OR_LATER
- AR_SREV_9287_12
- AR_SREV_9287_12_OR_LATER
- AR_SREV_9287_13_OR_LATER
- AR_SREV_9300
- AR_SREV_9300_20_OR_LATER
- AR_SREV_9300_22
- AR_SREV_9330
- AR_SREV_9330_11
- AR_SREV_9330_12
- AR_SREV_9340
- AR_SREV_9340_13
- AR_SREV_9340_13_OR_LATER
- AR_SREV_9462
- AR_SREV_9462_20
- AR_SREV_9462_20_OR_LATER
- AR_SREV_9462_21
- AR_SREV_9462_21_OR_LATER
- AR_SREV_9485
- AR_SREV_9485_11_OR_LATER
- AR_SREV_9485_OR_LATER
- AR_SREV_9531
- AR_SREV_9531_10
- AR_SREV_9531_11
- AR_SREV_9531_20
- AR_SREV_9550
- AR_SREV_9550_OR_LATER
- AR_SREV_9561
- AR_SREV_9565
- AR_SREV_9565_10
- AR_SREV_9565_101
- AR_SREV_9565_11
- AR_SREV_9565_11_OR_LATER
- AR_SREV_9580
- AR_SREV_9580_10
- AR_SREV_9580_10_OR_LATER
- AR_SREV_ID
- AR_SREV_ID2
- AR_SREV_REVISION
- AR_SREV_REVISION2
- AR_SREV_REVISION2_S
- AR_SREV_REVISION_5416_10
- AR_SREV_REVISION_5416_20
- AR_SREV_REVISION_5416_22
- AR_SREV_REVISION_9160_10
- AR_SREV_REVISION_9160_11
- AR_SREV_REVISION_9271_10
- AR_SREV_REVISION_9271_11
- AR_SREV_REVISION_9280_10
- AR_SREV_REVISION_9280_20
- AR_SREV_REVISION_9280_21
- AR_SREV_REVISION_9285_10
- AR_SREV_REVISION_9285_11
- AR_SREV_REVISION_9285_12
- AR_SREV_REVISION_9287_10
- AR_SREV_REVISION_9287_11
- AR_SREV_REVISION_9287_12
- AR_SREV_REVISION_9287_13
- AR_SREV_REVISION_9300_20
- AR_SREV_REVISION_9300_22
- AR_SREV_REVISION_9330_10
- AR_SREV_REVISION_9330_11
- AR_SREV_REVISION_9330_12
- AR_SREV_REVISION_9340_10
- AR_SREV_REVISION_9340_11
- AR_SREV_REVISION_9340_12
- AR_SREV_REVISION_9340_13
- AR_SREV_REVISION_9462_20
- AR_SREV_REVISION_9462_21
- AR_SREV_REVISION_9485_10
- AR_SREV_REVISION_9485_11
- AR_SREV_REVISION_9531_10
- AR_SREV_REVISION_9531_11
- AR_SREV_REVISION_9531_20
- AR_SREV_REVISION_9565_10
- AR_SREV_REVISION_9565_101
- AR_SREV_REVISION_9565_11
- AR_SREV_REVISION_9580_10
- AR_SREV_SOC
- AR_SREV_TYPE2
- AR_SREV_TYPE2_CHAIN
- AR_SREV_TYPE2_HOST_MODE
- AR_SREV_TYPE2_S
- AR_SREV_VERSION
- AR_SREV_VERSION2
- AR_SREV_VERSION2_S
- AR_SREV_VERSION_5416_PCI
- AR_SREV_VERSION_5416_PCIE
- AR_SREV_VERSION_9100
- AR_SREV_VERSION_9160
- AR_SREV_VERSION_9271
- AR_SREV_VERSION_9280
- AR_SREV_VERSION_9285
- AR_SREV_VERSION_9287
- AR_SREV_VERSION_9300
- AR_SREV_VERSION_9330
- AR_SREV_VERSION_9340
- AR_SREV_VERSION_9462
- AR_SREV_VERSION_9485
- AR_SREV_VERSION_9531
- AR_SREV_VERSION_9550
- AR_SREV_VERSION_9561
- AR_SREV_VERSION_9565
- AR_SREV_VERSION_9580
- AR_SREV_VERSION_S
- AR_STA_ID0
- AR_STA_ID1
- AR_STA_ID1_ACKCTS_6MB
- AR_STA_ID1_ADHOC
- AR_STA_ID1_AR9100_BA_FIX
- AR_STA_ID1_BASE_RATE_11B
- AR_STA_ID1_CBCIV_ENDIAN
- AR_STA_ID1_CRPT_MIC_ENABLE
- AR_STA_ID1_DEFANT_UPDATE
- AR_STA_ID1_KSRCHDIS
- AR_STA_ID1_KSRCH_MODE
- AR_STA_ID1_MCAST_KSRCH
- AR_STA_ID1_PCF
- AR_STA_ID1_PRESERVE_SEQNUM
- AR_STA_ID1_PWR_SAV
- AR_STA_ID1_RTS_USE_DEF
- AR_STA_ID1_SADH_MASK
- AR_STA_ID1_SECTOR_SELF_GEN
- AR_STA_ID1_STA_AP
- AR_STA_ID1_USE_DEFANT
- AR_STBC
- AR_STBC0
- AR_STBC1
- AR_STBC2
- AR_STBC3
- AR_STOMP_ALL_WLAN_WGHT
- AR_STOMP_LOW_WLAN_WGHT
- AR_STOMP_NONE_WLAN_WGHT
- AR_SUBVENDOR_ID_NEW_A
- AR_SUBVENDOR_ID_NOG
- AR_SWBA_PERIOD
- AR_SWBA_TIMER_EN
- AR_SWITCH_TABLE_ALL
- AR_SWITCH_TABLE_ALL_S
- AR_SWITCH_TABLE_COM2_ALL
- AR_SWITCH_TABLE_COM2_ALL_S
- AR_SWITCH_TABLE_COM_ALL
- AR_SWITCH_TABLE_COM_ALL_S
- AR_SWITCH_TABLE_COM_AR9462_ALL
- AR_SWITCH_TABLE_COM_AR9462_ALL_S
- AR_SWITCH_TABLE_COM_AR9550_ALL
- AR_SWITCH_TABLE_COM_AR9550_ALL_S
- AR_SWITCH_TABLE_COM_SPDT
- AR_SWITCH_TABLE_COM_SPDT_ALL
- AR_SWITCH_TABLE_COM_SPDT_ALL_S
- AR_SWITCH_TO_REFCLK
- AR_SW_WOW_CONTROL
- AR_SW_WOW_ENABLE
- AR_SendTimestamp
- AR_SeqNum
- AR_SeqNum_S
- AR_TBTT_TIMER_EN
- AR_TFCNT
- AR_TIMER_MODE
- AR_TIMER_OVERFLOW_INDEX
- AR_TIMER_OVERFLOW_INDEX_S
- AR_TIMER_THRESH
- AR_TIMER_THRESH_S
- AR_TIME_OUT
- AR_TIME_OUT_ACK
- AR_TIME_OUT_ACK_S
- AR_TIME_OUT_CTS
- AR_TIME_OUT_CTS_S
- AR_TIMT
- AR_TIMT_FIRST
- AR_TIMT_FIRST_S
- AR_TIMT_LAST
- AR_TIMT_LAST_S
- AR_TIM_PERIOD
- AR_TIM_TIMER_EN
- AR_TOPS
- AR_TOPS_MASK
- AR_TPC
- AR_TPC_ACK
- AR_TPC_ACK_S
- AR_TPC_CHIRP
- AR_TPC_CHIRP_S
- AR_TPC_CTS
- AR_TPC_CTS_S
- AR_TPC_RPT
- AR_TPC_RPT_S
- AR_TSFOOR_THRESHOLD
- AR_TSFOOR_THRESHOLD_VAL
- AR_TSF_INCREMENT_M
- AR_TSF_INCREMENT_S
- AR_TSF_L32
- AR_TSF_PARM
- AR_TSF_U32
- AR_TST_ADDAC
- AR_TXCFG
- AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
- AR_TXCFG_DMASZ_128B
- AR_TXCFG_DMASZ_16B
- AR_TXCFG_DMASZ_256B
- AR_TXCFG_DMASZ_32B
- AR_TXCFG_DMASZ_4B
- AR_TXCFG_DMASZ_512B
- AR_TXCFG_DMASZ_64B
- AR_TXCFG_DMASZ_8B
- AR_TXCFG_DMASZ_MASK
- AR_TXNPTO
- AR_TXNPTO_MASK
- AR_TXNPTO_QCU_MASK
- AR_TXOP_0_3
- AR_TXOP_12_15
- AR_TXOP_4_7
- AR_TXOP_8_11
- AR_TXOP_X
- AR_TXOP_X_VAL
- AR_TXSIFS
- AR_TXSIFS_ACK_SHIFT
- AR_TXSIFS_ACK_SHIFT_S
- AR_TXSIFS_TIME
- AR_TXSIFS_TX_LATENCY
- AR_TXSIFS_TX_LATENCY_S
- AR_TYPE_MASK
- AR_TYPE_RODATA
- AR_TYPE_RODATA_EXPDOWN
- AR_TYPE_RWDATA
- AR_TYPE_RWDATA_EXPDOWN
- AR_TYPE_WUSB
- AR_TYPE_WUSB_ASSOCIATE
- AR_TYPE_WUSB_RETRIEVE_HOST_INFO
- AR_TYPE_XOCODE
- AR_TYPE_XOCODE_CONF
- AR_TYPE_XRCODE
- AR_TYPE_XRCODE_CONF
- AR_TxBaStatus
- AR_TxCtlRsvd00
- AR_TxCtlRsvd01
- AR_TxCtlRsvd60
- AR_TxCtlRsvd61
- AR_TxDataUnderrun
- AR_TxDelimUnderrun
- AR_TxDescId
- AR_TxDescId_S
- AR_TxDone
- AR_TxEVM0
- AR_TxEVM1
- AR_TxEVM2
- AR_TxIntrReq
- AR_TxMore
- AR_TxOpExceeded
- AR_TxPtrChkSum
- AR_TxQcuNum
- AR_TxQcuNum_S
- AR_TxRSSIAnt00
- AR_TxRSSIAnt00_S
- AR_TxRSSIAnt01
- AR_TxRSSIAnt01_S
- AR_TxRSSIAnt02
- AR_TxRSSIAnt02_S
- AR_TxRSSIAnt10
- AR_TxRSSIAnt10_S
- AR_TxRSSIAnt11
- AR_TxRSSIAnt11_S
- AR_TxRSSIAnt12
- AR_TxRSSIAnt12_S
- AR_TxRSSICombined
- AR_TxRSSICombined_S
- AR_TxRxDesc
- AR_TxRxDesc_S
- AR_TxStatusRsvd00
- AR_TxStatusRsvd01
- AR_TxStatusRsvd10
- AR_TxStatusRsvd80
- AR_TxStatusRsvd81
- AR_TxStatusRsvd82
- AR_TxStatusRsvd83
- AR_TxTid
- AR_TxTid_S
- AR_TxTimerExpired
- AR_USEC
- AR_USEC_ASYNC_FIFO
- AR_USEC_RX_LAT
- AR_USEC_RX_LAT_S
- AR_USEC_TX_LAT
- AR_USEC_TX_LAT_S
- AR_USEC_USEC
- AR_VEOL
- AR_VirtMoreFrag
- AR_VirtRetryCnt
- AR_VirtRetryCnt_S
- AR_WA
- AR_WA_ANALOG_SHIFT
- AR_WA_ASPM_TIMER_BASED_DISABLE
- AR_WA_BIT22
- AR_WA_BIT23
- AR_WA_BIT6
- AR_WA_BIT7
- AR_WA_D3_L1_DISABLE
- AR_WA_D3_TO_L1_DISABLE_REAL
- AR_WA_DEFAULT
- AR_WA_POR_SHORT
- AR_WA_RESET_EN
- AR_WA_UNTIE_RESET_EN
- AR_WOW2_PATTERN_EN
- AR_WOW2_PATTERN_FOUND
- AR_WOW2_PATTERN_FOUND_MASK
- AR_WOW2_PATTERN_FOUND_SHIFT
- AR_WOW_AIFS_CNT
- AR_WOW_BACK_OFF_SHIFT
- AR_WOW_BCN_EN
- AR_WOW_BCN_TIMO
- AR_WOW_BEACON_FAIL
- AR_WOW_BEACON_FAIL_EN
- AR_WOW_BEACON_TIMO
- AR_WOW_BEACON_TIMO_MAX
- AR_WOW_BMISSTHRESHOLD
- AR_WOW_CLEAR_EVENTS
- AR_WOW_CLEAR_EVENTS2
- AR_WOW_CNT_AIFS_CNT
- AR_WOW_CNT_KA_CNT
- AR_WOW_CNT_SLOT_CNT
- AR_WOW_COUNT
- AR_WOW_KA_DESC_WORD2
- AR_WOW_KEEP_ALIVE
- AR_WOW_KEEP_ALIVE_AUTO_DIS
- AR_WOW_KEEP_ALIVE_CNT
- AR_WOW_KEEP_ALIVE_DELAY
- AR_WOW_KEEP_ALIVE_DELAY_VALUE
- AR_WOW_KEEP_ALIVE_FAIL
- AR_WOW_KEEP_ALIVE_FAIL_DIS
- AR_WOW_KEEP_ALIVE_NEVER
- AR_WOW_KEEP_ALIVE_TIMO
- AR_WOW_LEN1_SHIFT
- AR_WOW_LEN2_SHIFT
- AR_WOW_LEN3_SHIFT
- AR_WOW_LEN4_SHIFT
- AR_WOW_LENGTH1
- AR_WOW_LENGTH1_MASK
- AR_WOW_LENGTH2
- AR_WOW_LENGTH2_MASK
- AR_WOW_LENGTH3
- AR_WOW_LENGTH3_MASK
- AR_WOW_LENGTH4
- AR_WOW_LENGTH4_MASK
- AR_WOW_LENGTH_MAX
- AR_WOW_MAC_INTR
- AR_WOW_MAC_INTR_EN
- AR_WOW_MAGIC_EN
- AR_WOW_MAGIC_PAT_FOUND
- AR_WOW_PATTERN
- AR_WOW_PATTERN_EN
- AR_WOW_PATTERN_FOUND
- AR_WOW_PATTERN_FOUND_MASK
- AR_WOW_PATTERN_MATCH
- AR_WOW_PATTERN_MATCH_LT_256B
- AR_WOW_PATTERN_SUPPORTED
- AR_WOW_PATTERN_SUPPORTED_LEGACY
- AR_WOW_PAT_BACKOFF
- AR_WOW_PAT_END_OF_PKT
- AR_WOW_PAT_FOUND_SHIFT
- AR_WOW_PAT_OFF_MATCH
- AR_WOW_SLOT_CNT
- AR_WOW_STATUS
- AR_WOW_STATUS2
- AR_WOW_TB_MASK
- AR_WOW_TB_PATTERN
- AR_WOW_TRANSMIT_BUFFER
- AR_WOW_TXBUF
- AR_WRAPAROUND_PAGES
- AR_XmitDataTries0
- AR_XmitDataTries0_S
- AR_XmitDataTries1
- AR_XmitDataTries1_S
- AR_XmitDataTries2
- AR_XmitDataTries2_S
- AR_XmitDataTries3
- AR_XmitDataTries3_S
- AR_XmitPower0
- AR_XmitPower0_S
- AR_XmitPower1
- AR_XmitPower1_S
- AR_XmitPower2
- AR_XmitPower2_S
- AR_XmitPower3
- AR_XmitPower3_S
- AR_XmitRate0
- AR_XmitRate0_S
- AR_XmitRate1
- AR_XmitRate1_S
- AR_XmitRate2
- AR_XmitRate2_S
- AR_XmitRate3
- AR_XmitRate3_S
- AS102_DEVICE_MAJOR
- AS102_ELGATO_EYETV_DTT_NAME
- AS102_NBOX_DVBT_DONGLE_NAME
- AS102_PCTV_74E
- AS102_REFERENCE_DESIGN
- AS102_SKY_IT_DIGITAL_KEY_NAME
- AS102_USB_BUF_SIZE
- AS102_USB_DEVICE_PID_0001
- AS102_USB_DEVICE_RX_CTRL_CMD
- AS102_USB_DEVICE_TX_CTRL_CMD
- AS102_USB_DEVICE_VENDOR_ID
- AS10X_CMD_ERROR
- AS3711_ASIC_ID_1
- AS3711_ASIC_ID_2
- AS3711_BACKLIGHT
- AS3711_BL_SU1
- AS3711_BL_SU2
- AS3711_CHARGER_STATUS_1
- AS3711_CHARGER_STATUS_2
- AS3711_CURR1_VALUE
- AS3711_CURR2_VALUE
- AS3711_CURR3_VALUE
- AS3711_CURR_CONTROL
- AS3711_GPIO_SIGNAL_IN
- AS3711_GPIO_SIGNAL_OUT
- AS3711_INTERRUPT_STATUS_1
- AS3711_INTERRUPT_STATUS_2
- AS3711_INTERRUPT_STATUS_3
- AS3711_LDO_1_VOLTAGE
- AS3711_LDO_2_VOLTAGE
- AS3711_LDO_3_VOLTAGE
- AS3711_LDO_4_VOLTAGE
- AS3711_LDO_5_VOLTAGE
- AS3711_LDO_6_VOLTAGE
- AS3711_LDO_7_VOLTAGE
- AS3711_LDO_8_VOLTAGE
- AS3711_MAX_LDO
- AS3711_MAX_REG
- AS3711_MAX_STEPDOWN
- AS3711_MAX_STEPUP
- AS3711_NUM_REGS
- AS3711_REG
- AS3711_REGULATOR
- AS3711_REGULATOR_LDO_1
- AS3711_REGULATOR_LDO_2
- AS3711_REGULATOR_LDO_3
- AS3711_REGULATOR_LDO_4
- AS3711_REGULATOR_LDO_5
- AS3711_REGULATOR_LDO_6
- AS3711_REGULATOR_LDO_7
- AS3711_REGULATOR_LDO_8
- AS3711_REGULATOR_MAX
- AS3711_REGULATOR_NUM
- AS3711_REGULATOR_SD_1
- AS3711_REGULATOR_SD_2
- AS3711_REGULATOR_SD_3
- AS3711_REGULATOR_SD_4
- AS3711_REG_STATUS
- AS3711_SD_1_VOLTAGE
- AS3711_SD_2_VOLTAGE
- AS3711_SD_3_VOLTAGE
- AS3711_SD_4_VOLTAGE
- AS3711_SD_CONTROL
- AS3711_SD_CONTROL_1
- AS3711_SD_CONTROL_2
- AS3711_STEPUP_CONTROL_1
- AS3711_STEPUP_CONTROL_2
- AS3711_STEPUP_CONTROL_4
- AS3711_STEPUP_CONTROL_5
- AS3711_SU2_CURR1
- AS3711_SU2_CURR2
- AS3711_SU2_CURR3
- AS3711_SU2_CURR_AUTO
- AS3711_SU2_GPIO2
- AS3711_SU2_GPIO3
- AS3711_SU2_GPIO4
- AS3711_SU2_LX_SD4
- AS3711_SU2_VOLTAGE
- AS3722_ADC0_CONTROL_REG
- AS3722_ADC0_CONV_NOTREADY
- AS3722_ADC0_CONV_START
- AS3722_ADC0_LSB_RESULT_REG
- AS3722_ADC0_MSB_RESULT_REG
- AS3722_ADC0_SOURCE_SELECT_MASK
- AS3722_ADC1_CONTROL_REG
- AS3722_ADC1_CONV_NOTREADY
- AS3722_ADC1_CONV_START
- AS3722_ADC1_INTERVAL_TIME
- AS3722_ADC1_INTEVAL_SCAN
- AS3722_ADC1_INT_MASK
- AS3722_ADC1_INT_MODE_ON
- AS3722_ADC1_LOW_VOLTAGE_RANGE
- AS3722_ADC1_LSB_RESULT_REG
- AS3722_ADC1_MSB_RESULT_REG
- AS3722_ADC1_SOURCE_SELECT_MASK
- AS3722_ADC1_THRESHOLD_HI_LSB_REG
- AS3722_ADC1_THRESHOLD_HI_MSB_REG
- AS3722_ADC1_THRESHOLD_LO_LSB_REG
- AS3722_ADC1_THRESHOLD_LO_MSB_REG
- AS3722_ADC_BUF_ON
- AS3722_ADC_CONFIGURATION_REG
- AS3722_ADC_LSB_VAL_MASK
- AS3722_ADC_MSB_VAL_MASK
- AS3722_ASIC_ID1_REG
- AS3722_ASIC_ID2_REG
- AS3722_BATTERY_VOLTAGE_MONITOR2_REG
- AS3722_BATTERY_VOLTAGE_MONITOR_REG
- AS3722_BB_CHARGER_REG
- AS3722_CTRL_SEQU1_AC_OK_PWR_ON
- AS3722_CTRL_SEQU1_REG
- AS3722_CTRL_SEQU2_REG
- AS3722_CTRL_STATUS
- AS3722_DEVICE_ID
- AS3722_ENABLE_CTRL1_REG
- AS3722_ENABLE_CTRL2_REG
- AS3722_ENABLE_CTRL3_REG
- AS3722_ENABLE_CTRL4_REG
- AS3722_ENABLE_CTRL5_REG
- AS3722_EXT_CONTROL_ENABLE1
- AS3722_EXT_CONTROL_ENABLE2
- AS3722_EXT_CONTROL_ENABLE3
- AS3722_EXT_CONTROL_PIN_ENABLE1
- AS3722_EXT_CONTROL_PIN_ENABLE2
- AS3722_EXT_CONTROL_PIN_ENABLE3
- AS3722_FUSE7_REG
- AS3722_FUSE7_SD0_LOW_VOLTAGE
- AS3722_GPIO0_CONTROL_REG
- AS3722_GPIO1_CONTROL_REG
- AS3722_GPIO2_CONTROL_REG
- AS3722_GPIO3_CONTROL_REG
- AS3722_GPIO4_CONTROL_REG
- AS3722_GPIO5_CONTROL_REG
- AS3722_GPIO6_CONTROL_REG
- AS3722_GPIO7_CONTROL_REG
- AS3722_GPIO_DEB1_REG
- AS3722_GPIO_DEB2_REG
- AS3722_GPIO_INV
- AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN
- AS3722_GPIO_IOSF_INTERRUPT_OUT
- AS3722_GPIO_IOSF_ISINK_PWM_IN
- AS3722_GPIO_IOSF_MASK
- AS3722_GPIO_IOSF_NORMAL
- AS3722_GPIO_IOSF_PWM_OUT
- AS3722_GPIO_IOSF_PWR_GOOD_OUT
- AS3722_GPIO_IOSF_Q32K_OUT
- AS3722_GPIO_IOSF_SD0_OUT
- AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW
- AS3722_GPIO_IOSF_SOFT_RESET_IN
- AS3722_GPIO_IOSF_VAL
- AS3722_GPIO_IOSF_VOLTAGE_STBY
- AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT
- AS3722_GPIO_IOSF_VSUP_LOW_OUT
- AS3722_GPIO_IOSF_WATCHDOG_IN
- AS3722_GPIO_MODE_ADC_IN
- AS3722_GPIO_MODE_HIGH_IMPED
- AS3722_GPIO_MODE_INPUT
- AS3722_GPIO_MODE_INPUT_PULL_DOWN
- AS3722_GPIO_MODE_INPUT_PULL_UP
- AS3722_GPIO_MODE_IO_OPEN_DRAIN
- AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP
- AS3722_GPIO_MODE_MASK
- AS3722_GPIO_MODE_OPEN_DRAIN
- AS3722_GPIO_MODE_OUTPUT_VDDH
- AS3722_GPIO_MODE_OUTPUT_VDDL
- AS3722_GPIO_MODE_PULL_DOWN
- AS3722_GPIO_MODE_PULL_UP
- AS3722_GPIO_MODE_VAL
- AS3722_GPIO_SIGNAL_IN_REG
- AS3722_GPIO_SIGNAL_OUT_REG
- AS3722_GPIOn_CONTROL_REG
- AS3722_GPIOn_SIGNAL
- AS3722_I2C_PULL_UP
- AS3722_INTERRUPT_MASK1_ACOK
- AS3722_INTERRUPT_MASK1_ENABLE1
- AS3722_INTERRUPT_MASK1_LID
- AS3722_INTERRUPT_MASK1_LOWBAT
- AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0
- AS3722_INTERRUPT_MASK1_ONKEY
- AS3722_INTERRUPT_MASK1_ONKEY_LONG
- AS3722_INTERRUPT_MASK1_OVTMP
- AS3722_INTERRUPT_MASK1_REG
- AS3722_INTERRUPT_MASK2_ENABLE2
- AS3722_INTERRUPT_MASK2_PWM1_OV_PROT
- AS3722_INTERRUPT_MASK2_PWM2_OV_PROT
- AS3722_INTERRUPT_MASK2_REG
- AS3722_INTERRUPT_MASK2_RTC_REP
- AS3722_INTERRUPT_MASK2_SD0_LV
- AS3722_INTERRUPT_MASK2_SD1_LV
- AS3722_INTERRUPT_MASK2_SD2345_LV
- AS3722_INTERRUPT_MASK2_SD6_LV
- AS3722_INTERRUPT_MASK3_ENABLE3
- AS3722_INTERRUPT_MASK3_GPIO1
- AS3722_INTERRUPT_MASK3_GPIO2
- AS3722_INTERRUPT_MASK3_GPIO3
- AS3722_INTERRUPT_MASK3_GPIO4
- AS3722_INTERRUPT_MASK3_GPIO5
- AS3722_INTERRUPT_MASK3_REG
- AS3722_INTERRUPT_MASK3_RTC_ALARM
- AS3722_INTERRUPT_MASK3_WATCHDOG
- AS3722_INTERRUPT_MASK4_ADC
- AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6
- AS3722_INTERRUPT_MASK4_REG
- AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM
- AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN
- AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM
- AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN
- AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM
- AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN
- AS3722_INTERRUPT_STATUS1_REG
- AS3722_INTERRUPT_STATUS2_REG
- AS3722_INTERRUPT_STATUS3_REG
- AS3722_INTERRUPT_STATUS4_REG
- AS3722_INT_PULL_UP
- AS3722_IOVOLTAGE_REG
- AS3722_IRQ_ACOK
- AS3722_IRQ_ADC
- AS3722_IRQ_ENABLE1
- AS3722_IRQ_ENABLE2
- AS3722_IRQ_ENABLE3
- AS3722_IRQ_GPIO1
- AS3722_IRQ_GPIO2
- AS3722_IRQ_GPIO3
- AS3722_IRQ_GPIO4
- AS3722_IRQ_GPIO5
- AS3722_IRQ_LID
- AS3722_IRQ_LOWBAT
- AS3722_IRQ_MAX
- AS3722_IRQ_OCCUR_ALARM_SD0
- AS3722_IRQ_OCCUR_ALARM_SD6
- AS3722_IRQ_ONKEY
- AS3722_IRQ_ONKEY_LONG_PRESS
- AS3722_IRQ_OVTMP
- AS3722_IRQ_PWM1_OV_PROT
- AS3722_IRQ_PWM2_OV_PROT
- AS3722_IRQ_RTC_ALARM
- AS3722_IRQ_RTC_REP
- AS3722_IRQ_SD0_LV
- AS3722_IRQ_SD1_LV
- AS3722_IRQ_SD2_LV
- AS3722_IRQ_SD6_LV
- AS3722_IRQ_TEMP_SD0_ALARM
- AS3722_IRQ_TEMP_SD0_SHUTDOWN
- AS3722_IRQ_TEMP_SD1_ALARM
- AS3722_IRQ_TEMP_SD1_SHUTDOWN
- AS3722_IRQ_TEMP_SD2_SHUTDOWN
- AS3722_IRQ_TEMP_SD6_ALARM
- AS3722_IRQ_WATCHDOG
- AS3722_LDO0_CTRL
- AS3722_LDO0_EXT_ENABLE_MASK
- AS3722_LDO0_NUM_VOLT
- AS3722_LDO0_VOLTAGE_REG
- AS3722_LDO0_VSEL_MASK
- AS3722_LDO0_VSEL_MAX
- AS3722_LDO0_VSEL_MIN
- AS3722_LDO10_CTRL
- AS3722_LDO10_EXT_ENABLE_MASK
- AS3722_LDO10_VOLTAGE_REG
- AS3722_LDO11_CTRL
- AS3722_LDO11_EXT_ENABLE_MASK
- AS3722_LDO11_VOLTAGE_REG
- AS3722_LDO1_CTRL
- AS3722_LDO1_EXT_ENABLE_MASK
- AS3722_LDO1_VOLTAGE_REG
- AS3722_LDO2_CTRL
- AS3722_LDO2_EXT_ENABLE_MASK
- AS3722_LDO2_VOLTAGE_REG
- AS3722_LDO3_CTRL
- AS3722_LDO3_EXT_ENABLE_MASK
- AS3722_LDO3_MODE_MASK
- AS3722_LDO3_MODE_NMOS
- AS3722_LDO3_MODE_PMOS
- AS3722_LDO3_MODE_PMOS_TRACKING
- AS3722_LDO3_MODE_SWITCH
- AS3722_LDO3_MODE_VAL
- AS3722_LDO3_NUM_VOLT
- AS3722_LDO3_VOLTAGE_REG
- AS3722_LDO3_VSEL_MASK
- AS3722_LDO3_VSEL_MAX
- AS3722_LDO3_VSEL_MIN
- AS3722_LDO4_CTRL
- AS3722_LDO4_EXT_ENABLE_MASK
- AS3722_LDO4_VOLTAGE_REG
- AS3722_LDO5_CTRL
- AS3722_LDO5_EXT_ENABLE_MASK
- AS3722_LDO5_VOLTAGE_REG
- AS3722_LDO6_CTRL
- AS3722_LDO6_EXT_ENABLE_MASK
- AS3722_LDO6_VOLTAGE_REG
- AS3722_LDO6_VSEL_BYPASS
- AS3722_LDO7_CTRL
- AS3722_LDO7_EXT_ENABLE_MASK
- AS3722_LDO7_VOLTAGE_REG
- AS3722_LDO9_CTRL
- AS3722_LDO9_EXT_ENABLE_MASK
- AS3722_LDO9_VOLTAGE_REG
- AS3722_LDOCONTROL0_REG
- AS3722_LDOCONTROL1_REG
- AS3722_LDO_ILIMIT_BIT
- AS3722_LDO_ILIMIT_MASK
- AS3722_LDO_NUM_VOLT
- AS3722_LDO_VSEL_DNU_MAX
- AS3722_LDO_VSEL_DNU_MIN
- AS3722_LDO_VSEL_MASK
- AS3722_LDO_VSEL_MAX
- AS3722_LDO_VSEL_MIN
- AS3722_LOCK_REG
- AS3722_MAX_REGISTER
- AS3722_OC_PG_CTRL2_REG
- AS3722_OC_PG_CTRL_REG
- AS3722_OVCURRENT_DEB_REG
- AS3722_OVCURRENT_REG
- AS3722_OVCURRENT_SD0_ALARM_MASK
- AS3722_OVCURRENT_SD0_ALARM_SHIFT
- AS3722_OVCURRENT_SD0_TRIP_MASK
- AS3722_OVCURRENT_SD0_TRIP_SHIFT
- AS3722_OVCURRENT_SD1_TRIP_MASK
- AS3722_OVCURRENT_SD1_TRIP_SHIFT
- AS3722_OVCURRENT_SD6_ALARM_MASK
- AS3722_OVCURRENT_SD6_ALARM_SHIFT
- AS3722_OVCURRENT_SD6_TRIP_MASK
- AS3722_OVCURRENT_SD6_TRIP_SHIFT
- AS3722_OVER_TEMP_CONTROL_REG
- AS3722_PINGROUP
- AS3722_PINMUX_CLK32K_OUT
- AS3722_PINMUX_GPIO
- AS3722_PINMUX_GPIO_INTERRUPT
- AS3722_PINMUX_INTERRUPT_OUT
- AS3722_PINMUX_OC_PG_SD0
- AS3722_PINMUX_OC_PG_SD6
- AS3722_PINMUX_PG_OUT
- AS3722_PINMUX_PWM_INPUT
- AS3722_PINMUX_PWM_OUTPUT
- AS3722_PINMUX_SOFT_RESET_IN
- AS3722_PINMUX_VOLTAGE_IN_STBY
- AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT
- AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT
- AS3722_PINMUX_WATCHDOG_INPUT
- AS3722_PIN_GPIO0
- AS3722_PIN_GPIO1
- AS3722_PIN_GPIO2
- AS3722_PIN_GPIO3
- AS3722_PIN_GPIO4
- AS3722_PIN_GPIO5
- AS3722_PIN_GPIO6
- AS3722_PIN_GPIO7
- AS3722_PIN_NUM
- AS3722_POWER_OFF
- AS3722_PWM_CONTROL_H_REG
- AS3722_PWM_CONTROL_L_REG
- AS3722_PWM_VCONTROL1_REG
- AS3722_PWM_VCONTROL2_REG
- AS3722_PWM_VCONTROL3_REG
- AS3722_PWM_VCONTROL4_REG
- AS3722_REFERENCE_CONTROL_REG
- AS3722_REGULATOR_ID_LDO0
- AS3722_REGULATOR_ID_LDO1
- AS3722_REGULATOR_ID_LDO10
- AS3722_REGULATOR_ID_LDO11
- AS3722_REGULATOR_ID_LDO2
- AS3722_REGULATOR_ID_LDO3
- AS3722_REGULATOR_ID_LDO4
- AS3722_REGULATOR_ID_LDO5
- AS3722_REGULATOR_ID_LDO6
- AS3722_REGULATOR_ID_LDO7
- AS3722_REGULATOR_ID_LDO9
- AS3722_REGULATOR_ID_MAX
- AS3722_REGULATOR_ID_SD0
- AS3722_REGULATOR_ID_SD1
- AS3722_REGULATOR_ID_SD2
- AS3722_REGULATOR_ID_SD3
- AS3722_REGULATOR_ID_SD4
- AS3722_REGULATOR_ID_SD5
- AS3722_REGULATOR_ID_SD6
- AS3722_REG_SEQU_MOD1_REG
- AS3722_REG_SEQU_MOD2_REG
- AS3722_REG_SEQU_MOD3_REG
- AS3722_REG_STANDBY_MOD1_REG
- AS3722_REG_STANDBY_MOD2_REG
- AS3722_REG_STANDBY_MOD3_REG
- AS3722_RESET_CONTROL_REG
- AS3722_RESET_REASON_REG
- AS3722_RESET_TIMER_REG
- AS3722_RTC_ACCESS_REG
- AS3722_RTC_ALARM_DAY_REG
- AS3722_RTC_ALARM_HOUR_REG
- AS3722_RTC_ALARM_MINUTE_REG
- AS3722_RTC_ALARM_MONTH_REG
- AS3722_RTC_ALARM_SECOND_REG
- AS3722_RTC_ALARM_WAKEUP_EN
- AS3722_RTC_ALARM_YEAR_REG
- AS3722_RTC_CLK32K_OUT_EN
- AS3722_RTC_CONTROL_REG
- AS3722_RTC_DAY_REG
- AS3722_RTC_HOUR_REG
- AS3722_RTC_IRQMODE
- AS3722_RTC_MINUTE_REG
- AS3722_RTC_MONTH_REG
- AS3722_RTC_ON
- AS3722_RTC_REP_WAKEUP_EN
- AS3722_RTC_SECOND_REG
- AS3722_RTC_START_YEAR
- AS3722_RTC_STATUS_REG
- AS3722_RTC_YEAR_REG
- AS3722_SD0_CONTROL_REG
- AS3722_SD0_EXT_ENABLE_MASK
- AS3722_SD0_MODE_FAST
- AS3722_SD0_PROTECT_REG
- AS3722_SD0_VOLTAGE_REG
- AS3722_SD0_VSEL_LOW_VOL_MAX
- AS3722_SD0_VSEL_MAX
- AS3722_SD0_VSEL_MIN
- AS3722_SD1_CONTROL_REG
- AS3722_SD1_EXT_ENABLE_MASK
- AS3722_SD1_MODE_FAST
- AS3722_SD1_VOLTAGE_REG
- AS3722_SD23_CONTROL_REG
- AS3722_SD2_EXT_ENABLE_MASK
- AS3722_SD2_MODE_FAST
- AS3722_SD2_VOLTAGE_REG
- AS3722_SD2_VSEL_MAX
- AS3722_SD2_VSEL_MIN
- AS3722_SD3_EXT_ENABLE_MASK
- AS3722_SD3_MODE_FAST
- AS3722_SD3_VOLTAGE_REG
- AS3722_SD4_CONTROL_REG
- AS3722_SD4_EXT_ENABLE_MASK
- AS3722_SD4_MODE_FAST
- AS3722_SD4_VOLTAGE_REG
- AS3722_SD5_CONTROL_REG
- AS3722_SD5_EXT_ENABLE_MASK
- AS3722_SD5_MODE_FAST
- AS3722_SD5_VOLTAGE_REG
- AS3722_SD6_CONTROL_REG
- AS3722_SD6_EXT_ENABLE_MASK
- AS3722_SD6_MODE_FAST
- AS3722_SD6_PROTECT_REG
- AS3722_SD6_VOLTAGE_REG
- AS3722_SDLV_DEB_REG
- AS3722_SD_CONTROL_REG
- AS3722_SD_DVM_REG
- AS3722_SD_PHSW_CTRL_REG
- AS3722_SD_PHSW_STATUS
- AS3722_SD_VSEL_MASK
- AS3722_SDmph_CONTROL_REG
- AS3722_SDn_CTRL
- AS3722_SRAM_REG
- AS3722_STARTUP_CONTROL_REG
- AS3722_TEMP_STATUS_REG
- AS3722_WATCHDOG_CONTROL_REG
- AS3722_WATCHDOG_ON
- AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG
- AS3722_WATCHDOG_SW_SIG
- AS3722_WATCHDOG_TIMER_MAX
- AS3722_WATCHDOG_TIMER_REG
- AS3935_ADDRESS
- AS3935_AFE_GAIN
- AS3935_AFE_GAIN_MAX
- AS3935_AFE_MASK
- AS3935_AFE_PWR_BIT
- AS3935_CALIBRATE
- AS3935_DATA
- AS3935_DATA_MASK
- AS3935_DEFAULTS
- AS3935_DISTURB_INT
- AS3935_EVENT_INT
- AS3935_INT
- AS3935_INT_MASK
- AS3935_NFLWDTH
- AS3935_NFLWDTH_MASK
- AS3935_NOISE_INT
- AS3935_PM_OPS
- AS3935_READ_DATA
- AS3935_TUNE_CAP
- AS5011_CTRL1
- AS5011_CTRL1_DATA_VALID
- AS5011_CTRL1_EXT_CLK_EN
- AS5011_CTRL1_INT_ACT_EN
- AS5011_CTRL1_INT_WUP_EN
- AS5011_CTRL1_LP_ACTIVE
- AS5011_CTRL1_LP_CONTINUE
- AS5011_CTRL1_LP_PULSED
- AS5011_CTRL1_SOFT_RST
- AS5011_CTRL2
- AS5011_CTRL2_EXT_SAMPLE_EN
- AS5011_CTRL2_INV_SPINNING
- AS5011_CTRL2_RC_BIAS_ON
- AS5011_FLAT
- AS5011_FUZZ
- AS5011_MAX_AXIS
- AS5011_MIN_AXIS
- AS5011_XN
- AS5011_XP
- AS5011_X_REG
- AS5011_X_RES_INT
- AS5011_YN
- AS5011_YP
- AS5011_Y_REG
- AS5011_Y_RES_INT
- ASA_BASE
- ASB100_IN_MAX
- ASB100_IN_MIN
- ASB100_PWM_FROM_REG
- ASB100_PWM_TO_REG
- ASB100_REG_ALARM1
- ASB100_REG_ALARM2
- ASB100_REG_BANK
- ASB100_REG_CHIPID
- ASB100_REG_CHIPMAN
- ASB100_REG_CONFIG
- ASB100_REG_FAN
- ASB100_REG_FAN_MIN
- ASB100_REG_I2C_ADDR
- ASB100_REG_I2C_SUBADDR
- ASB100_REG_IN
- ASB100_REG_IN_MAX
- ASB100_REG_IN_MIN
- ASB100_REG_IRQ
- ASB100_REG_PIN
- ASB100_REG_PWM1
- ASB100_REG_SMIM1
- ASB100_REG_SMIM2
- ASB100_REG_TEMP
- ASB100_REG_TEMP2_CONFIG
- ASB100_REG_TEMP3_CONFIG
- ASB100_REG_TEMP_HYST
- ASB100_REG_TEMP_MAX
- ASB100_REG_VID_FANDIV
- ASB100_REG_WCHIPID
- ASB100_TEMP_MAX
- ASB100_TEMP_MIN
- ASB_ACK
- ASB_AXI_BRDG_ID
- ASB_BRDG_VERSION
- ASB_CALL_HELPER
- ASB_CONSENSUS
- ASB_CPR_CTRL
- ASB_DISCARD_LEAST_CHG
- ASB_DISCARD_LOCAL
- ASB_DISCARD_OLDER_PRI
- ASB_DISCARD_REMOTE
- ASB_DISCARD_SECONDARY
- ASB_DISCARD_YOUNGER_PRI
- ASB_DISCARD_ZERO_CHG
- ASB_DISCONNECT
- ASB_EMPTY
- ASB_FULL
- ASB_H264_M_CTRL
- ASB_H264_S_CTRL
- ASB_ISP_M_CTRL
- ASB_ISP_S_CTRL
- ASB_READ
- ASB_REQ_STOP
- ASB_V3D_M_CTRL
- ASB_V3D_S_CTRL
- ASB_VIOLENTLY
- ASB_WRITE
- ASC
- ASCBPTR
- ASCCLC_DISS
- ASCCLC_RMCMASK
- ASCCLC_RMCOFFSET
- ASCCON_BRS
- ASCCON_FDE
- ASCCON_FEN
- ASCCON_M_7ASYNC
- ASCCON_M_8ASYNC
- ASCCON_ODD
- ASCCON_R
- ASCCON_ROEN
- ASCCON_STP
- ASCCON_TOEN
- ASCEBC
- ASCEBC_500
- ASCEEP_CONFIG
- ASCE_TYPE_REGION1
- ASCE_TYPE_REGION2
- ASCE_TYPE_REGION3
- ASCE_TYPE_SEGMENT
- ASCFSTAT_RXFFLMASK
- ASCFSTAT_TXFFLMASK
- ASCFSTAT_TXFREEMASK
- ASCFSTAT_TXFREEOFF
- ASCII85_BUFSZ
- ASCII_DISPLAY_POS_BASE
- ASCII_DISPLAY_WORD_BASE
- ASCII_FLAG
- ASCII_NULL
- ASCOPT_CSIZE
- ASCOT2E_AUTO
- ASCOT2E_BW_1_7
- ASCOT2E_BW_6
- ASCOT2E_BW_7
- ASCOT2E_BW_8
- ASCOT2E_DTV_DVBC2_6
- ASCOT2E_DTV_DVBC2_8
- ASCOT2E_DTV_DVBC_6
- ASCOT2E_DTV_DVBC_8
- ASCOT2E_DTV_DVBT2_1_7
- ASCOT2E_DTV_DVBT2_5
- ASCOT2E_DTV_DVBT2_6
- ASCOT2E_DTV_DVBT2_7
- ASCOT2E_DTV_DVBT2_8
- ASCOT2E_DTV_DVBT_5
- ASCOT2E_DTV_DVBT_6
- ASCOT2E_DTV_DVBT_7
- ASCOT2E_DTV_DVBT_8
- ASCOT2E_DTV_UNKNOWN
- ASCOT2E_OFFSET
- ASCQ
- ASCQ_04H_ALUA_OFFLINE
- ASCQ_04H_ALUA_STATE_TRANSITION
- ASCQ_04H_ALUA_TG_PT_STANDBY
- ASCQ_04H_ALUA_TG_PT_UNAVAILABLE
- ASCQ_29H_BUS_DEVICE_RESET_FUNCTION_OCCURRED
- ASCQ_29H_DEVICE_INTERNAL_RESET
- ASCQ_29H_NEXUS_LOSS_OCCURRED
- ASCQ_29H_POWER_ON_OCCURRED
- ASCQ_29H_POWER_ON_RESET_OR_BUS_DEVICE_RESET_OCCURED
- ASCQ_29H_SCSI_BUS_RESET_OCCURED
- ASCQ_29H_TRANSCEIVER_MODE_CHANGED_TO_LVD
- ASCQ_29H_TRANSCEIVER_MODE_CHANGED_TO_SINGLE_ENDED
- ASCQ_2AH_ASYMMETRIC_ACCESS_STATE_CHANGED
- ASCQ_2AH_IMPLICIT_ASYMMETRIC_ACCESS_STATE_TRANSITION_FAILED
- ASCQ_2AH_LOG_PARAMETERS_CHANGED
- ASCQ_2AH_MODE_PARAMETERS_CHANGED
- ASCQ_2AH_PARAMETERS_CHANGED
- ASCQ_2AH_PRIORITY_CHANGED
- ASCQ_2AH_REGISTRATIONS_PREEMPTED
- ASCQ_2AH_RESERVATIONS_PREEMPTED
- ASCQ_2AH_RESERVATIONS_RELEASED
- ASCQ_2CH_PREVIOUS_RESERVATION_CONFLICT_STATUS
- ASCQ_3FH_INQUIRY_DATA_HAS_CHANGED
- ASCQ_3FH_REPORTED_LUNS_DATA_HAS_CHANGED
- ASCQ_ERR_CRITICAL_RE_ENTRY
- ASCQ_ERR_CUR_QNG
- ASCQ_ERR_ISR_ON_CRITICAL
- ASCQ_ERR_ISR_RE_ENTRY
- ASCQ_ERR_Q_STATUS
- ASCQ_ERR_SG_Q_LINKS
- ASCQ_INVLD_CDB
- ASCQ_INVLD_PARA
- ASCQ_LOAD_EJCT_ERR
- ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS
- ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ
- ASCQ_LU_NOT_READY
- ASCQ_MEDIA_IN_PROCESS
- ASCQ_MISCMP
- ASCQ_NO_INFO
- ASCQ_READ_ERR
- ASCQ_WRITE_ERR
- ASCQ_WRITE_PROTECT
- ASCR
- ASCRXFCON_RXFEN
- ASCRXFCON_RXFFLU
- ASCRXFCON_RXFITLMASK
- ASCRXFCON_RXFITLOFF
- ASCR_D1S
- ASCR_D2S
- ASCR_D3S
- ASCR_RDH
- ASCSTATE_ANY
- ASCSTATE_FE
- ASCSTATE_PE
- ASCSTATE_ROE
- ASCTXFCON_TXFEN
- ASCTXFCON_TXFFLU
- ASCTXFCON_TXFITLMASK
- ASCTXFCON_TXFITLOFF
- ASCV_ASCDVC_ERR_CODE_W
- ASCV_BREAK_ADDR
- ASCV_BREAK_CONTROL
- ASCV_BREAK_HIT_COUNT
- ASCV_BREAK_NOTIFY_COUNT
- ASCV_BREAK_SAVED_CODE
- ASCV_BUSY_QHEAD_B
- ASCV_CAN_TAGGED_QNG_B
- ASCV_CHKSUM_W
- ASCV_CURCDB_B
- ASCV_DISC1_QHEAD_B
- ASCV_DISC_ENABLE_B
- ASCV_DONENEXT_B
- ASCV_DONE_Q_TAIL_B
- ASCV_DONE_Q_TAIL_W
- ASCV_DVC_ERR_CODE_B
- ASCV_FREE_Q_HEAD_B
- ASCV_FREE_Q_HEAD_W
- ASCV_HALTCODE_SAVED_W
- ASCV_HALTCODE_W
- ASCV_HOSTSCSI_ID_B
- ASCV_HOST_FLAG_B
- ASCV_MAX_DVC_QNG_BEG
- ASCV_MCODE_CHKSUM_W
- ASCV_MCODE_CNTL_B
- ASCV_MCODE_SIZE_W
- ASCV_MC_DATE_W
- ASCV_MC_VER_W
- ASCV_MSGIN_BEG
- ASCV_MSGIN_SDTR_OFFSET
- ASCV_MSGIN_SDTR_PERIOD
- ASCV_MSGOUT_BEG
- ASCV_MSGOUT_SDTR_OFFSET
- ASCV_MSGOUT_SDTR_PERIOD
- ASCV_NEXTRDY_B
- ASCV_NULL_TARGET_B
- ASCV_OVERRUN_BSIZE_D
- ASCV_OVERRUN_PADDR_D
- ASCV_Q_DONE_IN_PROGRESS_B
- ASCV_RCLUN_B
- ASCV_REQ_SG_LIST_QP
- ASCV_RISC_FLAG_B
- ASCV_SCSIBUSY_B
- ASCV_SDTR_DATA_BEG
- ASCV_SDTR_DONE_BEG
- ASCV_STOP_CODE_B
- ASCV_TOTAL_READY_Q_B
- ASCV_USE_TAGGED_QNG_B
- ASCV_VER_SERIAL_B
- ASCV_WTM_FLAG_B
- ASCWHBSTATE_CLRFE
- ASCWHBSTATE_CLRPE
- ASCWHBSTATE_CLRREN
- ASCWHBSTATE_CLRROE
- ASCWHBSTATE_SETREN
- ASC_1000_ID0W
- ASC_1000_ID0W_FIX
- ASC_1000_ID1B
- ASC_ALL_DEVICE_BIT_SET
- ASC_BAUDRATE
- ASC_BIOS_ADDR_DEF
- ASC_BIOS_BANK_SIZE
- ASC_BIOS_DATA_QBEG
- ASC_BIOS_MAX_ADDR
- ASC_BIOS_MIN_ADDR
- ASC_BIOS_RAM_OFF
- ASC_BIOS_RAM_SIZE
- ASC_BIOS_SIZE
- ASC_BUF
- ASC_BUF_BASE
- ASC_BUF_SIZE
- ASC_BUG_FIX_ASYN_USE_SYN
- ASC_BUG_FIX_IF_NOT_DWB
- ASC_BUSY
- ASC_CAP_INFO
- ASC_CAP_INFO_ARRAY
- ASC_CFG0_BIOS_ON
- ASC_CFG0_HOST_INT_ON
- ASC_CFG0_SCSI_PARITY_ON
- ASC_CFG0_VERA_BURST_ON
- ASC_CFG1_LRAM_8BITS_ON
- ASC_CFG1_SCSI_TARGET_ON
- ASC_CFG_MSW_CLR_MASK
- ASC_CHAN
- ASC_CHIP_LATEST_VER_EISA
- ASC_CHIP_MAX_VER_EISA
- ASC_CHIP_MAX_VER_ISA
- ASC_CHIP_MAX_VER_PCI
- ASC_CHIP_MAX_VER_VL
- ASC_CHIP_MIN_VER_EISA
- ASC_CHIP_MIN_VER_ISA
- ASC_CHIP_MIN_VER_ISA_PNP
- ASC_CHIP_MIN_VER_PCI
- ASC_CHIP_MIN_VER_VL
- ASC_CHIP_VER_ASYN_BUG
- ASC_CHIP_VER_EISA_BIT
- ASC_CHIP_VER_ISAPNP_BIT
- ASC_CHIP_VER_ISA_BIT
- ASC_CHIP_VER_PCI
- ASC_CHIP_VER_PCI_BIT
- ASC_CHIP_VER_PCI_ULTRA_3050
- ASC_CHIP_VER_PCI_ULTRA_3150
- ASC_CNTL_BIOS_GT_1GB
- ASC_CNTL_BIOS_GT_2_DISK
- ASC_CNTL_BIOS_REMOVABLE
- ASC_CNTL_BURST_MODE
- ASC_CNTL_INITIATOR
- ASC_CNTL_INIT_INQUIRY
- ASC_CNTL_INIT_VERBOSE
- ASC_CNTL_INT_MULTI_Q
- ASC_CNTL_NO_LUN_SUPPORT
- ASC_CNTL_NO_SCAM
- ASC_CNTL_NO_VERIFY_COPY
- ASC_CNTL_RESET_SCSI
- ASC_CNTL_SCSI_PARITY
- ASC_CNTL_SDTR_ENABLE_ULTRA
- ASC_CODE_SEC_BEG
- ASC_CODE_SEC_END
- ASC_CONTROL
- ASC_CONTROL_OFF
- ASC_CS_TYPE
- ASC_CTL
- ASC_CTL_BAUDMODE
- ASC_CTL_CTSENABLE
- ASC_CTL_FIFOENABLE
- ASC_CTL_LOOPBACK
- ASC_CTL_MODE_7BIT_PAR
- ASC_CTL_MODE_8BIT
- ASC_CTL_MODE_8BIT_PAR
- ASC_CTL_MODE_8BIT_WKUP
- ASC_CTL_MODE_9BIT
- ASC_CTL_MODE_MSK
- ASC_CTL_PARITYODD
- ASC_CTL_RUN
- ASC_CTL_RXENABLE
- ASC_CTL_SCENABLE
- ASC_CTL_STOP_1BIT
- ASC_CTL_STOP_1_HALFBIT
- ASC_CTL_STOP_2BIT
- ASC_CTL_STOP_HALFBIT
- ASC_CTL_STOP_MSK
- ASC_CTRL_OFF
- ASC_DATA_SEC_BEG
- ASC_DATA_SEC_END
- ASC_DBG
- ASC_DBG_PRT_ADV_SCSI_REQ_Q
- ASC_DBG_PRT_ASC_QDONE_INFO
- ASC_DBG_PRT_ASC_SCSI_Q
- ASC_DBG_PRT_CDB
- ASC_DBG_PRT_HEX
- ASC_DBG_PRT_INQUIRY
- ASC_DBG_PRT_SCSI_HOST
- ASC_DBG_PRT_SENSE
- ASC_DEF_CHIP_SCSI_ID
- ASC_DEF_DVC_CNTL
- ASC_DEF_ISA_DMA_SPEED
- ASC_DEF_MAX_DVC_QNG
- ASC_DEF_MAX_HOST_QNG
- ASC_DEF_MAX_TOTAL_QNG
- ASC_DEF_MIN_DVC_QNG
- ASC_DEF_MIN_HOST_QNG
- ASC_DEF_SCSI1_QNG
- ASC_DEF_SCSI2_QNG
- ASC_DEF_SDTR_OFFSET
- ASC_DRV2_SEL
- ASC_DVC_CFG
- ASC_DVC_INQ_INFO
- ASC_DVC_VAR
- ASC_EEPROM_WORDS
- ASC_EEP_CMD_DONE
- ASC_EEP_CMD_READ
- ASC_EEP_CMD_WRITE
- ASC_EEP_CMD_WRITE_ABLE
- ASC_EEP_CMD_WRITE_DISABLE
- ASC_EEP_DVC_CFG_BEG
- ASC_EEP_DVC_CFG_BEG_VL
- ASC_EEP_GET_CHIP_ID
- ASC_EEP_GET_DMA_SPD
- ASC_EEP_MAX_DVC_ADDR
- ASC_EEP_MAX_DVC_ADDR_VL
- ASC_EEP_MAX_RETRY
- ASC_EEP_SET_CHIP_ID
- ASC_EEP_SET_DMA_SPD
- ASC_EISA_CFG_IOP_MASK
- ASC_EISA_REV_IOP_MASK
- ASC_ENABLE
- ASC_ENABLE_SAMPLE
- ASC_ERROR
- ASC_FALSE
- ASC_FIFO_SIZE
- ASC_FLAG_BIOS_ASYNC_IO
- ASC_FLAG_BIOS_SCSIQ_REQ
- ASC_FLAG_DOS_VM_CALLBACK
- ASC_FLAG_ISA_OVER_16MB
- ASC_FLAG_SCSIQ_REQ
- ASC_FLAG_SRB_LINEAR_ADDR
- ASC_FLAG_WIN16
- ASC_FLAG_WIN32
- ASC_FREQ
- ASC_GET_EISA_SLOT
- ASC_GUARDTIME
- ASC_GUARDTIME_MSK
- ASC_HALT_CHK_CONDITION
- ASC_HALT_DISABLE_ASYN_USE_SYN_FIX
- ASC_HALT_ENABLE_ASYN_USE_SYN_FIX
- ASC_HALT_EXTMSG_IN
- ASC_HALT_HOST_COPY_SG_LIST_TO_RISC
- ASC_HALT_SDTR_REJECTED
- ASC_HALT_SS_QUEUE_FULL
- ASC_HOST_FLAG_ACK_INT
- ASC_HOST_FLAG_IN_ISR
- ASC_IERR_BAD_CHIPTYPE
- ASC_IERR_BAD_SIGNATURE
- ASC_IERR_BIST_PRE_TEST
- ASC_IERR_BIST_RAM_TEST
- ASC_IERR_HVD_DEVICE
- ASC_IERR_ILLEGAL_CONNECTION
- ASC_IERR_MCODE_CHKSUM
- ASC_IERR_NO_BUS_TYPE
- ASC_IERR_NO_CARRIER
- ASC_IERR_REVERSED_CABLE
- ASC_IERR_SET_PC_ADDR
- ASC_IERR_SET_SCSI_ID
- ASC_IERR_SINGLE_END_DEVICE
- ASC_IERR_START_STOP_CHIP
- ASC_INFO_SIZE
- ASC_INIT_RESET_SCSI_DONE
- ASC_INIT_STATE_BEG_GET_CFG
- ASC_INIT_STATE_BEG_INQUIRY
- ASC_INIT_STATE_BEG_LOAD_MC
- ASC_INIT_STATE_BEG_SET_CFG
- ASC_INIT_STATE_END_GET_CFG
- ASC_INIT_STATE_END_INQUIRY
- ASC_INIT_STATE_END_LOAD_MC
- ASC_INIT_STATE_END_SET_CFG
- ASC_INIT_STATE_WITHOUT_EEP
- ASC_INTEN
- ASC_INTEN_FE
- ASC_INTEN_OE
- ASC_INTEN_PE
- ASC_INTEN_RBE
- ASC_INTEN_RHF
- ASC_INTEN_TE
- ASC_INTEN_THE
- ASC_INTEN_TNE
- ASC_INTEN_TOI
- ASC_INVLD_CDB
- ASC_INVLD_PARA
- ASC_IOADR_GAP
- ASC_IOADR_TABLE_MAX_IX
- ASC_IRNCR_EIR
- ASC_IRNCR_MASK
- ASC_IRNCR_RIR
- ASC_IRNCR_TIR
- ASC_IRNREN_ERR
- ASC_IRNREN_RX
- ASC_IRNREN_TX
- ASC_IRNREN_TX_BUF
- ASC_IS_BIG_ENDIAN
- ASC_IS_EISA
- ASC_IS_ISA
- ASC_IS_ISAPNP
- ASC_IS_MCA
- ASC_IS_PCI
- ASC_IS_PCI_ULTRA
- ASC_IS_PCMCIA
- ASC_IS_VL
- ASC_IS_WIDESCSI_16
- ASC_IS_WIDESCSI_32
- ASC_IS_WIDE_BOARD
- ASC_LOAD_EJCT_ERR
- ASC_LPT_IRQ7
- ASC_LUN_NOT_READY
- ASC_LUN_NOT_SUPPORTED
- ASC_LU_NOT_READY
- ASC_MAX_CDB_LEN
- ASC_MAX_INRAM_TAG_QNG
- ASC_MAX_ISA_DMA_COUNT
- ASC_MAX_LUN
- ASC_MAX_MGS_LEN
- ASC_MAX_PCI_DMA_COUNT
- ASC_MAX_PCI_INRAM_TOTAL_QNG
- ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG
- ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG
- ASC_MAX_PORTS
- ASC_MAX_QNO
- ASC_MAX_SCSI1_QNG
- ASC_MAX_SCSI2_QNG
- ASC_MAX_SCSI_RESET_WAIT
- ASC_MAX_SENSE_LEN
- ASC_MAX_SG_LIST
- ASC_MAX_SG_QUEUE
- ASC_MAX_TID
- ASC_MAX_TOTAL_QNG
- ASC_MAX_VL_DMA_COUNT
- ASC_MCNTL_NO_SEL_TIMEOUT
- ASC_MCNTL_NULL_TARGET
- ASC_MCODE_START_ADDR
- ASC_MC_BIOSLEN
- ASC_MC_BIOSMEM
- ASC_MC_BIOS_SIGNATURE
- ASC_MC_BIOS_VERSION
- ASC_MC_CAM_MODE_MASK
- ASC_MC_CHIP_TYPE
- ASC_MC_CODE_BEGIN_ADDR
- ASC_MC_CODE_CHK_SUM
- ASC_MC_CODE_END_ADDR
- ASC_MC_CONTROL_FLAG
- ASC_MC_DEFAULT_MEM_CFG
- ASC_MC_DEFAULT_SCSI_CFG0
- ASC_MC_DEFAULT_SCSI_CFG1
- ASC_MC_DEFAULT_SEL_MASK
- ASC_MC_DEVICE_HSHK_CFG_TABLE
- ASC_MC_DISC_ENABLE
- ASC_MC_ICQ
- ASC_MC_IDLE_CMD
- ASC_MC_IDLE_CMD_PARAMETER
- ASC_MC_IDLE_CMD_STATUS
- ASC_MC_INTRB_CODE
- ASC_MC_IRQ
- ASC_MC_NUMBER_OF_MAX_CMD
- ASC_MC_NUMBER_OF_QUEUED_CMD
- ASC_MC_PPR_ABLE
- ASC_MC_SAVED
- ASC_MC_SAVE_CODE_WSIZE
- ASC_MC_SAVE_DATA_WSIZE
- ASC_MC_SDTR_ABLE
- ASC_MC_SDTR_DONE
- ASC_MC_SDTR_SPEED1
- ASC_MC_SDTR_SPEED2
- ASC_MC_SDTR_SPEED3
- ASC_MC_SDTR_SPEED4
- ASC_MC_TAGQNG_ABLE
- ASC_MC_VERSION_DATE
- ASC_MC_VERSION_NUM
- ASC_MC_WDTR_ABLE
- ASC_MC_WDTR_DONE
- ASC_MEDIA_CHANGED
- ASC_MEDIA_IN_PROCESS
- ASC_MEDIA_NOT_PRESENT
- ASC_MIN_ACTIVE_QNO
- ASC_MIN_FREE_Q
- ASC_MIN_SENSE_LEN
- ASC_MIN_TAGGED_CMD
- ASC_MIN_TAG_Q_PER_DVC
- ASC_MIN_TOTAL_QNG
- ASC_MISCMP
- ASC_MODE
- ASC_MODE_SAMPLE
- ASC_NARROW_BOARD
- ASC_NOERROR
- ASC_NO_INFO
- ASC_OVERRUN_BSIZE
- ASC_PRINT
- ASC_PRINT1
- ASC_PRINT2
- ASC_PRINT3
- ASC_PRINT4
- ASC_QADR_BEG
- ASC_QADR_END
- ASC_QADR_USED
- ASC_QBLK_SIZE
- ASC_QC_DATA_CHECK
- ASC_QC_DATA_OUT
- ASC_QC_FREEZE_TIDQ
- ASC_QC_NO_OVERRUN
- ASC_QC_START_MOTOR
- ASC_QDONE_INFO
- ASC_QLAST_ADR
- ASC_QLINK_END
- ASC_QNO_TO_QADDR
- ASC_QSC_HEAD_TAG
- ASC_QSC_NO_DISC
- ASC_QSC_NO_SYNC
- ASC_QSC_NO_TAGMSG
- ASC_QSC_NO_WIDE
- ASC_QSC_ORDERED_TAG
- ASC_QSC_REDO_DTR
- ASC_READ_ERR
- ASC_RESERVED
- ASC_RETRIES
- ASC_RETRIES_MSK
- ASC_RISC_FLAG_GEN_INT
- ASC_RISC_FLAG_REQ_SG_LIST
- ASC_RISC_Q
- ASC_RISC_SG_LIST_Q
- ASC_RXBUF
- ASC_RXBUF_DUMMY_BE
- ASC_RXBUF_DUMMY_OE
- ASC_RXBUF_DUMMY_RX
- ASC_RXBUF_FE
- ASC_RXBUF_MSK
- ASC_RXBUF_PE
- ASC_RXRESET
- ASC_SCSIQ_1
- ASC_SCSIQ_2
- ASC_SCSIQ_3
- ASC_SCSIQ_4
- ASC_SCSIQ_B_BWD
- ASC_SCSIQ_B_CDB_LEN
- ASC_SCSIQ_B_CNTL
- ASC_SCSIQ_B_CUR_LIST_CNT
- ASC_SCSIQ_B_FIRST_SG_WK_QP
- ASC_SCSIQ_B_FWD
- ASC_SCSIQ_B_LIST_CNT
- ASC_SCSIQ_B_QNO
- ASC_SCSIQ_B_SENSE_LEN
- ASC_SCSIQ_B_SG_QUEUE_CNT
- ASC_SCSIQ_B_SG_WK_IX
- ASC_SCSIQ_B_SG_WK_QP
- ASC_SCSIQ_B_STATUS
- ASC_SCSIQ_B_TAG_CODE
- ASC_SCSIQ_B_TARGET_IX
- ASC_SCSIQ_CDB_BEG
- ASC_SCSIQ_CPY_BEG
- ASC_SCSIQ_DONE_INFO_BEG
- ASC_SCSIQ_DONE_STATUS
- ASC_SCSIQ_DW_REMAIN_XFER_ADDR
- ASC_SCSIQ_DW_REMAIN_XFER_CNT
- ASC_SCSIQ_D_DATA_ADDR
- ASC_SCSIQ_D_DATA_CNT
- ASC_SCSIQ_D_SRBPTR
- ASC_SCSIQ_HOST_STATUS
- ASC_SCSIQ_SCSI_STATUS
- ASC_SCSIQ_SGHD_CPY_BEG
- ASC_SCSIQ_W_ALT_DC1
- ASC_SCSIQ_W_VM_ID
- ASC_SCSI_BIOS_REQ_Q
- ASC_SCSI_BIT_ID_TYPE
- ASC_SCSI_ID_BITS
- ASC_SCSI_Q
- ASC_SCSI_RESET_HOLD_TIME_US
- ASC_SCSI_TIX_TYPE
- ASC_SCSI_WIDTH_BIT_SET
- ASC_SDTR_ULTRA_PCI_10MB_INDEX
- ASC_SERIAL_CONSOLE
- ASC_SERIAL_NAME
- ASC_SGQ_B_SG_CNTL
- ASC_SGQ_B_SG_CUR_LIST_CNT
- ASC_SGQ_B_SG_HEAD_QP
- ASC_SGQ_B_SG_LIST_CNT
- ASC_SGQ_LIST_BEG
- ASC_SG_HEAD
- ASC_SG_LIST
- ASC_SG_LIST_PER_Q
- ASC_SG_LIST_Q
- ASC_STA
- ASC_STATS
- ASC_STATS_ADD
- ASC_STA_FE
- ASC_STA_NKD
- ASC_STA_OE
- ASC_STA_OFF
- ASC_STA_PE
- ASC_STA_RBF
- ASC_STA_RHF
- ASC_STA_TE
- ASC_STA_TF
- ASC_STA_THE
- ASC_STA_TNE
- ASC_STA_TOI
- ASC_STA_TX_EMPTY
- ASC_STA_TX_FULL
- ASC_STOP_ACK_RISC_STOP
- ASC_STOP_CLEAN_UP_BUSY_Q
- ASC_STOP_CLEAN_UP_DISC_Q
- ASC_STOP_HOST_REQ_RISC_HALT
- ASC_STOP_REQ_RISC_STOP
- ASC_SYN_MAX_OFFSET
- ASC_SYN_OFFSET_ONE_DISABLE_LIST
- ASC_TAG_CODE_MASK
- ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX
- ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST
- ASC_TAG_FLAG_DISABLE_DISCONNECT
- ASC_TAG_FLAG_EXTRA_BYTES
- ASC_TENTHS
- ASC_TIDLUN_TO_IX
- ASC_TID_TO_TARGET_ID
- ASC_TID_TO_TIX
- ASC_TIMEOUT
- ASC_TIMEOUT_MSK
- ASC_TIX_TO_LUN
- ASC_TIX_TO_TARGET_ID
- ASC_TIX_TO_TID
- ASC_TRUE
- ASC_TXBUF
- ASC_TXBUF_MSK
- ASC_TXRESET
- ASC_TX_BUF_OFF
- ASC_VERSION
- ASC_VOLUME
- ASC_WARN_AUTO_CONFIG
- ASC_WARN_BUSRESET_ERROR
- ASC_WARN_CFG_MSW_RECOVER
- ASC_WARN_CMD_QNG_CONFLICT
- ASC_WARN_EEPROM_CHKSUM
- ASC_WARN_EEPROM_RECOVER
- ASC_WARN_EEPROM_TERMINATION
- ASC_WARN_ERROR
- ASC_WARN_IO_PORT_ROTATE
- ASC_WARN_IRQ_MODIFIED
- ASC_WARN_NO_ERROR
- ASC_WRITE_ERR
- ASC_WRITE_PROTECT
- ASD
- ASDM_SRC_SEL_CTL_MASK
- ASDM_SRC_SEL_CTL_MASK_SFT
- ASDM_SRC_SEL_CTL_SFT
- ASD_BUSADDR_HI
- ASD_BUSADDR_LO
- ASD_COMINIT_TIMEOUT
- ASD_CRC_DIS
- ASD_DDBSITE_READ
- ASD_DDBSITE_WRITE
- ASD_DDB_SIZE
- ASD_DEF_DL_TOGGLE
- ASD_DEV_PRESENT_TIMEOUT
- ASD_DL_SIZE
- ASD_DL_SIZE_BITS
- ASD_DMA_MODE_DOWNLOAD
- ASD_DPRINTK
- ASD_DRIVER_DESCRIPTION
- ASD_DRIVER_NAME
- ASD_DRIVER_VERSION
- ASD_EDBS_PER_SCB
- ASD_EDB_SIZE
- ASD_FLASH_SIZE
- ASD_MAX_DDBS
- ASD_MAX_PHYS
- ASD_NOTIFY_DOWN_COUNT
- ASD_NOTIFY_ENABLE_SPINUP
- ASD_NOTIFY_TIMEOUT
- ASD_ONE_MILLISEC_TIMEOUT
- ASD_PCBA_SN_SIZE
- ASD_RCV_FIS_TIMEOUT
- ASD_READ_OCM
- ASD_READ_REG
- ASD_READ_SW
- ASD_SATA_INTERLOCK_TIMEOUT
- ASD_SATA_SPINUP_HOLD
- ASD_SCBSITE_READ
- ASD_SCBSITE_WRITE
- ASD_SCB_SIZE
- ASD_SG_EL_DS_HM
- ASD_SG_EL_DS_MASK
- ASD_SG_EL_DS_OCM
- ASD_SG_EL_LIST_EOL
- ASD_SG_EL_LIST_EOS
- ASD_SG_EL_LIST_MASK
- ASD_SMP_RCV_TIMEOUT
- ASD_SRST_ASSERT_TIMEOUT
- ASD_STP_SHUTDOWN_TIMEOUT
- ASD_TEN_MILLISEC_TIMEOUT
- ASD_WRITE_OCM
- ASD_WRITE_REG
- ASD_WRITE_SW
- ASEBRKAK_MARK
- ASEL
- ASEM_PCI_OCR
- ASEM_RAW_CAN_DEVICE_ID
- ASEM_RAW_CAN_RST_MASK_CAN1
- ASEM_RAW_CAN_RST_MASK_CAN2
- ASEM_RAW_CAN_RST_REGISTER
- ASEM_RAW_CAN_SUB_DEVICE_ID
- ASEM_RAW_CAN_SUB_DEVICE_ID_BIS
- ASEM_RAW_CAN_SUB_VENDOR_ID
- ASEM_RAW_CAN_VENDOR_ID
- ASENCODE_BECOMING_READY
- ASENCODE_DIAGNOSTIC_FAILURE
- ASENCODE_END_OF_DATA
- ASENCODE_INIT_CMD_REQUIRED
- ASENCODE_INQUIRY_DATA_CHANGED
- ASENCODE_INTERNAL_TARGET_FAILURE
- ASENCODE_INVALID_CDB_FIELD
- ASENCODE_INVALID_COMMAND
- ASENCODE_INVALID_MESSAGE_ERROR
- ASENCODE_INVALID_PARAM_FIELD
- ASENCODE_LBA_OUT_OF_RANGE
- ASENCODE_LUN_FAILED_SELF_CONFIG
- ASENCODE_LUN_NOT_SELF_CONFIGURED_YET
- ASENCODE_LUN_NOT_SUPPORTED
- ASENCODE_NO_SENSE
- ASENCODE_OVERLAPPED_COMMAND
- ASENCODE_PARAM_LIST_LENGTH_ERROR
- ASENCODE_PARAM_NOT_SUPPORTED
- ASENCODE_PARAM_VALUE_INVALID
- ASENCODE_RESET_OCCURRED
- ASENCODE_SAVING_PARAMS_NOT_SUPPORTED
- ASER_FADDR_A1_MASK
- ASER_FADDR_A1_SHIFT
- ASER_FADDR_A2_MASK
- ASER_FADDR_A2_SHIFT
- ASER_FADDR_EN1
- ASER_FADDR_EN2
- ASER_MASTER_ME
- ASE_MAX_PIN
- ASF
- ASF_CSR_ERR
- ASF_DAP_ERR
- ASF_INIT_DONE
- ASF_INIT_DONE_ALIAS
- ASF_INIT_PRESENT
- ASF_INTEGRITY_ERR
- ASF_INT_FATAL_SELECT
- ASF_INT_MASK
- ASF_INT_RAW_STATUS
- ASF_INT_STATUS
- ASF_INT_TEST
- ASF_PROTOCOL_ERR
- ASF_PROTO_FAULT_M
- ASF_PROTO_FAULT_MASK
- ASF_PROTO_FAULT_MSTDDR_FAIL
- ASF_PROTO_FAULT_MSTSDR_RD_ABORT
- ASF_PROTO_FAULT_S
- ASF_PROTO_FAULT_SLVDDR_FAIL
- ASF_PROTO_FAULT_SLVSDR_RD_ABORT
- ASF_PROTO_FAULT_STATUS
- ASF_SRAM_CORR_ERR
- ASF_SRAM_CORR_FAULT_ADDR
- ASF_SRAM_CORR_FAULT_INSTANCE
- ASF_SRAM_CORR_FAULT_STATUS
- ASF_SRAM_FAULT_CORR_STATS
- ASF_SRAM_FAULT_STATS
- ASF_SRAM_FAULT_UNCORR_STATS
- ASF_SRAM_UNCORR_ERR
- ASF_SRAM_UNCORR_FAULT_STATUS
- ASF_STAT
- ASF_TRANS_TIMEOUT_ERR
- ASF_TRANS_TOUT_CTRL
- ASF_TRANS_TOUT_EN
- ASF_TRANS_TOUT_FAULT_APB
- ASF_TRANS_TOUT_FAULT_FSCL_HIGH
- ASF_TRANS_TOUT_FAULT_MASK
- ASF_TRANS_TOUT_FAULT_SCL_HIGH
- ASF_TRANS_TOUT_FAULT_SCL_LOW
- ASF_TRANS_TOUT_FAULT_STATUS
- ASF_TRANS_TOUT_VAL
- ASHARED
- ASHARED_MASK
- ASHARED_SHIFT
- ASHMEM_FULL_NAME_LEN
- ASHMEM_GET_NAME
- ASHMEM_GET_PIN_STATUS
- ASHMEM_GET_PROT_MASK
- ASHMEM_GET_SIZE
- ASHMEM_IS_PINNED
- ASHMEM_IS_UNPINNED
- ASHMEM_NAME_DEF
- ASHMEM_NAME_LEN
- ASHMEM_NAME_PREFIX
- ASHMEM_NAME_PREFIX_LEN
- ASHMEM_NOT_PURGED
- ASHMEM_PIN
- ASHMEM_PURGE_ALL_CACHES
- ASHMEM_SET_NAME
- ASHMEM_SET_PROT_MASK
- ASHMEM_SET_SIZE
- ASHMEM_UNPIN
- ASHMEM_WAS_PURGED
- ASI
- ASIC
- ASIC3_BANK_TO_BASE
- ASIC3_CLOCK_BASE
- ASIC3_CLOCK_CDEX
- ASIC3_CLOCK_EX0
- ASIC3_CLOCK_EX1
- ASIC3_CLOCK_LED0
- ASIC3_CLOCK_LED1
- ASIC3_CLOCK_LED2
- ASIC3_CLOCK_OWM
- ASIC3_CLOCK_PWM0
- ASIC3_CLOCK_PWM1
- ASIC3_CLOCK_SD_BUS
- ASIC3_CLOCK_SD_HOST
- ASIC3_CLOCK_SEL
- ASIC3_CLOCK_SMBUS
- ASIC3_CLOCK_SPI
- ASIC3_CONFIG_GPIO
- ASIC3_CONFIG_GPIO_ALT
- ASIC3_CONFIG_GPIO_DEFAULT
- ASIC3_CONFIG_GPIO_DEFAULT_OUT
- ASIC3_CONFIG_GPIO_DIR
- ASIC3_CONFIG_GPIO_INIT
- ASIC3_CONFIG_GPIO_PIN
- ASIC3_DEFAULT_ADDR_SHIFT
- ASIC3_EXTCF_BASE
- ASIC3_EXTCF_CF0_BUF_EN
- ASIC3_EXTCF_CF0_PWAIT_EN
- ASIC3_EXTCF_CF0_SLEEP_MODE
- ASIC3_EXTCF_CF1_BUF_EN
- ASIC3_EXTCF_CF1_PWAIT_EN
- ASIC3_EXTCF_CF1_SLEEP_MODE
- ASIC3_EXTCF_CF_SLEEP
- ASIC3_EXTCF_OWM_EN
- ASIC3_EXTCF_OWM_RESET
- ASIC3_EXTCF_OWM_SMB
- ASIC3_EXTCF_RESET
- ASIC3_EXTCF_SD_MEM_ENABLE
- ASIC3_EXTCF_SELECT
- ASIC3_EXTCF_SMOD0
- ASIC3_EXTCF_SMOD1
- ASIC3_EXTCF_SMOD2
- ASIC3_GPIO
- ASIC3_GPIOA11_PWM0
- ASIC3_GPIOA12_PWM1
- ASIC3_GPIOA15_CONTROL_CX
- ASIC3_GPIOC0_LED0
- ASIC3_GPIOC10_nPWE
- ASIC3_GPIOC11_PSKTSEL
- ASIC3_GPIOC12_nPREG
- ASIC3_GPIOC13_nPWAIT
- ASIC3_GPIOC14_nPIOIS16
- ASIC3_GPIOC15_nPIOR
- ASIC3_GPIOC1_LED1
- ASIC3_GPIOC2_LED2
- ASIC3_GPIOC3_SPI_RXD
- ASIC3_GPIOC4_CF_nCD
- ASIC3_GPIOC4_SPI_TXD
- ASIC3_GPIOC5_SPI_CLK
- ASIC3_GPIOC5_nCIOW
- ASIC3_GPIOC6_nCIOR
- ASIC3_GPIOC7_nPCE_1
- ASIC3_GPIOC8_nPCE_2
- ASIC3_GPIOC9_nPOE
- ASIC3_GPIOD11_nCIOIS16
- ASIC3_GPIOD12_nCWAIT
- ASIC3_GPIOD15_nPIOW
- ASIC3_GPIOD4_CF_nCD
- ASIC3_GPIOS_PER_BANK
- ASIC3_GPIO_ALT_FUNCTION
- ASIC3_GPIO_A_BASE
- ASIC3_GPIO_BANK_A
- ASIC3_GPIO_BANK_B
- ASIC3_GPIO_BANK_C
- ASIC3_GPIO_BANK_D
- ASIC3_GPIO_BASE_INCR
- ASIC3_GPIO_BAT_FAULT_OUT
- ASIC3_GPIO_B_BASE
- ASIC3_GPIO_C_BASE
- ASIC3_GPIO_DIRECTION
- ASIC3_GPIO_D_BASE
- ASIC3_GPIO_EDGE_TRIGGER
- ASIC3_GPIO_INT_STATUS
- ASIC3_GPIO_LEVEL_TRIGGER
- ASIC3_GPIO_MASK
- ASIC3_GPIO_OFFSET
- ASIC3_GPIO_OUT
- ASIC3_GPIO_SLEEP_CONF
- ASIC3_GPIO_SLEEP_MASK
- ASIC3_GPIO_SLEEP_OUT
- ASIC3_GPIO_STATUS
- ASIC3_GPIO_TO_BANK
- ASIC3_GPIO_TO_BASE
- ASIC3_GPIO_TO_BIT
- ASIC3_GPIO_TO_MASK
- ASIC3_GPIO_TRIGGER_TYPE
- ASIC3_GPIO_bit
- ASIC3_INTMASK_GINTEL
- ASIC3_INTMASK_GINTMASK
- ASIC3_INTMASK_MASK0
- ASIC3_INTMASK_MASK1
- ASIC3_INTMASK_MASK2
- ASIC3_INTMASK_MASK3
- ASIC3_INTMASK_MASK4
- ASIC3_INTMASK_MASK5
- ASIC3_INTR_BASE
- ASIC3_INTR_CPS
- ASIC3_INTR_CPS_SET
- ASIC3_INTR_INT_CPS
- ASIC3_INTR_INT_MASK
- ASIC3_INTR_INT_TBS
- ASIC3_INTR_LED0
- ASIC3_INTR_LED1
- ASIC3_INTR_LED2
- ASIC3_INTR_OWM
- ASIC3_INTR_PERIPHERAL_A
- ASIC3_INTR_PERIPHERAL_B
- ASIC3_INTR_PERIPHERAL_C
- ASIC3_INTR_PERIPHERAL_D
- ASIC3_INTR_P_INT_STAT
- ASIC3_INTR_SMBUS
- ASIC3_INTR_SPI
- ASIC3_IRQ_LED0
- ASIC3_IRQ_LED1
- ASIC3_IRQ_LED2
- ASIC3_IRQ_OWM
- ASIC3_IRQ_SMBUS
- ASIC3_IRQ_SPI
- ASIC3_LED_0_Base
- ASIC3_LED_1_Base
- ASIC3_LED_2_Base
- ASIC3_LED_AutoStopCount
- ASIC3_LED_DutyTime
- ASIC3_LED_PeriodTime
- ASIC3_LED_TimeBase
- ASIC3_MAP_SIZE_16BIT
- ASIC3_MAP_SIZE_32BIT
- ASIC3_NR_IRQS
- ASIC3_NUM_GPIOS
- ASIC3_NUM_GPIO_BANKS
- ASIC3_NUM_LEDS
- ASIC3_OFFSET
- ASIC3_OWM_BASE
- ASIC3_PHYS
- ASIC3_PWM_0_Base
- ASIC3_PWM_1_Base
- ASIC3_PWM_DutyTime
- ASIC3_PWM_PeriodTime
- ASIC3_PWM_TimeBase
- ASIC3_SDHWCTRL_BASE
- ASIC3_SDHWCTRL_CLKSEL
- ASIC3_SDHWCTRL_LEVCD
- ASIC3_SDHWCTRL_LEVWP
- ASIC3_SDHWCTRL_PCLR
- ASIC3_SDHWCTRL_SDCONF
- ASIC3_SDHWCTRL_SDLED
- ASIC3_SDHWCTRL_SDPWR
- ASIC3_SDHWCTRL_SUSPEND
- ASIC3_SDIO_CTRL_BASE
- ASIC3_SD_CONFIG_BASE
- ASIC3_SD_CONFIG_SIZE
- ASIC3_SD_CTRL_BASE
- ASIC3_SD_PHYS
- ASIC3_SPI_Base
- ASIC3_SPI_Control
- ASIC3_SPI_Int
- ASIC3_SPI_RxData
- ASIC3_SPI_Status
- ASIC3_SPI_TxData
- ASIC3_TO_GPIO
- ASICCtrl
- ASICCtrl_HiWord_bit
- ASICCtrl_HiWord_bits
- ASICCtrl_LoWord_bits
- ASICID_IS_TONGA_P
- ASICREV_IS_DALI
- ASICREV_IS_GREENLAND_M
- ASICREV_IS_GREENLAND_P
- ASICREV_IS_NAVI10_P
- ASICREV_IS_NAVI12_P
- ASICREV_IS_NAVI14_M
- ASICREV_IS_PICASSO
- ASICREV_IS_RAVEN
- ASICREV_IS_RAVEN2
- ASICREV_IS_RENOIR
- ASICREV_IS_RV1_F0
- ASICREV_IS_VEGA12_P
- ASICREV_IS_VEGA20_P
- ASIC_ALREADY_LOADED
- ASIC_BUS_TYPE_AGP
- ASIC_BUS_TYPE_PCI
- ASIC_BUS_TYPE_PCIE
- ASIC_CCLOCK_PS
- ASIC_CFG_DRV_STR
- ASIC_CFG_MUTEX
- ASIC_CFG_SBUS_EXECUTE
- ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK
- ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK
- ASIC_CFG_SBUS_REQUEST
- ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT
- ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT
- ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT
- ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT
- ASIC_CFG_SCRATCH
- ASIC_CFG_SCRATCH_1
- ASIC_CFG_SCRATCH_2
- ASIC_CFG_SCRATCH_3
- ASIC_CFG_THERM_POLL_EN
- ASIC_EEP_ADDR_CMD
- ASIC_EEP_ADDR_CMD_EP_ADDR_MASK
- ASIC_EEP_CTL_STAT
- ASIC_EEP_CTL_STAT_EP_RESET_SMASK
- ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT
- ASIC_EEP_CTL_STAT_RESETCSR
- ASIC_EEP_DATA
- ASIC_ENCODER_INFO
- ASIC_EXTERNAL_SS_ON_DP_CLOCK
- ASIC_EXT_DIG2_ENCODER_ID
- ASIC_EXT_DIG_ENCODER_ID
- ASIC_EXT_TV_ENCODER_ID
- ASIC_GOYA
- ASIC_GPIO_CLEAR
- ASIC_GPIO_FORCE
- ASIC_GPIO_IN
- ASIC_GPIO_INVERT
- ASIC_GPIO_MASK
- ASIC_GPIO_OE
- ASIC_GPIO_OUT
- ASIC_HI_WORD
- ASIC_ID_GET
- ASIC_INIT_CLOCK_PARAMETERS
- ASIC_INIT_PARAMETERS
- ASIC_INIT_PARAMETERS_V1_2
- ASIC_INIT_PS_ALLOCATION
- ASIC_INIT_PS_ALLOCATION_V1_2
- ASIC_INTERNAL_ENGINE_SS
- ASIC_INTERNAL_GPUPLL_SS
- ASIC_INTERNAL_MEMORY_SS
- ASIC_INTERNAL_SS_ON_DCPLL
- ASIC_INTERNAL_SS_ON_DP
- ASIC_INTERNAL_SS_ON_HDMI
- ASIC_INTERNAL_SS_ON_LVDS
- ASIC_INTERNAL_SS_ON_TMDS
- ASIC_INTERNAL_UVD_SS
- ASIC_INTERNAL_VCE_SS
- ASIC_INT_DAC1_ENCODER_ID
- ASIC_INT_DAC2_ENCODER_ID
- ASIC_INT_DIG1_ENCODER_ID
- ASIC_INT_DIG2_ENCODER_ID
- ASIC_INT_DIG3_ENCODER_ID
- ASIC_INT_DIG4_ENCODER_ID
- ASIC_INT_DIG5_ENCODER_ID
- ASIC_INT_DIG6_ENCODER_ID
- ASIC_INT_DIG7_ENCODER_ID
- ASIC_INT_DVO_ENCODER_ID
- ASIC_INT_TV_ENCODER_ID
- ASIC_INVALID
- ASIC_IS_AVIVO
- ASIC_IS_DCE2
- ASIC_IS_DCE3
- ASIC_IS_DCE32
- ASIC_IS_DCE4
- ASIC_IS_DCE41
- ASIC_IS_DCE5
- ASIC_IS_DCE6
- ASIC_IS_DCE61
- ASIC_IS_DCE64
- ASIC_IS_DCE8
- ASIC_IS_DCE81
- ASIC_IS_DCE82
- ASIC_IS_DCE83
- ASIC_IS_LOMBOK
- ASIC_IS_NODCE
- ASIC_IS_R300
- ASIC_IS_RN50
- ASIC_IS_RV100
- ASIC_IS_X2
- ASIC_LANCE
- ASIC_MAX_TEMP
- ASIC_MAX_TEMP_MASK
- ASIC_MAX_TEMP_SHIFT
- ASIC_MVDDC_Info
- ASIC_MVDDQ_Info
- ASIC_NOT_LOADED
- ASIC_NUM_SCRATCH
- ASIC_PCIE_SD_HOST_CMD
- ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT
- ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK
- ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT
- ASIC_PCIE_SD_HOST_CMD_TIMER_MASK
- ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT
- ASIC_PCIE_SD_HOST_STATUS
- ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK
- ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT
- ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK
- ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT
- ASIC_PCIE_SD_INTRPT_DATA_CODE
- ASIC_PCIE_SD_INTRPT_ENABLE
- ASIC_PCIE_SD_INTRPT_LIST
- ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT
- ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT
- ASIC_PCIE_SD_INTRPT_STATUS
- ASIC_PIPE_DISABLE
- ASIC_PIPE_ENABLE
- ASIC_PIPE_INIT
- ASIC_QSFP1_CLEAR
- ASIC_QSFP1_FORCE
- ASIC_QSFP1_IN
- ASIC_QSFP1_INVERT
- ASIC_QSFP1_MASK
- ASIC_QSFP1_OE
- ASIC_QSFP1_OUT
- ASIC_QSFP1_STATUS
- ASIC_QSFP2_CLEAR
- ASIC_QSFP2_FORCE
- ASIC_QSFP2_IN
- ASIC_QSFP2_INVERT
- ASIC_QSFP2_MASK
- ASIC_QSFP2_OE
- ASIC_QSFP2_OUT
- ASIC_QSFP2_STATUS
- ASIC_REG_CPU_CA53_CFG_MASKS_H_
- ASIC_REG_CPU_CA53_CFG_REGS_H_
- ASIC_REG_CPU_IF_REGS_H_
- ASIC_REG_CPU_PLL_REGS_H_
- ASIC_REG_DMA_CH_0_MASKS_H_
- ASIC_REG_DMA_CH_0_REGS_H_
- ASIC_REG_DMA_CH_1_REGS_H_
- ASIC_REG_DMA_CH_2_REGS_H_
- ASIC_REG_DMA_CH_3_REGS_H_
- ASIC_REG_DMA_CH_4_REGS_H_
- ASIC_REG_DMA_MACRO_MASKS_H_
- ASIC_REG_DMA_MACRO_REGS_H_
- ASIC_REG_DMA_NRTR_MASKS_H_
- ASIC_REG_DMA_NRTR_REGS_H_
- ASIC_REG_DMA_QM_0_MASKS_H_
- ASIC_REG_DMA_QM_0_REGS_H_
- ASIC_REG_DMA_QM_1_REGS_H_
- ASIC_REG_DMA_QM_2_REGS_H_
- ASIC_REG_DMA_QM_3_REGS_H_
- ASIC_REG_DMA_QM_4_REGS_H_
- ASIC_REG_GOYA_MASKS_H_
- ASIC_REG_GOYA_REGS_H_
- ASIC_REG_IC_PLL_REGS_H_
- ASIC_REG_MC_PLL_REGS_H_
- ASIC_REG_MME1_RTR_MASKS_H_
- ASIC_REG_MME1_RTR_REGS_H_
- ASIC_REG_MME2_RTR_REGS_H_
- ASIC_REG_MME3_RTR_REGS_H_
- ASIC_REG_MME4_RTR_REGS_H_
- ASIC_REG_MME5_RTR_REGS_H_
- ASIC_REG_MME6_RTR_REGS_H_
- ASIC_REG_MME_CMDQ_MASKS_H_
- ASIC_REG_MME_CMDQ_REGS_H_
- ASIC_REG_MME_MASKS_H_
- ASIC_REG_MME_QM_MASKS_H_
- ASIC_REG_MME_QM_REGS_H_
- ASIC_REG_MME_REGS_H_
- ASIC_REG_MMU_MASKS_H_
- ASIC_REG_MMU_REGS_H_
- ASIC_REG_PCIE_AUX_REGS_H_
- ASIC_REG_PCIE_WRAP_REGS_H_
- ASIC_REG_PCI_NRTR_MASKS_H_
- ASIC_REG_PCI_NRTR_REGS_H_
- ASIC_REG_PSOC_EMMC_PLL_REGS_H_
- ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
- ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_
- ASIC_REG_PSOC_MME_PLL_REGS_H_
- ASIC_REG_PSOC_PCI_PLL_REGS_H_
- ASIC_REG_PSOC_SPI_REGS_H_
- ASIC_REG_SRAM_Y0_X0_RTR_REGS_H_
- ASIC_REG_SRAM_Y0_X1_RTR_REGS_H_
- ASIC_REG_SRAM_Y0_X2_RTR_REGS_H_
- ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_
- ASIC_REG_SRAM_Y0_X4_RTR_REGS_H_
- ASIC_REG_STLB_MASKS_H_
- ASIC_REG_STLB_REGS_H_
- ASIC_REG_TPC0_CFG_MASKS_H_
- ASIC_REG_TPC0_CFG_REGS_H_
- ASIC_REG_TPC0_CMDQ_MASKS_H_
- ASIC_REG_TPC0_CMDQ_REGS_H_
- ASIC_REG_TPC0_EML_CFG_MASKS_H_
- ASIC_REG_TPC0_EML_CFG_REGS_H_
- ASIC_REG_TPC0_NRTR_MASKS_H_
- ASIC_REG_TPC0_NRTR_REGS_H_
- ASIC_REG_TPC0_QM_MASKS_H_
- ASIC_REG_TPC0_QM_REGS_H_
- ASIC_REG_TPC1_CFG_REGS_H_
- ASIC_REG_TPC1_CMDQ_REGS_H_
- ASIC_REG_TPC1_QM_REGS_H_
- ASIC_REG_TPC1_RTR_REGS_H_
- ASIC_REG_TPC2_CFG_REGS_H_
- ASIC_REG_TPC2_CMDQ_REGS_H_
- ASIC_REG_TPC2_QM_REGS_H_
- ASIC_REG_TPC2_RTR_REGS_H_
- ASIC_REG_TPC3_CFG_REGS_H_
- ASIC_REG_TPC3_CMDQ_REGS_H_
- ASIC_REG_TPC3_QM_REGS_H_
- ASIC_REG_TPC3_RTR_REGS_H_
- ASIC_REG_TPC4_CFG_REGS_H_
- ASIC_REG_TPC4_CMDQ_REGS_H_
- ASIC_REG_TPC4_QM_REGS_H_
- ASIC_REG_TPC4_RTR_REGS_H_
- ASIC_REG_TPC5_CFG_REGS_H_
- ASIC_REG_TPC5_CMDQ_REGS_H_
- ASIC_REG_TPC5_QM_REGS_H_
- ASIC_REG_TPC5_RTR_REGS_H_
- ASIC_REG_TPC6_CFG_REGS_H_
- ASIC_REG_TPC6_CMDQ_REGS_H_
- ASIC_REG_TPC6_QM_REGS_H_
- ASIC_REG_TPC6_RTR_REGS_H_
- ASIC_REG_TPC7_CFG_REGS_H_
- ASIC_REG_TPC7_CMDQ_REGS_H_
- ASIC_REG_TPC7_NRTR_REGS_H_
- ASIC_REG_TPC7_QM_REGS_H_
- ASIC_REG_TPC_PLL_REGS_H_
- ASIC_REV_5700
- ASIC_REV_5701
- ASIC_REV_5703
- ASIC_REV_5704
- ASIC_REV_5705
- ASIC_REV_5714
- ASIC_REV_5717
- ASIC_REV_5719
- ASIC_REV_5720
- ASIC_REV_5750
- ASIC_REV_5752
- ASIC_REV_5755
- ASIC_REV_5761
- ASIC_REV_5762
- ASIC_REV_57765
- ASIC_REV_57766
- ASIC_REV_57780
- ASIC_REV_5780
- ASIC_REV_5784
- ASIC_REV_5785
- ASIC_REV_5787
- ASIC_REV_5906
- ASIC_REV_IS_BHAVANI
- ASIC_REV_IS_BONAIRE_M
- ASIC_REV_IS_FIJI_P
- ASIC_REV_IS_GODAVARI
- ASIC_REV_IS_HAWAII_P
- ASIC_REV_IS_KALINDI
- ASIC_REV_IS_POLARIS10_P
- ASIC_REV_IS_POLARIS11_M
- ASIC_REV_IS_POLARIS12_V
- ASIC_REV_IS_STONEY
- ASIC_REV_IS_TONGA_P
- ASIC_REV_IS_VEGAM
- ASIC_REV_USE_PROD_ID_REG
- ASIC_STS_SBUS_COUNTERS
- ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_MASK
- ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_SHIFT
- ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_MASK
- ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_SHIFT
- ASIC_STS_SBUS_RESULT
- ASIC_STS_SBUS_RESULT_DATA_OUT_MASK
- ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT
- ASIC_STS_SBUS_RESULT_DONE_SMASK
- ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK
- ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK
- ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT
- ASIC_STS_THERM
- ASIC_STS_THERM_CRIT_TEMP_MASK
- ASIC_STS_THERM_CRIT_TEMP_SHIFT
- ASIC_STS_THERM_CURR_TEMP_MASK
- ASIC_STS_THERM_CURR_TEMP_SHIFT
- ASIC_STS_THERM_HI_TEMP_MASK
- ASIC_STS_THERM_HI_TEMP_SHIFT
- ASIC_STS_THERM_LOW_SHIFT
- ASIC_STS_THERM_LO_TEMP_MASK
- ASIC_STS_THERM_LO_TEMP_SHIFT
- ASIC_StaticPwrMgtStatusChange
- ASIC_T
- ASIC_TRANSMITTER_INFO
- ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE
- ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E
- ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F
- ASIC_TRANSMITTER_INFO_V2
- ASIC_T_MASK
- ASIC_T_SHIFT
- ASIC_VDDCI_Info
- ASIC_VER_GET
- ASID
- ASID_BITS
- ASID_FIRST_VERSION
- ASID_INC
- ASID_INSERT
- ASID_MASK
- ASID_USER_FIRST
- ASIEN
- ASIERR
- ASIERRADDR
- ASIERRDATAR
- ASIERRSTATR
- ASIE_show
- ASIE_store
- ASIFMTERR
- ASISEECHKERR
- ASISTAT0R
- ASISTAT1R
- ASIU_DIV_VAL
- ASIU_GATE_VAL
- ASIV_LENGTH
- ASIV_LENGTH_ATS
- ASIX111_DESC
- ASIX112_DESC
- ASIX_VENDOR_ID
- ASIZE
- ASIZE_16BIT
- ASIZE_MAX
- ASI_AFAR
- ASI_AFSR
- ASI_AIUP
- ASI_AIUPL
- ASI_AIUS
- ASI_AIUSL
- ASI_BLK_AIUP
- ASI_BLK_AIUPL
- ASI_BLK_AIUP_4V
- ASI_BLK_AIUP_L_4V
- ASI_BLK_AIUS
- ASI_BLK_AIUSL
- ASI_BLK_AIUS_4V
- ASI_BLK_AIUS_L_4V
- ASI_BLK_COMMIT_P
- ASI_BLK_COMMIT_S
- ASI_BLK_INIT_QUAD_LDD_AIUS
- ASI_BLK_INIT_QUAD_LDD_P
- ASI_BLK_INIT_QUAD_LDD_S
- ASI_BLK_P
- ASI_BLK_PL
- ASI_BLK_S
- ASI_BLK_SL
- ASI_BRPRED_ARRAY
- ASI_CESR_ID
- ASI_CMT_ERROR_STEERING
- ASI_CONTROL
- ASI_CORE_AVAILABLE
- ASI_CORE_ENABLE
- ASI_CORE_ENABLE_STAT
- ASI_CORE_ID
- ASI_CORE_RUNNING_RW
- ASI_CORE_RUNNING_STAT
- ASI_CORE_RUNNING_W1C
- ASI_CORE_RUNNING_W1S
- ASI_DCACHE_DATA
- ASI_DCACHE_INVALIDATE
- ASI_DCACHE_SNOOP_TAG
- ASI_DCACHE_TAG
- ASI_DCACHE_UTAG
- ASI_DCU_CONTROL_REG
- ASI_DMMU
- ASI_DMMU_DEMAP
- ASI_DMMU_TSB_64KB_PTR
- ASI_DMMU_TSB_8KB_PTR
- ASI_DMMU_TSB_DIRECT_PTR
- ASI_DTLB_DATA_ACCESS
- ASI_DTLB_DATA_IN
- ASI_DTLB_TAG_READ
- ASI_EC_CTRL
- ASI_EC_DATA
- ASI_EC_R
- ASI_EC_TAG_DATA
- ASI_EC_W
- ASI_ESTATE_ERROR_EN
- ASI_FL16_P
- ASI_FL16_PL
- ASI_FL16_S
- ASI_FL16_SL
- ASI_FL8_P
- ASI_FL8_PL
- ASI_FL8_S
- ASI_FL8_SL
- ASI_FLUSHCTX
- ASI_FLUSHPG
- ASI_FLUSHSEG
- ASI_HWFLUSHCONTEXT
- ASI_HWFLUSHPAGE
- ASI_HWFLUSHSEG
- ASI_IC_INSTR
- ASI_IC_NEXT_FIELD
- ASI_IC_PRE_DECODE
- ASI_IC_STAG
- ASI_IC_TAG
- ASI_IIU_INST_TRAP
- ASI_IMMU
- ASI_IMMU_DEMAP
- ASI_IMMU_TSB_64KB_PTR
- ASI_IMMU_TSB_8KB_PTR
- ASI_INTR_DATAN_R
- ASI_INTR_DATAN_W
- ASI_INTR_DISPATCH_STAT
- ASI_INTR_DISPATCH_W
- ASI_INTR_ID
- ASI_INTR_R
- ASI_INTR_RECEIVE
- ASI_INTR_W
- ASI_ITLB_DATA_ACCESS
- ASI_ITLB_DATA_IN
- ASI_ITLB_TAG_READ
- ASI_JBUS_CONFIG
- ASI_KERNELDATA
- ASI_KERNELTXT
- ASI_LEON3_SYSCTRL
- ASI_LEON3_SYSCTRL_CFG_SNOOPING
- ASI_LEON3_SYSCTRL_CFG_SSIZE
- ASI_LEON3_SYSCTRL_DCFG
- ASI_LEON3_SYSCTRL_ICFG
- ASI_LEON_BYPASS
- ASI_LEON_CACHEREGS
- ASI_LEON_DCACHE_MISS
- ASI_LEON_DFLUSH
- ASI_LEON_FLUSH_PAGE
- ASI_LEON_IFLUSH
- ASI_LEON_MMUFLUSH
- ASI_LEON_MMUREGS
- ASI_LEON_NOCACHE
- ASI_LSU_CONTROL
- ASI_MCD_PRIMARY
- ASI_MCD_PRIV_PRIMARY
- ASI_MCD_REAL
- ASI_MCD_ST_BLKINIT_PRIMARY
- ASI_MCU_CTRL_REG
- ASI_MMU
- ASI_M_ACTION
- ASI_M_BCOPY
- ASI_M_BFILL
- ASI_M_BYPASS
- ASI_M_CTL
- ASI_M_DATAC_DATA
- ASI_M_DATAC_TAG
- ASI_M_DCDR
- ASI_M_DC_FLCLEAR
- ASI_M_DIAGS
- ASI_M_FBMEM
- ASI_M_FLUSH_CTX
- ASI_M_FLUSH_IWHOLE
- ASI_M_FLUSH_PAGE
- ASI_M_FLUSH_PROBE
- ASI_M_FLUSH_REGION
- ASI_M_FLUSH_SEG
- ASI_M_FLUSH_USER
- ASI_M_IC_FLCLEAR
- ASI_M_IFLUSH_CTX
- ASI_M_IFLUSH_PAGE
- ASI_M_IFLUSH_REGION
- ASI_M_IFLUSH_SEG
- ASI_M_IFLUSH_USER
- ASI_M_IODIAG
- ASI_M_KERNELDATA
- ASI_M_KERNELTXT
- ASI_M_MMUREGS
- ASI_M_MXCC
- ASI_M_RES00
- ASI_M_SBUS
- ASI_M_TLBDIAG
- ASI_M_TXTC_DATA
- ASI_M_TXTC_TAG
- ASI_M_UNA01
- ASI_M_USERDATA
- ASI_M_USERTXT
- ASI_M_VIKING_TMP1
- ASI_M_VMEPS
- ASI_M_VMEPT
- ASI_M_VMEUS
- ASI_M_VMEUT
- ASI_N
- ASI_NL
- ASI_NUCLEUS_QUAD_LDD
- ASI_NUCLEUS_QUAD_LDD_L
- ASI_NULL1
- ASI_NULL2
- ASI_P
- ASI_PCACHE_DATA
- ASI_PCACHE_DATA_STATUS
- ASI_PCACHE_SNOOP_TAG
- ASI_PCACHE_TAG
- ASI_PHYS_BYPASS_EC_E
- ASI_PHYS_BYPASS_EC_E_L
- ASI_PHYS_USE_EC
- ASI_PHYS_USE_EC_L
- ASI_PIC
- ASI_PL
- ASI_PNF
- ASI_PNFL
- ASI_PST16_P
- ASI_PST16_PL
- ASI_PST16_S
- ASI_PST16_SL
- ASI_PST32_P
- ASI_PST32_PL
- ASI_PST32_S
- ASI_PST32_SL
- ASI_PST8_P
- ASI_PST8_PL
- ASI_PST8_S
- ASI_PST8_SL
- ASI_PTE
- ASI_QUAD_LDD_PHYS
- ASI_QUAD_LDD_PHYS_4V
- ASI_QUAD_LDD_PHYS_L
- ASI_QUAD_LDD_PHYS_L_4V
- ASI_QUEUE
- ASI_REGMAP
- ASI_S
- ASI_SAFARI_ADDRESS
- ASI_SAFARI_CONFIG
- ASI_SCRATCHPAD
- ASI_SEGMAP
- ASI_SL
- ASI_SNF
- ASI_SNFL
- ASI_SRAM_FAST_INIT
- ASI_STBIMRU_P
- ASI_STBI_P
- ASI_ST_BLKINIT_MRU_P
- ASI_ST_BLKINIT_MRU_PL
- ASI_ST_BLKINIT_MRU_S
- ASI_ST_BLKINIT_MRU_SL
- ASI_UDBH_CONTROL_R
- ASI_UDBH_ERROR_R
- ASI_UDBL_CONTROL_R
- ASI_UDBL_ERROR_R
- ASI_UDB_CONTROL_W
- ASI_UDB_ERROR_W
- ASI_UPA_CONFIG
- ASI_USERDATA
- ASI_USERTXT
- ASI_WCACHE_DATA
- ASI_WCACHE_SNOOP_TAG
- ASI_WCACHE_TAG
- ASI_WCACHE_VALID_BITS
- ASI_XIR_STEERING
- ASK_VGA
- ASLCOMMENT_INLINE
- ASLC_ALS_ILLUM_FAILED
- ASLC_BACKLIGHT_FAILED
- ASLC_BUTTON_ARRAY
- ASLC_BUTTON_ARRAY_FAILED
- ASLC_CONVERTIBLE_FAILED
- ASLC_CONVERTIBLE_INDICATOR
- ASLC_DOCKING_FAILED
- ASLC_DOCKING_INDICATOR
- ASLC_ISCT_STATE_CHANGE
- ASLC_ISCT_STATE_FAILED
- ASLC_PFIT_FAILED
- ASLC_PWM_FREQ_FAILED
- ASLC_REQ_MSK
- ASLC_ROTATION_ANGLES_FAILED
- ASLC_SET_ALS_ILLUM
- ASLC_SET_BACKLIGHT
- ASLC_SET_PFIT
- ASLC_SET_PWM_FREQ
- ASLC_SUPPORTED_ROTATION_ANGLES
- ASLE
- ASLEEP
- ASLE_ALS_EN
- ASLE_ALS_ILLUM_FAILED
- ASLE_ARDY_NOT_READY
- ASLE_ARDY_READY
- ASLE_BACKLIGHT_FAILED
- ASLE_BCLP_MSK
- ASLE_BCLP_VALID
- ASLE_BLC_EN
- ASLE_CBLV_VALID
- ASLE_IUER_CONVERTIBLE
- ASLE_IUER_DOCKING
- ASLE_IUER_POWER_BTN
- ASLE_IUER_ROTATION_LOCK_BTN
- ASLE_IUER_VOLUME_DOWN_BTN
- ASLE_IUER_VOLUME_UP_BTN
- ASLE_IUER_WINDOWS_BTN
- ASLE_PFIT_CENTER
- ASLE_PFIT_EN
- ASLE_PFIT_FAILED
- ASLE_PFIT_STRETCH_GFX
- ASLE_PFIT_STRETCH_TEXT
- ASLE_PFIT_VALID
- ASLE_PFMB_BRIGHTNESS_MASK
- ASLE_PFMB_BRIGHTNESS_VALID
- ASLE_PFMB_EN
- ASLE_PFMB_PWM_MASK
- ASLE_PFMB_PWM_VALID
- ASLE_PWM_FREQ_FAILED
- ASLE_REQ_MSK
- ASLE_SET_ALS_ILLUM
- ASLE_SET_BACKLIGHT
- ASLE_SET_PFIT
- ASLE_SET_PWM_FREQ
- ASLE_TCHE_ALS_EN
- ASLE_TCHE_BLC_EN
- ASLE_TCHE_PFIT_EN
- ASLE_TCHE_PFMB_EN
- ASLIPCOMPEN_F
- ASLIPCOMPEN_S
- ASLIPCOMPEN_V
- ASLP
- ASLP_TOUT
- ASLS
- ASL_COMMENT_CLOSE_BRACE
- ASL_COMMENT_CLOSE_PAREN
- ASL_COMMENT_OPEN_PAREN
- ASL_COMMENT_STANDARD
- ASL_CV_CAPTURE_COMMENTS
- ASL_CV_CAPTURE_COMMENTS_ONLY
- ASL_CV_CLEAR_OP_COMMENTS
- ASL_CV_CLOSE_BRACE
- ASL_CV_CLOSE_PAREN
- ASL_CV_FILE_HAS_SWITCHED
- ASL_CV_INIT_FILETREE
- ASL_CV_LABEL_FILENODE
- ASL_CV_PRINT_ONE_COMMENT
- ASL_CV_PRINT_ONE_COMMENT_LIST
- ASL_CV_SWITCH_FILES
- ASL_CV_TRANSFER_COMMENTS
- ASL_PREPROCESSOR
- ASL_RDESC_DMA_SIZE
- ASL_RDESC_END_DEPEND_SIZE
- ASL_RDESC_END_TAG_SIZE
- ASL_RDESC_FIXED_DMA_SIZE
- ASL_RDESC_FIXED_IO_SIZE
- ASL_RDESC_IO_SIZE
- ASL_RDESC_IRQ_SIZE
- ASL_RDESC_ST_DEPEND_SIZE
- ASM9260_AUART
- ASM9260_BM_AUTOBAUD_AUTORESTART
- ASM9260_BM_AUTOBAUD_EO_INT_CLR
- ASM9260_BM_AUTOBAUD_MODE
- ASM9260_BM_AUTOBAUD_START
- ASM9260_BM_AUTOBAUD_TO_INT_CLR
- ASM9260_BM_CLEAR_BIT
- ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT
- ASM9260_BM_CTRL0_RXDMA_RUN
- ASM9260_BM_CTRL0_RXTO_ENABLE
- ASM9260_BM_CTRL0_RXTO_MASK
- ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS
- ASM9260_BM_CTRL1_TXDMA_RUN
- ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL
- ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL
- ASM9260_BM_CTRL2_DTR
- ASM9260_BM_CTRL2_LBE
- ASM9260_BM_CTRL2_PORT_ENABLE
- ASM9260_BM_CTRL2_RXIFLSEL
- ASM9260_BM_CTRL2_TXIFLSEL
- ASM9260_BM_CTRL3_9BIT
- ASM9260_BM_CTRL3_BAUD8
- ASM9260_BM_CTRL3_MASTERMODE
- ASM9260_BM_CTRL3_MSBF
- ASM9260_BM_CTRL3_OUTCLK_DIV_MASK
- ASM9260_BM_CTRL3_SYNCMODE
- ASM9260_BM_CTRL_ARM_RSE_MODE
- ASM9260_BM_CTRL_CLKGATE
- ASM9260_BM_CTRL_IRQ_ENABLE
- ASM9260_BM_CTRL_NO_NESTING
- ASM9260_BM_CTRL_SFTRST
- ASM9260_BM_DEBUG_RXCMDEND
- ASM9260_BM_DEBUG_RXDMARQ
- ASM9260_BM_DEBUG_RXDMARUN
- ASM9260_BM_DEBUG_TXCMDEND
- ASM9260_BM_DEBUG_TXDMARQ
- ASM9260_BM_DEBUG_TXDMARUN
- ASM9260_BM_ICOLL_INTERRUPTn_ENABLE
- ASM9260_BM_ICOLL_INTERRUPTn_SHIFT
- ASM9260_BM_INTR_ABEO
- ASM9260_BM_INTR_ABTO
- ASM9260_BM_INTR_BEIEN
- ASM9260_BM_INTR_BEIS
- ASM9260_BM_INTR_DCDMIEN
- ASM9260_BM_INTR_DCDMIS
- ASM9260_BM_INTR_DSRMIEN
- ASM9260_BM_INTR_DSRMIS
- ASM9260_BM_INTR_FEIEN
- ASM9260_BM_INTR_FEIS
- ASM9260_BM_INTR_OEIEN
- ASM9260_BM_INTR_OEIS
- ASM9260_BM_INTR_PEIEN
- ASM9260_BM_INTR_PEIS
- ASM9260_BM_INTR_RIMIEN
- ASM9260_BM_INTR_RIMIS
- ASM9260_BM_INTR_TFEIEN
- ASM9260_BM_INTR_TFEIS
- ASM9260_BM_INT_ENABLE
- ASM9260_BM_INT_PRIORITY_MASK
- ASM9260_BM_INT_SOFTIRQ
- ASM9260_BM_ISO7816CTRL_DS_NACK
- ASM9260_BM_ISO7816CTRL_ENABLE
- ASM9260_BM_ISO7816CTRL_HS
- ASM9260_BM_ISO7816CTRL_INACK
- ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK
- ASM9260_BM_ISO7816CTRL_NEG_DATA
- ASM9260_BM_ISO7816_NB_ERRORS_MASK
- ASM9260_BM_ISO7816_STAT_ITERATION
- ASM9260_BM_LCTRL_CHRL_5
- ASM9260_BM_LCTRL_CHRL_6
- ASM9260_BM_LCTRL_CHRL_7
- ASM9260_BM_LCTRL_CHRL_8
- ASM9260_BM_LCTRL_SPS
- ASM9260_BM_LCTRL_WLEN
- ASM9260_BM_LEVELn
- ASM9260_BM_RS485ADRMATCH_MASK
- ASM9260_BM_RS485CTRL_AADEN
- ASM9260_BM_RS485CTRL_DIR_CTRL
- ASM9260_BM_RS485CTRL_ONIV
- ASM9260_BM_RS485CTRL_PINSEL
- ASM9260_BM_RS485CTRL_RS485EN
- ASM9260_BM_RS485CTRL_RXDIS
- ASM9260_BM_RS485DLY_MASK
- ASM9260_BM_STAT_HISPEED
- ASM9260_BM_STAT_PRESENT
- ASM9260_BM_STAT_RXFULL
- ASM9260_HW_AUTOBAUD
- ASM9260_HW_CTRL0
- ASM9260_HW_CTRL1
- ASM9260_HW_CTRL2
- ASM9260_HW_CTRL3
- ASM9260_HW_DATA
- ASM9260_HW_DEBUG
- ASM9260_HW_ICOLL_CLEAR0
- ASM9260_HW_ICOLL_CLEAR1
- ASM9260_HW_ICOLL_CLEARn
- ASM9260_HW_ICOLL_CTRL
- ASM9260_HW_ICOLL_INTERRUPT0
- ASM9260_HW_ICOLL_INTERRUPTn
- ASM9260_HW_ICOLL_LEVELACK
- ASM9260_HW_ICOLL_RAW0
- ASM9260_HW_ICOLL_RAW1
- ASM9260_HW_ICOLL_STAT_OFFSET
- ASM9260_HW_ICOLL_UNDEF_VECTOR
- ASM9260_HW_ICOLL_VBASE
- ASM9260_HW_ICOLL_VECTOR
- ASM9260_HW_ILPR
- ASM9260_HW_INTR
- ASM9260_HW_ISO7816_CTRL
- ASM9260_HW_ISO7816_ERRCNT
- ASM9260_HW_ISO7816_STATUS
- ASM9260_HW_LINECTRL
- ASM9260_HW_RS485ADRMATCH
- ASM9260_HW_RS485CTRL
- ASM9260_HW_RS485DLY
- ASM9260_HW_STAT
- ASM9260_ICOLL
- ASM9260_NUM_IRQS
- ASM9260_WDT_DEFAULT_TIMEOUT
- ASMARM_AMBA_H
- ASMARM_ARCH_IRDA_H
- ASMARM_ARCH_LED_H
- ASMARM_ARCH_MMC_H
- ASMARM_ARCH_OHCI_H
- ASMARM_ARCH_UART_H
- ASMARM_DEVICE_H
- ASMARM_DMA_CONTIGUOUS_H
- ASMARM_DMA_IOMMU_H
- ASMARM_DMA_MAPPING_H
- ASMARM_MACH_FLASH_H
- ASMARM_PCI_H
- ASMARM_SPARSEMEM_H
- ASMARM_THREAD_NOTIFY_H
- ASMARM_VGA_H
- ASMFORMAT
- ASMI_TIMING_CON1
- ASMO_TIMING_CON1
- ASMTYPE_JASPER
- ASMTYPE_JUNIPER
- ASMTYPE_PEARL
- ASMTYPE_SPRUCE
- ASMTYPE_TOPAZ
- ASMTYPE_UNKNOWN
- ASMT_CONTROL_REG
- ASMT_CONTROL_WRITE_BIT
- ASMT_DATA_WRITE0_REG
- ASMT_DATA_WRITE1_REG
- ASMT_FLOWCTL_ADDR
- ASMT_FLOWCTL_DATA
- ASMT_PSEUDO_DATA
- ASMT_WRITEREG_CMD
- ASM_ARCH_BALLOON3_H
- ASM_ARCH_MAINSTONE_H
- ASM_ARCH_ZIPIT2_H
- ASM_ARC_DMA_H
- ASM_ARM_CRYPTO_SHA1_H
- ASM_ARM_DMA_DIRECT_H
- ASM_ARM_HARDWARE_AMBA_KMI_H
- ASM_ARM_HARDWARE_SERIAL_AMBA_H
- ASM_ASYNC_IO_MODE
- ASM_BL_SWITCHER_H
- ASM_BUG
- ASM_BUG_FLAGS
- ASM_CALL_CONSTRAINT
- ASM_CELL_PIC_H
- ASM_CLAC
- ASM_CLIENT_EVENT_CMD_CLOSE_DONE
- ASM_CLIENT_EVENT_CMD_EOS_DONE
- ASM_CLIENT_EVENT_CMD_FLUSH_DONE
- ASM_CLIENT_EVENT_CMD_OUT_FLUSH_DONE
- ASM_CLIENT_EVENT_CMD_PAUSE_DONE
- ASM_CLIENT_EVENT_CMD_RUN_DONE
- ASM_CLIENT_EVENT_CMD_SUSPEND_DONE
- ASM_CLIENT_EVENT_DATA_READ_DONE
- ASM_CLIENT_EVENT_DATA_WRITE_DONE
- ASM_CMDRSP_SHARED_MEM_MAP_REGIONS
- ASM_CMD_SHARED_MEM_MAP_REGIONS
- ASM_CMD_SHARED_MEM_UNMAP_REGIONS
- ASM_CONST
- ASM_CPUID_MFC0
- ASM_DATA_CMD_EOS
- ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2
- ASM_DATA_CMD_READ_V2
- ASM_DATA_CMD_WRITE_V2
- ASM_DATA_EVENT_READ_DONE_V2
- ASM_DATA_EVENT_WRITE_DONE_V2
- ASM_DEFAULT_APP_TYPE
- ASM_DI
- ASM_EDAC_H
- ASM_EISA_EEPROM_H
- ASM_EISA_H
- ASM_ELF_NOTE_BEGIN
- ASM_ELF_NOTE_END
- ASM_EMIT_BELONG
- ASM_END_POINT_DEVICE_MATRIX
- ASM_EXCEPTIONTABLE_ENTRY
- ASM_EXCEPTIONTABLE_ENTRY_EFAULT
- ASM_FTR_IF
- ASM_FTR_IFCLR
- ASM_FTR_IFSET
- ASM_GLUE_CACHE_H
- ASM_GLUE_DF_H
- ASM_GLUE_PF_H
- ASM_GLUE_PROC_H
- ASM_HEXAGON_VM_H
- ASM_IA64_CYCLONE_H
- ASM_KVM_BOOKE_HV_ASM_H
- ASM_KVM_CACHE_REGS_H
- ASM_KVM_HOST_H
- ASM_LEGACY_STREAM_SESSION
- ASM_LINE_SEP
- ASM_LIVEPATCH_H
- ASM_LOAD_FPR_SINGLE_PRECISION
- ASM_LOAD_GPR_IMMED
- ASM_LOOP
- ASM_MEDIA_FMT_MP3
- ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2
- ASM_MFF
- ASM_MMU_FTR_IF
- ASM_MMU_FTR_IFCLR
- ASM_MMU_FTR_IFSET
- ASM_MTF
- ASM_NL
- ASM_NOP1
- ASM_NOP2
- ASM_NOP3
- ASM_NOP4
- ASM_NOP5
- ASM_NOP5_ATOMIC
- ASM_NOP6
- ASM_NOP7
- ASM_NOP8
- ASM_NOP_MAX
- ASM_NO_INPUT_CLOBBER
- ASM_NULL_POPP_TOPOLOGY
- ASM_OFFSETS_C
- ASM_OUTPUT2
- ASM_PARAM_ID_ENCDEC_ENC_CFG_BLK_V2
- ASM_PARISC_MCKINLEY_H
- ASM_PARISC_RUNWAY_H
- ASM_PARISC_SPARSEMEM_H
- ASM_PASEMI_DMA_H
- ASM_PL080_H
- ASM_POWERPC_DMA_DIRECT_H
- ASM_POWERPC_EEH_EVENT_H
- ASM_PPC_RIO_H
- ASM_RMI_MSIDEF_H
- ASM_SCHID_H
- ASM_SESSION_CMD_PAUSE
- ASM_SESSION_CMD_RUN_V2
- ASM_SESSION_CMD_SUSPEND
- ASM_SHIFT_GAPLESS_MODE_FLAG
- ASM_SHIFT_STREAM_PERF_MODE_FLAG_IN_OPEN_READ
- ASM_SIU_H
- ASM_SMP_CPUID_REG
- ASM_STAC
- ASM_STREAM_CMD_CLOSE
- ASM_STREAM_CMD_FLUSH
- ASM_STREAM_CMD_FLUSH_READBUFS
- ASM_STREAM_CMD_OPEN_READWRITE_V2
- ASM_STREAM_CMD_OPEN_READ_V3
- ASM_STREAM_CMD_OPEN_WRITE_V3
- ASM_STREAM_CMD_SET_ENCDEC_PARAM
- ASM_STREAM_POSTPROC_TOPO_ID_NONE
- ASM_SUPPORTED
- ASM_SYNC_IO_MODE
- ASM_TIME_H
- ASM_TUN_READ_IO_MODE
- ASM_TUN_WRITE_IO_MODE
- ASM_UD0
- ASM_UD1
- ASM_UD2
- ASM_ULONG_INSN
- ASM_UNREACHABLE
- ASM_UNW_PRLG_GRSAVE
- ASM_UNW_PRLG_PFS
- ASM_UNW_PRLG_PR
- ASM_UNW_PRLG_PSP
- ASM_UNW_PRLG_RP
- ASM_WORD_INSN
- ASM_X86_APBT_H
- ASM_X86_ARCHRANDOM_H
- ASM_X86_CAMELLIA_H
- ASM_X86_CMPXCHG_H
- ASM_X86_DMA_DIRECT_H
- ASM_X86_SERPENT_AVX_H
- ASM_X86_SERPENT_SSE2_H
- ASM_X86_TWOFISH_H
- ASN1_APL
- ASN1_APPL
- ASN1_BMPSTR
- ASN1_BOL
- ASN1_BOOL
- ASN1_BTS
- ASN1_CHRSTR
- ASN1_CLASS_BITS
- ASN1_CON
- ASN1_CONS
- ASN1_CONS_BIT
- ASN1_CONT
- ASN1_CTX
- ASN1_ENUM
- ASN1_EOC
- ASN1_EPDV
- ASN1_ERR_DEC_BADVALUE
- ASN1_ERR_DEC_EMPTY
- ASN1_ERR_DEC_EOC_MISMATCH
- ASN1_ERR_DEC_LENGTH_MISMATCH
- ASN1_ERR_NOERROR
- ASN1_EXT
- ASN1_GENSTR
- ASN1_GENTIM
- ASN1_GRASTR
- ASN1_IA5STR
- ASN1_INDEFINITE_LENGTH
- ASN1_INT
- ASN1_LONG_TAG
- ASN1_NUL
- ASN1_NULL
- ASN1_NUMSTR
- ASN1_ODE
- ASN1_OID
- ASN1_OJD
- ASN1_OJI
- ASN1_OP_ACT
- ASN1_OP_COMPLETE
- ASN1_OP_COND_FAIL
- ASN1_OP_COND_MATCH_ACT_OR_SKIP
- ASN1_OP_COND_MATCH_ANY
- ASN1_OP_COND_MATCH_ANY_ACT
- ASN1_OP_COND_MATCH_ANY_ACT_OR_SKIP
- ASN1_OP_COND_MATCH_ANY_OR_SKIP
- ASN1_OP_COND_MATCH_JUMP_OR_SKIP
- ASN1_OP_COND_MATCH_OR_SKIP
- ASN1_OP_END_SEQ
- ASN1_OP_END_SEQ_ACT
- ASN1_OP_END_SEQ_OF
- ASN1_OP_END_SEQ_OF_ACT
- ASN1_OP_END_SET
- ASN1_OP_END_SET_ACT
- ASN1_OP_END_SET_OF
- ASN1_OP_END_SET_OF_ACT
- ASN1_OP_END__ACT
- ASN1_OP_END__OF
- ASN1_OP_END__SET
- ASN1_OP_MATCH
- ASN1_OP_MATCH_ACT
- ASN1_OP_MATCH_ACT_OR_SKIP
- ASN1_OP_MATCH_ANY
- ASN1_OP_MATCH_ANY_ACT
- ASN1_OP_MATCH_ANY_ACT_OR_SKIP
- ASN1_OP_MATCH_ANY_OR_SKIP
- ASN1_OP_MATCH_JUMP
- ASN1_OP_MATCH_JUMP_OR_SKIP
- ASN1_OP_MATCH_OR_SKIP
- ASN1_OP_MATCH__ACT
- ASN1_OP_MATCH__ANY
- ASN1_OP_MATCH__COND
- ASN1_OP_MATCH__JUMP
- ASN1_OP_MATCH__SKIP
- ASN1_OP_MAYBE_ACT
- ASN1_OP_RETURN
- ASN1_OP__MATCHES_TAG
- ASN1_OP__NR
- ASN1_OTS
- ASN1_PRI
- ASN1_PRIM
- ASN1_PRIV
- ASN1_PRNSTR
- ASN1_PRV
- ASN1_REAL
- ASN1_RELOID
- ASN1_SEQ
- ASN1_SET
- ASN1_TEXSTR
- ASN1_UNI
- ASN1_UNISTR
- ASN1_UNITIM
- ASN1_UNIV
- ASN1_UTF8STR
- ASN1_VIDSTR
- ASN1_VISSTR
- ASN_CODE
- ASN_FIRST_VERSION
- ASOC_MADERA_H
- ASP1_RX_EVT_EN
- ASP1_TX_EVT_EN
- ASPECT_RATIO_16_9
- ASPECT_RATIO_256_135
- ASPECT_RATIO_4_3
- ASPECT_RATIO_64_27
- ASPECT_RATIO_FUTURE
- ASPECT_RATIO_INFO
- ASPECT_RATIO_NO_DATA
- ASPEED_ADC_CTRL_INIT_RDY
- ASPEED_ADC_INIT_POLLING_TIME
- ASPEED_ADC_INIT_TIMEOUT
- ASPEED_APLL_PARAM
- ASPEED_CHAN
- ASPEED_CLK_24M
- ASPEED_CLK_AHB
- ASPEED_CLK_APB
- ASPEED_CLK_APB1
- ASPEED_CLK_APB2
- ASPEED_CLK_APLL
- ASPEED_CLK_BCLK
- ASPEED_CLK_D1CLK
- ASPEED_CLK_DPLL
- ASPEED_CLK_ECLK
- ASPEED_CLK_ECLK_MUX
- ASPEED_CLK_EMMC
- ASPEED_CLK_EPLL
- ASPEED_CLK_GATE_BCLK
- ASPEED_CLK_GATE_D1CLK
- ASPEED_CLK_GATE_DCLK
- ASPEED_CLK_GATE_ECLK
- ASPEED_CLK_GATE_EMMCCLK
- ASPEED_CLK_GATE_ESPICLK
- ASPEED_CLK_GATE_FSICLK
- ASPEED_CLK_GATE_GCLK
- ASPEED_CLK_GATE_I3C0CLK
- ASPEED_CLK_GATE_I3C1CLK
- ASPEED_CLK_GATE_I3C2CLK
- ASPEED_CLK_GATE_I3C3CLK
- ASPEED_CLK_GATE_I3C4CLK
- ASPEED_CLK_GATE_I3C5CLK
- ASPEED_CLK_GATE_I3C6CLK
- ASPEED_CLK_GATE_I3C7CLK
- ASPEED_CLK_GATE_LCLK
- ASPEED_CLK_GATE_LHCCLK
- ASPEED_CLK_GATE_MAC1CLK
- ASPEED_CLK_GATE_MAC2CLK
- ASPEED_CLK_GATE_MAC3CLK
- ASPEED_CLK_GATE_MAC4CLK
- ASPEED_CLK_GATE_MCLK
- ASPEED_CLK_GATE_REF0CLK
- ASPEED_CLK_GATE_REF1CLK
- ASPEED_CLK_GATE_REFCLK
- ASPEED_CLK_GATE_RSACLK
- ASPEED_CLK_GATE_RVASCLK
- ASPEED_CLK_GATE_SDCLK
- ASPEED_CLK_GATE_UART10CLK
- ASPEED_CLK_GATE_UART11CLK
- ASPEED_CLK_GATE_UART12CLK
- ASPEED_CLK_GATE_UART13CLK
- ASPEED_CLK_GATE_UART1CLK
- ASPEED_CLK_GATE_UART2CLK
- ASPEED_CLK_GATE_UART3CLK
- ASPEED_CLK_GATE_UART4CLK
- ASPEED_CLK_GATE_UART5CLK
- ASPEED_CLK_GATE_UART6CLK
- ASPEED_CLK_GATE_UART7CLK
- ASPEED_CLK_GATE_UART8CLK
- ASPEED_CLK_GATE_UART9CLK
- ASPEED_CLK_GATE_USBPORT1CLK
- ASPEED_CLK_GATE_USBPORT2CLK
- ASPEED_CLK_GATE_USBUHCICLK
- ASPEED_CLK_GATE_VCLK
- ASPEED_CLK_GATE_YCLK
- ASPEED_CLK_HPLL
- ASPEED_CLK_LHCLK
- ASPEED_CLK_MAC
- ASPEED_CLK_MAC12
- ASPEED_CLK_MAC34
- ASPEED_CLK_MPLL
- ASPEED_CLK_SDIO
- ASPEED_CLK_SELECTION
- ASPEED_CLK_SELECTION_2
- ASPEED_CLK_STOP_CTRL
- ASPEED_CLK_UART
- ASPEED_CLK_UARTX
- ASPEED_CLK_USBPHY_40M
- ASPEED_CLK_VCLK
- ASPEED_CLOCKS_PER_SAMPLE
- ASPEED_DPLL_PARAM
- ASPEED_ENGINE_ENABLE
- ASPEED_EPLL_PARAM
- ASPEED_G4_NR_PINS
- ASPEED_G5_NR_PINS
- ASPEED_G6_CLK_SELECTION1
- ASPEED_G6_CLK_SELECTION2
- ASPEED_G6_CLK_SELECTION4
- ASPEED_G6_CLK_STOP_CTRL
- ASPEED_G6_CLK_STOP_CTRL2
- ASPEED_G6_MISC_CTRL
- ASPEED_G6_NR_PINS
- ASPEED_G6_NUM_CLKS
- ASPEED_G6_RESET_CTRL
- ASPEED_G6_RESET_CTRL2
- ASPEED_G6_SILICON_REV
- ASPEED_G6_STRAP1
- ASPEED_GPIO
- ASPEED_GPIO_PORT_A
- ASPEED_GPIO_PORT_AA
- ASPEED_GPIO_PORT_AB
- ASPEED_GPIO_PORT_AC
- ASPEED_GPIO_PORT_B
- ASPEED_GPIO_PORT_C
- ASPEED_GPIO_PORT_D
- ASPEED_GPIO_PORT_E
- ASPEED_GPIO_PORT_F
- ASPEED_GPIO_PORT_G
- ASPEED_GPIO_PORT_H
- ASPEED_GPIO_PORT_I
- ASPEED_GPIO_PORT_J
- ASPEED_GPIO_PORT_K
- ASPEED_GPIO_PORT_L
- ASPEED_GPIO_PORT_M
- ASPEED_GPIO_PORT_N
- ASPEED_GPIO_PORT_O
- ASPEED_GPIO_PORT_P
- ASPEED_GPIO_PORT_Q
- ASPEED_GPIO_PORT_R
- ASPEED_GPIO_PORT_S
- ASPEED_GPIO_PORT_T
- ASPEED_GPIO_PORT_U
- ASPEED_GPIO_PORT_V
- ASPEED_GPIO_PORT_W
- ASPEED_GPIO_PORT_X
- ASPEED_GPIO_PORT_Y
- ASPEED_GPIO_PORT_Z
- ASPEED_HPLL_PARAM
- ASPEED_I2CD_BUS_BUSY_STS
- ASPEED_I2CD_BUS_RECOVER_CMD
- ASPEED_I2CD_DEV_ADDR_MASK
- ASPEED_I2CD_INTR_ABNORMAL
- ASPEED_I2CD_INTR_ALL
- ASPEED_I2CD_INTR_ARBIT_LOSS
- ASPEED_I2CD_INTR_BUS_RECOVER_DONE
- ASPEED_I2CD_INTR_MASTER_ERRORS
- ASPEED_I2CD_INTR_NORMAL_STOP
- ASPEED_I2CD_INTR_RX_DONE
- ASPEED_I2CD_INTR_SCL_TIMEOUT
- ASPEED_I2CD_INTR_SDA_DL_TIMEOUT
- ASPEED_I2CD_INTR_SLAVE_MATCH
- ASPEED_I2CD_INTR_TX_ACK
- ASPEED_I2CD_INTR_TX_NAK
- ASPEED_I2CD_MASTER_CMDS_MASK
- ASPEED_I2CD_MASTER_EN
- ASPEED_I2CD_MULTI_MASTER_DIS
- ASPEED_I2CD_M_HIGH_SPEED_EN
- ASPEED_I2CD_M_RX_CMD
- ASPEED_I2CD_M_SDA_DRIVE_1T_EN
- ASPEED_I2CD_M_START_CMD
- ASPEED_I2CD_M_STOP_CMD
- ASPEED_I2CD_M_S_RX_CMD_LAST
- ASPEED_I2CD_M_TX_CMD
- ASPEED_I2CD_SCL_LINE_STS
- ASPEED_I2CD_SDA_DRIVE_1T_EN
- ASPEED_I2CD_SDA_LINE_STS
- ASPEED_I2CD_SLAVE_EN
- ASPEED_I2CD_S_TX_CMD
- ASPEED_I2CD_TIME_BASE_DIVISOR_MASK
- ASPEED_I2CD_TIME_SCL_HIGH_MASK
- ASPEED_I2CD_TIME_SCL_HIGH_SHIFT
- ASPEED_I2CD_TIME_SCL_LOW_MASK
- ASPEED_I2CD_TIME_SCL_LOW_SHIFT
- ASPEED_I2CD_TIME_SCL_REG_MAX
- ASPEED_I2CD_TIME_TACST_MASK
- ASPEED_I2CD_TIME_TBUF_MASK
- ASPEED_I2CD_TIME_THDSTA_MASK
- ASPEED_I2C_AC_TIMING_REG1
- ASPEED_I2C_AC_TIMING_REG2
- ASPEED_I2C_BYTE_BUF_REG
- ASPEED_I2C_CMD_REG
- ASPEED_I2C_DEV_ADDR_REG
- ASPEED_I2C_FUN_CTRL_REG
- ASPEED_I2C_IC_NUM_BUS
- ASPEED_I2C_INTR_CTRL_REG
- ASPEED_I2C_INTR_STS_REG
- ASPEED_I2C_MASTER_INACTIVE
- ASPEED_I2C_MASTER_PENDING
- ASPEED_I2C_MASTER_RX
- ASPEED_I2C_MASTER_RX_FIRST
- ASPEED_I2C_MASTER_START
- ASPEED_I2C_MASTER_STOP
- ASPEED_I2C_MASTER_TX
- ASPEED_I2C_MASTER_TX_FIRST
- ASPEED_I2C_SLAVE_INACTIVE
- ASPEED_I2C_SLAVE_READ_PROCESSED
- ASPEED_I2C_SLAVE_READ_REQUESTED
- ASPEED_I2C_SLAVE_START
- ASPEED_I2C_SLAVE_STOP
- ASPEED_I2C_SLAVE_WRITE_RECEIVED
- ASPEED_I2C_SLAVE_WRITE_REQUESTED
- ASPEED_IP_GFX
- ASPEED_IP_LPC
- ASPEED_IP_SCU
- ASPEED_LPC_CTRL_IOCTL_GET_SIZE
- ASPEED_LPC_CTRL_IOCTL_MAP
- ASPEED_LPC_CTRL_WINDOW_FLASH
- ASPEED_LPC_CTRL_WINDOW_MEMORY
- ASPEED_MCR_ADDR_REC
- ASPEED_MCR_ADDR_UNREC
- ASPEED_MCR_CONF
- ASPEED_MCR_CONF_DRAM_TYPE
- ASPEED_MCR_CONF_ECC
- ASPEED_MCR_INTR_CTRL
- ASPEED_MCR_INTR_CTRL_CLEAR
- ASPEED_MCR_INTR_CTRL_CNT_REC
- ASPEED_MCR_INTR_CTRL_CNT_UNREC
- ASPEED_MCR_INTR_CTRL_ENABLE
- ASPEED_MCR_LAST
- ASPEED_MCR_PROT
- ASPEED_MCR_PROT_PASSWD
- ASPEED_MDIO_CTRL
- ASPEED_MDIO_CTRL_FIRE
- ASPEED_MDIO_CTRL_MIIWDATA
- ASPEED_MDIO_CTRL_OP
- ASPEED_MDIO_CTRL_PHYAD
- ASPEED_MDIO_CTRL_REGAD
- ASPEED_MDIO_CTRL_ST
- ASPEED_MDIO_CTRL_ST_C22
- ASPEED_MDIO_CTRL_ST_C45
- ASPEED_MDIO_DATA
- ASPEED_MDIO_DATA_IDLE
- ASPEED_MDIO_DATA_MDC_THRES
- ASPEED_MDIO_DATA_MDIO_EDGE
- ASPEED_MDIO_DATA_MDIO_LATCH
- ASPEED_MDIO_DATA_MIIRDATA
- ASPEED_MDIO_INTERVAL_US
- ASPEED_MDIO_TIMEOUT_US
- ASPEED_MISC_CTRL
- ASPEED_MPLL_PARAM
- ASPEED_NO_TIMEOUT_CTRL
- ASPEED_NR_PINMUX_IPS
- ASPEED_NUM_CLKS
- ASPEED_OPERATION_MODE_NORMAL
- ASPEED_OPERATION_MODE_POWER_DOWN
- ASPEED_OPERATION_MODE_STANDBY
- ASPEED_P2A_CTRL_IOCTL_GET_MEMORY_CONFIG
- ASPEED_P2A_CTRL_IOCTL_SET_WINDOW
- ASPEED_P2A_CTRL_READWRITE
- ASPEED_P2A_CTRL_READ_ONLY
- ASPEED_PINCTRL_FUNC
- ASPEED_PINCTRL_GROUP
- ASPEED_PINCTRL_PIN
- ASPEED_PINMUX_H
- ASPEED_PTCR_CLK_CTRL
- ASPEED_PTCR_CLK_CTRL_EXT
- ASPEED_PTCR_CLK_CTRL_TYPEM_H
- ASPEED_PTCR_CLK_CTRL_TYPEM_L
- ASPEED_PTCR_CLK_CTRL_TYPEM_MASK
- ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT
- ASPEED_PTCR_CLK_CTRL_TYPEN_H
- ASPEED_PTCR_CLK_CTRL_TYPEN_L
- ASPEED_PTCR_CLK_CTRL_TYPEN_MASK
- ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT
- ASPEED_PTCR_CLK_CTRL_TYPEO_H
- ASPEED_PTCR_CLK_CTRL_TYPEO_L
- ASPEED_PTCR_CLK_CTRL_TYPEO_MASK
- ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT
- ASPEED_PTCR_CTRL
- ASPEED_PTCR_CTRL_CLK_EN
- ASPEED_PTCR_CTRL_CLK_SRC
- ASPEED_PTCR_CTRL_EXT
- ASPEED_PTCR_CTRL_FAN_NUM_EN
- ASPEED_PTCR_CTRL_PWMA_EN
- ASPEED_PTCR_CTRL_PWMB_EN
- ASPEED_PTCR_CTRL_PWMC_EN
- ASPEED_PTCR_CTRL_PWMD_EN
- ASPEED_PTCR_CTRL_PWME_EN
- ASPEED_PTCR_CTRL_PWMF_EN
- ASPEED_PTCR_CTRL_PWMG_EN
- ASPEED_PTCR_CTRL_PWMH_EN
- ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2
- ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK
- ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1
- ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2
- ASPEED_PTCR_DUTY0_CTRL
- ASPEED_PTCR_DUTY1_CTRL
- ASPEED_PTCR_DUTY2_CTRL
- ASPEED_PTCR_DUTY3_CTRL
- ASPEED_PTCR_INTR_CTRL
- ASPEED_PTCR_INTR_STS
- ASPEED_PTCR_RESULT
- ASPEED_PTCR_TACH_SOURCE
- ASPEED_PTCR_TACH_SOURCE_EXT
- ASPEED_PTCR_TRIGGER
- ASPEED_PTCR_TYPEM_CTRL
- ASPEED_PTCR_TYPEM_CTRL1
- ASPEED_PTCR_TYPEM_LIMIT
- ASPEED_PTCR_TYPEN_CTRL
- ASPEED_PTCR_TYPEN_CTRL1
- ASPEED_PTCR_TYPEN_LIMIT
- ASPEED_PTCR_TYPEO_CTRL
- ASPEED_PTCR_TYPEO_CTRL1
- ASPEED_PTCR_TYPEO_LIMIT
- ASPEED_REG_CLOCK_CONTROL
- ASPEED_REG_ENGINE_CONTROL
- ASPEED_REG_INTERRUPT_CONTROL
- ASPEED_REG_MAX
- ASPEED_REG_VGA_DETECT_CONTROL
- ASPEED_RESET2_OFFSET
- ASPEED_RESET_ADC
- ASPEED_RESET_AHB
- ASPEED_RESET_CRT1
- ASPEED_RESET_CTRL
- ASPEED_RESET_CTRL2
- ASPEED_RESET_DEV_MCTP
- ASPEED_RESET_DEV_XDMA
- ASPEED_RESET_DP
- ASPEED_RESET_DP_MCU
- ASPEED_RESET_GP_MCU
- ASPEED_RESET_GRAPHICS
- ASPEED_RESET_H2X
- ASPEED_RESET_I2C
- ASPEED_RESET_I3C_DMA
- ASPEED_RESET_JTAG_MASTER
- ASPEED_RESET_JTAG_MASTER2
- ASPEED_RESET_MCTP
- ASPEED_RESET_MIC
- ASPEED_RESET_MII
- ASPEED_RESET_PCIE_DEV_O
- ASPEED_RESET_PCIE_DEV_OEN
- ASPEED_RESET_PCIE_RC_O
- ASPEED_RESET_PCIE_RC_OEN
- ASPEED_RESET_PCI_DP
- ASPEED_RESET_PECI
- ASPEED_RESET_PWM
- ASPEED_RESET_RC_MCTP
- ASPEED_RESET_RC_XDMA
- ASPEED_RESET_SDRAM
- ASPEED_RESET_XDMA
- ASPEED_RESOLUTION_BITS
- ASPEED_RPM_STATUS_SLEEP_USEC
- ASPEED_SDC_INFO
- ASPEED_SDC_S0MMC8
- ASPEED_SDC_S1MMC8
- ASPEED_SGPIO_CLK_DIV_MASK
- ASPEED_SGPIO_CTRL
- ASPEED_SGPIO_ENABLE
- ASPEED_SGPIO_PINS_MASK
- ASPEED_STRAP
- ASPEED_VIDEO_JPEG_DCT_SIZE
- ASPEED_VIDEO_JPEG_HEADER_SIZE
- ASPEED_VIDEO_JPEG_NUM_QUALITIES
- ASPEED_VIDEO_JPEG_QUANT_SIZE
- ASPEED_VUART_ADDRH
- ASPEED_VUART_ADDRL
- ASPEED_VUART_GCRA
- ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD
- ASPEED_VUART_GCRA_VUART_EN
- ASPEED_VUART_GCRB
- ASPEED_VUART_GCRB_HOST_SIRQ_MASK
- ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT
- ASPENCODING
- ASPFMTALAW
- ASPFMTLINEAR16
- ASPFMTLINEAR8
- ASPFMTSPDIF
- ASPFMTSPORT
- ASPFMTULAW
- ASPI_SUPPORT
- ASPM_FORCE_CTL
- ASPM_L1_1_EN
- ASPM_L1_1_EN_MASK
- ASPM_L1_2_EN
- ASPM_L1_2_EN_MASK
- ASPM_L1_EN
- ASPM_L1_LATENCY
- ASPM_L1_SUPPORTED
- ASPM_MASK_NEG
- ASPM_MODE_DISABLED
- ASPM_MODE_DYNAMIC
- ASPM_MODE_ENABLED
- ASPM_RESCHED_TIMER_MS
- ASPM_STATE_ALL
- ASPM_STATE_L0S
- ASPM_STATE_L0S_DW
- ASPM_STATE_L0S_UP
- ASPM_STATE_L1
- ASPM_STATE_L1SS
- ASPM_STATE_L1_1
- ASPM_STATE_L1_1_PCIPM
- ASPM_STATE_L1_2
- ASPM_STATE_L1_2_MASK
- ASPM_STATE_L1_2_PCIPM
- ASPM_STATE_L1_SS_PCIPM
- ASPM_THRUPUT_LIMIT_100M
- ASPM_THRUPUT_LIMIT_10M
- ASPM_THRUPUT_LIMIT_1M
- ASPM_THRUPUT_LIMIT_MASK
- ASPM_THRUPUT_LIMIT_NO
- ASPM_THRUPUT_LIMIT_SHIFT
- ASPM_TIMER_MS
- ASPM_TRIGGER_MS
- ASPM_TRIGGER_NS
- ASPM_en
- ASP_GSC_IRQ
- ASP_INTERRUPT_ADDR
- ASP_LED_ADDR
- ASP_VER_OFFSET
- ASRC0
- ASRC1
- ASRCDRi_AICD
- ASRCDRi_AICDi_MASK
- ASRCDRi_AICDi_SHIFT
- ASRCDRi_AICP
- ASRCDRi_AICPi_MASK
- ASRCDRi_AICPi_SHIFT
- ASRCDRi_AOCD
- ASRCDRi_AOCDi_MASK
- ASRCDRi_AOCDi_SHIFT
- ASRCDRi_AOCP
- ASRCDRi_AOCPi_MASK
- ASRCDRi_AOCPi_SHIFT
- ASRCDRi_AxCPi_WIDTH
- ASRCFG_INIRQi
- ASRCFG_INIRQi_MASK
- ASRCFG_INIRQi_SHIFT
- ASRCFG_NDPRi
- ASRCFG_NDPRi_ALL_MASK
- ASRCFG_NDPRi_ALL_SHIFT
- ASRCFG_NDPRi_MASK
- ASRCFG_NDPRi_SHIFT
- ASRCFG_POSTMOD
- ASRCFG_POSTMODi_ALL_MASK
- ASRCFG_POSTMODi_DCON
- ASRCFG_POSTMODi_DOWN
- ASRCFG_POSTMODi_MASK
- ASRCFG_POSTMODi_SHIFT
- ASRCFG_POSTMODi_UP
- ASRCFG_POSTMODi_WIDTH
- ASRCFG_PREMOD
- ASRCFG_PREMODi_ALL_MASK
- ASRCFG_PREMODi_BYPASS
- ASRCFG_PREMODi_DCON
- ASRCFG_PREMODi_DOWN
- ASRCFG_PREMODi_MASK
- ASRCFG_PREMODi_SHIFT
- ASRCFG_PREMODi_UP
- ASRCFG_PREMODi_WIDTH
- ASRCNCR_ANCi
- ASRCNCR_ANCi_MASK
- ASRCNCR_ANCi_SHIFT
- ASRCSR_AICS
- ASRCSR_AICSi_MASK
- ASRCSR_AICSi_SHIFT
- ASRCSR_AOCS
- ASRCSR_AOCSi_MASK
- ASRCSR_AOCSi_SHIFT
- ASRCSR_AxCSi_MASK
- ASRCSR_AxCSi_WIDTH
- ASRCTR_ASRCE
- ASRCTR_ASRCEN
- ASRCTR_ASRCEN_MASK
- ASRCTR_ASRCEN_SHIFT
- ASRCTR_ASRCEi_ALL_MASK
- ASRCTR_ASRCEi_MASK
- ASRCTR_ASRCEi_SHIFT
- ASRCTR_ATS
- ASRCTR_ATSi_MASK
- ASRCTR_ATSi_SHIFT
- ASRCTR_IDR
- ASRCTR_IDRi_MASK
- ASRCTR_IDRi_SHIFT
- ASRCTR_SRST
- ASRCTR_SRST_MASK
- ASRCTR_SRST_SHIFT
- ASRCTR_USR
- ASRCTR_USRi_MASK
- ASRCTR_USRi_SHIFT
- ASRC_CLK_MAX_NUM
- ASRC_DMA_BUFFER_NUM
- ASRC_DMA_BUFFER_SIZE
- ASRC_FIFO_THRESHOLD_MAX
- ASRC_FIFO_THRESHOLD_MIN
- ASRC_INPUTFIFO_THRESHOLD
- ASRC_INPUT_BUFFER_UNDERRUN
- ASRC_INPUT_TASK_OVERLOAD
- ASRC_INVALID_PAIR
- ASRC_MAX_BUFFER_SIZE
- ASRC_OUTPUTFIFO_THRESHOLD
- ASRC_OUTPUT_BUFFER_OVERFLOW
- ASRC_OUTPUT_LAST_SAMPLE
- ASRC_OUTPUT_TASK_OVERLOAD
- ASRC_PAIR_A
- ASRC_PAIR_B
- ASRC_PAIR_C
- ASRC_PAIR_MAX_NUM
- ASRC_TASK_Q_OVERLOAD
- ASRC_WIDTH_16_BIT
- ASRC_WIDTH_24_BIT
- ASRC_WIDTH_8_BIT
- ASRFSTi_IAEi
- ASRFSTi_IAEi_MASK
- ASRFSTi_IAEi_SHIFT
- ASRFSTi_INPUT_FIFO_MASK
- ASRFSTi_INPUT_FIFO_SHIFT
- ASRFSTi_INPUT_FIFO_WIDTH
- ASRFSTi_OAFi
- ASRFSTi_OAFi_MASK
- ASRFSTi_OAFi_SHIFT
- ASRFSTi_OUTPUT_FIFO_MASK
- ASRFSTi_OUTPUT_FIFO_SHIFT
- ASRFSTi_OUTPUT_FIFO_WIDTH
- ASRIER_ADIE
- ASRIER_ADIEi_MASK
- ASRIER_ADIEi_SHIFT
- ASRIER_ADOE
- ASRIER_ADOEi_MASK
- ASRIER_ADOEi_SHIFT
- ASRIER_AFPWE
- ASRIER_AFPWE_MASK
- ASRIER_AFPWE_SHIFT
- ASRIER_AOLIE
- ASRIER_AOLIE_MASK
- ASRIER_AOLIE_SHIFT
- ASRMCR1i_IMSB_LSB
- ASRMCR1i_IMSB_MASK
- ASRMCR1i_IMSB_MSB
- ASRMCR1i_IMSB_SHIFT
- ASRMCR1i_IWD
- ASRMCR1i_IWD_MASK
- ASRMCR1i_IWD_SHIFT
- ASRMCR1i_IWD_WIDTH
- ASRMCR1i_OMSB_LSB
- ASRMCR1i_OMSB_MASK
- ASRMCR1i_OMSB_MSB
- ASRMCR1i_OMSB_SHIFT
- ASRMCR1i_OSGN
- ASRMCR1i_OSGN_MASK
- ASRMCR1i_OSGN_SHIFT
- ASRMCR1i_OW16
- ASRMCR1i_OW16_MASK
- ASRMCR1i_OW16_SHIFT
- ASRMCRi_BUFSTALLi
- ASRMCRi_BUFSTALLi_MASK
- ASRMCRi_BUFSTALLi_SHIFT
- ASRMCRi_BYPASSPOLYi
- ASRMCRi_BYPASSPOLYi_MASK
- ASRMCRi_BYPASSPOLYi_SHIFT
- ASRMCRi_EXTTHRSHi
- ASRMCRi_EXTTHRSHi_MASK
- ASRMCRi_EXTTHRSHi_SHIFT
- ASRMCRi_INFIFO_THRESHOLD
- ASRMCRi_INFIFO_THRESHOLD_MASK
- ASRMCRi_INFIFO_THRESHOLD_SHIFT
- ASRMCRi_INFIFO_THRESHOLD_WIDTH
- ASRMCRi_OUTFIFO_THRESHOLD
- ASRMCRi_OUTFIFO_THRESHOLD_MASK
- ASRMCRi_OUTFIFO_THRESHOLD_SHIFT
- ASRMCRi_OUTFIFO_THRESHOLD_WIDTH
- ASRMCRi_RSYNIFi
- ASRMCRi_RSYNIFi_MASK
- ASRMCRi_RSYNIFi_SHIFT
- ASRMCRi_RSYNOFi
- ASRMCRi_RSYNOFi_MASK
- ASRMCRi_RSYNOFi_SHIFT
- ASRMCRi_ZEROBUFi
- ASRMCRi_ZEROBUFi_MASK
- ASRMCRi_ZEROBUFi_SHIFT
- ASRSTR_AIDE
- ASRSTR_AIDEi_MASK
- ASRSTR_AIDEi_SHIFT
- ASRSTR_AIDU
- ASRSTR_AIDUi_MASK
- ASRSTR_AIDUi_SHIFT
- ASRSTR_AIOL
- ASRSTR_AIOLi_MASK
- ASRSTR_AIOLi_SHIFT
- ASRSTR_AODEi_SHIFT
- ASRSTR_AODF
- ASRSTR_AODFi_MASK
- ASRSTR_AODO
- ASRSTR_AODOi_MASK
- ASRSTR_AODOi_SHIFT
- ASRSTR_AOLE
- ASRSTR_AOLE_MASK
- ASRSTR_AOLE_SHIFT
- ASRSTR_AOOL
- ASRSTR_AOOLi_MASK
- ASRSTR_AOOLi_SHIFT
- ASRSTR_ATQOL
- ASRSTR_ATQOL_MASK
- ASRSTR_ATQOL_SHIFT
- ASRSTR_DSLCNT
- ASRSTR_DSLCNT_MASK
- ASRSTR_DSLCNT_SHIFT
- ASRSTR_FPWT
- ASRSTR_FPWT_MASK
- ASRSTR_FPWT_SHIFT
- ASRTFR1_TF_BASE
- ASRTFR1_TF_BASE_MASK
- ASRTFR1_TF_BASE_SHIFT
- ASRTFR1_TF_BASE_WIDTH
- ASR_BSY
- ASR_CIP
- ASR_DBR
- ASR_INT
- ASR_LCI
- ASR_MASK
- ASR_PE
- ASR_SHIFT
- ASSABET_BCR
- ASSABET_BCR_AUDIO_ON
- ASSABET_BCR_BASE
- ASSABET_BCR_CF_BUS_OFF
- ASSABET_BCR_CF_PWR
- ASSABET_BCR_CF_RST
- ASSABET_BCR_COM_DTR
- ASSABET_BCR_COM_RTS
- ASSABET_BCR_DB1110
- ASSABET_BCR_DB1111
- ASSABET_BCR_IRDA_FSEL
- ASSABET_BCR_IRDA_MD0
- ASSABET_BCR_IRDA_MD1
- ASSABET_BCR_LCD_12RGB
- ASSABET_BCR_LCD_ON
- ASSABET_BCR_LED_GREEN
- ASSABET_BCR_LED_RED
- ASSABET_BCR_LIGHT_ON
- ASSABET_BCR_NCODEC_RST
- ASSABET_BCR_NGFX_RST
- ASSABET_BCR_QMUTE
- ASSABET_BCR_RAD_ON
- ASSABET_BCR_RAD_WU
- ASSABET_BCR_RS232EN
- ASSABET_BCR_SMB_EN
- ASSABET_BCR_SPK_OFF
- ASSABET_BCR_STEREO_LB
- ASSABET_BCR_TV_IR_DEC
- ASSABET_BCR_VIB_ON
- ASSABET_BCR_clear
- ASSABET_BCR_frob
- ASSABET_BCR_set
- ASSABET_BSR
- ASSABET_BSR_BASE
- ASSABET_BSR_COM_CTS
- ASSABET_BSR_COM_DCD
- ASSABET_BSR_COM_DSR
- ASSABET_BSR_RAD_CTS
- ASSABET_BSR_RAD_DCD
- ASSABET_BSR_RAD_DSR
- ASSABET_BSR_RAD_RI
- ASSABET_BSR_RS232_VALID
- ASSABET_GPIO_BATT_LOW
- ASSABET_GPIO_GFX_IRQ
- ASSABET_GPIO_PS_MODE_SYNC
- ASSABET_GPIO_RADIO_IRQ
- ASSABET_GPIO_RCLK
- ASSABET_GPIO_STEREO_64FS_CLK
- ASSABET_SCR_FLASH_HIGH
- ASSABET_SCR_FLASH_LOW
- ASSABET_SCR_GFX
- ASSABET_SCR_INIT
- ASSABET_SCR_SA1111
- ASSABET_SCR_SDRAM_HIGH
- ASSABET_SCR_SDRAM_LOW
- ASSACT_PANIC
- ASSACT_REPORT
- ASSACT_RO
- ASSERT
- ASSERTCMP
- ASSERTIF
- ASSERTIFCMP
- ASSERTRANGE
- ASSERT_ACTION
- ASSERT_ALWAYS
- ASSERT_BLOCK_LOCKED
- ASSERT_CLEAR
- ASSERT_CRITICAL
- ASSERT_EQ
- ASSERT_EVEN_PARITY
- ASSERT_FALSE
- ASSERT_GE
- ASSERT_GT
- ASSERT_LE
- ASSERT_LT
- ASSERT_NE
- ASSERT_NONE
- ASSERT_NULL
- ASSERT_OUT_NAKING
- ASSERT_OVSL
- ASSERT_PDIR_SANITY
- ASSERT_RHT_MUTEX
- ASSERT_RST
- ASSERT_RTNL
- ASSERT_SET
- ASSERT_STREQ
- ASSERT_STRNE
- ASSERT_TRUE
- ASSERT_WDEV_LOCK
- ASSIGN
- ASSIGNED
- ASSIGN_32BIT_COUNTER
- ASSIGN_CTX_PDP
- ASSIGN_CTX_PML4
- ASSIGN_FETCH_TYPE
- ASSIGN_FETCH_TYPE_ALIAS
- ASSIGN_FETCH_TYPE_END
- ASSIGN_FUNC
- ASSIGN_FUNC_IPAC
- ASSIGN_FW_DOMAINS_TABLE
- ASSIGN_ID
- ASSIGN_OPS_HASH
- ASSIGN_RAW_READ_MMIO_VFUNCS
- ASSIGN_RAW_WRITE_MMIO_VFUNCS
- ASSIGN_READ_MMIO_VFUNCS
- ASSIGN_SAS_TASK
- ASSIGN_VMD_DMA_OPS
- ASSIGN_WRITE_MMIO_VFUNCS
- ASSIST_MBOX1_CLR_REG
- ASSIST_MBOX1_MASK
- ASSOCIATED
- ASSOCIATE_ENTRY_NUM
- ASSOC_ARRAY_FAN_MASK
- ASSOC_ARRAY_FAN_OUT
- ASSOC_ARRAY_KEY_CHUNK_MASK
- ASSOC_ARRAY_KEY_CHUNK_SHIFT
- ASSOC_ARRAY_KEY_CHUNK_SIZE
- ASSOC_ARRAY_LEVEL_STEP
- ASSOC_ARRAY_LEVEL_STEP_MASK
- ASSOC_ARRAY_PTR_LEAF_TYPE
- ASSOC_ARRAY_PTR_META_TYPE
- ASSOC_ARRAY_PTR_NODE_SUBTYPE
- ASSOC_ARRAY_PTR_SHORTCUT_SUBTYPE
- ASSOC_ARRAY_PTR_SUBTYPE_MASK
- ASSOC_ARRAY_PTR_TYPE_MASK
- ASSOC_EVENT
- ASSOC_FAILED
- ASSOC_INPROG_PHY
- ASSOC_REQ_DISABLE_HT
- ASSOC_REQ_DISABLE_VHT
- ASSOC_REQ_TYPE
- ASSOC_REQ_USE_RRM
- ASSOC_RESP_TYPE
- ASSP_0_WS_ENABLE
- ASSP_CLK_49MHZ_SELECT
- ASSP_CONTROL_A
- ASSP_CONTROL_B
- ASSP_CONTROL_C
- ASSP_CTRL_A_RESERVED1
- ASSP_CTRL_A_RESERVED2
- ASSP_CTRL_A_RESERVED3
- ASSP_DATA
- ASSP_DATA_PORT
- ASSP_HOSTW_DATA
- ASSP_HOSTW_INDEX
- ASSP_HOSTW_IRQ
- ASSP_HOST_INT_ENABLE
- ASSP_HOST_INT_STATUS
- ASSP_INDEX
- ASSP_INDEX_PORT
- ASSP_INT_ENABLE
- ASSP_INT_PENDING
- ASSP_MEMORY
- ASSP_MEMORY_PORT
- ASSUME_H
- ASSURE_BLOCK_NUMBER
- ASS_CLK_DIV
- ASS_CLK_GATE
- ASS_CLK_SRC
- AST1100
- AST1180
- AST2000
- AST2100
- AST2150
- AST2200
- AST2300
- AST2400
- AST2400_CLK_SOURCE_SEL
- AST2400_HPLL_BYPASS_EN
- AST2400_HPLL_PROGRAMMED
- AST2500
- AST2500PreCatchCRT
- AST2500_HPLL_BYPASS_EN
- ASTAT3_ACTDEASS
- ASTAT3_IRQEN
- ASTAT3_IRQMASK
- ASTAT3_RAMOVRLY
- ASTAT3_TARGERR
- ASTATUS
- ASTATUS_FC
- ASTAT_ARB
- ASTAT_BUSEN
- ASTAT_FIFODIR
- ASTAT_FIFOEN
- ASTAT_IRQ
- ASTAT_PAREN
- ASTAT_PARERR
- ASTAT_RST
- ASTBY_REG
- ASTROMETA_T2HYBRID
- ASTRO_IOC_OFFSET
- ASTRO_RUNWAY_PORT
- ASTRP_RCV
- ASTXQ
- AST_DDR2
- AST_DDR3
- AST_DEFAULT_HWC_NUM
- AST_DRAM_1Gx16
- AST_DRAM_1Gx32
- AST_DRAM_2Gx16
- AST_DRAM_4Gx16
- AST_DRAM_512Mx16
- AST_DRAM_512Mx32
- AST_DRAM_8Gx16
- AST_DRAM_TABLES_H
- AST_HWC_SIGNATURE_CHECKSUM
- AST_HWC_SIGNATURE_HOTSPOTX
- AST_HWC_SIGNATURE_HOTSPOTY
- AST_HWC_SIGNATURE_SIZE
- AST_HWC_SIGNATURE_SizeX
- AST_HWC_SIGNATURE_SizeY
- AST_HWC_SIGNATURE_X
- AST_HWC_SIGNATURE_Y
- AST_HWC_SIZE
- AST_IO_AR_PORT_WRITE
- AST_IO_CRTC_PORT
- AST_IO_DAC_DATA
- AST_IO_DAC_INDEX_READ
- AST_IO_DAC_INDEX_WRITE
- AST_IO_GR_PORT
- AST_IO_INPUT_STATUS1_READ
- AST_IO_MISC_PORT_READ
- AST_IO_MISC_PORT_WRITE
- AST_IO_MM_OFFSET
- AST_IO_SEQ_PORT
- AST_IO_VGA_ENABLE_PORT
- AST_MAX_HWC_HEIGHT
- AST_MAX_HWC_WIDTH
- AST_MM_ALIGN_MASK
- AST_MM_ALIGN_SHIFT
- AST_TABLES_H
- AST_TX_DP501
- AST_TX_ITE66121
- AST_TX_NONE
- AST_TX_SIL164
- AST_VGA_DEVICE
- AST_VHUB_CONF
- AST_VHUB_CONF_DESC_SIZE
- AST_VHUB_CTRL
- AST_VHUB_DESCS_COUNT
- AST_VHUB_DEV_EN_CTRL
- AST_VHUB_DEV_EP0_CTRL
- AST_VHUB_DEV_EP0_DATA
- AST_VHUB_DEV_ISR
- AST_VHUB_EP0_CTRL
- AST_VHUB_EP0_DATA
- AST_VHUB_EP0_MAX_PACKET
- AST_VHUB_EP1_CTRL
- AST_VHUB_EP1_STS_CHG
- AST_VHUB_EP_ACK_IER
- AST_VHUB_EP_ACK_ISR
- AST_VHUB_EP_CONFIG
- AST_VHUB_EP_DESC_BASE
- AST_VHUB_EP_DESC_STATUS
- AST_VHUB_EP_DMA_CTLSTAT
- AST_VHUB_EP_NACK_IER
- AST_VHUB_EP_NACK_ISR
- AST_VHUB_EP_TOGGLE
- AST_VHUB_EPn_MAX_PACKET
- AST_VHUB_HUB_DESC_SIZE
- AST_VHUB_IER
- AST_VHUB_ISO_FAIL_ACC
- AST_VHUB_ISR
- AST_VHUB_NUM_GEN_EPs
- AST_VHUB_NUM_PORTS
- AST_VHUB_SETUP0
- AST_VHUB_SETUP1
- AST_VHUB_STR_MANUF
- AST_VHUB_STR_PRODUCT
- AST_VHUB_STR_SERIAL
- AST_VHUB_SW_RESET
- AST_VHUB_USBSTS
- AST_VIDMEM_DEFAULT_SIZE
- AST_VIDMEM_SIZE_128M
- AST_VIDMEM_SIZE_16M
- AST_VIDMEM_SIZE_32M
- AST_VIDMEM_SIZE_64M
- AST_VIDMEM_SIZE_8M
- ASU
- ASUS_ACPI_UID_ASUSWMI
- ASUS_ACPI_UID_ATK
- ASUS_FAN_BOOST_MODES_MASK
- ASUS_FAN_BOOST_MODE_NORMAL
- ASUS_FAN_BOOST_MODE_OVERBOOST
- ASUS_FAN_BOOST_MODE_OVERBOOST_MASK
- ASUS_FAN_BOOST_MODE_SILENT
- ASUS_FAN_BOOST_MODE_SILENT_MASK
- ASUS_FAN_CTRL_AUTO
- ASUS_FAN_CTRL_FULLSPEED
- ASUS_FAN_CTRL_MANUAL
- ASUS_FAN_DESC
- ASUS_FAN_MFUN
- ASUS_FAN_SFUN_READ
- ASUS_FAN_SFUN_WRITE
- ASUS_HACK
- ASUS_LAPTOP_CLASS
- ASUS_LAPTOP_DEVICE_NAME
- ASUS_LAPTOP_FILE
- ASUS_LAPTOP_NAME
- ASUS_LAPTOP_PREFIX
- ASUS_LAPTOP_VERSION
- ASUS_NB_WMI_EVENT_GUID
- ASUS_NB_WMI_FILE
- ASUS_WMI_BRN_DOWN
- ASUS_WMI_BRN_UP
- ASUS_WMI_CREATE_DEVICE_ATTR
- ASUS_WMI_DEVID_ALS_ENABLE
- ASUS_WMI_DEVID_BACKLIGHT
- ASUS_WMI_DEVID_BLUETOOTH
- ASUS_WMI_DEVID_BRIGHTNESS
- ASUS_WMI_DEVID_CAMERA
- ASUS_WMI_DEVID_CARDREADER
- ASUS_WMI_DEVID_CPU_FAN_CTRL
- ASUS_WMI_DEVID_CWAP
- ASUS_WMI_DEVID_FAN_BOOST_MODE
- ASUS_WMI_DEVID_FAN_CTRL
- ASUS_WMI_DEVID_FNLOCK
- ASUS_WMI_DEVID_GPS
- ASUS_WMI_DEVID_HW_SWITCH
- ASUS_WMI_DEVID_KBD_BACKLIGHT
- ASUS_WMI_DEVID_LED1
- ASUS_WMI_DEVID_LED2
- ASUS_WMI_DEVID_LED3
- ASUS_WMI_DEVID_LED4
- ASUS_WMI_DEVID_LED5
- ASUS_WMI_DEVID_LED6
- ASUS_WMI_DEVID_LID_RESUME
- ASUS_WMI_DEVID_LIGHTBAR
- ASUS_WMI_DEVID_LIGHT_SENSOR
- ASUS_WMI_DEVID_PROCESSOR_STATE
- ASUS_WMI_DEVID_RSOC
- ASUS_WMI_DEVID_THERMAL_CTRL
- ASUS_WMI_DEVID_TOUCHPAD
- ASUS_WMI_DEVID_TOUCHPAD_LED
- ASUS_WMI_DEVID_UWB
- ASUS_WMI_DEVID_WIMAX
- ASUS_WMI_DEVID_WIRELESS_LED
- ASUS_WMI_DEVID_WLAN
- ASUS_WMI_DEVID_WLAN_LED
- ASUS_WMI_DEVID_WWAN3G
- ASUS_WMI_DSTS_BIOS_BIT
- ASUS_WMI_DSTS_BRIGHTNESS_MASK
- ASUS_WMI_DSTS_LIGHTBAR_MASK
- ASUS_WMI_DSTS_MAX_BRIGTH_MASK
- ASUS_WMI_DSTS_PRESENCE_BIT
- ASUS_WMI_DSTS_STATUS_BIT
- ASUS_WMI_DSTS_UNKNOWN_BIT
- ASUS_WMI_DSTS_USER_BIT
- ASUS_WMI_FNLOCK_BIOS_DISABLED
- ASUS_WMI_KEY_IGNORE
- ASUS_WMI_METHODID_AGFN
- ASUS_WMI_METHODID_BSTS
- ASUS_WMI_METHODID_CFVS
- ASUS_WMI_METHODID_DCTS
- ASUS_WMI_METHODID_DEVP
- ASUS_WMI_METHODID_DEVS
- ASUS_WMI_METHODID_DSTS
- ASUS_WMI_METHODID_GDSP
- ASUS_WMI_METHODID_GLCD
- ASUS_WMI_METHODID_GPID
- ASUS_WMI_METHODID_HKEY
- ASUS_WMI_METHODID_INIT
- ASUS_WMI_METHODID_KBFT
- ASUS_WMI_METHODID_OSVR
- ASUS_WMI_METHODID_QMOD
- ASUS_WMI_METHODID_SDSP
- ASUS_WMI_METHODID_SFBD
- ASUS_WMI_METHODID_SFUN
- ASUS_WMI_METHODID_SPEC
- ASUS_WMI_METHODID_SPLV
- ASUS_WMI_MGMT_GUID
- ASUS_WMI_UNSUPPORTED_METHOD
- ASV_LENGTH
- ASYM_ACCESS_CHANGED
- ASYNC
- ASYNCB_AUTOPROBE
- ASYNCB_AUTO_IRQ
- ASYNCB_BOOT_AUTOCONF
- ASYNCB_BUGGY_UART
- ASYNCB_CALLOUT_NOHUP
- ASYNCB_CHECK_CD
- ASYNCB_CLOSING
- ASYNCB_CONS_FLOW
- ASYNCB_CTS_FLOW
- ASYNCB_FIRST_KERNEL
- ASYNCB_FOURPORT
- ASYNCB_HARDPPS_CD
- ASYNCB_HUP_NOTIFY
- ASYNCB_INITIALIZED
- ASYNCB_LAST_USER
- ASYNCB_LOW_LATENCY
- ASYNCB_MAGIC_MULTIPLIER
- ASYNCB_NORMAL_ACTIVE
- ASYNCB_PGRP_LOCKOUT
- ASYNCB_SAK
- ASYNCB_SESSION_LOCKOUT
- ASYNCB_SHARE_IRQ
- ASYNCB_SKIP_TEST
- ASYNCB_SPD_HI
- ASYNCB_SPD_SHI
- ASYNCB_SPD_VHI
- ASYNCB_SPLIT_TERMIOS
- ASYNCB_SUSPENDED
- ASYNCEVT_ENABLE_VAR
- ASYNCHRONOUS_RESET
- ASYNCINDEX
- ASYNCRX_SCB_ADDR
- ASYNCSTAT_FIELDS
- ASYNCTX_SCB_ADDR
- ASYNC_ADDR_HI
- ASYNC_ADDR_LO
- ASYNC_AUTOPROBE
- ASYNC_AUTO_IRQ
- ASYNC_BID_TO_HAN
- ASYNC_BOOT_AUTOCONF
- ASYNC_BUGGY_UART
- ASYNC_CALLOUT_NOHUP
- ASYNC_CHECK_CD
- ASYNC_CLOSING
- ASYNC_CLOSING_WAIT_INF
- ASYNC_CLOSING_WAIT_NONE
- ASYNC_CONN_FLUSH_WORK
- ASYNC_CONN_IDLE
- ASYNC_CONN_INPROGRESS
- ASYNC_CONS_FLOW
- ASYNC_COOKIE_MAX
- ASYNC_CTS_FLOW
- ASYNC_DEBUG_EVENT_TYPE_QNQ
- ASYNC_DEPRECATED
- ASYNC_DIV_1_0
- ASYNC_DIV_1_5
- ASYNC_DIV_2_0
- ASYNC_DIV_3_0
- ASYNC_DOMAIN
- ASYNC_DOMAIN_EXCLUSIVE
- ASYNC_DRV_NAMES_MAX_LEN
- ASYNC_EVENT
- ASYNC_EVENTS_PENDING
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT
- ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT
- ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT
- ASYNC_EVENT_CMPL_ERROR_RECOVERY_V
- ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION
- ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE
- ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ
- ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE
- ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY
- ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD
- ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD
- ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT
- ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG
- ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
- ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED
- ASYNC_EVENT_CMPL_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
- ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD
- ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
- ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
- ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
- ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
- ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR
- ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT
- ASYNC_EVENT_CMPL_HW_FLOW_AGED_V
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT
- ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT
- ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V
- ASYNC_EVENT_CMPL_OPAQUE_MASK
- ASYNC_EVENT_CMPL_OPAQUE_SFT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT
- ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
- ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK
- ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST
- ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK
- ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT
- ASYNC_EVENT_CMPL_RESET_NOTIFY_V
- ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_TYPE_LAST
- ASYNC_EVENT_CMPL_TYPE_MASK
- ASYNC_EVENT_CMPL_TYPE_SFT
- ASYNC_EVENT_CMPL_V
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT
- ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V
- ASYNC_EVENT_CODE_GRP_5
- ASYNC_EVENT_CODE_ISCSI
- ASYNC_EVENT_CODE_LINK_STATE
- ASYNC_EVENT_CODE_MASK
- ASYNC_EVENT_CODE_QNQ
- ASYNC_EVENT_CODE_SHIFT
- ASYNC_EVENT_CODE_SLI
- ASYNC_EVENT_CODE_SLIPORT
- ASYNC_EVENT_COS_PRIORITY
- ASYNC_EVENT_FW_CONTROL
- ASYNC_EVENT_LINK_DOWN
- ASYNC_EVENT_LINK_UP
- ASYNC_EVENT_NEW_ISCSI_CONN
- ASYNC_EVENT_NEW_ISCSI_TGT_DISC
- ASYNC_EVENT_NEW_TCP_CONN
- ASYNC_EVENT_PORT_MISCONFIG
- ASYNC_EVENT_PVID_STATE
- ASYNC_EVENT_QOS_SPEED
- ASYNC_EVENT_SOURCES
- ASYNC_EVENT_TYPE_MASK
- ASYNC_EVENT_TYPE_SHIFT
- ASYNC_FLAGS
- ASYNC_FLAGS_MISALIGNED
- ASYNC_FLIP
- ASYNC_FLIP_PERF_DISABLE
- ASYNC_FOURPORT
- ASYNC_HAN_TO_BID
- ASYNC_HAN_TO_BS
- ASYNC_HARDPPS_CD
- ASYNC_HUP_NOTIFY
- ASYNC_INITIALIZED
- ASYNC_INTERNAL_FLAGS
- ASYNC_IP_OUTPUT_BUFFER1
- ASYNC_LOW_LATENCY
- ASYNC_MAGIC_MULTIPLIER
- ASYNC_MODE
- ASYNC_MSG_FIFO_SIZE
- ASYNC_NORMAL_ACTIVE
- ASYNC_NOTIF_RSPQ
- ASYNC_OFFSET
- ASYNC_OPERATION
- ASYNC_PARAMS
- ASYNC_PARITY_EVEN
- ASYNC_PARITY_NONE
- ASYNC_PARITY_ODD
- ASYNC_PARITY_SPACE
- ASYNC_PF_PER_VCPU
- ASYNC_PGRP_LOCKOUT
- ASYNC_SAK
- ASYNC_SCATTERLIST_CACHE
- ASYNC_SCSI_BUS_RESET
- ASYNC_SESSION_LOCKOUT
- ASYNC_SHARE_IRQ
- ASYNC_SKIP_TEST
- ASYNC_SLI_EVENT_TYPE_MISCONFIGURED
- ASYNC_SLI_LINK_EFFECT_SEV
- ASYNC_SLI_LINK_EFFECT_STATE
- ASYNC_SLI_LINK_EFFECT_VALID
- ASYNC_SPD_CUST
- ASYNC_SPD_HI
- ASYNC_SPD_MASK
- ASYNC_SPD_SHI
- ASYNC_SPD_VHI
- ASYNC_SPD_WARP
- ASYNC_SPLIT_TERMIOS
- ASYNC_STATUS_CN
- ASYNC_SUSPENDED
- ASYNC_TEMP_SAFE
- ASYNC_TEMP_WARN
- ASYNC_TEST_OUT_BCK_MASK
- ASYNC_TEST_OUT_BCK_MASK_SFT
- ASYNC_TEST_OUT_BCK_SFT
- ASYNC_TOKEN_ABANDONED
- ASYNC_TOKEN_ALLOCATED
- ASYNC_TOKEN_COMPLETED
- ASYNC_TOKEN_DISPATCHED
- ASYNC_TOKEN_UNALLOCATED
- ASYNC_TRAILER_EVENT_CODE_MASK
- ASYNC_TRAILER_EVENT_CODE_SHIFT
- ASYNC_TRAILER_EVENT_TYPE_MASK
- ASYNC_TRAILER_EVENT_TYPE_SHIFT
- ASYNC_TX_ACK
- ASYNC_TX_CHANNEL_SWITCH
- ASYNC_TX_DIRECT_SUBMIT
- ASYNC_TX_FENCE
- ASYNC_TX_PQ_XOR_DST
- ASYNC_TX_SUBMITTED
- ASYNC_TX_XOR_DROP_DST
- ASYNC_TX_XOR_ZERO_DST
- ASYNC_USR_MASK
- ASYN_INT_MODE
- ASYN_SDTR_DATA_FIX_PCI_REV_AB
- ASYS_I2SIN1_CON
- ASYS_I2SIN2_CON
- ASYS_I2SIN3_CON
- ASYS_I2SIN4_CON
- ASYS_I2SIN5_CON
- ASYS_I2SO1_CON
- ASYS_I2SO2_CON
- ASYS_I2SO3_CON
- ASYS_I2SO4_CON
- ASYS_I2SO5_CON
- ASYS_I2S_CON_FS
- ASYS_I2S_CON_FS_SET
- ASYS_I2S_CON_I2S_COUPLE_MODE
- ASYS_I2S_CON_I2S_EN
- ASYS_I2S_CON_I2S_MODE
- ASYS_I2S_CON_ONE_HEART_MODE
- ASYS_I2S_CON_RESET
- ASYS_I2S_CON_WIDE_MODE
- ASYS_I2S_CON_WIDE_MODE_SET
- ASYS_I2S_IN_PHASE_FIX
- ASYS_IRQ1_CON
- ASYS_IRQ2_CON
- ASYS_IRQ3_CON
- ASYS_IRQ_CLR
- ASYS_IRQ_STATUS
- ASYS_TOP_CON
- ASYS_TOP_CON_ASYS_TIMING_ON
- AS_BOOST_CURRENT_DISABLE
- AS_BOOST_CURRENT_ENABLE
- AS_BOOST_REG
- AS_COMMAND
- AS_COMMAND_FLUSH
- AS_COMMAND_FLUSH_MEM
- AS_COMMAND_FLUSH_PT
- AS_COMMAND_LOCK
- AS_COMMAND_NOP
- AS_COMMAND_UNLOCK
- AS_COMMAND_UPDATE
- AS_CONTINUATION
- AS_CONTROL_COIL_PEAK_SHIFT
- AS_CONTROL_EXT_TORCH_ON
- AS_CONTROL_MODE_SETTING_SHIFT
- AS_CONTROL_OUT_ON
- AS_CONTROL_REG
- AS_CONTROL_STROBE_ON
- AS_CONTROL_STROBE_TYPE_EDGE
- AS_CONTROL_STROBE_TYPE_LEVEL
- AS_CURRENT_ASSIST_LIGHT_SHIFT
- AS_CURRENT_FLASH_CURRENT_SHIFT
- AS_CURRENT_LED_DET_ON
- AS_CURRENT_SET_REG
- AS_DESIGN_INFO_FACTORY
- AS_DESIGN_INFO_MODEL
- AS_DESIGN_INFO_REG
- AS_DONE
- AS_EIO
- AS_ENOSPC
- AS_EXITING
- AS_FAULTADDRESS_HI
- AS_FAULTADDRESS_LO
- AS_FAULTEXTRA_HI
- AS_FAULTEXTRA_LO
- AS_FAULTSTATUS
- AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC
- AS_FAULTSTATUS_ACCESS_TYPE_EX
- AS_FAULTSTATUS_ACCESS_TYPE_MASK
- AS_FAULTSTATUS_ACCESS_TYPE_READ
- AS_FAULTSTATUS_ACCESS_TYPE_WRITE
- AS_FAULT_INFO_INDICATOR_LED
- AS_FAULT_INFO_INDUCTOR_PEAK_LIMIT
- AS_FAULT_INFO_LED_AMOUNT
- AS_FAULT_INFO_OVER_TEMPERATURE
- AS_FAULT_INFO_OVER_VOLTAGE
- AS_FAULT_INFO_REG
- AS_FAULT_INFO_SHORT_CIRCUIT
- AS_FAULT_INFO_TIMEOUT
- AS_FLASH_INTENSITY_MAX_1LED
- AS_FLASH_INTENSITY_MAX_2LEDS
- AS_FLASH_INTENSITY_MIN
- AS_FLASH_INTENSITY_STEP
- AS_FLASH_TIMEOUT_MAX
- AS_FLASH_TIMEOUT_MIN
- AS_FLASH_TIMEOUT_STEP
- AS_Host
- AS_I2C_ADDR
- AS_INDICATOR_AND_TIMER_INDICATOR_SHIFT
- AS_INDICATOR_AND_TIMER_REG
- AS_INDICATOR_AND_TIMER_TIMEOUT_SHIFT
- AS_INDICATOR_AND_TIMER_VREF_SHIFT
- AS_INDICATOR_INTENSITY_MAX
- AS_INDICATOR_INTENSITY_MIN
- AS_INDICATOR_INTENSITY_STEP
- AS_LED_FLASH
- AS_LED_INDICATOR
- AS_LOCKADDR_HI
- AS_LOCKADDR_LO
- AS_MEMATTR_HI
- AS_MEMATTR_LO
- AS_MM_ALL_LOCKS
- AS_MODE_ASSIST
- AS_MODE_EXT_TORCH
- AS_MODE_FLASH
- AS_MODE_INDICATOR
- AS_NAME
- AS_NO_WRITEBACK_TAGS
- AS_PASSWORD_REG
- AS_PASSWORD_UNLOCK_VALUE
- AS_PEAK_mA_MAX
- AS_PEAK_mA_TO_REG
- AS_PUSH_SHIFT
- AS_SEARCHING_FFT
- AS_SEARCHING_GUARD
- AS_SIGNAL_TYPE_DISPLAY_PORT
- AS_SIGNAL_TYPE_DVI
- AS_SIGNAL_TYPE_GPU_PLL
- AS_SIGNAL_TYPE_HDMI
- AS_SIGNAL_TYPE_LVDS
- AS_SIGNAL_TYPE_NONE
- AS_SIGNAL_TYPE_UNKNOWN
- AS_SIGNAL_TYPE_XGMI
- AS_START
- AS_STATUS
- AS_STATUS_AS_ACTIVE
- AS_TIMER_CODE_TO_US
- AS_TIMER_US_TO_CODE
- AS_TORCH_INTENSITY_MAX
- AS_TORCH_INTENSITY_MIN
- AS_TORCH_INTENSITY_STEP
- AS_TRANSCFG_HI
- AS_TRANSCFG_LO
- AS_TRANSTAB_HI
- AS_TRANSTAB_LO
- AS_TRANSTAB_LPAE_ADDR_SPACE_MASK
- AS_TRANSTAB_LPAE_ADRMODE_IDENTITY
- AS_TRANSTAB_LPAE_ADRMODE_MASK
- AS_TRANSTAB_LPAE_ADRMODE_TABLE
- AS_TRANSTAB_LPAE_READ_INNER
- AS_TRANSTAB_LPAE_SHARE_OUTER
- AS_UNEVICTABLE
- AS_UNLINK
- AS_VERSION_CONTROL_REG
- AS_VERSION_CONTROL_RFU
- AS_VERSION_CONTROL_VERSION
- AT
- AT1_MASK
- AT24_CHIP_DATA
- AT24_FLAG_ADDR16
- AT24_FLAG_IRUGO
- AT24_FLAG_MAC
- AT24_FLAG_NO_RDROL
- AT24_FLAG_READONLY
- AT24_FLAG_SERIAL
- AT24_FLAG_TAKE8ADDR
- AT250X0_PAGE_SIZE
- AT25_INSTR_BIT3
- AT25_RDSR
- AT25_READ
- AT25_SR_BP0
- AT25_SR_BP1
- AT25_SR_WEN
- AT25_SR_WPEN
- AT25_SR_nRDY
- AT25_WRDI
- AT25_WREN
- AT25_WRITE
- AT25_WRSR
- AT29LV512
- AT2_MASK
- AT30TS00_DEVID
- AT30TS00_DEVID_MASK
- AT30TSE004_DEVID
- AT30TSE004_DEVID_MASK
- AT49BV16X
- AT49BV16XT
- AT49BV32X
- AT49BV32XT
- AT49BV512
- AT49BV640D
- AT49BV640DT
- AT49BV6416
- AT73C213_MONO_SWITCH
- AT73C213_PM_OPS
- AT73C213_STEREO
- AT76_PM_OFF
- AT76_PM_ON
- AT76_PM_SMART
- AT76_RX_HDRLEN
- AT76_SUPPORTED_FILTERS
- AT76_TX_HDRLEN
- AT803X_BT_BX_REG_SEL
- AT803X_DEBUG_ADDR
- AT803X_DEBUG_DATA
- AT803X_DEBUG_REG_0
- AT803X_DEBUG_REG_5
- AT803X_DEBUG_RX_CLK_DLY_EN
- AT803X_DEBUG_TX_CLK_DLY_EN
- AT803X_DEVICE_ADDR
- AT803X_INTR_ENABLE
- AT803X_INTR_ENABLE_AUTONEG_ERR
- AT803X_INTR_ENABLE_DUPLEX_CHANGED
- AT803X_INTR_ENABLE_LINK_FAIL
- AT803X_INTR_ENABLE_LINK_SUCCESS
- AT803X_INTR_ENABLE_PAGE_RECEIVED
- AT803X_INTR_ENABLE_POLARITY_CHANGED
- AT803X_INTR_ENABLE_SPEED_CHANGED
- AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE
- AT803X_INTR_ENABLE_WOL
- AT803X_INTR_STATUS
- AT803X_LED_CONTROL
- AT803X_LOC_MAC_ADDR_0_15_OFFSET
- AT803X_LOC_MAC_ADDR_16_31_OFFSET
- AT803X_LOC_MAC_ADDR_32_47_OFFSET
- AT803X_MODE_CFG_MASK
- AT803X_MODE_CFG_SGMII
- AT803X_PHY_ID_MASK
- AT803X_PSSR
- AT803X_PSSR_MR_AN_COMPLETE
- AT803X_REG_CHIP_CONFIG
- AT803X_SMART_SPEED
- AT803X_SPECIFIC_STATUS
- AT803X_SS_DUPLEX
- AT803X_SS_MDIX
- AT803X_SS_SPEED_10
- AT803X_SS_SPEED_100
- AT803X_SS_SPEED_1000
- AT803X_SS_SPEED_DUPLEX_RESOLVED
- AT803X_SS_SPEED_MASK
- AT86RF212_MAX_TX_POWERS
- AT86RF230_H
- AT86RF23X_MAX_TX_POWERS
- AT86RF2XX_CAL_LOOP_TIMEOUT
- AT86RF2XX_MAX_BUF
- AT86RF2XX_MAX_ED_LEVELS
- AT86RF2XX_MAX_TX_RETRIES
- AT86RF2XX_NUMREGS
- AT91ETHER_MAX_RBUFF_SZ
- AT91ETHER_MAX_RX_DESCR
- AT91RL_ADC_IER_NOPEN
- AT91RL_ADC_IER_PEN
- AT91RM9200_CIDR_MATCH
- AT91RM9200_PMC_MCKUDP
- AT91RM9200_PMC_MDIV_1
- AT91RM9200_PMC_MDIV_2
- AT91RM9200_PMC_MDIV_3
- AT91RM9200_PMC_MDIV_4
- AT91RM9200_PMC_UDP
- AT91RM9200_PMC_UHP
- AT91SAM9260_CIDR_MATCH
- AT91SAM9260_MATRIX_EBICSA
- AT91SAM9260_MATRIX_MCFG
- AT91SAM9260_MATRIX_MRCR
- AT91SAM9260_MATRIX_PRS
- AT91SAM9260_MATRIX_SCFG
- AT91SAM9261_CIDR_MATCH
- AT91SAM9261_MATRIX_EBICSA
- AT91SAM9261_MATRIX_MRCR
- AT91SAM9261_MATRIX_SCFG
- AT91SAM9261_MATRIX_TCR
- AT91SAM9261_MATRIX_USBPUCR
- AT91SAM9263_CIDR_MATCH
- AT91SAM9263_MATRIX_EBI0CSA
- AT91SAM9263_MATRIX_EBI1CSA
- AT91SAM9263_MATRIX_MCFG
- AT91SAM9263_MATRIX_MRCR
- AT91SAM9263_MATRIX_PRS
- AT91SAM9263_MATRIX_SCFG
- AT91SAM9263_MATRIX_TCR
- AT91SAM926x_PMC_UDP
- AT91SAM926x_PMC_UHP
- AT91SAM9CN11_EXID_MATCH
- AT91SAM9CN12_EXID_MATCH
- AT91SAM9G15_EXID_MATCH
- AT91SAM9G20_CIDR_MATCH
- AT91SAM9G25_EXID_MATCH
- AT91SAM9G35_EXID_MATCH
- AT91SAM9G45_CIDR_MATCH
- AT91SAM9G45_EXID_MATCH
- AT91SAM9G45_MATRIX_DDRMPR
- AT91SAM9G45_MATRIX_EBICSA
- AT91SAM9G45_MATRIX_MCFG
- AT91SAM9G45_MATRIX_MRCR
- AT91SAM9G45_MATRIX_PRS
- AT91SAM9G45_MATRIX_SCFG
- AT91SAM9G45_MATRIX_TCR
- AT91SAM9G46_EXID_MATCH
- AT91SAM9M10_EXID_MATCH
- AT91SAM9M11_EXID_MATCH
- AT91SAM9N12_CIDR_MATCH
- AT91SAM9N12_EXID_MATCH
- AT91SAM9N12_MATRIX_EBICSA
- AT91SAM9N12_MATRIX_MCFG
- AT91SAM9N12_MATRIX_MRCR
- AT91SAM9N12_MATRIX_PRS
- AT91SAM9N12_MATRIX_SCFG
- AT91SAM9RL64_CIDR_MATCH
- AT91SAM9RL_MATRIX_EBICSA
- AT91SAM9RL_MATRIX_MCFG
- AT91SAM9RL_MATRIX_MRCR
- AT91SAM9RL_MATRIX_PRS
- AT91SAM9RL_MATRIX_SCFG
- AT91SAM9RL_MATRIX_TCR
- AT91SAM9X25_EXID_MATCH
- AT91SAM9X35_EXID_MATCH
- AT91SAM9X5_CIDR_MATCH
- AT91SAM9X5_MATRIX_EBICSA
- AT91SAM9X5_MATRIX_MCFG
- AT91SAM9X5_MATRIX_MRCR
- AT91SAM9X5_MATRIX_PRS
- AT91SAM9X5_MATRIX_SCFG
- AT91SAM9X5_PIO_DRIVER1
- AT91SAM9X5_PIO_DRIVER2
- AT91SAM9XE128_CIDR_MATCH
- AT91SAM9XE256_CIDR_MATCH
- AT91SAM9XE512_CIDR_MATCH
- AT91SAM9_DDRSDR_H
- AT91SAM9_PMC_MDIV_1
- AT91SAM9_PMC_MDIV_2
- AT91SAM9_PMC_MDIV_3
- AT91SAM9_PMC_MDIV_4
- AT91SAM9_PMC_MDIV_6
- AT91SAM9_SDRAMC_H
- AT91_ACR
- AT91_ADC_ACR
- AT91_ADC_ACR_PENDETSENS
- AT91_ADC_CDR0_9X5
- AT91_ADC_CH
- AT91_ADC_CHAN
- AT91_ADC_CHDR
- AT91_ADC_CHER
- AT91_ADC_CHR
- AT91_ADC_CHSR
- AT91_ADC_CR
- AT91_ADC_DATA
- AT91_ADC_DRDY
- AT91_ADC_ENDRX
- AT91_ADC_EOC
- AT91_ADC_GOVRE
- AT91_ADC_IDR
- AT91_ADC_IER
- AT91_ADC_IER_NOPEN
- AT91_ADC_IER_PEN
- AT91_ADC_IER_PRDY
- AT91_ADC_IER_XRDY
- AT91_ADC_IER_YRDY
- AT91_ADC_IMR
- AT91_ADC_ISR_PENS
- AT91_ADC_LCDR
- AT91_ADC_LDATA
- AT91_ADC_LOWRES
- AT91_ADC_MR
- AT91_ADC_OVRE
- AT91_ADC_PENDBC
- AT91_ADC_PENDBC_
- AT91_ADC_PENDET
- AT91_ADC_PRESCAL_
- AT91_ADC_PRESCAL_9260
- AT91_ADC_PRESCAL_9G45
- AT91_ADC_RXFUFF
- AT91_ADC_SHTIM
- AT91_ADC_SHTIM_
- AT91_ADC_SLEEP
- AT91_ADC_SR
- AT91_ADC_SR_9X5
- AT91_ADC_SR_DRDY_9X5
- AT91_ADC_START
- AT91_ADC_STARTUP_
- AT91_ADC_STARTUP_9260
- AT91_ADC_STARTUP_9G45
- AT91_ADC_STARTUP_9X5
- AT91_ADC_SWRST
- AT91_ADC_TRGEN
- AT91_ADC_TRGR_9260
- AT91_ADC_TRGR_9G45
- AT91_ADC_TRGR_9X5
- AT91_ADC_TRGR_MOD_PERIOD_TRIG
- AT91_ADC_TRGR_NONE
- AT91_ADC_TRGR_TRGMOD
- AT91_ADC_TRGR_TRGPER
- AT91_ADC_TRGR_TRGPER_
- AT91_ADC_TRGSEL
- AT91_ADC_TRGSEL_EXTERNAL
- AT91_ADC_TRGSEL_TC0
- AT91_ADC_TRGSEL_TC1
- AT91_ADC_TRGSEL_TC2
- AT91_ADC_TSAMOD
- AT91_ADC_TSAMOD_ADC_ONLY_MODE
- AT91_ADC_TSAMOD_TS_ONLY_MODE
- AT91_ADC_TSMR
- AT91_ADC_TSMR_NOTSDMA
- AT91_ADC_TSMR_PENDBC
- AT91_ADC_TSMR_PENDBC_
- AT91_ADC_TSMR_PENDET_DIS
- AT91_ADC_TSMR_PENDET_ENA
- AT91_ADC_TSMR_SCTIM
- AT91_ADC_TSMR_SCTIM_
- AT91_ADC_TSMR_TSAV
- AT91_ADC_TSMR_TSAV_
- AT91_ADC_TSMR_TSMODE
- AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS
- AT91_ADC_TSMR_TSMODE_4WIRE_PRESS
- AT91_ADC_TSMR_TSMODE_5WIRE
- AT91_ADC_TSMR_TSMODE_NONE
- AT91_ADC_TSPRESSR
- AT91_ADC_TSR
- AT91_ADC_TSR_SHTIM
- AT91_ADC_TSR_SHTIM_
- AT91_ADC_TSXPOSR
- AT91_ADC_TSYPOSR
- AT91_AIC5_CISR
- AT91_AIC5_DCR
- AT91_AIC5_EOICR
- AT91_AIC5_FFDR
- AT91_AIC5_FFER
- AT91_AIC5_FFSR
- AT91_AIC5_FVR
- AT91_AIC5_ICCR
- AT91_AIC5_IDCR
- AT91_AIC5_IECR
- AT91_AIC5_IMR
- AT91_AIC5_INTSEL_MSK
- AT91_AIC5_IPR0
- AT91_AIC5_IPR1
- AT91_AIC5_IPR2
- AT91_AIC5_IPR3
- AT91_AIC5_ISCR
- AT91_AIC5_ISR
- AT91_AIC5_IVR
- AT91_AIC5_SMR
- AT91_AIC5_SPU
- AT91_AIC5_SSR
- AT91_AIC5_SVR
- AT91_AIC_CISR
- AT91_AIC_DCR
- AT91_AIC_EOICR
- AT91_AIC_FVR
- AT91_AIC_ICCR
- AT91_AIC_IDCR
- AT91_AIC_IECR
- AT91_AIC_IMR
- AT91_AIC_IPR
- AT91_AIC_IRQ_MAX_PRIORITY
- AT91_AIC_IRQ_MIN_PRIORITY
- AT91_AIC_ISCR
- AT91_AIC_ISR
- AT91_AIC_IVR
- AT91_AIC_PRIOR
- AT91_AIC_SMR
- AT91_AIC_SPU
- AT91_AIC_SRCTYPE
- AT91_AIC_SRCTYPE_FALLING
- AT91_AIC_SRCTYPE_HIGH
- AT91_AIC_SRCTYPE_LOW
- AT91_AIC_SRCTYPE_RISING
- AT91_AIC_SVR
- AT91_BR
- AT91_BUFFER_MAX_BYTES
- AT91_BUFFER_MAX_CONVERSION_BYTES
- AT91_BUFFER_MAX_HWORDS
- AT91_CF_TRUE_IDE
- AT91_CHIPID_CIDR
- AT91_CHIPID_EXID
- AT91_CIDR_EXT
- AT91_CIDR_MATCH_MASK
- AT91_CIDR_VERSION
- AT91_CKGR_MCFR
- AT91_CKGR_MOR
- AT91_CKGR_PLLAR
- AT91_CKGR_PLLBR
- AT91_CKGR_UCKR
- AT91_DBGU_CIDR
- AT91_DBGU_EXID
- AT91_DBGU_SR
- AT91_DBGU_THR
- AT91_DBGU_TXEMPTY
- AT91_DBGU_TXRDY
- AT91_DDRSDRC_ACTBST
- AT91_DDRSDRC_APDE
- AT91_DDRSDRC_CAS
- AT91_DDRSDRC_CAS_2
- AT91_DDRSDRC_CAS_25
- AT91_DDRSDRC_CAS_3
- AT91_DDRSDRC_CLKFR
- AT91_DDRSDRC_COUNT
- AT91_DDRSDRC_CR
- AT91_DDRSDRC_DBW
- AT91_DDRSDRC_DBW_16BITS
- AT91_DDRSDRC_DBW_32BITS
- AT91_DDRSDRC_DELAY
- AT91_DDRSDRC_DICDS
- AT91_DDRSDRC_DIS_ATCP_RD
- AT91_DDRSDRC_DIS_DLL
- AT91_DDRSDRC_DLL
- AT91_DDRSDRC_DQMS
- AT91_DDRSDRC_DS
- AT91_DDRSDRC_HS
- AT91_DDRSDRC_KEY
- AT91_DDRSDRC_LPCB
- AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN
- AT91_DDRSDRC_LPCB_DISABLE
- AT91_DDRSDRC_LPCB_POWER_DOWN
- AT91_DDRSDRC_LPCB_SELF_REFRESH
- AT91_DDRSDRC_LPDDR2_PWOFF
- AT91_DDRSDRC_LPR
- AT91_DDRSDRC_MD
- AT91_DDRSDRC_MDDEC
- AT91_DDRSDRC_MDINC
- AT91_DDRSDRC_MDOVF
- AT91_DDRSDRC_MDR
- AT91_DDRSDRC_MDVAL
- AT91_DDRSDRC_MD_DDR2
- AT91_DDRSDRC_MD_LOW_POWER_DDR
- AT91_DDRSDRC_MD_LOW_POWER_SDR
- AT91_DDRSDRC_MD_LPDDR2
- AT91_DDRSDRC_MD_LPDDR3
- AT91_DDRSDRC_MD_SDR
- AT91_DDRSDRC_MODE
- AT91_DDRSDRC_MODE_DEEP
- AT91_DDRSDRC_MODE_EXT_LMR
- AT91_DDRSDRC_MODE_LMR
- AT91_DDRSDRC_MODE_NOP
- AT91_DDRSDRC_MODE_NORMAL
- AT91_DDRSDRC_MODE_PRECHARGE
- AT91_DDRSDRC_MODE_REFRESH
- AT91_DDRSDRC_MR
- AT91_DDRSDRC_NC
- AT91_DDRSDRC_NC_DDR10
- AT91_DDRSDRC_NC_DDR11
- AT91_DDRSDRC_NC_DDR12
- AT91_DDRSDRC_NC_DDR9
- AT91_DDRSDRC_NC_SDR10
- AT91_DDRSDRC_NC_SDR11
- AT91_DDRSDRC_NC_SDR8
- AT91_DDRSDRC_NC_SDR9
- AT91_DDRSDRC_NR
- AT91_DDRSDRC_NR_11
- AT91_DDRSDRC_NR_12
- AT91_DDRSDRC_NR_13
- AT91_DDRSDRC_NR_14
- AT91_DDRSDRC_OCD
- AT91_DDRSDRC_PASR
- AT91_DDRSDRC_RED_WRRD
- AT91_DDRSDRC_RST_DLL
- AT91_DDRSDRC_RTR
- AT91_DDRSDRC_T0PR
- AT91_DDRSDRC_T1PR
- AT91_DDRSDRC_T2PR
- AT91_DDRSDRC_TCSR
- AT91_DDRSDRC_TIMEOUT
- AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES
- AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES
- AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES
- AT91_DDRSDRC_TMRD
- AT91_DDRSDRC_TRAS
- AT91_DDRSDRC_TRC
- AT91_DDRSDRC_TRCD
- AT91_DDRSDRC_TRFC
- AT91_DDRSDRC_TRP
- AT91_DDRSDRC_TRPA
- AT91_DDRSDRC_TRRD
- AT91_DDRSDRC_TRTP
- AT91_DDRSDRC_TWR
- AT91_DDRSDRC_TWTR
- AT91_DDRSDRC_TXARD
- AT91_DDRSDRC_TXARDS
- AT91_DDRSDRC_TXP
- AT91_DDRSDRC_TXSNR
- AT91_DDRSDRC_TXSRD
- AT91_DDRSDRC_UPD_MR
- AT91_DDRSDRC_WP
- AT91_DDRSDRC_WPKEY
- AT91_DDRSDRC_WPMR
- AT91_DDRSDRC_WPSR
- AT91_DDRSDRC_WPVS
- AT91_DDRSDRC_WPVSRC
- AT91_DEVTYPE_SAM9263
- AT91_DEVTYPE_SAM9X5
- AT91_DMA_CFG_FIFOCFG_ALAP
- AT91_DMA_CFG_FIFOCFG_ASAP
- AT91_DMA_CFG_FIFOCFG_HALF
- AT91_DMA_CFG_FIFOCFG_MASK
- AT91_DMA_CFG_FIFOCFG_OFFSET
- AT91_DMA_CFG_PER_ID
- AT91_DMA_CFG_PER_ID_MASK
- AT91_ECR
- AT91_HWFIFO_MAX_SIZE
- AT91_HWFIFO_MAX_SIZE_STR
- AT91_I2C_DMA_THRESHOLD
- AT91_I2C_MAX_ALT_CMD_DATA_SIZE
- AT91_I2C_TIMEOUT
- AT91_IDE_SWAP_A0_A2
- AT91_IDR
- AT91_IER
- AT91_IMR
- AT91_IRQ_AERR
- AT91_IRQ_ALL
- AT91_IRQ_BERR
- AT91_IRQ_BOFF
- AT91_IRQ_CERR
- AT91_IRQ_ERRA
- AT91_IRQ_ERRP
- AT91_IRQ_ERR_ALL
- AT91_IRQ_ERR_FRAME
- AT91_IRQ_ERR_LINE
- AT91_IRQ_FERR
- AT91_IRQ_SERR
- AT91_IRQ_SLEEP
- AT91_IRQ_TOVF
- AT91_IRQ_TSTP
- AT91_IRQ_WAKEUP
- AT91_IRQ_WARN
- AT91_IS
- AT91_MAM
- AT91_MATRIX_ARBT
- AT91_MATRIX_ARBT_FIXED_PRIORITY
- AT91_MATRIX_ARBT_ROUND_ROBIN
- AT91_MATRIX_CSA
- AT91_MATRIX_DBPDC
- AT91_MATRIX_DBPUC
- AT91_MATRIX_DDR_IOSR
- AT91_MATRIX_DDR_MP_EN
- AT91_MATRIX_DEFMSTR_TYPE
- AT91_MATRIX_DEFMSTR_TYPE_FIXED
- AT91_MATRIX_DEFMSTR_TYPE_LAST
- AT91_MATRIX_DEFMSTR_TYPE_NONE
- AT91_MATRIX_DTCM_0
- AT91_MATRIX_DTCM_16
- AT91_MATRIX_DTCM_32
- AT91_MATRIX_DTCM_64
- AT91_MATRIX_DTCM_SIZE
- AT91_MATRIX_EBI_IOSR
- AT91_MATRIX_EBI_NUM_CS
- AT91_MATRIX_FIXED_DEFMSTR
- AT91_MATRIX_ITCM_0
- AT91_MATRIX_ITCM_16
- AT91_MATRIX_ITCM_32
- AT91_MATRIX_ITCM_64
- AT91_MATRIX_ITCM_SIZE
- AT91_MATRIX_MCFG
- AT91_MATRIX_MPR
- AT91_MATRIX_NFD0_SELECT
- AT91_MATRIX_PRAS
- AT91_MATRIX_PRBS
- AT91_MATRIX_RCB
- AT91_MATRIX_SCFG
- AT91_MATRIX_SLOT_CYCLE
- AT91_MATRIX_ULBT
- AT91_MATRIX_ULBT_EIGHT
- AT91_MATRIX_ULBT_FOUR
- AT91_MATRIX_ULBT_INFINITE
- AT91_MATRIX_ULBT_SINGLE
- AT91_MATRIX_ULBT_SIXTEEN
- AT91_MATRIX_USBPUCR_PUON
- AT91_MATRIX_VDDIOMSEL
- AT91_MATRIX_VDDIOMSEL_1_8V
- AT91_MATRIX_VDDIOMSEL_3_3V
- AT91_MAX_STATES
- AT91_MAX_USBH_PORTS
- AT91_MB_MASK
- AT91_MB_MODE_CONSUMER
- AT91_MB_MODE_DISABLED
- AT91_MB_MODE_PRODUCER
- AT91_MB_MODE_RX
- AT91_MB_MODE_RX_OVRWR
- AT91_MB_MODE_TX
- AT91_MCR
- AT91_MCR_MRTR
- AT91_MCR_MTCR
- AT91_MC_AASR
- AT91_MC_ABTSZ
- AT91_MC_ABTSZ_BYTE
- AT91_MC_ABTSZ_HALFWORD
- AT91_MC_ABTSZ_WORD
- AT91_MC_ABTTYP
- AT91_MC_ABTTYP_DATAREAD
- AT91_MC_ABTTYP_DATAWRITE
- AT91_MC_ABTTYP_FETCH
- AT91_MC_ASR
- AT91_MC_BFC_AVL
- AT91_MC_BFC_BAAEN
- AT91_MC_BFC_BFCC
- AT91_MC_BFC_BFCC_DIV2
- AT91_MC_BFC_BFCC_DIV4
- AT91_MC_BFC_BFCC_MCK
- AT91_MC_BFC_BFCOM
- AT91_MC_BFC_BFCOM_ASYNC
- AT91_MC_BFC_BFCOM_BURST
- AT91_MC_BFC_BFCOM_DISABLED
- AT91_MC_BFC_BFOEH
- AT91_MC_BFC_MR
- AT91_MC_BFC_MUXEN
- AT91_MC_BFC_OEL
- AT91_MC_BFC_PAGES
- AT91_MC_BFC_PAGES_1024
- AT91_MC_BFC_PAGES_128
- AT91_MC_BFC_PAGES_16
- AT91_MC_BFC_PAGES_256
- AT91_MC_BFC_PAGES_32
- AT91_MC_BFC_PAGES_512
- AT91_MC_BFC_PAGES_64
- AT91_MC_BFC_PAGES_NO_PAGE
- AT91_MC_BFC_RDYEN
- AT91_MC_EBI_CFGR
- AT91_MC_EBI_CS
- AT91_MC_EBI_CSA
- AT91_MC_EBI_DBPUC
- AT91_MC_EBI_NUM_CS
- AT91_MC_MISADD
- AT91_MC_MPR
- AT91_MC_MST
- AT91_MC_RCB
- AT91_MC_RCR
- AT91_MC_SDRAMC_CAS
- AT91_MC_SDRAMC_CAS_2
- AT91_MC_SDRAMC_COUNT
- AT91_MC_SDRAMC_CR
- AT91_MC_SDRAMC_DBW_16
- AT91_MC_SDRAMC_IDR
- AT91_MC_SDRAMC_IER
- AT91_MC_SDRAMC_IMR
- AT91_MC_SDRAMC_ISR
- AT91_MC_SDRAMC_LPCB
- AT91_MC_SDRAMC_LPR
- AT91_MC_SDRAMC_MODE
- AT91_MC_SDRAMC_MODE_LMR
- AT91_MC_SDRAMC_MODE_NOP
- AT91_MC_SDRAMC_MODE_NORMAL
- AT91_MC_SDRAMC_MODE_PRECHARGE
- AT91_MC_SDRAMC_MODE_REFRESH
- AT91_MC_SDRAMC_MR
- AT91_MC_SDRAMC_NB
- AT91_MC_SDRAMC_NB_2
- AT91_MC_SDRAMC_NB_4
- AT91_MC_SDRAMC_NC
- AT91_MC_SDRAMC_NC_10
- AT91_MC_SDRAMC_NC_11
- AT91_MC_SDRAMC_NC_8
- AT91_MC_SDRAMC_NC_9
- AT91_MC_SDRAMC_NR
- AT91_MC_SDRAMC_NR_11
- AT91_MC_SDRAMC_NR_12
- AT91_MC_SDRAMC_NR_13
- AT91_MC_SDRAMC_RES
- AT91_MC_SDRAMC_SRCB
- AT91_MC_SDRAMC_SRR
- AT91_MC_SDRAMC_TR
- AT91_MC_SDRAMC_TRAS
- AT91_MC_SDRAMC_TRC
- AT91_MC_SDRAMC_TRCD
- AT91_MC_SDRAMC_TRP
- AT91_MC_SDRAMC_TWR
- AT91_MC_SDRAMC_TXSR
- AT91_MC_SMC_ACSS
- AT91_MC_SMC_ACSS_
- AT91_MC_SMC_ACSS_MAX
- AT91_MC_SMC_BAT
- AT91_MC_SMC_CSR
- AT91_MC_SMC_DBW
- AT91_MC_SMC_DBW_16
- AT91_MC_SMC_DBW_8
- AT91_MC_SMC_DPR
- AT91_MC_SMC_NWS
- AT91_MC_SMC_NWS_
- AT91_MC_SMC_RWHOLD
- AT91_MC_SMC_RWHOLDSETUP_MAX
- AT91_MC_SMC_RWHOLD_
- AT91_MC_SMC_RWSETUP
- AT91_MC_SMC_RWSETUP_
- AT91_MC_SMC_TDF
- AT91_MC_SMC_TDF_
- AT91_MC_SMC_TDF_MAX
- AT91_MC_SMC_WSEN
- AT91_MC_SVMST
- AT91_MC_UNADD
- AT91_MDH
- AT91_MDL
- AT91_MEMCTRL_DDRSDR
- AT91_MEMCTRL_MC
- AT91_MEMCTRL_SDRAMC
- AT91_MFID
- AT91_MID
- AT91_MID_MIDE
- AT91_MMR
- AT91_MMR_PRIO_SHIFT
- AT91_MPR_MSTP
- AT91_MR
- AT91_MR_ABM
- AT91_MR_CANEN
- AT91_MR_DRPT
- AT91_MR_LPM
- AT91_MR_OVL
- AT91_MR_TEOF
- AT91_MR_TIMFRZ
- AT91_MR_TTM
- AT91_MSR
- AT91_MSR_MABT
- AT91_MSR_MMI
- AT91_MSR_MRDY
- AT91_MSR_MRTR
- AT91_MUX_GPIO
- AT91_MUX_PERIPH_A
- AT91_MUX_PERIPH_B
- AT91_MUX_PERIPH_C
- AT91_MUX_PERIPH_D
- AT91_OHCIICR_USB_SUSPEND
- AT91_OSR_16SAMPLES
- AT91_OSR_1SAMPLES
- AT91_OSR_4SAMPLES
- AT91_PERIPH_A
- AT91_PERIPH_B
- AT91_PERIPH_C
- AT91_PERIPH_D
- AT91_PERIPH_GPIO
- AT91_PINCTRL_DEBOUNCE
- AT91_PINCTRL_DEBOUNCE_VAL
- AT91_PINCTRL_DEGLITCH
- AT91_PINCTRL_DIS_SCHMIT
- AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT
- AT91_PINCTRL_DRIVE_STRENGTH_HI
- AT91_PINCTRL_DRIVE_STRENGTH_LOW
- AT91_PINCTRL_DRIVE_STRENGTH_MED
- AT91_PINCTRL_MULTI_DRIVE
- AT91_PINCTRL_NONE
- AT91_PINCTRL_OUTPUT
- AT91_PINCTRL_OUTPUT_VAL
- AT91_PINCTRL_PULL_DOWN
- AT91_PINCTRL_PULL_UP
- AT91_PINCTRL_PULL_UP_DEGLITCH
- AT91_PINCTRL_SLEWRATE
- AT91_PINCTRL_SLEWRATE_DIS
- AT91_PINCTRL_SLEWRATE_ENA
- AT91_PIOA
- AT91_PIOB
- AT91_PIOC
- AT91_PIOD
- AT91_PIOE
- AT91_PIT_CPIV
- AT91_PIT_MR
- AT91_PIT_PICNT
- AT91_PIT_PIIR
- AT91_PIT_PITEN
- AT91_PIT_PITIEN
- AT91_PIT_PITS
- AT91_PIT_PIV
- AT91_PIT_PIVR
- AT91_PIT_SR
- AT91_PMC3_MUL
- AT91_PMC3_MUL_GET
- AT91_PMC_ACC_CE
- AT91_PMC_ALT_PCKR_CSS
- AT91_PMC_ALT_PRES
- AT91_PMC_ALT_PRES_1
- AT91_PMC_ALT_PRES_16
- AT91_PMC_ALT_PRES_2
- AT91_PMC_ALT_PRES_32
- AT91_PMC_ALT_PRES_4
- AT91_PMC_ALT_PRES_64
- AT91_PMC_ALT_PRES_8
- AT91_PMC_AUDIO_PLL0
- AT91_PMC_AUDIO_PLL1
- AT91_PMC_AUDIO_PLL_FRACR_MASK
- AT91_PMC_AUDIO_PLL_ND
- AT91_PMC_AUDIO_PLL_ND_MASK
- AT91_PMC_AUDIO_PLL_ND_OFFSET
- AT91_PMC_AUDIO_PLL_PADEN
- AT91_PMC_AUDIO_PLL_PLLEN
- AT91_PMC_AUDIO_PLL_PMCEN
- AT91_PMC_AUDIO_PLL_QDPAD
- AT91_PMC_AUDIO_PLL_QDPAD_DIV
- AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK
- AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET
- AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV
- AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK
- AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX
- AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET
- AT91_PMC_AUDIO_PLL_QDPAD_MASK
- AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
- AT91_PMC_AUDIO_PLL_QDPMC
- AT91_PMC_AUDIO_PLL_QDPMC_MASK
- AT91_PMC_AUDIO_PLL_QDPMC_OFFSET
- AT91_PMC_AUDIO_PLL_RESETN
- AT91_PMC_BIASCOUNT
- AT91_PMC_BIASEN
- AT91_PMC_CFDEN
- AT91_PMC_CFDEV
- AT91_PMC_CPU_CKR
- AT91_PMC_CSS
- AT91_PMC_CSSMCK
- AT91_PMC_CSSMCK_CSS
- AT91_PMC_CSSMCK_MCK
- AT91_PMC_CSS_MAIN
- AT91_PMC_CSS_MASTER
- AT91_PMC_CSS_PLLA
- AT91_PMC_CSS_PLLB
- AT91_PMC_CSS_SLOW
- AT91_PMC_CSS_UPLL
- AT91_PMC_DIV
- AT91_PMC_FSMR
- AT91_PMC_FSPR
- AT91_PMC_FSTT
- AT91_PMC_FS_INPUT_MASK
- AT91_PMC_GCKRDY
- AT91_PMC_H
- AT91_PMC_H32MXDIV
- AT91_PMC_HCK0
- AT91_PMC_HCK1
- AT91_PMC_IDR
- AT91_PMC_IER
- AT91_PMC_IMR
- AT91_PMC_KEY
- AT91_PMC_KEY_MASK
- AT91_PMC_LOCKA
- AT91_PMC_LOCKB
- AT91_PMC_LOCKU
- AT91_PMC_LPM
- AT91_PMC_MAINF
- AT91_PMC_MAINRDY
- AT91_PMC_MCKR
- AT91_PMC_MCKRDY
- AT91_PMC_MDIV
- AT91_PMC_MOSCEN
- AT91_PMC_MOSCRCEN
- AT91_PMC_MOSCRCS
- AT91_PMC_MOSCS
- AT91_PMC_MOSCSEL
- AT91_PMC_MOSCSELS
- AT91_PMC_MUL
- AT91_PMC_MUL_GET
- AT91_PMC_OHCIUSBDIV
- AT91_PMC_OHCIUSBDIV_1
- AT91_PMC_OHCIUSBDIV_2
- AT91_PMC_OSCBYPASS
- AT91_PMC_OSCOUNT
- AT91_PMC_OSCSEL
- AT91_PMC_OUT
- AT91_PMC_PCDR
- AT91_PMC_PCDR1
- AT91_PMC_PCER
- AT91_PMC_PCER1
- AT91_PMC_PCK
- AT91_PMC_PCK0
- AT91_PMC_PCK0RDY
- AT91_PMC_PCK1
- AT91_PMC_PCK1RDY
- AT91_PMC_PCK2
- AT91_PMC_PCK2RDY
- AT91_PMC_PCK3
- AT91_PMC_PCK3RDY
- AT91_PMC_PCK4
- AT91_PMC_PCKR
- AT91_PMC_PCKRDY
- AT91_PMC_PCR
- AT91_PMC_PCR_CMD
- AT91_PMC_PCR_EN
- AT91_PMC_PCR_GCKDIV_MASK
- AT91_PMC_PCR_GCKEN
- AT91_PMC_PCR_PID_MASK
- AT91_PMC_PCSR
- AT91_PMC_PCSR1
- AT91_PMC_PDIV
- AT91_PMC_PDIV_1
- AT91_PMC_PDIV_2
- AT91_PMC_PLLADIV2
- AT91_PMC_PLLADIV2_OFF
- AT91_PMC_PLLADIV2_ON
- AT91_PMC_PLLCOUNT
- AT91_PMC_PLLICPR
- AT91_PMC_PRES
- AT91_PMC_PRES_1
- AT91_PMC_PRES_16
- AT91_PMC_PRES_2
- AT91_PMC_PRES_32
- AT91_PMC_PRES_4
- AT91_PMC_PRES_64
- AT91_PMC_PRES_8
- AT91_PMC_PROT
- AT91_PMC_PROTKEY
- AT91_PMC_RTCAL
- AT91_PMC_RTTAL
- AT91_PMC_RXLP_MCE
- AT91_PMC_SCDR
- AT91_PMC_SCER
- AT91_PMC_SCSR
- AT91_PMC_SDMMC_CD
- AT91_PMC_SMD
- AT91_PMC_SMDDIV
- AT91_PMC_SMDS
- AT91_PMC_SMD_DIV
- AT91_PMC_SR
- AT91_PMC_UPLLCOUNT
- AT91_PMC_UPLLEN
- AT91_PMC_USB
- AT91_PMC_USB96M
- AT91_PMC_USBAL
- AT91_PMC_USBDIV
- AT91_PMC_USBDIV_1
- AT91_PMC_USBDIV_2
- AT91_PMC_USBDIV_4
- AT91_PMC_USBS
- AT91_PMC_USBS_PLLA
- AT91_PMC_USBS_PLLB
- AT91_PMC_USBS_UPLL
- AT91_PMC_WAITMODE
- AT91_PMC_WPEN
- AT91_PMC_WPKEY
- AT91_PMC_WPSR
- AT91_PMC_WPVS
- AT91_PMC_WPVSRC
- AT91_PM_BACKUP
- AT91_PM_STANDBY
- AT91_PM_ULP0
- AT91_PM_ULP1
- AT91_RSTC_CR
- AT91_RSTC_ERSTL
- AT91_RSTC_EXTRST
- AT91_RSTC_KEY
- AT91_RSTC_MR
- AT91_RSTC_NRSTL
- AT91_RSTC_PERRST
- AT91_RSTC_PROCRST
- AT91_RSTC_RSTTYP
- AT91_RSTC_SR
- AT91_RSTC_SRCMP
- AT91_RSTC_URSTEN
- AT91_RSTC_URSTIEN
- AT91_RSTC_URSTS
- AT91_RTC_ACKUPD
- AT91_RTC_ALARM
- AT91_RTC_AMPM
- AT91_RTC_CALALR
- AT91_RTC_CALEV
- AT91_RTC_CALEVSEL
- AT91_RTC_CALEVSEL_MONTH
- AT91_RTC_CALEVSEL_WEEK
- AT91_RTC_CALEVSEL_YEAR
- AT91_RTC_CALR
- AT91_RTC_CENT
- AT91_RTC_CR
- AT91_RTC_DATE
- AT91_RTC_DATEEN
- AT91_RTC_DAY
- AT91_RTC_H
- AT91_RTC_HOUR
- AT91_RTC_HOUREN
- AT91_RTC_HRMOD
- AT91_RTC_IDR
- AT91_RTC_IER
- AT91_RTC_IMR
- AT91_RTC_IRQ_MASK
- AT91_RTC_MIN
- AT91_RTC_MINEN
- AT91_RTC_MONTH
- AT91_RTC_MR
- AT91_RTC_MTHEN
- AT91_RTC_NVCAL
- AT91_RTC_NVCALALR
- AT91_RTC_NVTIM
- AT91_RTC_NVTIMALR
- AT91_RTC_SCCR
- AT91_RTC_SEC
- AT91_RTC_SECEN
- AT91_RTC_SECEV
- AT91_RTC_SR
- AT91_RTC_TIMALR
- AT91_RTC_TIMEV
- AT91_RTC_TIMEVSEL
- AT91_RTC_TIMEVSEL_DAY12
- AT91_RTC_TIMEVSEL_DAY24
- AT91_RTC_TIMEVSEL_HOUR
- AT91_RTC_TIMEVSEL_MINUTE
- AT91_RTC_TIMR
- AT91_RTC_UPDCAL
- AT91_RTC_UPDTIM
- AT91_RTC_VER
- AT91_RTC_YEAR
- AT91_RTT_ALMIEN
- AT91_RTT_ALMS
- AT91_RTT_ALMV
- AT91_RTT_AR
- AT91_RTT_CRTV
- AT91_RTT_MR
- AT91_RTT_RTPRES
- AT91_RTT_RTTINC
- AT91_RTT_RTTINCIEN
- AT91_RTT_RTTRST
- AT91_RTT_SR
- AT91_RTT_VR
- AT91_SAMA5D2_ACR
- AT91_SAMA5D2_ACR_PENDETSENS_MASK
- AT91_SAMA5D2_ADC_P_CHANNEL
- AT91_SAMA5D2_ADC_X_CHANNEL
- AT91_SAMA5D2_ADC_Y_CHANNEL
- AT91_SAMA5D2_CDR0
- AT91_SAMA5D2_CECR
- AT91_SAMA5D2_CGR
- AT91_SAMA5D2_CHAN_DIFF
- AT91_SAMA5D2_CHAN_PRESSURE
- AT91_SAMA5D2_CHAN_SINGLE
- AT91_SAMA5D2_CHAN_TOUCH
- AT91_SAMA5D2_CHDR
- AT91_SAMA5D2_CHER
- AT91_SAMA5D2_CHSR
- AT91_SAMA5D2_COR
- AT91_SAMA5D2_COR_DIFF_OFFSET
- AT91_SAMA5D2_COSR
- AT91_SAMA5D2_CR
- AT91_SAMA5D2_CR_CMPRST
- AT91_SAMA5D2_CR_START
- AT91_SAMA5D2_CR_SWRST
- AT91_SAMA5D2_CR_TSCALIB
- AT91_SAMA5D2_CVR
- AT91_SAMA5D2_CWR
- AT91_SAMA5D2_DIFF_CHAN_CNT
- AT91_SAMA5D2_EMR
- AT91_SAMA5D2_EMR_ASTE
- AT91_SAMA5D2_EMR_OSR
- AT91_SAMA5D2_EMR_OSR_16SAMPLES
- AT91_SAMA5D2_EMR_OSR_1SAMPLES
- AT91_SAMA5D2_EMR_OSR_4SAMPLES
- AT91_SAMA5D2_EMR_OSR_MASK
- AT91_SAMA5D2_HW_TRIG_CNT
- AT91_SAMA5D2_IDR
- AT91_SAMA5D2_IER
- AT91_SAMA5D2_IER_GOVRE
- AT91_SAMA5D2_IER_NOPEN
- AT91_SAMA5D2_IER_PEN
- AT91_SAMA5D2_IER_PRDY
- AT91_SAMA5D2_IER_XRDY
- AT91_SAMA5D2_IER_YRDY
- AT91_SAMA5D2_IMR
- AT91_SAMA5D2_ISR
- AT91_SAMA5D2_ISR_PENS
- AT91_SAMA5D2_LCCWR
- AT91_SAMA5D2_LCDR
- AT91_SAMA5D2_LCTMR
- AT91_SAMA5D2_MAX_CHAN_IDX
- AT91_SAMA5D2_MAX_POS_BITS
- AT91_SAMA5D2_MR
- AT91_SAMA5D2_MR_ANACH
- AT91_SAMA5D2_MR_FWUP
- AT91_SAMA5D2_MR_PRESCAL
- AT91_SAMA5D2_MR_PRESCAL_MASK
- AT91_SAMA5D2_MR_PRESCAL_MAX
- AT91_SAMA5D2_MR_PRESCAL_OFFSET
- AT91_SAMA5D2_MR_SLEEP
- AT91_SAMA5D2_MR_STARTUP
- AT91_SAMA5D2_MR_STARTUP_MASK
- AT91_SAMA5D2_MR_TRACKTIM
- AT91_SAMA5D2_MR_TRACKTIM_MAX
- AT91_SAMA5D2_MR_TRANSFER
- AT91_SAMA5D2_MR_TRANSFER_MAX
- AT91_SAMA5D2_MR_TRGSEL
- AT91_SAMA5D2_MR_TRGSEL_TRIG0
- AT91_SAMA5D2_MR_TRGSEL_TRIG1
- AT91_SAMA5D2_MR_TRGSEL_TRIG2
- AT91_SAMA5D2_MR_TRGSEL_TRIG3
- AT91_SAMA5D2_MR_TRGSEL_TRIG4
- AT91_SAMA5D2_MR_TRGSEL_TRIG5
- AT91_SAMA5D2_MR_TRGSEL_TRIG6
- AT91_SAMA5D2_MR_TRGSEL_TRIG7
- AT91_SAMA5D2_MR_USEQ
- AT91_SAMA5D2_OVER
- AT91_SAMA5D2_PRESSR
- AT91_SAMA5D2_SEQR1
- AT91_SAMA5D2_SEQR2
- AT91_SAMA5D2_SINGLE_CHAN_CNT
- AT91_SAMA5D2_TIMESTAMP_CHAN_IDX
- AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US
- AT91_SAMA5D2_TOUCH_P_CHAN_IDX
- AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US
- AT91_SAMA5D2_TOUCH_X_CHAN_IDX
- AT91_SAMA5D2_TOUCH_Y_CHAN_IDX
- AT91_SAMA5D2_TRGR
- AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY
- AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL
- AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE
- AT91_SAMA5D2_TRGR_TRGMOD_MASK
- AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER
- AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC
- AT91_SAMA5D2_TRGR_TRGPER
- AT91_SAMA5D2_TRGR_TRGPER_MASK
- AT91_SAMA5D2_TSMR
- AT91_SAMA5D2_TSMR_NOTSDMA
- AT91_SAMA5D2_TSMR_PENDBC
- AT91_SAMA5D2_TSMR_PENDBC_MASK
- AT91_SAMA5D2_TSMR_PENDET_DIS
- AT91_SAMA5D2_TSMR_PENDET_ENA
- AT91_SAMA5D2_TSMR_TSAV
- AT91_SAMA5D2_TSMR_TSAV_MASK
- AT91_SAMA5D2_TSMR_TSFREQ
- AT91_SAMA5D2_TSMR_TSFREQ_MASK
- AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS
- AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS
- AT91_SAMA5D2_TSMR_TSMODE_5WIRE
- AT91_SAMA5D2_TSMR_TSMODE_NONE
- AT91_SAMA5D2_VERSION
- AT91_SAMA5D2_WPMR
- AT91_SAMA5D2_WPSR
- AT91_SAMA5D2_XPOSR
- AT91_SAMA5D2_XYZ_MASK
- AT91_SAMA5D2_YPOSR
- AT91_SCKC_CR
- AT91_SDRAMC_CAS
- AT91_SDRAMC_CAS_1
- AT91_SDRAMC_CAS_2
- AT91_SDRAMC_CAS_3
- AT91_SDRAMC_COUNT
- AT91_SDRAMC_CR
- AT91_SDRAMC_DBW
- AT91_SDRAMC_DBW_16
- AT91_SDRAMC_DBW_32
- AT91_SDRAMC_DS
- AT91_SDRAMC_IDR
- AT91_SDRAMC_IER
- AT91_SDRAMC_IMR
- AT91_SDRAMC_ISR
- AT91_SDRAMC_LPCB
- AT91_SDRAMC_LPCB_DEEP_POWER_DOWN
- AT91_SDRAMC_LPCB_DISABLE
- AT91_SDRAMC_LPCB_POWER_DOWN
- AT91_SDRAMC_LPCB_SELF_REFRESH
- AT91_SDRAMC_LPR
- AT91_SDRAMC_MD
- AT91_SDRAMC_MDR
- AT91_SDRAMC_MD_LOW_POWER_SDRAM
- AT91_SDRAMC_MD_SDRAM
- AT91_SDRAMC_MODE
- AT91_SDRAMC_MODE_DEEP
- AT91_SDRAMC_MODE_EXT_LMR
- AT91_SDRAMC_MODE_LMR
- AT91_SDRAMC_MODE_NOP
- AT91_SDRAMC_MODE_NORMAL
- AT91_SDRAMC_MODE_PRECHARGE
- AT91_SDRAMC_MODE_REFRESH
- AT91_SDRAMC_MR
- AT91_SDRAMC_NB
- AT91_SDRAMC_NB_2
- AT91_SDRAMC_NB_4
- AT91_SDRAMC_NC
- AT91_SDRAMC_NC_10
- AT91_SDRAMC_NC_11
- AT91_SDRAMC_NC_8
- AT91_SDRAMC_NC_9
- AT91_SDRAMC_NR
- AT91_SDRAMC_NR_11
- AT91_SDRAMC_NR_12
- AT91_SDRAMC_NR_13
- AT91_SDRAMC_PASR
- AT91_SDRAMC_RES
- AT91_SDRAMC_TCSR
- AT91_SDRAMC_TIMEOUT
- AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES
- AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES
- AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES
- AT91_SDRAMC_TR
- AT91_SDRAMC_TRAS
- AT91_SDRAMC_TRC
- AT91_SDRAMC_TRCD
- AT91_SDRAMC_TRP
- AT91_SDRAMC_TWR
- AT91_SDRAMC_TXSR
- AT91_SECUMOD_RAMRDY
- AT91_SECUMOD_RAMRDY_READY
- AT91_SFR_CCFG_DDR_MP_EN
- AT91_SFR_CCFG_EBICSA
- AT91_SFR_CCFG_EBI_CSA
- AT91_SFR_CCFG_EBI_DBPDC
- AT91_SFR_CCFG_EBI_DBPUC
- AT91_SFR_CCFG_EBI_DRIVE
- AT91_SFR_CCFG_NFD0_ON_D16
- AT91_SFR_DDRCFG
- AT91_SFR_I2SCLKSEL
- AT91_SFR_LS
- AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN
- AT91_SFR_LS_VALUE
- AT91_SFR_OHCIICR
- AT91_SFR_OHCIICR_APPSTART
- AT91_SFR_OHCIICR_ARIE
- AT91_SFR_OHCIICR_RES
- AT91_SFR_OHCIICR_UDPPUDIS
- AT91_SFR_OHCIICR_USB_SUSP
- AT91_SFR_OHCIISR
- AT91_SFR_OHCIISR_RIS
- AT91_SFR_UTMICKTRIM
- AT91_SFR_UTMISWAP
- AT91_SFR_UTMISWAP_PORT
- AT91_SFR_WPMR
- AT91_SFR_WPMR_WPEN
- AT91_SFR_WPMR_WPKEY_MASK
- AT91_SHDW_CPTWK0
- AT91_SHDW_CPTWK0_
- AT91_SHDW_CPTWK0_MAX
- AT91_SHDW_CR
- AT91_SHDW_KEY
- AT91_SHDW_MR
- AT91_SHDW_RTCWK
- AT91_SHDW_RTCWKEN
- AT91_SHDW_RTTWK
- AT91_SHDW_RTTWKEN
- AT91_SHDW_SHDW
- AT91_SHDW_SR
- AT91_SHDW_WAKEUP0
- AT91_SHDW_WKMODE0
- AT91_SHDW_WKMODE0_ANYLEVEL
- AT91_SHDW_WKMODE0_HIGH
- AT91_SHDW_WKMODE0_LOW
- AT91_SHDW_WKMODE0_NONE
- AT91_SHDW_WKUPDBC
- AT91_SHDW_WKUPDBC_MASK
- AT91_SHDW_WKUPDBC_SHIFT
- AT91_SHDW_WKUPEN
- AT91_SHDW_WKUPEN_MASK
- AT91_SHDW_WKUPIS
- AT91_SHDW_WKUPIS_MASK
- AT91_SHDW_WKUPIS_SHIFT
- AT91_SHDW_WKUPT
- AT91_SHDW_WKUPT_MASK
- AT91_SHDW_WKUPT_SHIFT
- AT91_SHDW_WUIR
- AT91_SOC
- AT91_SR
- AT91_SR_RBSY
- AT91_ST_ALMS
- AT91_ST_ALMV
- AT91_ST_CR
- AT91_ST_CRTR
- AT91_ST_CRTV
- AT91_ST_EXTEN
- AT91_ST_IDR
- AT91_ST_IER
- AT91_ST_IMR
- AT91_ST_PIMR
- AT91_ST_PITS
- AT91_ST_PIV
- AT91_ST_RSTEN
- AT91_ST_RTAR
- AT91_ST_RTMR
- AT91_ST_RTPRES
- AT91_ST_RTTINC
- AT91_ST_SR
- AT91_ST_WDMR
- AT91_ST_WDOVF
- AT91_ST_WDRST
- AT91_ST_WDV
- AT91_TCR
- AT91_TIM
- AT91_TIMESTP
- AT91_TWI_ACMDIS
- AT91_TWI_ACMEN
- AT91_TWI_ACR
- AT91_TWI_ACR_DATAL
- AT91_TWI_ACR_DIR
- AT91_TWI_CR
- AT91_TWI_CWGR
- AT91_TWI_CWGR_HOLD
- AT91_TWI_CWGR_HOLD_MAX
- AT91_TWI_EOSACC
- AT91_TWI_FIDR
- AT91_TWI_FIER
- AT91_TWI_FIFODIS
- AT91_TWI_FIFOEN
- AT91_TWI_FIMR
- AT91_TWI_FLR
- AT91_TWI_FMR
- AT91_TWI_FMR_RXRDYM
- AT91_TWI_FMR_RXRDYM_MASK
- AT91_TWI_FMR_TXRDYM
- AT91_TWI_FMR_TXRDYM_MASK
- AT91_TWI_FOUR_DATA
- AT91_TWI_FSR
- AT91_TWI_IADR
- AT91_TWI_IADRSZ_1
- AT91_TWI_IDR
- AT91_TWI_IER
- AT91_TWI_IMR
- AT91_TWI_INT_MASK
- AT91_TWI_LOCK
- AT91_TWI_LOCKCLR
- AT91_TWI_MMR
- AT91_TWI_MREAD
- AT91_TWI_MSDIS
- AT91_TWI_MSEN
- AT91_TWI_NACK
- AT91_TWI_ONE_DATA
- AT91_TWI_OVRE
- AT91_TWI_QUICK
- AT91_TWI_RHR
- AT91_TWI_RHRCLR
- AT91_TWI_RXRDY
- AT91_TWI_SMR
- AT91_TWI_SMR_SADR
- AT91_TWI_SMR_SADR_MAX
- AT91_TWI_SR
- AT91_TWI_START
- AT91_TWI_STOP
- AT91_TWI_SVACC
- AT91_TWI_SVDIS
- AT91_TWI_SVEN
- AT91_TWI_SVREAD
- AT91_TWI_SWRST
- AT91_TWI_THR
- AT91_TWI_THRCLR
- AT91_TWI_TWO_DATA
- AT91_TWI_TXCOMP
- AT91_TWI_TXRDY
- AT91_TWI_UNRE
- AT91_TWI_VER
- AT91_UDC_H
- AT91_UDP_CONFG
- AT91_UDP_CSR
- AT91_UDP_DIR
- AT91_UDP_DTGLE
- AT91_UDP_ENDBUSRES
- AT91_UDP_EP
- AT91_UDP_EPEDS
- AT91_UDP_EPTYPE
- AT91_UDP_EPTYPE_BULK_IN
- AT91_UDP_EPTYPE_BULK_OUT
- AT91_UDP_EPTYPE_CTRL
- AT91_UDP_EPTYPE_INT_IN
- AT91_UDP_EPTYPE_INT_OUT
- AT91_UDP_EPTYPE_ISO_IN
- AT91_UDP_EPTYPE_ISO_OUT
- AT91_UDP_ESR
- AT91_UDP_EXTRSM
- AT91_UDP_FADD
- AT91_UDP_FADDEN
- AT91_UDP_FADDR
- AT91_UDP_FDR
- AT91_UDP_FEN
- AT91_UDP_FORCESTALL
- AT91_UDP_FRM_ERR
- AT91_UDP_FRM_NUM
- AT91_UDP_FRM_OK
- AT91_UDP_GLB_STAT
- AT91_UDP_ICR
- AT91_UDP_IDR
- AT91_UDP_IER
- AT91_UDP_IMR
- AT91_UDP_ISR
- AT91_UDP_NUM
- AT91_UDP_RMWUPE
- AT91_UDP_RSMINPR
- AT91_UDP_RST_EP
- AT91_UDP_RXBYTECNT
- AT91_UDP_RXRSM
- AT91_UDP_RXSETUP
- AT91_UDP_RXSUSP
- AT91_UDP_RX_DATA_BK0
- AT91_UDP_RX_DATA_BK1
- AT91_UDP_SOFINT
- AT91_UDP_STALLSENT
- AT91_UDP_TXCOMP
- AT91_UDP_TXPKTRDY
- AT91_UDP_TXVC
- AT91_UDP_TXVC_PUON
- AT91_UDP_TXVC_TXVDIS
- AT91_UDP_WAKEUP
- AT91_USART_MODE_SERIAL
- AT91_USART_MODE_SPI
- AT91_UTMICKTRIM_FREQ
- AT91_WDT_CR
- AT91_WDT_H
- AT91_WDT_KEY
- AT91_WDT_MR
- AT91_WDT_SET_WDD
- AT91_WDT_SET_WDV
- AT91_WDT_SR
- AT91_WDT_WDD
- AT91_WDT_WDDBGHLT
- AT91_WDT_WDDIS
- AT91_WDT_WDERR
- AT91_WDT_WDFIEN
- AT91_WDT_WDIDLEHLT
- AT91_WDT_WDRPROC
- AT91_WDT_WDRSTEN
- AT91_WDT_WDRSTT
- AT91_WDT_WDUNF
- AT91_WDT_WDV
- AT91_XDMAC_DT_GET_MEM_IF
- AT91_XDMAC_DT_GET_PERID
- AT91_XDMAC_DT_GET_PER_IF
- AT91_XDMAC_DT_MEM_IF
- AT91_XDMAC_DT_MEM_IF_MASK
- AT91_XDMAC_DT_MEM_IF_OFFSET
- AT91_XDMAC_DT_PERID
- AT91_XDMAC_DT_PERID_MASK
- AT91_XDMAC_DT_PERID_OFFSET
- AT91_XDMAC_DT_PER_IF
- AT91_XDMAC_DT_PER_IF_MASK
- AT91_XDMAC_DT_PER_IF_OFFSET
- AT9285_COEX3WIRE_DA_SUBSYSID
- AT9285_COEX3WIRE_SA_SUBSYSID
- AT93C_ADDR_MAX
- AT93C_ADDR_SHIFT
- AT93C_CLK_M_100
- AT93C_CLK_M_200
- AT93C_CODE
- AT93C_CS_M_100
- AT93C_CS_M_200
- AT93C_ERASE
- AT93C_ER_ALL
- AT93C_RCMD
- AT93C_RDATA_REG_100
- AT93C_RDATA_REG_200
- AT93C_RDATA_SHIFT_100
- AT93C_RDATA_SHIFT_200
- AT93C_READ
- AT93C_REG_100
- AT93C_REG_200
- AT93C_WCMD
- AT93C_WDATA_SHIFT_100
- AT93C_WDATA_SHIFT_200
- AT93C_WDSCMD
- AT93C_WENCMD
- AT93C_WRITE
- AT93C_WR_ALL
- AT93C_WR_OFF
- AT93C_WR_ON
- ATA
- ATACFGE_CONF_DESC2
- ATACFGE_DESC_OVERRIDE
- ATACFGE_INIT_STATUS
- ATACFGE_LAST_LUN
- ATACFGE_SKIP_BOOT
- ATACFGE_STATE_SUSPEND
- ATACFG_ATAPI_RESET
- ATACFG_BLOCKSIZE
- ATACFG_MASTER
- ATACFG_TIMING
- ATACNR_OFS
- ATACS00_MARK
- ATACS00_N_MARK
- ATACS01_MARK
- ATACS01_N_MARK
- ATACS0_MARK
- ATACS10_MARK
- ATACS10_N_MARK
- ATACS11_MARK
- ATACS11_N_MARK
- ATACS1_MARK
- ATAC_BM0_CMD_PRIM
- ATAC_BM0_PRD
- ATAC_BM0_STS_PRIM
- ATAC_CH0D0_DMA
- ATAC_CH0D0_PIO
- ATAC_CH0D1_DMA
- ATAC_CH0D1_PIO
- ATAC_GLD_MSR_CAP
- ATAC_GLD_MSR_CONFIG
- ATAC_GLD_MSR_DIAG
- ATAC_GLD_MSR_ERROR
- ATAC_GLD_MSR_PM
- ATAC_GLD_MSR_SMI
- ATAC_IO_BAR
- ATAC_PCI_ABRTERR
- ATAC_RESET
- ATADDR_ANYNET
- ATADDR_ANYNODE
- ATADDR_ANYPORT
- ATADDR_BCAST
- ATADIR0_A_MARK
- ATADIR0_B_MARK
- ATADIR0_MARK
- ATADIR0_N_B_MARK
- ATADIR0_N_C_MARK
- ATADIR0_N_MARK
- ATADIR1_MARK
- ATADIR1_N_MARK
- ATADIR_MARK
- ATAFB_EXT
- ATAFB_FALCON
- ATAFB_STE
- ATAFB_TT
- ATAG0_A_MARK
- ATAG0_B_MARK
- ATAG0_MARK
- ATAG0_N_B_MARK
- ATAG0_N_C_MARK
- ATAG0_N_MARK
- ATAG1_MARK
- ATAG1_N_MARK
- ATAG_ACORN
- ATAG_CMDLINE
- ATAG_CORE
- ATAG_CORE_SIZE
- ATAG_CORE_SIZE_EMPTY
- ATAG_INITRD
- ATAG_INITRD2
- ATAG_MARK
- ATAG_MEM
- ATAG_MEMCLK
- ATAG_NONE
- ATAG_RAMDISK
- ATAG_REVISION
- ATAG_SERIAL
- ATAG_VIDEOLFB
- ATAG_VIDEOTEXT
- ATAO_2_DMATCCLR_REG
- ATAO_2_INT1CLR_REG
- ATAO_2_INT2CLR_REG
- ATAO_2_RTSISHFT_REG
- ATAO_2_RTSISHFT_RSI
- ATAO_2_RTSISTRB_REG
- ATAO_82C53_BASE
- ATAO_AO_REG
- ATAO_CFG1_CH
- ATAO_CFG1_CNT1SRC
- ATAO_CFG1_CNT2SRC
- ATAO_CFG1_CNTINT1EN
- ATAO_CFG1_CNTINT2EN
- ATAO_CFG1_DMAEN
- ATAO_CFG1_DMARQ
- ATAO_CFG1_EXTINT1EN
- ATAO_CFG1_EXTINT2EN
- ATAO_CFG1_EXTUPDEN
- ATAO_CFG1_FIFOEN
- ATAO_CFG1_GRP2WR
- ATAO_CFG1_REG
- ATAO_CFG1_TCINTEN
- ATAO_CFG2_CALLD
- ATAO_CFG2_CALLD_NOP
- ATAO_CFG2_DACS
- ATAO_CFG2_FFRTEN
- ATAO_CFG2_LDAC
- ATAO_CFG2_PROMEN
- ATAO_CFG2_REG
- ATAO_CFG2_SCLK
- ATAO_CFG2_SDATA
- ATAO_CFG3_CLKOUT
- ATAO_CFG3_DMAMODE
- ATAO_CFG3_DOUTEN1
- ATAO_CFG3_DOUTEN2
- ATAO_CFG3_EN2_5V
- ATAO_CFG3_RCLKEN
- ATAO_CFG3_REG
- ATAO_CFG3_SCANEN
- ATAO_DIO_REG
- ATAO_FIFO_CLEAR_REG
- ATAO_FIFO_WRITE_REG
- ATAO_STATUS_FE
- ATAO_STATUS_FF
- ATAO_STATUS_FH
- ATAO_STATUS_INT1
- ATAO_STATUS_INT2
- ATAO_STATUS_PROMOUT
- ATAO_STATUS_REG
- ATAO_STATUS_TCINT
- ATAPI
- ATAPI0
- ATAPI1
- ATAPI2
- ATAPI3
- ATAPI_ALT_STATUS
- ATAPI_ATAPII
- ATAPI_BYTE_SWAP_REG
- ATAPI_CAPABILITIES_PAGE_PAD_SIZE
- ATAPI_CAPABILITIES_PAGE_SIZE
- ATAPI_CAPACITY
- ATAPI_CDB_LEN
- ATAPI_CMD
- ATAPI_COD
- ATAPI_COMMAND
- ATAPI_CONTROL1_DESE
- ATAPI_CONTROL1_DTA32M
- ATAPI_CONTROL1_ISM
- ATAPI_CONTROL1_REG
- ATAPI_CONTROL1_RESET
- ATAPI_CONTROL1_RW
- ATAPI_CONTROL1_START
- ATAPI_CONTROL1_STOP
- ATAPI_CONTROL2_REG
- ATAPI_COUNT_HIGH
- ATAPI_COUNT_LOW
- ATAPI_DATA
- ATAPI_DEVICE_CONTROL
- ATAPI_DMADIR
- ATAPI_DMA_START_ADR_REG
- ATAPI_DMA_TRANS_CNT_REG
- ATAPI_DOOR
- ATAPI_DRIVE_SEL
- ATAPI_DTB_ADR_REG
- ATAPI_EOM
- ATAPI_ERROR
- ATAPI_FEATURES
- ATAPI_IDENTIFY
- ATAPI_ILI
- ATAPI_INT_ENABLE_ACT
- ATAPI_INT_ENABLE_DEVINT
- ATAPI_INT_ENABLE_DEVTRM
- ATAPI_INT_ENABLE_DNEND
- ATAPI_INT_ENABLE_ERR
- ATAPI_INT_ENABLE_NEND
- ATAPI_INT_ENABLE_REG
- ATAPI_INT_ENABLE_SATAINT
- ATAPI_INT_REASON
- ATAPI_IO
- ATAPI_LFS
- ATAPI_LOCK
- ATAPI_LOG_SENSE
- ATAPI_MAX_DRAIN
- ATAPI_MIN_CDB_BYTES
- ATAPI_MISC
- ATAPI_MODE_SENSE
- ATAPI_PASS_THRU
- ATAPI_PKT_DMA
- ATAPI_PROT_DMA
- ATAPI_PROT_NODATA
- ATAPI_PROT_PIO
- ATAPI_READ
- ATAPI_READ_10
- ATAPI_READ_6
- ATAPI_READ_CD
- ATAPI_REQ_SENSE
- ATAPI_REWIND
- ATAPI_SIG_ST_REG
- ATAPI_STATUS
- ATAPI_STATUS_ACT
- ATAPI_STATUS_DEVINT
- ATAPI_STATUS_DEVTRM
- ATAPI_STATUS_DNEND
- ATAPI_STATUS_ERR
- ATAPI_STATUS_NEND
- ATAPI_STATUS_REG
- ATAPI_STATUS_SATAINT
- ATAPI_TEST_READY
- ATAPI_WAIT_PC
- ATAPI_WAIT_WRITE_BUSY
- ATAPI_WFM
- ATAPI_WRITE
- ATAPI_WRITE_10
- ATAPI_WRITE_6
- ATARAID_MAJOR
- ATARD0_MARK
- ATARD0_N_B_MARK
- ATARD0_N_MARK
- ATARD1_MARK
- ATARD1_N_MARK
- ATARD_MARK
- ATARIHW_ANNOUNCE
- ATARIHW_DECLARE
- ATARIHW_PRESENT
- ATARIHW_SET
- ATARIMOUSE_MINOR
- ATARI_BOOTI_VERSION
- ATARI_CKS_LOC
- ATARI_CKS_RANGE_END
- ATARI_CKS_RANGE_START
- ATARI_ETHERNAT_IRQ
- ATARI_ETHERNAT_PHYS_ADDR
- ATARI_ETHERNEC_BASE
- ATARI_ETHERNEC_IRQ
- ATARI_ETHERNEC_PHYS_ADDR
- ATARI_MACH_AB40
- ATARI_MACH_HADES
- ATARI_MACH_MEDUSA
- ATARI_MACH_NORMAL
- ATARI_MCH_FALCON
- ATARI_MCH_ST
- ATARI_MCH_STE
- ATARI_MCH_TT
- ATARI_NETUSBEE_BASE
- ATARI_NETUSBEE_IRQ
- ATARI_NETUSBEE_PHYS_ADDR
- ATARI_RTC_PORT
- ATARI_SWITCH_IKBD
- ATARI_SWITCH_MIDI
- ATARI_SWITCH_OVSC_IKBD
- ATARI_SWITCH_OVSC_MASK
- ATARI_SWITCH_OVSC_MIDI
- ATARI_SWITCH_OVSC_SHIFT
- ATARI_SWITCH_OVSC_SND6
- ATARI_SWITCH_OVSC_SND7
- ATARI_SWITCH_SND6
- ATARI_SWITCH_SND7
- ATARI_USB_IRQ
- ATARI_USB_PHYS_ADDR
- ATAWR0_A_MARK
- ATAWR0_B_MARK
- ATAWR0_MARK
- ATAWR0_N_B_MARK
- ATAWR0_N_C_MARK
- ATAWR0_N_MARK
- ATAWR1_MARK
- ATAWR1_N_MARK
- ATAWR_MARK
- ATA_100
- ATA_100a
- ATA_12
- ATA_133
- ATA_133a
- ATA_16
- ATA_32
- ATA_33
- ATA_50
- ATA_66
- ATA_ABORTED
- ATA_ACPI_FILTER_DEFAULT
- ATA_ACPI_FILTER_DIPM
- ATA_ACPI_FILTER_FPDMA_AA
- ATA_ACPI_FILTER_FPDMA_OFFSET
- ATA_ACPI_FILTER_LOCK
- ATA_ACPI_FILTER_SETXFER
- ATA_ADDRESS_DEVHEAD_LBA_MODE
- ATA_ADDRESS_DEVHEAD_SLAVE
- ATA_ADDRESS_DEVHEAD_STD
- ATA_ALL_DEVICES
- ATA_AMNF
- ATA_ANY
- ATA_ASTS_DCTR
- ATA_BASE_SHT
- ATA_BBK
- ATA_BMDMA_SHT
- ATA_BUSY
- ATA_CBL_NONE
- ATA_CBL_PATA40
- ATA_CBL_PATA40_SHORT
- ATA_CBL_PATA80
- ATA_CBL_PATA_IGN
- ATA_CBL_PATA_UNK
- ATA_CBL_SATA
- ATA_CH
- ATA_CL
- ATA_CLOCK_25MHZ
- ATA_CLOCK_33MHZ
- ATA_CLOCK_40MHZ
- ATA_CLOCK_50MHZ
- ATA_CLOCK_66MHZ
- ATA_CMD_CFA_ERASE
- ATA_CMD_CFA_REQ_EXT_ERR
- ATA_CMD_CFA_TRANS_SECT
- ATA_CMD_CFA_WRITE_MULT_NE
- ATA_CMD_CFA_WRITE_NE
- ATA_CMD_CHK_MED_CRD_TYP
- ATA_CMD_CHK_POWER
- ATA_CMD_CONFIG_STREAM
- ATA_CMD_CONF_OVERLAY
- ATA_CMD_DEV_RESET
- ATA_CMD_DOWNLOAD_MICRO
- ATA_CMD_DOWNLOAD_MICRO_DMA
- ATA_CMD_DSM
- ATA_CMD_EDD
- ATA_CMD_FLUSH
- ATA_CMD_FLUSH_EXT
- ATA_CMD_FPDMA_READ
- ATA_CMD_FPDMA_RECV
- ATA_CMD_FPDMA_SEND
- ATA_CMD_FPDMA_WRITE
- ATA_CMD_IDLE
- ATA_CMD_IDLEIMMEDIATE
- ATA_CMD_ID_ATA
- ATA_CMD_ID_ATAPI
- ATA_CMD_INIT_DEV_PARAMS
- ATA_CMD_MEDIA_LOCK
- ATA_CMD_MEDIA_UNLOCK
- ATA_CMD_NCQ_NON_DATA
- ATA_CMD_NOP
- ATA_CMD_PACKET
- ATA_CMD_PIO_READ
- ATA_CMD_PIO_READ_EXT
- ATA_CMD_PIO_WRITE
- ATA_CMD_PIO_WRITE_EXT
- ATA_CMD_PMP_READ
- ATA_CMD_PMP_READ_DMA
- ATA_CMD_PMP_WRITE
- ATA_CMD_PMP_WRITE_DMA
- ATA_CMD_READ
- ATA_CMD_READ_EXT
- ATA_CMD_READ_LOG_DMA_EXT
- ATA_CMD_READ_LOG_EXT
- ATA_CMD_READ_LONG
- ATA_CMD_READ_LONG_ONCE
- ATA_CMD_READ_MULTI
- ATA_CMD_READ_MULTI_EXT
- ATA_CMD_READ_NATIVE_MAX
- ATA_CMD_READ_NATIVE_MAX_EXT
- ATA_CMD_READ_QUEUED
- ATA_CMD_READ_STREAM_DMA_EXT
- ATA_CMD_READ_STREAM_EXT
- ATA_CMD_REQ_SENSE_DATA
- ATA_CMD_RESTORE
- ATA_CMD_SANITIZE_DEVICE
- ATA_CMD_SCBPTR
- ATA_CMD_SEC_DISABLE_PASS
- ATA_CMD_SEC_ERASE_PREP
- ATA_CMD_SEC_ERASE_UNIT
- ATA_CMD_SEC_FREEZE_LOCK
- ATA_CMD_SEC_SET_PASS
- ATA_CMD_SEC_UNLOCK
- ATA_CMD_SERVICE
- ATA_CMD_SET_FEATURES
- ATA_CMD_SET_MAX
- ATA_CMD_SET_MAX_EXT
- ATA_CMD_SET_MULTI
- ATA_CMD_SLEEP
- ATA_CMD_SMART
- ATA_CMD_STANDBY
- ATA_CMD_STANDBYNOW1
- ATA_CMD_TRUSTED_NONDATA
- ATA_CMD_TRUSTED_RCV
- ATA_CMD_TRUSTED_RCV_DMA
- ATA_CMD_TRUSTED_SND
- ATA_CMD_TRUSTED_SND_DMA
- ATA_CMD_VERIFY
- ATA_CMD_VERIFY_EXT
- ATA_CMD_WRITE
- ATA_CMD_WRITE_EXT
- ATA_CMD_WRITE_FUA_EXT
- ATA_CMD_WRITE_LOG_DMA_EXT
- ATA_CMD_WRITE_LOG_EXT
- ATA_CMD_WRITE_LONG
- ATA_CMD_WRITE_LONG_ONCE
- ATA_CMD_WRITE_MULTI
- ATA_CMD_WRITE_MULTI_EXT
- ATA_CMD_WRITE_MULTI_FUA_EXT
- ATA_CMD_WRITE_QUEUED
- ATA_CMD_WRITE_QUEUED_FUA_EXT
- ATA_CMD_WRITE_STREAM_DMA_EXT
- ATA_CMD_WRITE_STREAM_EXT
- ATA_CMD_WRITE_UNCORR_EXT
- ATA_CMD_ZAC_MGMT_IN
- ATA_CMD_ZAC_MGMT_OUT
- ATA_COMMAND_GET_MEDIA_STATUS
- ATA_COMMAND_MEDIA_EJECT
- ATA_CORR
- ATA_DATA_PORT
- ATA_DATA_PORT_MASK
- ATA_DCO_FREEZE_LOCK
- ATA_DCO_IDENTIFY
- ATA_DCO_RESTORE
- ATA_DCO_SET
- ATA_DC_DISABLE_INTERRUPTS
- ATA_DC_REENABLE_CONTROLLER
- ATA_DC_RESET_CONTROLLER
- ATA_DEBUG
- ATA_DEFER_LINK
- ATA_DEFER_PORT
- ATA_DEF_QUEUE
- ATA_DEV1
- ATA_DEVCTL_OBS
- ATA_DEVICE_ATTR
- ATA_DEVICE_CLEAR_BEGIN
- ATA_DEVICE_CLEAR_END
- ATA_DEVICE_OBS
- ATA_DEV_ATA
- ATA_DEV_ATAPI
- ATA_DEV_ATAPI_UNSUP
- ATA_DEV_ATA_UNSUP
- ATA_DEV_ATTRS
- ATA_DEV_NONE
- ATA_DEV_PMP
- ATA_DEV_PMP_UNSUP
- ATA_DEV_SEMB
- ATA_DEV_SEMB_UNSUP
- ATA_DEV_UNKNOWN
- ATA_DEV_ZAC
- ATA_DEV_ZAC_UNSUP
- ATA_DF
- ATA_DFLAG_ACPI_DISABLED
- ATA_DFLAG_ACPI_FAILED
- ATA_DFLAG_ACPI_PENDING
- ATA_DFLAG_AN
- ATA_DFLAG_CDB_INTR
- ATA_DFLAG_CFG_MASK
- ATA_DFLAG_DA
- ATA_DFLAG_DETACH
- ATA_DFLAG_DETACHED
- ATA_DFLAG_DEVSLP
- ATA_DFLAG_DMADIR
- ATA_DFLAG_DUBIOUS_XFER
- ATA_DFLAG_D_SENSE
- ATA_DFLAG_FLUSH_EXT
- ATA_DFLAG_INIT_MASK
- ATA_DFLAG_LBA
- ATA_DFLAG_LBA48
- ATA_DFLAG_NCQ
- ATA_DFLAG_NCQ_OFF
- ATA_DFLAG_NCQ_PRIO
- ATA_DFLAG_NCQ_PRIO_ENABLE
- ATA_DFLAG_NCQ_SEND_RECV
- ATA_DFLAG_NO_UNLOAD
- ATA_DFLAG_PIO
- ATA_DFLAG_SLEEPING
- ATA_DFLAG_TRUSTED
- ATA_DFLAG_UNLOCK_HPA
- ATA_DFLAG_ZAC
- ATA_DITER_ALL
- ATA_DITER_ALL_REVERSE
- ATA_DITER_ENABLED
- ATA_DITER_ENABLED_REVERSE
- ATA_DMA_ACTIVE
- ATA_DMA_BOUNDARY
- ATA_DMA_CMD
- ATA_DMA_ERR
- ATA_DMA_INTR
- ATA_DMA_MASK
- ATA_DMA_MASK_ATA
- ATA_DMA_MASK_ATAPI
- ATA_DMA_MASK_CFA
- ATA_DMA_PAD_SZ
- ATA_DMA_START
- ATA_DMA_STATUS
- ATA_DMA_TABLE_OFS
- ATA_DMA_WR
- ATA_DNXFER_40C
- ATA_DNXFER_DMA
- ATA_DNXFER_FORCE_PIO
- ATA_DNXFER_FORCE_PIO0
- ATA_DNXFER_PIO
- ATA_DNXFER_QUIET
- ATA_DRDY
- ATA_DRQ
- ATA_DSC
- ATA_DSM_TRIM
- ATA_ECAT_ATA_BUS
- ATA_ECAT_DUBIOUS_ATA_BUS
- ATA_ECAT_DUBIOUS_NONE
- ATA_ECAT_DUBIOUS_TOUT_HSM
- ATA_ECAT_DUBIOUS_UNK_DEV
- ATA_ECAT_NONE
- ATA_ECAT_NR
- ATA_ECAT_TOUT_HSM
- ATA_ECAT_UNK_DEV
- ATA_EFLAG_DUBIOUS_XFER
- ATA_EFLAG_IS_IO
- ATA_EFLAG_OLD_ER
- ATA_EHI_DID_HARDRESET
- ATA_EHI_DID_RESET
- ATA_EHI_DID_SOFTRESET
- ATA_EHI_HOTPLUGGED
- ATA_EHI_NO_AUTOPSY
- ATA_EHI_NO_RECOVERY
- ATA_EHI_POST_SETMODE
- ATA_EHI_PRINTINFO
- ATA_EHI_QUIET
- ATA_EHI_SETMODE
- ATA_EHI_TO_SLAVE_MASK
- ATA_EH_ALL_ACTIONS
- ATA_EH_CMD_DFL_TIMEOUT
- ATA_EH_CMD_TIMEOUT_TABLE_SIZE
- ATA_EH_DESC_LEN
- ATA_EH_DEV_TRIES
- ATA_EH_ENABLE_LINK
- ATA_EH_FASTDRAIN_INTERVAL
- ATA_EH_HARDRESET
- ATA_EH_MAX_TRIES
- ATA_EH_PARK
- ATA_EH_PERDEV_MASK
- ATA_EH_PMP_LINK_TRIES
- ATA_EH_PMP_TRIES
- ATA_EH_PRERESET_TIMEOUT
- ATA_EH_PROBE_TRIALS
- ATA_EH_PROBE_TRIAL_INTERVAL
- ATA_EH_RESET
- ATA_EH_RESET_COOL_DOWN
- ATA_EH_REVALIDATE
- ATA_EH_SOFTRESET
- ATA_EH_SPDN_FALLBACK_TO_PIO
- ATA_EH_SPDN_KEEP_ERRORS
- ATA_EH_SPDN_NCQ_OFF
- ATA_EH_SPDN_SPEED_DOWN
- ATA_EH_UA_TRIES
- ATA_ERING_SIZE
- ATA_ERR
- ATA_ERROR_MEDIA_CHANGE
- ATA_ERR_FTR
- ATA_FLAG_ACPI_SATA
- ATA_FLAG_AN
- ATA_FLAG_DEBUGMSG
- ATA_FLAG_EM
- ATA_FLAG_FPDMA_AA
- ATA_FLAG_FPDMA_AUX
- ATA_FLAG_IGN_SIMPLEX
- ATA_FLAG_NCQ
- ATA_FLAG_NO_ATAPI
- ATA_FLAG_NO_DIPM
- ATA_FLAG_NO_HIBERNATE_SPINDOWN
- ATA_FLAG_NO_IORDY
- ATA_FLAG_NO_LOG_PAGE
- ATA_FLAG_NO_LPM
- ATA_FLAG_NO_POWEROFF_SPINDOWN
- ATA_FLAG_PIO_DMA
- ATA_FLAG_PIO_LBA48
- ATA_FLAG_PIO_POLLING
- ATA_FLAG_PMP
- ATA_FLAG_SAS_HOST
- ATA_FLAG_SATA
- ATA_FLAG_SLAVE_POSS
- ATA_FLAG_SW_ACTIVITY
- ATA_GEN_CLASS_MATCH
- ATA_GEN_FORCE_DMA
- ATA_GEN_INTEL_IDER
- ATA_HD_BASE
- ATA_HD_CONTROL
- ATA_HOB
- ATA_HORKAGE_1_5_GBPS
- ATA_HORKAGE_ATAPI_DMADIR
- ATA_HORKAGE_ATAPI_MOD16_DMA
- ATA_HORKAGE_BRIDGE_OK
- ATA_HORKAGE_BROKEN_FPDMA_AA
- ATA_HORKAGE_BROKEN_HPA
- ATA_HORKAGE_DIAGNOSTIC
- ATA_HORKAGE_DISABLE
- ATA_HORKAGE_DUMP_ID
- ATA_HORKAGE_FIRMWARE_WARN
- ATA_HORKAGE_HPA_SIZE
- ATA_HORKAGE_IVB
- ATA_HORKAGE_MAX_SEC_1024
- ATA_HORKAGE_MAX_SEC_128
- ATA_HORKAGE_MAX_SEC_LBA48
- ATA_HORKAGE_NODMA
- ATA_HORKAGE_NOLPM
- ATA_HORKAGE_NONCQ
- ATA_HORKAGE_NOSETXFER
- ATA_HORKAGE_NOTRIM
- ATA_HORKAGE_NO_DMA_LOG
- ATA_HORKAGE_NO_NCQ_TRIM
- ATA_HORKAGE_STUCK_ERR
- ATA_HORKAGE_WD_BROKEN_LPM
- ATA_HORKAGE_ZERO_AFTER_TRIM
- ATA_HOST_IGNORE_ATA
- ATA_HOST_PARALLEL_SCAN
- ATA_HOST_SIMPLEX
- ATA_HOST_STARTED
- ATA_ICRC
- ATA_IDNF
- ATA_ID_ADDITIONAL_SUPP
- ATA_ID_BUF_SIZE
- ATA_ID_CAPABILITY
- ATA_ID_CFA_KEY_MGMT
- ATA_ID_CFA_MODES
- ATA_ID_CFA_POWER
- ATA_ID_CFSSE
- ATA_ID_CFS_ENABLE_1
- ATA_ID_CFS_ENABLE_2
- ATA_ID_COMMAND_SET_1
- ATA_ID_COMMAND_SET_2
- ATA_ID_COMMAND_SET_3
- ATA_ID_COMMAND_SET_4
- ATA_ID_CONFIG
- ATA_ID_CSFO
- ATA_ID_CSF_DEFAULT
- ATA_ID_CUR_CYLS
- ATA_ID_CUR_HEADS
- ATA_ID_CUR_SECTORS
- ATA_ID_CYLS
- ATA_ID_DATA_SET_MGMT
- ATA_ID_DLF
- ATA_ID_DWORD_IO
- ATA_ID_EIDE_DMA_MIN
- ATA_ID_EIDE_DMA_TIME
- ATA_ID_EIDE_PIO
- ATA_ID_EIDE_PIO_IORDY
- ATA_ID_FEATURE_SUPP
- ATA_ID_FIELD_VALID
- ATA_ID_FW_REV
- ATA_ID_FW_REV_LEN
- ATA_ID_HEADS
- ATA_ID_HW_CONFIG
- ATA_ID_LAST_LUN
- ATA_ID_LBA_CAPACITY
- ATA_ID_LBA_CAPACITY_2
- ATA_ID_LOGICAL_SECTOR_SIZE
- ATA_ID_MAJOR_VER
- ATA_ID_MAX_MULTSECT
- ATA_ID_MULTSECT
- ATA_ID_MWDMA_MODES
- ATA_ID_OLD_DMA_MODES
- ATA_ID_OLD_PIO_MODES
- ATA_ID_PIO4
- ATA_ID_PIO_MODES
- ATA_ID_PROD
- ATA_ID_PROD_LEN
- ATA_ID_QUEUE_DEPTH
- ATA_ID_ROT_SPEED
- ATA_ID_SATA_CAPABILITY
- ATA_ID_SATA_CAPABILITY_2
- ATA_ID_SCT_CMD_XPORT
- ATA_ID_SECTORS
- ATA_ID_SECTOR_SIZE
- ATA_ID_SERNO
- ATA_ID_SERNO_LEN
- ATA_ID_SPG
- ATA_ID_SWDMA_MODES
- ATA_ID_TRUSTED
- ATA_ID_UDMA_MODES
- ATA_ID_WORDS
- ATA_ID_WWN
- ATA_ID_WWN_LEN
- ATA_IOC_GET_IO32
- ATA_IOC_SET_IO32
- ATA_IRQ_BIT
- ATA_IRQ_TRAP
- ATA_LBA
- ATA_LFLAG_ASSUME_ATA
- ATA_LFLAG_ASSUME_CLASS
- ATA_LFLAG_ASSUME_SEMB
- ATA_LFLAG_CHANGED
- ATA_LFLAG_DISABLED
- ATA_LFLAG_NO_DB_DELAY
- ATA_LFLAG_NO_HRST
- ATA_LFLAG_NO_LPM
- ATA_LFLAG_NO_RETRY
- ATA_LFLAG_NO_SRST
- ATA_LFLAG_RST_ONCE
- ATA_LFLAG_SW_ACTIVITY
- ATA_LINK_ATTRS
- ATA_LINK_CLEAR_BEGIN
- ATA_LINK_CLEAR_END
- ATA_LINK_RESUME_TRIES
- ATA_LITER_EDGE
- ATA_LITER_HOST_FIRST
- ATA_LITER_PMP_FIRST
- ATA_LOG_DEVSLP_DETO
- ATA_LOG_DEVSLP_MDAT
- ATA_LOG_DEVSLP_MDAT_MASK
- ATA_LOG_DEVSLP_OFFSET
- ATA_LOG_DEVSLP_SIZE
- ATA_LOG_DEVSLP_VALID
- ATA_LOG_DEVSLP_VALID_MASK
- ATA_LOG_DIRECTORY
- ATA_LOG_IDENTIFY_DEVICE
- ATA_LOG_NCQ_NON_DATA
- ATA_LOG_NCQ_NON_DATA_ABORT_ALL
- ATA_LOG_NCQ_NON_DATA_ABORT_NCQ
- ATA_LOG_NCQ_NON_DATA_ABORT_NON_STREAMING
- ATA_LOG_NCQ_NON_DATA_ABORT_OFFSET
- ATA_LOG_NCQ_NON_DATA_ABORT_SELECTED
- ATA_LOG_NCQ_NON_DATA_ABORT_STREAMING
- ATA_LOG_NCQ_NON_DATA_SIZE
- ATA_LOG_NCQ_NON_DATA_SUBCMDS_OFFSET
- ATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OFFSET
- ATA_LOG_NCQ_NON_DATA_ZAC_MGMT_OUT
- ATA_LOG_NCQ_PRIO_OFFSET
- ATA_LOG_NCQ_SEND_RECV
- ATA_LOG_NCQ_SEND_RECV_DSM_OFFSET
- ATA_LOG_NCQ_SEND_RECV_DSM_TRIM
- ATA_LOG_NCQ_SEND_RECV_RD_LOG_OFFSET
- ATA_LOG_NCQ_SEND_RECV_RD_LOG_SUPPORTED
- ATA_LOG_NCQ_SEND_RECV_SIZE
- ATA_LOG_NCQ_SEND_RECV_SUBCMDS_DSM
- ATA_LOG_NCQ_SEND_RECV_SUBCMDS_OFFSET
- ATA_LOG_NCQ_SEND_RECV_WR_LOG_OFFSET
- ATA_LOG_NCQ_SEND_RECV_WR_LOG_SUPPORTED
- ATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_IN_SUPPORTED
- ATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OFFSET
- ATA_LOG_NCQ_SEND_RECV_ZAC_MGMT_OUT_SUPPORTED
- ATA_LOG_SATA_NCQ
- ATA_LOG_SATA_SETTINGS
- ATA_LOG_SECURITY
- ATA_LOG_ZONED_INFORMATION
- ATA_LPM_EMPTY
- ATA_LPM_HIPM
- ATA_LPM_MAX_POWER
- ATA_LPM_MED_POWER
- ATA_LPM_MED_POWER_WITH_DIPM
- ATA_LPM_MIN_POWER
- ATA_LPM_MIN_POWER_WITH_PARTIAL
- ATA_LPM_UNKNOWN
- ATA_LPM_WAKE_ONLY
- ATA_MASK_MWDMA
- ATA_MASK_PIO
- ATA_MASK_UDMA
- ATA_MAX_DEVICES
- ATA_MAX_PRD
- ATA_MAX_QUEUE
- ATA_MAX_SECTORS
- ATA_MAX_SECTORS_1024
- ATA_MAX_SECTORS_128
- ATA_MAX_SECTORS_LBA48
- ATA_MAX_SECTORS_TAPE
- ATA_MAX_TRIM_RNUM
- ATA_MC
- ATA_MCR
- ATA_MSG_CTL
- ATA_MSG_DRV
- ATA_MSG_ERR
- ATA_MSG_INFO
- ATA_MSG_INTR
- ATA_MSG_MALLOC
- ATA_MSG_PROBE
- ATA_MSG_WARN
- ATA_MWDMA0
- ATA_MWDMA1
- ATA_MWDMA12_ONLY
- ATA_MWDMA2
- ATA_MWDMA2_ONLY
- ATA_MWDMA3
- ATA_MWDMA4
- ATA_NCQ_SHT
- ATA_NDEBUG
- ATA_NIEN
- ATA_NR_MWDMA_MODES
- ATA_NR_PIO_MODES
- ATA_NR_UDMA_MODES
- ATA_OP_NULL
- ATA_PABX_I2S_MODE
- ATA_PABX_WI2S_MODE
- ATA_PCI_CTL_OFS
- ATA_PFLAG_EH_IN_PROGRESS
- ATA_PFLAG_EH_PENDING
- ATA_PFLAG_EXTERNAL
- ATA_PFLAG_FROZEN
- ATA_PFLAG_INITIALIZING
- ATA_PFLAG_INIT_GTM_VALID
- ATA_PFLAG_LOADING
- ATA_PFLAG_PIO32
- ATA_PFLAG_PIO32CHANGE
- ATA_PFLAG_PM_PENDING
- ATA_PFLAG_RECOVERED
- ATA_PFLAG_RESETTING
- ATA_PFLAG_SCSI_HOTPLUG
- ATA_PFLAG_SUSPENDED
- ATA_PFLAG_UNLOADED
- ATA_PFLAG_UNLOADING
- ATA_PIO0
- ATA_PIO1
- ATA_PIO2
- ATA_PIO3
- ATA_PIO4
- ATA_PIO4_ONLY
- ATA_PIO5
- ATA_PIO6
- ATA_PIO_SHT
- ATA_PORT_ATTRS
- ATA_PRD_EOT
- ATA_PRD_SZ
- ATA_PRD_TBL_SZ
- ATA_PRIMARY_IRQ
- ATA_PRIO_HIGH
- ATA_PRIV_MISC
- ATA_PRIV_PC
- ATA_PRIV_PM_RESUME
- ATA_PRIV_PM_SUSPEND
- ATA_PRIV_SENSE
- ATA_PRIV_TASKFILE
- ATA_PROBE_MAX_TRIES
- ATA_PROT_DMA
- ATA_PROT_FLAG_ATAPI
- ATA_PROT_FLAG_DMA
- ATA_PROT_FLAG_NCQ
- ATA_PROT_FLAG_PIO
- ATA_PROT_NCQ
- ATA_PROT_NCQ_NODATA
- ATA_PROT_NODATA
- ATA_PROT_PIO
- ATA_PROT_UNKNOWN
- ATA_QCFLAG_ACTIVE
- ATA_QCFLAG_CLEAR_EXCL
- ATA_QCFLAG_DMAMAP
- ATA_QCFLAG_EH_SCHEDULED
- ATA_QCFLAG_FAILED
- ATA_QCFLAG_IO
- ATA_QCFLAG_QUIET
- ATA_QCFLAG_RESULT_TF
- ATA_QCFLAG_RETRY
- ATA_QCFLAG_SENSE_VALID
- ATA_Q_TYPE_MASK
- ATA_Q_TYPE_NCQ
- ATA_Q_TYPE_UNTAGGED
- ATA_READID_POSTRESET
- ATA_REG_BYTEH
- ATA_REG_BYTEL
- ATA_REG_CMD
- ATA_REG_DATA
- ATA_REG_DEVICE
- ATA_REG_DEVSEL
- ATA_REG_ERR
- ATA_REG_ERROR_OFFSET
- ATA_REG_FEATURE
- ATA_REG_HCYL_OFFSET
- ATA_REG_IRQ
- ATA_REG_LBAH
- ATA_REG_LBAL
- ATA_REG_LBAM
- ATA_REG_LCYL_OFFSET
- ATA_REG_NSECT
- ATA_REG_STATUS
- ATA_REG_STATUS_OFFSET
- ATA_RESP_FIS_SIZE
- ATA_SC
- ATA_SCSI_RBUF_SIZE
- ATA_SECONDARY_IRQ
- ATA_SECT_SIZE
- ATA_SENSE
- ATA_SET_MAX_ADDR
- ATA_SET_MAX_FREEZE_LOCK
- ATA_SET_MAX_LOCK
- ATA_SET_MAX_PASSWD
- ATA_SET_MAX_PASSWD_DMA
- ATA_SET_MAX_UNLOCK
- ATA_SET_MAX_UNLOCK_DMA
- ATA_SH
- ATA_SHIFT_MWDMA
- ATA_SHIFT_PIO
- ATA_SHIFT_PRIO
- ATA_SHIFT_UDMA
- ATA_SHORT_PAUSE
- ATA_SHT_EMULATED
- ATA_SHT_THIS_ID
- ATA_SMART_ENABLE
- ATA_SMART_LBAH_PASS
- ATA_SMART_LBAM_PASS
- ATA_SMART_READ_THRESHOLDS
- ATA_SMART_READ_VALUES
- ATA_SN
- ATA_SRST
- ATA_STS_CMD
- ATA_SUBCMD_FPDMA_RECV_RD_LOG_DMA_EXT
- ATA_SUBCMD_FPDMA_RECV_ZAC_MGMT_IN
- ATA_SUBCMD_FPDMA_SEND_DSM
- ATA_SUBCMD_FPDMA_SEND_WR_LOG_DMA_EXT
- ATA_SUBCMD_NCQ_NON_DATA_ABORT_QUEUE
- ATA_SUBCMD_NCQ_NON_DATA_SET_FEATURES
- ATA_SUBCMD_NCQ_NON_DATA_ZAC_MGMT_OUT
- ATA_SUBCMD_NCQ_NON_DATA_ZERO_EXT
- ATA_SUBCMD_ZAC_MGMT_IN_REPORT_ZONES
- ATA_SUBCMD_ZAC_MGMT_OUT_CLOSE_ZONE
- ATA_SUBCMD_ZAC_MGMT_OUT_FINISH_ZONE
- ATA_SUBCMD_ZAC_MGMT_OUT_OPEN_ZONE
- ATA_SUBCMD_ZAC_MGMT_OUT_RESET_WRITE_POINTER
- ATA_SWDMA0
- ATA_SWDMA1
- ATA_SWDMA2
- ATA_SWDMA2_ONLY
- ATA_TAG_INTERNAL
- ATA_TAG_POISON
- ATA_TFLAG_DEVICE
- ATA_TFLAG_FUA
- ATA_TFLAG_ISADDR
- ATA_TFLAG_LBA
- ATA_TFLAG_LBA48
- ATA_TFLAG_POLLING
- ATA_TFLAG_WRITE
- ATA_TIMING_8BIT
- ATA_TIMING_ACT8B
- ATA_TIMING_ACTIVE
- ATA_TIMING_ALL
- ATA_TIMING_CYC8B
- ATA_TIMING_CYCLE
- ATA_TIMING_DMACK_HOLD
- ATA_TIMING_REC8B
- ATA_TIMING_RECOVER
- ATA_TIMING_SETUP
- ATA_TIMING_UDMA
- ATA_TMOUT_BOOT
- ATA_TMOUT_BOOT_QUICK
- ATA_TMOUT_FF_WAIT
- ATA_TMOUT_FF_WAIT_LONG
- ATA_TMOUT_INTERNAL_QUICK
- ATA_TMOUT_MAX_PARK
- ATA_TMOUT_PMP_SRST_WAIT
- ATA_TMOUT_SPURIOUS_PHY
- ATA_TRK0NF
- ATA_UDMA0
- ATA_UDMA1
- ATA_UDMA2
- ATA_UDMA24_ONLY
- ATA_UDMA3
- ATA_UDMA4
- ATA_UDMA5
- ATA_UDMA6
- ATA_UDMA7
- ATA_UDMA_MASK_40C
- ATA_UNC
- ATA_VERBOSE_DEBUG
- ATA_WAIT_AFTER_RESET
- ATBM8830_PROD_8830
- ATBM8830_PROD_8831
- ATC20K1
- ATC20K2
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
- ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
- ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT
- ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK
- ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT
- ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK
- ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK
- ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK
- ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK
- ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK
- ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK
- ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT
- ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK
- ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__BANK_SELECT_MASK
- ATCL2_0_ATC_L2_CNTL2__BANK_SELECT__SHIFT
- ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK
- ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK
- ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT
- ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK
- ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT
- ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK
- ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT
- ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK
- ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT
- ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK
- ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT
- ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
- ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK
- ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT
- ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK
- ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT
- ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK
- ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT
- ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK
- ATCL2_0_ATC_L2_MISC_CG__ENABLE__SHIFT
- ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
- ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT
- ATCL2_0_ATC_L2_MISC_CG__OFFDLY_MASK
- ATCL2_0_ATC_L2_MISC_CG__OFFDLY__SHIFT
- ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK
- ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT
- ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK
- ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT
- ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK
- ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT
- ATCL2_0_ATC_L2_STATUS3__BUSY_MASK
- ATCL2_0_ATC_L2_STATUS3__BUSY__SHIFT
- ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK
- ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT
- ATCL2_0_ATC_L2_STATUS__BUSY_MASK
- ATCL2_0_ATC_L2_STATUS__BUSY__SHIFT
- ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK
- ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT
- ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK
- ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT
- ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK
- ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK
- ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK
- ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK
- ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK
- ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK
- ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT
- ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK
- ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__BANK_SELECT_MASK
- ATCL2_1_ATC_L2_CNTL2__BANK_SELECT__SHIFT
- ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK
- ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK
- ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT
- ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK
- ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT
- ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK
- ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT
- ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK
- ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT
- ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK
- ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT
- ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
- ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK
- ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT
- ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK
- ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT
- ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK
- ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT
- ATCL2_1_ATC_L2_MISC_CG__ENABLE_MASK
- ATCL2_1_ATC_L2_MISC_CG__ENABLE__SHIFT
- ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
- ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT
- ATCL2_1_ATC_L2_MISC_CG__OFFDLY_MASK
- ATCL2_1_ATC_L2_MISC_CG__OFFDLY__SHIFT
- ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK
- ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT
- ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK
- ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT
- ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK
- ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT
- ATCL2_1_ATC_L2_STATUS3__BUSY_MASK
- ATCL2_1_ATC_L2_STATUS3__BUSY__SHIFT
- ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK
- ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT
- ATCL2_1_ATC_L2_STATUS__BUSY_MASK
- ATCL2_1_ATC_L2_STATUS__BUSY__SHIFT
- ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK
- ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT
- ATCLK_MCUISP_FREQUENCY
- ATCNONE
- ATCS_ADVERTISE_CAPS
- ATCS_DOCKED
- ATCS_FORCE_LOW_POWER
- ATCS_FUNCTION_GET_EXTERNAL_STATE
- ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION
- ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST
- ATCS_FUNCTION_SET_PCIE_BUS_WIDTH
- ATCS_FUNCTION_VERIFY_INTERFACE
- ATCS_GET_EXTERNAL_STATE_SUPPORTED
- ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED
- ATCS_PCIE_LINK_SPEED
- ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED
- ATCS_PERF_LEVEL_1
- ATCS_PERF_LEVEL_2
- ATCS_PERF_LEVEL_3
- ATCS_REMOVE
- ATCS_REQUEST_COMPLETE
- ATCS_REQUEST_IN_PROGRESS
- ATCS_REQUEST_REFUSED
- ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED
- ATCS_VALID_FLAGS_MASK
- ATCS_WAIT_FOR_COMPLETION
- ATC_040
- ATC_AHB_PROT_MASK
- ATC_ATC_INT_STS_REG_ADDRESS_ERROR
- ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
- ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
- ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
- ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
- ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
- ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK
- ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT
- ATC_ATS_CNTL__DEBUG_ECO_MASK
- ATC_ATS_CNTL__DEBUG_ECO__SHIFT
- ATC_ATS_CNTL__DISABLE_ATC_MASK
- ATC_ATS_CNTL__DISABLE_ATC__SHIFT
- ATC_ATS_CNTL__DISABLE_PASID_MASK
- ATC_ATS_CNTL__DISABLE_PASID__SHIFT
- ATC_ATS_CNTL__DISABLE_PRI_MASK
- ATC_ATS_CNTL__DISABLE_PRI__SHIFT
- ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK
- ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT
- ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK
- ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT
- ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK
- ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT
- ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK
- ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT
- ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK
- ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT
- ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK
- ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
- ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK
- ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT
- ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK
- ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT
- ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK
- ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT
- ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK
- ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT
- ATC_ATS_DEBUG__EXE_BIT_MASK
- ATC_ATS_DEBUG__EXE_BIT__SHIFT
- ATC_ATS_DEBUG__IDENT_RETURN_MASK
- ATC_ATS_DEBUG__IDENT_RETURN__SHIFT
- ATC_ATS_DEBUG__IGNORE_FED_MASK
- ATC_ATS_DEBUG__IGNORE_FED__SHIFT
- ATC_ATS_DEBUG__INVALIDATE_ALL_MASK
- ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT
- ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK
- ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT
- ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK
- ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT
- ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK
- ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT
- ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK
- ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT
- ATC_ATS_DEBUG__PRIV_BIT_MASK
- ATC_ATS_DEBUG__PRIV_BIT__SHIFT
- ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK
- ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT
- ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK
- ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT
- ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK
- ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT
- ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK
- ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT
- ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK
- ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT
- ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK
- ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT
- ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK
- ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT
- ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK
- ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT
- ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK
- ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT
- ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK
- ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT
- ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK
- ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT
- ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK
- ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT
- ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK
- ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT
- ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK
- ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT
- ATC_ATS_FAULT_STATUS_INFO2__VF_MASK
- ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK
- ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK
- ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK
- ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK
- ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK
- ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK
- ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK
- ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT
- ATC_ATS_FAULT_STATUS_INFO__VMID_MASK
- ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT
- ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK
- ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT
- ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK
- ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT
- ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK
- ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT
- ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK
- ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT
- ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK
- ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK
- ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT
- ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK
- ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT
- ATC_ATS_STATUS__BUSY_MASK
- ATC_ATS_STATUS__BUSY__SHIFT
- ATC_ATS_STATUS__CRASHED_MASK
- ATC_ATS_STATUS__CRASHED__SHIFT
- ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK
- ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT
- ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK
- ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT
- ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK
- ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK
- ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK
- ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT
- ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT
- ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK
- ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT
- ATC_AUTO
- ATC_BTSIZE
- ATC_BTSIZE_MAX
- ATC_BUSY
- ATC_CFG_OFFSET
- ATC_CTRLA_OFFSET
- ATC_CTRLB_OFFSET
- ATC_DADDR_OFFSET
- ATC_DCSIZE
- ATC_DCSIZE_1
- ATC_DCSIZE_128
- ATC_DCSIZE_16
- ATC_DCSIZE_256
- ATC_DCSIZE_32
- ATC_DCSIZE_4
- ATC_DCSIZE_64
- ATC_DCSIZE_8
- ATC_DCSIZE_MASK
- ATC_DEFAULT_CFG
- ATC_DEFAULT_CTRLB
- ATC_DIF
- ATC_DISABLED
- ATC_DMA_BUSWIDTHS
- ATC_DONE
- ATC_DPIP_BOUNDARY
- ATC_DPIP_HOLE
- ATC_DPIP_OFFSET
- ATC_DSCR_IF
- ATC_DSCR_OFFSET
- ATC_DST_ADDR_MODE_DECR
- ATC_DST_ADDR_MODE_FIXED
- ATC_DST_ADDR_MODE_INCR
- ATC_DST_ADDR_MODE_MASK
- ATC_DST_DSCR_DIS
- ATC_DST_H2SEL
- ATC_DST_H2SEL_HW
- ATC_DST_H2SEL_SW
- ATC_DST_PER
- ATC_DST_PER_MSB
- ATC_DST_PIP
- ATC_DST_REP
- ATC_DST_WIDTH
- ATC_DST_WIDTH_BYTE
- ATC_DST_WIDTH_HALFWORD
- ATC_DST_WIDTH_MASK
- ATC_DST_WIDTH_WORD
- ATC_FC_MASK
- ATC_FC_MEM2MEM
- ATC_FC_MEM2PER
- ATC_FC_MEM2PER_PER
- ATC_FC_PER2MEM
- ATC_FC_PER2MEM_PER
- ATC_FC_PER2PER
- ATC_FC_PER2PER_DSTPER
- ATC_FC_PER2PER_SRCPER
- ATC_FIFOCFG_ENOUGHSPACE
- ATC_FIFOCFG_HALFFIFO
- ATC_FIFOCFG_LARGESTBURST
- ATC_FIFOCFG_MASK
- ATC_HASH
- ATC_IEN
- ATC_INVALID
- ATC_INV_SIZE_ALL
- ATC_IS_CYCLIC
- ATC_IS_ERROR
- ATC_IS_PAUSED
- ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK
- ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT
- ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK
- ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT
- ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK
- ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT
- ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK
- ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT
- ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK
- ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT
- ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK
- ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT
- ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK
- ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT
- ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK
- ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT
- ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK
- ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT
- ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK
- ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT
- ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK
- ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT
- ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK
- ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT
- ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK
- ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT
- ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK
- ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT
- ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK
- ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT
- ATC_L1RD_STATUS__BAD_NEED_ATS_MASK
- ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT
- ATC_L1RD_STATUS__BUSY_MASK
- ATC_L1RD_STATUS__BUSY__SHIFT
- ATC_L1RD_STATUS__CAM_INDEX_MASK
- ATC_L1RD_STATUS__CAM_INDEX__SHIFT
- ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK
- ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT
- ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK
- ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT
- ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK
- ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT
- ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK
- ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT
- ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK
- ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT
- ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK
- ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT
- ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK
- ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT
- ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK
- ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT
- ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK
- ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT
- ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK
- ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT
- ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK
- ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT
- ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK
- ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT
- ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK
- ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT
- ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK
- ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT
- ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK
- ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT
- ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK
- ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT
- ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK
- ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT
- ATC_L1WR_STATUS__BAD_NEED_ATS_MASK
- ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT
- ATC_L1WR_STATUS__BUSY_MASK
- ATC_L1WR_STATUS__BUSY__SHIFT
- ATC_L1WR_STATUS__CAM_INDEX_MASK
- ATC_L1WR_STATUS__CAM_INDEX__SHIFT
- ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK
- ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT
- ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK
- ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT
- ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK
- ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT
- ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK
- ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT
- ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK
- ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT
- ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK
- ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT
- ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK
- ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT
- ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK
- ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT
- ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK
- ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT
- ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK
- ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT
- ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK
- ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT
- ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK
- ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT
- ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK
- ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT
- ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
- ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- ATC_L2_CNTL2__BANK_SELECT_MASK
- ATC_L2_CNTL2__BANK_SELECT__SHIFT
- ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK
- ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK
- ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT
- ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK
- ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT
- ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
- ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
- ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK
- ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT
- ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK
- ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT
- ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK
- ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT
- ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK
- ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT
- ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK
- ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT
- ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK
- ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT
- ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK
- ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT
- ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK
- ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT
- ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK
- ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT
- ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK
- ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT
- ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
- ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK
- ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT
- ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK
- ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT
- ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK
- ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT
- ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK
- ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT
- ATC_L2_DEBUG2__DEBUG_ECO_MASK
- ATC_L2_DEBUG2__DEBUG_ECO__SHIFT
- ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK
- ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT
- ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK
- ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK
- ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT
- ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
- ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
- ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK
- ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT
- ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK
- ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT
- ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK
- ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT
- ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK
- ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT
- ATC_L2_DEBUG2__INVALIDATE_ALL_MASK
- ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT
- ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK
- ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT
- ATC_L2_DEBUG__CACHE_INDEX_MASK
- ATC_L2_DEBUG__CACHE_INDEX__SHIFT
- ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK
- ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT
- ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK
- ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT
- ATC_L2_DEBUG__CACHE_READ_MASK
- ATC_L2_DEBUG__CACHE_READ__SHIFT
- ATC_L2_DEBUG__CACHE_SELECT_MASK
- ATC_L2_DEBUG__CACHE_SELECT__SHIFT
- ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK
- ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT
- ATC_L2_DEBUG__CREDITS_L2_ATS_MASK
- ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT
- ATC_L2_DEBUG__L2_MEM_SELECT_MASK
- ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT
- ATC_L2_MEM_POWER_LS__LS_HOLD_MASK
- ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT
- ATC_L2_MEM_POWER_LS__LS_SETUP_MASK
- ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT
- ATC_L2_MISC_CG__ENABLE_MASK
- ATC_L2_MISC_CG__ENABLE__SHIFT
- ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
- ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT
- ATC_L2_MISC_CG__OFFDLY_MASK
- ATC_L2_MISC_CG__OFFDLY__SHIFT
- ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK
- ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
- ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK
- ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
- ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
- ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
- ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK
- ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
- ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK
- ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
- ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
- ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
- ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
- ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
- ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK
- ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT
- ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK
- ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT
- ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK
- ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT
- ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK
- ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT
- ATC_L2_STATUS__BUSY_MASK
- ATC_L2_STATUS__BUSY__SHIFT
- ATC_L2_STATUS__PARITY_ERROR_INFO_MASK
- ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT
- ATC_LOCK_B
- ATC_LOCK_IF
- ATC_LOCK_IF_L
- ATC_LOCK_IF_L_BUFFER
- ATC_LOCK_IF_L_CHUNK
- ATC_MAT
- ATC_MAT_MACTAB
- ATC_MAX_DSCR_TRIALS
- ATC_MISC_CG
- ATC_MISC_CG__ENABLE_MASK
- ATC_MISC_CG__ENABLE__SHIFT
- ATC_MISC_CG__MEM_LS_ENABLE_MASK
- ATC_MISC_CG__MEM_LS_ENABLE__SHIFT
- ATC_MISC_CG__OFFDLY_MASK
- ATC_MISC_CG__OFFDLY__SHIFT
- ATC_PERFCOUNTER0_CFG__CLEAR_MASK
- ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT
- ATC_PERFCOUNTER0_CFG__ENABLE_MASK
- ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT
- ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK
- ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK
- ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- ATC_PERFCOUNTER1_CFG__CLEAR_MASK
- ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT
- ATC_PERFCOUNTER1_CFG__ENABLE_MASK
- ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT
- ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK
- ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK
- ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- ATC_PERFCOUNTER2_CFG__CLEAR_MASK
- ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT
- ATC_PERFCOUNTER2_CFG__ENABLE_MASK
- ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT
- ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK
- ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
- ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
- ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
- ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK
- ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
- ATC_PERFCOUNTER3_CFG__CLEAR_MASK
- ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT
- ATC_PERFCOUNTER3_CFG__ENABLE_MASK
- ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT
- ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK
- ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
- ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
- ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
- ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK
- ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
- ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- ATC_PERFCOUNTER_HI__COUNTER_HI_MASK
- ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- ATC_PERFCOUNTER_LO__COUNTER_LO_MASK
- ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- ATC_PER_MSB
- ATC_REG_ATC_INIT_ARRAY
- ATC_REG_ATC_INIT_DONE
- ATC_REG_ATC_INT_STS_CLR
- ATC_REG_ATC_PRTY_MASK
- ATC_REG_ATC_PRTY_STS
- ATC_REG_ATC_PRTY_STS_CLR
- ATC_REG_TO_SRC_WIDTH
- ATC_SADDR_OFFSET
- ATC_SCSIZE
- ATC_SCSIZE_1
- ATC_SCSIZE_128
- ATC_SCSIZE_16
- ATC_SCSIZE_256
- ATC_SCSIZE_32
- ATC_SCSIZE_4
- ATC_SCSIZE_64
- ATC_SCSIZE_8
- ATC_SCSIZE_MASK
- ATC_SIF
- ATC_SOD
- ATC_SPIP_BOUNDARY
- ATC_SPIP_HOLE
- ATC_SPIP_OFFSET
- ATC_SRCH_END
- ATC_SRCH_HIT
- ATC_SRC_ADDR_MODE_DECR
- ATC_SRC_ADDR_MODE_FIXED
- ATC_SRC_ADDR_MODE_INCR
- ATC_SRC_ADDR_MODE_MASK
- ATC_SRC_DSCR_DIS
- ATC_SRC_H2SEL
- ATC_SRC_H2SEL_HW
- ATC_SRC_H2SEL_SW
- ATC_SRC_PER
- ATC_SRC_PER_MSB
- ATC_SRC_PIP
- ATC_SRC_REP
- ATC_SRC_WIDTH
- ATC_SRC_WIDTH_BYTE
- ATC_SRC_WIDTH_HALFWORD
- ATC_SRC_WIDTH_MASK
- ATC_SRC_WIDTH_WORD
- ATC_STATUS_OFF
- ATC_STATUS_ON
- ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT
- ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK
- ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT
- ATC_VMID0_PASID_MAPPING
- ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID0_PASID_MAPPING__PASID_MASK
- ATC_VMID0_PASID_MAPPING__PASID__SHIFT
- ATC_VMID0_PASID_MAPPING__VALID_MASK
- ATC_VMID0_PASID_MAPPING__VALID__SHIFT
- ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID10_PASID_MAPPING__PASID_MASK
- ATC_VMID10_PASID_MAPPING__PASID__SHIFT
- ATC_VMID10_PASID_MAPPING__VALID_MASK
- ATC_VMID10_PASID_MAPPING__VALID__SHIFT
- ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID11_PASID_MAPPING__PASID_MASK
- ATC_VMID11_PASID_MAPPING__PASID__SHIFT
- ATC_VMID11_PASID_MAPPING__VALID_MASK
- ATC_VMID11_PASID_MAPPING__VALID__SHIFT
- ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID12_PASID_MAPPING__PASID_MASK
- ATC_VMID12_PASID_MAPPING__PASID__SHIFT
- ATC_VMID12_PASID_MAPPING__VALID_MASK
- ATC_VMID12_PASID_MAPPING__VALID__SHIFT
- ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID13_PASID_MAPPING__PASID_MASK
- ATC_VMID13_PASID_MAPPING__PASID__SHIFT
- ATC_VMID13_PASID_MAPPING__VALID_MASK
- ATC_VMID13_PASID_MAPPING__VALID__SHIFT
- ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID14_PASID_MAPPING__PASID_MASK
- ATC_VMID14_PASID_MAPPING__PASID__SHIFT
- ATC_VMID14_PASID_MAPPING__VALID_MASK
- ATC_VMID14_PASID_MAPPING__VALID__SHIFT
- ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID15_PASID_MAPPING__PASID_MASK
- ATC_VMID15_PASID_MAPPING__PASID__SHIFT
- ATC_VMID15_PASID_MAPPING__VALID_MASK
- ATC_VMID15_PASID_MAPPING__VALID__SHIFT
- ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID16_PASID_MAPPING__PASID_MASK
- ATC_VMID16_PASID_MAPPING__PASID__SHIFT
- ATC_VMID16_PASID_MAPPING__VALID_MASK
- ATC_VMID16_PASID_MAPPING__VALID__SHIFT
- ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID17_PASID_MAPPING__PASID_MASK
- ATC_VMID17_PASID_MAPPING__PASID__SHIFT
- ATC_VMID17_PASID_MAPPING__VALID_MASK
- ATC_VMID17_PASID_MAPPING__VALID__SHIFT
- ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID18_PASID_MAPPING__PASID_MASK
- ATC_VMID18_PASID_MAPPING__PASID__SHIFT
- ATC_VMID18_PASID_MAPPING__VALID_MASK
- ATC_VMID18_PASID_MAPPING__VALID__SHIFT
- ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID19_PASID_MAPPING__PASID_MASK
- ATC_VMID19_PASID_MAPPING__PASID__SHIFT
- ATC_VMID19_PASID_MAPPING__VALID_MASK
- ATC_VMID19_PASID_MAPPING__VALID__SHIFT
- ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID1_PASID_MAPPING__PASID_MASK
- ATC_VMID1_PASID_MAPPING__PASID__SHIFT
- ATC_VMID1_PASID_MAPPING__VALID_MASK
- ATC_VMID1_PASID_MAPPING__VALID__SHIFT
- ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID20_PASID_MAPPING__PASID_MASK
- ATC_VMID20_PASID_MAPPING__PASID__SHIFT
- ATC_VMID20_PASID_MAPPING__VALID_MASK
- ATC_VMID20_PASID_MAPPING__VALID__SHIFT
- ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID21_PASID_MAPPING__PASID_MASK
- ATC_VMID21_PASID_MAPPING__PASID__SHIFT
- ATC_VMID21_PASID_MAPPING__VALID_MASK
- ATC_VMID21_PASID_MAPPING__VALID__SHIFT
- ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID22_PASID_MAPPING__PASID_MASK
- ATC_VMID22_PASID_MAPPING__PASID__SHIFT
- ATC_VMID22_PASID_MAPPING__VALID_MASK
- ATC_VMID22_PASID_MAPPING__VALID__SHIFT
- ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID23_PASID_MAPPING__PASID_MASK
- ATC_VMID23_PASID_MAPPING__PASID__SHIFT
- ATC_VMID23_PASID_MAPPING__VALID_MASK
- ATC_VMID23_PASID_MAPPING__VALID__SHIFT
- ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID24_PASID_MAPPING__PASID_MASK
- ATC_VMID24_PASID_MAPPING__PASID__SHIFT
- ATC_VMID24_PASID_MAPPING__VALID_MASK
- ATC_VMID24_PASID_MAPPING__VALID__SHIFT
- ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID25_PASID_MAPPING__PASID_MASK
- ATC_VMID25_PASID_MAPPING__PASID__SHIFT
- ATC_VMID25_PASID_MAPPING__VALID_MASK
- ATC_VMID25_PASID_MAPPING__VALID__SHIFT
- ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID26_PASID_MAPPING__PASID_MASK
- ATC_VMID26_PASID_MAPPING__PASID__SHIFT
- ATC_VMID26_PASID_MAPPING__VALID_MASK
- ATC_VMID26_PASID_MAPPING__VALID__SHIFT
- ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID27_PASID_MAPPING__PASID_MASK
- ATC_VMID27_PASID_MAPPING__PASID__SHIFT
- ATC_VMID27_PASID_MAPPING__VALID_MASK
- ATC_VMID27_PASID_MAPPING__VALID__SHIFT
- ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID28_PASID_MAPPING__PASID_MASK
- ATC_VMID28_PASID_MAPPING__PASID__SHIFT
- ATC_VMID28_PASID_MAPPING__VALID_MASK
- ATC_VMID28_PASID_MAPPING__VALID__SHIFT
- ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID29_PASID_MAPPING__PASID_MASK
- ATC_VMID29_PASID_MAPPING__PASID__SHIFT
- ATC_VMID29_PASID_MAPPING__VALID_MASK
- ATC_VMID29_PASID_MAPPING__VALID__SHIFT
- ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID2_PASID_MAPPING__PASID_MASK
- ATC_VMID2_PASID_MAPPING__PASID__SHIFT
- ATC_VMID2_PASID_MAPPING__VALID_MASK
- ATC_VMID2_PASID_MAPPING__VALID__SHIFT
- ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID30_PASID_MAPPING__PASID_MASK
- ATC_VMID30_PASID_MAPPING__PASID__SHIFT
- ATC_VMID30_PASID_MAPPING__VALID_MASK
- ATC_VMID30_PASID_MAPPING__VALID__SHIFT
- ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID31_PASID_MAPPING__PASID_MASK
- ATC_VMID31_PASID_MAPPING__PASID__SHIFT
- ATC_VMID31_PASID_MAPPING__VALID_MASK
- ATC_VMID31_PASID_MAPPING__VALID__SHIFT
- ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID3_PASID_MAPPING__PASID_MASK
- ATC_VMID3_PASID_MAPPING__PASID__SHIFT
- ATC_VMID3_PASID_MAPPING__VALID_MASK
- ATC_VMID3_PASID_MAPPING__VALID__SHIFT
- ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID4_PASID_MAPPING__PASID_MASK
- ATC_VMID4_PASID_MAPPING__PASID__SHIFT
- ATC_VMID4_PASID_MAPPING__VALID_MASK
- ATC_VMID4_PASID_MAPPING__VALID__SHIFT
- ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID5_PASID_MAPPING__PASID_MASK
- ATC_VMID5_PASID_MAPPING__PASID__SHIFT
- ATC_VMID5_PASID_MAPPING__VALID_MASK
- ATC_VMID5_PASID_MAPPING__VALID__SHIFT
- ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID6_PASID_MAPPING__PASID_MASK
- ATC_VMID6_PASID_MAPPING__PASID__SHIFT
- ATC_VMID6_PASID_MAPPING__VALID_MASK
- ATC_VMID6_PASID_MAPPING__VALID__SHIFT
- ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID7_PASID_MAPPING__PASID_MASK
- ATC_VMID7_PASID_MAPPING__PASID__SHIFT
- ATC_VMID7_PASID_MAPPING__VALID_MASK
- ATC_VMID7_PASID_MAPPING__VALID__SHIFT
- ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID8_PASID_MAPPING__PASID_MASK
- ATC_VMID8_PASID_MAPPING__PASID__SHIFT
- ATC_VMID8_PASID_MAPPING__VALID_MASK
- ATC_VMID8_PASID_MAPPING__VALID__SHIFT
- ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK
- ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT
- ATC_VMID9_PASID_MAPPING__PASID_MASK
- ATC_VMID9_PASID_MAPPING__PASID__SHIFT
- ATC_VMID9_PASID_MAPPING__VALID_MASK
- ATC_VMID9_PASID_MAPPING__VALID__SHIFT
- ATC_VMID_PASID_MAPPING_PASID_MASK
- ATC_VMID_PASID_MAPPING_PASID_SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK
- ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT
- ATC_VMID_PASID_MAPPING_VALID_MASK
- ATC_VMID_PASID_MAPPING_VALID_SHIFT
- ATC_VM_APERTURE0_CNTL
- ATC_VM_APERTURE0_CNTL2
- ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK
- ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT
- ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK
- ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT
- ATC_VM_APERTURE0_HIGH_ADDR
- ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK
- ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT
- ATC_VM_APERTURE0_LOW_ADDR
- ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK
- ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT
- ATC_VM_APERTURE1_CNTL
- ATC_VM_APERTURE1_CNTL2
- ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK
- ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT
- ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK
- ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT
- ATC_VM_APERTURE1_HIGH_ADDR
- ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK
- ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT
- ATC_VM_APERTURE1_LOW_ADDR
- ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK
- ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT
- ATDFCODE
- ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK
- ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT
- ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK
- ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT
- ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK
- ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT
- ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK
- ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT
- ATDONE
- ATEN
- ATENINTL_DEVICE_ID_UC2322
- ATENINTL_DEVICE_ID_UC2324
- ATEN_PRODUCT_ID
- ATEN_PRODUCT_ID2
- ATEN_PRODUCT_UC232B
- ATEN_PRODUCT_UC485
- ATEN_VENDOR_ID
- ATEN_VENDOR_ID2
- ATEN_VERSION
- ATE_BAR
- ATE_CO
- ATE_PFNSHIFT
- ATE_PREC
- ATE_PREF
- ATE_RMFSHIFT
- ATE_TIDSHIFT
- ATE_V
- ATF_COM
- ATF_DONTPUB
- ATF_NETMASK
- ATF_PERM
- ATF_PUBL
- ATF_USETRAILERS
- ATH10K_10_2_TX_STATS_OFFSET
- ATH10K_AHB_AXI_BUS_HALT_TIMEOUT
- ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK
- ATH10K_AHB_GCC_FEPLL_PLL_DIV
- ATH10K_AHB_TCSR_WCSS0_HALTACK
- ATH10K_AHB_TCSR_WCSS0_HALTREQ
- ATH10K_AHB_TCSR_WCSS1_HALTACK
- ATH10K_AHB_TCSR_WCSS1_HALTREQ
- ATH10K_AHB_TCSR_WIFI0_GLB_CFG
- ATH10K_AHB_TCSR_WIFI1_GLB_CFG
- ATH10K_AHB_WIFI_SCRATCH_5_REG
- ATH10K_AHB_WLAN_CORE_ID_REG
- ATH10K_AIRTIME_WEIGHT_MULTIPLIER
- ATH10K_AMPDU_SUBFRM_NUM_10
- ATH10K_AMPDU_SUBFRM_NUM_20
- ATH10K_AMPDU_SUBFRM_NUM_30
- ATH10K_AMPDU_SUBFRM_NUM_40
- ATH10K_AMPDU_SUBFRM_NUM_50
- ATH10K_AMPDU_SUBFRM_NUM_60
- ATH10K_AMPDU_SUBFRM_NUM_MAX
- ATH10K_AMPDU_SUBFRM_NUM_MORE
- ATH10K_AMSDU_SUBFRM_NUM_1
- ATH10K_AMSDU_SUBFRM_NUM_2
- ATH10K_AMSDU_SUBFRM_NUM_3
- ATH10K_AMSDU_SUBFRM_NUM_4
- ATH10K_AMSDU_SUBFRM_NUM_MAX
- ATH10K_AMSDU_SUBFRM_NUM_MORE
- ATH10K_BD_IE_BOARD
- ATH10K_BD_IE_BOARD_DATA
- ATH10K_BD_IE_BOARD_EXT
- ATH10K_BD_IE_BOARD_NAME
- ATH10K_BEACON_SCHEDULED
- ATH10K_BEACON_SENDING
- ATH10K_BEACON_SENT
- ATH10K_BMI_BOARD_ID_FROM_OTP_LSB
- ATH10K_BMI_BOARD_ID_FROM_OTP_MASK
- ATH10K_BMI_BOARD_ID_STATUS_MASK
- ATH10K_BMI_CHIP_ID_FROM_OTP_LSB
- ATH10K_BMI_CHIP_ID_FROM_OTP_MASK
- ATH10K_BMI_EBOARD_ID_STATUS_MASK
- ATH10K_BMI_EXT_BOARD_ID_SUPPORT
- ATH10K_BOARD_API2_FILE
- ATH10K_BOARD_MAGIC
- ATH10K_BUS_AHB
- ATH10K_BUS_PCI
- ATH10K_BUS_SDIO
- ATH10K_BUS_SNOC
- ATH10K_BUS_USB
- ATH10K_BW_NUM
- ATH10K_CAC_RUNNING
- ATH10K_CAL_MODE_DT
- ATH10K_CAL_MODE_EEPROM
- ATH10K_CAL_MODE_FILE
- ATH10K_CAL_MODE_OTP
- ATH10K_CONNECTION_LOSS_HZ
- ATH10K_COUNTER_TYPE_BYTES
- ATH10K_COUNTER_TYPE_MAX
- ATH10K_COUNTER_TYPE_PKTS
- ATH10K_CRYPT_MODE_HW
- ATH10K_CRYPT_MODE_SW
- ATH10K_DBGLOG_CFG_LOG_LVL_LSB
- ATH10K_DBGLOG_CFG_LOG_LVL_MASK
- ATH10K_DBGLOG_CFG_REPORTING_ENABLE_LSB
- ATH10K_DBGLOG_CFG_REPORTING_ENABLE_MASK
- ATH10K_DBGLOG_CFG_REPORT_SIZE_LSB
- ATH10K_DBGLOG_CFG_REPORT_SIZE_MASK
- ATH10K_DBGLOG_CFG_RESOLUTION_LSB
- ATH10K_DBGLOG_CFG_RESOLUTION_MASK
- ATH10K_DBGLOG_CFG_VAP_LOG_LSB
- ATH10K_DBGLOG_CFG_VAP_LOG_MASK
- ATH10K_DBGLOG_LEVEL_ERR
- ATH10K_DBGLOG_LEVEL_INFO
- ATH10K_DBGLOG_LEVEL_VERBOSE
- ATH10K_DBGLOG_LEVEL_WARN
- ATH10K_DBG_AGGR_MODE_AUTO
- ATH10K_DBG_AGGR_MODE_MANUAL
- ATH10K_DBG_AGGR_MODE_MAX
- ATH10K_DBG_AHB
- ATH10K_DBG_ANY
- ATH10K_DBG_BMI
- ATH10K_DBG_BOOT
- ATH10K_DBG_DATA
- ATH10K_DBG_HTC
- ATH10K_DBG_HTT
- ATH10K_DBG_HTT_DUMP
- ATH10K_DBG_MAC
- ATH10K_DBG_MGMT
- ATH10K_DBG_PCI
- ATH10K_DBG_PCI_DUMP
- ATH10K_DBG_PCI_PS
- ATH10K_DBG_QMI
- ATH10K_DBG_REGULATORY
- ATH10K_DBG_SDIO
- ATH10K_DBG_SDIO_DUMP
- ATH10K_DBG_SNOC
- ATH10K_DBG_TESTMODE
- ATH10K_DBG_USB
- ATH10K_DBG_USB_BULK
- ATH10K_DBG_WMI
- ATH10K_DBG_WMI_PRINT
- ATH10K_DEBUG_CAL_DATA_LEN
- ATH10K_DEBUG_HTT_STATS_INTERVAL
- ATH10K_DEFAULT_ATIM
- ATH10K_DEFAULT_NOISE_FLOOR
- ATH10K_DEV_TYPE_HL
- ATH10K_DEV_TYPE_LL
- ATH10K_DFS_POOL_STAT
- ATH10K_DFS_STAT
- ATH10K_DFS_STAT_INC
- ATH10K_DIAG_TRANSFER_LIMIT
- ATH10K_ENABLE_FW_LOG_CE
- ATH10K_ENABLE_FW_LOG_DIAG
- ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL
- ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF
- ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON
- ATH10K_FIRMWARE_MAGIC
- ATH10K_FIRMWARE_MODE_NORMAL
- ATH10K_FIRMWARE_MODE_UTF
- ATH10K_FLAG_BTCOEX
- ATH10K_FLAG_CORE_REGISTERED
- ATH10K_FLAG_CRASH_FLUSH
- ATH10K_FLAG_HW_CRYPTO_DISABLED
- ATH10K_FLAG_PEER_STATS
- ATH10K_FLAG_RAW_MODE
- ATH10K_FLUSH_TIMEOUT_HZ
- ATH10K_FRAGMT_THRESHOLD_MAX
- ATH10K_FRAGMT_THRESHOLD_MIN
- ATH10K_FW_API2_FILE
- ATH10K_FW_API3_FILE
- ATH10K_FW_API4_FILE
- ATH10K_FW_API5_FILE
- ATH10K_FW_API6_FILE
- ATH10K_FW_API_MAX
- ATH10K_FW_API_MIN
- ATH10K_FW_CRASH_DUMP_CE_DATA
- ATH10K_FW_CRASH_DUMP_MAX
- ATH10K_FW_CRASH_DUMP_RAM_DATA
- ATH10K_FW_CRASH_DUMP_REGISTERS
- ATH10K_FW_CRASH_DUMP_VERSION
- ATH10K_FW_DIR
- ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST
- ATH10K_FW_FEATURE_BTCOEX_PARAM
- ATH10K_FW_FEATURE_COUNT
- ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX
- ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX
- ATH10K_FW_FEATURE_IGNORE_OTP_RESULT
- ATH10K_FW_FEATURE_MFP_SUPPORT
- ATH10K_FW_FEATURE_MGMT_TX_BY_REF
- ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT
- ATH10K_FW_FEATURE_NON_BMI
- ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING
- ATH10K_FW_FEATURE_NO_P2P
- ATH10K_FW_FEATURE_NO_PS
- ATH10K_FW_FEATURE_PEER_FIXED_RATE
- ATH10K_FW_FEATURE_PEER_FLOW_CONTROL
- ATH10K_FW_FEATURE_RAW_MODE_SUPPORT
- ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL
- ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR
- ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA
- ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT
- ATH10K_FW_FEATURE_WMI_10X
- ATH10K_FW_FEATURE_WMI_10_2
- ATH10K_FW_FEATURE_WOWLAN_SUPPORT
- ATH10K_FW_FILE_BASE
- ATH10K_FW_HTT_OP_VERSION_10_1
- ATH10K_FW_HTT_OP_VERSION_10_4
- ATH10K_FW_HTT_OP_VERSION_MAIN
- ATH10K_FW_HTT_OP_VERSION_MAX
- ATH10K_FW_HTT_OP_VERSION_TLV
- ATH10K_FW_HTT_OP_VERSION_UNSET
- ATH10K_FW_IE_FEATURES
- ATH10K_FW_IE_FW_CODE_SWAP_IMAGE
- ATH10K_FW_IE_FW_IMAGE
- ATH10K_FW_IE_FW_VERSION
- ATH10K_FW_IE_HTT_OP_VERSION
- ATH10K_FW_IE_OTP_IMAGE
- ATH10K_FW_IE_TIMESTAMP
- ATH10K_FW_IE_WMI_OP_VERSION
- ATH10K_FW_SKIPPED_RATE_CTRL
- ATH10K_FW_STATS_BUF_SIZE
- ATH10K_FW_UTF_API2_FILE
- ATH10K_FW_UTF_FILE
- ATH10K_FW_UTF_FILE_BASE
- ATH10K_FW_WMI_OP_VERSION_10_1
- ATH10K_FW_WMI_OP_VERSION_10_2
- ATH10K_FW_WMI_OP_VERSION_10_2_4
- ATH10K_FW_WMI_OP_VERSION_10_4
- ATH10K_FW_WMI_OP_VERSION_MAIN
- ATH10K_FW_WMI_OP_VERSION_MAX
- ATH10K_FW_WMI_OP_VERSION_TLV
- ATH10K_FW_WMI_OP_VERSION_UNSET
- ATH10K_GCC_REG_BASE
- ATH10K_GCC_REG_SIZE
- ATH10K_GI_NUM
- ATH10K_HIF_GMBOX_BASE_ADDR
- ATH10K_HIF_GMBOX_WIDTH
- ATH10K_HIF_MBOX0_EXT_BASE_ADDR
- ATH10K_HIF_MBOX0_EXT_WIDTH
- ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0
- ATH10K_HIF_MBOX1_EXT_WIDTH
- ATH10K_HIF_MBOX_BASE_ADDR
- ATH10K_HIF_MBOX_BLOCK_SIZE
- ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE
- ATH10K_HIF_MBOX_NUM_MAX
- ATH10K_HIF_MBOX_TOT_WIDTH
- ATH10K_HIF_MBOX_WIDTH
- ATH10K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL
- ATH10K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE
- ATH10K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK
- ATH10K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH
- ATH10K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF
- ATH10K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS
- ATH10K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY
- ATH10K_HTC_CONN_SVC_STATUS_FAILED
- ATH10K_HTC_CONN_SVC_STATUS_NOT_FOUND
- ATH10K_HTC_CONN_SVC_STATUS_NO_MORE_EP
- ATH10K_HTC_CONN_SVC_STATUS_NO_RESOURCES
- ATH10K_HTC_CONN_SVC_STATUS_SUCCESS
- ATH10K_HTC_CONN_SVC_TIMEOUT_HZ
- ATH10K_HTC_CONTROL_BUFFER_SIZE
- ATH10K_HTC_EP_0
- ATH10K_HTC_EP_1
- ATH10K_HTC_EP_2
- ATH10K_HTC_EP_3
- ATH10K_HTC_EP_4
- ATH10K_HTC_EP_5
- ATH10K_HTC_EP_6
- ATH10K_HTC_EP_7
- ATH10K_HTC_EP_8
- ATH10K_HTC_EP_COUNT
- ATH10K_HTC_EP_UNUSED
- ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK
- ATH10K_HTC_FLAG_BUNDLE_MASK
- ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE
- ATH10K_HTC_FLAG_SEND_BUNDLE
- ATH10K_HTC_FLAG_TRAILER_PRESENT
- ATH10K_HTC_MAILBOX
- ATH10K_HTC_MAILBOX_MASK
- ATH10K_HTC_MAX_CTRL_MSG_LEN
- ATH10K_HTC_MAX_LEN
- ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH
- ATH10K_HTC_MSG_CONNECT_SERVICE_ID
- ATH10K_HTC_MSG_CONNECT_SERVICE_RESP_ID
- ATH10K_HTC_MSG_READY_ID
- ATH10K_HTC_MSG_SEND_SUSPEND_COMPLETE
- ATH10K_HTC_MSG_SETUP_COMPLETE_EX_ID
- ATH10K_HTC_MSG_SETUP_COMPLETE_ID
- ATH10K_HTC_RECORD_CREDITS
- ATH10K_HTC_RECORD_LOOKAHEAD
- ATH10K_HTC_RECORD_LOOKAHEAD_BUNDLE
- ATH10K_HTC_RECORD_NULL
- ATH10K_HTC_SETUP_COMPLETE_FLAGS_RX_BNDL_EN
- ATH10K_HTC_SVC_GRP_HTT
- ATH10K_HTC_SVC_GRP_LAST
- ATH10K_HTC_SVC_GRP_NMI
- ATH10K_HTC_SVC_GRP_RSVD
- ATH10K_HTC_SVC_GRP_TEST
- ATH10K_HTC_SVC_GRP_WMI
- ATH10K_HTC_SVC_ID_HTT_DATA2_MSG
- ATH10K_HTC_SVC_ID_HTT_DATA3_MSG
- ATH10K_HTC_SVC_ID_HTT_DATA_MSG
- ATH10K_HTC_SVC_ID_HTT_LOG_MSG
- ATH10K_HTC_SVC_ID_NMI_CONTROL
- ATH10K_HTC_SVC_ID_NMI_DATA
- ATH10K_HTC_SVC_ID_RESERVED
- ATH10K_HTC_SVC_ID_RSVD_CTRL
- ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS
- ATH10K_HTC_SVC_ID_UNUSED
- ATH10K_HTC_SVC_ID_WMI_CONTROL
- ATH10K_HTC_SVC_ID_WMI_DATA_BE
- ATH10K_HTC_SVC_ID_WMI_DATA_BK
- ATH10K_HTC_SVC_ID_WMI_DATA_VI
- ATH10K_HTC_SVC_ID_WMI_DATA_VO
- ATH10K_HTC_VERSION_2P0
- ATH10K_HTC_VERSION_2P1
- ATH10K_HTC_WAIT_TIMEOUT_HZ
- ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT
- ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT
- ATH10K_HTT_MAX_NUM_REFILL
- ATH10K_HTT_TXRX_PEER_SECURITY_MAX
- ATH10K_HT_MCS_NUM
- ATH10K_HWMON_NAME_LEN
- ATH10K_HW_AMPDU
- ATH10K_HW_BA_FAIL
- ATH10K_HW_BW
- ATH10K_HW_CC_WRAP_DISABLED
- ATH10K_HW_CC_WRAP_SHIFTED_ALL
- ATH10K_HW_CC_WRAP_SHIFTED_EACH
- ATH10K_HW_GI
- ATH10K_HW_LEGACY_RATE
- ATH10K_HW_MCS_RATE
- ATH10K_HW_NSS
- ATH10K_HW_PREAMBLE
- ATH10K_HW_QCA4019
- ATH10K_HW_QCA6174
- ATH10K_HW_QCA9377
- ATH10K_HW_QCA9887
- ATH10K_HW_QCA9888
- ATH10K_HW_QCA988X
- ATH10K_HW_QCA9984
- ATH10K_HW_QCA99X0
- ATH10K_HW_RATECODE
- ATH10K_HW_RATE_CCK_LP_11M
- ATH10K_HW_RATE_CCK_LP_1M
- ATH10K_HW_RATE_CCK_LP_2M
- ATH10K_HW_RATE_CCK_LP_5_5M
- ATH10K_HW_RATE_CCK_SP_11M
- ATH10K_HW_RATE_CCK_SP_2M
- ATH10K_HW_RATE_CCK_SP_5_5M
- ATH10K_HW_RATE_OFDM_12M
- ATH10K_HW_RATE_OFDM_18M
- ATH10K_HW_RATE_OFDM_24M
- ATH10K_HW_RATE_OFDM_36M
- ATH10K_HW_RATE_OFDM_48M
- ATH10K_HW_RATE_OFDM_54M
- ATH10K_HW_RATE_OFDM_6M
- ATH10K_HW_RATE_OFDM_9M
- ATH10K_HW_RATE_REV2_CCK_LP_11M
- ATH10K_HW_RATE_REV2_CCK_LP_1M
- ATH10K_HW_RATE_REV2_CCK_LP_2M
- ATH10K_HW_RATE_REV2_CCK_LP_5_5M
- ATH10K_HW_RATE_REV2_CCK_SP_11M
- ATH10K_HW_RATE_REV2_CCK_SP_2M
- ATH10K_HW_RATE_REV2_CCK_SP_5_5M
- ATH10K_HW_REFCLK_19_2_MHZ
- ATH10K_HW_REFCLK_24_MHZ
- ATH10K_HW_REFCLK_26_MHZ
- ATH10K_HW_REFCLK_37_4_MHZ
- ATH10K_HW_REFCLK_38_4_MHZ
- ATH10K_HW_REFCLK_40_MHZ
- ATH10K_HW_REFCLK_48_MHZ
- ATH10K_HW_REFCLK_52_MHZ
- ATH10K_HW_REFCLK_COUNT
- ATH10K_HW_REFCLK_UNKNOWN
- ATH10K_HW_TXRX_ETHERNET
- ATH10K_HW_TXRX_MGMT
- ATH10K_HW_TXRX_NATIVE_WIFI
- ATH10K_HW_TXRX_RAW
- ATH10K_HW_WCN3990
- ATH10K_IEEE80211_EXTIV
- ATH10K_IEEE80211_TKIP_MICLEN
- ATH10K_INVALID_RSSI
- ATH10K_KEEPALIVE_MAX_IDLE
- ATH10K_KEEPALIVE_MAX_UNRESPONSIVE
- ATH10K_KEEPALIVE_MIN_IDLE
- ATH10K_KICKOUT_THRESHOLD
- ATH10K_LEGACY_NUM
- ATH10K_LOG_SERVICE_GROUP
- ATH10K_MAC_FIRST_OFDM_RATE_IDX
- ATH10K_MAC_TX_HTT
- ATH10K_MAC_TX_HTT_MGMT
- ATH10K_MAC_TX_UNKNOWN
- ATH10K_MAC_TX_WMI_MGMT
- ATH10K_MAGIC_NOT_COPIED
- ATH10K_MAX_5G_CHAN
- ATH10K_MAX_HW_LISTEN_INTERVAL
- ATH10K_MAX_NUM_MGMT_PENDING
- ATH10K_MAX_NUM_PEER_IDS
- ATH10K_MCAST2UCAST_DISABLED
- ATH10K_MCAST2UCAST_ENABLED
- ATH10K_MEM_REGION_TYPE_AXI
- ATH10K_MEM_REGION_TYPE_DRAM
- ATH10K_MEM_REGION_TYPE_IOREG
- ATH10K_MEM_REGION_TYPE_IOSRAM
- ATH10K_MEM_REGION_TYPE_IRAM1
- ATH10K_MEM_REGION_TYPE_IRAM2
- ATH10K_MEM_REGION_TYPE_REG
- ATH10K_MSG_MAX
- ATH10K_NAPI_BUDGET
- ATH10K_NSS_NUM
- ATH10K_NUM_CHANS
- ATH10K_NUM_CONTROL_TX_BUFFERS
- ATH10K_PCI_IRQ_AUTO
- ATH10K_PCI_IRQ_LEGACY
- ATH10K_PCI_IRQ_MSI
- ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS
- ATH10K_PCI_RESET_AUTO
- ATH10K_PCI_RESET_WARM_ONLY
- ATH10K_PCI_RX_POST_RETRY_MS
- ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC
- ATH10K_PCI_TARGET_WAIT
- ATH10K_PKTLOG_ANY
- ATH10K_PKTLOG_DBG_PRINT
- ATH10K_PKTLOG_PEER_STATS
- ATH10K_PKTLOG_RCFIND
- ATH10K_PKTLOG_RCUPDATE
- ATH10K_PKTLOG_RX
- ATH10K_PKTLOG_TX
- ATH10K_PKT_RX_ERR_CRYPT
- ATH10K_PKT_RX_ERR_FCS
- ATH10K_PKT_RX_ERR_MAX
- ATH10K_PKT_RX_ERR_PEER_IDX_INVAL
- ATH10K_PKT_RX_ERR_TKIP
- ATH10K_PRE_CAL_MODE_DT
- ATH10K_PRE_CAL_MODE_FILE
- ATH10K_PROT_CTSONLY
- ATH10K_PROT_NONE
- ATH10K_PROT_RTSCTS
- ATH10K_QMI_CLIENT_ID
- ATH10K_QMI_EVENT_FW_DOWN_IND
- ATH10K_QMI_EVENT_FW_READY_IND
- ATH10K_QMI_EVENT_MAX
- ATH10K_QMI_EVENT_MSA_READY_IND
- ATH10K_QMI_EVENT_SERVER_ARRIVE
- ATH10K_QMI_EVENT_SERVER_EXIT
- ATH10K_QMI_TIMEOUT
- ATH10K_QUIET_PERIOD_DEFAULT
- ATH10K_QUIET_PERIOD_MIN
- ATH10K_QUIET_START_OFFSET
- ATH10K_RADAR_CONFIRMATION_IDLE
- ATH10K_RADAR_CONFIRMATION_INPROGRESS
- ATH10K_RADAR_CONFIRMATION_STOPPED
- ATH10K_RATE_INFO_FLAGS_SGI_BIT
- ATH10K_RATE_TABLE_NUM
- ATH10K_ROC_TIMEOUT_HZ
- ATH10K_RXCB_SKB
- ATH10K_SCAN_ABORTING
- ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD
- ATH10K_SCAN_ID
- ATH10K_SCAN_IDLE
- ATH10K_SCAN_RUNNING
- ATH10K_SCAN_STARTING
- ATH10K_SDIO_BUS_REQUEST_MAX_NUM
- ATH10K_SDIO_DRIVE_DTSX_MASK
- ATH10K_SDIO_DRIVE_DTSX_TYPE_A
- ATH10K_SDIO_DRIVE_DTSX_TYPE_B
- ATH10K_SDIO_DRIVE_DTSX_TYPE_C
- ATH10K_SDIO_DRIVE_DTSX_TYPE_D
- ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ
- ATH10K_SDIO_MAX_BUFFER_SIZE
- ATH10K_SDIO_MAX_RX_MSGS
- ATH10K_SDIO_PM_OPS
- ATH10K_SDIO_TARGET_DEBUG_INTR_MASK
- ATH10K_SKB_CB
- ATH10K_SKB_F_DELIVER_CAB
- ATH10K_SKB_F_DTIM_ZERO
- ATH10K_SKB_F_MGMT
- ATH10K_SKB_F_NO_HWCRYPT
- ATH10K_SKB_F_QOS
- ATH10K_SKB_F_RAW_TX
- ATH10K_SKB_RXCB
- ATH10K_SMBIOS_BDF_EXT_LENGTH
- ATH10K_SMBIOS_BDF_EXT_MAGIC
- ATH10K_SMBIOS_BDF_EXT_OFFSET
- ATH10K_SMBIOS_BDF_EXT_STR_LENGTH
- ATH10K_SMBIOS_BDF_EXT_TYPE
- ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK
- ATH10K_SNOC_FLAG_RECOVERY
- ATH10K_SNOC_FLAG_REGISTERED
- ATH10K_SNOC_FLAG_UNREGISTERING
- ATH10K_SNOC_RX_POST_RETRY_MS
- ATH10K_SNOC_WAKE_IRQ
- ATH10K_SSTATS_LEN
- ATH10K_STATE_OFF
- ATH10K_STATE_ON
- ATH10K_STATE_RESTARTED
- ATH10K_STATE_RESTARTING
- ATH10K_STATE_UTF
- ATH10K_STATE_WEDGED
- ATH10K_STATS_TYPE_AMPDU
- ATH10K_STATS_TYPE_FAIL
- ATH10K_STATS_TYPE_MAX
- ATH10K_STATS_TYPE_RETRY
- ATH10K_STATS_TYPE_SUCC
- ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX
- ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ
- ATH10K_SWAP_CODE_SEG_NUM_MAX
- ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED
- ATH10K_TCSR_REG_BASE
- ATH10K_TCSR_REG_SIZE
- ATH10K_TESTMODE_VERSION_MAJOR
- ATH10K_TESTMODE_VERSION_MINOR
- ATH10K_THERMAL_SYNC_TIMEOUT_HZ
- ATH10K_THERMAL_THROTTLE_MAX
- ATH10K_TM_ATTR_CMD
- ATH10K_TM_ATTR_DATA
- ATH10K_TM_ATTR_MAX
- ATH10K_TM_ATTR_VERSION_MAJOR
- ATH10K_TM_ATTR_VERSION_MINOR
- ATH10K_TM_ATTR_WMI_CMDID
- ATH10K_TM_ATTR_WMI_OP_VERSION
- ATH10K_TM_CMD_GET_VERSION
- ATH10K_TM_CMD_UTF_START
- ATH10K_TM_CMD_UTF_STOP
- ATH10K_TM_CMD_WMI
- ATH10K_TM_DATA_MAX_LEN
- ATH10K_TPC_CONFIG_BUF_SIZE
- ATH10K_TPC_PREAM_TABLE_END
- ATH10K_TPC_TABLE_TYPE_FLAG
- ATH10K_TXRX_NUM_EXT_TIDS
- ATH10K_TX_PAUSE_MAX
- ATH10K_TX_PAUSE_Q_FULL
- ATH10K_TX_POWER_MAX_VAL
- ATH10K_TX_POWER_MIN_VAL
- ATH10K_USB_CONTROL_REQ_DIAG_CMD
- ATH10K_USB_CONTROL_REQ_DIAG_RESP
- ATH10K_USB_CONTROL_REQ_RECV_BMI_RESP
- ATH10K_USB_CONTROL_REQ_SEND_BMI_CMD
- ATH10K_USB_CTRL_DIAG_CC_READ
- ATH10K_USB_CTRL_DIAG_CC_WRITE
- ATH10K_USB_EP_ADDR_APP_CTRL_IN
- ATH10K_USB_EP_ADDR_APP_CTRL_OUT
- ATH10K_USB_EP_ADDR_APP_DATA2_IN
- ATH10K_USB_EP_ADDR_APP_DATA_HP_OUT
- ATH10K_USB_EP_ADDR_APP_DATA_IN
- ATH10K_USB_EP_ADDR_APP_DATA_LP_OUT
- ATH10K_USB_EP_ADDR_APP_DATA_MP_OUT
- ATH10K_USB_EP_ADDR_APP_INT_IN
- ATH10K_USB_IS_BULK_EP
- ATH10K_USB_IS_DIR_IN
- ATH10K_USB_IS_INT_EP
- ATH10K_USB_IS_ISOC_EP
- ATH10K_USB_MAX_DIAG_CMD
- ATH10K_USB_MAX_DIAG_RESP
- ATH10K_USB_PIPE_FLAG_TX
- ATH10K_USB_PIPE_INVALID
- ATH10K_USB_PIPE_MAX
- ATH10K_USB_PIPE_RX_CTRL
- ATH10K_USB_PIPE_RX_DATA
- ATH10K_USB_PIPE_RX_DATA2
- ATH10K_USB_PIPE_RX_INT
- ATH10K_USB_PIPE_TX_CTRL
- ATH10K_USB_PIPE_TX_DATA_HP
- ATH10K_USB_PIPE_TX_DATA_LP
- ATH10K_USB_PIPE_TX_DATA_MP
- ATH10K_USB_RX_BUFFER_SIZE
- ATH10K_VDEV_DELETE_TIMEOUT_HZ
- ATH10K_VDEV_SETUP_TIMEOUT_HZ
- ATH10K_VHT_MCS_NUM
- ATH10K_WMI_BARRIER_ECHO_ID
- ATH10K_WMI_BARRIER_TIMEOUT_HZ
- ATH10K_WMI_DFS_CONF_TIMEOUT_HZ
- ATH25_BD_MAGIC
- ATH25_IRQ_CPU_CLOCK
- ATH25_REG_MS
- ATH25_SOC_AR2312
- ATH25_SOC_AR2313
- ATH25_SOC_AR2315
- ATH25_SOC_AR2316
- ATH25_SOC_AR2317
- ATH25_SOC_AR2318
- ATH25_SOC_AR5312
- ATH25_SOC_UNKNOWN
- ATH3K_DNLOAD
- ATH3K_FIRMWARE
- ATH3K_GETSTATE
- ATH3K_GETVERSION
- ATH3K_MODE_MASK
- ATH3K_NAME_LEN
- ATH3K_NORMAL_MODE
- ATH3K_PATCH_UPDATE
- ATH3K_SET_NORMAL_MODE
- ATH3K_SYSCFG_UPDATE
- ATH3K_XTAL_FREQ_19P2
- ATH3K_XTAL_FREQ_26M
- ATH3K_XTAL_FREQ_40M
- ATH5K_ANI_CCK_TRIG_HIGH
- ATH5K_ANI_CCK_TRIG_LOW
- ATH5K_ANI_LISTEN_PERIOD
- ATH5K_ANI_MAX_FIRSTEP_LVL
- ATH5K_ANI_MAX_NOISE_IMM_LVL
- ATH5K_ANI_MODE_AUTO
- ATH5K_ANI_MODE_MANUAL_HIGH
- ATH5K_ANI_MODE_MANUAL_LOW
- ATH5K_ANI_MODE_OFF
- ATH5K_ANI_OFDM_TRIG_HIGH
- ATH5K_ANI_OFDM_TRIG_LOW
- ATH5K_ANI_RSSI_THR_HIGH
- ATH5K_ANI_RSSI_THR_LOW
- ATH5K_DBG
- ATH5K_DBG_UNLIMIT
- ATH5K_DEBUG_ANI
- ATH5K_DEBUG_ANY
- ATH5K_DEBUG_BEACON
- ATH5K_DEBUG_CALIBRATE
- ATH5K_DEBUG_DESC
- ATH5K_DEBUG_DMA
- ATH5K_DEBUG_DUMPBANDS
- ATH5K_DEBUG_INTR
- ATH5K_DEBUG_LED
- ATH5K_DEBUG_MODE
- ATH5K_DEBUG_RESET
- ATH5K_DEBUG_TXPOWER
- ATH5K_DEBUG_XMIT
- ATH5K_ERR
- ATH5K_INFO
- ATH5K_LED_MAX_NAME_LEN
- ATH5K_MAX_TSF_READ
- ATH5K_NF_CAL_HIST_MAX
- ATH5K_PHYERR_CNT_MAX
- ATH5K_PM_OPS
- ATH5K_PRINTF
- ATH5K_PRINTK
- ATH5K_PRINTK_LIMIT
- ATH5K_RATE_CODE_11M
- ATH5K_RATE_CODE_12M
- ATH5K_RATE_CODE_18M
- ATH5K_RATE_CODE_1M
- ATH5K_RATE_CODE_24M
- ATH5K_RATE_CODE_2M
- ATH5K_RATE_CODE_36M
- ATH5K_RATE_CODE_48M
- ATH5K_RATE_CODE_54M
- ATH5K_RATE_CODE_5_5M
- ATH5K_RATE_CODE_6M
- ATH5K_RATE_CODE_9M
- ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
- ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
- ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT
- ATH5K_TXQ_LEN_LOW
- ATH5K_TXQ_LEN_MAX
- ATH5K_TX_COMPLETE_POLL_INT
- ATH5K_WARN
- ATH6KL_ABI_VERSION
- ATH6KL_AID_SHIFT
- ATH6KL_AMSDU_BUFFER_SIZE
- ATH6KL_AMSDU_REFILL_THRESHOLD
- ATH6KL_ANALOG_PLL_REGISTER
- ATH6KL_APSD_ALL_FRAME
- ATH6KL_APSD_FRAME_MASK
- ATH6KL_APSD_NUM_OF_AC
- ATH6KL_AR6003_HI_START_ADDR
- ATH6KL_AR6004_HI_START_ADDR
- ATH6KL_BUFFER_SIZE
- ATH6KL_CAPABILITY_LEN
- ATH6KL_CFG80211_H
- ATH6KL_CFG_SUSPEND_CUTPOWER
- ATH6KL_CFG_SUSPEND_DEEPSLEEP
- ATH6KL_CFG_SUSPEND_WOW
- ATH6KL_CIPHER_AES_CCM
- ATH6KL_CIPHER_AES_OCB
- ATH6KL_CIPHER_CCKM_KRK
- ATH6KL_CIPHER_CKIP
- ATH6KL_CIPHER_NONE
- ATH6KL_CIPHER_TKIP
- ATH6KL_CIPHER_WEP
- ATH6KL_CONF_ENABLE_11N
- ATH6KL_CONF_ENABLE_TX_BURST
- ATH6KL_CONF_IGNORE_ERP_BARKER
- ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN
- ATH6KL_CONF_UART_DEBUG
- ATH6KL_CONTROL_PKT_TAG
- ATH6KL_COUNTRY_RD_SHIFT
- ATH6KL_DATA_OFFSET
- ATH6KL_DATA_PKT_TAG
- ATH6KL_DBG_AGGR
- ATH6KL_DBG_ANY
- ATH6KL_DBG_BMI
- ATH6KL_DBG_BOOT
- ATH6KL_DBG_CREDIT
- ATH6KL_DBG_HIF
- ATH6KL_DBG_HTC
- ATH6KL_DBG_IRQ
- ATH6KL_DBG_RAW_BYTES
- ATH6KL_DBG_RECOVERY
- ATH6KL_DBG_SCATTER
- ATH6KL_DBG_SDIO
- ATH6KL_DBG_SDIO_DUMP
- ATH6KL_DBG_SUSPEND
- ATH6KL_DBG_TRC
- ATH6KL_DBG_USB
- ATH6KL_DBG_USB_BULK
- ATH6KL_DBG_WLAN_CFG
- ATH6KL_DBG_WLAN_RX
- ATH6KL_DBG_WLAN_TX
- ATH6KL_DBG_WMI
- ATH6KL_DBG_WMI_DUMP
- ATH6KL_DEFAULT_BMISS_TIME
- ATH6KL_DEFAULT_LISTEN_INTVAL
- ATH6KL_FG_SCAN_INTERVAL
- ATH6KL_FIRMWARE_MAGIC
- ATH6KL_FWLOG_MAX_ENTRIES
- ATH6KL_FWLOG_PAYLOAD_SIZE
- ATH6KL_FWLOG_VALID_MASK
- ATH6KL_FW_API2_FILE
- ATH6KL_FW_API3_FILE
- ATH6KL_FW_API4_FILE
- ATH6KL_FW_API5_FILE
- ATH6KL_FW_ASSERT
- ATH6KL_FW_CAPABILITY_64BIT_RATES
- ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS
- ATH6KL_FW_CAPABILITY_BMISS_ENHANCE
- ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR
- ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL
- ATH6KL_FW_CAPABILITY_HOST_P2P
- ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT
- ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT
- ATH6KL_FW_CAPABILITY_MAX
- ATH6KL_FW_CAPABILITY_NO_IP_CHECKSUM
- ATH6KL_FW_CAPABILITY_RATETABLE_MCS15
- ATH6KL_FW_CAPABILITY_REGDOMAIN
- ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE
- ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD
- ATH6KL_FW_CAPABILITY_SCHED_SCAN
- ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST
- ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2
- ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX
- ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY
- ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER
- ATH6KL_FW_EP_FULL
- ATH6KL_FW_HB_RESP_FAILURE
- ATH6KL_FW_IE_BOARD_ADDR
- ATH6KL_FW_IE_CAPABILITIES
- ATH6KL_FW_IE_FW_IMAGE
- ATH6KL_FW_IE_FW_VERSION
- ATH6KL_FW_IE_OTP_IMAGE
- ATH6KL_FW_IE_PATCH_ADDR
- ATH6KL_FW_IE_PATCH_IMAGE
- ATH6KL_FW_IE_RESERVED_RAM_SIZE
- ATH6KL_FW_IE_TIMESTAMP
- ATH6KL_FW_IE_VIF_MAX
- ATH6KL_HB_RESP_MISS_THRES
- ATH6KL_HIF_COMMUNICATION_TIMEOUT
- ATH6KL_HIF_TYPE_SDIO
- ATH6KL_HIF_TYPE_USB
- ATH6KL_HOST_MODE_ASLEEP
- ATH6KL_HOST_MODE_AWAKE
- ATH6KL_HTC_ALIGN_BYTES
- ATH6KL_HTC_TYPE_MBOX
- ATH6KL_HTC_TYPE_PIPE
- ATH6KL_HW_SDIO_CRC_ERROR_WAR
- ATH6KL_KEYBUF_SIZE
- ATH6KL_KEY_DEFAULT
- ATH6KL_KEY_RECV
- ATH6KL_KEY_SEQ_LEN
- ATH6KL_KEY_XMIT
- ATH6KL_MAX_AMSDU_RX_BUFFERS
- ATH6KL_MAX_BMISS_TIME
- ATH6KL_MAX_ENDPOINTS
- ATH6KL_MAX_IE
- ATH6KL_MAX_RX_BUFFERS
- ATH6KL_MAX_SEQ_NO
- ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER
- ATH6KL_MAX_WOW_LISTEN_INTL
- ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE
- ATH6KL_MICBUF_SIZE
- ATH6KL_MSG_MAX
- ATH6KL_NEXT_SEQ_NO
- ATH6KL_NUM_BANDS
- ATH6KL_OPTION_SLEEP_DISABLE
- ATH6KL_RATE_MAXSIZE
- ATH6KL_SCATTER_ENTRIES_PER_REQ
- ATH6KL_SCATTER_REQS
- ATH6KL_SCHED_SCAN_RESULT_DELAY
- ATH6KL_SDIO_PM_OPS
- ATH6KL_STATE_CUTPOWER
- ATH6KL_STATE_DEEPSLEEP
- ATH6KL_STATE_OFF
- ATH6KL_STATE_ON
- ATH6KL_STATE_RECOVERY
- ATH6KL_STATE_RESUMING
- ATH6KL_STATE_SUSPENDING
- ATH6KL_STATE_WOW
- ATH6KL_STATS_LEN
- ATH6KL_TARGET_DEBUG_INTR_MASK
- ATH6KL_TID_MASK
- ATH6KL_TIME_QUANTUM
- ATH6KL_TM_ATTR_CMD
- ATH6KL_TM_ATTR_DATA
- ATH6KL_TM_ATTR_MAX
- ATH6KL_TM_CMD_RX_REPORT
- ATH6KL_TM_CMD_TCMD
- ATH6KL_TM_DATA_MAX_LEN
- ATH6KL_TX_TIMEOUT
- ATH6KL_USB_CONTROL_REQ_DIAG_CMD
- ATH6KL_USB_CONTROL_REQ_DIAG_RESP
- ATH6KL_USB_CONTROL_REQ_RECV_BMI_RESP
- ATH6KL_USB_CONTROL_REQ_SEND_BMI_CMD
- ATH6KL_USB_CTRL_DIAG_CC_READ
- ATH6KL_USB_CTRL_DIAG_CC_WRITE
- ATH6KL_USB_EP_ADDR_APP_CTRL_IN
- ATH6KL_USB_EP_ADDR_APP_CTRL_OUT
- ATH6KL_USB_EP_ADDR_APP_DATA2_IN
- ATH6KL_USB_EP_ADDR_APP_DATA_HP_OUT
- ATH6KL_USB_EP_ADDR_APP_DATA_IN
- ATH6KL_USB_EP_ADDR_APP_DATA_LP_OUT
- ATH6KL_USB_EP_ADDR_APP_DATA_MP_OUT
- ATH6KL_USB_EP_ADDR_APP_INT_IN
- ATH6KL_USB_IS_BULK_EP
- ATH6KL_USB_IS_DIR_IN
- ATH6KL_USB_IS_INT_EP
- ATH6KL_USB_IS_ISOC_EP
- ATH6KL_USB_MAX_DIAG_CMD
- ATH6KL_USB_MAX_DIAG_RESP
- ATH6KL_USB_PIPE_FLAG_TX
- ATH6KL_USB_PIPE_ID
- ATH6KL_USB_PIPE_INVALID
- ATH6KL_USB_PIPE_MAX
- ATH6KL_USB_PIPE_RX_CTRL
- ATH6KL_USB_PIPE_RX_DATA
- ATH6KL_USB_PIPE_RX_DATA2
- ATH6KL_USB_PIPE_RX_INT
- ATH6KL_USB_PIPE_TX_CTRL
- ATH6KL_USB_PIPE_TX_DATA_HP
- ATH6KL_USB_PIPE_TX_DATA_LP
- ATH6KL_USB_PIPE_TX_DATA_MP
- ATH6KL_USB_RX_BUFFER_SIZE
- ATH6KL_VIF_MAX
- ATH6KL_WOW_MODE_DISABLE
- ATH6KL_WOW_MODE_ENABLE
- ATH6K_DEBUG_MASK
- ATH6K_MAX_MC_FILTERS_PER_LIST
- ATH79_CLK_AHB
- ATH79_CLK_CPU
- ATH79_CLK_DDR
- ATH79_CLK_END
- ATH79_CLK_MDIO
- ATH79_CLK_REF
- ATH79_CPU_IRQ
- ATH79_IP2_IRQ
- ATH79_IP2_IRQ_BASE
- ATH79_IP2_IRQ_COUNT
- ATH79_IP3_IRQ
- ATH79_IP3_IRQ_BASE
- ATH79_IP3_IRQ_COUNT
- ATH79_MEM_SIZE_MAX
- ATH79_MEM_SIZE_MIN
- ATH79_MISC_IRQ
- ATH79_MISC_IRQ_BASE
- ATH79_MISC_IRQ_COUNT
- ATH79_MISC_PERF_IRQ
- ATH79_PCI_IRQ
- ATH79_PCI_IRQ_BASE
- ATH79_PCI_IRQ_COUNT
- ATH79_SOC_AR7130
- ATH79_SOC_AR7141
- ATH79_SOC_AR7161
- ATH79_SOC_AR7240
- ATH79_SOC_AR7241
- ATH79_SOC_AR7242
- ATH79_SOC_AR9130
- ATH79_SOC_AR9132
- ATH79_SOC_AR9330
- ATH79_SOC_AR9331
- ATH79_SOC_AR9341
- ATH79_SOC_AR9342
- ATH79_SOC_AR9344
- ATH79_SOC_QCA9533
- ATH79_SOC_QCA9556
- ATH79_SOC_QCA9558
- ATH79_SOC_QCA956X
- ATH79_SOC_TP9343
- ATH79_SOC_UNKNOWN
- ATH79_SPI_RRW_DELAY_FACTOR
- ATH79_SYS_TYPE_LEN
- ATH8030_PHY_ID
- ATH8031_PHY_ID
- ATH8035_PHY_ID
- ATH9K_2GHZ_ALL
- ATH9K_2GHZ_CH01_11
- ATH9K_2GHZ_CH12_13
- ATH9K_2GHZ_CH14
- ATH9K_5GHZ_5150_5350
- ATH9K_5GHZ_5470_5850
- ATH9K_5GHZ_5725_5850
- ATH9K_5GHZ_ALL
- ATH9K_5GHZ_NO_MIDBAND
- ATH9K_ANI_ALL
- ATH9K_ANI_CCK_DEF_LEVEL
- ATH9K_ANI_CCK_MAX_LEVEL
- ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI
- ATH9K_ANI_CCK_NUM_LEVEL
- ATH9K_ANI_CCK_TRIG_HIGH
- ATH9K_ANI_CCK_TRIG_HIGH_OLD
- ATH9K_ANI_CCK_TRIG_LOW
- ATH9K_ANI_CCK_TRIG_LOW_OLD
- ATH9K_ANI_FIRSTEP_LEVEL
- ATH9K_ANI_FIRSTEP_LVL
- ATH9K_ANI_MRC_CCK
- ATH9K_ANI_OFDM_DEF_LEVEL
- ATH9K_ANI_OFDM_MAX_LEVEL
- ATH9K_ANI_OFDM_NUM_LEVEL
- ATH9K_ANI_OFDM_TRIG_HIGH
- ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI
- ATH9K_ANI_OFDM_TRIG_HIGH_OLD
- ATH9K_ANI_OFDM_TRIG_LOW
- ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI
- ATH9K_ANI_OFDM_TRIG_LOW_OLD
- ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION
- ATH9K_ANI_PERIOD
- ATH9K_ANI_POLLINTERVAL
- ATH9K_ANI_RSSI_THR_HIGH
- ATH9K_ANI_RSSI_THR_LOW
- ATH9K_ANI_SPUR_IMMUNE_LVL
- ATH9K_ANI_SPUR_IMMUNITY_LEVEL
- ATH9K_ANTENNA0_CHAINMASK
- ATH9K_ANTENNA1_CHAINMASK
- ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
- ATH9K_CLOCK_RATE_2GHZ_OFDM
- ATH9K_CLOCK_RATE_5GHZ_OFDM
- ATH9K_CLOCK_RATE_CCK
- ATH9K_DECOMP_MASK_SIZE
- ATH9K_DFS_DEBUG_H
- ATH9K_DFS_H
- ATH9K_DFS_POOL_STAT
- ATH9K_DFS_STAT
- ATH9K_H
- ATH9K_HAL_FREQ_BAND_2GHZ
- ATH9K_HAL_FREQ_BAND_5GHZ
- ATH9K_HIF_USB
- ATH9K_HTC_AMPDU
- ATH9K_HTC_BEACON
- ATH9K_HTC_INIT_TXQ
- ATH9K_HTC_MAX_BCN_VIF
- ATH9K_HTC_MAX_STA
- ATH9K_HTC_MAX_TID
- ATH9K_HTC_MAX_VIF
- ATH9K_HTC_MGMT
- ATH9K_HTC_NORMAL
- ATH9K_HTC_OP_TX_DRAIN
- ATH9K_HTC_OP_TX_QUEUES_STOP
- ATH9K_HTC_RXBUF
- ATH9K_HTC_SSTATS_LEN
- ATH9K_HTC_TXSTAT_ACK
- ATH9K_HTC_TXSTAT_CW40
- ATH9K_HTC_TXSTAT_EPID
- ATH9K_HTC_TXSTAT_EPID_S
- ATH9K_HTC_TXSTAT_FILT
- ATH9K_HTC_TXSTAT_MCS
- ATH9K_HTC_TXSTAT_RATE
- ATH9K_HTC_TXSTAT_RATE_S
- ATH9K_HTC_TXSTAT_RTC_CTS
- ATH9K_HTC_TXSTAT_SGI
- ATH9K_HTC_TX_CLEANUP_INTERVAL
- ATH9K_HTC_TX_CTSONLY
- ATH9K_HTC_TX_RESERVE
- ATH9K_HTC_TX_RTSCTS
- ATH9K_HTC_TX_THRESHOLD
- ATH9K_HTC_TX_TIMEOUT_COUNT
- ATH9K_HTC_TX_TIMEOUT_INTERVAL
- ATH9K_HW_BIT_IN_SLICE
- ATH9K_HW_CAP_2GHZ
- ATH9K_HW_CAP_4KB_SPLITTRANS
- ATH9K_HW_CAP_5GHZ
- ATH9K_HW_CAP_ANT_DIV_COMB
- ATH9K_HW_CAP_APM
- ATH9K_HW_CAP_AUTOSLEEP
- ATH9K_HW_CAP_BT_ANT_DIV
- ATH9K_HW_CAP_DFS
- ATH9K_HW_CAP_EDMA
- ATH9K_HW_CAP_FASTCLOCK
- ATH9K_HW_CAP_FCC_BAND_SWITCH
- ATH9K_HW_CAP_HT
- ATH9K_HW_CAP_LDPC
- ATH9K_HW_CAP_MCI
- ATH9K_HW_CAP_PAPRD
- ATH9K_HW_CAP_RAC_SUPPORTED
- ATH9K_HW_CAP_RFSILENT
- ATH9K_HW_CAP_RTT
- ATH9K_HW_CAP_SGI_20
- ATH9K_HW_MAX_DCU
- ATH9K_HW_OPS_H
- ATH9K_HW_RX_HP_QDEPTH
- ATH9K_HW_RX_LP_QDEPTH
- ATH9K_HW_SLICE_PER_DCU
- ATH9K_INT_BB_WATCHDOG
- ATH9K_INT_BMISC
- ATH9K_INT_BMISS
- ATH9K_INT_BNR
- ATH9K_INT_CABEND
- ATH9K_INT_COMMON
- ATH9K_INT_CST
- ATH9K_INT_DTIM
- ATH9K_INT_DTIMSYNC
- ATH9K_INT_FATAL
- ATH9K_INT_GENTIMER
- ATH9K_INT_GLOBAL
- ATH9K_INT_GPIO
- ATH9K_INT_GTT
- ATH9K_INT_MCI
- ATH9K_INT_MIB
- ATH9K_INT_NOCARD
- ATH9K_INT_RX
- ATH9K_INT_RXDESC
- ATH9K_INT_RXEOL
- ATH9K_INT_RXHP
- ATH9K_INT_RXKCM
- ATH9K_INT_RXLP
- ATH9K_INT_RXNOFRM
- ATH9K_INT_RXORN
- ATH9K_INT_RXPHY
- ATH9K_INT_SWBA
- ATH9K_INT_TIM
- ATH9K_INT_TIM_TIMER
- ATH9K_INT_TSFOOR
- ATH9K_INT_TX
- ATH9K_INT_TXDESC
- ATH9K_INT_TXURN
- ATH9K_KEY_TYPE_AES
- ATH9K_KEY_TYPE_CLEAR
- ATH9K_KEY_TYPE_TKIP
- ATH9K_KEY_TYPE_WEP
- ATH9K_MAX_TSF_READ
- ATH9K_NF_CAL_HIST_MAX
- ATH9K_NF_CAL_NOISE_THRESH
- ATH9K_NUM_CHANCTX
- ATH9K_NUM_CHANNELS
- ATH9K_NUM_DMA_DEBUG_REGS
- ATH9K_NUM_QUEUES
- ATH9K_NUM_TX_QUEUES
- ATH9K_PCI_AR9565_1ANT
- ATH9K_PCI_AR9565_2ANT
- ATH9K_PCI_BT_ANT_DIV
- ATH9K_PCI_CUS198
- ATH9K_PCI_CUS217
- ATH9K_PCI_CUS230
- ATH9K_PCI_CUS252
- ATH9K_PCI_D3_L1_WAR
- ATH9K_PCI_KILLER
- ATH9K_PCI_LED_ACT_HI
- ATH9K_PCI_NO_PLL_PWRSAVE
- ATH9K_PCI_WOW
- ATH9K_PHYERR_CCK_BLOCKER
- ATH9K_PHYERR_CCK_HEADER_CRC
- ATH9K_PHYERR_CCK_LENGTH_ILLEGAL
- ATH9K_PHYERR_CCK_POWER_DROP
- ATH9K_PHYERR_CCK_RATE_ILLEGAL
- ATH9K_PHYERR_CCK_RESTART
- ATH9K_PHYERR_CCK_SERVICE
- ATH9K_PHYERR_CCK_TIMING
- ATH9K_PHYERR_FALSE_RADAR_EXT
- ATH9K_PHYERR_GREEN_FIELD
- ATH9K_PHYERR_HT_CRC_ERROR
- ATH9K_PHYERR_HT_LENGTH_ILLEGAL
- ATH9K_PHYERR_HT_RATE_ILLEGAL
- ATH9K_PHYERR_HT_ZLF
- ATH9K_PHYERR_LENGTH
- ATH9K_PHYERR_MAX
- ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL
- ATH9K_PHYERR_OFDM_POWER_DROP
- ATH9K_PHYERR_OFDM_RATE_ILLEGAL
- ATH9K_PHYERR_OFDM_RESTART
- ATH9K_PHYERR_OFDM_SERVICE
- ATH9K_PHYERR_OFDM_SIGNAL_PARITY
- ATH9K_PHYERR_OFDM_TIMING
- ATH9K_PHYERR_PARITY
- ATH9K_PHYERR_RADAR
- ATH9K_PHYERR_RATE
- ATH9K_PHYERR_SERVICE
- ATH9K_PHYERR_SPECTRAL
- ATH9K_PHYERR_TIMING
- ATH9K_PHYERR_TOR
- ATH9K_PHYERR_UNDERRUN
- ATH9K_PKT_TYPE_ATIM
- ATH9K_PKT_TYPE_BEACON
- ATH9K_PKT_TYPE_CHIRP
- ATH9K_PKT_TYPE_GRP_POLL
- ATH9K_PKT_TYPE_NORMAL
- ATH9K_PKT_TYPE_PROBE_RESP
- ATH9K_PKT_TYPE_PSPOLL
- ATH9K_PLAT_EEP_MAX_WORDS
- ATH9K_PM_AWAKE
- ATH9K_PM_FULL_SLEEP
- ATH9K_PM_NETWORK_SLEEP
- ATH9K_PM_OPS
- ATH9K_PM_UNDEFINED
- ATH9K_POW_SM
- ATH9K_RATESERIES_2040
- ATH9K_RATESERIES_HALFGI
- ATH9K_RATESERIES_RTS_CTS
- ATH9K_RATESERIES_STBC
- ATH9K_RESET_COLD
- ATH9K_RESET_POWER_ON
- ATH9K_RESET_WARM
- ATH9K_RNG_BUF_SIZE
- ATH9K_RNG_ENTROPY
- ATH9K_RSSI_BAD
- ATH9K_RXDESC_INTREQ
- ATH9K_RXERR_CORRUPT_DESC
- ATH9K_RXERR_CRC
- ATH9K_RXERR_DECRYPT
- ATH9K_RXERR_FIFO
- ATH9K_RXERR_KEYMISS
- ATH9K_RXERR_MIC
- ATH9K_RXERR_PHY
- ATH9K_RXKEYIX_INVALID
- ATH9K_RX_2040
- ATH9K_RX_DECRYPT_BUSY
- ATH9K_RX_DELIM_CRC_POST
- ATH9K_RX_DELIM_CRC_PRE
- ATH9K_RX_FILTER_4ADDRESS
- ATH9K_RX_FILTER_BCAST
- ATH9K_RX_FILTER_BEACON
- ATH9K_RX_FILTER_COMP_BA
- ATH9K_RX_FILTER_COMP_BAR
- ATH9K_RX_FILTER_CONTROL
- ATH9K_RX_FILTER_CONTROL_WRAPPER
- ATH9K_RX_FILTER_MCAST
- ATH9K_RX_FILTER_MCAST_BCAST_ALL
- ATH9K_RX_FILTER_MYBEACON
- ATH9K_RX_FILTER_PHYERR
- ATH9K_RX_FILTER_PHYRADAR
- ATH9K_RX_FILTER_PROBEREQ
- ATH9K_RX_FILTER_PROM
- ATH9K_RX_FILTER_PSPOLL
- ATH9K_RX_FILTER_UCAST
- ATH9K_RX_FILTER_UNCOMP_BA_BAR
- ATH9K_RX_GI
- ATH9K_RX_MORE
- ATH9K_RX_MORE_AGGR
- ATH9K_RX_QUEUE_HP
- ATH9K_RX_QUEUE_LP
- ATH9K_RX_QUEUE_MAX
- ATH9K_SIG_FIRSTEP_SETTING_MAX
- ATH9K_SIG_FIRSTEP_SETTING_MIN
- ATH9K_SIG_SPUR_IMM_SETTING_MAX
- ATH9K_SIG_SPUR_IMM_SETTING_MIN
- ATH9K_SSTATS_LEN
- ATH9K_TIME_QUANTUM
- ATH9K_TSFOOR_THRESHOLD
- ATH9K_TXDESC_CLRDMASK
- ATH9K_TXDESC_CTSENA
- ATH9K_TXDESC_EXT_AND_CTL
- ATH9K_TXDESC_EXT_ONLY
- ATH9K_TXDESC_FRAG_IS_ON
- ATH9K_TXDESC_INTREQ
- ATH9K_TXDESC_LDPC
- ATH9K_TXDESC_LOWRXCHAIN
- ATH9K_TXDESC_NOACK
- ATH9K_TXDESC_PAPRD
- ATH9K_TXDESC_PAPRD_S
- ATH9K_TXDESC_RTSENA
- ATH9K_TXDESC_VEOL
- ATH9K_TXDESC_VMF
- ATH9K_TXERR_FIFO
- ATH9K_TXERR_FILT
- ATH9K_TXERR_MASK
- ATH9K_TXERR_TIMER_EXPIRED
- ATH9K_TXERR_XRETRY
- ATH9K_TXERR_XTXOP
- ATH9K_TXKEYIX_INVALID
- ATH9K_TXQ_USEDEFAULT
- ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS
- ATH9K_TX_ACKED
- ATH9K_TX_BA
- ATH9K_TX_DATA_UNDERRUN
- ATH9K_TX_DELIM_UNDERRUN
- ATH9K_TX_DESC_CFG_ERR
- ATH9K_TX_FLUSH
- ATH9K_TX_PWRMGMT
- ATH9K_TX_QUEUE_BEACON
- ATH9K_TX_QUEUE_CAB
- ATH9K_TX_QUEUE_DATA
- ATH9K_TX_QUEUE_INACTIVE
- ATH9K_TX_QUEUE_PSPOLL
- ATH9K_TX_QUEUE_UAPSD
- ATH9K_TX_STOP_DMA_TIMEOUT
- ATH9K_TX_SW_FILTERED
- ATH9K_WME_UPSD
- ATHEROS_VENDOR_ID
- ATHUB_BASE__INST0_SEG0
- ATHUB_BASE__INST0_SEG1
- ATHUB_BASE__INST0_SEG2
- ATHUB_BASE__INST0_SEG3
- ATHUB_BASE__INST0_SEG4
- ATHUB_BASE__INST0_SEG5
- ATHUB_BASE__INST1_SEG0
- ATHUB_BASE__INST1_SEG1
- ATHUB_BASE__INST1_SEG2
- ATHUB_BASE__INST1_SEG3
- ATHUB_BASE__INST1_SEG4
- ATHUB_BASE__INST1_SEG5
- ATHUB_BASE__INST2_SEG0
- ATHUB_BASE__INST2_SEG1
- ATHUB_BASE__INST2_SEG2
- ATHUB_BASE__INST2_SEG3
- ATHUB_BASE__INST2_SEG4
- ATHUB_BASE__INST2_SEG5
- ATHUB_BASE__INST3_SEG0
- ATHUB_BASE__INST3_SEG1
- ATHUB_BASE__INST3_SEG2
- ATHUB_BASE__INST3_SEG3
- ATHUB_BASE__INST3_SEG4
- ATHUB_BASE__INST3_SEG5
- ATHUB_BASE__INST4_SEG0
- ATHUB_BASE__INST4_SEG1
- ATHUB_BASE__INST4_SEG2
- ATHUB_BASE__INST4_SEG3
- ATHUB_BASE__INST4_SEG4
- ATHUB_BASE__INST4_SEG5
- ATHUB_BASE__INST5_SEG0
- ATHUB_BASE__INST5_SEG1
- ATHUB_BASE__INST5_SEG2
- ATHUB_BASE__INST5_SEG3
- ATHUB_BASE__INST5_SEG4
- ATHUB_BASE__INST5_SEG5
- ATHUB_BASE__INST6_SEG0
- ATHUB_BASE__INST6_SEG1
- ATHUB_BASE__INST6_SEG2
- ATHUB_BASE__INST6_SEG3
- ATHUB_BASE__INST6_SEG4
- ATHUB_BASE__INST6_SEG5
- ATHUB_BASE__INST7_SEG0
- ATHUB_BASE__INST7_SEG1
- ATHUB_BASE__INST7_SEG2
- ATHUB_BASE__INST7_SEG3
- ATHUB_BASE__INST7_SEG4
- ATHUB_BASE__INST7_SEG5
- ATHUB_COMMAND__BUS_MASTER_EN_MASK
- ATHUB_COMMAND__BUS_MASTER_EN__SHIFT
- ATHUB_HWID
- ATHUB_HWIP
- ATHUB_IH_CREDIT__CREDIT_VALUE_MASK
- ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT
- ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK
- ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT
- ATHUB_MEM_POWER_LS__LS_HOLD_MASK
- ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT
- ATHUB_MEM_POWER_LS__LS_SETUP_MASK
- ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT
- ATHUB_MISC_CNTL__CG_ENABLE_MASK
- ATHUB_MISC_CNTL__CG_ENABLE__SHIFT
- ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK
- ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT
- ATHUB_MISC_CNTL__CG_OFFDLY_MASK
- ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT
- ATHUB_MISC_CNTL__CG_STATUS_MASK
- ATHUB_MISC_CNTL__CG_STATUS__SHIFT
- ATHUB_MISC_CNTL__PG_ENABLE_MASK
- ATHUB_MISC_CNTL__PG_ENABLE__SHIFT
- ATHUB_MISC_CNTL__PG_OFFDLY_MASK
- ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT
- ATHUB_MISC_CNTL__PG_STATUS_MASK
- ATHUB_MISC_CNTL__PG_STATUS__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK
- ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
- ATHUB_PCIE_ATS_CNTL__STU_MASK
- ATHUB_PCIE_ATS_CNTL__STU__SHIFT
- ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
- ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
- ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
- ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
- ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
- ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
- ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK
- ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT
- ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
- ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
- ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
- ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
- ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK
- ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT
- ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK
- ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT
- ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK
- ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT
- ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK
- ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT
- ATH_AGGR_DELIM_SZ
- ATH_AGGR_ENCRYPTDELIM
- ATH_AGGR_GET_NDELIM
- ATH_AGGR_MINPLEN
- ATH_AGGR_MIN_QDEPTH
- ATH_AHB
- ATH_AIC_BT_AIC_ENABLE
- ATH_AIC_BT_JUPITER_CTRL
- ATH_AIC_MAX_AIC_LIN_TABLE
- ATH_AIC_MAX_BT_CHANNEL
- ATH_AIC_MAX_COM_ATT_DB_TABLE
- ATH_AIC_MAX_ROT_DIR_ATT_DB
- ATH_AIC_MAX_ROT_QUAD_ATT_DB
- ATH_AIC_MEAS_MAG_THRESH
- ATH_AIC_MIN_ROT_DIR_ATT_DB
- ATH_AIC_MIN_ROT_QUAD_ATT_DB
- ATH_AIC_SRAM_AUTO_INCREMENT
- ATH_AIC_SRAM_CAL_OFFSET
- ATH_AIC_SRAM_GAIN_TABLE_OFFSET
- ATH_AIC_SRAM_OFFSET
- ATH_AMPDU_LIMIT_MAX
- ATH_ANI_MAX_SKIP_COUNT
- ATH_ANI_POLLINTERVAL
- ATH_ANI_POLLINTERVAL_NEW
- ATH_ANI_POLLINTERVAL_OLD
- ATH_ANT_DIV_COMB_ALT_ANT_RATIO
- ATH_ANT_DIV_COMB_ALT_ANT_RATIO2
- ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI
- ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI
- ATH_ANT_DIV_COMB_INIT_COUNT
- ATH_ANT_DIV_COMB_LNA1
- ATH_ANT_DIV_COMB_LNA1_DELTA_HI
- ATH_ANT_DIV_COMB_LNA1_DELTA_LOW
- ATH_ANT_DIV_COMB_LNA1_DELTA_MID
- ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2
- ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2
- ATH_ANT_DIV_COMB_LNA2
- ATH_ANT_DIV_COMB_MAX_COUNT
- ATH_ANT_DIV_COMB_MAX_PKTCOUNT
- ATH_ANT_DIV_COMB_SHORT_SCAN_INTR
- ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT
- ATH_ANT_RX_CURRENT_SHIFT
- ATH_ANT_RX_MAIN_SHIFT
- ATH_ANT_RX_MASK
- ATH_AN_2_TID
- ATH_AP_SHORT_CALINTERVAL
- ATH_BA_INDEX
- ATH_BA_INDEX2SEQ
- ATH_BA_ISSET
- ATH_BCBUF
- ATH_BTACTIVE_GPIO_9280
- ATH_BTACTIVE_GPIO_9300
- ATH_BTCOEX_BMISS_THRESH
- ATH_BTCOEX_BTSCAN_DUTY_CYCLE
- ATH_BTCOEX_CFG_2WIRE
- ATH_BTCOEX_CFG_3WIRE
- ATH_BTCOEX_CFG_MCI
- ATH_BTCOEX_CFG_NONE
- ATH_BTCOEX_DEF_BT_PERIOD
- ATH_BTCOEX_DEF_DUTY_CYCLE
- ATH_BTCOEX_HT20_MAX_TXPOWER
- ATH_BTCOEX_HT40_MAX_TXPOWER
- ATH_BTCOEX_RX_WAIT_TIME
- ATH_BTCOEX_STOMP_ALL
- ATH_BTCOEX_STOMP_AUDIO
- ATH_BTCOEX_STOMP_FTP_THRESH
- ATH_BTCOEX_STOMP_LOW
- ATH_BTCOEX_STOMP_LOW_FTP
- ATH_BTCOEX_STOMP_MAX
- ATH_BTCOEX_STOMP_NONE
- ATH_BTPRIORITY_GPIO_9285
- ATH_BTPRIORITY_GPIO_9300
- ATH_BT_CNT_SCAN_THRESHOLD
- ATH_BT_CNT_THRESHOLD
- ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE
- ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A
- ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE
- ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A
- ATH_BT_COEX_ANT_DIV_SWITCH_COM
- ATH_BT_COEX_MODE_DISABLED
- ATH_BT_COEX_MODE_LEGACY
- ATH_BT_COEX_MODE_SLOTTED
- ATH_BT_COEX_MODE_UNSLOTTED
- ATH_BT_PRIORITY_TIME_THRESHOLD
- ATH_CABQ_READY_TIME
- ATH_CHANCTX_EVENT_ASSIGN
- ATH_CHANCTX_EVENT_AUTHORIZED
- ATH_CHANCTX_EVENT_BEACON_PREPARE
- ATH_CHANCTX_EVENT_BEACON_RECEIVED
- ATH_CHANCTX_EVENT_BEACON_SENT
- ATH_CHANCTX_EVENT_CHANGE
- ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL
- ATH_CHANCTX_EVENT_SWITCH
- ATH_CHANCTX_EVENT_TSF_TIMER
- ATH_CHANCTX_EVENT_UNASSIGN
- ATH_CHANCTX_STATE_FORCE_ACTIVE
- ATH_CHANCTX_STATE_IDLE
- ATH_CHANCTX_STATE_SWITCH
- ATH_CHANCTX_STATE_WAIT_FOR_BEACON
- ATH_CHANCTX_STATE_WAIT_FOR_TIMER
- ATH_CHAN_MAX
- ATH_CIPHER_AES_CCM
- ATH_CIPHER_AES_OCB
- ATH_CIPHER_CKIP
- ATH_CIPHER_CLR
- ATH_CIPHER_MIC
- ATH_CIPHER_TKIP
- ATH_CIPHER_WEP
- ATH_CRYPT_CAP_CIPHER_AESCCM
- ATH_CRYPT_CAP_MIC_COMBINED
- ATH_DBG_ANI
- ATH_DBG_ANY
- ATH_DBG_BEACON
- ATH_DBG_BSTUCK
- ATH_DBG_BTCOEX
- ATH_DBG_CALIBRATE
- ATH_DBG_CHAN_CTX
- ATH_DBG_CONFIG
- ATH_DBG_DEFAULT
- ATH_DBG_DFS
- ATH_DBG_DYNACK
- ATH_DBG_EEPROM
- ATH_DBG_FATAL
- ATH_DBG_INTERRUPT
- ATH_DBG_MAX_LEN
- ATH_DBG_MCI
- ATH_DBG_PS
- ATH_DBG_QUEUE
- ATH_DBG_REGULATORY
- ATH_DBG_RESET
- ATH_DBG_SPECTRAL_SCAN
- ATH_DBG_WARN
- ATH_DBG_WARN_ON_ONCE
- ATH_DBG_WMI
- ATH_DBG_WOW
- ATH_DBG_XMIT
- ATH_DEBUG
- ATH_DEFAULT_BINTVAL
- ATH_DEFAULT_BMISS_LIMIT
- ATH_DEFAULT_NOISE_FLOOR
- ATH_DESC_4KB_BOUND_CHECK
- ATH_DESC_4KB_BOUND_NUM_SKIPPED
- ATH_DUMP_BTCOEX
- ATH_DYN_BUF
- ATH_EP_MUL
- ATH_EP_RND
- ATH_FFT_SAMPLE_ATH10K
- ATH_FFT_SAMPLE_HT20
- ATH_FFT_SAMPLE_HT20_40
- ATH_H
- ATH_HTC_BTCOEX_PRODUCT_ID
- ATH_HTC_RATE_MAX
- ATH_HW_CHECK_POLL_INT
- ATH_HW_INITIALIZED
- ATH_HW_UNAVAILABLE
- ATH_INI_CORE
- ATH_INI_NUM_SPLIT
- ATH_INI_POST
- ATH_INI_PRE
- ATH_KEYMAX
- ATH_LED
- ATH_LED_PIN_7010
- ATH_LED_PIN_9271
- ATH_LED_PIN_9287
- ATH_LED_PIN_9300
- ATH_LED_PIN_9462
- ATH_LED_PIN_9485
- ATH_LED_PIN_DEF
- ATH_LONG_CALINTERVAL
- ATH_LONG_CALINTERVAL_INT
- ATH_LPF_RSSI
- ATH_MAX_GEN_TIMER
- ATH_MAX_SW_RETRIES
- ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED
- ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED
- ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED
- ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED
- ATH_MCI_ANT_ARCH_3_ANT
- ATH_MCI_BDR_DUTY_CYCLE
- ATH_MCI_CONCUR_TX_SWITCH
- ATH_MCI_CONFIG_AGGR_THRESH
- ATH_MCI_CONFIG_AGGR_THRESH_S
- ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN
- ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S
- ATH_MCI_CONFIG_ANT_ARCH
- ATH_MCI_CONFIG_ANT_ARCH_S
- ATH_MCI_CONFIG_CLK_DIV
- ATH_MCI_CONFIG_CLK_DIV_S
- ATH_MCI_CONFIG_CONCUR_TX
- ATH_MCI_CONFIG_DISABLE_AGGR_THRESH
- ATH_MCI_CONFIG_DISABLE_AIC
- ATH_MCI_CONFIG_DISABLE_FTP_STOMP
- ATH_MCI_CONFIG_DISABLE_MCI
- ATH_MCI_CONFIG_DISABLE_MCI_CAL
- ATH_MCI_CONFIG_DISABLE_OSLA
- ATH_MCI_CONFIG_DISABLE_TUNING
- ATH_MCI_CONFIG_FORCE_2CHAIN_ACK
- ATH_MCI_CONFIG_FORCE_QUIET_ACK
- ATH_MCI_CONFIG_FORCE_QUIET_ACK_S
- ATH_MCI_CONFIG_MCI_OBS_BT
- ATH_MCI_CONFIG_MCI_OBS_GPIO
- ATH_MCI_CONFIG_MCI_OBS_MASK
- ATH_MCI_CONFIG_MCI_OBS_MCI
- ATH_MCI_CONFIG_MCI_OBS_TXRX
- ATH_MCI_CONFIG_MCI_STAT_DBG
- ATH_MCI_CONFIG_MCI_WEIGHT_DBG
- ATH_MCI_CONFIG_NO_QUIET_ACK
- ATH_MCI_CONFIG_NO_QUIET_ACK_S
- ATH_MCI_DEF_AGGR_LIMIT
- ATH_MCI_DEF_BT_PERIOD
- ATH_MCI_GPM_BUF_SIZE
- ATH_MCI_GPM_MAX_ENTRY
- ATH_MCI_HI_PRIO
- ATH_MCI_INQUIRY_PRIO
- ATH_MCI_MAX_ACL_PROFILE
- ATH_MCI_MAX_DUTY_CYCLE
- ATH_MCI_MAX_PROFILE
- ATH_MCI_MAX_SCO_PROFILE
- ATH_MCI_NUM_BT_CHANNELS
- ATH_MCI_SCHED_BUF_SIZE
- ATH_NON_AGGR_MIN_QDEPTH
- ATH_OFFCHANNEL_IDLE
- ATH_OFFCHANNEL_PROBE_SEND
- ATH_OFFCHANNEL_PROBE_WAIT
- ATH_OFFCHANNEL_ROC_DONE
- ATH_OFFCHANNEL_ROC_START
- ATH_OFFCHANNEL_ROC_WAIT
- ATH_OFFCHANNEL_SUSPEND
- ATH_OP_ANI_RUN
- ATH_OP_BEACONS
- ATH_OP_HW_RESET
- ATH_OP_INVALID
- ATH_OP_MULTI_CHANNEL
- ATH_OP_PRIM_STA_VIF
- ATH_OP_SCANNING
- ATH_OP_WOW_ENABLED
- ATH_OUI_TYPE
- ATH_P2P_PS_STOP_TIME
- ATH_PAPRD_TIMEOUT
- ATH_PCI
- ATH_PCI_RESET_WAIT_MAX
- ATH_PHY_ID
- ATH_PIN
- ATH_PKTLOG_TYPE_TX_CTRL
- ATH_PKTLOG_TYPE_TX_STAT
- ATH_PLL_WORK_INTERVAL
- ATH_POLARITY
- ATH_RC_TX_STBC_FLAG
- ATH_REGISTERS_H
- ATH_RESTART_CALINTERVAL
- ATH_ROC_COMPLETE_ABORT
- ATH_ROC_COMPLETE_CANCEL
- ATH_ROC_COMPLETE_EXPIRE
- ATH_RSSI_DUMMY_MARKER
- ATH_RSSI_EP_MULTIPLIER
- ATH_RSSI_IN
- ATH_RSSI_LPF
- ATH_RSSI_LPF_LEN
- ATH_RXBUF
- ATH_SDEVICE
- ATH_STAT_INVALID
- ATH_STAT_LEDSOFT
- ATH_STAT_RESET
- ATH_STAT_STARTED
- ATH_STA_SHORT_CALINTERVAL
- ATH_SW_VER_BUILD
- ATH_SW_VER_MAJOR
- ATH_SW_VER_MINOR
- ATH_SW_VER_PATCH
- ATH_TID_MAX_BUFS
- ATH_TXBUF
- ATH_TXBUF_RESERVE
- ATH_TXBUF_RESET
- ATH_TXFIFO_DEPTH
- ATH_TXMAXTRY
- ATH_TXPOWER_MAX
- ATH_TXQ_AC_BE
- ATH_TXQ_AC_BK
- ATH_TXQ_AC_VI
- ATH_TXQ_AC_VO
- ATH_TXQ_SETUP
- ATH_TXSTATUS_RING_SIZE
- ATH_TX_ERROR
- ATH_USB
- ATH_USB_RX_STREAM_MODE_TAG
- ATH_USB_TX_STREAM_MODE_TAG
- ATH_WLANACTIVE_GPIO_9280
- ATH_WLANACTIVE_GPIO_9300
- ATI
- ATI2E
- ATI32
- ATI36
- ATI638
- ATID
- ATID_MASK
- ATID_SHIFT
- ATIF_CRT1
- ATIF_CRT2
- ATIF_CV
- ATIF_DFP1
- ATIF_DFP2
- ATIF_DFP3
- ATIF_DFP4
- ATIF_DFP5
- ATIF_DFP6
- ATIF_DGPU_DISPLAY_EVENT
- ATIF_DGPU_DISPLAY_EVENT_SUPPORTED
- ATIF_DISPLAY_CONF_CHANGE_REQUEST
- ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED
- ATIF_DISPLAY_SWITCH_REQUEST
- ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED
- ATIF_EXPANSION_MODE_CHANGE_REQUEST
- ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED
- ATIF_EXTERNAL_GRAPHICS_PORT
- ATIF_FORCED_POWER_STATE_CHANGE_REQUEST
- ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED
- ATIF_FUNCTION_GET_EXTERNAL_GPU_INFORMATION
- ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES
- ATIF_FUNCTION_GET_LID_STATE
- ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS
- ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS
- ATIF_FUNCTION_GET_SYSTEM_PARAMETERS
- ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS
- ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
- ATIF_FUNCTION_READY_TO_UNDOCK_NOTIFICATION
- ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS
- ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS
- ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS
- ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION
- ATIF_FUNCTION_VERIFY_INTERFACE
- ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED
- ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED
- ATIF_GET_LID_STATE_SUPPORTED
- ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED
- ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED
- ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED
- ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED
- ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST
- ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED
- ATIF_LCD1
- ATIF_LCD2
- ATIF_NOTIFY_81
- ATIF_NOTIFY_MASK
- ATIF_NOTIFY_N
- ATIF_NOTIFY_NONE
- ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST
- ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED
- ATIF_PANEL_EXPANSION_ASPECT
- ATIF_PANEL_EXPANSION_DISABLE
- ATIF_PANEL_EXPANSION_FULL
- ATIF_POWER_SOURCE_AC
- ATIF_POWER_SOURCE_DC
- ATIF_POWER_SOURCE_RESTRICTED_AC_1
- ATIF_POWER_SOURCE_RESTRICTED_AC_2
- ATIF_PROBE
- ATIF_PROBE_FAIL
- ATIF_PX_GFX_SWITCH_REQUEST
- ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED
- ATIF_PX_REMOVABLE_GRAPHICS_DEVICE
- ATIF_QBTC_ERROR_CODE_DEVICE_NOT_SUPPORTED
- ATIF_QBTC_ERROR_CODE_FAILURE
- ATIF_QBTC_ERROR_CODE_SUCCESS
- ATIF_QBTC_MAX_DATA_POINTS
- ATIF_QBTC_REQUEST_CRT1
- ATIF_QBTC_REQUEST_CRT2
- ATIF_QBTC_REQUEST_DFP1
- ATIF_QBTC_REQUEST_DFP2
- ATIF_QBTC_REQUEST_DFP3
- ATIF_QBTC_REQUEST_DFP4
- ATIF_QBTC_REQUEST_DFP5
- ATIF_QBTC_REQUEST_DFP6
- ATIF_QBTC_REQUEST_LCD1
- ATIF_QBTC_REQUEST_LCD2
- ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED
- ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED
- ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED
- ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED
- ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED
- ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST
- ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED
- ATIF_TARGET_GFX_PX_DGPU
- ATIF_TARGET_GFX_PX_IGPU
- ATIF_TARGET_GFX_SINGLE
- ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED
- ATIF_THERMAL_STATE_CHANGE_REQUEST
- ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED
- ATIF_TV
- ATIF_TV_STD_NTSC
- ATIF_TV_STD_NTSCJ
- ATIF_TV_STD_PAL
- ATIF_TV_STD_PAL60
- ATIF_TV_STD_PALCN
- ATIF_TV_STD_PALM
- ATIF_TV_STD_PALN
- ATIF_TV_STD_SCART_RGB
- ATIF_VGA_ENABLED_GRAPHICS_DEVICE
- ATIF_XGP_PORT
- ATIF_XGP_PORT_IN_DOCK
- ATIHDMI_NUM_CAPTURE
- ATIHDMI_NUM_PLAYBACK
- ATIIXP_IDE_MDMA_TIMING
- ATIIXP_IDE_MWDMA_TIMING
- ATIIXP_IDE_PIO_CONTROL
- ATIIXP_IDE_PIO_MODE
- ATIIXP_IDE_PIO_TIMING
- ATIIXP_IDE_UDMA_CONTROL
- ATIIXP_IDE_UDMA_MODE
- ATIMPTR
- ATIMWND
- ATIM_WINDOW
- ATIOCTL_H
- ATIO_ACA_QUEUE
- ATIO_CANT_PROV_CAP
- ATIO_CDB_VALID
- ATIO_ENTRY_CNT_24XX
- ATIO_EXCHANGE_ADDRESS_UNKNOWN
- ATIO_EXEC_READ
- ATIO_EXEC_WRITE
- ATIO_HEAD_OF_QUEUE
- ATIO_ORDERED_QUEUE
- ATIO_PATH_INVALID
- ATIO_PROCESSED
- ATIO_SIMPLE_QUEUE
- ATIO_TYPE7
- ATIO_UNTAGGED
- ATIReduceRatio
- ATIXL_BUSMOUSE_MINOR
- ATI_AUDIODESC_CHANNELS
- ATI_AUDIODESC_LPCM_STEREO_RATES
- ATI_AUDIODESC_RATES
- ATI_CHIP_264CT
- ATI_CHIP_264ET
- ATI_CHIP_264GT
- ATI_CHIP_264GT2C
- ATI_CHIP_264GTB
- ATI_CHIP_264GTPRO
- ATI_CHIP_264LT
- ATI_CHIP_264LTG
- ATI_CHIP_264LTPRO
- ATI_CHIP_264VT
- ATI_CHIP_264VT3
- ATI_CHIP_264VT4
- ATI_CHIP_264VTB
- ATI_CHIP_264XL
- ATI_CHIP_88800CX
- ATI_CHIP_88800GX
- ATI_CHIP_MOBILITY
- ATI_DATATYPE_ARGB1555
- ATI_DATATYPE_ARGB4444
- ATI_DATATYPE_ARGB8888
- ATI_DATATYPE_AYUV_444
- ATI_DATATYPE_CI16
- ATI_DATATYPE_CI4
- ATI_DATATYPE_CI8
- ATI_DATATYPE_RGB332
- ATI_DATATYPE_RGB565
- ATI_DATATYPE_RGB8
- ATI_DATATYPE_RGB888
- ATI_DATATYPE_VQ
- ATI_DATATYPE_VYUY_422
- ATI_DATATYPE_Y8
- ATI_DATATYPE_YVYU_422
- ATI_DELAY_AUDIO_LATENCY
- ATI_DELAY_VIDEO_LATENCY
- ATI_DESC_LIST_SIZE
- ATI_DEVICE_ID
- ATI_DMA_CAPTURE
- ATI_DMA_PLAYBACK
- ATI_DMA_SPDIF
- ATI_FORCE_HPET_RESUME
- ATI_GART_BASE
- ATI_GART_CACHE_CNTRL
- ATI_GART_CACHE_ENTRY_CNTRL
- ATI_GART_CACHE_SZBASE
- ATI_GART_FEATURE_ID
- ATI_GART_MMBASE_BAR
- ATI_HBR_CAPABLE
- ATI_HBR_ENABLE
- ATI_INFO_IDX_MANUFACTURER_ID
- ATI_INFO_IDX_PORT_ID_HIGH
- ATI_INFO_IDX_PORT_ID_LOW
- ATI_INFO_IDX_PRODUCT_ID
- ATI_INFO_IDX_SINK_DESC_FIRST
- ATI_INFO_IDX_SINK_DESC_LAST
- ATI_INFO_IDX_SINK_DESC_LEN
- ATI_MAX_DESCRIPTORS
- ATI_MODERN_SET
- ATI_MULTICHANNEL_MODE_PAIRED
- ATI_MULTICHANNEL_MODE_SINGLE
- ATI_OUT_ENABLE
- ATI_PCIGART_PAGE_SIZE
- ATI_PCMDEV_ANALOG
- ATI_PCMDEV_DIGITAL
- ATI_PCM_IN
- ATI_PCM_OUT
- ATI_PCM_SPDIF
- ATI_REG_6CH_REORDER
- ATI_REG_6CH_REORDER_EN
- ATI_REG_AUDIO_MIRROR
- ATI_REG_CMD
- ATI_REG_CMD_ACLINK_ACTIVE
- ATI_REG_CMD_AC_RESET
- ATI_REG_CMD_AC_SOFT_RESET
- ATI_REG_CMD_AC_SYNC
- ATI_REG_CMD_AUDIO_PRESENT
- ATI_REG_CMD_BURST_EN
- ATI_REG_CMD_INTERLEAVE_IN
- ATI_REG_CMD_INTERLEAVE_OUT
- ATI_REG_CMD_INTERLEAVE_SPDF
- ATI_REG_CMD_IN_DMA_EN
- ATI_REG_CMD_LOOPBACK_EN
- ATI_REG_CMD_MODEM_GPIO_THRU_DMA
- ATI_REG_CMD_MODEM_IN_DMA_EN
- ATI_REG_CMD_MODEM_OUT_DMA1_EN
- ATI_REG_CMD_MODEM_OUT_DMA2_EN
- ATI_REG_CMD_MODEM_OUT_DMA3_EN
- ATI_REG_CMD_MODEM_PRESENT
- ATI_REG_CMD_MODEM_RECEIVE_EN
- ATI_REG_CMD_MODEM_SEND1_EN
- ATI_REG_CMD_MODEM_SEND2_EN
- ATI_REG_CMD_MODEM_SEND3_EN
- ATI_REG_CMD_MODEM_STATUS_MEM
- ATI_REG_CMD_OUT_DMA_EN
- ATI_REG_CMD_PACKED_DIS
- ATI_REG_CMD_PANIC_EN
- ATI_REG_CMD_POWERDOWN
- ATI_REG_CMD_RECEIVE_EN
- ATI_REG_CMD_SEND_EN
- ATI_REG_CMD_SPDF_CONFIG_01
- ATI_REG_CMD_SPDF_CONFIG_34
- ATI_REG_CMD_SPDF_CONFIG_69
- ATI_REG_CMD_SPDF_CONFIG_78
- ATI_REG_CMD_SPDF_CONFIG_MASK
- ATI_REG_CMD_SPDF_DMA_EN
- ATI_REG_CMD_SPDF_OUT_EN
- ATI_REG_CMD_SPDF_OUT_STOPPED
- ATI_REG_CMD_SPDF_STATUS_MEM
- ATI_REG_CMD_SPDF_THRESHOLD
- ATI_REG_CMD_SPDF_THRESHOLD_SHIFT
- ATI_REG_CMD_STATUS_MEM
- ATI_REG_COUNTER
- ATI_REG_COUNTER_BITCLOCK
- ATI_REG_COUNTER_SLOT
- ATI_REG_DMA_DT_SIZE
- ATI_REG_DMA_FIFO_FREE
- ATI_REG_DMA_FIFO_USED
- ATI_REG_DMA_STATE
- ATI_REG_FIFO_FLUSH
- ATI_REG_FIFO_IN_FLUSH
- ATI_REG_FIFO_OUT_FLUSH
- ATI_REG_IER
- ATI_REG_IER_CODEC0_INTR_EN
- ATI_REG_IER_CODEC1_INTR_EN
- ATI_REG_IER_CODEC2_INTR_EN
- ATI_REG_IER_IN_XRUN_EN
- ATI_REG_IER_IO_STATUS_EN
- ATI_REG_IER_MODEM_GPIO_DATA_EN
- ATI_REG_IER_MODEM_IN_XRUN_EN
- ATI_REG_IER_MODEM_OUT1_XRUN_EN
- ATI_REG_IER_MODEM_OUT2_XRUN_EN
- ATI_REG_IER_MODEM_OUT3_XRUN_EN
- ATI_REG_IER_MODEM_SET_BUS_BUSY
- ATI_REG_IER_MODEM_STATUS_EN
- ATI_REG_IER_NEW_FRAME_EN
- ATI_REG_IER_OUT_XRUN_COND
- ATI_REG_IER_OUT_XRUN_EN
- ATI_REG_IER_PHYS_INTR_EN
- ATI_REG_IER_PHYS_MISMATCH_EN
- ATI_REG_IER_SET_BUS_BUSY
- ATI_REG_IER_SPDF_STATUS_EN
- ATI_REG_IER_SPDF_XRUN_EN
- ATI_REG_IN_DMA_DT_CUR
- ATI_REG_IN_DMA_DT_NEXT
- ATI_REG_IN_DMA_DT_SIZE
- ATI_REG_IN_DMA_DT_START
- ATI_REG_IN_DMA_LINKPTR
- ATI_REG_IN_FIFO_THRESHOLD
- ATI_REG_ISR
- ATI_REG_ISR_CODEC0_NOT_READY
- ATI_REG_ISR_CODEC1_NOT_READY
- ATI_REG_ISR_CODEC2_NOT_READY
- ATI_REG_ISR_IN_STATUS
- ATI_REG_ISR_IN_XRUN
- ATI_REG_ISR_MODEM_GPIO_DATA
- ATI_REG_ISR_MODEM_IN_STATUS
- ATI_REG_ISR_MODEM_IN_XRUN
- ATI_REG_ISR_MODEM_OUT1_STATUS
- ATI_REG_ISR_MODEM_OUT1_XRUN
- ATI_REG_ISR_MODEM_OUT2_STATUS
- ATI_REG_ISR_MODEM_OUT2_XRUN
- ATI_REG_ISR_MODEM_OUT3_STATUS
- ATI_REG_ISR_MODEM_OUT3_XRUN
- ATI_REG_ISR_NEW_FRAME
- ATI_REG_ISR_OUT_STATUS
- ATI_REG_ISR_OUT_XRUN
- ATI_REG_ISR_PHYS_INTR
- ATI_REG_ISR_PHYS_MISMATCH
- ATI_REG_ISR_SPDF_STATUS
- ATI_REG_ISR_SPDF_XRUN
- ATI_REG_LINKPTR_EN
- ATI_REG_MODEM_FIFO_FLUSH
- ATI_REG_MODEM_FIFO_IN_FLUSH
- ATI_REG_MODEM_FIFO_OUT1_FLUSH
- ATI_REG_MODEM_FIFO_OUT2_FLUSH
- ATI_REG_MODEM_FIFO_OUT3_FLUSH
- ATI_REG_MODEM_IN_DMA_DT_CUR
- ATI_REG_MODEM_IN_DMA_DT_NEXT
- ATI_REG_MODEM_IN_DMA_DT_SIZE
- ATI_REG_MODEM_IN_DMA_DT_START
- ATI_REG_MODEM_IN_DMA_LINKPTR
- ATI_REG_MODEM_IN_GPIO
- ATI_REG_MODEM_MIRROR
- ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK
- ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT
- ATI_REG_MODEM_OUT_DMA12_DT_SIZE
- ATI_REG_MODEM_OUT_DMA1_DT_CUR
- ATI_REG_MODEM_OUT_DMA1_DT_NEXT
- ATI_REG_MODEM_OUT_DMA1_DT_START
- ATI_REG_MODEM_OUT_DMA1_LINKPTR
- ATI_REG_MODEM_OUT_DMA2_DT_CUR
- ATI_REG_MODEM_OUT_DMA2_DT_NEXT
- ATI_REG_MODEM_OUT_DMA2_DT_START
- ATI_REG_MODEM_OUT_DMA2_LINKPTR
- ATI_REG_MODEM_OUT_DMA3_DT_CUR
- ATI_REG_MODEM_OUT_DMA3_DT_NEXT
- ATI_REG_MODEM_OUT_DMA3_DT_SIZE
- ATI_REG_MODEM_OUT_DMA3_DT_START
- ATI_REG_MODEM_OUT_DMA3_LINKPTR
- ATI_REG_MODEM_OUT_FIFO
- ATI_REG_MODEM_OUT_FIFO_USED
- ATI_REG_MODEM_OUT_GPIO
- ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT
- ATI_REG_MODEM_OUT_GPIO_EN
- ATI_REG_OUT_DMA_DT_CUR
- ATI_REG_OUT_DMA_DT_NEXT
- ATI_REG_OUT_DMA_DT_SIZE
- ATI_REG_OUT_DMA_DT_START
- ATI_REG_OUT_DMA_LINKPTR
- ATI_REG_OUT_DMA_SLOT
- ATI_REG_OUT_DMA_SLOT_BIT
- ATI_REG_OUT_DMA_SLOT_MASK
- ATI_REG_OUT_DMA_THRESHOLD_MASK
- ATI_REG_OUT_DMA_THRESHOLD_SHIFT
- ATI_REG_PHYS_IN_ADDR
- ATI_REG_PHYS_IN_ADDR_SHIFT
- ATI_REG_PHYS_IN_DATA_SHIFT
- ATI_REG_PHYS_IN_READ_FLAG
- ATI_REG_PHYS_OUT_ADDR
- ATI_REG_PHYS_OUT_ADDR_EN
- ATI_REG_PHYS_OUT_ADDR_SHIFT
- ATI_REG_PHYS_OUT_CODEC_MASK
- ATI_REG_PHYS_OUT_DATA_SHIFT
- ATI_REG_PHYS_OUT_RW
- ATI_REG_SLOTREQ
- ATI_REG_SPDF_CMD
- ATI_REG_SPDF_CMD_LFSR
- ATI_REG_SPDF_CMD_LFSR_ACC
- ATI_REG_SPDF_CMD_SINGLE_CH
- ATI_REG_SPDF_DMA_DT_CUR
- ATI_REG_SPDF_DMA_DT_NEXT
- ATI_REG_SPDF_DMA_DT_SIZE
- ATI_REG_SPDF_DMA_DT_START
- ATI_REG_SPDF_DMA_LINKPTR
- ATI_REMOTE2_AUX1
- ATI_REMOTE2_AUX2
- ATI_REMOTE2_AUX3
- ATI_REMOTE2_AUX4
- ATI_REMOTE2_MAX_CHANNEL_MASK
- ATI_REMOTE2_MAX_MODE_MASK
- ATI_REMOTE2_MODES
- ATI_REMOTE2_OPENED
- ATI_REMOTE2_PC
- ATI_REMOTE2_SUSPENDED
- ATI_REMOTE_PRODUCT_ID
- ATI_REMOTE_VENDOR_ID
- ATI_REV_ID_FUSE_MACRO__ADDRESS
- ATI_REV_ID_FUSE_MACRO__MASK
- ATI_REV_ID_FUSE_MACRO__SHIFT
- ATI_REV_ID_MASK
- ATI_REV_ID_SHIFT
- ATI_RS100_APSIZE
- ATI_RS100_IG_AGPMODE
- ATI_RS300_APSIZE
- ATI_RS300_IG_AGPMODE
- ATI_SB450_HDAUDIO_ENABLE_SNOOP
- ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
- ATI_SPKALLOC_SPKALLOC
- ATI_SPKALLOC_TYPE_DISPLAYPORT
- ATI_SPKALLOC_TYPE_HDMI
- ATI_VENDOR_ID
- ATI_VERB_GET_AUDIO_DESCRIPTOR
- ATI_VERB_GET_AUDIO_VIDEO_DELAY
- ATI_VERB_GET_CHANNEL_ALLOCATION
- ATI_VERB_GET_DOWNMIX_INFO
- ATI_VERB_GET_HBR_CONTROL
- ATI_VERB_GET_MULTICHANNEL_01
- ATI_VERB_GET_MULTICHANNEL_1
- ATI_VERB_GET_MULTICHANNEL_23
- ATI_VERB_GET_MULTICHANNEL_3
- ATI_VERB_GET_MULTICHANNEL_45
- ATI_VERB_GET_MULTICHANNEL_5
- ATI_VERB_GET_MULTICHANNEL_67
- ATI_VERB_GET_MULTICHANNEL_7
- ATI_VERB_GET_MULTICHANNEL_MODE
- ATI_VERB_GET_RAMP_RATE
- ATI_VERB_GET_SINK_INFO_DATA
- ATI_VERB_GET_SINK_INFO_INDEX
- ATI_VERB_GET_SPEAKER_ALLOCATION
- ATI_VERB_SET_AUDIO_DESCRIPTOR
- ATI_VERB_SET_CHANNEL_ALLOCATION
- ATI_VERB_SET_DOWNMIX_INFO
- ATI_VERB_SET_HBR_CONTROL
- ATI_VERB_SET_MULTICHANNEL_01
- ATI_VERB_SET_MULTICHANNEL_1
- ATI_VERB_SET_MULTICHANNEL_23
- ATI_VERB_SET_MULTICHANNEL_3
- ATI_VERB_SET_MULTICHANNEL_45
- ATI_VERB_SET_MULTICHANNEL_5
- ATI_VERB_SET_MULTICHANNEL_67
- ATI_VERB_SET_MULTICHANNEL_7
- ATI_VERB_SET_MULTICHANNEL_MODE
- ATI_VERB_SET_RAMP_RATE
- ATI_VERB_SET_SINK_INFO_INDEX
- ATI_W3220_PHYS
- ATKBD_CMD_ENABLE
- ATKBD_CMD_EX_ENABLE
- ATKBD_CMD_EX_SETLEDS
- ATKBD_CMD_GETID
- ATKBD_CMD_GSCANSET
- ATKBD_CMD_OK_GETID
- ATKBD_CMD_RESEND
- ATKBD_CMD_RESET_BAT
- ATKBD_CMD_RESET_DEF
- ATKBD_CMD_RESET_DIS
- ATKBD_CMD_SETALL_MB
- ATKBD_CMD_SETALL_MBR
- ATKBD_CMD_SETLEDS
- ATKBD_CMD_SETREP
- ATKBD_CMD_SSCANSET
- ATKBD_DEFINE_ATTR
- ATKBD_DEFINE_RO_ATTR
- ATKBD_KEYMAP_SIZE
- ATKBD_KEY_NULL
- ATKBD_KEY_UNKNOWN
- ATKBD_LED_EVENT_BIT
- ATKBD_REP_EVENT_BIT
- ATKBD_RET_ACK
- ATKBD_RET_BAT
- ATKBD_RET_EMUL0
- ATKBD_RET_EMUL1
- ATKBD_RET_ERR
- ATKBD_RET_HANGEUL
- ATKBD_RET_HANJA
- ATKBD_RET_NAK
- ATKBD_RET_RELEASE
- ATKBD_SCR_1
- ATKBD_SCR_2
- ATKBD_SCR_4
- ATKBD_SCR_8
- ATKBD_SCR_CLICK
- ATKBD_SCR_LEFT
- ATKBD_SCR_RIGHT
- ATKBD_SPECIAL
- ATKBD_XL_ACK
- ATKBD_XL_BAT
- ATKBD_XL_ERR
- ATKBD_XL_HANGEUL
- ATKBD_XL_HANJA
- ATKBD_XL_NAK
- ATKD_BRNDOWN
- ATKD_BRNDOWN_MAX
- ATKD_BRNDOWN_MIN
- ATKD_BRNUP
- ATKD_BRNUP_MAX
- ATKD_BRNUP_MIN
- ATKD_LCD_OFF
- ATKD_LCD_ON
- ATKHLDM
- ATKHLDM_ATTACKTIME
- ATKHLDM_HOLDTIME
- ATKHLDM_PHASE0
- ATKHLDV
- ATKHLDV_ATTACKTIME_MASK
- ATKHLDV_HOLDTIME_MASK
- ATKHLDV_PHASE0
- ATK_CLASS_FAN_CTL
- ATK_CLASS_FREQ_CTL
- ATK_CLASS_HWMON
- ATK_CLASS_MASK
- ATK_CLASS_MGMT
- ATK_EC_ID
- ATK_ELEMENT_ID_MASK
- ATK_HID
- ATK_MUX_HWMON
- ATK_MUX_MGMT
- ATK_TYPE_MASK
- ATL1C_APS_MODE_ENABLE
- ATL1C_ASPM_CTRL_MON
- ATL1C_ASPM_L0S_SUPPORT
- ATL1C_ASPM_L0s_ENABLE
- ATL1C_ASPM_L1_ENABLE
- ATL1C_ASPM_L1_SUPPORT
- ATL1C_BUFFER_BUSY
- ATL1C_BUFFER_FREE
- ATL1C_BUFFER_STATE_MASK
- ATL1C_CLK_GATING_EN
- ATL1C_CMB_ENABLE
- ATL1C_DRV_VERSION
- ATL1C_FPGA_VERSION
- ATL1C_GET_DESC
- ATL1C_HIB_DISABLE
- ATL1C_INTR_CLEAR_ON_READ
- ATL1C_INTR_MODRT_ENABLE
- ATL1C_LINK_CAP_1000M
- ATL1C_LINK_EXT_SYNC
- ATL1C_LINK_PATCH
- ATL1C_PCIE_L0S_L1_DISABLE
- ATL1C_PCIE_PHY_RESET
- ATL1C_PCIMAP_DIRECTION_MASK
- ATL1C_PCIMAP_FROMDEVICE
- ATL1C_PCIMAP_PAGE
- ATL1C_PCIMAP_SINGLE
- ATL1C_PCIMAP_TODEVICE
- ATL1C_PCIMAP_TYPE_MASK
- ATL1C_RFD_DESC
- ATL1C_RRD_DESC
- ATL1C_RX_IPV6_CHKSUM
- ATL1C_SET_BUFFER_STATE
- ATL1C_SET_PCIMAP_TYPE
- ATL1C_SMB_ENABLE
- ATL1C_TPD_DESC
- ATL1C_TXQ_MODE_ENHANCE
- ATL1C_WORK_EVENT_LINK_CHANGE
- ATL1C_WORK_EVENT_RESET
- ATL1E_DEFAULT_RX_MEM_SIZE
- ATL1E_DEFAULT_TX_DESC_CNT
- ATL1E_MAX_NIC
- ATL1E_MAX_RX_MEM_SIZE
- ATL1E_MAX_TX_DESC_CNT
- ATL1E_MIN_RX_MEM_SIZE
- ATL1E_MIN_TX_DESC_CNT
- ATL1E_PARAM
- ATL1E_PARAM_INIT
- ATL1E_SET_PCIMAP_TYPE
- ATL1E_TX_PCIMAP_PAGE
- ATL1E_TX_PCIMAP_SINGLE
- ATL1E_TX_PCIMAP_TYPE_MASK
- ATL1_DEFAULT_RFD
- ATL1_DEFAULT_TPD
- ATL1_EEDUMP_LEN
- ATL1_GET_DESC
- ATL1_H
- ATL1_MAX_INTR
- ATL1_MAX_NIC
- ATL1_MAX_RFD
- ATL1_MAX_TPD
- ATL1_MAX_TX_BUF_LEN
- ATL1_MIN_RFD
- ATL1_MIN_TPD
- ATL1_PARAM_INIT
- ATL1_REG_COUNT
- ATL1_RFD_DESC
- ATL1_RRD_DESC
- ATL1_STAT
- ATL1_TPD_DESC
- ATL2_DEFAULT_RXD_COUNT
- ATL2_DEFAULT_TX_MEMSIZE
- ATL2_DRV_VERSION
- ATL2_MAX_NIC
- ATL2_MAX_RXD_COUNT
- ATL2_MAX_TX_MEMSIZE
- ATL2_MIN_RXD_COUNT
- ATL2_MIN_TX_MEMSIZE
- ATL2_PARAM
- ATL2_PARAM_INIT
- ATL2_READ_REG
- ATL2_READ_REGB
- ATL2_READ_REGW
- ATL2_READ_REG_ARRAY
- ATL2_REGS_LEN
- ATL2_WRITE_FLUSH
- ATL2_WRITE_REG
- ATL2_WRITE_REGB
- ATL2_WRITE_REGW
- ATL2_WRITE_REG_ARRAY
- ATLAS6_CODEC_ENABLE_BITS
- ATLAS6_CODEC_RESET_BITS
- ATLAS7_GPIO_BASE
- ATLAS7_GPIO_CTL_DATAIN_MASK
- ATLAS7_GPIO_CTL_DATAOUT_MASK
- ATLAS7_GPIO_CTL_INTR_EN_MASK
- ATLAS7_GPIO_CTL_INTR_HIGH_MASK
- ATLAS7_GPIO_CTL_INTR_LOW_MASK
- ATLAS7_GPIO_CTL_INTR_STATUS_MASK
- ATLAS7_GPIO_CTL_INTR_TYPE_MASK
- ATLAS7_GPIO_CTL_OUT_EN_MASK
- ATLAS7_GPIO_CTRL
- ATLAS7_GPIO_INT_STATUS
- ATLAS7_PINCTRL_BANK_0_PINS
- ATLAS7_PINCTRL_BANK_1_PINS
- ATLAS7_PINCTRL_REG_BANKS
- ATLAS7_PINCTRL_TOTAL_PINS
- ATLAS7_TIMER_WDT_INDEX
- ATLAS7_WDT_CNT
- ATLAS7_WDT_CNT_CTRL
- ATLAS7_WDT_CNT_EN
- ATLAS7_WDT_CNT_MATCH
- ATLAS7_WDT_DEFAULT_TIMEOUT
- ATLAS7_WDT_EN
- ATLAS_DRV_NAME
- ATLAS_EC_CHANNEL
- ATLAS_EC_INT_TIME_IN_MS
- ATLAS_EC_SM
- ATLAS_INTR_SPREAD_BLOCKING_DURATION
- ATLAS_INTR_SPREAD_ENABLE
- ATLAS_INTR_SPREAD_USE_STANDBYWFI
- ATLAS_NR_CLK
- ATLAS_ORP_INT_TIME_IN_MS
- ATLAS_ORP_SM
- ATLAS_P0_P1_CFIFO_ENTRIES
- ATLAS_P0_P1_DFIFO_ENTRIES
- ATLAS_P2_P3_CFIFO_ENTRIES
- ATLAS_P2_P3_DFIFO_ENTRIES
- ATLAS_PH_INT_TIME_IN_MS
- ATLAS_PH_SM
- ATLAS_PLL_CON0
- ATLAS_PLL_CON1
- ATLAS_PLL_FREQ_DET
- ATLAS_PLL_LOCK
- ATLAS_PWR_CTRL
- ATLAS_PWR_CTRL2
- ATLAS_REGMAP_NAME
- ATLAS_REG_DEV_TYPE
- ATLAS_REG_DEV_VERSION
- ATLAS_REG_EC_CALIB_STATUS
- ATLAS_REG_EC_CALIB_STATUS_DRY
- ATLAS_REG_EC_CALIB_STATUS_HIGH
- ATLAS_REG_EC_CALIB_STATUS_LOW
- ATLAS_REG_EC_CALIB_STATUS_MASK
- ATLAS_REG_EC_CALIB_STATUS_SINGLE
- ATLAS_REG_EC_DATA
- ATLAS_REG_EC_PROBE
- ATLAS_REG_EC_TEMP_DATA
- ATLAS_REG_INT_CONTROL
- ATLAS_REG_INT_CONTROL_EN
- ATLAS_REG_ORP_CALIB_STATUS
- ATLAS_REG_ORP_DATA
- ATLAS_REG_PH_CALIB_STATUS
- ATLAS_REG_PH_CALIB_STATUS_HIGH
- ATLAS_REG_PH_CALIB_STATUS_LOW
- ATLAS_REG_PH_CALIB_STATUS_MASK
- ATLAS_REG_PH_CALIB_STATUS_MID
- ATLAS_REG_PH_DATA
- ATLAS_REG_PH_TEMP_DATA
- ATLAS_REG_PSS_DATA
- ATLAS_REG_PWR_CONTROL
- ATLAS_REG_TDS_DATA
- ATLX_C
- ATLX_DRIVER_NAME
- ATLX_DRIVER_VERSION
- ATLX_ERR_PHY
- ATLX_ERR_PHY_RES
- ATLX_ERR_PHY_SPEED
- ATLX_H
- ATLX_WUFC_BC
- ATLX_WUFC_EX
- ATLX_WUFC_LNKC
- ATLX_WUFC_MAG
- ATLX_WUFC_MC
- ATL_BUF_FILL
- ATL_PTD_OFFSET
- ATMARPD_CTRL
- ATMARP_ENCAP
- ATMARP_MAX_UNRES_PACKETS
- ATMARP_MKIP
- ATMARP_RETRY_DELAY
- ATMARP_SETENTRY
- ATMCI_ACKRCV
- ATMCI_ACKRCVE
- ATMCI_ARGR
- ATMCI_BCNT
- ATMCI_BLKE
- ATMCI_BLKLEN
- ATMCI_BLKOVRE
- ATMCI_BLKR
- ATMCI_CARD_NEED_INIT
- ATMCI_CARD_PRESENT
- ATMCI_CFG
- ATMCI_CFG_FERRCTRL_COR
- ATMCI_CFG_FIFOMODE_1DATA
- ATMCI_CFG_HSMODE
- ATMCI_CFG_LSYNC
- ATMCI_CMDR
- ATMCI_CMDRDY
- ATMCI_CMDR_BLOCK
- ATMCI_CMDR_CMDNB
- ATMCI_CMDR_MAXLAT_5CYC
- ATMCI_CMDR_MAXLAT_64CYC
- ATMCI_CMDR_MULTI_BLOCK
- ATMCI_CMDR_OPDCMD
- ATMCI_CMDR_RSPTYP_136BIT
- ATMCI_CMDR_RSPTYP_48BIT
- ATMCI_CMDR_RSPTYP_NONE
- ATMCI_CMDR_SDIO_BLOCK
- ATMCI_CMDR_SDIO_BYTE
- ATMCI_CMDR_SDIO_RESUME
- ATMCI_CMDR_SDIO_SUSPEND
- ATMCI_CMDR_SPCMD_INIT
- ATMCI_CMDR_SPCMD_INT
- ATMCI_CMDR_SPCMD_INTRESP
- ATMCI_CMDR_SPCMD_SYNC
- ATMCI_CMDR_START_XFER
- ATMCI_CMDR_STOP_XFER
- ATMCI_CMDR_STREAM
- ATMCI_CMDR_TRDIR_READ
- ATMCI_CMDR_TRDIR_WRITE
- ATMCI_CR
- ATMCI_CR_MCIDIS
- ATMCI_CR_MCIEN
- ATMCI_CR_PWSDIS
- ATMCI_CR_PWSEN
- ATMCI_CR_SWRST
- ATMCI_CSRCV
- ATMCI_CSTOCYC
- ATMCI_CSTOE
- ATMCI_CSTOMUL
- ATMCI_CSTOR
- ATMCI_DATA_ERROR_FLAGS
- ATMCI_DCRCE
- ATMCI_DMA
- ATMCI_DMADONE
- ATMCI_DMAEN
- ATMCI_DMA_CHKSIZE
- ATMCI_DMA_OFFSET
- ATMCI_DMA_THRESHOLD
- ATMCI_DTIP
- ATMCI_DTOCYC
- ATMCI_DTOE
- ATMCI_DTOMUL
- ATMCI_DTOR
- ATMCI_ENDRX
- ATMCI_ENDTX
- ATMCI_FIFOEMPTY
- ATMCI_FIFO_APERTURE
- ATMCI_GET_WP_VS
- ATMCI_GET_WP_VSRC
- ATMCI_IDR
- ATMCI_IER
- ATMCI_IMR
- ATMCI_MAX_NR_SLOTS
- ATMCI_MR
- ATMCI_MR_CLKDIV
- ATMCI_MR_CLKODD
- ATMCI_MR_PDCFBYTE
- ATMCI_MR_PDCMODE
- ATMCI_MR_PDCPADV
- ATMCI_MR_PWSDIV
- ATMCI_MR_RDPROOF
- ATMCI_MR_WRPROOF
- ATMCI_NOTBUSY
- ATMCI_OVRE
- ATMCI_RCRCE
- ATMCI_RDIRE
- ATMCI_RDR
- ATMCI_REGS_SIZE
- ATMCI_RENDE
- ATMCI_RINDE
- ATMCI_RSPR
- ATMCI_RSPR1
- ATMCI_RSPR2
- ATMCI_RSPR3
- ATMCI_RTOE
- ATMCI_RXBUFF
- ATMCI_RXRDY
- ATMCI_SDCBUS_1BIT
- ATMCI_SDCBUS_4BIT
- ATMCI_SDCBUS_8BIT
- ATMCI_SDCBUS_MASK
- ATMCI_SDCR
- ATMCI_SDCSEL_MASK
- ATMCI_SDCSEL_SLOT_A
- ATMCI_SDCSEL_SLOT_B
- ATMCI_SDIOIRQA
- ATMCI_SDIOIRQB
- ATMCI_SDIOWAIT
- ATMCI_SHUTDOWN
- ATMCI_SR
- ATMCI_TDR
- ATMCI_TXBUFE
- ATMCI_TXRDY
- ATMCI_UNRE
- ATMCI_VERSION
- ATMCI_WPMR
- ATMCI_WPSR
- ATMCI_WP_EN
- ATMCI_WP_KEY
- ATMCI_XFRDONE
- ATMELFWL
- ATMELIDIFC
- ATMELMAGIC
- ATMELRD
- ATMEL_16M
- ATMEL_1M
- ATMEL_4M_2M
- ATMEL_8M
- ATMEL_AC97C_PM_OPS
- ATMEL_ADC_TOUCHSCREEN_4WIRE
- ATMEL_ADC_TOUCHSCREEN_5WIRE
- ATMEL_ADC_TOUCHSCREEN_NONE
- ATMEL_AES_BUFFER_ORDER
- ATMEL_AES_BUFFER_SIZE
- ATMEL_AES_DMA_THRESHOLD
- ATMEL_AES_PRIORITY
- ATMEL_AES_QUEUE_LENGTH
- ATMEL_AT24C02_CHIP_SIZE
- ATMEL_AT24C02_PAGE_SIZE
- ATMEL_AT24C512_CHIP_SIZE
- ATMEL_AT24C512_PAGE_SIZE
- ATMEL_AT24C64_CHIP_SIZE
- ATMEL_AT24C64_PAGE_SIZE
- ATMEL_AT25F512_PAGE_SIZE
- ATMEL_AT45DB0X1B_PAGE_POS
- ATMEL_AT45DB0X1B_PAGE_SIZE
- ATMEL_CLASSD_CODEC_DAI_NAME
- ATMEL_CLASSD_PREALLOC_BUF_SIZE
- ATMEL_CLASSD_RATES
- ATMEL_CLASSD_REG_MAX
- ATMEL_CONSOLE_DEVICE
- ATMEL_DEVICENAME
- ATMEL_ECC_NIST_P256_N_SIZE
- ATMEL_ECC_PRIORITY
- ATMEL_ECC_PUBKEY_SIZE
- ATMEL_FLEXCOM_MODE_SPI
- ATMEL_FLEXCOM_MODE_TWI
- ATMEL_FLEXCOM_MODE_USART
- ATMEL_FPGA_BLOCK
- ATMEL_FPGA_PAGE
- ATMEL_FW_TYPE_502
- ATMEL_FW_TYPE_502D
- ATMEL_FW_TYPE_502E
- ATMEL_FW_TYPE_502_3COM
- ATMEL_FW_TYPE_504
- ATMEL_FW_TYPE_504A_2958
- ATMEL_FW_TYPE_504_2958
- ATMEL_FW_TYPE_506
- ATMEL_FW_TYPE_NONE
- ATMEL_GET_PIN_FUNC
- ATMEL_GET_PIN_IOSET
- ATMEL_GET_PIN_NO
- ATMEL_HLCDC_ARGB1555_MODE
- ATMEL_HLCDC_ARGB4444_MODE
- ATMEL_HLCDC_ARGB8888_MODE
- ATMEL_HLCDC_AYUV_MODE
- ATMEL_HLCDC_BASE_LAYER
- ATMEL_HLCDC_C1_MODE
- ATMEL_HLCDC_C2_MODE
- ATMEL_HLCDC_C4_MODE
- ATMEL_HLCDC_C8_MODE
- ATMEL_HLCDC_CFG
- ATMEL_HLCDC_CGDIS
- ATMEL_HLCDC_CLKDIV
- ATMEL_HLCDC_CLKDIV_MASK
- ATMEL_HLCDC_CLKDIV_SHFT
- ATMEL_HLCDC_CLKPOL
- ATMEL_HLCDC_CLKPWMSEL
- ATMEL_HLCDC_CLKSEL
- ATMEL_HLCDC_CLUT_MODE
- ATMEL_HLCDC_CLUT_SIZE
- ATMEL_HLCDC_CURSOR_LAYER
- ATMEL_HLCDC_DIS
- ATMEL_HLCDC_DISP
- ATMEL_HLCDC_DISPDLY
- ATMEL_HLCDC_DISPPOL
- ATMEL_HLCDC_DITHER
- ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE
- ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED
- ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN
- ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED
- ATMEL_HLCDC_DSCALEOPT
- ATMEL_HLCDC_EN
- ATMEL_HLCDC_FIFOERR
- ATMEL_HLCDC_GUARDTIME_MASK
- ATMEL_HLCDC_HSPOL
- ATMEL_HLCDC_IDR
- ATMEL_HLCDC_IER
- ATMEL_HLCDC_IMR
- ATMEL_HLCDC_ISR
- ATMEL_HLCDC_LAYER_A2Q
- ATMEL_HLCDC_LAYER_ADD_IRQ
- ATMEL_HLCDC_LAYER_CHDR
- ATMEL_HLCDC_LAYER_CHER
- ATMEL_HLCDC_LAYER_CHSR
- ATMEL_HLCDC_LAYER_CLUT
- ATMEL_HLCDC_LAYER_CRKEY
- ATMEL_HLCDC_LAYER_DFETCH
- ATMEL_HLCDC_LAYER_DISCEN
- ATMEL_HLCDC_LAYER_DISC_POS
- ATMEL_HLCDC_LAYER_DISC_SIZE
- ATMEL_HLCDC_LAYER_DMA
- ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16
- ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4
- ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8
- ATMEL_HLCDC_LAYER_DMA_BLEN_MASK
- ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE
- ATMEL_HLCDC_LAYER_DMA_CFG
- ATMEL_HLCDC_LAYER_DMA_DLBO
- ATMEL_HLCDC_LAYER_DMA_IRQ
- ATMEL_HLCDC_LAYER_DMA_LOCKDIS
- ATMEL_HLCDC_LAYER_DMA_ROTDIS
- ATMEL_HLCDC_LAYER_DMA_SIF
- ATMEL_HLCDC_LAYER_DONE_IRQ
- ATMEL_HLCDC_LAYER_DSCR_IRQ
- ATMEL_HLCDC_LAYER_DSTKEY
- ATMEL_HLCDC_LAYER_EN
- ATMEL_HLCDC_LAYER_FORMAT_CFG
- ATMEL_HLCDC_LAYER_GA
- ATMEL_HLCDC_LAYER_GAEN
- ATMEL_HLCDC_LAYER_GA_MASK
- ATMEL_HLCDC_LAYER_GA_SHIFT
- ATMEL_HLCDC_LAYER_IDR
- ATMEL_HLCDC_LAYER_IER
- ATMEL_HLCDC_LAYER_IMR
- ATMEL_HLCDC_LAYER_INV
- ATMEL_HLCDC_LAYER_IRQS_OFFSET
- ATMEL_HLCDC_LAYER_ISR
- ATMEL_HLCDC_LAYER_ITER
- ATMEL_HLCDC_LAYER_ITER2BL
- ATMEL_HLCDC_LAYER_LAEN
- ATMEL_HLCDC_LAYER_LFETCH
- ATMEL_HLCDC_LAYER_MAX_PLANES
- ATMEL_HLCDC_LAYER_OVR
- ATMEL_HLCDC_LAYER_OVR_IRQ
- ATMEL_HLCDC_LAYER_PLANE_ADDR
- ATMEL_HLCDC_LAYER_PLANE_CTRL
- ATMEL_HLCDC_LAYER_PLANE_HEAD
- ATMEL_HLCDC_LAYER_PLANE_NEXT
- ATMEL_HLCDC_LAYER_POS
- ATMEL_HLCDC_LAYER_REP
- ATMEL_HLCDC_LAYER_REVALPHA
- ATMEL_HLCDC_LAYER_RGB
- ATMEL_HLCDC_LAYER_RST
- ATMEL_HLCDC_LAYER_SCALER_ENABLE
- ATMEL_HLCDC_LAYER_SCALER_FACTORS
- ATMEL_HLCDC_LAYER_SIZE
- ATMEL_HLCDC_LAYER_STATUS
- ATMEL_HLCDC_LAYER_UPDATE
- ATMEL_HLCDC_LAYER_YUV
- ATMEL_HLCDC_MAX_LAYERS
- ATMEL_HLCDC_MODE_MASK
- ATMEL_HLCDC_NO_LAYER
- ATMEL_HLCDC_NV21_MODE
- ATMEL_HLCDC_NV61_MODE
- ATMEL_HLCDC_OUTPUT_MODE_MASK
- ATMEL_HLCDC_OVERLAY_LAYER
- ATMEL_HLCDC_PIXEL_CLK
- ATMEL_HLCDC_PP
- ATMEL_HLCDC_PP_LAYER
- ATMEL_HLCDC_PWM
- ATMEL_HLCDC_PWMCVAL
- ATMEL_HLCDC_PWMCVAL_MASK
- ATMEL_HLCDC_PWMPOL
- ATMEL_HLCDC_PWMPS
- ATMEL_HLCDC_PWMPS_MASK
- ATMEL_HLCDC_PWMPS_MAX
- ATMEL_HLCDC_REG_MAX
- ATMEL_HLCDC_RGB444_OUTPUT
- ATMEL_HLCDC_RGB565_MODE
- ATMEL_HLCDC_RGB565_OUTPUT
- ATMEL_HLCDC_RGB666_OUTPUT
- ATMEL_HLCDC_RGB888_MODE
- ATMEL_HLCDC_RGB888_OUTPUT
- ATMEL_HLCDC_RGBA4444_MODE
- ATMEL_HLCDC_RGBA8888_MODE
- ATMEL_HLCDC_RGB_MODE
- ATMEL_HLCDC_SIG_CFG
- ATMEL_HLCDC_SIP
- ATMEL_HLCDC_SOF
- ATMEL_HLCDC_SR
- ATMEL_HLCDC_SYNC
- ATMEL_HLCDC_SYNCDIS
- ATMEL_HLCDC_UYVY_MODE
- ATMEL_HLCDC_VSPDLYE
- ATMEL_HLCDC_VSPDLYS
- ATMEL_HLCDC_VSPHO
- ATMEL_HLCDC_VSPOL
- ATMEL_HLCDC_VSPSU
- ATMEL_HLCDC_VYUY_MODE
- ATMEL_HLCDC_XPHIDEF
- ATMEL_HLCDC_XRGB4444_MODE
- ATMEL_HLCDC_XRGB8888_MODE
- ATMEL_HLCDC_YPHIDEF
- ATMEL_HLCDC_YUV420_MODE
- ATMEL_HLCDC_YUV422ROT
- ATMEL_HLCDC_YUV422SWP
- ATMEL_HLCDC_YUV422_MODE
- ATMEL_HLCDC_YUV_MODE
- ATMEL_HLCDC_YUYV_MODE
- ATMEL_HLCDC_YVYU_MODE
- ATMEL_HSMC_CYCLE
- ATMEL_HSMC_MODE
- ATMEL_HSMC_NFC_ADDR
- ATMEL_HSMC_NFC_BANK
- ATMEL_HSMC_NFC_CFG
- ATMEL_HSMC_NFC_CFG_DTO
- ATMEL_HSMC_NFC_CFG_DTO_MAX
- ATMEL_HSMC_NFC_CFG_FALLING_EDGE
- ATMEL_HSMC_NFC_CFG_PAGESIZE
- ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK
- ATMEL_HSMC_NFC_CFG_RBEDGE
- ATMEL_HSMC_NFC_CFG_RSPARE
- ATMEL_HSMC_NFC_CFG_SPARESIZE
- ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK
- ATMEL_HSMC_NFC_CFG_WSPARE
- ATMEL_HSMC_NFC_CTRL
- ATMEL_HSMC_NFC_CTRL_DIS
- ATMEL_HSMC_NFC_CTRL_EN
- ATMEL_HSMC_NFC_IDR
- ATMEL_HSMC_NFC_IER
- ATMEL_HSMC_NFC_IMR
- ATMEL_HSMC_NFC_SR
- ATMEL_HSMC_NFC_SR_AWB
- ATMEL_HSMC_NFC_SR_BUSY
- ATMEL_HSMC_NFC_SR_CMDDONE
- ATMEL_HSMC_NFC_SR_CSID
- ATMEL_HSMC_NFC_SR_DTOE
- ATMEL_HSMC_NFC_SR_ENABLED
- ATMEL_HSMC_NFC_SR_ERRORS
- ATMEL_HSMC_NFC_SR_NFCASE
- ATMEL_HSMC_NFC_SR_RBEDGE
- ATMEL_HSMC_NFC_SR_RB_FALL
- ATMEL_HSMC_NFC_SR_RB_RISE
- ATMEL_HSMC_NFC_SR_UNDEF
- ATMEL_HSMC_NFC_SR_WR
- ATMEL_HSMC_NFC_SR_XFRDONE
- ATMEL_HSMC_PULSE
- ATMEL_HSMC_SETUP
- ATMEL_HSMC_TIMINGS
- ATMEL_HSMC_TIMINGS_NFSEL
- ATMEL_HSMC_TIMINGS_OCMS
- ATMEL_HSMC_TIMINGS_RBNSEL
- ATMEL_HSMC_TIMINGS_TADL_SHIFT
- ATMEL_HSMC_TIMINGS_TAR_SHIFT
- ATMEL_HSMC_TIMINGS_TCLR_SHIFT
- ATMEL_HSMC_TIMINGS_TRR_SHIFT
- ATMEL_HSMC_TIMINGS_TWB_SHIFT
- ATMEL_I2SC_CR
- ATMEL_I2SC_CR_CKDIS
- ATMEL_I2SC_CR_CKEN
- ATMEL_I2SC_CR_RXDIS
- ATMEL_I2SC_CR_RXEN
- ATMEL_I2SC_CR_SWRST
- ATMEL_I2SC_CR_TXDIS
- ATMEL_I2SC_CR_TXEN
- ATMEL_I2SC_IDR
- ATMEL_I2SC_IER
- ATMEL_I2SC_IMR
- ATMEL_I2SC_INT_RXOR
- ATMEL_I2SC_INT_RXRDY
- ATMEL_I2SC_INT_TXRDY
- ATMEL_I2SC_INT_TXUR
- ATMEL_I2SC_MAX_TDM_CHANNELS
- ATMEL_I2SC_MR
- ATMEL_I2SC_MR_DATALENGTH_16_BITS
- ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT
- ATMEL_I2SC_MR_DATALENGTH_18_BITS
- ATMEL_I2SC_MR_DATALENGTH_20_BITS
- ATMEL_I2SC_MR_DATALENGTH_24_BITS
- ATMEL_I2SC_MR_DATALENGTH_32_BITS
- ATMEL_I2SC_MR_DATALENGTH_8_BITS
- ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT
- ATMEL_I2SC_MR_DATALENGTH_MASK
- ATMEL_I2SC_MR_FORMAT_I2S
- ATMEL_I2SC_MR_FORMAT_LJ
- ATMEL_I2SC_MR_FORMAT_MASK
- ATMEL_I2SC_MR_FORMAT_TDM
- ATMEL_I2SC_MR_FORMAT_TDMLJ
- ATMEL_I2SC_MR_IMCKDIV
- ATMEL_I2SC_MR_IMCKDIV_MASK
- ATMEL_I2SC_MR_IMCKFS
- ATMEL_I2SC_MR_IMCKFS_MASK
- ATMEL_I2SC_MR_IMCKMODE_I2SCK
- ATMEL_I2SC_MR_IMCKMODE_I2SMCK
- ATMEL_I2SC_MR_IMCKMODE_MASK
- ATMEL_I2SC_MR_IWS
- ATMEL_I2SC_MR_MODE_MASK
- ATMEL_I2SC_MR_MODE_MASTER
- ATMEL_I2SC_MR_MODE_SLAVE
- ATMEL_I2SC_MR_RXDMA_MASK
- ATMEL_I2SC_MR_RXDMA_MULTIPLE
- ATMEL_I2SC_MR_RXDMA_SINGLE
- ATMEL_I2SC_MR_RXLOOP
- ATMEL_I2SC_MR_RXMONO
- ATMEL_I2SC_MR_TXDMA_MASK
- ATMEL_I2SC_MR_TXDMA_SINGLE
- ATMEL_I2SC_MR_TXDME_MULTIPLE
- ATMEL_I2SC_MR_TXMONO
- ATMEL_I2SC_MR_TXSAME_MASK
- ATMEL_I2SC_MR_TXSAME_PREVIOUS
- ATMEL_I2SC_MR_TXSAME_ZERO
- ATMEL_I2SC_RHR
- ATMEL_I2SC_SCR
- ATMEL_I2SC_SR
- ATMEL_I2SC_SR_RXEN
- ATMEL_I2SC_SR_RXOR
- ATMEL_I2SC_SR_RXORCH
- ATMEL_I2SC_SR_RXORCH_MASK
- ATMEL_I2SC_SR_RXRDY
- ATMEL_I2SC_SR_TXEN
- ATMEL_I2SC_SR_TXRDY
- ATMEL_I2SC_SR_TXUR
- ATMEL_I2SC_SR_TXURCH
- ATMEL_I2SC_SR_TXURCH_MASK
- ATMEL_I2SC_SSR
- ATMEL_I2SC_THR
- ATMEL_I2SC_VERSION
- ATMEL_I2S_FORMATS
- ATMEL_I2S_RATES
- ATMEL_ISC_NAME
- ATMEL_ISC_REG_MAX
- ATMEL_ISR_PASS_LIMIT
- ATMEL_LCDC_ADDRINC
- ATMEL_LCDC_ADDRINC_OFFSET
- ATMEL_LCDC_BLENGTH
- ATMEL_LCDC_BLENGTH_OFFSET
- ATMEL_LCDC_BUSY
- ATMEL_LCDC_BYPASS
- ATMEL_LCDC_CLKMOD
- ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY
- ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
- ATMEL_LCDC_CLKVAL
- ATMEL_LCDC_CLKVAL_OFFSET
- ATMEL_LCDC_CONTRAST_CTR
- ATMEL_LCDC_CONTRAST_VAL
- ATMEL_LCDC_CVAL
- ATMEL_LCDC_CVAL_DEFAULT
- ATMEL_LCDC_DISTYPE
- ATMEL_LCDC_DISTYPE_STNCOLOR
- ATMEL_LCDC_DISTYPE_STNMONO
- ATMEL_LCDC_DISTYPE_TFT
- ATMEL_LCDC_DMA2DCFG
- ATMEL_LCDC_DMA2DEN
- ATMEL_LCDC_DMABADDR1
- ATMEL_LCDC_DMABADDR2
- ATMEL_LCDC_DMABUSY
- ATMEL_LCDC_DMACON
- ATMEL_LCDC_DMAEN
- ATMEL_LCDC_DMAFRMADD1
- ATMEL_LCDC_DMAFRMADD2
- ATMEL_LCDC_DMAFRMCFG
- ATMEL_LCDC_DMAFRMPT1
- ATMEL_LCDC_DMAFRMPT2
- ATMEL_LCDC_DMARST
- ATMEL_LCDC_DMAUPDT
- ATMEL_LCDC_DMA_BURST_LEN
- ATMEL_LCDC_DP1_2
- ATMEL_LCDC_DP1_2_VAL
- ATMEL_LCDC_DP2_3
- ATMEL_LCDC_DP2_3_VAL
- ATMEL_LCDC_DP3_4
- ATMEL_LCDC_DP3_4_VAL
- ATMEL_LCDC_DP3_5
- ATMEL_LCDC_DP3_5_VAL
- ATMEL_LCDC_DP4_5
- ATMEL_LCDC_DP4_5_VAL
- ATMEL_LCDC_DP4_7
- ATMEL_LCDC_DP4_7_VAL
- ATMEL_LCDC_DP5_7
- ATMEL_LCDC_DP5_7_VAL
- ATMEL_LCDC_DP6_7
- ATMEL_LCDC_DP6_7_VAL
- ATMEL_LCDC_ENA
- ATMEL_LCDC_ENA_PWMDISABLE
- ATMEL_LCDC_ENA_PWMENABLE
- ATMEL_LCDC_EOFI
- ATMEL_LCDC_FIFO
- ATMEL_LCDC_FIFOTH
- ATMEL_LCDC_FIFO_SIZE
- ATMEL_LCDC_FRSIZE
- ATMEL_LCDC_GUARDT
- ATMEL_LCDC_GUARDT_OFFSET
- ATMEL_LCDC_HBP
- ATMEL_LCDC_HFP
- ATMEL_LCDC_HFP_OFFSET
- ATMEL_LCDC_HOZVAL
- ATMEL_LCDC_HOZVAL_OFFSET
- ATMEL_LCDC_HPW
- ATMEL_LCDC_HPW_OFFSET
- ATMEL_LCDC_ICR
- ATMEL_LCDC_IDR
- ATMEL_LCDC_IER
- ATMEL_LCDC_IFWIDTH
- ATMEL_LCDC_IFWIDTH_16
- ATMEL_LCDC_IFWIDTH_4
- ATMEL_LCDC_IFWIDTH_8
- ATMEL_LCDC_IMR
- ATMEL_LCDC_INVCLK
- ATMEL_LCDC_INVCLK_INVERTED
- ATMEL_LCDC_INVCLK_NORMAL
- ATMEL_LCDC_INVDVAL
- ATMEL_LCDC_INVDVAL_INVERTED
- ATMEL_LCDC_INVDVAL_NORMAL
- ATMEL_LCDC_INVFRAME
- ATMEL_LCDC_INVFRAME_INVERTED
- ATMEL_LCDC_INVFRAME_NORMAL
- ATMEL_LCDC_INVLINE
- ATMEL_LCDC_INVLINE_INVERTED
- ATMEL_LCDC_INVLINE_NORMAL
- ATMEL_LCDC_INVVD
- ATMEL_LCDC_INVVD_INVERTED
- ATMEL_LCDC_INVVD_NORMAL
- ATMEL_LCDC_ISR
- ATMEL_LCDC_LCDCON1
- ATMEL_LCDC_LCDCON2
- ATMEL_LCDC_LCDFRMCFG
- ATMEL_LCDC_LINCNT
- ATMEL_LCDC_LINEVAL
- ATMEL_LCDC_LNI
- ATMEL_LCDC_LSTLNI
- ATMEL_LCDC_LUT
- ATMEL_LCDC_MEMOR
- ATMEL_LCDC_MEMOR_BIG
- ATMEL_LCDC_MEMOR_LITTLE
- ATMEL_LCDC_MERI
- ATMEL_LCDC_MVAL
- ATMEL_LCDC_OWRI
- ATMEL_LCDC_PIXELOFF
- ATMEL_LCDC_PIXELOFF_OFFSET
- ATMEL_LCDC_PIXELSIZE
- ATMEL_LCDC_PIXELSIZE_1
- ATMEL_LCDC_PIXELSIZE_16
- ATMEL_LCDC_PIXELSIZE_2
- ATMEL_LCDC_PIXELSIZE_24
- ATMEL_LCDC_PIXELSIZE_32
- ATMEL_LCDC_PIXELSIZE_4
- ATMEL_LCDC_PIXELSIZE_8
- ATMEL_LCDC_POL
- ATMEL_LCDC_POL_NEGATIVE
- ATMEL_LCDC_POL_POSITIVE
- ATMEL_LCDC_PS
- ATMEL_LCDC_PS_DIV1
- ATMEL_LCDC_PS_DIV2
- ATMEL_LCDC_PS_DIV4
- ATMEL_LCDC_PS_DIV8
- ATMEL_LCDC_PWR
- ATMEL_LCDC_PWRCON
- ATMEL_LCDC_SCANMOD
- ATMEL_LCDC_SCANMOD_DUAL
- ATMEL_LCDC_SCANMOD_SINGLE
- ATMEL_LCDC_TIM1
- ATMEL_LCDC_TIM2
- ATMEL_LCDC_UFLWI
- ATMEL_LCDC_VBP
- ATMEL_LCDC_VBP_OFFSET
- ATMEL_LCDC_VFP
- ATMEL_LCDC_VHDLY
- ATMEL_LCDC_VHDLY_OFFSET
- ATMEL_LCDC_VPW
- ATMEL_LCDC_VPW_OFFSET
- ATMEL_LCDC_WIRING_BGR
- ATMEL_LCDC_WIRING_RGB
- ATMEL_MANID
- ATMEL_MANID2
- ATMEL_MAX_UART
- ATMEL_MIN_FIFO_SIZE
- ATMEL_NAND_ALE_OFFSET
- ATMEL_NAND_CLE_OFFSET
- ATMEL_NAND_GPIO_RB
- ATMEL_NAND_NATIVE_RB
- ATMEL_NAND_NO_RB
- ATMEL_NFC_ACYCLE
- ATMEL_NFC_CMD
- ATMEL_NFC_CSID
- ATMEL_NFC_DATAEN
- ATMEL_NFC_MAX_ADDR_CYCLES
- ATMEL_NFC_MAX_RB_ID
- ATMEL_NFC_NFCWR
- ATMEL_NFC_NO_DATA
- ATMEL_NFC_READ_DATA
- ATMEL_NFC_SRAM_SIZE
- ATMEL_NFC_VCMD2
- ATMEL_NFC_WRITE_DATA
- ATMEL_PDC_H
- ATMEL_PDC_PTCR
- ATMEL_PDC_PTSR
- ATMEL_PDC_RCR
- ATMEL_PDC_RNCR
- ATMEL_PDC_RNPR
- ATMEL_PDC_RPR
- ATMEL_PDC_RXTDIS
- ATMEL_PDC_RXTEN
- ATMEL_PDC_SCND_BUF_OFF
- ATMEL_PDC_TCR
- ATMEL_PDC_TNCR
- ATMEL_PDC_TNPR
- ATMEL_PDC_TPR
- ATMEL_PDC_TXTDIS
- ATMEL_PDC_TXTEN
- ATMEL_PDMIC_CODEC_DAI_NAME
- ATMEL_PDMIC_FORMATS
- ATMEL_PDMIC_MAX_BUF_SIZE
- ATMEL_PDMIC_PREALLOC_BUF_SIZE
- ATMEL_PDMIC_REG_MAX
- ATMEL_PIN_CONFIG_DRIVE_STRENGTH
- ATMEL_PIO_BANK
- ATMEL_PIO_BANK_OFFSET
- ATMEL_PIO_CFGR
- ATMEL_PIO_CFGR_EVTSEL_BOTH
- ATMEL_PIO_CFGR_EVTSEL_FALLING
- ATMEL_PIO_CFGR_EVTSEL_HIGH
- ATMEL_PIO_CFGR_EVTSEL_LOW
- ATMEL_PIO_CFGR_EVTSEL_MASK
- ATMEL_PIO_CFGR_EVTSEL_RISING
- ATMEL_PIO_CFGR_FUNC_MASK
- ATMEL_PIO_CODR
- ATMEL_PIO_DIR_MASK
- ATMEL_PIO_DRVSTR_HI
- ATMEL_PIO_DRVSTR_LO
- ATMEL_PIO_DRVSTR_MASK
- ATMEL_PIO_DRVSTR_ME
- ATMEL_PIO_DRVSTR_OFFSET
- ATMEL_PIO_IDR
- ATMEL_PIO_IER
- ATMEL_PIO_IFEN_MASK
- ATMEL_PIO_IFSCEN_MASK
- ATMEL_PIO_IMR
- ATMEL_PIO_IOFR
- ATMEL_PIO_ISR
- ATMEL_PIO_LINE
- ATMEL_PIO_LOCKSR
- ATMEL_PIO_MSKR
- ATMEL_PIO_NPINS_PER_BANK
- ATMEL_PIO_ODSR
- ATMEL_PIO_OPD_MASK
- ATMEL_PIO_PDEN_MASK
- ATMEL_PIO_PDSR
- ATMEL_PIO_PUEN_MASK
- ATMEL_PIO_SCHMITT_MASK
- ATMEL_PIO_SODR
- ATMEL_PMECC_CFG
- ATMEL_PMECC_CLK
- ATMEL_PMECC_CTRL
- ATMEL_PMECC_EADDR
- ATMEL_PMECC_ECC
- ATMEL_PMECC_H
- ATMEL_PMECC_IDR
- ATMEL_PMECC_IER
- ATMEL_PMECC_IMR
- ATMEL_PMECC_ISR
- ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH
- ATMEL_PMECC_OOBOFFSET_AUTO
- ATMEL_PMECC_REM
- ATMEL_PMECC_SADDR
- ATMEL_PMECC_SAREA
- ATMEL_PMECC_SECTOR_SIZE_AUTO
- ATMEL_PMECC_SR
- ATMEL_PMERRLOC_EL
- ATMEL_PMERRLOC_ELCFG
- ATMEL_PMERRLOC_ELDIS
- ATMEL_PMERRLOC_ELEN
- ATMEL_PMERRLOC_ELIDR
- ATMEL_PMERRLOC_ELIER
- ATMEL_PMERRLOC_ELIMR
- ATMEL_PMERRLOC_ELISR
- ATMEL_PMERRLOC_ELPRIM
- ATMEL_PMERRLOC_ELSR
- ATMEL_PMERRLOC_SIGMA
- ATMEL_RTS_HIGH_OFFSET
- ATMEL_RTS_LOW_OFFSET
- ATMEL_SERIAL_H
- ATMEL_SERIAL_RINGSIZE
- ATMEL_SHA_DMA_THRESHOLD
- ATMEL_SHA_QUEUE_LENGTH
- ATMEL_SMC_CYCLE
- ATMEL_SMC_CYCLE_XLATE
- ATMEL_SMC_MODE
- ATMEL_SMC_MODE_BAT_MASK
- ATMEL_SMC_MODE_BAT_SELECT
- ATMEL_SMC_MODE_BAT_WRITE
- ATMEL_SMC_MODE_DBW_16
- ATMEL_SMC_MODE_DBW_32
- ATMEL_SMC_MODE_DBW_8
- ATMEL_SMC_MODE_DBW_MASK
- ATMEL_SMC_MODE_EXNWMODE_DISABLE
- ATMEL_SMC_MODE_EXNWMODE_FROZEN
- ATMEL_SMC_MODE_EXNWMODE_MASK
- ATMEL_SMC_MODE_EXNWMODE_READY
- ATMEL_SMC_MODE_PMEN
- ATMEL_SMC_MODE_PS_16
- ATMEL_SMC_MODE_PS_32
- ATMEL_SMC_MODE_PS_4
- ATMEL_SMC_MODE_PS_8
- ATMEL_SMC_MODE_PS_MASK
- ATMEL_SMC_MODE_READMODE_MASK
- ATMEL_SMC_MODE_READMODE_NCS
- ATMEL_SMC_MODE_READMODE_NRD
- ATMEL_SMC_MODE_TDF
- ATMEL_SMC_MODE_TDFMODE_OPTIMIZED
- ATMEL_SMC_MODE_TDF_MASK
- ATMEL_SMC_MODE_TDF_MAX
- ATMEL_SMC_MODE_TDF_MIN
- ATMEL_SMC_MODE_WRITEMODE_MASK
- ATMEL_SMC_MODE_WRITEMODE_NCS
- ATMEL_SMC_MODE_WRITEMODE_NWE
- ATMEL_SMC_NCS_RD_SHIFT
- ATMEL_SMC_NCS_WR_SHIFT
- ATMEL_SMC_NRD_SHIFT
- ATMEL_SMC_NWE_SHIFT
- ATMEL_SMC_PULSE
- ATMEL_SMC_PULSE_XLATE
- ATMEL_SMC_SETUP
- ATMEL_SMC_SETUP_XLATE
- ATMEL_SOLOS_BLOCK
- ATMEL_SOLOS_PAGE
- ATMEL_SPI_PM_OPS
- ATMEL_SSC_CMR_DIV
- ATMEL_SSC_DMABUF_SIZE
- ATMEL_SSC_FORMATS
- ATMEL_SSC_RCMR_PERIOD
- ATMEL_SSC_TCMR_PERIOD
- ATMEL_STS_OK
- ATMEL_SYSCLK_MCK
- ATMEL_TC_ABETRG
- ATMEL_TC_ACMR_MASK
- ATMEL_TC_ACPA
- ATMEL_TC_ACPA_CLEAR
- ATMEL_TC_ACPA_NONE
- ATMEL_TC_ACPA_SET
- ATMEL_TC_ACPA_TOGGLE
- ATMEL_TC_ACPC
- ATMEL_TC_ACPC_CLEAR
- ATMEL_TC_ACPC_NONE
- ATMEL_TC_ACPC_SET
- ATMEL_TC_ACPC_TOGGLE
- ATMEL_TC_AEEVT
- ATMEL_TC_AEEVT_CLEAR
- ATMEL_TC_AEEVT_NONE
- ATMEL_TC_AEEVT_SET
- ATMEL_TC_AEEVT_TOGGLE
- ATMEL_TC_ALL_IRQ
- ATMEL_TC_ASWTRG
- ATMEL_TC_ASWTRG_CLEAR
- ATMEL_TC_ASWTRG_NONE
- ATMEL_TC_ASWTRG_SET
- ATMEL_TC_ASWTRG_TOGGLE
- ATMEL_TC_BCMR_MASK
- ATMEL_TC_BCPB
- ATMEL_TC_BCPB_CLEAR
- ATMEL_TC_BCPB_NONE
- ATMEL_TC_BCPB_SET
- ATMEL_TC_BCPB_TOGGLE
- ATMEL_TC_BCPC
- ATMEL_TC_BCPC_CLEAR
- ATMEL_TC_BCPC_NONE
- ATMEL_TC_BCPC_SET
- ATMEL_TC_BCPC_TOGGLE
- ATMEL_TC_BCR
- ATMEL_TC_BEEVT
- ATMEL_TC_BEEVT_CLEAR
- ATMEL_TC_BEEVT_NONE
- ATMEL_TC_BEEVT_SET
- ATMEL_TC_BEEVT_TOGGLE
- ATMEL_TC_BMR
- ATMEL_TC_BSWTRG
- ATMEL_TC_BSWTRG_CLEAR
- ATMEL_TC_BSWTRG_NONE
- ATMEL_TC_BSWTRG_SET
- ATMEL_TC_BSWTRG_TOGGLE
- ATMEL_TC_BURST
- ATMEL_TC_CCR
- ATMEL_TC_CHAN
- ATMEL_TC_CLKDIS
- ATMEL_TC_CLKEN
- ATMEL_TC_CLKI
- ATMEL_TC_CLKSTA
- ATMEL_TC_CMR
- ATMEL_TC_COVFS
- ATMEL_TC_CPAS
- ATMEL_TC_CPBS
- ATMEL_TC_CPCDIS
- ATMEL_TC_CPCS
- ATMEL_TC_CPCSTOP
- ATMEL_TC_CPCTRG
- ATMEL_TC_CV
- ATMEL_TC_EEVT
- ATMEL_TC_EEVTEDG
- ATMEL_TC_EEVTEDG_BOTH
- ATMEL_TC_EEVTEDG_FALLING
- ATMEL_TC_EEVTEDG_NONE
- ATMEL_TC_EEVTEDG_RISING
- ATMEL_TC_EEVT_TIOB
- ATMEL_TC_EEVT_XC0
- ATMEL_TC_EEVT_XC1
- ATMEL_TC_EEVT_XC2
- ATMEL_TC_ENETRG
- ATMEL_TC_ETRGEDG
- ATMEL_TC_ETRGEDG_BOTH
- ATMEL_TC_ETRGEDG_FALLING
- ATMEL_TC_ETRGEDG_NONE
- ATMEL_TC_ETRGEDG_RISING
- ATMEL_TC_ETRGS
- ATMEL_TC_GATE_NONE
- ATMEL_TC_GATE_XC0
- ATMEL_TC_GATE_XC1
- ATMEL_TC_GATE_XC2
- ATMEL_TC_IDR
- ATMEL_TC_IER
- ATMEL_TC_IMR
- ATMEL_TC_LDBDIS
- ATMEL_TC_LDBSTOP
- ATMEL_TC_LDRA
- ATMEL_TC_LDRAS
- ATMEL_TC_LDRA_BOTH
- ATMEL_TC_LDRA_FALLING
- ATMEL_TC_LDRA_NONE
- ATMEL_TC_LDRA_RISING
- ATMEL_TC_LDRB
- ATMEL_TC_LDRBS
- ATMEL_TC_LDRB_BOTH
- ATMEL_TC_LDRB_FALLING
- ATMEL_TC_LDRB_NONE
- ATMEL_TC_LDRB_RISING
- ATMEL_TC_LOVRS
- ATMEL_TC_MTIOA
- ATMEL_TC_MTIOB
- ATMEL_TC_RA
- ATMEL_TC_RB
- ATMEL_TC_RC
- ATMEL_TC_REG
- ATMEL_TC_SR
- ATMEL_TC_SWTRG
- ATMEL_TC_SYNC
- ATMEL_TC_TC0XC0S
- ATMEL_TC_TC0XC0S_NONE
- ATMEL_TC_TC0XC0S_TCLK0
- ATMEL_TC_TC0XC0S_TIOA1
- ATMEL_TC_TC0XC0S_TIOA2
- ATMEL_TC_TC1XC1S
- ATMEL_TC_TC1XC1S_NONE
- ATMEL_TC_TC1XC1S_TCLK1
- ATMEL_TC_TC1XC1S_TIOA0
- ATMEL_TC_TC1XC1S_TIOA2
- ATMEL_TC_TC2XC2S
- ATMEL_TC_TC2XC2S_NONE
- ATMEL_TC_TC2XC2S_TCLK2
- ATMEL_TC_TC2XC2S_TIOA0
- ATMEL_TC_TC2XC2S_TIOA1
- ATMEL_TC_TCCLKS
- ATMEL_TC_TIMER_CLOCK1
- ATMEL_TC_TIMER_CLOCK2
- ATMEL_TC_TIMER_CLOCK3
- ATMEL_TC_TIMER_CLOCK4
- ATMEL_TC_TIMER_CLOCK5
- ATMEL_TC_WAVE
- ATMEL_TC_WAVESEL
- ATMEL_TC_WAVESEL_UP
- ATMEL_TC_WAVESEL_UPDOWN
- ATMEL_TC_WAVESEL_UPDOWN_AUTO
- ATMEL_TC_WAVESEL_UP_AUTO
- ATMEL_TC_XC0
- ATMEL_TC_XC1
- ATMEL_TC_XC2
- ATMEL_TDES_QUEUE_LENGTH
- ATMEL_TP_I2C_ADDR
- ATMEL_TP_I2C_BL_ADDR
- ATMEL_TS_I2C_ADDR
- ATMEL_TS_I2C_BL_ADDR
- ATMEL_UA_RTOR
- ATMEL_US_BRGR
- ATMEL_US_CD
- ATMEL_US_CHMODE
- ATMEL_US_CHMODE_ECHO
- ATMEL_US_CHMODE_LOC_LOOP
- ATMEL_US_CHMODE_NORMAL
- ATMEL_US_CHMODE_REM_LOOP
- ATMEL_US_CHRL
- ATMEL_US_CHRL_5
- ATMEL_US_CHRL_6
- ATMEL_US_CHRL_7
- ATMEL_US_CHRL_8
- ATMEL_US_CLKO
- ATMEL_US_CMPR
- ATMEL_US_CR
- ATMEL_US_CSR
- ATMEL_US_CTS
- ATMEL_US_CTSIC
- ATMEL_US_DCD
- ATMEL_US_DCDIC
- ATMEL_US_DSNACK
- ATMEL_US_DSR
- ATMEL_US_DSRIC
- ATMEL_US_DTRDIS
- ATMEL_US_DTREN
- ATMEL_US_ENDRX
- ATMEL_US_ENDTX
- ATMEL_US_FESR
- ATMEL_US_FIDI
- ATMEL_US_FIDR
- ATMEL_US_FIER
- ATMEL_US_FIFODIS
- ATMEL_US_FIFOEN
- ATMEL_US_FILTER
- ATMEL_US_FIMR
- ATMEL_US_FLR
- ATMEL_US_FMR
- ATMEL_US_FOUR_DATA
- ATMEL_US_FP_MASK
- ATMEL_US_FP_OFFSET
- ATMEL_US_FRAME
- ATMEL_US_FRTSC
- ATMEL_US_IDR
- ATMEL_US_IER
- ATMEL_US_IF
- ATMEL_US_IMR
- ATMEL_US_INACK
- ATMEL_US_ITERATION
- ATMEL_US_MAX_ITER
- ATMEL_US_MAX_ITER_MASK
- ATMEL_US_MODE9
- ATMEL_US_MR
- ATMEL_US_MSBF
- ATMEL_US_NACK
- ATMEL_US_NAME
- ATMEL_US_NBSTOP
- ATMEL_US_NBSTOP_1
- ATMEL_US_NBSTOP_1_5
- ATMEL_US_NBSTOP_2
- ATMEL_US_NER
- ATMEL_US_ONE_DATA
- ATMEL_US_OVER
- ATMEL_US_OVRE
- ATMEL_US_PAR
- ATMEL_US_PARE
- ATMEL_US_PAR_EVEN
- ATMEL_US_PAR_MARK
- ATMEL_US_PAR_MULTI_DROP
- ATMEL_US_PAR_NONE
- ATMEL_US_PAR_ODD
- ATMEL_US_PAR_SPACE
- ATMEL_US_RETTO
- ATMEL_US_RHR
- ATMEL_US_RI
- ATMEL_US_RIIC
- ATMEL_US_RSTIT
- ATMEL_US_RSTNACK
- ATMEL_US_RSTRX
- ATMEL_US_RSTSTA
- ATMEL_US_RSTTX
- ATMEL_US_RTOR
- ATMEL_US_RTSDIS
- ATMEL_US_RTSEN
- ATMEL_US_RXBRK
- ATMEL_US_RXBUFF
- ATMEL_US_RXDIS
- ATMEL_US_RXEN
- ATMEL_US_RXFCLR
- ATMEL_US_RXFEF
- ATMEL_US_RXFFF
- ATMEL_US_RXFL
- ATMEL_US_RXFPTEF
- ATMEL_US_RXFTHF
- ATMEL_US_RXFTHF2
- ATMEL_US_RXFTHRES
- ATMEL_US_RXFTHRES2
- ATMEL_US_RXRDY
- ATMEL_US_RXRDYM
- ATMEL_US_SENDA
- ATMEL_US_STPBRK
- ATMEL_US_STTBRK
- ATMEL_US_STTTO
- ATMEL_US_SYNC
- ATMEL_US_SYNH
- ATMEL_US_TG
- ATMEL_US_THR
- ATMEL_US_TIMEOUT
- ATMEL_US_TO
- ATMEL_US_TTGR
- ATMEL_US_TWO_DATA
- ATMEL_US_TXBUFE
- ATMEL_US_TXDIS
- ATMEL_US_TXEMPTY
- ATMEL_US_TXEN
- ATMEL_US_TXFCLR
- ATMEL_US_TXFEF
- ATMEL_US_TXFFF
- ATMEL_US_TXFL
- ATMEL_US_TXFLCLR
- ATMEL_US_TXFLOCK
- ATMEL_US_TXFPTEF
- ATMEL_US_TXFTHF
- ATMEL_US_TXFTHRES
- ATMEL_US_TXRDY
- ATMEL_US_TXRDYM
- ATMEL_US_USCLKS
- ATMEL_US_USCLKS_MCK
- ATMEL_US_USCLKS_MCK_DIV8
- ATMEL_US_USCLKS_SCK
- ATMEL_US_USMODE
- ATMEL_US_USMODE_HWHS
- ATMEL_US_USMODE_IRDA
- ATMEL_US_USMODE_ISO7816_T0
- ATMEL_US_USMODE_ISO7816_T1
- ATMEL_US_USMODE_MODEM
- ATMEL_US_USMODE_NORMAL
- ATMEL_US_USMODE_RS485
- ATMEL_US_VERSION
- ATMEL_VID
- ATMIOC_AREQUIPA
- ATMIOC_BACKEND
- ATMIOC_BACKEND_END
- ATMIOC_CLIP
- ATMIOC_CLIP_END
- ATMIOC_ITF
- ATMIOC_ITF_END
- ATMIOC_LANE
- ATMIOC_MPOA
- ATMIOC_PHYCOM
- ATMIOC_PHYCOM_END
- ATMIOC_PHYPRV
- ATMIOC_PHYPRV_END
- ATMIOC_PHYTYP
- ATMIOC_PHYTYP_END
- ATMIOC_SARCOM
- ATMIOC_SARCOM_END
- ATMIOC_SARPRV
- ATMIOC_SARPRV_END
- ATMIOC_SPECIAL
- ATMIOC_SPECIAL_END
- ATMLEC_CTRL
- ATMLEC_DATA
- ATMLEC_MCAST
- ATMLEC_MSG_TYPE_MAX
- ATML_STATUS_ABORT
- ATML_STATUS_BUSY
- ATML_STATUS_DATA_AVAIL
- ATML_STATUS_LASTBYTE
- ATML_STATUS_READY
- ATML_STATUS_REWRITE
- ATMMPC_CTRL
- ATMMPC_DATA
- ATMSIGD_CTRL
- ATMTCP_CREATE
- ATMTCP_CTRL_CLOSE
- ATMTCP_CTRL_OPEN
- ATMTCP_HDR_MAGIC
- ATMTCP_REMOVE
- ATM_25_PCR
- ATM_AAL0
- ATM_AAL0_SDU
- ATM_AAL1
- ATM_AAL2
- ATM_AAL34
- ATM_AAL5
- ATM_AAL5_TRAILER
- ATM_ABR
- ATM_ADDADDR
- ATM_ADDADDR32
- ATM_ADDLECSADDR
- ATM_ADDPARTY
- ATM_ADDR_LECS
- ATM_ADDR_LOCAL
- ATM_AFI_DCC
- ATM_AFI_DCC_GROUP
- ATM_AFI_E164
- ATM_AFI_E164_GROUP
- ATM_AFI_ICD
- ATM_AFI_ICD_GROUP
- ATM_AFI_LOCAL
- ATM_AFI_LOCAL_GROUP
- ATM_ANYCLASS
- ATM_ATMOPT_CLP
- ATM_BACKEND_BR2684
- ATM_BACKEND_PPP
- ATM_BACKEND_RAW
- ATM_BACKLOG_DEFAULT
- ATM_CBR
- ATM_CELL_HEADER
- ATM_CELL_PAYLOAD
- ATM_CELL_SIZE
- ATM_CI_MAX
- ATM_DELADDR
- ATM_DELADDR32
- ATM_DELLECSADDR
- ATM_DESC
- ATM_DF_REMOVED
- ATM_DROPPARTY
- ATM_DS3_PCR
- ATM_E164_LEN
- ATM_ESA_LEN
- ATM_GETADDR
- ATM_GETADDR32
- ATM_GETCIRANGE
- ATM_GETCIRANGE32
- ATM_GETESI
- ATM_GETESI32
- ATM_GETLECSADDR
- ATM_GETLINKRATE
- ATM_GETLINKRATE32
- ATM_GETLOOP
- ATM_GETLOOP32
- ATM_GETNAMES
- ATM_GETNAMES32
- ATM_GETSTAT
- ATM_GETSTAT32
- ATM_GETSTATZ
- ATM_GETSTATZ32
- ATM_GETTYPE
- ATM_GETTYPE32
- ATM_HDR_CLP
- ATM_HDR_GFC_MASK
- ATM_HDR_GFC_SHIFT
- ATM_HDR_PTI_MASK
- ATM_HDR_PTI_SHIFT
- ATM_HDR_VCI_MASK
- ATM_HDR_VCI_SHIFT
- ATM_HDR_VPI_MASK
- ATM_HDR_VPI_SHIFT
- ATM_HL_HLP
- ATM_HL_ISO
- ATM_HL_NONE
- ATM_HL_USER
- ATM_HL_VENDOR
- ATM_IDT77252_SEND_IDLE
- ATM_IMD_EXTENDED
- ATM_IMD_NONE
- ATM_IMD_NORMAL
- ATM_ITFTYP_LEN
- ATM_ITF_ANY
- ATM_L2_HDLC_ABM
- ATM_L2_HDLC_ARM
- ATM_L2_HDLC_NRM
- ATM_L2_ISO1745
- ATM_L2_ISO7776
- ATM_L2_ISO8802
- ATM_L2_LAPB
- ATM_L2_NONE
- ATM_L2_Q291
- ATM_L2_Q922
- ATM_L2_USER
- ATM_L2_X25_LL
- ATM_L2_X25_ML
- ATM_L2_X75
- ATM_L3_H310
- ATM_L3_H321
- ATM_L3_ISO8208
- ATM_L3_ISO8473
- ATM_L3_NONE
- ATM_L3_T70
- ATM_L3_TR9577
- ATM_L3_USER
- ATM_L3_X223
- ATM_L3_X25
- ATM_LAYER_SELECT
- ATM_LAYER_STATUS
- ATM_LIJ
- ATM_LIJ_NJ
- ATM_LIJ_NONE
- ATM_LIJ_RPJ
- ATM_LM_LOC_AAL
- ATM_LM_LOC_ANALOG
- ATM_LM_LOC_ATM
- ATM_LM_LOC_PHY
- ATM_LM_NONE
- ATM_LM_RMT_AAL
- ATM_LM_RMT_ANALOG
- ATM_LM_RMT_ATM
- ATM_LM_RMT_PHY
- ATM_LNC_C6_AUTO_DEMOTE
- ATM_MASK
- ATM_MAX_AAL34_PDU
- ATM_MAX_AAL5_PDU
- ATM_MAX_BLLI
- ATM_MAX_CDV
- ATM_MAX_HLI
- ATM_MAX_PCR
- ATM_MAX_VCI
- ATM_MAX_VPI
- ATM_MAX_VPI_NNI
- ATM_MC_H221
- ATM_MC_NONE
- ATM_MC_PS
- ATM_MC_PS_FEC
- ATM_MC_TS
- ATM_MC_TS_FEC
- ATM_MF_BWD
- ATM_MF_DEC_RSV
- ATM_MF_DEC_SHP
- ATM_MF_IMMED
- ATM_MF_INC_RSV
- ATM_MF_INC_SHP
- ATM_MF_SET
- ATM_NEWBACKENDIF
- ATM_NONE
- ATM_NOT_RSV_VCI
- ATM_NO_AAL
- ATM_OC12_PCR
- ATM_OC3_PCR
- ATM_OF_IMMED
- ATM_OF_INRATE
- ATM_PHY_SIG_FOUND
- ATM_PHY_SIG_LOST
- ATM_PHY_SIG_UNKNOWN
- ATM_POISON
- ATM_POISON_FREE
- ATM_PTI_E2EF5
- ATM_PTI_RSV
- ATM_PTI_RSV_RM
- ATM_PTI_SEGF5
- ATM_PTI_UCES0
- ATM_PTI_UCES1
- ATM_PTI_US0
- ATM_PTI_US1
- ATM_QUERYLOOP
- ATM_QUERYLOOP32
- ATM_RSTADDR
- ATM_RSTADDR32
- ATM_SC_RX
- ATM_SC_TX
- ATM_SD
- ATM_SETBACKEND
- ATM_SETCIRANGE
- ATM_SETCIRANGE32
- ATM_SETESI
- ATM_SETESI32
- ATM_SETESIF
- ATM_SETESIF32
- ATM_SETLOOP
- ATM_SETLOOP32
- ATM_SETSC
- ATM_SKB
- ATM_TT_NONE
- ATM_TT_RX
- ATM_TT_RXTX
- ATM_TT_TX
- ATM_UBR
- ATM_VBR
- ATM_VCI_ANY
- ATM_VCI_UNSPEC
- ATM_VF2TXT_MAP
- ATM_VF2VS
- ATM_VF_ADDR
- ATM_VF_BOUND
- ATM_VF_CLOSE
- ATM_VF_HASQOS
- ATM_VF_HASSAP
- ATM_VF_IS_CLIP
- ATM_VF_LISTEN
- ATM_VF_META
- ATM_VF_PARTIAL
- ATM_VF_READY
- ATM_VF_REGIS
- ATM_VF_RELEASED
- ATM_VF_SESSION
- ATM_VF_WAITING
- ATM_VPI_ANY
- ATM_VPI_UNSPEC
- ATM_VS2TXT_MAP
- ATM_VS_BOUND
- ATM_VS_CLOSING
- ATM_VS_CONNECTED
- ATM_VS_IDLE
- ATM_VS_INUSE
- ATM_VS_LISTEN
- ATNTARG
- ATN_BUTTON
- ATN_CODE
- ATN_LED_STATE_BLINK
- ATN_LED_STATE_MASK
- ATN_LED_STATE_OFF
- ATN_LED_STATE_ON
- ATN_LED_STATE_SHIFT
- ATOMIC64_DECL
- ATOMIC64_DECL_ONE
- ATOMIC64_EXPORT
- ATOMIC64_FETCH_OP
- ATOMIC64_FETCH_OPS
- ATOMIC64_FETCH_OP_AND
- ATOMIC64_FETCH_OP_RELAXED
- ATOMIC64_FETCH_OP_SUB
- ATOMIC64_INIT
- ATOMIC64_OP
- ATOMIC64_OPS
- ATOMIC64_OP_ADD_RETURN
- ATOMIC64_OP_RETURN
- ATOMIC64_OP_RETURN_RELAXED
- ATOMIC64_OP_SUB_RETURN
- ATOMICACKETH_PRN
- ATOMICDONE
- ATOMICERR
- ATOMICETH_PRN
- ATOMICSTATCTL
- ATOMICWIN
- ATOMICXCHG
- ATOMIC_ACKNOWLEDGE
- ATOMIC_BITOP
- ATOMIC_FETCH_OP
- ATOMIC_FETCH_OPS
- ATOMIC_FETCH_OP_AND
- ATOMIC_FETCH_OP_RELAXED
- ATOMIC_FETCH_OP_SUB
- ATOMIC_FILE
- ATOMIC_HASH
- ATOMIC_HASH_SIZE
- ATOMIC_INIT
- ATOMIC_INITIALIZER
- ATOMIC_INIT_NOTIFIER_HEAD
- ATOMIC_LONG_INIT
- ATOMIC_MAYFAIL
- ATOMIC_NOTIFIER_HEAD
- ATOMIC_NOTIFIER_INIT
- ATOMIC_OP
- ATOMIC_OPS
- ATOMIC_OP_ADD_RETURN
- ATOMIC_OP_RETURN
- ATOMIC_OP_RETURN_RELAXED
- ATOMIC_OP_SUB_RETURN
- ATOMIC_TAG
- ATOMIC_TSSI_SETTING
- ATOMIC_WRITTEN_PAGE
- ATOM_ACC_CHANGE_ACC_MODE
- ATOM_ACC_CHANGE_ACC_MODE_SHIFT
- ATOM_ACC_CHANGE_INFO_DEF
- ATOM_ACC_CHANGE_LID_STATUS
- ATOM_ACC_CHANGE_LID_STATUS_SHIFT
- ATOM_ACTIVE_INFO_DEF
- ATOM_ACTIVE_INFO_DEVICE_MASK
- ATOM_ADJUST_MEMORY_CLOCK_FREQ
- ATOM_ANALOG_ENCODER
- ATOM_ANALOG_TV_INFO
- ATOM_ANALOG_TV_INFO_V1_2
- ATOM_ARG_FB
- ATOM_ARG_ID
- ATOM_ARG_IMM
- ATOM_ARG_MC
- ATOM_ARG_PLL
- ATOM_ARG_PS
- ATOM_ARG_REG
- ATOM_ARG_WS
- ATOM_ASIC_INIT_COMPLETE
- ATOM_ASIC_INTERNAL_SS_INFO
- ATOM_ASIC_INTERNAL_SS_INFO_V2
- ATOM_ASIC_INTERNAL_SS_INFO_V3
- ATOM_ASIC_MVDD_INFO
- ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE
- ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE
- ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE
- ATOM_ASIC_PROFILE_VOLTAGE
- ATOM_ASIC_PROFILING_INFO
- ATOM_ASIC_PROFILING_INFO_V2_1
- ATOM_ASIC_PROFILING_INFO_V3_1
- ATOM_ASIC_PROFILING_INFO_V3_2
- ATOM_ASIC_PROFILING_INFO_V3_3
- ATOM_ASIC_PROFILING_INFO_V3_4
- ATOM_ASIC_PROFILING_INFO_V3_5
- ATOM_ASIC_PROFILING_INFO_V3_6
- ATOM_ASIC_SS_ASSIGNMENT
- ATOM_ASIC_SS_ASSIGNMENT_V2
- ATOM_ASIC_SS_ASSIGNMENT_V3
- ATOM_ATI_MAGIC
- ATOM_ATI_MAGIC_PTR
- ATOM_AVAILABLE_SCLK_LIST
- ATOM_BIG_ENDIAN
- ATOM_BIOS_EXTENDED_FUNCTION_CODE
- ATOM_BIOS_FUNCTION_ASIC_DSTATE
- ATOM_BIOS_FUNCTION_COP_MODE
- ATOM_BIOS_FUNCTION_DEBUG_PLAY
- ATOM_BIOS_FUNCTION_DEVICE_DET
- ATOM_BIOS_FUNCTION_DEVICE_ON_OFF
- ATOM_BIOS_FUNCTION_DEVICE_SWITCH
- ATOM_BIOS_FUNCTION_DISPLAY_INFO
- ATOM_BIOS_FUNCTION_GET_DDC
- ATOM_BIOS_FUNCTION_HW_ICON
- ATOM_BIOS_FUNCTION_OLD_DEVICE_DET
- ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH
- ATOM_BIOS_FUNCTION_PANEL_CONTROL
- ATOM_BIOS_FUNCTION_SET_CMOS
- ATOM_BIOS_FUNCTION_SHORT_QUERY1
- ATOM_BIOS_FUNCTION_SHORT_QUERY2
- ATOM_BIOS_FUNCTION_SHORT_QUERY3
- ATOM_BIOS_FUNCTION_STV_STD
- ATOM_BIOS_FUNCTION_VESA_DPMS
- ATOM_BIOS_FUNCTION_VIDEO_STATE
- ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED
- ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE
- ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU
- ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT
- ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT
- ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT
- ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT
- ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK
- ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT
- ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT
- ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT
- ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM
- ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET
- ATOM_BIOS_INFO_WMI_SUPPORT
- ATOM_BIOS_INT_TVSTD_MODE
- ATOM_BIOS_MAGIC
- ATOM_BIOS_REG_HIGH_MASK
- ATOM_BIOS_REG_LOW_MASK
- ATOM_BIOS_RETURN_CODE_MASK
- ATOM_BITS_H
- ATOM_BLANKING
- ATOM_BLANKING_OFF
- ATOM_BL_BRI_LEVEL_INFO_DEF
- ATOM_BRACKET_LAYOUT_RECORD
- ATOM_BRACKET_LAYOUT_RECORD_TYPE
- ATOM_CASE_END
- ATOM_CASE_MAGIC
- ATOM_CLK_VOLT_CAPABILITY
- ATOM_CLK_VOLT_CAPABILITY_V2
- ATOM_CMD_INIT
- ATOM_CMD_SETMCLK
- ATOM_CMD_SETPCLK
- ATOM_CMD_SETSCLK
- ATOM_CMD_SPDFANCNTL
- ATOM_COMBOPHY_PLL0
- ATOM_COMBOPHY_PLL1
- ATOM_COMBOPHY_PLL2
- ATOM_COMBOPHY_PLL3
- ATOM_COMBOPHY_PLL4
- ATOM_COMBOPHY_PLL5
- ATOM_COMMON_RECORD_HEADER
- ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
- ATOM_COMMON_TABLE_HEADER
- ATOM_COMPONENT_VIDEO_INFO
- ATOM_COMPONENT_VIDEO_INFO_LAST
- ATOM_COMPONENT_VIDEO_INFO_V21
- ATOM_COMPOSITESYNC
- ATOM_COMPUTE_CLOCK_FREQ
- ATOM_COND_ABOVE
- ATOM_COND_ABOVEOREQUAL
- ATOM_COND_ALWAYS
- ATOM_COND_BELOW
- ATOM_COND_BELOWOREQUAL
- ATOM_COND_EQUAL
- ATOM_COND_NOTEQUAL
- ATOM_CONNECTOR_AUXDDC_LUT_RECORD
- ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
- ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY
- ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL
- ATOM_CONNECTOR_CF_RECORD
- ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB
- ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA
- ATOM_CONNECTOR_CF_RECORD_TYPE
- ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
- ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE
- ATOM_CONNECTOR_DEVICE_TAG
- ATOM_CONNECTOR_DEVICE_TAG_RECORD
- ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE
- ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
- ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE
- ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD
- ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
- ATOM_CONNECTOR_HARDCODE_DTD_RECORD
- ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE
- ATOM_CONNECTOR_HPDPIN_LUT_RECORD
- ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
- ATOM_CONNECTOR_INC_SRC_BITMAP
- ATOM_CONNECTOR_INFO
- ATOM_CONNECTOR_INFO_ACCESS
- ATOM_CONNECTOR_INFO_I2C
- ATOM_CONNECTOR_LAYOUT_INFO
- ATOM_CONNECTOR_OBJECT_TABLE
- ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
- ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
- ATOM_CONNECTOR_REMOTE_CAP_RECORD
- ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE
- ATOM_CONNECT_INFO_DEVICE_MASK
- ATOM_CRT1
- ATOM_CRT1_DTD_MODE_TBL_ADDR
- ATOM_CRT1_EDID_ADDR
- ATOM_CRT1_STD_MODE_TBL_ADDR
- ATOM_CRT2
- ATOM_CRT2_DTD_MODE_TBL_ADDR
- ATOM_CRT2_EDID_ADDR
- ATOM_CRT2_STD_MODE_TBL_ADDR
- ATOM_CRTC1
- ATOM_CRTC2
- ATOM_CRTC3
- ATOM_CRTC4
- ATOM_CRTC5
- ATOM_CRTC6
- ATOM_CRTC_INVALID
- ATOM_CRT_EXT_ENCODER1_INDEX
- ATOM_CRT_INT_ENCODER1_INDEX
- ATOM_CRT_INT_ENCODER2_INDEX
- ATOM_CT_CODE_PTR
- ATOM_CT_PS_MASK
- ATOM_CT_PS_PTR
- ATOM_CT_SIZE_PTR
- ATOM_CT_WS_PTR
- ATOM_CURRENT_BL_LEVEL_MASK
- ATOM_CURRENT_BL_LEVEL_SHIFT
- ATOM_CURSOR1
- ATOM_CURSOR2
- ATOM_CV_DTD_MODE_TBL_ADDR
- ATOM_CV_EDID_ADDR
- ATOM_CV_EXT_ENCODER1_INDEX
- ATOM_CV_INT_ENCODER1_INDEX
- ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A
- ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B
- ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT
- ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A
- ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B
- ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT
- ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A
- ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B
- ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT
- ATOM_CV_LINE3_ASPECTRATIO_EXIST
- ATOM_CV_LINE3_ASPECTRATIO_MASK
- ATOM_CV_RESTRICT_FORMAT_SELECTION
- ATOM_CV_STD_MODE_TBL_ADDR
- ATOM_DAC1_CV
- ATOM_DAC1_NTSC
- ATOM_DAC1_PAL
- ATOM_DAC1_PS2
- ATOM_DAC2_CV
- ATOM_DAC2_NTSC
- ATOM_DAC2_PAL
- ATOM_DAC2_PS2
- ATOM_DAC_A
- ATOM_DAC_B
- ATOM_DAC_INFO
- ATOM_DAC_SRC
- ATOM_DATA_FWI_PTR
- ATOM_DATA_IIO_PTR
- ATOM_DCPLL
- ATOM_DEBUG
- ATOM_DEVICE_CONNECTOR_CASE_1
- ATOM_DEVICE_CONNECTOR_COMPOSITE
- ATOM_DEVICE_CONNECTOR_DIGI_LINK
- ATOM_DEVICE_CONNECTOR_DISPLAYPORT
- ATOM_DEVICE_CONNECTOR_DVI_A
- ATOM_DEVICE_CONNECTOR_DVI_D
- ATOM_DEVICE_CONNECTOR_DVI_I
- ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A
- ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B
- ATOM_DEVICE_CONNECTOR_LVDS
- ATOM_DEVICE_CONNECTOR_SCART
- ATOM_DEVICE_CONNECTOR_SVIDEO
- ATOM_DEVICE_CONNECTOR_TYPE_MASK
- ATOM_DEVICE_CONNECTOR_TYPE_SHIFT
- ATOM_DEVICE_CONNECTOR_VGA
- ATOM_DEVICE_CONNECT_INFO_DEF
- ATOM_DEVICE_CRT1_INDEX
- ATOM_DEVICE_CRT1_SUPPORT
- ATOM_DEVICE_CRT2_INDEX
- ATOM_DEVICE_CRT2_SUPPORT
- ATOM_DEVICE_CRT_SUPPORT
- ATOM_DEVICE_CV_INDEX
- ATOM_DEVICE_CV_SUPPORT
- ATOM_DEVICE_DAC_INFO_DACA
- ATOM_DEVICE_DAC_INFO_DACB
- ATOM_DEVICE_DAC_INFO_EXDAC
- ATOM_DEVICE_DAC_INFO_MASK
- ATOM_DEVICE_DAC_INFO_NODAC
- ATOM_DEVICE_DAC_INFO_SHIFT
- ATOM_DEVICE_DFP1I_INDEX
- ATOM_DEVICE_DFP1I_SUPPORT
- ATOM_DEVICE_DFP1X_INDEX
- ATOM_DEVICE_DFP1X_SUPPORT
- ATOM_DEVICE_DFP1_INDEX
- ATOM_DEVICE_DFP1_SUPPORT
- ATOM_DEVICE_DFP2I_INDEX
- ATOM_DEVICE_DFP2I_SUPPORT
- ATOM_DEVICE_DFP2_INDEX
- ATOM_DEVICE_DFP2_SUPPORT
- ATOM_DEVICE_DFP3_INDEX
- ATOM_DEVICE_DFP3_SUPPORT
- ATOM_DEVICE_DFP4_INDEX
- ATOM_DEVICE_DFP4_SUPPORT
- ATOM_DEVICE_DFP5_INDEX
- ATOM_DEVICE_DFP5_SUPPORT
- ATOM_DEVICE_DFP6_INDEX
- ATOM_DEVICE_DFP6_SUPPORT
- ATOM_DEVICE_DFP_SUPPORT
- ATOM_DEVICE_DPMS_STATE
- ATOM_DEVICE_I2C_HARDWARE_CAP_MASK
- ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT
- ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL
- ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE
- ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE
- ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE
- ATOM_DEVICE_I2C_ID_MASK
- ATOM_DEVICE_I2C_ID_NOI2C
- ATOM_DEVICE_I2C_ID_SHIFT
- ATOM_DEVICE_I2C_LINEMUX_MASK
- ATOM_DEVICE_I2C_LINEMUX_SHIFT
- ATOM_DEVICE_LCD1_INDEX
- ATOM_DEVICE_LCD1_SUPPORT
- ATOM_DEVICE_LCD2_INDEX
- ATOM_DEVICE_LCD2_SUPPORT
- ATOM_DEVICE_LCD_SUPPORT
- ATOM_DEVICE_REQ_INFO_DEF
- ATOM_DEVICE_RESERVEDC_INDEX
- ATOM_DEVICE_RESERVEDD_INDEX
- ATOM_DEVICE_RESERVEDE_INDEX
- ATOM_DEVICE_RESERVEDF_INDEX
- ATOM_DEVICE_TV1_INDEX
- ATOM_DEVICE_TV1_SUPPORT
- ATOM_DEVICE_TV2_INDEX
- ATOM_DEVICE_TV2_SUPPORT
- ATOM_DEVICE_TV_SUPPORT
- ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C
- ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C
- ATOM_DFP1_DTD_MODE_TBL_ADDR
- ATOM_DFP1_EDID_ADDR
- ATOM_DFP1_STD_MODE_TBL_ADDR
- ATOM_DFP2_DTD_MODE_TBL_ADDR
- ATOM_DFP2_EDID_ADDR
- ATOM_DFP2_STD_MODE_TBL_ADDR
- ATOM_DFP3_DTD_MODE_TBL_ADDR
- ATOM_DFP3_EDID_ADDR
- ATOM_DFP3_STD_MODE_TBL_ADDR
- ATOM_DFP4_DTD_MODE_TBL_ADDR
- ATOM_DFP4_EDID_ADDR
- ATOM_DFP4_STD_MODE_TBL_ADDR
- ATOM_DFP5_DTD_MODE_TBL_ADDR
- ATOM_DFP5_EDID_ADDR
- ATOM_DFP5_STD_MODE_TBL_ADDR
- ATOM_DFP6_DTD_MODE_TBL_ADDR
- ATOM_DFP6_EDID_ADDR
- ATOM_DFP6_STD_MODE_TBL_ADDR
- ATOM_DFP_EXT_ENCODER1_INDEX
- ATOM_DFP_INT_ENCODER1_INDEX
- ATOM_DFP_INT_ENCODER2_INDEX
- ATOM_DFP_INT_ENCODER3_INDEX
- ATOM_DFP_INT_ENCODER4_INDEX
- ATOM_DGPU_VRAM_TYPE_GDDR5
- ATOM_DGPU_VRAM_TYPE_GDDR6
- ATOM_DGPU_VRAM_TYPE_HBM2
- ATOM_DIGA
- ATOM_DIGB
- ATOM_DIGITAL_ENCODER
- ATOM_DIG_ENCODER_CONFIG_V2
- ATOM_DIG_ENCODER_CONFIG_V3
- ATOM_DIG_ENCODER_CONFIG_V4
- ATOM_DIG_TRANSMITTER_CONFIG_V2
- ATOM_DIG_TRANSMITTER_CONFIG_V3
- ATOM_DIG_TRANSMITTER_CONFIG_V4
- ATOM_DIG_TRANSMITTER_CONFIG_V5
- ATOM_DISABLE
- ATOM_DISPLAY_DEVICE_PRIORITY_INFO
- ATOM_DISPLAY_DFP1_ACTIVE
- ATOM_DISPLAY_DFP1_CONNECT
- ATOM_DISPLAY_DFP1_REQ
- ATOM_DISPLAY_DFP1_SUPPORT
- ATOM_DISPLAY_DFP2_ACTIVE
- ATOM_DISPLAY_DFP2_CONNECT
- ATOM_DISPLAY_DFP2_REQ
- ATOM_DISPLAY_DFP2_SUPPORT
- ATOM_DISPLAY_DFP3_ACTIVE
- ATOM_DISPLAY_DFP3_CONNECT
- ATOM_DISPLAY_DFP3_REQ
- ATOM_DISPLAY_DFP3_SUPPORT
- ATOM_DISPLAY_DFP4_ACTIVE
- ATOM_DISPLAY_DFP4_CONNECT
- ATOM_DISPLAY_DFP4_REQ
- ATOM_DISPLAY_DFP4_SUPPORT
- ATOM_DISPLAY_DFP5_ACTIVE
- ATOM_DISPLAY_DFP5_CONNECT
- ATOM_DISPLAY_DFP5_REQ
- ATOM_DISPLAY_DFP5_SUPPORT
- ATOM_DISPLAY_DFP6_ACTIVE
- ATOM_DISPLAY_DFP6_CONNECT
- ATOM_DISPLAY_DFP6_REQ
- ATOM_DISPLAY_DFP6_SUPPORT
- ATOM_DISPLAY_DFPx_CONNECT
- ATOM_DISPLAY_DFPx_SUPPORT
- ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
- ATOM_DISPLAY_LCD1_ACTIVE
- ATOM_DISPLAY_LCD1_CONNECT
- ATOM_DISPLAY_LCD1_REQ
- ATOM_DISPLAY_LCD1_SUPPORT
- ATOM_DISPLAY_OBJECT_PATH
- ATOM_DISPLAY_OBJECT_PATH_TABLE
- ATOM_DISP_CLOCK_ID
- ATOM_DISP_OUT_INFO
- ATOM_DISP_OUT_INFO_V2
- ATOM_DISP_OUT_INFO_V3
- ATOM_DOS_MODE_INFO_DEF
- ATOM_DOS_REQ_INFO_DEF
- ATOM_DOUBLE_CLOCK_MODE
- ATOM_DPCD_INFO
- ATOM_DPCD_MAX_LANE_MASK
- ATOM_DP_ACTION_BLANKING
- ATOM_DP_ACTION_GET_SINK_TYPE
- ATOM_DP_ACTION_GET_VSWING_PREEMP
- ATOM_DP_ACTION_SET_VSWING_PREEMP
- ATOM_DP_ACTION_TRAINING_COMPLETE
- ATOM_DP_ACTION_TRAINING_PATTERN_SEL
- ATOM_DP_ACTION_TRAINING_START
- ATOM_DP_CONFIG_DIG1_ENCODER
- ATOM_DP_CONFIG_DIG2_ENCODER
- ATOM_DP_CONFIG_ENCODER_SEL_MASK
- ATOM_DP_CONFIG_EXTERNAL_ENCODER
- ATOM_DP_CONFIG_LINK_A
- ATOM_DP_CONFIG_LINK_B
- ATOM_DP_CONFIG_LINK_SEL_MASK
- ATOM_DP_CONN_CHANNEL_MAPPING
- ATOM_DP_DPCD_OFFSET
- ATOM_DP_DTO
- ATOM_DP_ENCODER
- ATOM_DP_SS_ID1
- ATOM_DP_SS_ID2
- ATOM_DP_TRAINING_TBL_ADDR
- ATOM_DP_VS_MODE
- ATOM_DP_VS_MODE_V4
- ATOM_DRAM_DATA_REMAP
- ATOM_DTD_FORMAT
- ATOM_DTD_MODE_SUPPORT_TBL_SIZE
- ATOM_DVI_CONN_CHANNEL_MAPPING
- ATOM_EDID_RAW_DATASIZE
- ATOM_ENABLE
- ATOM_ENABLE_DP_HBR3_TUNINGSET
- ATOM_ENABLE_DP_TUNINGSET
- ATOM_ENABLE_DVI_TUNINGSET
- ATOM_ENABLE_HDMI6G_TUNINGSET
- ATOM_ENABLE_HDMI_TUNINGSET
- ATOM_ENCODER_ANALOG_ATTRIBUTE
- ATOM_ENCODER_ATTRIBUTE
- ATOM_ENCODER_CAP_RECORD
- ATOM_ENCODER_CAP_RECORD_HBR2
- ATOM_ENCODER_CAP_RECORD_HBR2_EN
- ATOM_ENCODER_CAP_RECORD_HBR3_EN
- ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN
- ATOM_ENCODER_CAP_RECORD_MST_EN
- ATOM_ENCODER_CAP_RECORD_TYPE
- ATOM_ENCODER_CAP_RECORD_USB_C_TYPE
- ATOM_ENCODER_CAP_RECORD_V2
- ATOM_ENCODER_CMD_DISABLE_DIG
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4
- ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
- ATOM_ENCODER_CMD_DP_VIDEO_OFF
- ATOM_ENCODER_CMD_DP_VIDEO_ON
- ATOM_ENCODER_CMD_ENABLE_DIG
- ATOM_ENCODER_CMD_ENCODER_BLANK
- ATOM_ENCODER_CMD_LINK_SETUP
- ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
- ATOM_ENCODER_CMD_SETUP
- ATOM_ENCODER_CMD_SETUP_PANEL_MODE
- ATOM_ENCODER_CMD_STREAM_SETUP
- ATOM_ENCODER_CONFIG_DIGB
- ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ
- ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
- ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ
- ATOM_ENCODER_CONFIG_DPLINKRATE_MASK
- ATOM_ENCODER_CONFIG_LINKA
- ATOM_ENCODER_CONFIG_LINKA_B
- ATOM_ENCODER_CONFIG_LINKB
- ATOM_ENCODER_CONFIG_LINKB_A
- ATOM_ENCODER_CONFIG_LINK_SEL_MASK
- ATOM_ENCODER_CONFIG_LVTMA
- ATOM_ENCODER_CONFIG_TRANSMITTER1
- ATOM_ENCODER_CONFIG_TRANSMITTER2
- ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK
- ATOM_ENCODER_CONFIG_UNIPHY
- ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ
- ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ
- ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK
- ATOM_ENCODER_CONFIG_V2_LINKA
- ATOM_ENCODER_CONFIG_V2_LINKB
- ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK
- ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
- ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
- ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
- ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK
- ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER
- ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER
- ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER
- ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER
- ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER
- ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER
- ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ
- ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
- ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK
- ATOM_ENCODER_CONFIG_V3_ENCODER_SEL
- ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER
- ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER
- ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ
- ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
- ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ
- ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
- ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK
- ATOM_ENCODER_CONFIG_V4_ENCODER_SEL
- ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER
- ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER
- ATOM_ENCODER_DIGITAL_ATTRIBUTE
- ATOM_ENCODER_DVO_CF_RECORD
- ATOM_ENCODER_DVO_CF_RECORD_TYPE
- ATOM_ENCODER_ENUM_ID1
- ATOM_ENCODER_ENUM_ID2
- ATOM_ENCODER_ENUM_ID3
- ATOM_ENCODER_ENUM_ID4
- ATOM_ENCODER_ENUM_ID5
- ATOM_ENCODER_ENUM_ID6
- ATOM_ENCODER_ENUM_MASK
- ATOM_ENCODER_FPGA_CONTROL_RECORD
- ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE
- ATOM_ENCODER_INIT
- ATOM_ENCODER_MODE_CRT
- ATOM_ENCODER_MODE_CV
- ATOM_ENCODER_MODE_DP
- ATOM_ENCODER_MODE_DP_AUDIO
- ATOM_ENCODER_MODE_DP_MST
- ATOM_ENCODER_MODE_DP_SST
- ATOM_ENCODER_MODE_DVI
- ATOM_ENCODER_MODE_DVO
- ATOM_ENCODER_MODE_HDMI
- ATOM_ENCODER_MODE_LVDS
- ATOM_ENCODER_MODE_SDVO
- ATOM_ENCODER_MODE_TV
- ATOM_ENCODER_OBJECT_TABLE
- ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE
- ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE
- ATOM_EVV_DPM_INFO
- ATOM_EVV_VOLTAGE_OBJECT_V3
- ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
- ATOM_EXTERNAL_SS_MASK
- ATOM_EXT_CLOCK
- ATOM_EXT_DAC
- ATOM_EXT_PLL1
- ATOM_EXT_PLL2
- ATOM_FAKE_DESKTOP_STRING
- ATOM_FAKE_EDID_PATCH_RECORD
- ATOM_FCH_CLK
- ATOM_FEATURE_NOT_SUPPORTED
- ATOM_FEATURE_SUPPORTED
- ATOM_FIREGL_FLAG_STRING
- ATOM_FIRMWARE_CAPABILITY
- ATOM_FIRMWARE_CAPABILITY_ACCESS
- ATOM_FIRMWARE_CAP_FIRMWARE_POSTED
- ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION
- ATOM_FIRMWARE_CAP_HWEMU_ENABLE
- ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG
- ATOM_FIRMWARE_CAP_SRAM_ECC
- ATOM_FIRMWARE_CAP_WMI_SUPPORT
- ATOM_FIRMWARE_INFO
- ATOM_FIRMWARE_INFO_LAST
- ATOM_FIRMWARE_INFO_V1_2
- ATOM_FIRMWARE_INFO_V1_3
- ATOM_FIRMWARE_INFO_V1_4
- ATOM_FIRMWARE_INFO_V2_1
- ATOM_FIRMWARE_INFO_V2_2
- ATOM_FIRMWARE_VRAM_RESERVE_INFO
- ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
- ATOM_FLAG_CLEAR
- ATOM_FLAG_SET
- ATOM_FUSION_SYSTEM_INFO_V1
- ATOM_FUSION_SYSTEM_INFO_V2
- ATOM_FUSION_SYSTEM_INFO_V3
- ATOM_FWI_DEFMCLK_PTR
- ATOM_FWI_DEFSCLK_PTR
- ATOM_FWI_MAXMCLK_PTR
- ATOM_FWI_MAXSCLK_PTR
- ATOM_Fiji_Fan_Table
- ATOM_Fiji_PowerTune_Table
- ATOM_GCK_DFS
- ATOM_GET_LEAKAGE_ID
- ATOM_GET_MAX_VOLTAGE
- ATOM_GET_SDI_SUPPORT
- ATOM_GET_STATUS
- ATOM_GET_VOLTAGE_EVV_VOLTAGE
- ATOM_GET_VOLTAGE_LEVEL
- ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID
- ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID
- ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID
- ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID
- ATOM_GET_VOLTAGE_SVID2
- ATOM_GET_VOLTAGE_VID
- ATOM_GET_VOLTTAGE_PHASE_PHASE_VID
- ATOM_GET_VOTLAGE_INIT_SEQ
- ATOM_GFX_INFO_V2_1
- ATOM_GPIO_DEFAULT_MODE_EN
- ATOM_GPIO_I2C_ASSIGMENT
- ATOM_GPIO_I2C_INFO
- ATOM_GPIO_INDEX_GLSYNC_HSYNC
- ATOM_GPIO_INDEX_GLSYNC_INTERRUPT
- ATOM_GPIO_INDEX_GLSYNC_MAX
- ATOM_GPIO_INDEX_GLSYNC_REFCLK
- ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL
- ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT
- ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ
- ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL
- ATOM_GPIO_INDEX_GLSYNC_VSYNC
- ATOM_GPIO_INDEX_GLSYNC_V_RESET
- ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A
- ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B
- ATOM_GPIO_INFO
- ATOM_GPIO_PIN_ASSIGNMENT
- ATOM_GPIO_PIN_CONTROL_PAIR
- ATOM_GPIO_PIN_LUT
- ATOM_GPIO_SETTINGS_ACTIVE_MASK
- ATOM_GPIO_SETTINGS_BITSHIFT_MASK
- ATOM_GPIO_SETTINGS_RESERVED_MASK
- ATOM_GPIO_SETTING_PERMODE_MASK
- ATOM_GPIO_VOLTAGE_OBJECT_V3
- ATOM_GPU_VIRTUALIZATION_INFO_V2_1
- ATOM_GRAPH_CONTROL_SET_DISP_START
- ATOM_GRAPH_CONTROL_SET_PITCH
- ATOM_H
- ATOM_HEADER_VERSION
- ATOM_HOLE_INFO
- ATOM_HPD_INT_RECORD
- ATOM_HPD_INT_RECORD_TYPE
- ATOM_HSYNC_POLARITY
- ATOM_HWICON1_SURFACE_ADDR
- ATOM_HWICON2_SURFACE_ADDR
- ATOM_HWICON_INFOTABLE_ADDR
- ATOM_HWICON_INFOTABLE_SIZE
- ATOM_HWICON_SURFACE_SIZE
- ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
- ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
- ATOM_HW_MISC_OPERATION_PS_ALLOCATION
- ATOM_H_CUTOFF
- ATOM_H_REPLICATIONBY2
- ATOM_I2C_CHANNEL_STATUS1_DEF
- ATOM_I2C_CHANNEL_STATUS_DEF
- ATOM_I2C_DATA_RECORD
- ATOM_I2C_DEVICE_SETUP_INFO
- ATOM_I2C_ID_CONFIG
- ATOM_I2C_ID_CONFIG_ACCESS
- ATOM_I2C_RECORD
- ATOM_I2C_RECORD_TYPE
- ATOM_I2C_REG_INFO
- ATOM_I2C_VOLTAGE_OBJECT_V3
- ATOM_ICON1
- ATOM_ICON2
- ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE
- ATOM_IIO_CLEAR
- ATOM_IIO_END
- ATOM_IIO_MOVE_ATTR
- ATOM_IIO_MOVE_DATA
- ATOM_IIO_MOVE_INDEX
- ATOM_IIO_NOP
- ATOM_IIO_READ
- ATOM_IIO_SET
- ATOM_IIO_START
- ATOM_IIO_WRITE
- ATOM_INIT
- ATOM_INIT_REG_BLOCK
- ATOM_INIT_REG_INDEX_FORMAT
- ATOM_INIT_REG_MASK_FLAG
- ATOM_INIT_VOLTAGE_REGULATOR
- ATOM_INTEGRATED_SYSTEM_INFO
- ATOM_INTEGRATED_SYSTEM_INFO_V1_10
- ATOM_INTEGRATED_SYSTEM_INFO_V1_7
- ATOM_INTEGRATED_SYSTEM_INFO_V1_8
- ATOM_INTEGRATED_SYSTEM_INFO_V1_9
- ATOM_INTEGRATED_SYSTEM_INFO_V2
- ATOM_INTEGRATED_SYSTEM_INFO_V5
- ATOM_INTEGRATED_SYSTEM_INFO_V6
- ATOM_INTERLACE
- ATOM_INTERNAL_SS_MASK
- ATOM_INTERNAL_TIMER_DEF
- ATOM_INTERNAL_TIMER_INFO_DEF
- ATOM_INT_OR_EXT_SS_MASK
- ATOM_IO_IIO
- ATOM_IO_MM
- ATOM_IO_NAMES_CNT
- ATOM_IO_PCI
- ATOM_IO_SYSIO
- ATOM_JTAG_RECORD
- ATOM_JTAG_RECORD_TYPE
- ATOM_LCD1_DTD_MODE_TBL_ADDR
- ATOM_LCD1_EDID_ADDR
- ATOM_LCD1_STD_MODE_TBL_ADDR
- ATOM_LCD2_DTD_MODE_TBL_ADDR
- ATOM_LCD2_EDID_ADDR
- ATOM_LCD2_STD_MODE_TBL_ADDR
- ATOM_LCD_BLOFF
- ATOM_LCD_BLON
- ATOM_LCD_BL_BRIGHTNESS_CONTROL
- ATOM_LCD_BL_OFF
- ATOM_LCD_BL_OM
- ATOM_LCD_EXT_ENCODER1_INDEX
- ATOM_LCD_INFO_DEF
- ATOM_LCD_INFO_LAST
- ATOM_LCD_INFO_V13
- ATOM_LCD_INT_ENCODER1_INDEX
- ATOM_LCD_MODE_CONTROL_CAP
- ATOM_LCD_REFRESH_RATE_SUPPORT
- ATOM_LCD_RTS_RECORD
- ATOM_LCD_SELFTEST_START
- ATOM_LCD_SELFTEST_STOP
- ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
- ATOM_LEAKID_VOLTAGE
- ATOM_LVDS_INFO
- ATOM_LVDS_INFO_LAST
- ATOM_LVDS_INFO_V12
- ATOM_LVLINK_1620MHz_SS_ID
- ATOM_LVLINK_2700MHz_SS_ID
- ATOM_M54T_FLAG_STRING
- ATOM_MAJOR_VERSION
- ATOM_MASTER_COMMAND_TABLE
- ATOM_MASTER_DATA_TABLE
- ATOM_MASTER_DATA_TABLE_REVISION
- ATOM_MASTER_LIST_OF_COMMAND_TABLES
- ATOM_MASTER_LIST_OF_DATA_TABLES
- ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO
- ATOM_MAX_HW_I2C_READ
- ATOM_MAX_HW_I2C_WRITE
- ATOM_MAX_MISC_INFO
- ATOM_MAX_NUMBEROF_POWER_BLOCK
- ATOM_MAX_NUMBER_OF_VRAM_MODULE
- ATOM_MAX_OBJECT_RECORD_NUMBER
- ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING
- ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
- ATOM_MAX_SIZE_OF_M54T_FLAG_STRING
- ATOM_MAX_SS_ENTRY
- ATOM_MAX_SUPPORTED_DEVICE
- ATOM_MAX_SUPPORTED_DEVICE_INFO
- ATOM_MAX_SUPPORTED_DEVICE_INFO_2
- ATOM_MAX_SUPPORTED_DEVICE_INFO_3
- ATOM_MCLK_SS_INFO
- ATOM_MC_INIT_PARAM_TABLE
- ATOM_MC_INIT_PARAM_TABLE_V2_1
- ATOM_MEMORY_FORMAT
- ATOM_MEMORY_SETTING_DATA_BLOCK
- ATOM_MEMORY_SETTING_ID_CONFIG
- ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
- ATOM_MEMORY_TIMING_FORMAT
- ATOM_MEMORY_TIMING_FORMAT_V1
- ATOM_MEMORY_TIMING_FORMAT_V2
- ATOM_MEMORY_TRAINING_INFO
- ATOM_MEMORY_TRAINING_INFO_V3_1
- ATOM_MEMORY_VENDOR_BLOCK
- ATOM_MEM_TYPE_DDR2_STRING
- ATOM_MEM_TYPE_DDR3_STRING
- ATOM_MEM_TYPE_DDR_STRING
- ATOM_MEM_TYPE_GDDR3_STRING
- ATOM_MEM_TYPE_GDDR4_STRING
- ATOM_MEM_TYPE_GDDR5_STRING
- ATOM_MEM_TYPE_HBM_STRING
- ATOM_MERGED_VOLTAGE_OBJECT_V3
- ATOM_MINOR_VERSION
- ATOM_MISC_CONTROL_INFO
- ATOM_MODE_MISC_INFO
- ATOM_MODE_MISC_INFO_ACCESS
- ATOM_MODE_TIMING
- ATOM_MULTIMEDIA_CAPABILITY_INFO
- ATOM_MULTIMEDIA_CONFIG_INFO
- ATOM_NAMES_H
- ATOM_OBJECT
- ATOM_OBJECT_GPIO_CNTL_RECORD
- ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
- ATOM_OBJECT_HEADER
- ATOM_OBJECT_HEADER_V3
- ATOM_OBJECT_LINK_RECORD
- ATOM_OBJECT_LINK_RECORD_TYPE
- ATOM_OBJECT_TABLE
- ATOM_OEM_INFO
- ATOM_OP_CNT
- ATOM_OP_EOT
- ATOM_OP_NAMES_CNT
- ATOM_OUTPUT_PROTECTION_RECORD
- ATOM_OUTPUT_PROTECTION_RECORD_TYPE
- ATOM_PANEL_MISC_888RGB
- ATOM_PANEL_MISC_API_ENABLED
- ATOM_PANEL_MISC_DUAL
- ATOM_PANEL_MISC_FPDI
- ATOM_PANEL_MISC_GREY_LEVEL
- ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
- ATOM_PANEL_MISC_SPATIAL
- ATOM_PANEL_MISC_TEMPORAL
- ATOM_PANEL_MISC_V13_6BIT_PER_COLOR
- ATOM_PANEL_MISC_V13_8BIT_PER_COLOR
- ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK
- ATOM_PANEL_MISC_V13_DUAL
- ATOM_PANEL_MISC_V13_FPDI
- ATOM_PANEL_MISC_V13_GREY_LEVEL
- ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT
- ATOM_PANEL_RESOLUTION_PATCH_RECORD
- ATOM_PARAMETER_VESA_DPMS_OFF
- ATOM_PARAMETER_VESA_DPMS_ON
- ATOM_PARAMETER_VESA_DPMS_REDUCE_ON
- ATOM_PARAMETER_VESA_DPMS_STANDBY
- ATOM_PARAMETER_VESA_DPMS_SUSPEND
- ATOM_PATCH_RECORD_MODE
- ATOM_PHY_ID_UNIPHYA
- ATOM_PHY_ID_UNIPHYB
- ATOM_PHY_ID_UNIPHYC
- ATOM_PHY_ID_UNIPHYD
- ATOM_PHY_ID_UNIPHYE
- ATOM_PHY_ID_UNIPHYF
- ATOM_PHY_ID_UNIPHYG
- ATOM_PHY_PLL0
- ATOM_PHY_PLL1
- ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE
- ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE
- ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN
- ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9
- ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN
- ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN
- ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE
- ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO
- ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT
- ATOM_PM_MISCINFO2_NOT_VALID_ON_DC
- ATOM_PM_MISCINFO2_STUTTER_MODE_EN
- ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
- ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE
- ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
- ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE
- ATOM_PM_MISCINFO_3D_ACCELERATION_EN
- ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN
- ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN
- ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN
- ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
- ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
- ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
- ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2
- ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4
- ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN
- ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN
- ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE
- ATOM_PM_MISCINFO_ENABLE_BACK_BIAS
- ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN
- ATOM_PM_MISCINFO_FRAME_MODULATION_MASK
- ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT
- ATOM_PM_MISCINFO_LOAD_BALANCE_EN
- ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN
- ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE
- ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN
- ATOM_PM_MISCINFO_OVER_CLOCK_MODE
- ATOM_PM_MISCINFO_OVER_DRIVE_MODE
- ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK
- ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT
- ATOM_PM_MISCINFO_POWER_SAVING_MODE
- ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
- ATOM_PM_MISCINFO_SPLIT_CLOCK
- ATOM_PM_MISCINFO_THERMAL_DIODE_MODE
- ATOM_PM_MISCINFO_USING_MCLK_SRC
- ATOM_PM_MISCINFO_USING_SCLK_SRC
- ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
- ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
- ATOM_PM_OFF
- ATOM_PM_ON
- ATOM_PM_STANDBY
- ATOM_PM_SUSPEND
- ATOM_PORT_ATI
- ATOM_PORT_PCI
- ATOM_PORT_SYSIO
- ATOM_POWERMODE_INFO
- ATOM_POWERMODE_INFO_V2
- ATOM_POWERMODE_INFO_V3
- ATOM_POWERPLAY_INFO
- ATOM_POWERPLAY_INFO_V2
- ATOM_POWERPLAY_INFO_V3
- ATOM_POWER_SOURCE_INFO
- ATOM_POWER_SOURCE_OBJECT
- ATOM_PPLIB_ACPClk_Voltage_Limit_Record
- ATOM_PPLIB_ACPClk_Voltage_Limit_Table
- ATOM_PPLIB_ACP_Table
- ATOM_PPLIB_CAC_Leakage_Record
- ATOM_PPLIB_CAC_Leakage_Table
- ATOM_PPLIB_CI_CLOCK_INFO
- ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2
- ATOM_PPLIB_CLASSIFICATION2_MVC
- ATOM_PPLIB_CLASSIFICATION2_ULV
- ATOM_PPLIB_CLASSIFICATION_3DLOW
- ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
- ATOM_PPLIB_CLASSIFICATION_ACPI
- ATOM_PPLIB_CLASSIFICATION_BOOT
- ATOM_PPLIB_CLASSIFICATION_FORCED
- ATOM_PPLIB_CLASSIFICATION_HD2STATE
- ATOM_PPLIB_CLASSIFICATION_HDSTATE
- ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE
- ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE
- ATOM_PPLIB_CLASSIFICATION_REST
- ATOM_PPLIB_CLASSIFICATION_SDSTATE
- ATOM_PPLIB_CLASSIFICATION_THERMAL
- ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
- ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
- ATOM_PPLIB_CLASSIFICATION_UI_MASK
- ATOM_PPLIB_CLASSIFICATION_UI_NONE
- ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
- ATOM_PPLIB_CLASSIFICATION_UI_SHIFT
- ATOM_PPLIB_CLASSIFICATION_UVDSTATE
- ATOM_PPLIB_CZ_CLOCK_INFO
- ATOM_PPLIB_Clock_Voltage_Dependency_Record
- ATOM_PPLIB_Clock_Voltage_Dependency_Table
- ATOM_PPLIB_Clock_Voltage_Limit_Record
- ATOM_PPLIB_Clock_Voltage_Limit_Table
- ATOM_PPLIB_DISALLOW_ON_DC
- ATOM_PPLIB_ENABLE_DRR
- ATOM_PPLIB_ENABLE_VARIBRIGHT
- ATOM_PPLIB_EVERGREEN_CLOCK_INFO
- ATOM_PPLIB_EXTENDEDHEADER
- ATOM_PPLIB_FANTABLE
- ATOM_PPLIB_FANTABLE2
- ATOM_PPLIB_FANTABLE3
- ATOM_PPLIB_FANTABLE4
- ATOM_PPLIB_FANTABLE5
- ATOM_PPLIB_KV_CLOCK_INFO
- ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ
- ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED
- ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK
- ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT
- ATOM_PPLIB_M3ARB_MASK
- ATOM_PPLIB_M3ARB_SHIFT
- ATOM_PPLIB_NONCLOCKINFO_VER1
- ATOM_PPLIB_NONCLOCKINFO_VER2
- ATOM_PPLIB_NONCLOCK_INFO
- ATOM_PPLIB_PCIE_LINK_SPEED_MASK
- ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT
- ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
- ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
- ATOM_PPLIB_POWERPLAYTABLE
- ATOM_PPLIB_POWERPLAYTABLE2
- ATOM_PPLIB_POWERPLAYTABLE3
- ATOM_PPLIB_POWERPLAYTABLE4
- ATOM_PPLIB_POWERPLAYTABLE5
- ATOM_PPLIB_POWERTUNE_Table
- ATOM_PPLIB_POWERTUNE_Table_V1
- ATOM_PPLIB_PPM_Table
- ATOM_PPLIB_PhaseSheddingLimits_Record
- ATOM_PPLIB_PhaseSheddingLimits_Table
- ATOM_PPLIB_R600_CLOCK_INFO
- ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE
- ATOM_PPLIB_R600_FLAGS_LOWPOWER
- ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF
- ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF
- ATOM_PPLIB_R600_FLAGS_PCIEGEN2
- ATOM_PPLIB_R600_FLAGS_UVDSAFE
- ATOM_PPLIB_RS780_CLOCK_INFO
- ATOM_PPLIB_RS780_HTLINKFREQ_HIGH
- ATOM_PPLIB_RS780_HTLINKFREQ_LOW
- ATOM_PPLIB_RS780_HTLINKFREQ_NONE
- ATOM_PPLIB_RS780_SPMCLK_HIGH
- ATOM_PPLIB_RS780_SPMCLK_LOW
- ATOM_PPLIB_RS780_SPMCLK_NONE
- ATOM_PPLIB_RS780_VOLTAGE_HIGH
- ATOM_PPLIB_RS780_VOLTAGE_LOW
- ATOM_PPLIB_RS780_VOLTAGE_NONE
- ATOM_PPLIB_RS780_VOLTAGE_VARIABLE
- ATOM_PPLIB_SAMClk_Voltage_Limit_Record
- ATOM_PPLIB_SAMClk_Voltage_Limit_Table
- ATOM_PPLIB_SAMU_Table
- ATOM_PPLIB_SINGLE_DISPLAY_ONLY
- ATOM_PPLIB_SI_CLOCK_INFO
- ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING
- ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS
- ATOM_PPLIB_STATE
- ATOM_PPLIB_STATE_V2
- ATOM_PPLIB_SUMO_CLOCK_INFO
- ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK
- ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF
- ATOM_PPLIB_THERMALCONTROLLER
- ATOM_PPLIB_THERMAL_STATE
- ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
- ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
- ATOM_PPLIB_UVD_Table
- ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
- ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
- ATOM_PPLIB_VCE_State_Record
- ATOM_PPLIB_VCE_State_Table
- ATOM_PPLIB_VCE_Table
- ATOM_PPLIB_VQ_Budgeting_Record
- ATOM_PPLIB_VQ_Budgeting_Table
- ATOM_PPLL0
- ATOM_PPLL1
- ATOM_PPLL2
- ATOM_PPLL3
- ATOM_PPLL_INVALID
- ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK
- ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT
- ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK
- ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT
- ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK
- ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT
- ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK
- ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT
- ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD
- ATOM_PPLL_SS_TYPE_V2_DCPLL
- ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD
- ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD
- ATOM_PPLL_SS_TYPE_V2_P1PLL
- ATOM_PPLL_SS_TYPE_V2_P2PLL
- ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK
- ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD
- ATOM_PPLL_SS_TYPE_V3_DCPLL
- ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD
- ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD
- ATOM_PPLL_SS_TYPE_V3_P0PLL
- ATOM_PPLL_SS_TYPE_V3_P1PLL
- ATOM_PPLL_SS_TYPE_V3_P2PLL
- ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK
- ATOM_PPM_A_A
- ATOM_PPM_A_I
- ATOM_PP_FANPARAMETERS_NOFAN
- ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK
- ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN
- ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64
- ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649
- ATOM_PP_PLATFORM_CAP_ASPM_L0s
- ATOM_PP_PLATFORM_CAP_ASPM_L1
- ATOM_PP_PLATFORM_CAP_BACKBIAS
- ATOM_PP_PLATFORM_CAP_BACO
- ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC
- ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT
- ATOM_PP_PLATFORM_CAP_EVV
- ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY
- ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT
- ATOM_PP_PLATFORM_CAP_HARDWAREDC
- ATOM_PP_PLATFORM_CAP_HTLINKCONTROL
- ATOM_PP_PLATFORM_CAP_MVDDCONTROL
- ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE
- ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17
- ATOM_PP_PLATFORM_CAP_POWERPLAY
- ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
- ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY
- ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE
- ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL
- ATOM_PP_PLATFORM_CAP_STEPVDDC
- ATOM_PP_PLATFORM_CAP_TEMP_INVERSION
- ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1
- ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL
- ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL
- ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE
- ATOM_PP_PLATFORM_CAP_VRHOT_POLARITY_HIGH
- ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL
- ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE
- ATOM_PP_THERMALCONTROLLER_ADM1030
- ATOM_PP_THERMALCONTROLLER_ADM1032
- ATOM_PP_THERMALCONTROLLER_ADT7473
- ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
- ATOM_PP_THERMALCONTROLLER_CISLANDS
- ATOM_PP_THERMALCONTROLLER_EMC2103
- ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
- ATOM_PP_THERMALCONTROLLER_EVERGREEN
- ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
- ATOM_PP_THERMALCONTROLLER_F75375
- ATOM_PP_THERMALCONTROLLER_FIJI
- ATOM_PP_THERMALCONTROLLER_ICELAND
- ATOM_PP_THERMALCONTROLLER_KAVERI
- ATOM_PP_THERMALCONTROLLER_KONG
- ATOM_PP_THERMALCONTROLLER_LM63
- ATOM_PP_THERMALCONTROLLER_LM64
- ATOM_PP_THERMALCONTROLLER_LM96163
- ATOM_PP_THERMALCONTROLLER_MUA6649
- ATOM_PP_THERMALCONTROLLER_NISLANDS
- ATOM_PP_THERMALCONTROLLER_NONE
- ATOM_PP_THERMALCONTROLLER_POLARIS10
- ATOM_PP_THERMALCONTROLLER_RV6xx
- ATOM_PP_THERMALCONTROLLER_RV770
- ATOM_PP_THERMALCONTROLLER_SISLANDS
- ATOM_PP_THERMALCONTROLLER_SUMO
- ATOM_PP_THERMALCONTROLLER_TONGA
- ATOM_PP_THERMALCONTROLLER_VEGA10
- ATOM_PRE_OS_ASSERTION_DEF
- ATOM_PRE_OS_MODE_8BIT_PAL_EN
- ATOM_PRE_OS_MODE_GOP
- ATOM_PRE_OS_MODE_INFO_DEF
- ATOM_PRE_OS_MODE_MASK
- ATOM_PRE_OS_MODE_NUMBER_MASK
- ATOM_PRE_OS_MODE_PIXEL_DEPTH
- ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK
- ATOM_PRE_OS_MODE_VESA
- ATOM_PRE_OS_MODE_VGA
- ATOM_Polaris10_PCIE_Record
- ATOM_Polaris10_PCIE_Table
- ATOM_Polaris_SCLK_Dependency_Record
- ATOM_Polaris_SCLK_Dependency_Table
- ATOM_PowerTune_Table
- ATOM_RECORD_END_TYPE
- ATOM_REFRESH_43
- ATOM_REFRESH_47
- ATOM_REFRESH_56
- ATOM_REFRESH_60
- ATOM_REFRESH_65
- ATOM_REFRESH_70
- ATOM_REFRESH_72
- ATOM_REFRESH_75
- ATOM_REFRESH_85
- ATOM_REG_INIT_SETTING
- ATOM_REQ_INFO_DEVICE_MASK
- ATOM_RGB888_MODE
- ATOM_ROM_CMD_PTR
- ATOM_ROM_DATA_PTR
- ATOM_ROM_HEADER
- ATOM_ROM_HEADER_V2_1
- ATOM_ROM_LOCATION_DEF
- ATOM_ROM_MAGIC
- ATOM_ROM_MAGIC_PTR
- ATOM_ROM_MSG_PTR
- ATOM_ROM_PART_NUMBER_PTR
- ATOM_ROM_TABLE_PTR
- ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
- ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
- ATOM_ROUTER_DDC_PATH_SELECT_RECORD
- ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
- ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT
- ATOM_ROUTER_MUX_PIN_STATE_MASK
- ATOM_S0_CRT1_COLOR
- ATOM_S0_CRT1_COLORb0
- ATOM_S0_CRT1_MASK
- ATOM_S0_CRT1_MASKb0
- ATOM_S0_CRT1_MONO
- ATOM_S0_CRT1_MONOb0
- ATOM_S0_CRT2_COLOR
- ATOM_S0_CRT2_COLORb1
- ATOM_S0_CRT2_MASK
- ATOM_S0_CRT2_MASKb1
- ATOM_S0_CRT2_MONO
- ATOM_S0_CRT2_MONOb1
- ATOM_S0_CV
- ATOM_S0_CV_A
- ATOM_S0_CV_DIN
- ATOM_S0_CV_DIN_A
- ATOM_S0_CV_DINb0
- ATOM_S0_CV_DINb1
- ATOM_S0_CV_MASK
- ATOM_S0_CV_MASK_A
- ATOM_S0_CV_MASKb0
- ATOM_S0_CV_MASKb1
- ATOM_S0_CVb0
- ATOM_S0_CVb1
- ATOM_S0_DFP1
- ATOM_S0_DFP1I
- ATOM_S0_DFP1X
- ATOM_S0_DFP1b2
- ATOM_S0_DFP2
- ATOM_S0_DFP2I
- ATOM_S0_DFP2Ib2
- ATOM_S0_DFP2b2
- ATOM_S0_DFP3
- ATOM_S0_DFP3b2
- ATOM_S0_DFP4
- ATOM_S0_DFP4b2
- ATOM_S0_DFP5
- ATOM_S0_DFP5b2
- ATOM_S0_DFP6
- ATOM_S0_DFP6b2
- ATOM_S0_DFP_MASK
- ATOM_S0_FAD_REGISTER_BUG
- ATOM_S0_LCD1
- ATOM_S0_LCD1_SHIFT
- ATOM_S0_LCD1b2
- ATOM_S0_LCD2
- ATOM_S0_LCD2b2
- ATOM_S0_SYSTEM_POWER_STATE_MASK
- ATOM_S0_SYSTEM_POWER_STATE_MASKb3
- ATOM_S0_SYSTEM_POWER_STATE_SHIFT
- ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC
- ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC
- ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC
- ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC
- ATOM_S0_THERMAL_STATE_MASK
- ATOM_S0_THERMAL_STATE_MASKb3
- ATOM_S0_THERMAL_STATE_SHIFT
- ATOM_S0_THERMAL_STATE_SHIFTb3
- ATOM_S0_TV1_COMPOSITE
- ATOM_S0_TV1_COMPOSITE_A
- ATOM_S0_TV1_COMPOSITEb0
- ATOM_S0_TV1_COMPOSITEb1
- ATOM_S0_TV1_MASK
- ATOM_S0_TV1_MASK_A
- ATOM_S0_TV1_MASKb0
- ATOM_S0_TV1_MASKb1
- ATOM_S0_TV1_SCART
- ATOM_S0_TV1_SCARTb1
- ATOM_S0_TV1_SVIDEO
- ATOM_S0_TV1_SVIDEO_A
- ATOM_S0_TV1_SVIDEOb0
- ATOM_S0_TV1_SVIDEOb1
- ATOM_S0_TV2
- ATOM_S1_PCI_BUS_DEV_MASK
- ATOM_S1_ROM_LOCATION_MASK
- ATOM_S2_CRT1_DPMS_STATE
- ATOM_S2_CRT1_DPMS_STATEb2
- ATOM_S2_CRT2_DPMS_STATE
- ATOM_S2_CRT2_DPMS_STATEb2
- ATOM_S2_CURRENT_BL_LEVEL_MASK
- ATOM_S2_CURRENT_BL_LEVEL_MASKb1
- ATOM_S2_CURRENT_BL_LEVEL_SHIFT
- ATOM_S2_CV_DPMS_STATE
- ATOM_S2_CV_DPMS_STATEb3
- ATOM_S2_DEVICE_DPMS_MASKw1
- ATOM_S2_DEVICE_DPMS_STATE
- ATOM_S2_DEVICE_DPMS_STATEb2
- ATOM_S2_DFP1I_DPMS_STATE
- ATOM_S2_DFP1X_DPMS_STATE
- ATOM_S2_DFP1_DPMS_STATE
- ATOM_S2_DFP1_DPMS_STATEb2
- ATOM_S2_DFP2I_DPMS_STATE
- ATOM_S2_DFP2I_DPMS_STATEb3
- ATOM_S2_DFP2_DPMS_STATE
- ATOM_S2_DFP2_DPMS_STATEb2
- ATOM_S2_DFP3_DPMS_STATE
- ATOM_S2_DFP3_DPMS_STATEb3
- ATOM_S2_DFP4_DPMS_STATE
- ATOM_S2_DFP4_DPMS_STATEb3
- ATOM_S2_DFP5_DPMS_STATE
- ATOM_S2_DFP5_DPMS_STATEb3
- ATOM_S2_DISPLAY_ROTATION_0_DEGREE
- ATOM_S2_DISPLAY_ROTATION_180_DEGREE
- ATOM_S2_DISPLAY_ROTATION_270_DEGREE
- ATOM_S2_DISPLAY_ROTATION_90_DEGREE
- ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK
- ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT
- ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE
- ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3
- ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK
- ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT
- ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3
- ATOM_S2_LCD1_DPMS_STATE
- ATOM_S2_LCD1_DPMS_STATEb2
- ATOM_S2_LCD2_DPMS_STATE
- ATOM_S2_LCD2_DPMS_STATEb2
- ATOM_S2_ROTATION_STATE_MASKb3
- ATOM_S2_TMDS_COHERENT_MODEb3
- ATOM_S2_TV1_DPMS_STATE
- ATOM_S2_TV1_DPMS_STATEb2
- ATOM_S2_TV1_STANDARD_MASK
- ATOM_S2_TV1_STANDARD_MASKb0
- ATOM_S2_TV2_DPMS_STATE
- ATOM_S2_TV2_DPMS_STATEb2
- ATOM_S2_VRI_BRIGHT_ENABLE
- ATOM_S2_VRI_BRIGHT_ENABLEb3
- ATOM_S3_ACTIVE_CRTC1w0
- ATOM_S3_ACTIVE_CRTC2w1
- ATOM_S3_ALLOW_FAST_PWR_SWITCH
- ATOM_S3_ALLOW_FAST_PWR_SWITCHb3
- ATOM_S3_ASIC_GUI_ENGINE_HUNG
- ATOM_S3_ASIC_GUI_ENGINE_HUNGb3
- ATOM_S3_CRT1_ACTIVE
- ATOM_S3_CRT1_ACTIVEb0
- ATOM_S3_CRT1_CRTC_ACTIVE
- ATOM_S3_CRT1_CRTC_ACTIVEb2
- ATOM_S3_CRT2_ACTIVE
- ATOM_S3_CRT2_ACTIVEb0
- ATOM_S3_CRT2_CRTC_ACTIVE
- ATOM_S3_CRT2_CRTC_ACTIVEb2
- ATOM_S3_CV_ACTIVE
- ATOM_S3_CV_ACTIVEb1
- ATOM_S3_CV_CRTC_ACTIVE
- ATOM_S3_CV_CRTC_ACTIVEb3
- ATOM_S3_DEVICE_ACTIVE_MASK
- ATOM_S3_DEVICE_CRTC_ACTIVE_MASK
- ATOM_S3_DFP1I_ACTIVE
- ATOM_S3_DFP1I_CRTC_ACTIVE
- ATOM_S3_DFP1X_ACTIVE
- ATOM_S3_DFP1X_CRTC_ACTIVE
- ATOM_S3_DFP1_ACTIVE
- ATOM_S3_DFP1_ACTIVEb0
- ATOM_S3_DFP1_CRTC_ACTIVE
- ATOM_S3_DFP1_CRTC_ACTIVEb2
- ATOM_S3_DFP2I_ACTIVE
- ATOM_S3_DFP2I_ACTIVEb1
- ATOM_S3_DFP2I_CRTC_ACTIVE
- ATOM_S3_DFP2I_CRTC_ACTIVEb3
- ATOM_S3_DFP2_ACTIVE
- ATOM_S3_DFP2_ACTIVEb0
- ATOM_S3_DFP2_CRTC_ACTIVE
- ATOM_S3_DFP2_CRTC_ACTIVEb2
- ATOM_S3_DFP3_ACTIVE
- ATOM_S3_DFP3_ACTIVEb1
- ATOM_S3_DFP3_CRTC_ACTIVE
- ATOM_S3_DFP3_CRTC_ACTIVEb3
- ATOM_S3_DFP4_ACTIVE
- ATOM_S3_DFP4_ACTIVEb1
- ATOM_S3_DFP4_CRTC_ACTIVE
- ATOM_S3_DFP4_CRTC_ACTIVEb3
- ATOM_S3_DFP5_ACTIVE
- ATOM_S3_DFP5_ACTIVEb1
- ATOM_S3_DFP5_CRTC_ACTIVE
- ATOM_S3_DFP5_CRTC_ACTIVEb3
- ATOM_S3_DFP6_ACTIVE
- ATOM_S3_DFP6_ACTIVEb0
- ATOM_S3_DFP6_CRTC_ACTIVE
- ATOM_S3_DFP6_CRTC_ACTIVEb2
- ATOM_S3_LCD1_ACTIVE
- ATOM_S3_LCD1_ACTIVEb0
- ATOM_S3_LCD1_CRTC_ACTIVE
- ATOM_S3_LCD1_CRTC_ACTIVEb2
- ATOM_S3_LCD2_ACTIVE
- ATOM_S3_LCD2_ACTIVEb0
- ATOM_S3_LCD2_CRTC_ACTIVE
- ATOM_S3_LCD2_CRTC_ACTIVEb2
- ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE
- ATOM_S3_LCD_FULLEXPANSION_ACTIVE
- ATOM_S3_RQST_GPU_USE_MIN_PWR
- ATOM_S3_RQST_GPU_USE_MIN_PWRb3
- ATOM_S3_TV1_ACTIVE
- ATOM_S3_TV1_ACTIVEb0
- ATOM_S3_TV1_CRTC_ACTIVE
- ATOM_S3_TV1_CRTC_ACTIVEb2
- ATOM_S3_TV2_ACTIVE
- ATOM_S3_TV2_CRTC_ACTIVE
- ATOM_S4_LCD1_PANEL_ID_MASK
- ATOM_S4_LCD1_PANEL_ID_MASKb0
- ATOM_S4_LCD1_REFRESH_MASK
- ATOM_S4_LCD1_REFRESH_MASKb1
- ATOM_S4_LCD1_REFRESH_SHIFT
- ATOM_S4_VRAM_INFO_MASKb2
- ATOM_S5_DOS_FORCE_CRT1b2
- ATOM_S5_DOS_FORCE_CRT2b2
- ATOM_S5_DOS_FORCE_CVb3
- ATOM_S5_DOS_FORCE_DEVICEw1
- ATOM_S5_DOS_FORCE_TV1b2
- ATOM_S5_DOS_REQ_CRT1
- ATOM_S5_DOS_REQ_CRT1b0
- ATOM_S5_DOS_REQ_CRT2
- ATOM_S5_DOS_REQ_CRT2b0
- ATOM_S5_DOS_REQ_CV
- ATOM_S5_DOS_REQ_CVb1
- ATOM_S5_DOS_REQ_DEVICEw0
- ATOM_S5_DOS_REQ_DFP1
- ATOM_S5_DOS_REQ_DFP1b0
- ATOM_S5_DOS_REQ_DFP2
- ATOM_S5_DOS_REQ_DFP2I
- ATOM_S5_DOS_REQ_DFP2Ib1
- ATOM_S5_DOS_REQ_DFP2b0
- ATOM_S5_DOS_REQ_DFP3
- ATOM_S5_DOS_REQ_DFP3b1
- ATOM_S5_DOS_REQ_DFP4
- ATOM_S5_DOS_REQ_DFP4b1
- ATOM_S5_DOS_REQ_DFP5
- ATOM_S5_DOS_REQ_DFP5b1
- ATOM_S5_DOS_REQ_DFP6
- ATOM_S5_DOS_REQ_DFP6b0
- ATOM_S5_DOS_REQ_LCD1
- ATOM_S5_DOS_REQ_LCD1b0
- ATOM_S5_DOS_REQ_LCD2
- ATOM_S5_DOS_REQ_LCD2b0
- ATOM_S5_DOS_REQ_TV1
- ATOM_S5_DOS_REQ_TV1b0
- ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
- ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT
- ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3
- ATOM_S6_ACC_MODE
- ATOM_S6_ACC_MODE_SHIFT
- ATOM_S6_ACC_MODEb0
- ATOM_S6_ACC_REQ_CRT1
- ATOM_S6_ACC_REQ_CRT1b2
- ATOM_S6_ACC_REQ_CRT2
- ATOM_S6_ACC_REQ_CRT2b2
- ATOM_S6_ACC_REQ_CV
- ATOM_S6_ACC_REQ_CVb3
- ATOM_S6_ACC_REQ_DEVICEw1
- ATOM_S6_ACC_REQ_DFP1
- ATOM_S6_ACC_REQ_DFP1I
- ATOM_S6_ACC_REQ_DFP1X
- ATOM_S6_ACC_REQ_DFP1b2
- ATOM_S6_ACC_REQ_DFP2
- ATOM_S6_ACC_REQ_DFP2I
- ATOM_S6_ACC_REQ_DFP2Ib3
- ATOM_S6_ACC_REQ_DFP2b2
- ATOM_S6_ACC_REQ_DFP3
- ATOM_S6_ACC_REQ_DFP3b3
- ATOM_S6_ACC_REQ_DFP4
- ATOM_S6_ACC_REQ_DFP4b3
- ATOM_S6_ACC_REQ_DFP5
- ATOM_S6_ACC_REQ_DFP5b3
- ATOM_S6_ACC_REQ_DFP6
- ATOM_S6_ACC_REQ_DFP6b2
- ATOM_S6_ACC_REQ_LCD1
- ATOM_S6_ACC_REQ_LCD1b2
- ATOM_S6_ACC_REQ_LCD2
- ATOM_S6_ACC_REQ_LCD2b2
- ATOM_S6_ACC_REQ_MASK
- ATOM_S6_ACC_REQ_TV1
- ATOM_S6_ACC_REQ_TV1b2
- ATOM_S6_ACC_REQ_TV2
- ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK
- ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT
- ATOM_S6_CONFIG_DISPLAY_CHANGEb3
- ATOM_S6_CRITICAL_STATE
- ATOM_S6_CRITICAL_STATE_SHIFT
- ATOM_S6_CRITICAL_STATEb1
- ATOM_S6_DEVICE_CHANGE
- ATOM_S6_DEVICE_CHANGE_SHIFT
- ATOM_S6_DEVICE_CHANGEb0
- ATOM_S6_DISPLAY_STATE_CHANGE
- ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT
- ATOM_S6_DOCKING_CHANGE
- ATOM_S6_DOCKING_CHANGE_SHIFT
- ATOM_S6_DOCKING_CHANGEb0
- ATOM_S6_DOCK_STATE
- ATOM_S6_DOCK_STATE_SHIFT
- ATOM_S6_DOCK_STATEb0
- ATOM_S6_EXT_DESKTOP_MODE
- ATOM_S6_EXT_DESKTOP_MODE_SHIFT
- ATOM_S6_EXT_DESKTOP_MODEb0
- ATOM_S6_HW_I2C_BUSY_STATE
- ATOM_S6_HW_I2C_BUSY_STATE_SHIFT
- ATOM_S6_HW_I2C_BUSY_STATEb1
- ATOM_S6_I2C_STATE_CHANGE
- ATOM_S6_I2C_STATE_CHANGE_SHIFT
- ATOM_S6_INTERRUPT_SET_BY_BIOS
- ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT
- ATOM_S6_INTERRUPT_SET_BY_BIOSb1
- ATOM_S6_LID_CHANGE
- ATOM_S6_LID_CHANGE_SHIFT
- ATOM_S6_LID_CHANGEb0
- ATOM_S6_LID_STATE
- ATOM_S6_LID_STATE_SHIFT
- ATOM_S6_LID_STATEb0
- ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO
- ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1
- ATOM_S6_REQ_LCD_EXPANSION_FULL
- ATOM_S6_REQ_LCD_EXPANSION_FULLb1
- ATOM_S6_REQ_SCALER_ARATIO_SHIFT
- ATOM_S6_REQ_SCALER_SHIFT
- ATOM_S6_SCALER_CHANGE
- ATOM_S6_SCALER_CHANGE_SHIFT
- ATOM_S6_SCALER_CHANGEb0
- ATOM_S6_SYSTEM_POWER_MODE_CHANGE
- ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT
- ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3
- ATOM_S6_THERMAL_STATE_CHANGE
- ATOM_S6_THERMAL_STATE_CHANGE_SHIFT
- ATOM_S6_THERMAL_STATE_CHANGEb1
- ATOM_S6_VRI_BRIGHTNESS_CHANGE
- ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT
- ATOM_S6_VRI_BRIGHTNESS_CHANGEb3
- ATOM_S7_ASIC_INIT_COMPLETE_MASK
- ATOM_S7_ASIC_INIT_COMPLETEb1
- ATOM_S7_DOS_8BIT_DAC_EN_SHIFT
- ATOM_S7_DOS_8BIT_DAC_ENb1
- ATOM_S7_DOS_MODE_EXTb0
- ATOM_S7_DOS_MODE_NUMBERw1
- ATOM_S7_DOS_MODE_PIXEL_DEPTHb0
- ATOM_S7_DOS_MODE_PIXEL_FORMATb0
- ATOM_S7_DOS_MODE_TYPEb0
- ATOM_S7_DOS_MODE_VESAb0
- ATOM_S7_DOS_MODE_VGAb0
- ATOM_S8_I2C_CHANNEL_BUSY_MASK
- ATOM_S8_I2C_CHANNEL_BUSY_SHIFT
- ATOM_S8_I2C_ENGINE_BUSY_SHIFT
- ATOM_S8_I2C_HW_ENGINE_BUSY_MASK
- ATOM_S9_I2C_CHANNEL_ABORTED_MASK
- ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
- ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
- ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
- ATOM_SCALER1
- ATOM_SCALER2
- ATOM_SCALER_CENTER
- ATOM_SCALER_DISABLE
- ATOM_SCALER_EXPANSION
- ATOM_SCALER_MULTI_EX
- ATOM_SCLK_FCW_RANGE_ENTRY_V1
- ATOM_SERVICE_DESCRIPTION
- ATOM_SERVICE_INFO
- ATOM_SET_VOLTAGE
- ATOM_SET_VOLTAGE_PHASE
- ATOM_SMU_INFO_V2_1
- ATOM_SPREAD_SPECTRUM_ASSIGNMENT
- ATOM_SPREAD_SPECTRUM_INFO
- ATOM_SRC_BYTE0
- ATOM_SRC_BYTE16
- ATOM_SRC_BYTE24
- ATOM_SRC_BYTE8
- ATOM_SRC_DAC1
- ATOM_SRC_DAC2
- ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
- ATOM_SRC_DWORD
- ATOM_SRC_WORD0
- ATOM_SRC_WORD16
- ATOM_SRC_WORD8
- ATOM_SS_CENTER_OR_DOWN_MODE_MASK
- ATOM_SS_CENTRE_SPREAD_MODE
- ATOM_SS_CENTRE_SPREAD_MODE_MASK
- ATOM_SS_DOWN_SPREAD_MODE
- ATOM_SS_DOWN_SPREAD_MODE_MASK
- ATOM_STACK_STORAGE_END
- ATOM_STACK_STORAGE_START
- ATOM_STANDARD_VESA_TIMING
- ATOM_STD_FORMAT
- ATOM_STD_MODE_SUPPORT_TBL_SIZE
- ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE
- ATOM_SUB_FUNCTION_GET_CRITICAL_STATE
- ATOM_SUB_FUNCTION_GET_DPMS
- ATOM_SUB_FUNCTION_GET_LIDSTATE
- ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE
- ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT
- ATOM_SUB_FUNCTION_SET_DPMS
- ATOM_SUB_FUNCTION_SET_LIDSTATE
- ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE
- ATOM_SUPPORTED_DEVICES_INFO
- ATOM_SUPPORTED_DEVICES_INFO_2
- ATOM_SUPPORTED_DEVICES_INFO_2d1
- ATOM_SUPPORTED_DEVICES_INFO_LAST
- ATOM_SVID2_VOLTAGE_OBJECT_V3
- ATOM_S_MPLL_FB_DIVIDER
- ATOM_TABLE_ATTRIBUTE
- ATOM_TABLE_ATTRIBUTE_ACCESS
- ATOM_TABLE_NAMES_CNT
- ATOM_TDP_CONFIG
- ATOM_TDP_CONFIG_BITS
- ATOM_TMDS_INFO
- ATOM_TONGA_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE
- ATOM_TONGA_PP_FANPARAMETERS_NOFAN
- ATOM_TONGA_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK
- ATOM_TONGA_PP_PLATFORM_CAP_BACO
- ATOM_TONGA_PP_PLATFORM_CAP_DISABLE_VOLTAGE_ISLAND
- ATOM_TONGA_PP_PLATFORM_CAP_HARDWAREDC
- ATOM_TONGA_PP_PLATFORM_CAP_MVDD_CONTROL
- ATOM_TONGA_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17
- ATOM_TONGA_PP_PLATFORM_CAP_POWERPLAY
- ATOM_TONGA_PP_PLATFORM_CAP_SBIOSPOWERSOURCE
- ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL
- ATOM_TONGA_PP_PLATFORM_CAP_VDDGFX_CONTROL
- ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL
- ATOM_TONGA_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
- ATOM_TONGA_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
- ATOM_TONGA_PP_THERMALCONTROLLER_FIJI
- ATOM_TONGA_PP_THERMALCONTROLLER_LM96163
- ATOM_TONGA_PP_THERMALCONTROLLER_NONE
- ATOM_TONGA_PP_THERMALCONTROLLER_TONGA
- ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK
- ATOM_TRANMSITTER_V5__DIGA_SEL
- ATOM_TRANMSITTER_V5__DIGB_SEL
- ATOM_TRANMSITTER_V5__DIGC_SEL
- ATOM_TRANMSITTER_V5__DIGD_SEL
- ATOM_TRANMSITTER_V5__DIGE_SEL
- ATOM_TRANMSITTER_V5__DIGF_SEL
- ATOM_TRANMSITTER_V5__DIGG_SEL
- ATOM_TRANMSITTER_V6__DIGA_SEL
- ATOM_TRANMSITTER_V6__DIGB_SEL
- ATOM_TRANMSITTER_V6__DIGC_SEL
- ATOM_TRANMSITTER_V6__DIGD_SEL
- ATOM_TRANMSITTER_V6__DIGE_SEL
- ATOM_TRANMSITTER_V6__DIGF_SEL
- ATOM_TRANMSITTER_V6__DIGG_SEL
- ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
- ATOM_TRANSMITTER_ACTION_DISABLE
- ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
- ATOM_TRANSMITTER_ACTION_ENABLE
- ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
- ATOM_TRANSMITTER_ACTION_INIT
- ATOM_TRANSMITTER_ACTION_LCD_BLOFF
- ATOM_TRANSMITTER_ACTION_LCD_BLON
- ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START
- ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP
- ATOM_TRANSMITTER_ACTION_POWER_OFF
- ATOM_TRANSMITTER_ACTION_POWER_ON
- ATOM_TRANSMITTER_ACTION_SETUP
- ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
- ATOM_TRANSMITTER_CONFIG_8LANE_LINK
- ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK
- ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE
- ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
- ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN
- ATOM_TRANSMITTER_CONFIG_COHERENT
- ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
- ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
- ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_LANE_0_3
- ATOM_TRANSMITTER_CONFIG_LANE_0_7
- ATOM_TRANSMITTER_CONFIG_LANE_12_15
- ATOM_TRANSMITTER_CONFIG_LANE_4_7
- ATOM_TRANSMITTER_CONFIG_LANE_8_11
- ATOM_TRANSMITTER_CONFIG_LANE_8_15
- ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_LINKA
- ATOM_TRANSMITTER_CONFIG_LINKA_B
- ATOM_TRANSMITTER_CONFIG_LINKB
- ATOM_TRANSMITTER_CONFIG_LINKB_A
- ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V2_COHERENT
- ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER
- ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER
- ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR
- ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V2_LINKA
- ATOM_TRANSMITTER_CONFIG_V2_LINKB
- ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1
- ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2
- ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3
- ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V3_COHERENT
- ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER
- ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER
- ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR
- ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V3_LINKA
- ATOM_TRANSMITTER_CONFIG_V3_LINKB
- ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1
- ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2
- ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3
- ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V4_COHERENT
- ATOM_TRANSMITTER_CONFIG_V4_DCPLL
- ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER
- ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER
- ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR
- ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V4_LINKA
- ATOM_TRANSMITTER_CONFIG_V4_LINKB
- ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V4_P1PLL
- ATOM_TRANSMITTER_CONFIG_V4_P2PLL
- ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT
- ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1
- ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2
- ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3
- ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V5_COHERENT
- ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL
- ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT
- ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL
- ATOM_TRANSMITTER_CONFIG_V5_P0PLL
- ATOM_TRANSMITTER_CONFIG_V5_P1PLL
- ATOM_TRANSMITTER_CONFIG_V5_P2PLL
- ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK
- ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT
- ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT
- ATOM_TRANSMITTER_DIGMODE_V5_DP
- ATOM_TRANSMITTER_DIGMODE_V5_DP_MST
- ATOM_TRANSMITTER_DIGMODE_V5_DVI
- ATOM_TRANSMITTER_DIGMODE_V5_HDMI
- ATOM_TRANSMITTER_DIGMODE_V5_LVDS
- ATOM_TRANSMITTER_DIGMODE_V5_SDVO
- ATOM_TRANSMITTER_DIGMODE_V6_DP
- ATOM_TRANSMITTER_DIGMODE_V6_DP_MST
- ATOM_TRANSMITTER_DIGMODE_V6_DVI
- ATOM_TRANSMITTER_DIGMODE_V6_HDMI
- ATOM_TRANSMITTER_V6_HPD1_SEL
- ATOM_TRANSMITTER_V6_HPD2_SEL
- ATOM_TRANSMITTER_V6_HPD3_SEL
- ATOM_TRANSMITTER_V6_HPD4_SEL
- ATOM_TRANSMITTER_V6_HPD5_SEL
- ATOM_TRANSMITTER_V6_HPD6_SEL
- ATOM_TRANSMITTER_V6_NO_HPD_SEL
- ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR
- ATOM_TRASMITTER_CONFIG_V3_P1PLL
- ATOM_TRASMITTER_CONFIG_V3_P2PLL
- ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK
- ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT
- ATOM_TV1_DTD_MODE_TBL_ADDR
- ATOM_TV_CV
- ATOM_TV_EXT_ENCODER1_INDEX
- ATOM_TV_INT_ENCODER1_INDEX
- ATOM_TV_MODE
- ATOM_TV_MODE_SCALER_PTR
- ATOM_TV_NTSC
- ATOM_TV_NTSCJ
- ATOM_TV_PAL
- ATOM_TV_PAL60
- ATOM_TV_PALCN
- ATOM_TV_PALM
- ATOM_TV_PALN
- ATOM_TV_SECAM
- ATOM_TV_STANDARD_DEF
- ATOM_TYPES_H
- ATOM_Tonga_DISALLOW_ON_DC
- ATOM_Tonga_ENABLE_VARIBRIGHT
- ATOM_Tonga_Fan_Table
- ATOM_Tonga_GPIO_Table
- ATOM_Tonga_Hard_Limit_Record
- ATOM_Tonga_Hard_Limit_Table
- ATOM_Tonga_MCLK_Dependency_Record
- ATOM_Tonga_MCLK_Dependency_Table
- ATOM_Tonga_MM_Dependency_Record
- ATOM_Tonga_MM_Dependency_Table
- ATOM_Tonga_PCIE_Record
- ATOM_Tonga_PCIE_Table
- ATOM_Tonga_POWERPLAYTABLE
- ATOM_Tonga_PPM_Table
- ATOM_Tonga_PowerTune_Table
- ATOM_Tonga_SCLK_Dependency_Record
- ATOM_Tonga_SCLK_Dependency_Table
- ATOM_Tonga_State
- ATOM_Tonga_State_Array
- ATOM_Tonga_TABLE_REVISION_TONGA
- ATOM_Tonga_Thermal_Controller
- ATOM_Tonga_VCE_State_Record
- ATOM_Tonga_VCE_State_Table
- ATOM_Tonga_Voltage_Lookup_Record
- ATOM_Tonga_Voltage_Lookup_Table
- ATOM_UNDERLAY_PIPE0
- ATOM_UNDERLAY_PIPE1
- ATOM_UNIT_MICROSEC
- ATOM_UNIT_MILLISEC
- ATOM_UNKNOWN_CMD
- ATOM_VEGA10_PP_FANPARAMETERS_NOFAN
- ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK
- ATOM_VEGA10_PP_PLATFORM_CAP_BACO
- ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC
- ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY
- ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE
- ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL
- ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
- ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
- ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163
- ATOM_VEGA10_PP_THERMALCONTROLLER_NONE
- ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10
- ATOM_VEGA12_ODSETTING_COUNT
- ATOM_VEGA12_ODSETTING_FANRPMACOUSTICLIMIT
- ATOM_VEGA12_ODSETTING_FANRPMMIN
- ATOM_VEGA12_ODSETTING_FANTARGETTEMPERATURE
- ATOM_VEGA12_ODSETTING_GFXCLKFMAX
- ATOM_VEGA12_ODSETTING_GFXCLKFMIN
- ATOM_VEGA12_ODSETTING_ID
- ATOM_VEGA12_ODSETTING_OPERATINGTEMPMAX
- ATOM_VEGA12_ODSETTING_POWERPERCENTAGE
- ATOM_VEGA12_ODSETTING_UCLKFMAX
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P1
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P2
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEFREQ_P3
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2
- ATOM_VEGA12_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3
- ATOM_VEGA12_PPCLOCK_COUNT
- ATOM_VEGA12_PPCLOCK_DCEFCLK
- ATOM_VEGA12_PPCLOCK_DCLK
- ATOM_VEGA12_PPCLOCK_DISPCLK
- ATOM_VEGA12_PPCLOCK_ECLK
- ATOM_VEGA12_PPCLOCK_GFXCLK
- ATOM_VEGA12_PPCLOCK_ID
- ATOM_VEGA12_PPCLOCK_PHYCLK
- ATOM_VEGA12_PPCLOCK_PIXCLK
- ATOM_VEGA12_PPCLOCK_SOCCLK
- ATOM_VEGA12_PPCLOCK_UCLK
- ATOM_VEGA12_PPCLOCK_VCLK
- ATOM_VEGA12_PP_PLATFORM_CAP_BACO
- ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO
- ATOM_VEGA12_PP_PLATFORM_CAP_ENABLESHADOWPSTATE
- ATOM_VEGA12_PP_PLATFORM_CAP_HARDWAREDC
- ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY
- ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE
- ATOM_VEGA12_PP_THERMALCONTROLLER_NONE
- ATOM_VEGA12_PP_THERMALCONTROLLER_VEGA12
- ATOM_VEGA12_TABLE_REVISION_VEGA12
- ATOM_VEGA20_ODFEATURE_COUNT
- ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT
- ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN
- ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL
- ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE
- ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS
- ATOM_VEGA20_ODFEATURE_ID
- ATOM_VEGA20_ODFEATURE_MAX_COUNT
- ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE
- ATOM_VEGA20_ODFEATURE_POWER_LIMIT
- ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN
- ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM
- ATOM_VEGA20_ODFEATURE_UCLK_MAX
- ATOM_VEGA20_ODSETTING_COUNT
- ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT
- ATOM_VEGA20_ODSETTING_FANRPMMIN
- ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE
- ATOM_VEGA20_ODSETTING_GFXCLKFMAX
- ATOM_VEGA20_ODSETTING_GFXCLKFMIN
- ATOM_VEGA20_ODSETTING_ID
- ATOM_VEGA20_ODSETTING_MAX_COUNT
- ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX
- ATOM_VEGA20_ODSETTING_POWERPERCENTAGE
- ATOM_VEGA20_ODSETTING_UCLKFMAX
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2
- ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3
- ATOM_VEGA20_OVERDRIVE8_RECORD
- ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD
- ATOM_VEGA20_PPCLOCK_COUNT
- ATOM_VEGA20_PPCLOCK_DCEFCLK
- ATOM_VEGA20_PPCLOCK_DCLK
- ATOM_VEGA20_PPCLOCK_DISPCLK
- ATOM_VEGA20_PPCLOCK_ECLK
- ATOM_VEGA20_PPCLOCK_FCLK
- ATOM_VEGA20_PPCLOCK_GFXCLK
- ATOM_VEGA20_PPCLOCK_ID
- ATOM_VEGA20_PPCLOCK_MAX_COUNT
- ATOM_VEGA20_PPCLOCK_PHYCLK
- ATOM_VEGA20_PPCLOCK_PIXCLK
- ATOM_VEGA20_PPCLOCK_SOCCLK
- ATOM_VEGA20_PPCLOCK_UCLK
- ATOM_VEGA20_PPCLOCK_VCLK
- ATOM_VEGA20_PP_PLATFORM_CAP_BACO
- ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO
- ATOM_VEGA20_PP_PLATFORM_CAP_ENABLESHADOWPSTATE
- ATOM_VEGA20_PP_PLATFORM_CAP_HARDWAREDC
- ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY
- ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE
- ATOM_VEGA20_PP_THERMALCONTROLLER_NONE
- ATOM_VEGA20_PP_THERMALCONTROLLER_VEGA20
- ATOM_VEGA20_TABLE_REVISION_VEGA20
- ATOM_VERSION_MAJOR
- ATOM_VERSION_MINOR
- ATOM_VESA_TO_EXTENDED_MODE
- ATOM_VESA_TO_INTENAL_MODE_LUT
- ATOM_VIRTUAL_VOLTAGE_ID0
- ATOM_VIRTUAL_VOLTAGE_ID1
- ATOM_VIRTUAL_VOLTAGE_ID2
- ATOM_VIRTUAL_VOLTAGE_ID3
- ATOM_VIRTUAL_VOLTAGE_ID4
- ATOM_VIRTUAL_VOLTAGE_ID5
- ATOM_VIRTUAL_VOLTAGE_ID6
- ATOM_VIRTUAL_VOLTAGE_ID7
- ATOM_VOLTAGE_CONTROL
- ATOM_VOLTAGE_FORMULA
- ATOM_VOLTAGE_FORMULA_V2
- ATOM_VOLTAGE_INFO
- ATOM_VOLTAGE_INFO_HEADER
- ATOM_VOLTAGE_OBJECT
- ATOM_VOLTAGE_OBJECT_HEADER_V3
- ATOM_VOLTAGE_OBJECT_INFO
- ATOM_VOLTAGE_OBJECT_INFO_V2
- ATOM_VOLTAGE_OBJECT_INFO_V3_1
- ATOM_VOLTAGE_OBJECT_V2
- ATOM_VOLTAGE_OBJECT_V3
- ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION
- ATOM_VRAM_BLOCK_NEEDS_RESERVATION
- ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION
- ATOM_VRAM_GPIO_DETECTION_INFO
- ATOM_VRAM_INFO_HEADER_V2_1
- ATOM_VRAM_INFO_HEADER_V2_2
- ATOM_VRAM_INFO_LAST
- ATOM_VRAM_INFO_V2
- ATOM_VRAM_INFO_V3
- ATOM_VRAM_INFO_V4
- ATOM_VRAM_MODULE
- ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK
- ATOM_VRAM_MODULE_V1
- ATOM_VRAM_MODULE_V2
- ATOM_VRAM_MODULE_V3
- ATOM_VRAM_MODULE_V4
- ATOM_VRAM_MODULE_V5
- ATOM_VRAM_MODULE_V6
- ATOM_VRAM_MODULE_V7
- ATOM_VRAM_MODULE_V8
- ATOM_VRAM_OPERATION_FLAGS_MASK
- ATOM_VRAM_OPERATION_FLAGS_SHIFT
- ATOM_VRAM_RESERVE_SIZE
- ATOM_VRAM_RESERVE_V2_SIZE
- ATOM_VRAM_USAGE_BY_FIRMWARE
- ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
- ATOM_VSYNC_POLARITY
- ATOM_V_CUTOFF
- ATOM_V_REPLICATIONBY2
- ATOM_Vega10_CLK_Dependency_Record
- ATOM_Vega10_DCEFCLK_Dependency_Table
- ATOM_Vega10_DISALLOW_ON_DC
- ATOM_Vega10_DISPCLK_Dependency_Table
- ATOM_Vega10_ENABLE_VARIBRIGHT
- ATOM_Vega10_Fan_Table
- ATOM_Vega10_Fan_Table_V2
- ATOM_Vega10_Fan_Table_V3
- ATOM_Vega10_GFXCLK_Dependency_Record
- ATOM_Vega10_GFXCLK_Dependency_Record_V2
- ATOM_Vega10_GFXCLK_Dependency_Table
- ATOM_Vega10_Hard_Limit_Record
- ATOM_Vega10_Hard_Limit_Table
- ATOM_Vega10_MCLK_Dependency_Record
- ATOM_Vega10_MCLK_Dependency_Table
- ATOM_Vega10_MM_Dependency_Record
- ATOM_Vega10_MM_Dependency_Table
- ATOM_Vega10_PCIE_Record
- ATOM_Vega10_PCIE_Table
- ATOM_Vega10_PHYCLK_Dependency_Table
- ATOM_Vega10_PIXCLK_Dependency_Table
- ATOM_Vega10_POWERPLAYTABLE
- ATOM_Vega10_PowerTune_Table
- ATOM_Vega10_PowerTune_Table_V2
- ATOM_Vega10_PowerTune_Table_V3
- ATOM_Vega10_SOCCLK_Dependency_Table
- ATOM_Vega10_State
- ATOM_Vega10_State_Array
- ATOM_Vega10_TABLE_REVISION_VEGA10
- ATOM_Vega10_Thermal_Controller
- ATOM_Vega10_VCE_State_Record
- ATOM_Vega10_VCE_State_Table
- ATOM_Vega10_VoltageMode_AVFS_Interpolate
- ATOM_Vega10_VoltageMode_AVFS_WorstCase
- ATOM_Vega10_VoltageMode_Static
- ATOM_Vega10_Voltage_Lookup_Record
- ATOM_Vega10_Voltage_Lookup_Table
- ATOM_Vega12_POWERPLAYTABLE
- ATOM_Vega20_POWERPLAYTABLE
- ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK
- ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK
- ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK
- ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE
- ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES
- ATOM_WS_AND_MASK
- ATOM_WS_ATTRIBUTES
- ATOM_WS_DATAPTR
- ATOM_WS_FB_WINDOW
- ATOM_WS_OR_MASK
- ATOM_WS_QUOTIENT
- ATOM_WS_REGPTR
- ATOM_WS_REMAINDER
- ATOM_WS_SHIFT
- ATOM_XTMDS_ASIC_SI164_ID
- ATOM_XTMDS_ASIC_SI178_ID
- ATOM_XTMDS_ASIC_TFP513_ID
- ATOM_XTMDS_INFO
- ATOM_XTMDS_MVPU_FPGA
- ATOM_XTMDS_SUPPORTED_DUALLINK
- ATOM_XTMDS_SUPPORTED_SINGLELINK
- ATOPIC64_OPS
- ATP867X_BAR_IOBASE
- ATP867X_BAR_ROMBASE
- ATP867X_IOBASE
- ATP867X_IO_8BPIOSPD
- ATP867X_IO_ALTSTATUS
- ATP867X_IO_CHANNEL_OFFSET
- ATP867X_IO_DMABASE
- ATP867X_IO_DMAMODE
- ATP867X_IO_DMAMODE_DISABLE
- ATP867X_IO_DMAMODE_MSTR_MASK
- ATP867X_IO_DMAMODE_MSTR_SHIFT
- ATP867X_IO_DMAMODE_SLAVE_MASK
- ATP867X_IO_DMAMODE_SLAVE_SHIFT
- ATP867X_IO_DMAMODE_UDMA_0
- ATP867X_IO_DMAMODE_UDMA_1
- ATP867X_IO_DMAMODE_UDMA_2
- ATP867X_IO_DMAMODE_UDMA_3
- ATP867X_IO_DMAMODE_UDMA_4
- ATP867X_IO_DMAMODE_UDMA_5
- ATP867X_IO_DMAMODE_UDMA_6
- ATP867X_IO_MSTRPIOSPD
- ATP867X_IO_PIOSPD_ACTIVE_SHIFT
- ATP867X_IO_PIOSPD_RECOVER_SHIFT
- ATP867X_IO_PORTBASE
- ATP867X_IO_PORTSPD
- ATP867X_IO_PORTSPD_VAL
- ATP867X_IO_PREREAD
- ATP867X_IO_SLAVPIOSPD
- ATP867X_IO_STATUS
- ATP867X_IO_SYS_INFO_66MHZ
- ATP867X_IO_SYS_INFO_SLOW_UDMA5
- ATP867X_IO_SYS_MASK_RESERVED
- ATP867X_NUM_PORTS
- ATP867X_PREREAD_VAL
- ATP867X_SYS_INFO
- ATP870U_MAX_SECTORS
- ATP870U_SCATTER
- ATP880_DEVID1
- ATP880_DEVID2
- ATP885_DEVID
- ATPORT_FIRST
- ATPORT_LAST
- ATPORT_RESERVED
- ATPX_ACF_NOT_SUPPORTED
- ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS
- ATPX_CRT1_RGB_SIGNAL_MUXED
- ATPX_DDC1
- ATPX_DDC2
- ATPX_DDC3
- ATPX_DDC4
- ATPX_DDC5
- ATPX_DDC6
- ATPX_DDC7
- ATPX_DDC8
- ATPX_DDC_NONE
- ATPX_DFP_SIGNAL_MUXED
- ATPX_DGPU_CAN_DRIVE_DISPLAYS
- ATPX_DGPU_REQ_POWER_FOR_DISPLAYS
- ATPX_DISCRETE_GPU
- ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE
- ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE
- ATPX_DISPLAY_MUX_CONTROL_SUPPORTED
- ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE
- ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS
- ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED
- ATPX_DYNAMIC_PX_SUPPORTED
- ATPX_FIXED_NOT_SUPPORTED
- ATPX_FUNCTION_DISPLAY_MUX_CONTROL
- ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING
- ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS
- ATPX_FUNCTION_GET_PX_PARAMETERS
- ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION
- ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION
- ATPX_FUNCTION_I2C_MUX_CONTROL
- ATPX_FUNCTION_POWER_CONTROL
- ATPX_FUNCTION_VERIFY_INTERFACE
- ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED
- ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED
- ATPX_GET_PX_PARAMETERS_SUPPORTED
- ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED
- ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED
- ATPX_HPD1
- ATPX_HPD2
- ATPX_HPD3
- ATPX_HPD4
- ATPX_HPD5
- ATPX_HPD6
- ATPX_HPD_NONE
- ATPX_I2C_MUX_CONTROL_SUPPORTED
- ATPX_INTEGRATED_GPU
- ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS
- ATPX_MS_HYBRID_GFX_SUPPORTED
- ATPX_POWER_CONTROL_SUPPORTED
- ATPX_SEPARATE_MUX_FOR_I2C
- ATPX_TV_SIGNAL_MUXED
- ATP_DEVICE
- ATP_GEYSER_MODE_READ_REQUEST_ID
- ATP_GEYSER_MODE_REQUEST_INDEX
- ATP_GEYSER_MODE_REQUEST_VALUE
- ATP_GEYSER_MODE_VENDOR_VALUE
- ATP_GEYSER_MODE_WRITE_REQUEST_ID
- ATP_PRESSURE
- ATP_SCALE
- ATP_SMOOTHSIZE
- ATP_STATUS_BASE_UPDATE
- ATP_STATUS_BUTTON
- ATP_STATUS_FROM_RESET
- ATP_THRESHOLD
- ATP_URB_STATUS_ERROR
- ATP_URB_STATUS_ERROR_FATAL
- ATP_URB_STATUS_SUCCESS
- ATP_XSENSORS
- ATP_YSENSORS
- ATRAP
- ATRDY_TIMEOUT
- ATREPM
- ATRLENCK
- ATRM_BIOS_PAGE
- ATRR0
- ATRR1
- ATRR2
- ATR_REQ_GB_OFFSET
- ATS1CPR
- ATSC
- ATSCMH_RSCODE_211_187
- ATSCMH_RSCODE_223_187
- ATSCMH_RSCODE_235_187
- ATSCMH_RSCODE_RES
- ATSCMH_RSFRAME_ENS_PRI
- ATSCMH_RSFRAME_ENS_SEC
- ATSCMH_RSFRAME_PRI_ONLY
- ATSCMH_RSFRAME_PRI_SEC
- ATSCMH_RSFRAME_RES
- ATSCMH_SCCC_BLK_COMB
- ATSCMH_SCCC_BLK_RES
- ATSCMH_SCCC_BLK_SEP
- ATSCMH_SCCC_CODE_HLF
- ATSCMH_SCCC_CODE_QTR
- ATSCMH_SCCC_CODE_RES
- ATSC_QAM
- ATSC_VSB
- ATSIDL_S
- ATSIDU_S
- ATSR_ACTIVE
- ATS_ACCESS_MODE_ALWAYS
- ATS_ACCESS_MODE_NEVER
- ATS_GET_FLAGS
- ATS_IH_CREDIT__CREDIT_VALUE_MASK
- ATS_IH_CREDIT__CREDIT_VALUE__SHIFT
- ATS_IH_CREDIT__IH_CLIENT_ID_MASK
- ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT
- ATS_SET_FLAGS
- ATS_TYPE_DATA
- ATS_TYPE_FLAT_RD
- ATS_TYPE_FLAT_RDWR
- ATS_TYPE_SGL_RD
- ATS_TYPE_SGL_RDWR
- ATTACHED
- ATTACHED_FMT
- ATTACH_ALL_REQ
- ATTACH_MCAST
- ATTACH_OKAY
- ATTACH_REJECT
- ATTACK_DECAY
- ATTACK_TIME_UNIT
- ATTCH
- ATTCHE
- ATTEMPTS
- ATTEMPT_TUNE
- ATTENTION_BB
- ATTENTION_BB_DIFFERENT
- ATTENTION_BB_MASK
- ATTENTION_BB_SHIFT
- ATTENTION_FORMAT_CUIR
- ATTENTION_FORMAT_OOS
- ATTENTION_ID
- ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK
- ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT
- ATTENTION_INCORRECT_ACCESS_CLIENT_MASK
- ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT
- ATTENTION_INCORRECT_ACCESS_PF_ID_MASK
- ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT
- ATTENTION_INCORRECT_ACCESS_VF_ID_MASK
- ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT
- ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK
- ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT
- ATTENTION_INCORRECT_ACCESS_WR_MASK
- ATTENTION_INCORRECT_ACCESS_WR_SHIFT
- ATTENTION_LENGTH
- ATTENTION_LENGTH_CUIR
- ATTENTION_LENGTH_MASK
- ATTENTION_LENGTH_OOS
- ATTENTION_LENGTH_SHIFT
- ATTENTION_OFFSET_MASK
- ATTENTION_OFFSET_SHIFT
- ATTENTION_PAR
- ATTENTION_PARITY
- ATTENTION_PAR_INT
- ATTENTION_SINGLE
- ATTGAIN_CTL_MASK
- ATTGAIN_CTL_MASK_SFT
- ATTGAIN_CTL_SFT
- ATTN
- ATTN_ABORT
- ATTN_BITS_MASKABLE
- ATTN_BUTTN
- ATTN_BUTTON
- ATTN_GENERAL_ATTN_1
- ATTN_GENERAL_ATTN_2
- ATTN_GENERAL_ATTN_3
- ATTN_GENERAL_ATTN_4
- ATTN_GENERAL_ATTN_5
- ATTN_GENERAL_ATTN_6
- ATTN_HARD_WIRED_MASK
- ATTN_IMMED
- ATTN_LED
- ATTN_NIG_FOR_FUNC
- ATTN_START
- ATTN_STATE_BITS
- ATTN_SW_TIMER_4_FUNC
- ATTN_TYPE_INTERRUPT
- ATTN_TYPE_PARITY
- ATTODeviceInfo_t
- ATTOFLAG_DISC
- ATTOFLAG_ID_ENB
- ATTOFLAG_LUN_ENB
- ATTOFLAG_TAGGED
- ATTOFLAG_WIDE_ENB
- ATTONODE_NAME
- ATTO_AC_AF_GET_STATE
- ATTO_AC_AF_GET_TEMP
- ATTO_AC_AF_HARD_RST
- ATTO_AC_AS_DEGRADED
- ATTO_AC_AS_DISABLED
- ATTO_AC_AS_OK
- ATTO_AC_AS_RST_DISC
- ATTO_AC_AS_RST_IN_PROG
- ATTO_AC_AS_RST_SCHED
- ATTO_AC_AS_TEMP
- ATTO_AC_AS_UNKNOWN
- ATTO_AC_TS_FAULT
- ATTO_AC_TS_INIT_FAILED
- ATTO_AC_TS_NORMAL
- ATTO_AC_TS_OUT_OF_RANGE
- ATTO_AC_TS_UNKNOWN
- ATTO_AC_TS_UNSUPP
- ATTO_DEVICE_INFO
- ATTO_DID_INTEL_IOP348
- ATTO_DID_MV_88RC9580
- ATTO_DID_MV_88RC9580TL
- ATTO_DID_MV_88RC9580TS
- ATTO_DID_MV_88RC9580TSE
- ATTO_ESAS_R608
- ATTO_ESAS_R60F
- ATTO_ESAS_R644
- ATTO_ESAS_R648
- ATTO_ESAS_R680
- ATTO_ESAS_R6F0
- ATTO_FUNC_ADAP_CTRL
- ATTO_FUNC_CONN_CTRL
- ATTO_FUNC_GET_ADAP_ADDR
- ATTO_FUNC_GET_ADAP_INFO
- ATTO_FUNC_GET_DEV_ADDR
- ATTO_FUNC_GET_DEV_INFO
- ATTO_FUNC_MEM_RW
- ATTO_FUNC_PHY_CTRL
- ATTO_FUNC_SCSI_PASS_THRU
- ATTO_FUNC_TRACE
- ATTO_GAA_AT_CURR_MAC
- ATTO_GAA_AT_NODE
- ATTO_GAA_AT_PERM_MAC
- ATTO_GAA_AT_PORT
- ATTO_GAA_AT_VNIC
- ATTO_GAI_AF2_ADAP_CTRL_SUPP
- ATTO_GAI_AF2_DEV_INFO_SUPP
- ATTO_GAI_AF2_FCOE_SUPP
- ATTO_GAI_AF2_LOCATE_SUPP
- ATTO_GAI_AF2_MP_SUPP
- ATTO_GAI_AF2_NIC_SUPP
- ATTO_GAI_AF2_NPIV_SUPP
- ATTO_GAI_AF_CONN_CTRL
- ATTO_GAI_AF_DEGRADED
- ATTO_GAI_AF_DEVADDR_SUPP
- ATTO_GAI_AF_DIAG_SUPP
- ATTO_GAI_AF_PHYCTRL_SUPP
- ATTO_GAI_AF_SPT_SUPP
- ATTO_GAI_AF_TEST_SUPP
- ATTO_GAI_AF_VIRT_SES
- ATTO_GAI_AT_CELERITY
- ATTO_GAI_AT_CELERITY16
- ATTO_GAI_AT_CELERITY8
- ATTO_GAI_AT_EPCIU320
- ATTO_GAI_AT_ESASHBA
- ATTO_GAI_AT_ESASHBA2
- ATTO_GAI_AT_ESASHBA3
- ATTO_GAI_AT_ESASHBA4
- ATTO_GAI_AT_ESASRAID
- ATTO_GAI_AT_ESASRAID2
- ATTO_GAI_AT_FASTFRAME
- ATTO_GAI_AT_TLSASHBA
- ATTO_GAI_PCIIM_LEGACY
- ATTO_GAI_PCIIM_MSI
- ATTO_GAI_PCIIM_MSIX
- ATTO_GAI_PCIIM_UNKNOWN
- ATTO_GAI_PCILS_GEN1
- ATTO_GAI_PCILS_GEN2
- ATTO_GAI_PCILS_GEN3
- ATTO_GAI_PCILS_UNKNOWN
- ATTO_GAI_PCILW_UNKNOWN
- ATTO_GAI_TF_CONN_CTRL
- ATTO_GAI_TF_GET_DEV_ADDR
- ATTO_GAI_TF_GET_DEV_INFO
- ATTO_GAI_TF_MEM_RW
- ATTO_GAI_TF_PHY_CTRL
- ATTO_GAI_TF_SCSI_PASS_THRU
- ATTO_GAI_TF_TRACE
- ATTO_GDA_AT_MAC
- ATTO_GDA_AT_NODE
- ATTO_GDA_AT_PORT
- ATTO_GDA_AT_PORTID
- ATTO_GDA_AT_UNIQUE
- ATTO_GDI_IT_FC
- ATTO_GDI_IT_FCOE
- ATTO_GDI_IT_SAS
- ATTO_GDI_IT_UNKNOWN
- ATTO_SCSIPortPage2_t
- ATTO_SDI_DT_END_DEVICE
- ATTO_SDI_DT_EXPANDER
- ATTO_SDI_DT_PORT_MULT
- ATTO_SDI_LF_DIRECT
- ATTO_SDI_LF_EXPANDER
- ATTO_SDI_LF_PORT_MULT
- ATTO_SDI_MAX_PHYS_WIDE_PORT
- ATTO_SDI_PHY_ID_INV
- ATTO_SDI_SAS_LVL_INV
- ATTO_SDI_SLOT_NUM_INV
- ATTO_SMPF_ROOT_EXP
- ATTO_SMP_FUNC_DISC_SMP
- ATTO_SMP_FUNC_DISC_SMP_DIRECT
- ATTO_SMP_FUNC_DISC_TARG
- ATTO_SMP_FUNC_DISC_TARG_DIRECT
- ATTO_SMP_FUNC_SEND_CMD
- ATTO_SMP_FUNC_SEND_CMD_DIRECT
- ATTO_SMP_STS_FAILURE
- ATTO_SMP_STS_NOT_FOUND
- ATTO_SMP_STS_RESCAN
- ATTO_SMP_STS_SUCCESS
- ATTO_SMP_VERSION
- ATTO_SMP_VERSION0
- ATTO_SMP_VERSION1
- ATTO_SMP_VERSION2
- ATTO_SPTF_DATA_IN
- ATTO_SPTF_DATA_OUT
- ATTO_SPTF_HEAD_OF_Q
- ATTO_SPTF_ORDERED_Q
- ATTO_SPTF_SIMPLE_Q
- ATTO_SPT_RS_ABORTED
- ATTO_SPT_RS_BUSY
- ATTO_SPT_RS_BUS_RESET
- ATTO_SPT_RS_DEGRADED
- ATTO_SPT_RS_FAILED
- ATTO_SPT_RS_NO_DEVICE
- ATTO_SPT_RS_NO_LUN
- ATTO_SPT_RS_OVERRUN
- ATTO_SPT_RS_SUCCESS
- ATTO_SPT_RS_TIMEOUT
- ATTO_SPT_RS_UNDERRUN
- ATTO_SSDID_TBT
- ATTO_STS_DEGRADED
- ATTO_STS_FAILED
- ATTO_STS_INV_ADAPTER
- ATTO_STS_INV_DRVR_VER
- ATTO_STS_INV_FUNC
- ATTO_STS_INV_PARAM
- ATTO_STS_INV_VERSION
- ATTO_STS_NOT_APPL
- ATTO_STS_OUT_OF_RSRC
- ATTO_STS_SUCCESS
- ATTO_STS_TIMEOUT
- ATTO_STS_UNSUPPORTED
- ATTO_TLSH_1068
- ATTO_TRC_TF_DISABLE
- ATTO_TRC_TF_ENABLE
- ATTO_TRC_TF_GET_INFO
- ATTO_TRC_TF_RESET
- ATTO_TRC_TF_SET_MASK
- ATTO_TRC_TF_UPLOAD
- ATTO_TRC_TT_DRIVER
- ATTO_TRC_TT_FWCOREDUMP
- ATTO_TSSC_3808
- ATTO_TSSC_3808E
- ATTO_VDA_CFG_VER
- ATTO_VDA_CFG_VER0
- ATTO_VDA_CLI_VER
- ATTO_VDA_CLI_VER0
- ATTO_VDA_DIAG_VER
- ATTO_VDA_DIAG_VER0
- ATTO_VDA_FLASH_VER
- ATTO_VDA_FLASH_VER0
- ATTO_VDA_GSV_VER
- ATTO_VDA_GSV_VER0
- ATTO_VDA_MGT_VER
- ATTO_VDA_MGT_VER0
- ATTO_VDA_SCSI_VER
- ATTO_VDA_SCSI_VER0
- ATTO_VDA_SMP_VER
- ATTO_VDA_SMP_VER0
- ATTO_VDA_VER_UNSUPPORTED
- ATTO_VENDOR_ID
- ATTO_VER_ADAP_CTRL
- ATTO_VER_ADAP_CTRL0
- ATTO_VER_GET_ADAP_ADDR
- ATTO_VER_GET_ADAP_ADDR0
- ATTO_VER_GET_ADAP_INFO
- ATTO_VER_GET_ADAP_INFO0
- ATTO_VER_GET_DEV_ADDR
- ATTO_VER_GET_DEV_ADDR0
- ATTO_VER_GET_DEV_INFO
- ATTO_VER_GET_DEV_INFO0
- ATTO_VER_MEM_RW
- ATTO_VER_MEM_RW0
- ATTO_VER_SCSI_PASS_THRU
- ATTO_VER_SCSI_PASS_THRU0
- ATTO_VER_TRACE
- ATTO_VER_TRACE0
- ATTO_VER_TRACE1
- ATTR
- ATTR00__ATTR_PAL_MASK
- ATTR00__ATTR_PAL__SHIFT
- ATTR01__ATTR_PAL_MASK
- ATTR01__ATTR_PAL__SHIFT
- ATTR02__ATTR_PAL_MASK
- ATTR02__ATTR_PAL__SHIFT
- ATTR03__ATTR_PAL_MASK
- ATTR03__ATTR_PAL__SHIFT
- ATTR04__ATTR_PAL_MASK
- ATTR04__ATTR_PAL__SHIFT
- ATTR05__ATTR_PAL_MASK
- ATTR05__ATTR_PAL__SHIFT
- ATTR06__ATTR_PAL_MASK
- ATTR06__ATTR_PAL__SHIFT
- ATTR07__ATTR_PAL_MASK
- ATTR07__ATTR_PAL__SHIFT
- ATTR08__ATTR_PAL_MASK
- ATTR08__ATTR_PAL__SHIFT
- ATTR09__ATTR_PAL_MASK
- ATTR09__ATTR_PAL__SHIFT
- ATTR0A__ATTR_PAL_MASK
- ATTR0A__ATTR_PAL__SHIFT
- ATTR0B__ATTR_PAL_MASK
- ATTR0B__ATTR_PAL__SHIFT
- ATTR0C__ATTR_PAL_MASK
- ATTR0C__ATTR_PAL__SHIFT
- ATTR0D__ATTR_PAL_MASK
- ATTR0D__ATTR_PAL__SHIFT
- ATTR0E__ATTR_PAL_MASK
- ATTR0E__ATTR_PAL__SHIFT
- ATTR0F__ATTR_PAL_MASK
- ATTR0F__ATTR_PAL__SHIFT
- ATTR0_BONUS_WAYS_MASK
- ATTR0_BONUS_WAYS_SHIFT
- ATTR0_RES_WAYS_MASK
- ATTR10__ATTR_BLINK_EN_MASK
- ATTR10__ATTR_BLINK_EN__SHIFT
- ATTR10__ATTR_CSEL_EN_MASK
- ATTR10__ATTR_CSEL_EN__SHIFT
- ATTR10__ATTR_GRPH_MODE_MASK
- ATTR10__ATTR_GRPH_MODE__SHIFT
- ATTR10__ATTR_LGRPH_EN_MASK
- ATTR10__ATTR_LGRPH_EN__SHIFT
- ATTR10__ATTR_MONO_EN_MASK
- ATTR10__ATTR_MONO_EN__SHIFT
- ATTR10__ATTR_PANTOPONLY_MASK
- ATTR10__ATTR_PANTOPONLY__SHIFT
- ATTR10__ATTR_PCLKBY2_MASK
- ATTR10__ATTR_PCLKBY2__SHIFT
- ATTR11__ATTR_OVSC_MASK
- ATTR11__ATTR_OVSC__SHIFT
- ATTR12__ATTR_MAP_EN_MASK
- ATTR12__ATTR_MAP_EN__SHIFT
- ATTR12__ATTR_VSMUX_MASK
- ATTR12__ATTR_VSMUX__SHIFT
- ATTR13__ATTR_PPAN_MASK
- ATTR13__ATTR_PPAN__SHIFT
- ATTR14__ATTR_CSEL1_MASK
- ATTR14__ATTR_CSEL1__SHIFT
- ATTR14__ATTR_CSEL2_MASK
- ATTR14__ATTR_CSEL2__SHIFT
- ATTR1_FIXED_SIZE_SHIFT
- ATTR1_MAX_CAP_SHIFT
- ATTR1_PRIORITY_SHIFT
- ATTR1_PROBE_TARGET_WAYS_SHIFT
- ATTRCMP
- ATTRDR__ATTR_DATA_MASK
- ATTRDR__ATTR_DATA__SHIFT
- ATTRDW__ATTR_DATA_MASK
- ATTRDW__ATTR_DATA__SHIFT
- ATTRELI_EI
- ATTRELI_EI_MASK
- ATTRELI_EL
- ATTRELI_EL_MASK
- ATTRELI_INIT_SETTINGS
- ATTRIB
- ATTRIBUTE
- ATTRIBUTE_CONTAINER_NO_CLASSDEVS
- ATTRIBUTE_GROUPS
- ATTRIBUTE_SECINFO
- ATTRIBUTE_UNUSED
- ATTRIB_BLEEP
- ATTRIB_BLEEP_DEC
- ATTRIB_BLEEP_INC
- ATTRIB_NORET
- ATTRIB_SIZE
- ATTRSHIFT
- ATTRX__ATTR_IDX_MASK
- ATTRX__ATTR_IDX__SHIFT
- ATTRX__ATTR_PAL_RW_ENB_MASK
- ATTRX__ATTR_PAL_RW_ENB__SHIFT
- ATTR_ACA
- ATTR_ACCL_MATRIX
- ATTR_ADDR_MATCH
- ATTR_ALLOC
- ATTR_ARCH
- ATTR_ARCHIVE
- ATTR_ATIME
- ATTR_ATIME_SET
- ATTR_BACKUP_SEMANTICS
- ATTR_BAR_OFFSETS
- ATTR_BAR_SIZES
- ATTR_BAT_IMAX
- ATTR_BAT_ISAFE
- ATTR_BAT_VMAX
- ATTR_BAT_VMIN
- ATTR_BAT_VSAFE
- ATTR_BDSTASH
- ATTR_BTREE_MUTEX
- ATTR_BUFSTASH
- ATTR_CFG_FLD_branch_filter_CFG
- ATTR_CFG_FLD_branch_filter_HI
- ATTR_CFG_FLD_branch_filter_LO
- ATTR_CFG_FLD_event_filter_CFG
- ATTR_CFG_FLD_event_filter_HI
- ATTR_CFG_FLD_event_filter_LO
- ATTR_CFG_FLD_jitter_CFG
- ATTR_CFG_FLD_jitter_HI
- ATTR_CFG_FLD_jitter_LO
- ATTR_CFG_FLD_load_filter_CFG
- ATTR_CFG_FLD_load_filter_HI
- ATTR_CFG_FLD_load_filter_LO
- ATTR_CFG_FLD_min_latency_CFG
- ATTR_CFG_FLD_min_latency_HI
- ATTR_CFG_FLD_min_latency_LO
- ATTR_CFG_FLD_pa_enable_CFG
- ATTR_CFG_FLD_pa_enable_HI
- ATTR_CFG_FLD_pa_enable_LO
- ATTR_CFG_FLD_pct_enable_CFG
- ATTR_CFG_FLD_pct_enable_HI
- ATTR_CFG_FLD_pct_enable_LO
- ATTR_CFG_FLD_store_filter_CFG
- ATTR_CFG_FLD_store_filter_HI
- ATTR_CFG_FLD_store_filter_LO
- ATTR_CFG_FLD_ts_enable_CFG
- ATTR_CFG_FLD_ts_enable_HI
- ATTR_CFG_FLD_ts_enable_LO
- ATTR_CFG_GET_FLD
- ATTR_CHG_VDET
- ATTR_CODE
- ATTR_COMPRESSED
- ATTR_COMPRESSION_MASK
- ATTR_COUNTER
- ATTR_CREATE
- ATTR_CTIME
- ATTR_DATA
- ATTR_DCIN_IMAX
- ATTR_DEF
- ATTR_DEF_ALWAYS_LOG
- ATTR_DEF_FLAGS
- ATTR_DEF_INDEXABLE
- ATTR_DEF_INDEXED_UNIQUE
- ATTR_DEF_MULTIPLE
- ATTR_DEF_NAMED_UNIQUE
- ATTR_DEF_NOT_ZERO
- ATTR_DEF_RESIDENT
- ATTR_DELETE_ON_CLOSE
- ATTR_DEVICE
- ATTR_DEVICE_OWNER
- ATTR_DEVICE_TYPE
- ATTR_DIR
- ATTR_DIRECTORY
- ATTR_DONTFOLLOW
- ATTR_DRIVER_VERSION
- ATTR_ENCRYPTED
- ATTR_ENTBASESIZE
- ATTR_ENTRY
- ATTR_ENTSIZE
- ATTR_EXT
- ATTR_EXTEND
- ATTR_FILE
- ATTR_FLAGS
- ATTR_FORCE
- ATTR_FRAMEWORK_VERSION
- ATTR_GET
- ATTR_GID
- ATTR_GYRO_MATRIX
- ATTR_HARDWARE_REVISION
- ATTR_HEADOFQUEUE
- ATTR_HIDDEN
- ATTR_HW_COHERENCY
- ATTR_ICC_LVL_UNIT_MASK
- ATTR_ICC_LVL_UNIT_OFFSET
- ATTR_ICC_LVL_VALUE_MASK
- ATTR_INCOMPLETE
- ATTR_INDEX
- ATTR_INIT_SETTINGS
- ATTR_INTERRUPT_COUNTS
- ATTR_IS_COMPRESSED
- ATTR_IS_DEVICE_OWNED
- ATTR_IS_ENCRYPTED
- ATTR_IS_SPARSE
- ATTR_KERNEL_FLAGS
- ATTR_KERNEL_HIB_NUM_ACTIVE_PAGES
- ATTR_KERNEL_HIB_PAGE_TABLE_SIZE
- ATTR_KERNEL_HIB_SIMPLE_PAGE_TABLE_SIZE
- ATTR_KERNOTIME
- ATTR_KERNOVAL
- ATTR_KILL_PRIV
- ATTR_KILL_SGID
- ATTR_KILL_SUID
- ATTR_LEN
- ATTR_LIST
- ATTR_LIST_ENTRY
- ATTR_MAX
- ATTR_MAX_VALUELEN
- ATTR_MODE
- ATTR_MTIME
- ATTR_MTIME_SET
- ATTR_NAME_SIZE
- ATTR_NONE
- ATTR_NORMAL
- ATTR_NOT_CONTENT_INDEXED
- ATTR_NO_BUFFERING
- ATTR_OCC
- ATTR_OFFLINE
- ATTR_OPEN
- ATTR_ORDERED
- ATTR_PCI_ADDRESS
- ATTR_POSIX_SEMANTICS
- ATTR_QETH_ISOLATION_DROP
- ATTR_QETH_ISOLATION_FWD
- ATTR_QETH_ISOLATION_NONE
- ATTR_RANDOM_ACCESS
- ATTR_READ
- ATTR_READONLY
- ATTR_REC
- ATTR_RECORD
- ATTR_REPARSE
- ATTR_REPLACE
- ATTR_RESET_COUNT
- ATTR_RMTVALUE_MAPSIZE
- ATTR_RO
- ATTR_ROOT
- ATTR_RWMASK
- ATTR_SECURE
- ATTR_SEQUENTIAL_SCAN
- ATTR_SET
- ATTR_SET_NOR
- ATTR_SET_ST
- ATTR_SET_TYPE_MASK
- ATTR_SHOW_FN
- ATTR_SIMPLE
- ATTR_SIZE
- ATTR_SNOOPING
- ATTR_SPARSE
- ATTR_STATUS
- ATTR_STORE_FN
- ATTR_SUBDIR
- ATTR_SYMLINK
- ATTR_SYS
- ATTR_SYSTEM
- ATTR_TEMPORARY
- ATTR_TIMES_SET
- ATTR_TOUCH
- ATTR_TRUST
- ATTR_TYPE
- ATTR_UID
- ATTR_UNTAGGED
- ATTR_UNUSED
- ATTR_USBIN_IMAX
- ATTR_USER_MEM_RANGES
- ATTR_VIN_MIN
- ATTR_VOLUME
- ATTR_WRITE
- ATTR_WRITE_OPEN_COUNT
- ATTR_WRITE_THROUGH
- ATTRin
- ATTRout
- ATT_IW
- ATT_OWN
- ATT_THRESH_MASK
- ATT_THRESH_SHIFT
- ATUSB_ALLOC_DELAY_MS
- ATUSB_BUF_READ
- ATUSB_BUF_WRITE
- ATUSB_BUILD
- ATUSB_BUILD_SIZE
- ATUSB_EUI64_READ
- ATUSB_EUI64_WRITE
- ATUSB_GPIO
- ATUSB_GPIO_CLEANUP
- ATUSB_HW_TYPE_100813
- ATUSB_HW_TYPE_101216
- ATUSB_HW_TYPE_110131
- ATUSB_HW_TYPE_HULUSB
- ATUSB_HW_TYPE_RZUSB
- ATUSB_ID
- ATUSB_JEDEC_ATMEL
- ATUSB_MAX_ED_LEVELS
- ATUSB_MAX_TX_POWERS
- ATUSB_NUM_RX_URBS
- ATUSB_POLL_INT
- ATUSB_PRODUCT_ID
- ATUSB_REG_READ
- ATUSB_REG_WRITE
- ATUSB_REQ_FROM_DEV
- ATUSB_REQ_TO_DEV
- ATUSB_RESET
- ATUSB_RF_RESET
- ATUSB_RX_MODE
- ATUSB_SLP_TR
- ATUSB_SPI_READ1
- ATUSB_SPI_READ2
- ATUSB_SPI_WRITE
- ATUSB_SPI_WRITE2_SYNC
- ATUSB_SRAM_READ
- ATUSB_SRAM_WRITE
- ATUSB_TEST
- ATUSB_TIMER
- ATUSB_TX
- ATUSB_TX_TIMEOUT_MS
- ATUSB_VENDOR_ID
- ATU_64_SPACE_SIZE
- ATVDA_H
- ATV_AFT_COMM_EXEC_ACTIVE
- ATV_AFT_COMM_EXEC_HOLD
- ATV_AFT_COMM_EXEC_STOP
- ATV_AFT_COMM_EXEC__A
- ATV_AFT_COMM_EXEC__M
- ATV_AFT_COMM_EXEC__PRE
- ATV_AFT_COMM_EXEC__W
- ATV_AFT_TST__A
- ATV_AFT_TST__M
- ATV_AFT_TST__PRE
- ATV_AFT_TST__W
- ATV_COMM_EXEC_ACTIVE
- ATV_COMM_EXEC_HOLD
- ATV_COMM_EXEC_STOP
- ATV_COMM_EXEC__A
- ATV_COMM_EXEC__M
- ATV_COMM_EXEC__PRE
- ATV_COMM_EXEC__W
- ATV_COMM_INT_MSK__A
- ATV_COMM_INT_MSK__M
- ATV_COMM_INT_MSK__PRE
- ATV_COMM_INT_MSK__W
- ATV_COMM_INT_REQ_COMM_INT_REQ__B
- ATV_COMM_INT_REQ_COMM_INT_REQ__M
- ATV_COMM_INT_REQ_COMM_INT_REQ__PRE
- ATV_COMM_INT_REQ_COMM_INT_REQ__W
- ATV_COMM_INT_REQ__A
- ATV_COMM_INT_REQ__M
- ATV_COMM_INT_REQ__PRE
- ATV_COMM_INT_REQ__W
- ATV_COMM_INT_STA__A
- ATV_COMM_INT_STA__M
- ATV_COMM_INT_STA__PRE
- ATV_COMM_INT_STA__W
- ATV_COMM_INT_STM__A
- ATV_COMM_INT_STM__M
- ATV_COMM_INT_STM__PRE
- ATV_COMM_INT_STM__W
- ATV_COMM_KEY_KEY
- ATV_COMM_KEY_MAX
- ATV_COMM_KEY_MIN
- ATV_COMM_KEY__A
- ATV_COMM_KEY__M
- ATV_COMM_KEY__PRE
- ATV_COMM_KEY__W
- ATV_COMM_MB__A
- ATV_COMM_MB__M
- ATV_COMM_MB__PRE
- ATV_COMM_MB__W
- ATV_COMM_STATE__A
- ATV_COMM_STATE__M
- ATV_COMM_STATE__PRE
- ATV_COMM_STATE__W
- ATV_PORTA_CONTROL_REG_BASE
- ATV_PORTB_CONTROL_REG_BASE
- ATV_TOP_AF_SIF_ATT_0DB
- ATV_TOP_AF_SIF_ATT_M3DB
- ATV_TOP_AF_SIF_ATT_M6DB
- ATV_TOP_AF_SIF_ATT_M9DB
- ATV_TOP_AF_SIF_ATT__A
- ATV_TOP_AF_SIF_ATT__M
- ATV_TOP_AF_SIF_ATT__PRE
- ATV_TOP_AF_SIF_ATT__W
- ATV_TOP_COMM_EXEC_ACTIVE
- ATV_TOP_COMM_EXEC_HOLD
- ATV_TOP_COMM_EXEC_STOP
- ATV_TOP_COMM_EXEC__A
- ATV_TOP_COMM_EXEC__M
- ATV_TOP_COMM_EXEC__PRE
- ATV_TOP_COMM_EXEC__W
- ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B
- ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M
- ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE
- ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W
- ATV_TOP_COMM_INT_MSK_FAGC_MSK__B
- ATV_TOP_COMM_INT_MSK_FAGC_MSK__M
- ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE
- ATV_TOP_COMM_INT_MSK_FAGC_MSK__W
- ATV_TOP_COMM_INT_MSK_OVM_MSK__B
- ATV_TOP_COMM_INT_MSK_OVM_MSK__M
- ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE
- ATV_TOP_COMM_INT_MSK_OVM_MSK__W
- ATV_TOP_COMM_INT_MSK__A
- ATV_TOP_COMM_INT_MSK__M
- ATV_TOP_COMM_INT_MSK__PRE
- ATV_TOP_COMM_INT_MSK__W
- ATV_TOP_COMM_INT_REQ__A
- ATV_TOP_COMM_INT_REQ__M
- ATV_TOP_COMM_INT_REQ__PRE
- ATV_TOP_COMM_INT_REQ__W
- ATV_TOP_COMM_INT_STA_AMPTH_STA__B
- ATV_TOP_COMM_INT_STA_AMPTH_STA__M
- ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE
- ATV_TOP_COMM_INT_STA_AMPTH_STA__W
- ATV_TOP_COMM_INT_STA_FAGC_STA__B
- ATV_TOP_COMM_INT_STA_FAGC_STA__M
- ATV_TOP_COMM_INT_STA_FAGC_STA__PRE
- ATV_TOP_COMM_INT_STA_FAGC_STA__W
- ATV_TOP_COMM_INT_STA_OVM_STA__B
- ATV_TOP_COMM_INT_STA_OVM_STA__M
- ATV_TOP_COMM_INT_STA_OVM_STA__PRE
- ATV_TOP_COMM_INT_STA_OVM_STA__W
- ATV_TOP_COMM_INT_STA__A
- ATV_TOP_COMM_INT_STA__M
- ATV_TOP_COMM_INT_STA__PRE
- ATV_TOP_COMM_INT_STA__W
- ATV_TOP_COMM_INT_STM_AMPTH_STM__B
- ATV_TOP_COMM_INT_STM_AMPTH_STM__M
- ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE
- ATV_TOP_COMM_INT_STM_AMPTH_STM__W
- ATV_TOP_COMM_INT_STM_FAGC_STM__B
- ATV_TOP_COMM_INT_STM_FAGC_STM__M
- ATV_TOP_COMM_INT_STM_FAGC_STM__PRE
- ATV_TOP_COMM_INT_STM_FAGC_STM__W
- ATV_TOP_COMM_INT_STM_OVM_STM__B
- ATV_TOP_COMM_INT_STM_OVM_STM__M
- ATV_TOP_COMM_INT_STM_OVM_STM__PRE
- ATV_TOP_COMM_INT_STM_OVM_STM__W
- ATV_TOP_COMM_INT_STM__A
- ATV_TOP_COMM_INT_STM__M
- ATV_TOP_COMM_INT_STM__PRE
- ATV_TOP_COMM_INT_STM__W
- ATV_TOP_COMM_KEY_KEY_KEY
- ATV_TOP_COMM_KEY_KEY_MAX
- ATV_TOP_COMM_KEY_KEY_MIN
- ATV_TOP_COMM_KEY_KEY__B
- ATV_TOP_COMM_KEY_KEY__M
- ATV_TOP_COMM_KEY_KEY__PRE
- ATV_TOP_COMM_KEY_KEY__W
- ATV_TOP_COMM_KEY__A
- ATV_TOP_COMM_KEY__M
- ATV_TOP_COMM_KEY__PRE
- ATV_TOP_COMM_KEY__W
- ATV_TOP_COMM_MB_CTL__B
- ATV_TOP_COMM_MB_CTL__M
- ATV_TOP_COMM_MB_CTL__PRE
- ATV_TOP_COMM_MB_CTL__W
- ATV_TOP_COMM_MB_MUX_CTRL_CORR_O
- ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ
- ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O
- ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S
- ATV_TOP_COMM_MB_MUX_CTRL_POST_S
- ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O
- ATV_TOP_COMM_MB_MUX_CTRL_SIF_O
- ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O
- ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN
- ATV_TOP_COMM_MB_MUX_CTRL__B
- ATV_TOP_COMM_MB_MUX_CTRL__M
- ATV_TOP_COMM_MB_MUX_CTRL__PRE
- ATV_TOP_COMM_MB_MUX_CTRL__W
- ATV_TOP_COMM_MB_MUX_OBS_CORR_O
- ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ
- ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O
- ATV_TOP_COMM_MB_MUX_OBS_PEAK_S
- ATV_TOP_COMM_MB_MUX_OBS_POST_S
- ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O
- ATV_TOP_COMM_MB_MUX_OBS_SIF_O
- ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O
- ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN
- ATV_TOP_COMM_MB_MUX_OBS__B
- ATV_TOP_COMM_MB_MUX_OBS__M
- ATV_TOP_COMM_MB_MUX_OBS__PRE
- ATV_TOP_COMM_MB_MUX_OBS__W
- ATV_TOP_COMM_MB_OBS__B
- ATV_TOP_COMM_MB_OBS__M
- ATV_TOP_COMM_MB_OBS__PRE
- ATV_TOP_COMM_MB_OBS__W
- ATV_TOP_COMM_MB__A
- ATV_TOP_COMM_MB__M
- ATV_TOP_COMM_MB__PRE
- ATV_TOP_COMM_MB__W
- ATV_TOP_COMM_STATE_STATE__B
- ATV_TOP_COMM_STATE_STATE__M
- ATV_TOP_COMM_STATE_STATE__PRE
- ATV_TOP_COMM_STATE_STATE__W
- ATV_TOP_COMM_STATE__A
- ATV_TOP_COMM_STATE__M
- ATV_TOP_COMM_STATE__PRE
- ATV_TOP_COMM_STATE__W
- ATV_TOP_CR_AMP_TH_BG
- ATV_TOP_CR_AMP_TH_DK
- ATV_TOP_CR_AMP_TH_FM
- ATV_TOP_CR_AMP_TH_I
- ATV_TOP_CR_AMP_TH_L
- ATV_TOP_CR_AMP_TH_LP
- ATV_TOP_CR_AMP_TH_MN
- ATV_TOP_CR_AMP_TH__A
- ATV_TOP_CR_AMP_TH__M
- ATV_TOP_CR_AMP_TH__PRE
- ATV_TOP_CR_AMP_TH__W
- ATV_TOP_CR_CONT_CR_D_BG
- ATV_TOP_CR_CONT_CR_D_DK
- ATV_TOP_CR_CONT_CR_D_FM
- ATV_TOP_CR_CONT_CR_D_I
- ATV_TOP_CR_CONT_CR_D_L
- ATV_TOP_CR_CONT_CR_D_LP
- ATV_TOP_CR_CONT_CR_D_MN
- ATV_TOP_CR_CONT_CR_D__B
- ATV_TOP_CR_CONT_CR_D__M
- ATV_TOP_CR_CONT_CR_D__PRE
- ATV_TOP_CR_CONT_CR_D__W
- ATV_TOP_CR_CONT_CR_I_BG
- ATV_TOP_CR_CONT_CR_I_DK
- ATV_TOP_CR_CONT_CR_I_FM
- ATV_TOP_CR_CONT_CR_I_I
- ATV_TOP_CR_CONT_CR_I_L
- ATV_TOP_CR_CONT_CR_I_LP
- ATV_TOP_CR_CONT_CR_I_MN
- ATV_TOP_CR_CONT_CR_I__B
- ATV_TOP_CR_CONT_CR_I__M
- ATV_TOP_CR_CONT_CR_I__PRE
- ATV_TOP_CR_CONT_CR_I__W
- ATV_TOP_CR_CONT_CR_P_BG
- ATV_TOP_CR_CONT_CR_P_DK
- ATV_TOP_CR_CONT_CR_P_FM
- ATV_TOP_CR_CONT_CR_P_I
- ATV_TOP_CR_CONT_CR_P_L
- ATV_TOP_CR_CONT_CR_P_LP
- ATV_TOP_CR_CONT_CR_P_MN
- ATV_TOP_CR_CONT_CR_P__B
- ATV_TOP_CR_CONT_CR_P__M
- ATV_TOP_CR_CONT_CR_P__PRE
- ATV_TOP_CR_CONT_CR_P__W
- ATV_TOP_CR_CONT__A
- ATV_TOP_CR_CONT__M
- ATV_TOP_CR_CONT__PRE
- ATV_TOP_CR_CONT__W
- ATV_TOP_CR_FREQ__A
- ATV_TOP_CR_FREQ__M
- ATV_TOP_CR_FREQ__PRE
- ATV_TOP_CR_FREQ__W
- ATV_TOP_CR_OVM_TH_BG
- ATV_TOP_CR_OVM_TH_DK
- ATV_TOP_CR_OVM_TH_FM
- ATV_TOP_CR_OVM_TH_I
- ATV_TOP_CR_OVM_TH_L
- ATV_TOP_CR_OVM_TH_LP
- ATV_TOP_CR_OVM_TH_MN
- ATV_TOP_CR_OVM_TH__A
- ATV_TOP_CR_OVM_TH__M
- ATV_TOP_CR_OVM_TH__PRE
- ATV_TOP_CR_OVM_TH__W
- ATV_TOP_CR_PHAD__A
- ATV_TOP_CR_PHAD__M
- ATV_TOP_CR_PHAD__PRE
- ATV_TOP_CR_PHAD__W
- ATV_TOP_EQU0_EQU_C0_BG
- ATV_TOP_EQU0_EQU_C0_DK
- ATV_TOP_EQU0_EQU_C0_FM
- ATV_TOP_EQU0_EQU_C0_I
- ATV_TOP_EQU0_EQU_C0_L
- ATV_TOP_EQU0_EQU_C0_LP
- ATV_TOP_EQU0_EQU_C0_MN
- ATV_TOP_EQU0_EQU_C0__B
- ATV_TOP_EQU0_EQU_C0__M
- ATV_TOP_EQU0_EQU_C0__PRE
- ATV_TOP_EQU0_EQU_C0__W
- ATV_TOP_EQU0__A
- ATV_TOP_EQU0__M
- ATV_TOP_EQU0__PRE
- ATV_TOP_EQU0__W
- ATV_TOP_EQU1_EQU_C1_BG
- ATV_TOP_EQU1_EQU_C1_DK
- ATV_TOP_EQU1_EQU_C1_FM
- ATV_TOP_EQU1_EQU_C1_I
- ATV_TOP_EQU1_EQU_C1_L
- ATV_TOP_EQU1_EQU_C1_LP
- ATV_TOP_EQU1_EQU_C1_MN
- ATV_TOP_EQU1_EQU_C1__B
- ATV_TOP_EQU1_EQU_C1__M
- ATV_TOP_EQU1_EQU_C1__PRE
- ATV_TOP_EQU1_EQU_C1__W
- ATV_TOP_EQU1__A
- ATV_TOP_EQU1__M
- ATV_TOP_EQU1__PRE
- ATV_TOP_EQU1__W
- ATV_TOP_EQU2_EQU_C2_BG
- ATV_TOP_EQU2_EQU_C2_DK
- ATV_TOP_EQU2_EQU_C2_FM
- ATV_TOP_EQU2_EQU_C2_I
- ATV_TOP_EQU2_EQU_C2_L
- ATV_TOP_EQU2_EQU_C2_LP
- ATV_TOP_EQU2_EQU_C2_MN
- ATV_TOP_EQU2_EQU_C2__B
- ATV_TOP_EQU2_EQU_C2__M
- ATV_TOP_EQU2_EQU_C2__PRE
- ATV_TOP_EQU2_EQU_C2__W
- ATV_TOP_EQU2__A
- ATV_TOP_EQU2__M
- ATV_TOP_EQU2__PRE
- ATV_TOP_EQU2__W
- ATV_TOP_EQU3_EQU_C3_BG
- ATV_TOP_EQU3_EQU_C3_DK
- ATV_TOP_EQU3_EQU_C3_FM
- ATV_TOP_EQU3_EQU_C3_I
- ATV_TOP_EQU3_EQU_C3_L
- ATV_TOP_EQU3_EQU_C3_LP
- ATV_TOP_EQU3_EQU_C3_MN
- ATV_TOP_EQU3_EQU_C3__B
- ATV_TOP_EQU3_EQU_C3__M
- ATV_TOP_EQU3_EQU_C3__PRE
- ATV_TOP_EQU3_EQU_C3__W
- ATV_TOP_EQU3__A
- ATV_TOP_EQU3__M
- ATV_TOP_EQU3__PRE
- ATV_TOP_EQU3__W
- ATV_TOP_FAGC_TH_MN
- ATV_TOP_FAGC_TH__A
- ATV_TOP_FAGC_TH__M
- ATV_TOP_FAGC_TH__PRE
- ATV_TOP_FAGC_TH__W
- ATV_TOP_MOD_ACCU__A
- ATV_TOP_MOD_ACCU__M
- ATV_TOP_MOD_ACCU__PRE
- ATV_TOP_MOD_ACCU__W
- ATV_TOP_MOD_CONTROL_MOD_IF_FM
- ATV_TOP_MOD_CONTROL_MOD_IF_MN
- ATV_TOP_MOD_CONTROL_MOD_IF__B
- ATV_TOP_MOD_CONTROL_MOD_IF__M
- ATV_TOP_MOD_CONTROL_MOD_IF__PRE
- ATV_TOP_MOD_CONTROL_MOD_IF__W
- ATV_TOP_MOD_CONTROL_MOD_IR_FM
- ATV_TOP_MOD_CONTROL_MOD_IR_MN
- ATV_TOP_MOD_CONTROL_MOD_IR__B
- ATV_TOP_MOD_CONTROL_MOD_IR__M
- ATV_TOP_MOD_CONTROL_MOD_IR__PRE
- ATV_TOP_MOD_CONTROL_MOD_IR__W
- ATV_TOP_MOD_CONTROL_MOD_MODE_RISE
- ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL
- ATV_TOP_MOD_CONTROL_MOD_MODE__B
- ATV_TOP_MOD_CONTROL_MOD_MODE__M
- ATV_TOP_MOD_CONTROL_MOD_MODE__PRE
- ATV_TOP_MOD_CONTROL_MOD_MODE__W
- ATV_TOP_MOD_CONTROL_MOD_TH_FM
- ATV_TOP_MOD_CONTROL_MOD_TH_MN
- ATV_TOP_MOD_CONTROL_MOD_TH__B
- ATV_TOP_MOD_CONTROL_MOD_TH__M
- ATV_TOP_MOD_CONTROL_MOD_TH__PRE
- ATV_TOP_MOD_CONTROL_MOD_TH__W
- ATV_TOP_MOD_CONTROL__A
- ATV_TOP_MOD_CONTROL__M
- ATV_TOP_MOD_CONTROL__PRE
- ATV_TOP_MOD_CONTROL__W
- ATV_TOP_NOISE_TH_MN
- ATV_TOP_NOISE_TH__A
- ATV_TOP_NOISE_TH__M
- ATV_TOP_NOISE_TH__PRE
- ATV_TOP_NOISE_TH__W
- ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED
- ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL
- ATV_TOP_OUT_CONF_CVBS_DAC_BR__B
- ATV_TOP_OUT_CONF_CVBS_DAC_BR__M
- ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE
- ATV_TOP_OUT_CONF_CVBS_DAC_BR__W
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE
- ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W
- ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED
- ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED
- ATV_TOP_OUT_CONF_SIF20_SIGN__B
- ATV_TOP_OUT_CONF_SIF20_SIGN__M
- ATV_TOP_OUT_CONF_SIF20_SIGN__PRE
- ATV_TOP_OUT_CONF_SIF20_SIGN__W
- ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED
- ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL
- ATV_TOP_OUT_CONF_SIF_DAC_BR__B
- ATV_TOP_OUT_CONF_SIF_DAC_BR__M
- ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE
- ATV_TOP_OUT_CONF_SIF_DAC_BR__W
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE
- ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W
- ATV_TOP_OUT_CONF__A
- ATV_TOP_OUT_CONF__M
- ATV_TOP_OUT_CONF__PRE
- ATV_TOP_OUT_CONF__W
- ATV_TOP_OVERRIDE_SFR_ACTIVE
- ATV_TOP_OVERRIDE_SFR_OVERRIDE
- ATV_TOP_OVERRIDE_SFR__A
- ATV_TOP_OVERRIDE_SFR__M
- ATV_TOP_OVERRIDE_SFR__PRE
- ATV_TOP_OVERRIDE_SFR__W
- ATV_TOP_OVM_COMP__A
- ATV_TOP_OVM_COMP__M
- ATV_TOP_OVM_COMP__PRE
- ATV_TOP_OVM_COMP__W
- ATV_TOP_ROT_MODE_ALWAYS
- ATV_TOP_ROT_MODE_AMPTH_DEPEND
- ATV_TOP_ROT_MODE__A
- ATV_TOP_ROT_MODE__M
- ATV_TOP_ROT_MODE__PRE
- ATV_TOP_ROT_MODE__W
- ATV_TOP_SFR_AGC_RES__A
- ATV_TOP_SFR_AGC_RES__M
- ATV_TOP_SFR_AGC_RES__PRE
- ATV_TOP_SFR_AGC_RES__W
- ATV_TOP_SFR_VID_GAIN__A
- ATV_TOP_SFR_VID_GAIN__M
- ATV_TOP_SFR_VID_GAIN__PRE
- ATV_TOP_SFR_VID_GAIN__W
- ATV_TOP_SIF_GAIN__A
- ATV_TOP_SIF_GAIN__M
- ATV_TOP_SIF_GAIN__PRE
- ATV_TOP_SIF_GAIN__W
- ATV_TOP_SIF_TP__A
- ATV_TOP_SIF_TP__M
- ATV_TOP_SIF_TP__PRE
- ATV_TOP_SIF_TP__W
- ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE
- ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY
- ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE
- ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY
- ATV_TOP_STDBY_CVBS_STDBY__B
- ATV_TOP_STDBY_CVBS_STDBY__M
- ATV_TOP_STDBY_CVBS_STDBY__PRE
- ATV_TOP_STDBY_CVBS_STDBY__W
- ATV_TOP_STDBY_SIF_STDBY_ACTIVE
- ATV_TOP_STDBY_SIF_STDBY_STANDBY
- ATV_TOP_STDBY_SIF_STDBY__B
- ATV_TOP_STDBY_SIF_STDBY__M
- ATV_TOP_STDBY_SIF_STDBY__PRE
- ATV_TOP_STDBY_SIF_STDBY__W
- ATV_TOP_STDBY__A
- ATV_TOP_STDBY__M
- ATV_TOP_STDBY__PRE
- ATV_TOP_STDBY__W
- ATV_TOP_STD_MODE_BG
- ATV_TOP_STD_MODE_DK
- ATV_TOP_STD_MODE_FM
- ATV_TOP_STD_MODE_I
- ATV_TOP_STD_MODE_L
- ATV_TOP_STD_MODE_LP
- ATV_TOP_STD_MODE_MN
- ATV_TOP_STD_MODE__B
- ATV_TOP_STD_MODE__M
- ATV_TOP_STD_MODE__PRE
- ATV_TOP_STD_MODE__W
- ATV_TOP_STD_VID_POL_BG
- ATV_TOP_STD_VID_POL_DK
- ATV_TOP_STD_VID_POL_FM
- ATV_TOP_STD_VID_POL_I
- ATV_TOP_STD_VID_POL_L
- ATV_TOP_STD_VID_POL_LP
- ATV_TOP_STD_VID_POL_MN
- ATV_TOP_STD_VID_POL_NEG
- ATV_TOP_STD_VID_POL_POS
- ATV_TOP_STD_VID_POL__B
- ATV_TOP_STD_VID_POL__M
- ATV_TOP_STD_VID_POL__PRE
- ATV_TOP_STD_VID_POL__W
- ATV_TOP_STD__A
- ATV_TOP_STD__M
- ATV_TOP_STD__PRE
- ATV_TOP_STD__W
- ATV_TOP_SYNC_SLICE_MN
- ATV_TOP_SYNC_SLICE__A
- ATV_TOP_SYNC_SLICE__M
- ATV_TOP_SYNC_SLICE__PRE
- ATV_TOP_SYNC_SLICE__W
- ATV_TOP_VID_AMP_BG
- ATV_TOP_VID_AMP_DK
- ATV_TOP_VID_AMP_FM
- ATV_TOP_VID_AMP_I
- ATV_TOP_VID_AMP_L
- ATV_TOP_VID_AMP_LP
- ATV_TOP_VID_AMP_MN
- ATV_TOP_VID_AMP__A
- ATV_TOP_VID_AMP__M
- ATV_TOP_VID_AMP__PRE
- ATV_TOP_VID_AMP__W
- ATV_TOP_VID_PEAK__A
- ATV_TOP_VID_PEAK__M
- ATV_TOP_VID_PEAK__PRE
- ATV_TOP_VID_PEAK__W
- ATXCTL_B24
- ATXCTL_BEN
- ATXCTL_BMUX
- ATXCTL_CD
- ATXCTL_CPF
- ATXCTL_EN
- ATXCTL_LIV
- ATXCTL_LSAT
- ATXCTL_MODE
- ATXCTL_MT
- ATXCTL_NUC
- ATXCTL_RAW
- ATXCTL_RIV
- ATXCTL_RSAT
- ATXP1_CVID
- ATXP1_GPIO1
- ATXP1_GPIO1MASK
- ATXP1_GPIO2
- ATXP1_VID
- ATXP1_VIDENA
- ATXP1_VIDMASK
- ATYIO_CLKR
- ATYIO_CLKW
- ATYIO_FEATR
- ATYIO_FEATW
- ATY_MIRROR_CRT_ON
- ATY_MIRROR_LCD_ON
- ATY_RADEON_CRT_ON
- ATY_RADEON_LCD_ON
- AT_ADI_BLKSZ
- AT_ADI_NBITS
- AT_ADI_UEONADI
- AT_ADV_MASK
- AT_ASPM_L0S_TIMER
- AT_ASPM_L1_TIMER
- AT_ATTRIBUTE_LIST
- AT_BASE
- AT_BASE_PLATFORM
- AT_BC
- AT_BITMAP
- AT_CLIP
- AT_CLKTCK
- AT_COMPAT_CLRIOCHK
- AT_COMPAT_CLRSERR
- AT_COMPAT_IOCHK
- AT_COMPAT_SERR
- AT_DATA
- AT_DCACHEBSIZE
- AT_DEF_RECEIVE_QUEUE
- AT_DIAL
- AT_DMA_ARB_CFG
- AT_DMA_ARB_CFG_FIXED
- AT_DMA_ARB_CFG_ROUND_ROBIN
- AT_DMA_BTC
- AT_DMA_CBTC
- AT_DMA_CBTC_OFFSET
- AT_DMA_CHDR
- AT_DMA_CHER
- AT_DMA_CHSR
- AT_DMA_CH_REGS_BASE
- AT_DMA_CREQ
- AT_DMA_DCREQ
- AT_DMA_DIS
- AT_DMA_DLAST
- AT_DMA_DSREQ
- AT_DMA_EBCIDR
- AT_DMA_EBCIER
- AT_DMA_EBCIMR
- AT_DMA_EBCISR
- AT_DMA_EMPT
- AT_DMA_EN
- AT_DMA_ENA
- AT_DMA_ENABLE
- AT_DMA_ERR
- AT_DMA_ERR_OFFSET
- AT_DMA_GCFG
- AT_DMA_HI_ADDR_MASK
- AT_DMA_IF_BIGEND
- AT_DMA_KEEP
- AT_DMA_LAST
- AT_DMA_LO_ADDR_MASK
- AT_DMA_MAX_NR_CHANNELS
- AT_DMA_MEM_IF
- AT_DMA_PER_IF
- AT_DMA_RES
- AT_DMA_SCREQ
- AT_DMA_SLAST
- AT_DMA_SREQ
- AT_DMA_SSREQ
- AT_DMA_STAL
- AT_DMA_SUSP
- AT_DMA_SYNC
- AT_DMA_SYR
- AT_EA
- AT_EA_INFORMATION
- AT_EEPROM_LEN
- AT_EGID
- AT_EMPTY_PATH
- AT_END
- AT_ENTRY
- AT_ERR_CONFIG
- AT_ERR_EEPROM
- AT_ERR_MAC_TYPE
- AT_ERR_PARAM
- AT_ERR_PHY
- AT_ERR_PHY_RES
- AT_ERR_PHY_SPEED
- AT_ERR_PHY_TYPE
- AT_ERR_TIMEOUT
- AT_EUID
- AT_EXECFD
- AT_EXECFN
- AT_FDCWD
- AT_FILE_NAME
- AT_FIRST_USER_DEFINED_ATTRIBUTE
- AT_FLAGS
- AT_FPUCW
- AT_GID
- AT_HDMAC_H
- AT_HDMAC_REGS_H
- AT_HWCAP
- AT_HWCAP2
- AT_HW_MAX_IDLE_DELAY
- AT_ICACHEBSIZE
- AT_IGNORE
- AT_IGNOREPPC
- AT_INDEX_ALLOCATION
- AT_INDEX_ROOT
- AT_ISO
- AT_L1D_CACHEGEOMETRY
- AT_L1D_CACHESHAPE
- AT_L1D_CACHESIZE
- AT_L1I_CACHEGEOMETRY
- AT_L1I_CACHESHAPE
- AT_L1I_CACHESIZE
- AT_L2_CACHEGEOMETRY
- AT_L2_CACHESHAPE
- AT_L2_CACHESIZE
- AT_L3_CACHEGEOMETRY
- AT_L3_CACHESHAPE
- AT_L3_CACHESIZE
- AT_LCKDET_TIMER
- AT_LOGGED_UTILITY_STREAM
- AT_MASK
- AT_MAX_INT_WORK
- AT_MAX_RECEIVE_QUEUE
- AT_MAX_TRANSMIT_QUEUE
- AT_MINSIGSTKSZ
- AT_MODE
- AT_MSN
- AT_NOTELF
- AT_NO_AUTOMOUNT
- AT_NULL
- AT_NUM
- AT_OBJECT_ID
- AT_PAGESZ
- AT_PAGE_NUM_PER_QUEUE
- AT_PHDR
- AT_PHENT
- AT_PHNUM
- AT_PKT_TYPE
- AT_PLATFORM
- AT_PROPERTY_SET
- AT_PROTO
- AT_RANDOM
- AT_READ_REG
- AT_READ_REGB
- AT_READ_REGW
- AT_READ_REG_ARRAY
- AT_RECURSIVE
- AT_REGS_LEN
- AT_REMOVEDIR
- AT_REPARSE_POINT
- AT_RX_BUF_SIZE
- AT_SECURE
- AT_SECURITY_DESCRIPTOR
- AT_SHIFT
- AT_SLICE_BOUNDARY
- AT_STANDARD_INFORMATION
- AT_STATX_DONT_SYNC
- AT_STATX_FORCE_SYNC
- AT_STATX_SYNC_AS_STAT
- AT_STATX_SYNC_TYPE
- AT_SUSPEND_LINK_TIMEOUT
- AT_SYMLINK_FOLLOW
- AT_SYMLINK_NOFOLLOW
- AT_SYSINFO
- AT_SYSINFO_EHDR
- AT_TAG_TO_VLAN
- AT_TPD_TAG_TO_VLAN_TAG
- AT_TWSI_EEPROM_TIMEOUT
- AT_TX_WATCHDOG
- AT_TYPE
- AT_UCACHEBSIZE
- AT_UID
- AT_UNUSED
- AT_VECTOR_SIZE
- AT_VECTOR_SIZE_ARCH
- AT_VECTOR_SIZE_BASE
- AT_VENDOR_ID
- AT_VLAN_TAG_TO_TPD_TAG
- AT_VLAN_TO_TAG
- AT_VOLUME_INFORMATION
- AT_VOLUME_NAME
- AT_VTKIT3_PRODUCT_ID
- AT_WRITE_FLUSH
- AT_WRITE_REG
- AT_WRITE_REGB
- AT_WRITE_REGW
- AT_WRITE_REG_ARRAY
- AT_WUFC_BC
- AT_WUFC_EX
- AT_WUFC_LNKC
- AT_WUFC_MAG
- AT_WUFC_MC
- AT_XDMAC_CBC
- AT_XDMAC_CC
- AT_XDMAC_CC_CSIZE
- AT_XDMAC_CC_DAM_FIXED_AM
- AT_XDMAC_CC_DAM_INCREMENTED_AM
- AT_XDMAC_CC_DAM_MASK
- AT_XDMAC_CC_DAM_UBS_AM
- AT_XDMAC_CC_DAM_UBS_DS_AM
- AT_XDMAC_CC_DIF
- AT_XDMAC_CC_DSYNC
- AT_XDMAC_CC_DSYNC_MEM2PER
- AT_XDMAC_CC_DSYNC_PER2MEM
- AT_XDMAC_CC_DWIDTH
- AT_XDMAC_CC_DWIDTH_BYTE
- AT_XDMAC_CC_DWIDTH_DWORD
- AT_XDMAC_CC_DWIDTH_HALFWORD
- AT_XDMAC_CC_DWIDTH_MASK
- AT_XDMAC_CC_DWIDTH_OFFSET
- AT_XDMAC_CC_DWIDTH_WORD
- AT_XDMAC_CC_INITD
- AT_XDMAC_CC_INITD_IN_PROGRESS
- AT_XDMAC_CC_INITD_TERMINATED
- AT_XDMAC_CC_MBSIZE_EIGHT
- AT_XDMAC_CC_MBSIZE_FOUR
- AT_XDMAC_CC_MBSIZE_MASK
- AT_XDMAC_CC_MBSIZE_SINGLE
- AT_XDMAC_CC_MBSIZE_SIXTEEN
- AT_XDMAC_CC_MEMSET
- AT_XDMAC_CC_MEMSET_HW_MODE
- AT_XDMAC_CC_MEMSET_NORMAL_MODE
- AT_XDMAC_CC_PERID
- AT_XDMAC_CC_PROT
- AT_XDMAC_CC_PROT_SEC
- AT_XDMAC_CC_PROT_UNSEC
- AT_XDMAC_CC_RDIP
- AT_XDMAC_CC_RDIP_DONE
- AT_XDMAC_CC_RDIP_IN_PROGRESS
- AT_XDMAC_CC_SAM_FIXED_AM
- AT_XDMAC_CC_SAM_INCREMENTED_AM
- AT_XDMAC_CC_SAM_MASK
- AT_XDMAC_CC_SAM_UBS_AM
- AT_XDMAC_CC_SAM_UBS_DS_AM
- AT_XDMAC_CC_SIF
- AT_XDMAC_CC_SWREQ
- AT_XDMAC_CC_SWREQ_HWR_CONNECTED
- AT_XDMAC_CC_SWREQ_SWR_CONNECTED
- AT_XDMAC_CC_TYPE
- AT_XDMAC_CC_TYPE_MEM_TRAN
- AT_XDMAC_CC_TYPE_PER_TRAN
- AT_XDMAC_CC_WRIP
- AT_XDMAC_CC_WRIP_DONE
- AT_XDMAC_CC_WRIP_IN_PROGRESS
- AT_XDMAC_CDA
- AT_XDMAC_CDS_MSP
- AT_XDMAC_CDUS
- AT_XDMAC_CHAN_IS_CYCLIC
- AT_XDMAC_CHAN_IS_PAUSED
- AT_XDMAC_CHAN_REG_BASE
- AT_XDMAC_CID
- AT_XDMAC_CID_BID
- AT_XDMAC_CID_DID
- AT_XDMAC_CID_FID
- AT_XDMAC_CID_LID
- AT_XDMAC_CID_RBEID
- AT_XDMAC_CID_ROID
- AT_XDMAC_CID_WBEID
- AT_XDMAC_CIE
- AT_XDMAC_CIE_BIE
- AT_XDMAC_CIE_DIE
- AT_XDMAC_CIE_FIE
- AT_XDMAC_CIE_LIE
- AT_XDMAC_CIE_RBEIE
- AT_XDMAC_CIE_ROIE
- AT_XDMAC_CIE_WBEIE
- AT_XDMAC_CIM
- AT_XDMAC_CIM_BIM
- AT_XDMAC_CIM_DIM
- AT_XDMAC_CIM_FIM
- AT_XDMAC_CIM_LIM
- AT_XDMAC_CIM_RBEIM
- AT_XDMAC_CIM_ROIM
- AT_XDMAC_CIM_WBEIM
- AT_XDMAC_CIS
- AT_XDMAC_CIS_BIS
- AT_XDMAC_CIS_DIS
- AT_XDMAC_CIS_FIS
- AT_XDMAC_CIS_LIS
- AT_XDMAC_CIS_RBEIS
- AT_XDMAC_CIS_ROIS
- AT_XDMAC_CIS_WBEIS
- AT_XDMAC_CNDA
- AT_XDMAC_CNDA_NDA
- AT_XDMAC_CNDA_NDAIF
- AT_XDMAC_CNDC
- AT_XDMAC_CNDC_NDDUP
- AT_XDMAC_CNDC_NDE
- AT_XDMAC_CNDC_NDSUP
- AT_XDMAC_CNDC_NDVIEW_NDV0
- AT_XDMAC_CNDC_NDVIEW_NDV1
- AT_XDMAC_CNDC_NDVIEW_NDV2
- AT_XDMAC_CNDC_NDVIEW_NDV3
- AT_XDMAC_CSA
- AT_XDMAC_CSUS
- AT_XDMAC_CUBC
- AT_XDMAC_DMA_BUSWIDTHS
- AT_XDMAC_FIFO_SZ
- AT_XDMAC_GCFG
- AT_XDMAC_GD
- AT_XDMAC_GE
- AT_XDMAC_GID
- AT_XDMAC_GIE
- AT_XDMAC_GIM
- AT_XDMAC_GIS
- AT_XDMAC_GRS
- AT_XDMAC_GRWR
- AT_XDMAC_GRWS
- AT_XDMAC_GS
- AT_XDMAC_GSWF
- AT_XDMAC_GSWR
- AT_XDMAC_GSWS
- AT_XDMAC_GTYPE
- AT_XDMAC_GWAC
- AT_XDMAC_GWS
- AT_XDMAC_MAX_CHAN
- AT_XDMAC_MAX_CSIZE
- AT_XDMAC_MAX_DWIDTH
- AT_XDMAC_MBR_UBC_NDE
- AT_XDMAC_MBR_UBC_NDEN
- AT_XDMAC_MBR_UBC_NDV0
- AT_XDMAC_MBR_UBC_NDV1
- AT_XDMAC_MBR_UBC_NDV2
- AT_XDMAC_MBR_UBC_NDV3
- AT_XDMAC_MBR_UBC_NSEN
- AT_XDMAC_MBR_UBC_UBLEN_MAX
- AT_XDMAC_NB_CH
- AT_XDMAC_NB_REQ
- AT_XDMAC_RESIDUE_MAX_RETRIES
- AT_XDMAC_VERSION
- AT_spin
- AU0828_AUDIOCTRL_50C
- AU0828_BOARD_DVICO_FUSIONHDTV7
- AU0828_BOARD_HAUPPAUGE_HVR850
- AU0828_BOARD_HAUPPAUGE_HVR950Q
- AU0828_BOARD_HAUPPAUGE_HVR950Q_MXL
- AU0828_BOARD_HAUPPAUGE_WOODBURY
- AU0828_BOARD_UNKNOWN
- AU0828_DEF_BUF
- AU0828_DEVICE
- AU0828_I2C_CLK_100KHZ
- AU0828_I2C_CLK_20KHZ
- AU0828_I2C_CLK_250KHZ
- AU0828_I2C_CLK_30KHZ
- AU0828_I2C_CLK_DIVIDER_202
- AU0828_I2C_DEST_ADDR_203
- AU0828_I2C_MULTIBYTE_MODE_2FF
- AU0828_I2C_READ_FIFO_209
- AU0828_I2C_STATUS_201
- AU0828_I2C_STATUS_BUSY
- AU0828_I2C_STATUS_NO_READ_ACK
- AU0828_I2C_STATUS_NO_WRITE_ACK
- AU0828_I2C_STATUS_READ_DONE
- AU0828_I2C_STATUS_WRITE_DONE
- AU0828_I2C_TRIGGER_200
- AU0828_I2C_TRIGGER_HOLD
- AU0828_I2C_TRIGGER_READ
- AU0828_I2C_TRIGGER_WRITE
- AU0828_I2C_WRITE_FIFO_205
- AU0828_INTERLACED_DEFAULT
- AU0828_ISO_PACKETS_PER_URB
- AU0828_MAX_INPUT
- AU0828_MAX_ISO_BUFS
- AU0828_MIN_BUF
- AU0828_RESOURCE_VBI
- AU0828_RESOURCE_VIDEO
- AU0828_SENSORCTRL_100
- AU0828_SENSORCTRL_VBI_103
- AU0828_VMUX_CABLE
- AU0828_VMUX_COMPOSITE
- AU0828_VMUX_DVB
- AU0828_VMUX_SVIDEO
- AU0828_VMUX_TELEVISION
- AU0828_VMUX_UNDEFINED
- AU0_AC97_SEL
- AU1000_AC97C_INT
- AU1000_AC97_PHYS_ADDR
- AU1000_ACSYNC_INT
- AU1000_DEF_MSG_ENABLE
- AU1000_DMA_INT_BASE
- AU1000_DMA_PHYS_ADDR
- AU1000_FIRST_INT
- AU1000_GPIO0_INT
- AU1000_GPIO10_INT
- AU1000_GPIO11_INT
- AU1000_GPIO12_INT
- AU1000_GPIO13_INT
- AU1000_GPIO14_INT
- AU1000_GPIO15_INT
- AU1000_GPIO16_INT
- AU1000_GPIO17_INT
- AU1000_GPIO18_INT
- AU1000_GPIO19_INT
- AU1000_GPIO1_INT
- AU1000_GPIO20_INT
- AU1000_GPIO21_INT
- AU1000_GPIO22_INT
- AU1000_GPIO23_INT
- AU1000_GPIO24_INT
- AU1000_GPIO25_INT
- AU1000_GPIO26_INT
- AU1000_GPIO27_INT
- AU1000_GPIO28_INT
- AU1000_GPIO29_INT
- AU1000_GPIO2_DIR
- AU1000_GPIO2_ENABLE
- AU1000_GPIO2_INT
- AU1000_GPIO2_INTENABLE
- AU1000_GPIO2_OUTPUT
- AU1000_GPIO2_PINSTATE
- AU1000_GPIO30_INT
- AU1000_GPIO31_INT
- AU1000_GPIO3_INT
- AU1000_GPIO4_INT
- AU1000_GPIO5_INT
- AU1000_GPIO6_INT
- AU1000_GPIO7_INT
- AU1000_GPIO8_INT
- AU1000_GPIO9_INT
- AU1000_I2S_PHYS_ADDR
- AU1000_I2S_UO_INT
- AU1000_IC0_PHYS_ADDR
- AU1000_IC1_PHYS_ADDR
- AU1000_INTC0_INT_BASE
- AU1000_INTC0_INT_LAST
- AU1000_INTC1_INT_BASE
- AU1000_INTC1_INT_LAST
- AU1000_IRDA_PHYS_ADDR
- AU1000_IRDA_PHY_MODE_FIR
- AU1000_IRDA_PHY_MODE_OFF
- AU1000_IRDA_PHY_MODE_SIR
- AU1000_IRDA_RX_INT
- AU1000_IRDA_TX_INT
- AU1000_MAC0_DMA_INT
- AU1000_MAC0_PHYS_ADDR
- AU1000_MAC1_DMA_INT
- AU1000_MAC1_PHYS_ADDR
- AU1000_MACDMA0_PHYS_ADDR
- AU1000_MACDMA1_PHYS_ADDR
- AU1000_MACEN_PHYS_ADDR
- AU1000_MAX_INTR
- AU1000_MEM_PHYS_ADDR
- AU1000_MEM_SDADDR0
- AU1000_MEM_SDADDR1
- AU1000_MEM_SDADDR2
- AU1000_MEM_SDAUTOREF
- AU1000_MEM_SDMODE0
- AU1000_MEM_SDMODE1
- AU1000_MEM_SDMODE2
- AU1000_MEM_SDPRECMD
- AU1000_MEM_SDREFCFG
- AU1000_MEM_SDSLEEP
- AU1000_MEM_SDSMCKE
- AU1000_MEM_SDWRMD0
- AU1000_MEM_SDWRMD1
- AU1000_MEM_SDWRMD2
- AU1000_MEM_STADDR0
- AU1000_MEM_STADDR1
- AU1000_MEM_STADDR2
- AU1000_MEM_STADDR3
- AU1000_MEM_STCFG0
- AU1000_MEM_STCFG1
- AU1000_MEM_STCFG2
- AU1000_MEM_STCFG3
- AU1000_MEM_STNDCTL
- AU1000_MEM_STSTAT
- AU1000_MEM_STTIME0
- AU1000_MEM_STTIME1
- AU1000_MEM_STTIME2
- AU1000_MEM_STTIME3
- AU1000_OHCICFG
- AU1000_PCMCIA_ATTR_PHYS_ADDR
- AU1000_PCMCIA_IO_PHYS_ADDR
- AU1000_PCMCIA_MEM_PHYS_ADDR
- AU1000_RTC_INT
- AU1000_RTC_MATCH0_INT
- AU1000_RTC_MATCH1_INT
- AU1000_RTC_MATCH2_INT
- AU1000_SSI0_INT
- AU1000_SSI0_PHYS_ADDR
- AU1000_SSI1_INT
- AU1000_SSI1_PHYS_ADDR
- AU1000_STATIC_MEM_PHYS_ADDR
- AU1000_SYS_AUXPLL
- AU1000_SYS_CLKSRC
- AU1000_SYS_CNTRCTRL
- AU1000_SYS_CPUPLL
- AU1000_SYS_ENDIAN
- AU1000_SYS_FREQCTRL0
- AU1000_SYS_FREQCTRL1
- AU1000_SYS_OUTPUTCLR
- AU1000_SYS_OUTPUTRD
- AU1000_SYS_OUTPUTSET
- AU1000_SYS_PHYS_ADDR
- AU1000_SYS_PINFUNC
- AU1000_SYS_PININPUTEN
- AU1000_SYS_PINSTATERD
- AU1000_SYS_POWERCTRL
- AU1000_SYS_RTCMATCH0
- AU1000_SYS_RTCMATCH1
- AU1000_SYS_RTCMATCH2
- AU1000_SYS_RTCREAD
- AU1000_SYS_RTCTRIM
- AU1000_SYS_RTCWRITE
- AU1000_SYS_SCRATCH0
- AU1000_SYS_SCRATCH1
- AU1000_SYS_SLEEP
- AU1000_SYS_SLPPWR
- AU1000_SYS_TOYMATCH0
- AU1000_SYS_TOYMATCH1
- AU1000_SYS_TOYMATCH2
- AU1000_SYS_TOYREAD
- AU1000_SYS_TOYTRIM
- AU1000_SYS_TOYWRITE
- AU1000_SYS_TRIOUTCLR
- AU1000_SYS_TRIOUTRD
- AU1000_SYS_WAKEMSK
- AU1000_SYS_WAKESRC
- AU1000_TOY_INT
- AU1000_TOY_MATCH0_INT
- AU1000_TOY_MATCH1_INT
- AU1000_TOY_MATCH2_INT
- AU1000_UART0_INT
- AU1000_UART0_PHYS_ADDR
- AU1000_UART1_INT
- AU1000_UART1_PHYS_ADDR
- AU1000_UART2_INT
- AU1000_UART2_PHYS_ADDR
- AU1000_UART3_INT
- AU1000_UART3_PHYS_ADDR
- AU1000_USB_DEV_REQ_INT
- AU1000_USB_DEV_SUS_INT
- AU1000_USB_HOST_INT
- AU1000_USB_OHCI_PHYS_ADDR
- AU1000_USB_UDC_PHYS_ADDR
- AU1100FB_NBR_VIDEO_BUFFERS
- AU1100_AC97C_INT
- AU1100_ACSYNC_INT
- AU1100_DMA_INT_BASE
- AU1100_FIRST_INT
- AU1100_GPIO0_INT
- AU1100_GPIO10_INT
- AU1100_GPIO11_INT
- AU1100_GPIO12_INT
- AU1100_GPIO13_INT
- AU1100_GPIO14_INT
- AU1100_GPIO15_INT
- AU1100_GPIO16_INT
- AU1100_GPIO17_INT
- AU1100_GPIO18_INT
- AU1100_GPIO19_INT
- AU1100_GPIO1_INT
- AU1100_GPIO208_215_INT
- AU1100_GPIO20_INT
- AU1100_GPIO21_INT
- AU1100_GPIO22_INT
- AU1100_GPIO23_INT
- AU1100_GPIO24_INT
- AU1100_GPIO25_INT
- AU1100_GPIO26_INT
- AU1100_GPIO27_INT
- AU1100_GPIO28_INT
- AU1100_GPIO29_INT
- AU1100_GPIO2_INT
- AU1100_GPIO30_INT
- AU1100_GPIO31_INT
- AU1100_GPIO3_INT
- AU1100_GPIO4_INT
- AU1100_GPIO5_INT
- AU1100_GPIO6_INT
- AU1100_GPIO7_INT
- AU1100_GPIO8_INT
- AU1100_GPIO9_INT
- AU1100_IRDA_RX_INT
- AU1100_IRDA_TX_INT
- AU1100_LCD_INT
- AU1100_LCD_MAX_BPP
- AU1100_LCD_MAX_CLK
- AU1100_LCD_MAX_XRES
- AU1100_LCD_MAX_YRES
- AU1100_LCD_NBR_PALETTE_ENTRIES
- AU1100_LCD_PHYS_ADDR
- AU1100_MAC0_DMA_INT
- AU1100_MMC_DESCRIPTOR_SIZE
- AU1100_RTC_INT
- AU1100_RTC_MATCH0_INT
- AU1100_RTC_MATCH1_INT
- AU1100_RTC_MATCH2_INT
- AU1100_SD0_PHYS_ADDR
- AU1100_SD1_PHYS_ADDR
- AU1100_SD_INT
- AU1100_SSI0_INT
- AU1100_SSI1_INT
- AU1100_TOY_INT
- AU1100_TOY_MATCH0_INT
- AU1100_TOY_MATCH1_INT
- AU1100_TOY_MATCH2_INT
- AU1100_UART0_INT
- AU1100_UART1_INT
- AU1100_UART3_INT
- AU1100_USB_DEV_REQ_INT
- AU1100_USB_DEV_SUS_INT
- AU1100_USB_HOST_INT
- AU1200FB_NBR_VIDEO_BUFFERS
- AU1200FB_PMOPS
- AU1200_AES_INT
- AU1200_AES_PHYS_ADDR
- AU1200_CAMERA_INT
- AU1200_CIM_PHYS_ADDR
- AU1200_DDMA_INT
- AU1200_DSCR_CMD0_AES_RX
- AU1200_DSCR_CMD0_AES_TX
- AU1200_DSCR_CMD0_CIM_RXA
- AU1200_DSCR_CMD0_CIM_RXB
- AU1200_DSCR_CMD0_CIM_RXC
- AU1200_DSCR_CMD0_CIM_SYNC
- AU1200_DSCR_CMD0_DMA_REQ0
- AU1200_DSCR_CMD0_DMA_REQ1
- AU1200_DSCR_CMD0_LCD
- AU1200_DSCR_CMD0_MAE_BE
- AU1200_DSCR_CMD0_MAE_BOTH
- AU1200_DSCR_CMD0_MAE_FE
- AU1200_DSCR_CMD0_NAND_FLASH
- AU1200_DSCR_CMD0_PSC0_RX
- AU1200_DSCR_CMD0_PSC0_SYNC
- AU1200_DSCR_CMD0_PSC0_TX
- AU1200_DSCR_CMD0_PSC1_RX
- AU1200_DSCR_CMD0_PSC1_SYNC
- AU1200_DSCR_CMD0_PSC1_TX
- AU1200_DSCR_CMD0_SDMS_RX0
- AU1200_DSCR_CMD0_SDMS_RX1
- AU1200_DSCR_CMD0_SDMS_TX0
- AU1200_DSCR_CMD0_SDMS_TX1
- AU1200_DSCR_CMD0_UART0_RX
- AU1200_DSCR_CMD0_UART0_TX
- AU1200_DSCR_CMD0_UART1_RX
- AU1200_DSCR_CMD0_UART1_TX
- AU1200_FIRST_INT
- AU1200_GPIO0_INT
- AU1200_GPIO10_INT
- AU1200_GPIO11_INT
- AU1200_GPIO12_INT
- AU1200_GPIO13_INT
- AU1200_GPIO14_INT
- AU1200_GPIO15_INT
- AU1200_GPIO16_INT
- AU1200_GPIO17_INT
- AU1200_GPIO18_INT
- AU1200_GPIO19_INT
- AU1200_GPIO1_INT
- AU1200_GPIO200_INT
- AU1200_GPIO201_INT
- AU1200_GPIO202_INT
- AU1200_GPIO203_INT
- AU1200_GPIO204_INT
- AU1200_GPIO205_INT
- AU1200_GPIO206_INT
- AU1200_GPIO207_INT
- AU1200_GPIO208_215_INT
- AU1200_GPIO20_INT
- AU1200_GPIO21_INT
- AU1200_GPIO22_INT
- AU1200_GPIO23_INT
- AU1200_GPIO24_INT
- AU1200_GPIO25_INT
- AU1200_GPIO26_INT
- AU1200_GPIO27_INT
- AU1200_GPIO28_INT
- AU1200_GPIO29_INT
- AU1200_GPIO2_INT
- AU1200_GPIO30_INT
- AU1200_GPIO31_INT
- AU1200_GPIO3_INT
- AU1200_GPIO4_INT
- AU1200_GPIO5_INT
- AU1200_GPIO6_INT
- AU1200_GPIO7_INT
- AU1200_GPIO8_INT
- AU1200_GPIO9_INT
- AU1200_LCD_ADDR
- AU1200_LCD_FB_IOCTL
- AU1200_LCD_GET_PANEL
- AU1200_LCD_GET_SCREEN
- AU1200_LCD_GET_WINDOW
- AU1200_LCD_INT
- AU1200_LCD_MAX_BPP
- AU1200_LCD_MAX_CLK
- AU1200_LCD_MAX_XRES
- AU1200_LCD_MAX_YRES
- AU1200_LCD_NBR_PALETTE_ENTRIES
- AU1200_LCD_PHYS_ADDR
- AU1200_LCD_SET_PANEL
- AU1200_LCD_SET_SCREEN
- AU1200_LCD_SET_WINDOW
- AU1200_MAEBE_PHYS_ADDR
- AU1200_MAEFE_PHYS_ADDR
- AU1200_MAE_BE_INT
- AU1200_MAE_BOTH_INT
- AU1200_MAE_FE_INT
- AU1200_MMC_DESCRIPTOR_SIZE
- AU1200_NAND_INT
- AU1200_PSC0_INT
- AU1200_PSC1_INT
- AU1200_RTC_INT
- AU1200_RTC_MATCH0_INT
- AU1200_RTC_MATCH1_INT
- AU1200_RTC_MATCH2_INT
- AU1200_SD_INT
- AU1200_SWCNT_PHYS_ADDR
- AU1200_SWT_INT
- AU1200_TOY_INT
- AU1200_TOY_MATCH0_INT
- AU1200_TOY_MATCH1_INT
- AU1200_TOY_MATCH2_INT
- AU1200_UART0_INT
- AU1200_UART1_INT
- AU1200_USBCFG
- AU1200_USB_CTL_PHYS_ADDR
- AU1200_USB_EHCI_PHYS_ADDR
- AU1200_USB_INT
- AU1200_USB_OHCI_PHYS_ADDR
- AU1200_USB_OTG_PHYS_ADDR
- AU1200_USB_UDC_PHYS_ADDR
- AU1300_AES_INT
- AU1300_BSA_INT
- AU1300_CIM_INT
- AU1300_DDMA_INT
- AU1300_DSCR_CMD0_AES_RX
- AU1300_DSCR_CMD0_AES_TX
- AU1300_DSCR_CMD0_CIM_SYNC
- AU1300_DSCR_CMD0_DMA_REQ0
- AU1300_DSCR_CMD0_DMA_REQ1
- AU1300_DSCR_CMD0_LCD
- AU1300_DSCR_CMD0_NAND_FLASH
- AU1300_DSCR_CMD0_PSC0_RX
- AU1300_DSCR_CMD0_PSC0_TX
- AU1300_DSCR_CMD0_PSC1_RX
- AU1300_DSCR_CMD0_PSC1_TX
- AU1300_DSCR_CMD0_PSC2_RX
- AU1300_DSCR_CMD0_PSC2_TX
- AU1300_DSCR_CMD0_PSC3_RX
- AU1300_DSCR_CMD0_PSC3_TX
- AU1300_DSCR_CMD0_SDMS_RX0
- AU1300_DSCR_CMD0_SDMS_RX1
- AU1300_DSCR_CMD0_SDMS_RX2
- AU1300_DSCR_CMD0_SDMS_TX0
- AU1300_DSCR_CMD0_SDMS_TX1
- AU1300_DSCR_CMD0_SDMS_TX2
- AU1300_DSCR_CMD0_UART0_RX
- AU1300_DSCR_CMD0_UART0_TX
- AU1300_DSCR_CMD0_UART1_RX
- AU1300_DSCR_CMD0_UART1_TX
- AU1300_DSCR_CMD0_UART2_RX
- AU1300_DSCR_CMD0_UART2_TX
- AU1300_DSCR_CMD0_UART3_RX
- AU1300_DSCR_CMD0_UART3_TX
- AU1300_DSCR_CMD0_UDMA
- AU1300_FIRST_INT
- AU1300_GPIC_ADDR
- AU1300_GPIC_DEVCLR
- AU1300_GPIC_DEVSEL
- AU1300_GPIC_DMASEL
- AU1300_GPIC_IDIS
- AU1300_GPIC_IEN
- AU1300_GPIC_IPEND
- AU1300_GPIC_PHYS_ADDR
- AU1300_GPIC_PINCFG
- AU1300_GPIC_PINVAL
- AU1300_GPIC_PINVALCLR
- AU1300_GPIC_PRIENC
- AU1300_GPIC_RSTVAL
- AU1300_GPIO_BASE
- AU1300_GPIO_MAX
- AU1300_GPIO_NUM
- AU1300_GPU_INT
- AU1300_GPU_PHYS_ADDR
- AU1300_ITE_INT
- AU1300_LCD_INT
- AU1300_MAEBSA_PHYS_ADDR
- AU1300_MAEITE_PHYS_ADDR
- AU1300_MAEMPE_PHYS_ADDR
- AU1300_MMU_INT
- AU1300_MPE_INT
- AU1300_MPU_INT
- AU1300_NAND_INT
- AU1300_OTP_PHYS_ADDR
- AU1300_PIN_CIMFS
- AU1300_PIN_CIMLS
- AU1300_PIN_EXTCLK0
- AU1300_PIN_EXTCLK1
- AU1300_PIN_FG3AUX
- AU1300_PIN_LCDCLKIN
- AU1300_PIN_LCDPWM0
- AU1300_PIN_LCDPWM1
- AU1300_PIN_PCE1
- AU1300_PIN_PCE2
- AU1300_PIN_PIOR
- AU1300_PIN_PIOS16
- AU1300_PIN_PIOW
- AU1300_PIN_POE
- AU1300_PIN_PREG
- AU1300_PIN_PSC0CLK
- AU1300_PIN_PSC0D0
- AU1300_PIN_PSC0D1
- AU1300_PIN_PSC0SYNC0
- AU1300_PIN_PSC0SYNC1
- AU1300_PIN_PSC1CLK
- AU1300_PIN_PSC1D0
- AU1300_PIN_PSC1D1
- AU1300_PIN_PSC1SYNC0
- AU1300_PIN_PSC1SYNC1
- AU1300_PIN_PSC2CLK
- AU1300_PIN_PSC2D0
- AU1300_PIN_PSC2D1
- AU1300_PIN_PSC2SYNC0
- AU1300_PIN_PSC2SYNC1
- AU1300_PIN_PSC3CLK
- AU1300_PIN_PSC3D0
- AU1300_PIN_PSC3D1
- AU1300_PIN_PSC3SYNC0
- AU1300_PIN_PSC3SYNC1
- AU1300_PIN_PWAIT
- AU1300_PIN_PWE
- AU1300_PIN_SD0DAT4
- AU1300_PIN_SD0DAT5
- AU1300_PIN_SD0DAT6
- AU1300_PIN_SD0DAT7
- AU1300_PIN_SD1CLK
- AU1300_PIN_SD1CMD
- AU1300_PIN_SD1DAT0
- AU1300_PIN_SD1DAT1
- AU1300_PIN_SD1DAT2
- AU1300_PIN_SD1DAT3
- AU1300_PIN_SD2CLK
- AU1300_PIN_SD2CMD
- AU1300_PIN_SD2DAT0
- AU1300_PIN_SD2DAT1
- AU1300_PIN_SD2DAT2
- AU1300_PIN_SD2DAT3
- AU1300_PIN_U0CTS
- AU1300_PIN_U0DCD
- AU1300_PIN_U0DSR
- AU1300_PIN_U0DTR
- AU1300_PIN_U0RI
- AU1300_PIN_U0RTS
- AU1300_PIN_U1CTS
- AU1300_PIN_U1DCD
- AU1300_PIN_U1DSR
- AU1300_PIN_U1DTR
- AU1300_PIN_U1RI
- AU1300_PIN_U1RTS
- AU1300_PIN_U1RX
- AU1300_PIN_U1TX
- AU1300_PIN_U2RX
- AU1300_PIN_U2TX
- AU1300_PIN_U3RX
- AU1300_PIN_U3TX
- AU1300_PIN_WAKE0
- AU1300_PIN_WAKE1
- AU1300_PIN_WAKE2
- AU1300_PIN_WAKE3
- AU1300_PSC0_INT
- AU1300_PSC0_PHYS_ADDR
- AU1300_PSC1_INT
- AU1300_PSC1_PHYS_ADDR
- AU1300_PSC2_INT
- AU1300_PSC2_PHYS_ADDR
- AU1300_PSC3_INT
- AU1300_PSC3_PHYS_ADDR
- AU1300_ROM_PHYS_ADDR
- AU1300_RTC_INT
- AU1300_RTC_MATCH0_INT
- AU1300_RTC_MATCH1_INT
- AU1300_RTC_MATCH2_INT
- AU1300_SD0_INT
- AU1300_SD1_INT
- AU1300_SD1_PHYS_ADDR
- AU1300_SD2_INT
- AU1300_SD2_PHYS_ADDR
- AU1300_SYS_AUXPLL2
- AU1300_SYS_PHYS_ADDR
- AU1300_TOY_INT
- AU1300_TOY_MATCH0_INT
- AU1300_TOY_MATCH1_INT
- AU1300_TOY_MATCH2_INT
- AU1300_UART0_INT
- AU1300_UART0_PHYS_ADDR
- AU1300_UART1_INT
- AU1300_UART1_PHYS_ADDR
- AU1300_UART2_INT
- AU1300_UART2_PHYS_ADDR
- AU1300_UART3_INT
- AU1300_UART3_PHYS_ADDR
- AU1300_UDMA_INT
- AU1300_UDMA_PHYS_ADDR
- AU1300_USB_CTL_PHYS_ADDR
- AU1300_USB_EHCI_PHYS_ADDR
- AU1300_USB_INT
- AU1300_USB_OHCI0_PHYS_ADDR
- AU1300_USB_OHCI1_PHYS_ADDR
- AU1300_USB_OTG_PHYS_ADDR
- AU1300_VSS_BSA
- AU1300_VSS_GPE
- AU1300_VSS_MGP
- AU1300_VSS_MPE
- AU1300_VSS_PHYS_ADDR
- AU1500_AC97C_INT
- AU1500_ACSYNC_INT
- AU1500_DMA_INT_BASE
- AU1500_FIRST_INT
- AU1500_GPIO0_INT
- AU1500_GPIO10_INT
- AU1500_GPIO11_INT
- AU1500_GPIO12_INT
- AU1500_GPIO13_INT
- AU1500_GPIO14_INT
- AU1500_GPIO15_INT
- AU1500_GPIO1_INT
- AU1500_GPIO200_INT
- AU1500_GPIO201_INT
- AU1500_GPIO202_INT
- AU1500_GPIO203_INT
- AU1500_GPIO204_INT
- AU1500_GPIO205_INT
- AU1500_GPIO206_INT
- AU1500_GPIO207_INT
- AU1500_GPIO208_215_INT
- AU1500_GPIO20_INT
- AU1500_GPIO23_INT
- AU1500_GPIO24_INT
- AU1500_GPIO25_INT
- AU1500_GPIO26_INT
- AU1500_GPIO27_INT
- AU1500_GPIO28_INT
- AU1500_GPIO2_INT
- AU1500_GPIO2_PHYS_ADDR
- AU1500_GPIO3_INT
- AU1500_GPIO4_INT
- AU1500_GPIO5_INT
- AU1500_GPIO6_INT
- AU1500_GPIO7_INT
- AU1500_GPIO8_INT
- AU1500_GPIO9_INT
- AU1500_MAC0_DMA_INT
- AU1500_MAC0_PHYS_ADDR
- AU1500_MAC1_DMA_INT
- AU1500_MAC1_PHYS_ADDR
- AU1500_MACEN_PHYS_ADDR
- AU1500_PCI_CONFIG0_PHYS_ADDR
- AU1500_PCI_CONFIG1_PHYS_ADDR
- AU1500_PCI_ERR_INT
- AU1500_PCI_INTA
- AU1500_PCI_INTB
- AU1500_PCI_INTC
- AU1500_PCI_INTD
- AU1500_PCI_IO_PHYS_ADDR
- AU1500_PCI_MEM_PHYS_ADDR
- AU1500_PCI_PHYS_ADDR
- AU1500_RESERVED_INT
- AU1500_RTC_INT
- AU1500_RTC_MATCH0_INT
- AU1500_RTC_MATCH1_INT
- AU1500_RTC_MATCH2_INT
- AU1500_TOY_INT
- AU1500_TOY_MATCH0_INT
- AU1500_TOY_MATCH1_INT
- AU1500_TOY_MATCH2_INT
- AU1500_UART0_INT
- AU1500_UART3_INT
- AU1500_USB_DEV_REQ_INT
- AU1500_USB_DEV_SUS_INT
- AU1500_USB_HOST_INT
- AU1550_CRYPTO_INT
- AU1550_DBDMA_CONF_PHYS_ADDR
- AU1550_DBDMA_PHYS_ADDR
- AU1550_DDMA_INT
- AU1550_DSCR_CMD0_DMA_REQ0
- AU1550_DSCR_CMD0_DMA_REQ1
- AU1550_DSCR_CMD0_DMA_REQ2
- AU1550_DSCR_CMD0_DMA_REQ3
- AU1550_DSCR_CMD0_MAC0_RX
- AU1550_DSCR_CMD0_MAC0_TX
- AU1550_DSCR_CMD0_MAC1_RX
- AU1550_DSCR_CMD0_MAC1_TX
- AU1550_DSCR_CMD0_NAND_FLASH
- AU1550_DSCR_CMD0_PCI_WRITE
- AU1550_DSCR_CMD0_PSC0_RX
- AU1550_DSCR_CMD0_PSC0_TX
- AU1550_DSCR_CMD0_PSC1_RX
- AU1550_DSCR_CMD0_PSC1_TX
- AU1550_DSCR_CMD0_PSC2_RX
- AU1550_DSCR_CMD0_PSC2_TX
- AU1550_DSCR_CMD0_PSC3_RX
- AU1550_DSCR_CMD0_PSC3_TX
- AU1550_DSCR_CMD0_UART0_RX
- AU1550_DSCR_CMD0_UART0_TX
- AU1550_DSCR_CMD0_UART3_RX
- AU1550_DSCR_CMD0_UART3_TX
- AU1550_DSCR_CMD0_USBDEV_RX0
- AU1550_DSCR_CMD0_USBDEV_RX3
- AU1550_DSCR_CMD0_USBDEV_RX4
- AU1550_DSCR_CMD0_USBDEV_TX0
- AU1550_DSCR_CMD0_USBDEV_TX1
- AU1550_DSCR_CMD0_USBDEV_TX2
- AU1550_FIRST_INT
- AU1550_GPIO0_INT
- AU1550_GPIO10_INT
- AU1550_GPIO11_INT
- AU1550_GPIO12_INT
- AU1550_GPIO13_INT
- AU1550_GPIO14_INT
- AU1550_GPIO15_INT
- AU1550_GPIO16_INT
- AU1550_GPIO17_INT
- AU1550_GPIO1_INT
- AU1550_GPIO200_INT
- AU1550_GPIO201_205_INT
- AU1550_GPIO206_INT
- AU1550_GPIO207_INT
- AU1550_GPIO208_215_INT
- AU1550_GPIO20_INT
- AU1550_GPIO21_INT
- AU1550_GPIO22_INT
- AU1550_GPIO23_INT
- AU1550_GPIO24_INT
- AU1550_GPIO25_INT
- AU1550_GPIO26_INT
- AU1550_GPIO27_INT
- AU1550_GPIO28_INT
- AU1550_GPIO2_INT
- AU1550_GPIO3_INT
- AU1550_GPIO4_INT
- AU1550_GPIO5_INT
- AU1550_GPIO6_INT
- AU1550_GPIO7_INT
- AU1550_GPIO8_INT
- AU1550_GPIO9_INT
- AU1550_MAC0_DMA_INT
- AU1550_MAC1_DMA_INT
- AU1550_MEM_SDADDR0
- AU1550_MEM_SDADDR1
- AU1550_MEM_SDADDR2
- AU1550_MEM_SDAUTOREF
- AU1550_MEM_SDCONFIGA
- AU1550_MEM_SDCONFIGB
- AU1550_MEM_SDERRADDR
- AU1550_MEM_SDMODE0
- AU1550_MEM_SDMODE1
- AU1550_MEM_SDMODE2
- AU1550_MEM_SDPRECMD
- AU1550_MEM_SDSLEEP
- AU1550_MEM_SDSREF
- AU1550_MEM_SDSTAT
- AU1550_MEM_SDSTRIDE0
- AU1550_MEM_SDSTRIDE1
- AU1550_MEM_SDSTRIDE2
- AU1550_MEM_SDWRMD0
- AU1550_MEM_SDWRMD1
- AU1550_MEM_SDWRMD2
- AU1550_NAND_INT
- AU1550_OHCICFG
- AU1550_PCI_INTA
- AU1550_PCI_INTB
- AU1550_PCI_INTC
- AU1550_PCI_INTD
- AU1550_PCI_RST_INT
- AU1550_PE_PHYS_ADDR
- AU1550_PSC0_INT
- AU1550_PSC0_PHYS_ADDR
- AU1550_PSC1_INT
- AU1550_PSC1_PHYS_ADDR
- AU1550_PSC2_INT
- AU1550_PSC2_PHYS_ADDR
- AU1550_PSC3_INT
- AU1550_PSC3_PHYS_ADDR
- AU1550_RTC_INT
- AU1550_RTC_MATCH0_INT
- AU1550_RTC_MATCH1_INT
- AU1550_RTC_MATCH2_INT
- AU1550_SPI_DBDMA_DESCRIPTORS
- AU1550_SPI_DMA_RXTMP_MINSIZE
- AU1550_SPI_RX_WORD
- AU1550_SPI_TX_WORD
- AU1550_TOY_INT
- AU1550_TOY_MATCH0_INT
- AU1550_TOY_MATCH1_INT
- AU1550_TOY_MATCH2_INT
- AU1550_UART0_INT
- AU1550_UART1_INT
- AU1550_UART3_INT
- AU1550_USB_DEV_REQ_INT
- AU1550_USB_DEV_SUS_INT
- AU1550_USB_HOST_INT
- AU1550_USB_OHCI_PHYS_ADDR
- AU1XI2SC_FMTS
- AU1XI2SC_PMOPS
- AU1XI2SC_RATES
- AU1XMMC_DESCRIPTOR_COUNT
- AU1XMMC_DETECT_TIMEOUT
- AU1XMMC_INTERRUPTS
- AU1XMMC_MAX_TRANSFER
- AU1XMMC_OCR
- AU1XPSCAC97_PMOPS
- AU1XPSCI2S_PMOPS
- AU1XPSC_BUFFER_MIN_BYTES
- AU1XPSC_I2S_DAIFMT
- AU1XPSC_I2S_DIR
- AU1XPSC_I2S_FMTS
- AU1XPSC_I2S_RATES
- AU1XPSC_PERIOD_MIN_BYTES
- AU1XPSC_SMBUS_PMOPS
- AU1XXX_ATA_RQSIZE
- AU1_GPIO_SEL
- AU1_SPDIFO_GPIO_EN
- AU6601_ACTIVE_CTRL
- AU6601_BASE_CLOCK
- AU6601_BUF_CTRL_RESET
- AU6601_BUS_STAT_CMD
- AU6601_BUS_STAT_DAT0
- AU6601_BUS_STAT_DAT1
- AU6601_BUS_STAT_DAT2
- AU6601_BUS_STAT_DAT3
- AU6601_BUS_STAT_DAT_MASK
- AU6601_BUS_WIDTH_1BIT
- AU6601_BUS_WIDTH_4BIT
- AU6601_BUS_WIDTH_8BIT
- AU6601_CLK_125_MHZ
- AU6601_CLK_31_25_MHZ
- AU6601_CLK_384_MHZ
- AU6601_CLK_48_MHZ
- AU6601_CLK_CMD_POSITIVE_EDGE
- AU6601_CLK_DATA_POSITIVE_EDGE
- AU6601_CLK_DELAY
- AU6601_CLK_DIVIDER
- AU6601_CLK_ENABLE
- AU6601_CLK_EXT_PLL
- AU6601_CLK_OVER_CLK
- AU6601_CLK_POSITIVE_EDGE_ALL
- AU6601_CLK_SELECT
- AU6601_CLK_X2_MODE
- AU6601_CMD_17_BYTE_CRC
- AU6601_CMD_6_BYTE_CRC
- AU6601_CMD_6_BYTE_WO_CRC
- AU6601_CMD_NO_RESP
- AU6601_CMD_START_XFER
- AU6601_CMD_STOP_WAIT_RDY
- AU6601_CMD_XFER_CTRL
- AU6601_DATA_DMA_MODE
- AU6601_DATA_PIN_STATE
- AU6601_DATA_START_XFER
- AU6601_DATA_WRITE
- AU6601_DATA_XFER_CTRL
- AU6601_DETECT_EN
- AU6601_DETECT_STATUS
- AU6601_DETECT_STATUS_M
- AU6601_DLINK_MODE
- AU6601_DMA_BOUNDARY
- AU6601_DMA_LOCAL_SEGMENTS
- AU6601_FUNCTION
- AU6601_INTERFACE_MODE_CTRL
- AU6601_INTERRUPT_DELAY_TIME
- AU6601_INT_ALL_MASK
- AU6601_INT_CARD_INSERT
- AU6601_INT_CARD_REMOVE
- AU6601_INT_CMD_CRC_ERR
- AU6601_INT_CMD_END
- AU6601_INT_CMD_END_BIT_ERR
- AU6601_INT_CMD_INDEX_ERR
- AU6601_INT_CMD_MASK
- AU6601_INT_CMD_TIMEOUT_ERR
- AU6601_INT_DATA_CRC_ERR
- AU6601_INT_DATA_END
- AU6601_INT_DATA_END_BIT_ERR
- AU6601_INT_DATA_MASK
- AU6601_INT_DATA_TIMEOUT_ERR
- AU6601_INT_DMA_END
- AU6601_INT_ERROR
- AU6601_INT_ERROR_MASK
- AU6601_INT_NORMAL_MASK
- AU6601_INT_OVER_CURRENT_ERR
- AU6601_INT_READ_BUF_RDY
- AU6601_INT_WRITE_BUF_RDY
- AU6601_MAX_CLOCK
- AU6601_MAX_DMA_BLOCKS
- AU6601_MAX_DMA_BLOCK_SIZE
- AU6601_MAX_DMA_SEGMENTS
- AU6601_MAX_PIO_BLOCK_SIZE
- AU6601_MAX_PIO_SEGMENTS
- AU6601_MIN_CLOCK
- AU6601_MS_BUS_1BIT_MODE
- AU6601_MS_BUS_4BIT_MODE
- AU6601_MS_BUS_8BIT_MODE
- AU6601_MS_BUS_MODE_CTRL
- AU6601_MS_CARD
- AU6601_MS_CARD_WP
- AU6601_MS_DATA_PIN_STATE
- AU6601_MS_DETECTED
- AU6601_MS_INT_BUF_READ_RDY
- AU6601_MS_INT_BUF_WRITE_RDY
- AU6601_MS_INT_CARD_INSERT
- AU6601_MS_INT_CARD_REMOVE
- AU6601_MS_INT_CED_ERROR
- AU6601_MS_INT_DATA_CRC_ERROR
- AU6601_MS_INT_DATA_MASK
- AU6601_MS_INT_DMA_END
- AU6601_MS_INT_ENABLE
- AU6601_MS_INT_ERROR
- AU6601_MS_INT_INT_RESP_ERROR
- AU6601_MS_INT_INT_TIMEOUT
- AU6601_MS_INT_OVER_CURRENT_ERROR
- AU6601_MS_INT_STATUS
- AU6601_MS_INT_TPC_END
- AU6601_MS_INT_TPC_ERROR
- AU6601_MS_INT_TPC_MASK
- AU6601_MS_INT_TPC_TIMEOUT
- AU6601_MS_STATUS
- AU6601_MS_TPC_CMD
- AU6601_MS_TPC_EX_SET_CMD
- AU6601_MS_TPC_GET_INT
- AU6601_MS_TPC_READ_PAGE_DATA
- AU6601_MS_TPC_READ_REG
- AU6601_MS_TPC_READ_SHORT_DATA
- AU6601_MS_TPC_SET_CMD
- AU6601_MS_TPC_SET_RW_REG_ADRS
- AU6601_MS_TPC_WRITE_PAGE_DATA
- AU6601_MS_TPC_WRITE_REG
- AU6601_MS_TPC_WRITE_SHORT_DATA
- AU6601_MS_TRANSFER_MODE
- AU6601_MS_XFER_DMA_ENABLE
- AU6601_MS_XFER_INT_TIMEOUT_CHK
- AU6601_MS_XFER_START
- AU6601_OPT
- AU6601_OPT_CMD_LINE_LEVEL
- AU6601_OPT_CMD_NWT
- AU6601_OPT_DDR_MODE
- AU6601_OPT_NCRC_16_CLK
- AU6601_OPT_SD_18V
- AU6601_OPT_STOP_CLK
- AU6601_OUTPUT_ENABLE
- AU6601_PAD_DRIVE0
- AU6601_PAD_DRIVE1
- AU6601_PAD_DRIVE2
- AU6601_POWER_CONTROL
- AU6601_REG_BLOCK_SIZE
- AU6601_REG_BUFFER
- AU6601_REG_BUS_CTRL
- AU6601_REG_CMD_ARG
- AU6601_REG_CMD_OPCODE
- AU6601_REG_CMD_RSP0
- AU6601_REG_CMD_RSP1
- AU6601_REG_CMD_RSP2
- AU6601_REG_CMD_RSP3
- AU6601_REG_INT_ENABLE
- AU6601_REG_INT_STATUS
- AU6601_REG_SDMA_ADDR
- AU6601_REG_SW_RESET
- AU6601_RESET_CMD
- AU6601_RESET_DATA
- AU6601_SDMA_MASK
- AU6601_SD_CARD
- AU6601_SD_CARD_WP
- AU6601_SD_DETECTED
- AU6601_SIGNAL_REQ_CTRL
- AU6601_TIME_OUT_CTRL
- AU6601_XD_CARD
- AU6610_H
- AU6610_REQ_I2C_READ
- AU6610_REQ_I2C_WRITE
- AU6610_REQ_USB_READ
- AU6610_REQ_USB_WRITE
- AU6610_USB_TIMEOUT
- AU6621_DMA_CTRL
- AU6621_DMA_ENABLE
- AU6621_DMA_PAGE_CNT
- AU8522_AGC_CONTROL_RANGE_REG0A6H
- AU8522_ANALOG_MODE
- AU8522_AUDIOAGC2_REG605H
- AU8522_AUDIOAGC_REG0EEH
- AU8522_AUDIOFREQ_REG606H
- AU8522_AUDIO_MODE_REG0F1H
- AU8522_AUDIO_NONE
- AU8522_AUDIO_SIF
- AU8522_AUDIO_STATUS_REG0F0H
- AU8522_AUDIO_VOLUME_L_REG0F2H
- AU8522_AUDIO_VOLUME_REG0F4H
- AU8522_AUDIO_VOLUME_R_REG0F3H
- AU8522_CARRFREQOFFSET0_REG201H
- AU8522_CARRFREQOFFSET1_REG202H
- AU8522_CHIP_MODE_REG0FEH
- AU8522_CLAMPING_CONTROL_REG083H
- AU8522_COMPOSITE_CH1
- AU8522_COMPOSITE_CH2
- AU8522_COMPOSITE_CH3
- AU8522_COMPOSITE_CH4
- AU8522_COMPOSITE_CH4_SIF
- AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH
- AU8522_DECIMATION_GAIN_REG21AH
- AU8522_DEMODLOCKING
- AU8522_DEMODULATION_STATUS_REG088H
- AU8522_DFE_AVERAGE_REG302H
- AU8522_DIGITAL_MODE
- AU8522_ENA_USB_REG101H
- AU8522_FILTER_COEF_R410
- AU8522_FILTER_COEF_R411
- AU8522_FILTER_COEF_R412
- AU8522_FILTER_COEF_R413
- AU8522_FILTER_COEF_R414
- AU8522_FILTER_COEF_R415
- AU8522_FILTER_COEF_R416
- AU8522_FILTER_COEF_R417
- AU8522_FILTER_COEF_R418
- AU8522_FILTER_COEF_R419
- AU8522_FILTER_COEF_R41A
- AU8522_FILTER_COEF_R41B
- AU8522_FILTER_COEF_R41C
- AU8522_FILTER_COEF_R41D
- AU8522_FILTER_COEF_R41E
- AU8522_FILTER_COEF_R41F
- AU8522_FILTER_COEF_R420
- AU8522_FILTER_COEF_R421
- AU8522_FILTER_COEF_R422
- AU8522_FILTER_COEF_R423
- AU8522_FILTER_COEF_R424
- AU8522_FILTER_COEF_R425
- AU8522_FILTER_COEF_R426
- AU8522_FILTER_COEF_R427
- AU8522_FILTER_COEF_R428
- AU8522_FILTER_COEF_R429
- AU8522_FILTER_COEF_R42A
- AU8522_FILTER_COEF_R42B
- AU8522_FILTER_COEF_R42C
- AU8522_FILTER_COEF_R42D
- AU8522_FRAME_COUNT0_REG084H
- AU8522_FRMREGAGC1H_REG0B1H
- AU8522_FRMREGAGC2H_REG0D9H
- AU8522_FRMREGAUPHASE_REG0F7H
- AU8522_FRMREGBBH_REG0B5H
- AU8522_FRMREGBBL_REG0B7H
- AU8522_FRMREGBBM_REG0B6H
- AU8522_FRMREGCRLOCK0THH_REG223H
- AU8522_FRMREGCRLOCK0THL_REG225H
- AU8522_FRMREGCRLOCK1THH_REG224H
- AU8522_FRMREGCRLOCK1THL_REG226H
- AU8522_FRMREGCRLOCKDMAX_REG221H
- AU8522_FRMREGCRPERIODMASK_REG222H
- AU8522_FRMREGCSTHRD_REG220H
- AU8522_FRMREGDFECONTROL1_REG305H
- AU8522_FRMREGDFECONTROL_REG122H
- AU8522_FRMREGDFEKEEP_REG301H
- AU8522_FRMREGEQLERRLOW_REG306H
- AU8522_FRMREGEQLERRWIN_REG303H
- AU8522_FRMREGFFECONTROL_REG121H
- AU8522_FRMREGFFEKEEP_REG304H
- AU8522_FRMREGFREQFBCTRL_REG228H
- AU8522_FRMREGIFSLP_REG21BH
- AU8522_FRMREGPILOTH_REG0DCH
- AU8522_FRMREGPILOTL_REG0DEH
- AU8522_FRMREGPILOTM_REG0DDH
- AU8522_FRMREGPLLMODE_REG21FH
- AU8522_FRMREGSHIFT1_REG0B2H
- AU8522_FRMREGSTEP3DB_REG21DH
- AU8522_FRMREGTHRD1_REG0B0H
- AU8522_FRMREGTHRD2_REG0D8H
- AU8522_FRMREGTHRDL2_REG21CH
- AU8522_GPIO_CONTROL_REG0E0H
- AU8522_GPIO_DATA_REG0E2H
- AU8522_GPIO_STATUS_REG0E1H
- AU8522_I2C_CONTROL_REG0_REG090H
- AU8522_I2C_CONTROL_REG1_REG091H
- AU8522_I2C_RD_DATA0_REG09BH
- AU8522_I2C_RD_DATA1_REG09CH
- AU8522_I2C_RD_DATA2_REG09DH
- AU8522_I2C_RD_DATA3_REG09EH
- AU8522_I2C_RD_DATA4_REG09FH
- AU8522_I2C_RD_DATA5_REG0A0H
- AU8522_I2C_RD_DATA6_REG0A1H
- AU8522_I2C_RD_DATA7_REG0A2H
- AU8522_I2C_STATUS_REG092H
- AU8522_I2C_WR_DATA0_REG093H
- AU8522_I2C_WR_DATA1_REG094H
- AU8522_I2C_WR_DATA2_REG095H
- AU8522_I2C_WR_DATA3_REG096H
- AU8522_I2C_WR_DATA4_REG097H
- AU8522_I2C_WR_DATA5_REG098H
- AU8522_I2C_WR_DATA6_REG099H
- AU8522_I2C_WR_DATA7_REG09AH
- AU8522_I2S_CTRL_0_REG110H
- AU8522_I2S_CTRL_1_REG111H
- AU8522_I2S_CTRL_2_REG112H
- AU8522_IF_3_25MHZ
- AU8522_IF_4MHZ
- AU8522_IF_6MHZ
- AU8522_INPUT_CONTROL_REG081H
- AU8522_INPUT_CONTROL_REG081H_ATSC
- AU8522_INPUT_CONTROL_REG081H_ATVRF
- AU8522_INPUT_CONTROL_REG081H_ATVRF13
- AU8522_INPUT_CONTROL_REG081H_CVBS
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH1
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH2
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH3
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH4
- AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF
- AU8522_INPUT_CONTROL_REG081H_J83B256
- AU8522_INPUT_CONTROL_REG081H_J83B64
- AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13
- AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64
- AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO
- AU8522_NUM_PADS
- AU8522_PAD_AUDIO_OUT
- AU8522_PAD_IF_INPUT
- AU8522_PAD_VID_OUT
- AU8522_PGA_CONTROL_REG082H
- AU8522_REG016H
- AU8522_REG016H_CVBS
- AU8522_REG071H
- AU8522_REG071H_CVBS
- AU8522_REG072H
- AU8522_REG072H_CVBS
- AU8522_REG074H
- AU8522_REG074H_CVBS
- AU8522_REG075H
- AU8522_REG075H_CVBS
- AU8522_REG0F9H
- AU8522_REG0F9H_AUDIO
- AU8522_REG42EH
- AU8522_REG42FH
- AU8522_REG430H
- AU8522_REG431H
- AU8522_REG432H
- AU8522_REG433H
- AU8522_REG434H
- AU8522_REG435H
- AU8522_REG436H
- AU8522_RS_STATUS_B0_REG086H
- AU8522_RS_STATUS_E_REG087H
- AU8522_RS_STATUS_G0_REG085H
- AU8522_RX_PGA_IFOUT_REG0ECH
- AU8522_RX_PGA_PGAOUT_REG0EDH
- AU8522_RX_PGA_RFOUT_REG0EBH
- AU8522_SUSPEND_MODE
- AU8522_SVIDEO_CH13
- AU8522_SVIDEO_CH24
- AU8522_SYSTEM_GAIN_CONTROL_REG0A7H
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL
- AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM
- AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO
- AU8522_TOREGAAGC_REG0E5H
- AU8522_TOREGAAGC_REG0E5H_CVBS
- AU8522_TOREGAGC1_REG0B3H
- AU8522_TOREGAGC2_REG0DAH
- AU8522_TOREGASHIFT1_REG0B4H
- AU8522_TOREGFREQ_REG0DFH
- AU8522_TOREGSHIFT2_REG0DBH
- AU8522_TOREGTRESTATUS_REG0E6H
- AU8522_TSPORT_CONTROL_REG10BH
- AU8522_TSTHES_REG10CH
- AU8522_TUNERLOCKING
- AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH
- AU8522_TUNER_AGC_IF_START_REG0ACH
- AU8522_TUNER_AGC_IF_STOP_REG0ABH
- AU8522_TUNER_AGC_RF_START_REG0A9H
- AU8522_TUNER_AGC_RF_STOP_REG0A8H
- AU8522_TUNER_AGC_STEP_REG0AEH
- AU8522_TUNER_GAIN_STEP_REG0AFH
- AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH
- AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H
- AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS
- AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H
- AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS
- AU8522_TVDEC_BRIGHTNESS_REG00AH
- AU8522_TVDEC_CHROMA_AGC_REG401H
- AU8522_TVDEC_CHROMA_SFT_REG402H
- AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH
- AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS
- AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO
- AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH
- AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS
- AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO
- AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH
- AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS
- AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H
- AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS
- AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H
- AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS
- AU8522_TVDEC_COMB_HDIF_THR1_REG069H
- AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS
- AU8522_TVDEC_COMB_HDIF_THR2_REG06AH
- AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS
- AU8522_TVDEC_COMB_HDIF_THR3_REG06BH
- AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS
- AU8522_TVDEC_COMB_MODE_REG015H
- AU8522_TVDEC_COMB_MODE_REG015H_CVBS
- AU8522_TVDEC_COMB_NOTCH_THR_REG068H
- AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS
- AU8522_TVDEC_COMB_VDIF_THR1_REG065H
- AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS
- AU8522_TVDEC_COMB_VDIF_THR2_REG066H
- AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS
- AU8522_TVDEC_COMB_VDIF_THR3_REG067H
- AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS
- AU8522_TVDEC_CONTRAST_REG00BH
- AU8522_TVDEC_CONTRAST_REG00BH_CVBS
- AU8522_TVDEC_DCAGC_CTRL_REG077H
- AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS
- AU8522_TVDEC_FORMAT_CTRL1_REG061H
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO
- AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES
- AU8522_TVDEC_FORMAT_CTRL2_REG062H
- AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT
- AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC
- AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M
- AU8522_TVDEC_FSC_FREQ_REG07FH
- AU8522_TVDEC_HUE_H_REG00EH
- AU8522_TVDEC_HUE_H_REG00EH_CVBS
- AU8522_TVDEC_HUE_L_REG00FH
- AU8522_TVDEC_HUE_L_REG00FH_CVBS
- AU8522_TVDEC_INTRP_CTRL_REG07BH
- AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS
- AU8522_TVDEC_INT_MASK_REG010H
- AU8522_TVDEC_INT_STATUS_REG001H
- AU8522_TVDEC_MACROVISION_STATUS_REG002H
- AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH
- AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS
- AU8522_TVDEC_PGA_REG012H
- AU8522_TVDEC_PGA_REG012H_CVBS
- AU8522_TVDEC_PIC_START_ADJ_REG078H
- AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS
- AU8522_TVDEC_PLL_STATUS_REG07EH
- AU8522_TVDEC_SATURATION_CB_REG00CH
- AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS
- AU8522_TVDEC_SATURATION_CR_REG00DH
- AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS
- AU8522_TVDEC_SHARPNESSREG009H
- AU8522_TVDEC_STATUS_REG000H
- AU8522_TVDEC_UV_SEP_THR_REG06FH
- AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS
- AU8522_TVDEC_VBI6A_REG035H_CVBS
- AU8522_TVDEC_VBI_CTRL_H_REG017H
- AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON
- AU8522_TVDEC_VBI_CTRL_L_REG018H
- AU8522_TVDEC_VBI_FIFO_STATUS_REG007H
- AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H
- AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H
- AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H
- AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H
- AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H
- AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H
- AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H
- AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH
- AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH
- AU8522_TVDEC_VBI_USER_THRESH1_REG01CH
- AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H
- AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH
- AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH
- AU8522_TVDEC_VCR_DET_HLIM_REG064H
- AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS
- AU8522_TVDEC_VCR_DET_LLIM_REG063H
- AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS
- AU8522_TVDED_DBG_MODE_REG060H
- AU8522_TVDED_DBG_MODE_REG060H_CVBS
- AU8522_UNIT
- AU8522_VIDEO_MODE_REG011H
- AU88X0_EQ_H
- AUART0_CTS
- AUART0_RTS
- AUART0_RX
- AUART0_TX
- AUART1_CTS
- AUART1_RTS
- AUART1_RX
- AUART1_TX
- AUART2_CTS
- AUART2_RTS
- AUART2_RX
- AUART2_TX
- AUART3_CTS
- AUART3_RTS
- AUART3_RX
- AUART3_TX
- AUART_AUTOBAUD
- AUART_CTRL0
- AUART_CTRL0_CLKGATE
- AUART_CTRL0_RXTIMEOUT
- AUART_CTRL0_RXTO_ENABLE
- AUART_CTRL0_SFTRST
- AUART_CTRL0_XFER_COUNT
- AUART_CTRL1
- AUART_CTRL1_XFER_COUNT
- AUART_CTRL2
- AUART_CTRL2_CTSEN
- AUART_CTRL2_DMAONERR
- AUART_CTRL2_RTS
- AUART_CTRL2_RTSEN
- AUART_CTRL2_RXDMAE
- AUART_CTRL2_RXE
- AUART_CTRL2_TXDMAE
- AUART_CTRL2_TXE
- AUART_CTRL2_UARTEN
- AUART_DATA
- AUART_DEBUG
- AUART_INTR
- AUART_INTR_CTSMIEN
- AUART_INTR_CTSMIS
- AUART_INTR_RTIEN
- AUART_INTR_RTIS
- AUART_INTR_RXIEN
- AUART_INTR_RXIS
- AUART_INTR_TXIEN
- AUART_INTR_TXIS
- AUART_LINECTRL
- AUART_LINECTRL2
- AUART_LINECTRL_BAUD_DIVFRAC
- AUART_LINECTRL_BAUD_DIVFRAC_MASK
- AUART_LINECTRL_BAUD_DIVFRAC_SHIFT
- AUART_LINECTRL_BAUD_DIVINT
- AUART_LINECTRL_BAUD_DIVINT_MASK
- AUART_LINECTRL_BAUD_DIVINT_SHIFT
- AUART_LINECTRL_BAUD_DIV_MAX
- AUART_LINECTRL_BAUD_DIV_MIN
- AUART_LINECTRL_BRK
- AUART_LINECTRL_EPS
- AUART_LINECTRL_FEN
- AUART_LINECTRL_PEN
- AUART_LINECTRL_SPS
- AUART_LINECTRL_STP2
- AUART_LINECTRL_WLEN
- AUART_LINECTRL_WLEN_MASK
- AUART_STAT
- AUART_STAT_BERR
- AUART_STAT_BUSY
- AUART_STAT_CTS
- AUART_STAT_FERR
- AUART_STAT_OERR
- AUART_STAT_PERR
- AUART_STAT_RXCOUNT_MASK
- AUART_STAT_RXFE
- AUART_STAT_TXFE
- AUART_STAT_TXFF
- AUART_VERSION
- AUBURN_EEPROM_CLK_FALL
- AUBURN_EEPROM_CLK_RISE
- AUBURN_EEPROM_CS
- AUBURN_EEPROM_CS_0
- AUBURN_EEPROM_CS_1
- AUBURN_EEPROM_DI
- AUBURN_EEPROM_DI_0
- AUBURN_EEPROM_DI_1
- AUBURN_EEPROM_DO
- AUBURN_EEPROM_DO_0
- AUBURN_EEPROM_DO_1
- AUD0_REGISTER_OFFSET
- AUD1_REGISTER_OFFSET
- AUD2_REGISTER_OFFSET
- AUD3_REGISTER_OFFSET
- AUD4_REGISTER_OFFSET
- AUD5_REGISTER_OFFSET
- AUD6_REGISTER_OFFSET
- AUD7_REGISTER_OFFSET
- AUD96P22_FORMATS
- AUD96P22_HS1VOL_0
- AUD96P22_HS1VOL_1
- AUD96P22_I2S1_CONFIG_0
- AUD96P22_LDR1SEL_0
- AUD96P22_LDR1SEL_1
- AUD96P22_LDR2SEL_0
- AUD96P22_LMVOL_0
- AUD96P22_LMVOL_1
- AUD96P22_MUTE_0
- AUD96P22_MUTE_2
- AUD96P22_MUTE_4
- AUD96P22_PD_0
- AUD96P22_PD_1
- AUD96P22_PD_3
- AUD96P22_PD_4
- AUD96P22_PGA1SEL_0
- AUD96P22_PGA1SEL_1
- AUD96P22_PGA1VOL_0
- AUD96P22_PGA1VOL_1
- AUD96P22_RATES
- AUD96P22_RECVOL_0
- AUD96P22_RECVOL_1
- AUD96P22_REG_MAX
- AUD96P22_RESET
- AUDADCLPWRUP_PERIODIC_INVERSE_MASK
- AUDADCLPWRUP_PERIODIC_INVERSE_MASK_SFT
- AUDADCLPWRUP_PERIODIC_INVERSE_SFT
- AUDADCLPWRUP_PERIODIC_MODE_MASK
- AUDADCLPWRUP_PERIODIC_MODE_MASK_SFT
- AUDADCLPWRUP_PERIODIC_MODE_SFT
- AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK
- AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDADCLPWRUP_PERIODIC_OFF_CYCLE_SFT
- AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK
- AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK_SFT
- AUDADCLPWRUP_PERIODIC_ON_CYCLE_SFT
- AUDATA0
- AUDATA0_MARK
- AUDATA1
- AUDATA1_MARK
- AUDATA2
- AUDATA2_MARK
- AUDATA3
- AUDATA3_MARK
- AUDATA4_MARK
- AUDATA5_MARK
- AUDATA6_MARK
- AUDATA7_MARK
- AUDCFG_AUTO_MUTE_EN
- AUDCFG_BUS_I2S
- AUDCFG_BUS_SHIFT
- AUDCFG_BUS_SPDIF
- AUDCFG_CLK_INVERT
- AUDCFG_HBR_DEMUX
- AUDCFG_HBR_SHIFT
- AUDCFG_HBR_STRAIGHT
- AUDCFG_I2SW_16
- AUDCFG_I2SW_32
- AUDCFG_I2SW_SHIFT
- AUDCFG_TEST_TONE
- AUDCFG_TYPE_DST
- AUDCFG_TYPE_HBR
- AUDCFG_TYPE_MASK
- AUDCFG_TYPE_OBA
- AUDCFG_TYPE_PCM
- AUDCFG_TYPE_SHIFT
- AUDCK_MARK
- AUDDEC_ANA_ID_MASK
- AUDDEC_ANA_ID_MASK_SFT
- AUDDEC_ANA_ID_SFT
- AUDDEC_ANA_MAJOR_REV_MASK
- AUDDEC_ANA_MAJOR_REV_MASK_SFT
- AUDDEC_ANA_MAJOR_REV_SFT
- AUDDEC_ANA_MINOR_REV_MASK
- AUDDEC_ANA_MINOR_REV_MASK_SFT
- AUDDEC_ANA_MINOR_REV_SFT
- AUDDEC_DIG_ID_MASK
- AUDDEC_DIG_ID_MASK_SFT
- AUDDEC_DIG_ID_SFT
- AUDDEC_DIG_MAJOR_REV_MASK
- AUDDEC_DIG_MAJOR_REV_MASK_SFT
- AUDDEC_DIG_MAJOR_REV_SFT
- AUDDEC_DIG_MINOR_REV_MASK
- AUDDEC_DIG_MINOR_REV_MASK_SFT
- AUDDEC_DIG_MINOR_REV_SFT
- AUDDEC_DSN_BIX_MASK
- AUDDEC_DSN_BIX_MASK_SFT
- AUDDEC_DSN_BIX_SFT
- AUDDEC_DSN_CBS_MASK
- AUDDEC_DSN_CBS_MASK_SFT
- AUDDEC_DSN_CBS_SFT
- AUDDEC_DSN_ESP_MASK
- AUDDEC_DSN_ESP_MASK_SFT
- AUDDEC_DSN_ESP_SFT
- AUDDEC_DSN_FPI_MASK
- AUDDEC_DSN_FPI_MASK_SFT
- AUDDEC_DSN_FPI_SFT
- AUDDIGMICEN_PERIODIC_INVERSE_MASK
- AUDDIGMICEN_PERIODIC_INVERSE_MASK_SFT
- AUDDIGMICEN_PERIODIC_INVERSE_SFT
- AUDDIGMICEN_PERIODIC_MODE_MASK
- AUDDIGMICEN_PERIODIC_MODE_MASK_SFT
- AUDDIGMICEN_PERIODIC_MODE_SFT
- AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK
- AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDDIGMICEN_PERIODIC_OFF_CYCLE_SFT
- AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK
- AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK_SFT
- AUDDIGMICEN_PERIODIC_ON_CYCLE_SFT
- AUDDTS
- AUDENC_ANA_ID_MASK
- AUDENC_ANA_ID_MASK_SFT
- AUDENC_ANA_ID_SFT
- AUDENC_ANA_MAJOR_REV_MASK
- AUDENC_ANA_MAJOR_REV_MASK_SFT
- AUDENC_ANA_MAJOR_REV_SFT
- AUDENC_ANA_MINOR_REV_MASK
- AUDENC_ANA_MINOR_REV_MASK_SFT
- AUDENC_ANA_MINOR_REV_SFT
- AUDENC_DIG_ID_MASK
- AUDENC_DIG_ID_MASK_SFT
- AUDENC_DIG_ID_SFT
- AUDENC_DIG_MAJOR_REV_MASK
- AUDENC_DIG_MAJOR_REV_MASK_SFT
- AUDENC_DIG_MAJOR_REV_SFT
- AUDENC_DIG_MINOR_REV_MASK
- AUDENC_DIG_MINOR_REV_MASK_SFT
- AUDENC_DIG_MINOR_REV_SFT
- AUDENC_DSN_BIX_MASK
- AUDENC_DSN_BIX_MASK_SFT
- AUDENC_DSN_BIX_SFT
- AUDENC_DSN_CBS_MASK
- AUDENC_DSN_CBS_MASK_SFT
- AUDENC_DSN_CBS_SFT
- AUDENC_DSN_ESP_MASK
- AUDENC_DSN_ESP_MASK_SFT
- AUDENC_DSN_ESP_SFT
- AUDENC_DSN_FPI_MASK
- AUDENC_DSN_FPI_MASK_SFT
- AUDENC_DSN_FPI_SFT
- AUDFMT_TYPE_DISABLED
- AUDFMT_TYPE_I2S
- AUDFMT_TYPE_SPDIF
- AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK
- AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK_SFT
- AUDGLBVOWLPWEN_PERIODIC_INVERSE_SFT
- AUDGLBVOWLPWEN_PERIODIC_MODE_MASK
- AUDGLBVOWLPWEN_PERIODIC_MODE_MASK_SFT
- AUDGLBVOWLPWEN_PERIODIC_MODE_SFT
- AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK
- AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_SFT
- AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK
- AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK_SFT
- AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_SFT
- AUDGLB_PWRDN_PERIODIC_INVERSE_MASK
- AUDGLB_PWRDN_PERIODIC_INVERSE_MASK_SFT
- AUDGLB_PWRDN_PERIODIC_INVERSE_SFT
- AUDGLB_PWRDN_PERIODIC_MODE_MASK
- AUDGLB_PWRDN_PERIODIC_MODE_MASK_SFT
- AUDGLB_PWRDN_PERIODIC_MODE_SFT
- AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK
- AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_SFT
- AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK
- AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK_SFT
- AUDGLB_PWRDN_PERIODIC_ON_CYCLE_SFT
- AUDIGY_DMA_MASK
- AUDIO
- AUDIO1_IRQ
- AUDIO1_PLL
- AUDIO2X
- AUDIO2_IRQ
- AUDIOCMD
- AUDIOMUX1_I2SMUX_ADC_DMIC
- AUDIOMUX1_I2SMUX_CLASSD_DSP
- AUDIOMUX1_I2SMUX_DAC_DSP
- AUDIOMUX1_I2SMUX_DMIC2
- AUDIOMUX1_I2SMUX_I2S1
- AUDIOMUX1_I2SMUX_I2S2
- AUDIOMUX1_I2SMUX_I2S3
- AUDIOMUX1_I2SMUX_SUB_DSP
- AUDIORINGIPDSP0_END
- AUDIORINGIPDSP0_START
- AUDIORINGIPDSP1_END
- AUDIORINGIPDSP1_START
- AUDIORINGIPDSP2_END
- AUDIORINGIPDSP2_START
- AUDIORINGIPDSP3_END
- AUDIORINGIPDSP3_START
- AUDIORINGOPDSP0_END
- AUDIORINGOPDSP0_START
- AUDIORINGOPDSP1_END
- AUDIORINGOPDSP1_START
- AUDIORINGOPDSP2_END
- AUDIORINGOPDSP2_START
- AUDIORINGOPDSP3_END
- AUDIORINGOPDSP3_START
- AUDIO_16M384
- AUDIO_1764K
- AUDIO_192K
- AUDIO_24M
- AUDIO_32K
- AUDIO_441K
- AUDIO_48K
- AUDIO_882K
- AUDIO_96K
- AUDIO_99M
- AUDIO_ANALOG_VOLUME_HPOUTL
- AUDIO_ANALOG_VOLUME_HPOUTR
- AUDIO_ANALOG_VOLUME_HSOUTL
- AUDIO_ANALOG_VOLUME_HSOUTR
- AUDIO_ANALOG_VOLUME_LINEOUTL
- AUDIO_ANALOG_VOLUME_LINEOUTR
- AUDIO_ANALOG_VOLUME_MICAMP1
- AUDIO_ANALOG_VOLUME_MICAMP2
- AUDIO_ANALOG_VOLUME_TYPE_MAX
- AUDIO_APB
- AUDIO_APBRIDGEA_DIRECTION_RX
- AUDIO_APBRIDGEA_DIRECTION_TX
- AUDIO_APBRIDGEA_PCM_FMT_16
- AUDIO_APBRIDGEA_PCM_FMT_24
- AUDIO_APBRIDGEA_PCM_FMT_32
- AUDIO_APBRIDGEA_PCM_FMT_64
- AUDIO_APBRIDGEA_PCM_FMT_8
- AUDIO_APBRIDGEA_PCM_RATE_11025
- AUDIO_APBRIDGEA_PCM_RATE_16000
- AUDIO_APBRIDGEA_PCM_RATE_176400
- AUDIO_APBRIDGEA_PCM_RATE_192000
- AUDIO_APBRIDGEA_PCM_RATE_22050
- AUDIO_APBRIDGEA_PCM_RATE_32000
- AUDIO_APBRIDGEA_PCM_RATE_44100
- AUDIO_APBRIDGEA_PCM_RATE_48000
- AUDIO_APBRIDGEA_PCM_RATE_5512
- AUDIO_APBRIDGEA_PCM_RATE_64000
- AUDIO_APBRIDGEA_PCM_RATE_8000
- AUDIO_APBRIDGEA_PCM_RATE_88200
- AUDIO_APBRIDGEA_PCM_RATE_96000
- AUDIO_APBRIDGEA_TYPE_PREPARE_RX
- AUDIO_APBRIDGEA_TYPE_PREPARE_TX
- AUDIO_APBRIDGEA_TYPE_REGISTER_CPORT
- AUDIO_APBRIDGEA_TYPE_SET_CONFIG
- AUDIO_APBRIDGEA_TYPE_SET_RX_DATA_SIZE
- AUDIO_APBRIDGEA_TYPE_SET_TX_DATA_SIZE
- AUDIO_APBRIDGEA_TYPE_SHUTDOWN_RX
- AUDIO_APBRIDGEA_TYPE_SHUTDOWN_TX
- AUDIO_APBRIDGEA_TYPE_START_RX
- AUDIO_APBRIDGEA_TYPE_START_TX
- AUDIO_APBRIDGEA_TYPE_STOP_RX
- AUDIO_APBRIDGEA_TYPE_STOP_TX
- AUDIO_APBRIDGEA_TYPE_UNREGISTER_CPORT
- AUDIO_AZ_HWID
- AUDIO_BCL_INV
- AUDIO_BILINGUAL_CHANNEL_SELECT
- AUDIO_BLOCK
- AUDIO_BLOCK_SIZE
- AUDIO_CAP_AAC
- AUDIO_CAP_AC3
- AUDIO_CAP_DTS
- AUDIO_CAP_LPCM
- AUDIO_CAP_MP1
- AUDIO_CAP_MP2
- AUDIO_CAP_MP3
- AUDIO_CAP_OGG
- AUDIO_CAP_SDDS
- AUDIO_CDT_SIZE
- AUDIO_CDT_SIZE_QW
- AUDIO_CFS
- AUDIO_CFS_INV
- AUDIO_CHANNELS_1
- AUDIO_CHANNELS_2
- AUDIO_CHANNELS_3
- AUDIO_CHANNELS_4
- AUDIO_CHANNELS_5
- AUDIO_CHANNELS_6
- AUDIO_CHANNELS_7
- AUDIO_CHANNELS_8
- AUDIO_CHANNELS_COUNT
- AUDIO_CHANNEL_OFFSET
- AUDIO_CHANNEL_SELECT
- AUDIO_CH_NUM
- AUDIO_CLEAR_BUFFER
- AUDIO_CLK
- AUDIO_CLKA_A_MARK
- AUDIO_CLKA_B_MARK
- AUDIO_CLKA_C_MARK
- AUDIO_CLKA_D_MARK
- AUDIO_CLKA_MARK
- AUDIO_CLKB_A_MARK
- AUDIO_CLKB_B_MARK
- AUDIO_CLKB_C_MARK
- AUDIO_CLKB_MARK
- AUDIO_CLKC_A_MARK
- AUDIO_CLKC_B_MARK
- AUDIO_CLKC_C_MARK
- AUDIO_CLKC_MARK
- AUDIO_CLKOUT_A_MARK
- AUDIO_CLKOUT_B_MARK
- AUDIO_CLKOUT_C_MARK
- AUDIO_CLKOUT_D_MARK
- AUDIO_CLKOUT_MARK
- AUDIO_CLK_GATE_EN
- AUDIO_CLK_LOCKER_CTRL
- AUDIO_CLK_MARK
- AUDIO_CLK_PDMIN_CTRL0
- AUDIO_CLK_PDMIN_CTRL1
- AUDIO_CLK_RESAMPLE_CTRL
- AUDIO_CLK_SEL
- AUDIO_CLK_SEL0
- AUDIO_CLK_SEL1
- AUDIO_CLK_SEL2
- AUDIO_CLK_SPDIFIN_CTRL
- AUDIO_CLK_SPDIFOUT_B_CTRL
- AUDIO_CLK_SPDIFOUT_CTRL
- AUDIO_CLK_SRC
- AUDIO_CLK_TDMIN_A_CTRL
- AUDIO_CLK_TDMIN_B_CTRL
- AUDIO_CLK_TDMIN_C_CTRL
- AUDIO_CLK_TDMIN_LB_CTRL
- AUDIO_CLK_TDMOUT_A_CTRL
- AUDIO_CLK_TDMOUT_B_CTRL
- AUDIO_CLK_TDMOUT_C_CTRL
- AUDIO_CLOCK_PLL_PD
- AUDIO_CLOCK_SEL_128FS
- AUDIO_CLOCK_SEL_16FS
- AUDIO_CLOCK_SEL_256FS
- AUDIO_CLOCK_SEL_32FS
- AUDIO_CLOCK_SEL_512FS
- AUDIO_CLOCK_SEL_64FS
- AUDIO_CLOCK_SEL_MASK
- AUDIO_CLUSTER_SIZE
- AUDIO_CLUSTER_SIZE_QW
- AUDIO_CMDS_SIZE
- AUDIO_CMD_MONO_L
- AUDIO_CMD_MONO_R
- AUDIO_CMD_MUTE
- AUDIO_CMD_PCM16
- AUDIO_CMD_STEREO
- AUDIO_CMD_SYNC_OFF
- AUDIO_CMD_SYNC_ON
- AUDIO_CMD_UNMUTE
- AUDIO_CNTRL0_ERROR_TOLERANCE
- AUDIO_CNTRL0_FRAMES_PER_BLOCK
- AUDIO_CNTRL0_SOURCE_SELECT_AUTO
- AUDIO_CNTRL0_SOURCE_SELECT_HDAL
- AUDIO_CNTRL0_SOURCE_SELECT_SPDIF
- AUDIO_CODEC_CDCFS8K16K
- AUDIO_CODING_TYPE_AACLC
- AUDIO_CODING_TYPE_AC3
- AUDIO_CODING_TYPE_ATRAC
- AUDIO_CODING_TYPE_DST
- AUDIO_CODING_TYPE_DTS
- AUDIO_CODING_TYPE_DTS_HD
- AUDIO_CODING_TYPE_EAC3
- AUDIO_CODING_TYPE_HE_AAC
- AUDIO_CODING_TYPE_HE_AAC2
- AUDIO_CODING_TYPE_LPCM
- AUDIO_CODING_TYPE_MLP
- AUDIO_CODING_TYPE_MP3
- AUDIO_CODING_TYPE_MPEG1
- AUDIO_CODING_TYPE_MPEG2
- AUDIO_CODING_TYPE_MPEG_SURROUND
- AUDIO_CODING_TYPE_REF_CXT
- AUDIO_CODING_TYPE_REF_STREAM_HEADER
- AUDIO_CODING_TYPE_SACD
- AUDIO_CODING_TYPE_WMAPRO
- AUDIO_CODING_XTYPE_FIRST_RESERVED
- AUDIO_CODING_XTYPE_HE_AAC
- AUDIO_CODING_XTYPE_HE_AAC2
- AUDIO_CODING_XTYPE_HE_REF_CT
- AUDIO_CODING_XTYPE_MPEG_SURROUND
- AUDIO_CONTINUE
- AUDIO_CONTROL1
- AUDIO_CONTROL2
- AUDIO_CONTROL3
- AUDIO_CONTROL_CODEC_PRESENT
- AUDIO_CONTROL_NAME_MAX
- AUDIO_CONTROL_RESET
- AUDIO_CP_CHANGE_TRANSCODER_A
- AUDIO_CP_CHANGE_TRANSCODER_B
- AUDIO_CP_CHANGE_TRANSCODER_C
- AUDIO_CP_READY
- AUDIO_CP_REQUEST_TRANSCODER_A
- AUDIO_CP_REQUEST_TRANSCODER_B
- AUDIO_CP_REQUEST_TRANSCODER_C
- AUDIO_CSM
- AUDIO_CTL_ELEM_NAME_MAX
- AUDIO_C_CLK_EN
- AUDIO_C_EN
- AUDIO_C_RESET
- AUDIO_DAC_CFS_DLY_B
- AUDIO_DAI_NAME_MAX
- AUDIO_DEFAULT_CONTROL
- AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK
- AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AUDIO_DEST_AUTO
- AUDIO_DEST_HDMI
- AUDIO_DEST_HEADPHONES
- AUDIO_DEST_MAX
- AUDIO_DET
- AUDIO_DEV_SET
- AUDIO_DIG_ANA_ID_MASK
- AUDIO_DIG_ANA_ID_MASK_SFT
- AUDIO_DIG_ANA_ID_SFT
- AUDIO_DIG_ANA_MAJOR_REV_MASK
- AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT
- AUDIO_DIG_ANA_MAJOR_REV_SFT
- AUDIO_DIG_ANA_MINOR_REV_MASK
- AUDIO_DIG_ANA_MINOR_REV_MASK_SFT
- AUDIO_DIG_ANA_MINOR_REV_SFT
- AUDIO_DIG_DIG_ID_MASK
- AUDIO_DIG_DIG_ID_MASK_SFT
- AUDIO_DIG_DIG_ID_SFT
- AUDIO_DIG_DIG_MAJOR_REV_MASK
- AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT
- AUDIO_DIG_DIG_MAJOR_REV_SFT
- AUDIO_DIG_DIG_MINOR_REV_MASK
- AUDIO_DIG_DIG_MINOR_REV_MASK_SFT
- AUDIO_DIG_DIG_MINOR_REV_SFT
- AUDIO_DIG_DSN_BIX_MASK
- AUDIO_DIG_DSN_BIX_MASK_SFT
- AUDIO_DIG_DSN_BIX_SFT
- AUDIO_DIG_DSN_CBS_MASK
- AUDIO_DIG_DSN_CBS_MASK_SFT
- AUDIO_DIG_DSN_CBS_SFT
- AUDIO_DIG_DSN_FPI_MASK
- AUDIO_DIG_DSN_FPI_MASK_SFT
- AUDIO_DIG_DSN_FPI_SFT
- AUDIO_DIG_ESP_MASK
- AUDIO_DIG_ESP_MASK_SFT
- AUDIO_DIG_ESP_SFT
- AUDIO_DIV
- AUDIO_DIV_SERCLK_1
- AUDIO_DIV_SERCLK_16
- AUDIO_DIV_SERCLK_2
- AUDIO_DIV_SERCLK_32
- AUDIO_DIV_SERCLK_4
- AUDIO_DIV_SERCLK_8
- AUDIO_DMA_SIZE_MASK
- AUDIO_DMA_SIZE_MAX
- AUDIO_DMA_SIZE_MIN
- AUDIO_DMA_SIZE_SHIFT
- AUDIO_DTO
- AUDIO_DTO_MODULE
- AUDIO_DTO_PHASE
- AUDIO_ELD_VALID
- AUDIO_EN
- AUDIO_ENABLE
- AUDIO_ENABLED
- AUDIO_ENABLE_SET
- AUDIO_ENUM_NAME_MAX
- AUDIO_EXT_INT_MSK
- AUDIO_EXT_INT_MSTAT
- AUDIO_EXT_INT_SSTAT
- AUDIO_EXT_INT_STAT
- AUDIO_FAST_PLL
- AUDIO_FIFO_EMPTY
- AUDIO_FIFO_FULL
- AUDIO_FIFO_OFLOW
- AUDIO_FIFO_RESET
- AUDIO_FIFO_START
- AUDIO_FIFO_UFLOW
- AUDIO_FORMAT_CODE_1BITAUDIO
- AUDIO_FORMAT_CODE_AAC
- AUDIO_FORMAT_CODE_AC3
- AUDIO_FORMAT_CODE_ATRAC
- AUDIO_FORMAT_CODE_COUNT
- AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS
- AUDIO_FORMAT_CODE_DST
- AUDIO_FORMAT_CODE_DTS
- AUDIO_FORMAT_CODE_DTS_HD
- AUDIO_FORMAT_CODE_FIRST
- AUDIO_FORMAT_CODE_LAST
- AUDIO_FORMAT_CODE_LINEARPCM
- AUDIO_FORMAT_CODE_MAT_MLP
- AUDIO_FORMAT_CODE_MP3
- AUDIO_FORMAT_CODE_MPEG1
- AUDIO_FORMAT_CODE_MPEG2
- AUDIO_FORMAT_CODE_WMAPRO
- AUDIO_FS_HIGH
- AUDIO_FS_LOW
- AUDIO_GET_CAPABILITIES
- AUDIO_GET_STATUS
- AUDIO_HDMI_CONFIG_A
- AUDIO_HDMI_CONFIG_B
- AUDIO_HDMI_CONFIG_C
- AUDIO_I2C0_CLK
- AUDIO_I2C0_PCLK
- AUDIO_I2C0_WCLK
- AUDIO_I2S0_CLK
- AUDIO_I2S0_DIV_CFG1
- AUDIO_I2S0_DIV_CFG2
- AUDIO_I2S0_PCLK
- AUDIO_I2S0_WCLK
- AUDIO_I2S1_CLK
- AUDIO_I2S1_DIV_CFG1
- AUDIO_I2S1_DIV_CFG2
- AUDIO_I2S1_PCLK
- AUDIO_I2S1_WCLK
- AUDIO_I2S2_CLK
- AUDIO_I2S2_DIV_CFG1
- AUDIO_I2S2_DIV_CFG2
- AUDIO_I2S2_PCLK
- AUDIO_I2S2_WCLK
- AUDIO_I2S3_CLK
- AUDIO_I2S3_DIV_CFG1
- AUDIO_I2S3_DIV_CFG2
- AUDIO_I2S3_PCLK
- AUDIO_I2S3_WCLK
- AUDIO_I2S_MAP
- AUDIO_I2S_MODE
- AUDIO_I2S_NCTS_SEL
- AUDIO_I2S_NCTS_SEL_128
- AUDIO_I2S_NCTS_SEL_64
- AUDIO_I2S_SWAPS_SPDIF
- AUDIO_IC_CODEC_CTRL0
- AUDIO_IC_CODEC_CTRL1
- AUDIO_IC_CODEC_CTRL2
- AUDIO_IC_CODEC_CTRL3
- AUDIO_IC_CODEC_PWR
- AUDIO_ID_INTERNAL_AZALIA
- AUDIO_ID_UNKNOWN
- AUDIO_IFACE
- AUDIO_IFACE_TO_VAL
- AUDIO_INACTIVE
- AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS
- AUDIO_INPUT
- AUDIO_INPUT_LINE
- AUDIO_INPUT_MUTE
- AUDIO_INPUT_SPDIF
- AUDIO_INPUT_TUNER_FM
- AUDIO_INPUT_TUNER_TV
- AUDIO_INT
- AUDIO_INTM
- AUDIO_INT_ENABLE
- AUDIO_INT_INT_MSK
- AUDIO_INT_INT_MSTAT
- AUDIO_INT_INT_SSTAT
- AUDIO_INT_INT_STAT
- AUDIO_INT_MASK
- AUDIO_INT_READ_BUFFER_FULL
- AUDIO_INT_STATUS
- AUDIO_INT_WRITE_BUFFER_1_EMPTY
- AUDIO_INT_WRITE_BUFFER_2_EMPTY
- AUDIO_IO_AIM
- AUDIO_IO_HAS_MUTE_LEVEL
- AUDIO_IO_HAS_MUTE_MONITORING_1
- AUDIO_IO_HAS_MUTE_MONITORING_2
- AUDIO_IO_HAS_MUTE_MONITOR_1
- AUDIO_IO_MCLK
- AUDIO_IO_RX_BLRCLK
- AUDIO_IO_RX_CTL
- AUDIO_IO_RX_SRT_CTL
- AUDIO_IO_SET
- AUDIO_IO_TX_BLRCLK
- AUDIO_IO_TX_CSTAT_H
- AUDIO_IO_TX_CSTAT_L
- AUDIO_IO_TX_CTL
- AUDIO_IQ_SIZE
- AUDIO_IQ_SIZE_DW
- AUDIO_LAYOUT_0
- AUDIO_LAYOUT_1
- AUDIO_LAYOUT_LAYOUT1
- AUDIO_LAYOUT_MANUAL
- AUDIO_LAYOUT_SELECT
- AUDIO_LAYOUT_SP_FLAG
- AUDIO_LINE_SIZE
- AUDIO_LIPSYNC
- AUDIO_MCLK_A_CTRL
- AUDIO_MCLK_B_CTRL
- AUDIO_MCLK_C_CTRL
- AUDIO_MCLK_D_CTRL
- AUDIO_MCLK_E_CTRL
- AUDIO_MCLK_F_CTRL
- AUDIO_MODE
- AUDIO_MODE_MASTER_MODE
- AUDIO_MODE_SPDIF_MODE
- AUDIO_MONO
- AUDIO_MONO_LEFT
- AUDIO_MONO_RIGHT
- AUDIO_MST_A_SCLK_CTRL0
- AUDIO_MST_A_SCLK_CTRL1
- AUDIO_MST_B_SCLK_CTRL0
- AUDIO_MST_B_SCLK_CTRL1
- AUDIO_MST_C_SCLK_CTRL0
- AUDIO_MST_C_SCLK_CTRL1
- AUDIO_MST_D_SCLK_CTRL0
- AUDIO_MST_D_SCLK_CTRL1
- AUDIO_MST_E_SCLK_CTRL0
- AUDIO_MST_E_SCLK_CTRL1
- AUDIO_MST_F_SCLK_CTRL0
- AUDIO_MST_F_SCLK_CTRL1
- AUDIO_MST_PAD_CTRL0
- AUDIO_MST_PAD_CTRL1
- AUDIO_MUTE_MSK
- AUDIO_NR_CLKS
- AUDIO_N_GENERATE_ALTERNATE
- AUDIO_N_GENERATE_NORMAL
- AUDIO_N_H
- AUDIO_N_L
- AUDIO_N_M
- AUDIO_N_RESETF
- AUDIO_N_VALUE
- AUDIO_OUTPUT_ENABLE
- AUDIO_OUT_48
- AUDIO_OUT_ENABLE
- AUDIO_OUT_ENABLE_ACLK
- AUDIO_OUT_ENABLE_AP0
- AUDIO_OUT_ENABLE_AP1
- AUDIO_OUT_ENABLE_AP2
- AUDIO_OUT_ENABLE_AP3
- AUDIO_OUT_ENABLE_WS
- AUDIO_PACKET_OFF
- AUDIO_PACK_CONTROL
- AUDIO_PACK_EN
- AUDIO_PACK_STATUS
- AUDIO_PAUSE
- AUDIO_PAUSED
- AUDIO_PFC_DAT
- AUDIO_PFC_PIN
- AUDIO_PLAY
- AUDIO_PLAYING
- AUDIO_PLL
- AUDIO_PLL1
- AUDIO_PLL2
- AUDIO_PLL_DIV_FRAC
- AUDIO_PLL_FOUT_MAX
- AUDIO_PLL_FOUT_MIN
- AUDIO_PLL_ND_MAX
- AUDIO_PLL_QDPAD
- AUDIO_PLL_QDPMC_MAX
- AUDIO_PORT_IC_CODEC_RX_CTRL
- AUDIO_PORT_IC_CODEC_TX_CTRL
- AUDIO_PORT_IC_RXFIFO_INT
- AUDIO_PORT_IC_RXFIFO_INT_MSK
- AUDIO_PORT_IC_RXFIFO_LEV_CHK
- AUDIO_PORT_IC_RXFIFO_OP
- AUDIO_PORT_IC_RXFIFO_STS
- AUDIO_PORT_IC_TXFIFO_INT
- AUDIO_PORT_IC_TXFIFO_INT_MSK
- AUDIO_PORT_IC_TXFIFO_LEV_CHK
- AUDIO_PORT_IC_TXFIFO_OP
- AUDIO_PORT_IC_TXFIFO_STS
- AUDIO_PORT_RX_FIFO_HC_OFFSET
- AUDIO_PORT_RX_FIFO_LC_OFFSET
- AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK
- AUDIO_PORT_RX_FIFO_SC_OFFSET
- AUDIO_PORT_TX_FIFO_HC_OFFSET
- AUDIO_PORT_TX_FIFO_LC_OFFSET
- AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK
- AUDIO_PORT_TX_FIFO_SC_OFFSET
- AUDIO_POWER_STATE_CHANGE_B
- AUDIO_POWER_STATE_CHANGE_C
- AUDIO_POWER_STATE_CHANGE_D
- AUDIO_PRODUCT_NUM
- AUDIO_READ_BUFFER_AVAILABLE
- AUDIO_READ_SUPPORTED
- AUDIO_ROUTE_I2S
- AUDIO_ROUTE_NUM
- AUDIO_ROUTE_SPDIF
- AUDIO_RX0_ADDCDC
- AUDIO_RX0_ADDRXIN
- AUDIO_RX0_ADDSTDC
- AUDIO_RX0_ALSPEN
- AUDIO_RX0_ALSPSEL
- AUDIO_RX1_ARXINEN
- AUDIO_RX1_PGARXEN
- AUDIO_RX1_PGASTEN
- AUDIO_SAMPLE_RATE
- AUDIO_SAMPLING_RATE_176_4KHZ
- AUDIO_SAMPLING_RATE_192KHZ
- AUDIO_SAMPLING_RATE_32KHZ
- AUDIO_SAMPLING_RATE_44_1KHZ
- AUDIO_SAMPLING_RATE_48KHZ
- AUDIO_SAMPLING_RATE_88_2KHZ
- AUDIO_SAMPLING_RATE_96KHZ
- AUDIO_SDM_LEVEL_MUTE
- AUDIO_SDM_LEVEL_NORMAL
- AUDIO_SECTION_ON
- AUDIO_SECTION_RESET
- AUDIO_SELECT_SOURCE
- AUDIO_SET_AV_SYNC
- AUDIO_SET_BYPASS_MODE
- AUDIO_SET_ID
- AUDIO_SET_MIXER
- AUDIO_SET_MUTE
- AUDIO_SET_READ_BUFFER
- AUDIO_SET_READ_BUFFER_HIGH
- AUDIO_SET_STREAMTYPE
- AUDIO_SET_WRITE_BUFFER_1
- AUDIO_SET_WRITE_BUFFER_1_HIGH
- AUDIO_SET_WRITE_BUFFER_2
- AUDIO_SET_WRITE_BUFFER_2_HIGH
- AUDIO_SLIMBUS_CLK
- AUDIO_SLOT_BLOCK_NUM
- AUDIO_SOURCE_DEMUX
- AUDIO_SOURCE_IIS
- AUDIO_SOURCE_MEMORY
- AUDIO_SOURCE_SPDIF
- AUDIO_SPDIF0_CLK
- AUDIO_SPDIF0_DIV_CFG1
- AUDIO_SPDIF0_DIV_CFG2
- AUDIO_SPDIF0_PCLK
- AUDIO_SPDIF0_WCLK
- AUDIO_SPDIF1_CLK
- AUDIO_SPDIF1_DIV_CFG1
- AUDIO_SPDIF1_DIV_CFG2
- AUDIO_SPDIF1_PCLK
- AUDIO_SPDIF1_WCLK
- AUDIO_SRAM_CHANNEL
- AUDIO_SRC_CNFG
- AUDIO_SRC_CNTL
- AUDIO_SSI_SEL
- AUDIO_START_READ
- AUDIO_STATUS_COPYRIGHT
- AUDIO_STATUS_DIG_ENABLE
- AUDIO_STATUS_EMPHASIS
- AUDIO_STATUS_LEVEL
- AUDIO_STATUS_NONAUDIO
- AUDIO_STATUS_PROFESSIONAL
- AUDIO_STATUS_V
- AUDIO_STATUS_VCFG
- AUDIO_STEREO
- AUDIO_STEREO_SWAPPED
- AUDIO_STOP
- AUDIO_STOPPED
- AUDIO_STREAM_E
- AUDIO_STREAM_S
- AUDIO_SW_RESET
- AUDIO_SW_RST
- AUDIO_SYNC_CLK
- AUDIO_SYNC_CLK_DMIC1
- AUDIO_SYNC_CLK_DMIC2
- AUDIO_SYNC_CLK_DMIC3
- AUDIO_SYNC_CLK_I2S0
- AUDIO_SYNC_CLK_I2S1
- AUDIO_SYNC_CLK_I2S2
- AUDIO_SYNC_CLK_I2S3
- AUDIO_SYNC_CLK_I2S4
- AUDIO_SYNC_CLK_SPDIF
- AUDIO_SYNC_DOUBLER
- AUDIO_SYS_TOP_MON_SEL_MASK
- AUDIO_SYS_TOP_MON_SEL_MASK_SFT
- AUDIO_SYS_TOP_MON_SEL_SFT
- AUDIO_SYS_TOP_MON_SWAP_MASK
- AUDIO_SYS_TOP_MON_SWAP_MASK_SFT
- AUDIO_SYS_TOP_MON_SWAP_SFT
- AUDIO_TDM_CLK
- AUDIO_TDM_PCLK
- AUDIO_TDM_WCLK
- AUDIO_TEST_PATTERN_OPERATOR_DEFINED
- AUDIO_TEST_PATTERN_SAWTOOTH
- AUDIO_TIMER_CLK
- AUDIO_TIMER_PCLK
- AUDIO_TIMER_WCLK
- AUDIO_TOP_CON0
- AUDIO_TOP_CON1
- AUDIO_TOP_CON3
- AUDIO_TOP_CON4
- AUDIO_TOP_CON5
- AUDIO_TOP_DBG_CON
- AUDIO_TOP_DBG_MON0
- AUDIO_TOP_DBG_MON1
- AUDIO_TOP_DBG_MON2
- AUDIO_TS_CLK
- AUDIO_TS_PCLK
- AUDIO_TX_AMC1LEN
- AUDIO_TX_AMC1REN
- AUDIO_TX_AMC2EN
- AUDIO_TX_ATXINEN
- AUDIO_TX_RXINREC
- AUDIO_TYPE_LPCM
- AUDIO_UPSTREAM_SRAM_CHANNEL_B
- AUDIO_VENDOR_NUM
- AUDIO_WIDGET_NAME_MAX
- AUDIO_WRITE_BUFFER_1
- AUDIO_WRITE_BUFFER_2
- AUDIO_XOUT_MARK
- AUDIO_ZERO
- AUDIT
- AUDITSC_ARGS
- AUDITSC_FAILURE
- AUDITSC_INVALID
- AUDITSC_SUCCESS
- AUDIT_ADD
- AUDIT_ADD_RULE
- AUDIT_ALL
- AUDIT_ALWAYS
- AUDIT_ANOM_ABEND
- AUDIT_ANOM_LINK
- AUDIT_ANOM_PROMISCUOUS
- AUDIT_APPARMOR_ALLOWED
- AUDIT_APPARMOR_AUDIT
- AUDIT_APPARMOR_AUTO
- AUDIT_APPARMOR_DENIED
- AUDIT_APPARMOR_ERROR
- AUDIT_APPARMOR_HINT
- AUDIT_APPARMOR_KILL
- AUDIT_APPARMOR_STATUS
- AUDIT_ARCH
- AUDIT_ARCH_AARCH64
- AUDIT_ARCH_ALPHA
- AUDIT_ARCH_ARCOMPACT
- AUDIT_ARCH_ARCOMPACTBE
- AUDIT_ARCH_ARCV2
- AUDIT_ARCH_ARCV2BE
- AUDIT_ARCH_ARM
- AUDIT_ARCH_ARMEB
- AUDIT_ARCH_C6X
- AUDIT_ARCH_C6XBE
- AUDIT_ARCH_CRIS
- AUDIT_ARCH_CSKY
- AUDIT_ARCH_FRV
- AUDIT_ARCH_H8300
- AUDIT_ARCH_HEXAGON
- AUDIT_ARCH_I386
- AUDIT_ARCH_IA64
- AUDIT_ARCH_M32R
- AUDIT_ARCH_M68K
- AUDIT_ARCH_MICROBLAZE
- AUDIT_ARCH_MIPS
- AUDIT_ARCH_MIPS64
- AUDIT_ARCH_MIPS64N32
- AUDIT_ARCH_MIPSEL
- AUDIT_ARCH_MIPSEL64
- AUDIT_ARCH_MIPSEL64N32
- AUDIT_ARCH_NDS32
- AUDIT_ARCH_NDS32BE
- AUDIT_ARCH_NIOS2
- AUDIT_ARCH_OPENRISC
- AUDIT_ARCH_PARISC
- AUDIT_ARCH_PARISC64
- AUDIT_ARCH_PPC
- AUDIT_ARCH_PPC64
- AUDIT_ARCH_PPC64LE
- AUDIT_ARCH_RISCV32
- AUDIT_ARCH_RISCV64
- AUDIT_ARCH_S390
- AUDIT_ARCH_S390X
- AUDIT_ARCH_SH
- AUDIT_ARCH_SH64
- AUDIT_ARCH_SHEL
- AUDIT_ARCH_SHEL64
- AUDIT_ARCH_SPARC
- AUDIT_ARCH_SPARC64
- AUDIT_ARCH_TILEGX
- AUDIT_ARCH_TILEGX32
- AUDIT_ARCH_TILEPRO
- AUDIT_ARCH_UNICORE
- AUDIT_ARCH_X86_64
- AUDIT_ARCH_XTENSA
- AUDIT_ARG0
- AUDIT_ARG1
- AUDIT_ARG2
- AUDIT_ARG3
- AUDIT_AUX_IPCPERM
- AUDIT_AUX_PIDS
- AUDIT_AVC
- AUDIT_AVC_PATH
- AUDIT_BACKLOG_WAIT_TIME
- AUDIT_BIT
- AUDIT_BITMASK_SIZE
- AUDIT_BIT_MASK
- AUDIT_BIT_TEST
- AUDIT_BPRM_FCAPS
- AUDIT_BUFSIZ
- AUDIT_BUILD_CONTEXT
- AUDIT_CAPSET
- AUDIT_CAUSE_LEN_MAX
- AUDIT_CLASS_CHATTR
- AUDIT_CLASS_CHATTR_32
- AUDIT_CLASS_DIR_WRITE
- AUDIT_CLASS_DIR_WRITE_32
- AUDIT_CLASS_READ
- AUDIT_CLASS_READ_32
- AUDIT_CLASS_SIGNAL
- AUDIT_CLASS_SIGNAL_32
- AUDIT_CLASS_WRITE
- AUDIT_CLASS_WRITE_32
- AUDIT_COMPARE_AUID_TO_EUID
- AUDIT_COMPARE_AUID_TO_FSUID
- AUDIT_COMPARE_AUID_TO_OBJ_UID
- AUDIT_COMPARE_AUID_TO_SUID
- AUDIT_COMPARE_EGID_TO_FSGID
- AUDIT_COMPARE_EGID_TO_OBJ_GID
- AUDIT_COMPARE_EGID_TO_SGID
- AUDIT_COMPARE_EUID_TO_FSUID
- AUDIT_COMPARE_EUID_TO_OBJ_UID
- AUDIT_COMPARE_EUID_TO_SUID
- AUDIT_COMPARE_FSGID_TO_OBJ_GID
- AUDIT_COMPARE_FSUID_TO_OBJ_UID
- AUDIT_COMPARE_GID_TO_EGID
- AUDIT_COMPARE_GID_TO_FSGID
- AUDIT_COMPARE_GID_TO_OBJ_GID
- AUDIT_COMPARE_GID_TO_SGID
- AUDIT_COMPARE_SGID_TO_FSGID
- AUDIT_COMPARE_SGID_TO_OBJ_GID
- AUDIT_COMPARE_SUID_TO_FSUID
- AUDIT_COMPARE_SUID_TO_OBJ_UID
- AUDIT_COMPARE_UID_TO_AUID
- AUDIT_COMPARE_UID_TO_EUID
- AUDIT_COMPARE_UID_TO_FSUID
- AUDIT_COMPARE_UID_TO_OBJ_UID
- AUDIT_COMPARE_UID_TO_SUID
- AUDIT_CONFIG_CHANGE
- AUDIT_CWD
- AUDIT_DAEMON_ABORT
- AUDIT_DAEMON_CONFIG
- AUDIT_DAEMON_END
- AUDIT_DAEMON_START
- AUDIT_DEL
- AUDIT_DEL_RULE
- AUDIT_DEVMAJOR
- AUDIT_DEVMINOR
- AUDIT_DEV_UNSET
- AUDIT_DIR
- AUDIT_DISABLED
- AUDIT_EGID
- AUDIT_EOE
- AUDIT_EQUAL
- AUDIT_EUID
- AUDIT_EXE
- AUDIT_EXECVE
- AUDIT_EXIT
- AUDIT_FAIL_PANIC
- AUDIT_FAIL_PRINTK
- AUDIT_FAIL_SILENT
- AUDIT_FANOTIFY
- AUDIT_FD_PAIR
- AUDIT_FEATURE_BITMAP_ALL
- AUDIT_FEATURE_BITMAP_BACKLOG_LIMIT
- AUDIT_FEATURE_BITMAP_BACKLOG_WAIT_TIME
- AUDIT_FEATURE_BITMAP_EXCLUDE_EXTEND
- AUDIT_FEATURE_BITMAP_EXECUTABLE_PATH
- AUDIT_FEATURE_BITMAP_FILTER_FS
- AUDIT_FEATURE_BITMAP_LOST_RESET
- AUDIT_FEATURE_BITMAP_SESSIONID_FILTER
- AUDIT_FEATURE_CHANGE
- AUDIT_FEATURE_LOGINUID_IMMUTABLE
- AUDIT_FEATURE_ONLY_UNSET_LOGINUID
- AUDIT_FEATURE_TO_MASK
- AUDIT_FEATURE_VERSION
- AUDIT_FIELD_COMPARE
- AUDIT_FILETYPE
- AUDIT_FILTERKEY
- AUDIT_FILTER_ENTRY
- AUDIT_FILTER_EXCLUDE
- AUDIT_FILTER_EXIT
- AUDIT_FILTER_FS
- AUDIT_FILTER_PREPEND
- AUDIT_FILTER_TASK
- AUDIT_FILTER_TYPE
- AUDIT_FILTER_USER
- AUDIT_FILTER_WATCH
- AUDIT_FIRST_KERN_ANOM_MSG
- AUDIT_FIRST_USER_MSG
- AUDIT_FIRST_USER_MSG2
- AUDIT_FSGID
- AUDIT_FSTYPE
- AUDIT_FSUID
- AUDIT_FS_EVENTS
- AUDIT_FS_WATCH
- AUDIT_GET
- AUDIT_GET_FEATURE
- AUDIT_GID
- AUDIT_GREATER_THAN
- AUDIT_GREATER_THAN_OR_EQUAL
- AUDIT_INITIALIZED
- AUDIT_INODE
- AUDIT_INODE_BUCKETS
- AUDIT_INODE_HIDDEN
- AUDIT_INODE_NOEVAL
- AUDIT_INODE_PARENT
- AUDIT_INO_UNSET
- AUDIT_INTEGRITY_DATA
- AUDIT_INTEGRITY_EVM_XATTR
- AUDIT_INTEGRITY_HASH
- AUDIT_INTEGRITY_METADATA
- AUDIT_INTEGRITY_PCR
- AUDIT_INTEGRITY_POLICY_RULE
- AUDIT_INTEGRITY_RULE
- AUDIT_INTEGRITY_STATUS
- AUDIT_IPC
- AUDIT_IPC_SET_PERM
- AUDIT_KERNEL
- AUDIT_KERNEL_OTHER
- AUDIT_KERN_MODULE
- AUDIT_LAST_FEATURE
- AUDIT_LAST_KERN_ANOM_MSG
- AUDIT_LAST_USER_MSG
- AUDIT_LAST_USER_MSG2
- AUDIT_LESS_THAN
- AUDIT_LESS_THAN_OR_EQUAL
- AUDIT_LIST
- AUDIT_LIST_RULES
- AUDIT_LOCKED
- AUDIT_LOGIN
- AUDIT_LOGINUID
- AUDIT_LOGINUID_LEGACY
- AUDIT_LOGINUID_SET
- AUDIT_MAC_CALIPSO_ADD
- AUDIT_MAC_CALIPSO_DEL
- AUDIT_MAC_CIPSOV4_ADD
- AUDIT_MAC_CIPSOV4_DEL
- AUDIT_MAC_CONFIG_CHANGE
- AUDIT_MAC_IPSEC_ADDSA
- AUDIT_MAC_IPSEC_ADDSPD
- AUDIT_MAC_IPSEC_DELSA
- AUDIT_MAC_IPSEC_DELSPD
- AUDIT_MAC_IPSEC_EVENT
- AUDIT_MAC_MAP_ADD
- AUDIT_MAC_MAP_DEL
- AUDIT_MAC_POLICY_LOAD
- AUDIT_MAC_STATUS
- AUDIT_MAC_UNLBL_ALLOW
- AUDIT_MAC_UNLBL_STCADD
- AUDIT_MAC_UNLBL_STCDEL
- AUDIT_MAKE_EQUIV
- AUDIT_MAX_FIELDS
- AUDIT_MAX_FIELD_COMPARE
- AUDIT_MAX_INDEX
- AUDIT_MAX_KEY_LEN
- AUDIT_MESSAGE_TEXT_MAX
- AUDIT_MMAP
- AUDIT_MODE
- AUDIT_MQ_GETSETATTR
- AUDIT_MQ_NOTIFY
- AUDIT_MQ_OPEN
- AUDIT_MQ_SENDRECV
- AUDIT_MSGTYPE
- AUDIT_NAMES
- AUDIT_NAME_FULL
- AUDIT_NEGATE
- AUDIT_NETFILTER_CFG
- AUDIT_NETFILTER_PKT
- AUDIT_NEVER
- AUDIT_NLGRP_MAX
- AUDIT_NLGRP_NONE
- AUDIT_NLGRP_READLOG
- AUDIT_NOQUIET
- AUDIT_NORMAL
- AUDIT_NOT_EQUAL
- AUDIT_NR_FILTERS
- AUDIT_NTP_ADJUST
- AUDIT_NTP_FREQ
- AUDIT_NTP_NVALS
- AUDIT_NTP_OFFSET
- AUDIT_NTP_STATUS
- AUDIT_NTP_TAI
- AUDIT_NTP_TICK
- AUDIT_OBJ_GID
- AUDIT_OBJ_LEV_HIGH
- AUDIT_OBJ_LEV_LOW
- AUDIT_OBJ_PID
- AUDIT_OBJ_ROLE
- AUDIT_OBJ_TYPE
- AUDIT_OBJ_UID
- AUDIT_OBJ_USER
- AUDIT_OFF
- AUDIT_ON
- AUDIT_OPERATORS
- AUDIT_PATH
- AUDIT_PERM
- AUDIT_PERM_ATTR
- AUDIT_PERM_EXEC
- AUDIT_PERM_READ
- AUDIT_PERM_WRITE
- AUDIT_PERS
- AUDIT_PID
- AUDIT_POSSIBLE
- AUDIT_POST_PAGE_FAULT
- AUDIT_POST_PTE_WRITE
- AUDIT_POST_SYNC
- AUDIT_PPID
- AUDIT_PRE_PAGE_FAULT
- AUDIT_PRE_PTE_WRITE
- AUDIT_PRE_SYNC
- AUDIT_PROCTITLE
- AUDIT_QUIET
- AUDIT_QUIET_DENIED
- AUDIT_RECORD_CONTEXT
- AUDIT_REPLACE
- AUDIT_SADDR_FAM
- AUDIT_SECCOMP
- AUDIT_SELINUX_ERR
- AUDIT_SESSIONID
- AUDIT_SET
- AUDIT_SET_FEATURE
- AUDIT_SGID
- AUDIT_SID_UNSET
- AUDIT_SIGNAL_INFO
- AUDIT_SOCKADDR
- AUDIT_SOCKETCALL
- AUDIT_STATUS_BACKLOG_LIMIT
- AUDIT_STATUS_BACKLOG_WAIT_TIME
- AUDIT_STATUS_ENABLED
- AUDIT_STATUS_FAILURE
- AUDIT_STATUS_LOST
- AUDIT_STATUS_PID
- AUDIT_STATUS_RATE_LIMIT
- AUDIT_SUBJ_CLR
- AUDIT_SUBJ_ROLE
- AUDIT_SUBJ_SEN
- AUDIT_SUBJ_TYPE
- AUDIT_SUBJ_USER
- AUDIT_SUCCESS
- AUDIT_SUID
- AUDIT_SYSCALL
- AUDIT_SYSCALL_CLASSES
- AUDIT_TIME_ADJNTPVAL
- AUDIT_TIME_INJOFFSET
- AUDIT_TRIM
- AUDIT_TTY
- AUDIT_TTY_ENABLE
- AUDIT_TTY_GET
- AUDIT_TTY_LOG_PASSWD
- AUDIT_TTY_SET
- AUDIT_TYPE_CHILD_CREATE
- AUDIT_TYPE_CHILD_DELETE
- AUDIT_TYPE_NORMAL
- AUDIT_TYPE_PARENT
- AUDIT_TYPE_UNKNOWN
- AUDIT_UID
- AUDIT_UID_UNSET
- AUDIT_UNINITIALIZED
- AUDIT_UNUSED_BITS
- AUDIT_USER
- AUDIT_USER_AVC
- AUDIT_USER_TTY
- AUDIT_VERSION_BACKLOG_LIMIT
- AUDIT_VERSION_BACKLOG_WAIT_TIME
- AUDIT_VERSION_LATEST
- AUDIT_WATCH
- AUDIT_WATCH_INS
- AUDIT_WATCH_LIST
- AUDIT_WATCH_REM
- AUDIT_WORD
- AUDPARARINGIODSP0_END
- AUDPARARINGIODSP0_START
- AUDPARARINGIODSP1_END
- AUDPARARINGIODSP1_START
- AUDPARARINGIODSP2_END
- AUDPARARINGIODSP2_START
- AUDPARARINGIODSP3_END
- AUDPARARINGIODSP3_START
- AUDPLL_TUNER_EN
- AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK
- AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK
- AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK
- AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK
- AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK_SFT
- AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_SFT
- AUDPREAMPLON_PERIODIC_INVERSE_MASK
- AUDPREAMPLON_PERIODIC_INVERSE_MASK_SFT
- AUDPREAMPLON_PERIODIC_INVERSE_SFT
- AUDPREAMPLON_PERIODIC_MODE_MASK
- AUDPREAMPLON_PERIODIC_MODE_MASK_SFT
- AUDPREAMPLON_PERIODIC_MODE_SFT
- AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK
- AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDPREAMPLON_PERIODIC_OFF_CYCLE_SFT
- AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK
- AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK_SFT
- AUDPREAMPLON_PERIODIC_ON_CYCLE_SFT
- AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK
- AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK_SFT
- AUDPWDBMICBIAS0_PERIODIC_INVERSE_SFT
- AUDPWDBMICBIAS0_PERIODIC_MODE_MASK
- AUDPWDBMICBIAS0_PERIODIC_MODE_MASK_SFT
- AUDPWDBMICBIAS0_PERIODIC_MODE_SFT
- AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK
- AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_SFT
- AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK
- AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK_SFT
- AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_SFT
- AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK
- AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK_SFT
- AUDPWDBMICBIAS1_PERIODIC_INVERSE_SFT
- AUDPWDBMICBIAS1_PERIODIC_MODE_MASK
- AUDPWDBMICBIAS1_PERIODIC_MODE_MASK_SFT
- AUDPWDBMICBIAS1_PERIODIC_MODE_SFT
- AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK
- AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK_SFT
- AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_SFT
- AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK
- AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK_SFT
- AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_SFT
- AUDRCVDMADONEA
- AUDRCVDMADONEB
- AUDRDD
- AUDRFSR
- AUDROR
- AUDSS_MAX_CLKS
- AUDSTO
- AUDSYNC
- AUDSYNC_MARK
- AUDTFSR
- AUDTUR
- AUDUNIT_CLOCK_GATE_DISABLE
- AUDXMTDMADONEA
- AUDXMTDMADONEB
- AUD_A2
- AUD_AFE_12DB_EN
- AUD_APB_IN_RATE_ADJ
- AUD_A_CDT
- AUD_A_CFG
- AUD_A_DOWN_CLUSTER_1
- AUD_A_DOWN_CLUSTER_2
- AUD_A_DOWN_CLUSTER_3
- AUD_A_DOWN_CMDS
- AUD_A_GPCNT
- AUD_A_GPCNT_CTL
- AUD_A_INT_MSK
- AUD_A_INT_MSTAT
- AUD_A_INT_SSTAT
- AUD_A_INT_STAT
- AUD_A_IQ
- AUD_A_LNGTH
- AUD_A_UP_CLUSTER_1
- AUD_A_UP_CLUSTER_2
- AUD_A_UP_CLUSTER_3
- AUD_A_UP_CMDS
- AUD_BAL_CTL
- AUD_BAUDRATE
- AUD_BCLK_OUT_INV
- AUD_BCLK_OUT_INV_INVERSE
- AUD_BCLK_OUT_INV_NO_INVERSE
- AUD_BIQUAD_PLL_K0
- AUD_BIQUAD_PLL_K1
- AUD_BIQUAD_PLL_K2
- AUD_BIQUAD_PLL_K3
- AUD_BIQUAD_PLL_K4
- AUD_BT_MODE
- AUD_BT_MODE_DUAL_MIC_ON_TX
- AUD_BT_MODE_SINGLE_MIC_ON_TX
- AUD_BUF_ADDR
- AUD_BUF_A_ADDR
- AUD_BUF_A_LENGTH
- AUD_BUF_B_ADDR
- AUD_BUF_B_LENGTH
- AUD_BUF_CH_SWAP
- AUD_BUF_CONFIG
- AUD_BUF_C_ADDR
- AUD_BUF_C_LENGTH
- AUD_BUF_D_ADDR
- AUD_BUF_D_LENGTH
- AUD_BUF_INTR_EN
- AUD_BUF_LEN
- AUD_BUF_VALID
- AUD_BUILD_NUM
- AUD_B_CDT
- AUD_B_CFG
- AUD_B_DOWN_CLUSTER_1
- AUD_B_DOWN_CLUSTER_2
- AUD_B_DOWN_CLUSTER_3
- AUD_B_DOWN_CMDS
- AUD_B_GPCNT
- AUD_B_GPCNT_CTL
- AUD_B_INT_MSK
- AUD_B_INT_MSTAT
- AUD_B_INT_SSTAT
- AUD_B_INT_STAT
- AUD_B_IQ
- AUD_B_LNGTH
- AUD_B_UP_CLUSTER_1
- AUD_B_UP_CLUSTER_2
- AUD_B_UP_CLUSTER_3
- AUD_B_UP_CMDS
- AUD_C1_LO_THR
- AUD_C1_UP_THR
- AUD_C2_LO_THR
- AUD_C2_UP_THR
- AUD_CARRIER_STRENGTH_QP_0DB
- AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100
- AUD_CFG_MM2S_MASK
- AUD_CFG_S2MM_MASK
- AUD_CHAN_SRC_FLATIRON
- AUD_CHAN_SRC_I2S_INPUT
- AUD_CHAN_SRC_PARALLEL
- AUD_CHAN_SRC_PARALLEL3
- AUD_CH_STATUS_0
- AUD_CH_STATUS_1
- AUD_CLKID_DDR_ARB
- AUD_CLKID_FRDDR_A
- AUD_CLKID_FRDDR_B
- AUD_CLKID_FRDDR_C
- AUD_CLKID_LOOPBACK
- AUD_CLKID_MST_A_LRCLK
- AUD_CLKID_MST_A_LRCLK_DIV
- AUD_CLKID_MST_A_MCLK
- AUD_CLKID_MST_A_MCLK_DIV
- AUD_CLKID_MST_A_MCLK_SEL
- AUD_CLKID_MST_A_SCLK
- AUD_CLKID_MST_A_SCLK_DIV
- AUD_CLKID_MST_A_SCLK_POST_EN
- AUD_CLKID_MST_A_SCLK_PRE_EN
- AUD_CLKID_MST_B_LRCLK
- AUD_CLKID_MST_B_LRCLK_DIV
- AUD_CLKID_MST_B_MCLK
- AUD_CLKID_MST_B_MCLK_DIV
- AUD_CLKID_MST_B_MCLK_SEL
- AUD_CLKID_MST_B_SCLK
- AUD_CLKID_MST_B_SCLK_DIV
- AUD_CLKID_MST_B_SCLK_POST_EN
- AUD_CLKID_MST_B_SCLK_PRE_EN
- AUD_CLKID_MST_C_LRCLK
- AUD_CLKID_MST_C_LRCLK_DIV
- AUD_CLKID_MST_C_MCLK
- AUD_CLKID_MST_C_MCLK_DIV
- AUD_CLKID_MST_C_MCLK_SEL
- AUD_CLKID_MST_C_SCLK
- AUD_CLKID_MST_C_SCLK_DIV
- AUD_CLKID_MST_C_SCLK_POST_EN
- AUD_CLKID_MST_C_SCLK_PRE_EN
- AUD_CLKID_MST_D_LRCLK
- AUD_CLKID_MST_D_LRCLK_DIV
- AUD_CLKID_MST_D_MCLK
- AUD_CLKID_MST_D_MCLK_DIV
- AUD_CLKID_MST_D_MCLK_SEL
- AUD_CLKID_MST_D_SCLK
- AUD_CLKID_MST_D_SCLK_DIV
- AUD_CLKID_MST_D_SCLK_POST_EN
- AUD_CLKID_MST_D_SCLK_PRE_EN
- AUD_CLKID_MST_E_LRCLK
- AUD_CLKID_MST_E_LRCLK_DIV
- AUD_CLKID_MST_E_MCLK
- AUD_CLKID_MST_E_MCLK_DIV
- AUD_CLKID_MST_E_MCLK_SEL
- AUD_CLKID_MST_E_SCLK
- AUD_CLKID_MST_E_SCLK_DIV
- AUD_CLKID_MST_E_SCLK_POST_EN
- AUD_CLKID_MST_E_SCLK_PRE_EN
- AUD_CLKID_MST_F_LRCLK
- AUD_CLKID_MST_F_LRCLK_DIV
- AUD_CLKID_MST_F_MCLK
- AUD_CLKID_MST_F_MCLK_DIV
- AUD_CLKID_MST_F_MCLK_SEL
- AUD_CLKID_MST_F_SCLK
- AUD_CLKID_MST_F_SCLK_DIV
- AUD_CLKID_MST_F_SCLK_POST_EN
- AUD_CLKID_MST_F_SCLK_PRE_EN
- AUD_CLKID_PDM
- AUD_CLKID_PDM_DCLK
- AUD_CLKID_PDM_DCLK_DIV
- AUD_CLKID_PDM_DCLK_SEL
- AUD_CLKID_PDM_SYSCLK
- AUD_CLKID_PDM_SYSCLK_DIV
- AUD_CLKID_PDM_SYSCLK_SEL
- AUD_CLKID_POWER_DETECT
- AUD_CLKID_RESAMPLE
- AUD_CLKID_SPDIFIN
- AUD_CLKID_SPDIFIN_CLK
- AUD_CLKID_SPDIFIN_CLK_DIV
- AUD_CLKID_SPDIFIN_CLK_SEL
- AUD_CLKID_SPDIFOUT
- AUD_CLKID_SPDIFOUT_B
- AUD_CLKID_SPDIFOUT_B_CLK
- AUD_CLKID_SPDIFOUT_B_CLK_DIV
- AUD_CLKID_SPDIFOUT_B_CLK_SEL
- AUD_CLKID_SPDIFOUT_CLK
- AUD_CLKID_SPDIFOUT_CLK_DIV
- AUD_CLKID_SPDIFOUT_CLK_SEL
- AUD_CLKID_TDMIN_A
- AUD_CLKID_TDMIN_A_LRCLK
- AUD_CLKID_TDMIN_A_SCLK
- AUD_CLKID_TDMIN_A_SCLK_POST_EN
- AUD_CLKID_TDMIN_A_SCLK_PRE_EN
- AUD_CLKID_TDMIN_A_SCLK_SEL
- AUD_CLKID_TDMIN_B
- AUD_CLKID_TDMIN_B_LRCLK
- AUD_CLKID_TDMIN_B_SCLK
- AUD_CLKID_TDMIN_B_SCLK_POST_EN
- AUD_CLKID_TDMIN_B_SCLK_PRE_EN
- AUD_CLKID_TDMIN_B_SCLK_SEL
- AUD_CLKID_TDMIN_C
- AUD_CLKID_TDMIN_C_LRCLK
- AUD_CLKID_TDMIN_C_SCLK
- AUD_CLKID_TDMIN_C_SCLK_POST_EN
- AUD_CLKID_TDMIN_C_SCLK_PRE_EN
- AUD_CLKID_TDMIN_C_SCLK_SEL
- AUD_CLKID_TDMIN_LB
- AUD_CLKID_TDMIN_LB_LRCLK
- AUD_CLKID_TDMIN_LB_SCLK
- AUD_CLKID_TDMIN_LB_SCLK_POST_EN
- AUD_CLKID_TDMIN_LB_SCLK_PRE_EN
- AUD_CLKID_TDMIN_LB_SCLK_SEL
- AUD_CLKID_TDMOUT_A
- AUD_CLKID_TDMOUT_A_LRCLK
- AUD_CLKID_TDMOUT_A_SCLK
- AUD_CLKID_TDMOUT_A_SCLK_POST_EN
- AUD_CLKID_TDMOUT_A_SCLK_PRE_EN
- AUD_CLKID_TDMOUT_A_SCLK_SEL
- AUD_CLKID_TDMOUT_B
- AUD_CLKID_TDMOUT_B_LRCLK
- AUD_CLKID_TDMOUT_B_SCLK
- AUD_CLKID_TDMOUT_B_SCLK_POST_EN
- AUD_CLKID_TDMOUT_B_SCLK_PRE_EN
- AUD_CLKID_TDMOUT_B_SCLK_SEL
- AUD_CLKID_TDMOUT_C
- AUD_CLKID_TDMOUT_C_LRCLK
- AUD_CLKID_TDMOUT_C_SCLK
- AUD_CLKID_TDMOUT_C_SCLK_POST_EN
- AUD_CLKID_TDMOUT_C_SCLK_PRE_EN
- AUD_CLKID_TDMOUT_C_SCLK_SEL
- AUD_CLKID_TDM_LRCLK_PAD0
- AUD_CLKID_TDM_LRCLK_PAD1
- AUD_CLKID_TDM_LRCLK_PAD2
- AUD_CLKID_TDM_MCLK_PAD0
- AUD_CLKID_TDM_MCLK_PAD1
- AUD_CLKID_TDM_SCLK_PAD0
- AUD_CLKID_TDM_SCLK_PAD1
- AUD_CLKID_TDM_SCLK_PAD2
- AUD_CLKID_TODDR_A
- AUD_CLKID_TODDR_B
- AUD_CLKID_TODDR_C
- AUD_CLK_A
- AUD_CLK_A1
- AUD_CLK_A2
- AUD_CLK_APLL
- AUD_CLK_AUD_UART
- AUD_CLK_CHG
- AUD_CLK_DMAC
- AUD_CLK_F
- AUD_CLK_F1
- AUD_CLK_F2
- AUD_CLK_HSC0
- AUD_CLK_I2S
- AUD_CLK_IO
- AUD_CLK_PCM
- AUD_CLK_RX0
- AUD_CLK_SRAMC
- AUD_CLK_USB0
- AUD_CNTL_ST
- AUD_COMMON_MASK_SH_LIST
- AUD_COMMON_MASK_SH_LIST_BASE
- AUD_COMMON_REG_LIST
- AUD_COMM_EXEC_ACTIVE
- AUD_COMM_EXEC_STOP
- AUD_COMM_EXEC__A
- AUD_COMM_EXEC__M
- AUD_COMM_EXEC__PRE
- AUD_COMM_EXEC__W
- AUD_COMM_MB__A
- AUD_COMM_MB__M
- AUD_COMM_MB__PRE
- AUD_COMM_MB__W
- AUD_CONFIG
- AUD_CONFIG_CH_MASK
- AUD_CONFIG_DISABLE_NCTS
- AUD_CONFIG_DP_MODE
- AUD_CONFIG_LOWER_N_MASK
- AUD_CONFIG_LOWER_N_SHIFT
- AUD_CONFIG_M_MASK
- AUD_CONFIG_N
- AUD_CONFIG_N_MASK
- AUD_CONFIG_N_PROG_ENABLE
- AUD_CONFIG_N_VALUE_INDEX
- AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
- AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
- AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
- AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
- AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
- AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
- AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
- AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
- AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
- AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
- AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
- AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT
- AUD_CONFIG_UPPER_N_MASK
- AUD_CONFIG_UPPER_N_SHIFT
- AUD_CONFIG_VALID_BIT
- AUD_CORDIC_SHIFT_0
- AUD_CORDIC_SHIFT_1
- AUD_CRDC0_SHIFT
- AUD_CRDC0_SRC_SEL
- AUD_CRDC1_SHIFT
- AUD_CRDC1_SRC_SEL
- AUD_CTL
- AUD_CTRL_ACTIVE_CH_SHIFT
- AUD_CTRL_DATA_WIDTH_SHIFT
- AUD_CTRL_DMA_EN_MASK
- AUD_CTRL_IOC_IRQ_MASK
- AUD_CTRL_RESET_MASK
- AUD_CTRL_TOUT_IRQ_MASK
- AUD_C_CDT
- AUD_C_CFG
- AUD_C_DOWN_CLUSTER_1
- AUD_C_DOWN_CLUSTER_2
- AUD_C_DOWN_CLUSTER_3
- AUD_C_DOWN_CMDS
- AUD_C_GPCNT
- AUD_C_GPCNT_CTL
- AUD_C_INT_MSK
- AUD_C_INT_MSTAT
- AUD_C_INT_SSTAT
- AUD_C_INT_STAT
- AUD_C_IQ
- AUD_C_LNGTH
- AUD_C_UP_CLUSTER_1
- AUD_C_UP_CLUSTER_2
- AUD_C_UP_CLUSTER_3
- AUD_C_UP_CMDS
- AUD_DAC_BYPASS_CTL
- AUD_DAC_BYPASS_L
- AUD_DAC_BYPASS_R
- AUD_DBX_IN_GAIN
- AUD_DBX_RMS_SE
- AUD_DBX_RMS_WBE
- AUD_DBX_SE_BYPASS
- AUD_DBX_SE_GAIN
- AUD_DBX_WBE_GAIN
- AUD_DCOC0_SHIFT
- AUD_DCOC1_SHIFT
- AUD_DCOC2_SHIFT
- AUD_DCOC_0_SHIFT_IN0
- AUD_DCOC_0_SHIFT_IN1
- AUD_DCOC_0_SRC
- AUD_DCOC_1_SHIFT_IN0
- AUD_DCOC_1_SHIFT_IN1
- AUD_DCOC_1_SRC
- AUD_DCOC_2_SHIFT_IN0
- AUD_DCOC_2_SHIFT_IN1
- AUD_DCOC_2_SRC
- AUD_DCOC_PASS_IN
- AUD_DC_COMP_EN_MASK
- AUD_DC_COMP_EN_MASK_SFT
- AUD_DC_COMP_EN_SFT
- AUD_DEEMPH0_A0
- AUD_DEEMPH0_A1
- AUD_DEEMPH0_B0
- AUD_DEEMPH0_B1
- AUD_DEEMPH0_G0
- AUD_DEEMPH0_SHIFT
- AUD_DEEMPH0_SRC_SEL
- AUD_DEEMPH1_A0
- AUD_DEEMPH1_A1
- AUD_DEEMPH1_B0
- AUD_DEEMPH1_B1
- AUD_DEEMPH1_G0
- AUD_DEEMPH1_SHIFT
- AUD_DEEMPH1_SRC_SEL
- AUD_DEEMPHDENOM1_R
- AUD_DEEMPHDENOM2_R
- AUD_DEEMPHGAIN_R
- AUD_DEEMPHNUMER1_R
- AUD_DEEMPHNUMER2_R
- AUD_DEM_RAM_A2_THRSHLD__A
- AUD_DEM_RAM_BTSC_THRSHLD__A
- AUD_DEM_RAM_CM_A_THRSHLD__A
- AUD_DEM_RAM_CM_B_THRSHLD__A
- AUD_DEM_RAM_DCO_A_HI__A
- AUD_DEM_RAM_DCO_A_LO__A
- AUD_DEM_RAM_DCO_B_HI__A
- AUD_DEM_RAM_DCO_B_LO__A
- AUD_DEM_RAM_I2S_CONFIG1__A
- AUD_DEM_RAM_I2S_CONFIG2__A
- AUD_DEM_RAM_MODUS_HI__A
- AUD_DEM_RAM_MODUS_HI__M
- AUD_DEM_RAM_MODUS_LO__A
- AUD_DEM_RAM_MODUS_LO__M
- AUD_DEM_RAM_NICAM_THRSHLD__A
- AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B
- AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M
- AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE
- AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W
- AUD_DEM_RD_NIC_ADD_BITS_HI__A
- AUD_DEM_RD_NIC_ADD_BITS_HI__M
- AUD_DEM_RD_NIC_ADD_BITS_HI__PRE
- AUD_DEM_RD_NIC_ADD_BITS_HI__W
- AUD_DEM_RD_NIC_CIB_CIB1__B
- AUD_DEM_RD_NIC_CIB_CIB1__M
- AUD_DEM_RD_NIC_CIB_CIB1__PRE
- AUD_DEM_RD_NIC_CIB_CIB1__W
- AUD_DEM_RD_NIC_CIB_CIB2__B
- AUD_DEM_RD_NIC_CIB_CIB2__M
- AUD_DEM_RD_NIC_CIB_CIB2__PRE
- AUD_DEM_RD_NIC_CIB_CIB2__W
- AUD_DEM_RD_NIC_CIB__A
- AUD_DEM_RD_NIC_CIB__M
- AUD_DEM_RD_NIC_CIB__PRE
- AUD_DEM_RD_NIC_CIB__W
- AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B
- AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M
- AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE
- AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W
- AUD_DEM_RD_NIC_C_AD_BITS_C__B
- AUD_DEM_RD_NIC_C_AD_BITS_C__M
- AUD_DEM_RD_NIC_C_AD_BITS_C__PRE
- AUD_DEM_RD_NIC_C_AD_BITS_C__W
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE
- AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W
- AUD_DEM_RD_NIC_C_AD_BITS__A
- AUD_DEM_RD_NIC_C_AD_BITS__M
- AUD_DEM_RD_NIC_C_AD_BITS__PRE
- AUD_DEM_RD_NIC_C_AD_BITS__W
- AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B
- AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M
- AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE
- AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W
- AUD_DEM_RD_NIC_ERROR_RATE__A
- AUD_DEM_RD_NIC_ERROR_RATE__M
- AUD_DEM_RD_NIC_ERROR_RATE__PRE
- AUD_DEM_RD_NIC_ERROR_RATE__W
- AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID
- AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B
- AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M
- AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE
- AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W
- AUD_DEM_RD_RDS_ARRAY_CNT__A
- AUD_DEM_RD_RDS_ARRAY_CNT__M
- AUD_DEM_RD_RDS_ARRAY_CNT__PRE
- AUD_DEM_RD_RDS_ARRAY_CNT__W
- AUD_DEM_RD_RDS_DATA__A
- AUD_DEM_RD_RDS_DATA__M
- AUD_DEM_RD_RDS_DATA__PRE
- AUD_DEM_RD_RDS_DATA__W
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J
- AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM
- AUD_DEM_RD_STANDARD_RES_STD_RESULT__B
- AUD_DEM_RD_STANDARD_RES_STD_RESULT__M
- AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE
- AUD_DEM_RD_STANDARD_RES_STD_RESULT__W
- AUD_DEM_RD_STANDARD_RES__A
- AUD_DEM_RD_STANDARD_RES__M
- AUD_DEM_RD_STANDARD_RES__PRE
- AUD_DEM_RD_STANDARD_RES__W
- AUD_DEM_RD_STATUS_BAD_NICAM_BAD
- AUD_DEM_RD_STATUS_BAD_NICAM_OK
- AUD_DEM_RD_STATUS_BAD_NICAM__B
- AUD_DEM_RD_STATUS_BAD_NICAM__M
- AUD_DEM_RD_STATUS_BAD_NICAM__PRE
- AUD_DEM_RD_STATUS_BAD_NICAM__W
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE
- AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W
- AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED
- AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED
- AUD_DEM_RD_STATUS_STAT_CARR_A__B
- AUD_DEM_RD_STATUS_STAT_CARR_A__M
- AUD_DEM_RD_STATUS_STAT_CARR_A__PRE
- AUD_DEM_RD_STATUS_STAT_CARR_A__W
- AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED
- AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED
- AUD_DEM_RD_STATUS_STAT_CARR_B__B
- AUD_DEM_RD_STATUS_STAT_CARR_B__M
- AUD_DEM_RD_STATUS_STAT_CARR_B__PRE
- AUD_DEM_RD_STATUS_STAT_CARR_B__W
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE
- AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W
- AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA
- AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA
- AUD_DEM_RD_STATUS_STAT_NEW_RDS__B
- AUD_DEM_RD_STATUS_STAT_NEW_RDS__M
- AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE
- AUD_DEM_RD_STATUS_STAT_NEW_RDS__W
- AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED
- AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM
- AUD_DEM_RD_STATUS_STAT_NICAM__B
- AUD_DEM_RD_STATUS_STAT_NICAM__M
- AUD_DEM_RD_STATUS_STAT_NICAM__PRE
- AUD_DEM_RD_STATUS_STAT_NICAM__W
- AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO
- AUD_DEM_RD_STATUS_STAT_STEREO_STEREO
- AUD_DEM_RD_STATUS_STAT_STEREO__B
- AUD_DEM_RD_STATUS_STAT_STEREO__M
- AUD_DEM_RD_STATUS_STAT_STEREO__PRE
- AUD_DEM_RD_STATUS_STAT_STEREO__W
- AUD_DEM_RD_STATUS__A
- AUD_DEM_RD_STATUS__M
- AUD_DEM_RD_STATUS__PRE
- AUD_DEM_RD_STATUS__W
- AUD_DEM_WR_A2_THRSHLD_A2_THLD__B
- AUD_DEM_WR_A2_THRSHLD_A2_THLD__M
- AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE
- AUD_DEM_WR_A2_THRSHLD_A2_THLD__W
- AUD_DEM_WR_A2_THRSHLD__A
- AUD_DEM_WR_A2_THRSHLD__M
- AUD_DEM_WR_A2_THRSHLD__PRE
- AUD_DEM_WR_A2_THRSHLD__W
- AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B
- AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M
- AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE
- AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W
- AUD_DEM_WR_BTSC_THRSHLD__A
- AUD_DEM_WR_BTSC_THRSHLD__M
- AUD_DEM_WR_BTSC_THRSHLD__PRE
- AUD_DEM_WR_BTSC_THRSHLD__W
- AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B
- AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M
- AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE
- AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W
- AUD_DEM_WR_CM_A_THRSHLD__A
- AUD_DEM_WR_CM_A_THRSHLD__M
- AUD_DEM_WR_CM_A_THRSHLD__PRE
- AUD_DEM_WR_CM_A_THRSHLD__W
- AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B
- AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M
- AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE
- AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W
- AUD_DEM_WR_CM_B_THRSHLD__A
- AUD_DEM_WR_CM_B_THRSHLD__M
- AUD_DEM_WR_CM_B_THRSHLD__PRE
- AUD_DEM_WR_CM_B_THRSHLD__W
- AUD_DEM_WR_DCO_A_HI__A
- AUD_DEM_WR_DCO_A_HI__M
- AUD_DEM_WR_DCO_A_HI__PRE
- AUD_DEM_WR_DCO_A_HI__W
- AUD_DEM_WR_DCO_A_LO__A
- AUD_DEM_WR_DCO_A_LO__M
- AUD_DEM_WR_DCO_A_LO__PRE
- AUD_DEM_WR_DCO_A_LO__W
- AUD_DEM_WR_DCO_B_HI__A
- AUD_DEM_WR_DCO_B_HI__M
- AUD_DEM_WR_DCO_B_HI__PRE
- AUD_DEM_WR_DCO_B_HI__W
- AUD_DEM_WR_DCO_B_LO__A
- AUD_DEM_WR_DCO_B_LO__M
- AUD_DEM_WR_DCO_B_LO__PRE
- AUD_DEM_WR_DCO_B_LO__W
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE
- AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W
- AUD_DEM_WR_FM_DC_NOTCH_SW__A
- AUD_DEM_WR_FM_DC_NOTCH_SW__M
- AUD_DEM_WR_FM_DC_NOTCH_SW__PRE
- AUD_DEM_WR_FM_DC_NOTCH_SW__W
- AUD_DEM_WR_FM_DEEMPH_50US
- AUD_DEM_WR_FM_DEEMPH_75US
- AUD_DEM_WR_FM_DEEMPH_OFF
- AUD_DEM_WR_FM_DEEMPH__A
- AUD_DEM_WR_FM_DEEMPH__M
- AUD_DEM_WR_FM_DEEMPH__PRE
- AUD_DEM_WR_FM_DEEMPH__W
- AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX
- AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX
- AUD_DEM_WR_FM_MATRIX_NO_MATRIX
- AUD_DEM_WR_FM_MATRIX_SOUND_A
- AUD_DEM_WR_FM_MATRIX_SOUND_B
- AUD_DEM_WR_FM_MATRIX__A
- AUD_DEM_WR_FM_MATRIX__M
- AUD_DEM_WR_FM_MATRIX__PRE
- AUD_DEM_WR_FM_MATRIX__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE
- AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W
- AUD_DEM_WR_I2S_CONFIG2__A
- AUD_DEM_WR_I2S_CONFIG2__M
- AUD_DEM_WR_I2S_CONFIG2__PRE
- AUD_DEM_WR_I2S_CONFIG2__W
- AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA
- AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC
- AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ
- AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA
- AUD_DEM_WR_MODUS_MOD_4_5MHZ__B
- AUD_DEM_WR_MODUS_MOD_4_5MHZ__M
- AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE
- AUD_DEM_WR_MODUS_MOD_4_5MHZ__W
- AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K
- AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM
- AUD_DEM_WR_MODUS_MOD_6_5MHZ__B
- AUD_DEM_WR_MODUS_MOD_6_5MHZ__M
- AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE
- AUD_DEM_WR_MODUS_MOD_6_5MHZ__W
- AUD_DEM_WR_MODUS_MOD_ASS_OFF
- AUD_DEM_WR_MODUS_MOD_ASS_ON
- AUD_DEM_WR_MODUS_MOD_ASS__B
- AUD_DEM_WR_MODUS_MOD_ASS__M
- AUD_DEM_WR_MODUS_MOD_ASS__PRE
- AUD_DEM_WR_MODUS_MOD_ASS__W
- AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP
- AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO
- AUD_DEM_WR_MODUS_MOD_BTSC__B
- AUD_DEM_WR_MODUS_MOD_BTSC__M
- AUD_DEM_WR_MODUS_MOD_BTSC__PRE
- AUD_DEM_WR_MODUS_MOD_BTSC__W
- AUD_DEM_WR_MODUS_MOD_CM_A_MUTE
- AUD_DEM_WR_MODUS_MOD_CM_A_NOISE
- AUD_DEM_WR_MODUS_MOD_CM_A__B
- AUD_DEM_WR_MODUS_MOD_CM_A__M
- AUD_DEM_WR_MODUS_MOD_CM_A__PRE
- AUD_DEM_WR_MODUS_MOD_CM_A__W
- AUD_DEM_WR_MODUS_MOD_CM_B_MUTE
- AUD_DEM_WR_MODUS_MOD_CM_B_NOISE
- AUD_DEM_WR_MODUS_MOD_CM_B__B
- AUD_DEM_WR_MODUS_MOD_CM_B__M
- AUD_DEM_WR_MODUS_MOD_CM_B__PRE
- AUD_DEM_WR_MODUS_MOD_CM_B__W
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE
- AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W
- AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U
- AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U
- AUD_DEM_WR_MODUS_MOD_FMRADIO__B
- AUD_DEM_WR_MODUS_MOD_FMRADIO__M
- AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE
- AUD_DEM_WR_MODUS_MOD_FMRADIO__W
- AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION
- AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL
- AUD_DEM_WR_MODUS_MOD_HDEV_A__B
- AUD_DEM_WR_MODUS_MOD_HDEV_A__M
- AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE
- AUD_DEM_WR_MODUS_MOD_HDEV_A__W
- AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE
- AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE
- AUD_DEM_WR_MODUS_MOD_STATINTERR__B
- AUD_DEM_WR_MODUS_MOD_STATINTERR__M
- AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE
- AUD_DEM_WR_MODUS_MOD_STATINTERR__W
- AUD_DEM_WR_MODUS__A
- AUD_DEM_WR_MODUS__M
- AUD_DEM_WR_MODUS__PRE
- AUD_DEM_WR_MODUS__W
- AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B
- AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M
- AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE
- AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W
- AUD_DEM_WR_NICAM_THRSHLD__A
- AUD_DEM_WR_NICAM_THRSHLD__M
- AUD_DEM_WR_NICAM_THRSHLD__PRE
- AUD_DEM_WR_NICAM_THRSHLD__W
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM
- AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA
- AUD_DEM_WR_STANDARD_SEL_STD_SEL__B
- AUD_DEM_WR_STANDARD_SEL_STD_SEL__M
- AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE
- AUD_DEM_WR_STANDARD_SEL_STD_SEL__W
- AUD_DEM_WR_STANDARD_SEL__A
- AUD_DEM_WR_STANDARD_SEL__M
- AUD_DEM_WR_STANDARD_SEL__PRE
- AUD_DEM_WR_STANDARD_SEL__W
- AUD_DIG_CNVT
- AUD_DIV
- AUD_DMD_RA_DDS
- AUD_DN0_FREQ
- AUD_DN1_AFC
- AUD_DN1_FREQ
- AUD_DN1_FREQ_SHIFT
- AUD_DN1_SHFT
- AUD_DN1_SRC_SEL
- AUD_DN2_AFC
- AUD_DN2_FREQ
- AUD_DN2_FREQ_SHIFT
- AUD_DN2_SHFT
- AUD_DN2_SRC_SEL
- AUD_DOUT_ACLK_AUD_131
- AUD_DOUT_SCLK_AUD_I2S
- AUD_DOUT_SCLK_AUD_PCM
- AUD_DOUT_SCLK_AUD_UART
- AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B
- AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M
- AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE
- AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W
- AUD_DSP_RD_FM_DC_LEVEL_A__A
- AUD_DSP_RD_FM_DC_LEVEL_A__M
- AUD_DSP_RD_FM_DC_LEVEL_A__PRE
- AUD_DSP_RD_FM_DC_LEVEL_A__W
- AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B
- AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M
- AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE
- AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W
- AUD_DSP_RD_FM_DC_LEVEL_B__A
- AUD_DSP_RD_FM_DC_LEVEL_B__M
- AUD_DSP_RD_FM_DC_LEVEL_B__PRE
- AUD_DSP_RD_FM_DC_LEVEL_B__W
- AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B
- AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M
- AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE
- AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W
- AUD_DSP_RD_FM_IDENT_VALUE__A
- AUD_DSP_RD_FM_IDENT_VALUE__M
- AUD_DSP_RD_FM_IDENT_VALUE__PRE
- AUD_DSP_RD_FM_IDENT_VALUE__W
- AUD_DSP_RD_QPEAK_L__A
- AUD_DSP_RD_QPEAK_L__M
- AUD_DSP_RD_QPEAK_L__PRE
- AUD_DSP_RD_QPEAK_L__W
- AUD_DSP_RD_QPEAK_R__A
- AUD_DSP_RD_QPEAK_R__M
- AUD_DSP_RD_QPEAK_R__PRE
- AUD_DSP_RD_QPEAK_R__W
- AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC
- AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE
- AUD_DSP_RD_STATUS2_AV_ACTIVE__B
- AUD_DSP_RD_STATUS2_AV_ACTIVE__M
- AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE
- AUD_DSP_RD_STATUS2_AV_ACTIVE__W
- AUD_DSP_RD_STATUS2__A
- AUD_DSP_RD_STATUS2__M
- AUD_DSP_RD_STATUS2__PRE
- AUD_DSP_RD_STATUS2__W
- AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B
- AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M
- AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE
- AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W
- AUD_DSP_RD_XDFP_FW__A
- AUD_DSP_RD_XDFP_FW__M
- AUD_DSP_RD_XDFP_FW__PRE
- AUD_DSP_RD_XDFP_FW__W
- AUD_DSP_RD_XFP_FW_FP_FW_REV__B
- AUD_DSP_RD_XFP_FW_FP_FW_REV__M
- AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE
- AUD_DSP_RD_XFP_FW_FP_FW_REV__W
- AUD_DSP_RD_XFP_FW__A
- AUD_DSP_RD_XFP_FW__M
- AUD_DSP_RD_XFP_FW__PRE
- AUD_DSP_RD_XFP_FW__W
- AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC
- AUD_DSP_WR_AVC_AVC_DECAY_2_SEC
- AUD_DSP_WR_AVC_AVC_DECAY_4_SEC
- AUD_DSP_WR_AVC_AVC_DECAY_8_SEC
- AUD_DSP_WR_AVC_AVC_DECAY__B
- AUD_DSP_WR_AVC_AVC_DECAY__M
- AUD_DSP_WR_AVC_AVC_DECAY__PRE
- AUD_DSP_WR_AVC_AVC_DECAY__W
- AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB
- AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB
- AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB
- AUD_DSP_WR_AVC_AVC_MAX_ATT__B
- AUD_DSP_WR_AVC_AVC_MAX_ATT__M
- AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE
- AUD_DSP_WR_AVC_AVC_MAX_ATT__W
- AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB
- AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB
- AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB
- AUD_DSP_WR_AVC_AVC_MAX_GAIN__B
- AUD_DSP_WR_AVC_AVC_MAX_GAIN__M
- AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE
- AUD_DSP_WR_AVC_AVC_MAX_GAIN__W
- AUD_DSP_WR_AVC_AVC_ON_OFF
- AUD_DSP_WR_AVC_AVC_ON_ON
- AUD_DSP_WR_AVC_AVC_ON__B
- AUD_DSP_WR_AVC_AVC_ON__M
- AUD_DSP_WR_AVC_AVC_ON__PRE
- AUD_DSP_WR_AVC_AVC_ON__W
- AUD_DSP_WR_AVC_AVC_REF_LEV__B
- AUD_DSP_WR_AVC_AVC_REF_LEV__M
- AUD_DSP_WR_AVC_AVC_REF_LEV__PRE
- AUD_DSP_WR_AVC_AVC_REF_LEV__W
- AUD_DSP_WR_AVC__A
- AUD_DSP_WR_AVC__M
- AUD_DSP_WR_AVC__PRE
- AUD_DSP_WR_AVC__W
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE
- AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W
- AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE
- AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE
- AUD_DSP_WR_AV_SYNC_AV_ON__B
- AUD_DSP_WR_AV_SYNC_AV_ON__M
- AUD_DSP_WR_AV_SYNC_AV_ON__PRE
- AUD_DSP_WR_AV_SYNC_AV_ON__W
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE
- AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W
- AUD_DSP_WR_AV_SYNC__A
- AUD_DSP_WR_AV_SYNC__M
- AUD_DSP_WR_AV_SYNC__PRE
- AUD_DSP_WR_AV_SYNC__W
- AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B
- AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M
- AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE
- AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W
- AUD_DSP_WR_BEEPER_BEEP_VOLUME__B
- AUD_DSP_WR_BEEPER_BEEP_VOLUME__M
- AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE
- AUD_DSP_WR_BEEPER_BEEP_VOLUME__W
- AUD_DSP_WR_BEEPER__A
- AUD_DSP_WR_BEEPER__M
- AUD_DSP_WR_BEEPER__PRE
- AUD_DSP_WR_BEEPER__W
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE
- AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W
- AUD_DSP_WR_FM_PRESC__A
- AUD_DSP_WR_FM_PRESC__M
- AUD_DSP_WR_FM_PRESC__PRE
- AUD_DSP_WR_FM_PRESC__W
- AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B
- AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M
- AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE
- AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W
- AUD_DSP_WR_I2S_OUT_FS__A
- AUD_DSP_WR_I2S_OUT_FS__M
- AUD_DSP_WR_I2S_OUT_FS__PRE
- AUD_DSP_WR_I2S_OUT_FS__W
- AUD_DSP_WR_NICAM_PRESC__A
- AUD_DSP_WR_NICAM_PRESC__M
- AUD_DSP_WR_NICAM_PRESC__PRE
- AUD_DSP_WR_NICAM_PRESC__W
- AUD_DSP_WR_QPEAK_MAT_QP_MONO
- AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A
- AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B
- AUD_DSP_WR_QPEAK_MAT_QP_STEREO
- AUD_DSP_WR_QPEAK_MAT_QP__B
- AUD_DSP_WR_QPEAK_MAT_QP__M
- AUD_DSP_WR_QPEAK_MAT_QP__PRE
- AUD_DSP_WR_QPEAK_MAT_QP__W
- AUD_DSP_WR_QPEAK_SRC_QP_MONO
- AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A
- AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB
- AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B
- AUD_DSP_WR_QPEAK_SRC_QP__B
- AUD_DSP_WR_QPEAK_SRC_QP__M
- AUD_DSP_WR_QPEAK_SRC_QP__PRE
- AUD_DSP_WR_QPEAK_SRC_QP__W
- AUD_DSP_WR_QPEAK__A
- AUD_DSP_WR_QPEAK__M
- AUD_DSP_WR_QPEAK__PRE
- AUD_DSP_WR_QPEAK__W
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE
- AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE
- AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W
- AUD_DSP_WR_SRC_I2S_MATR__A
- AUD_DSP_WR_SRC_I2S_MATR__M
- AUD_DSP_WR_SRC_I2S_MATR__PRE
- AUD_DSP_WR_SRC_I2S_MATR__W
- AUD_DSP_WR_SYNC_OUT_OFF
- AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS
- AUD_DSP_WR_SYNC_OUT__A
- AUD_DSP_WR_SYNC_OUT__M
- AUD_DSP_WR_SYNC_OUT__PRE
- AUD_DSP_WR_SYNC_OUT__W
- AUD_DSP_WR_VOLUME_VOL_MAIN__B
- AUD_DSP_WR_VOLUME_VOL_MAIN__M
- AUD_DSP_WR_VOLUME_VOL_MAIN__PRE
- AUD_DSP_WR_VOLUME_VOL_MAIN__W
- AUD_DSP_WR_VOLUME__A
- AUD_DSP_WR_VOLUME__M
- AUD_DSP_WR_VOLUME__PRE
- AUD_DSP_WR_VOLUME__W
- AUD_DST_A_DMA
- AUD_DST_B_DMA
- AUD_DST_C_DMA
- AUD_DST_D_DMA
- AUD_D_CDT
- AUD_D_CFG
- AUD_D_DOWN_CLUSTER_1
- AUD_D_DOWN_CLUSTER_2
- AUD_D_DOWN_CLUSTER_3
- AUD_D_DOWN_CMDS
- AUD_D_GPCNT
- AUD_D_GPCNT_CTL
- AUD_D_INT_MSK
- AUD_D_INT_MSTAT
- AUD_D_INT_SSTAT
- AUD_D_INT_STAT
- AUD_D_IQ
- AUD_D_LNGTH
- AUD_EN
- AUD_ERRINTRPTTHSHLD1_R
- AUD_ERRINTRPTTHSHLD2_R
- AUD_ERRINTRPTTHSHLD3_R
- AUD_ERRLOG1
- AUD_ERRLOG2
- AUD_ERRLOG3
- AUD_ERRLOGPERIOD_R
- AUD_EXT_A_MODE
- AUD_EXT_DMA
- AUD_EXT_DMA_CTL
- AUD_EXT_GPCNT
- AUD_EXT_GPCNT_CTL
- AUD_EXT_INT_MSK
- AUD_EXT_INT_MSTAT
- AUD_EXT_INT_SSTAT
- AUD_EXT_INT_STAT
- AUD_EXT_LNGTH
- AUD_EXT_MODEM
- AUD_EXT_MODEM_SELECT_EXTERNAL
- AUD_EXT_MODEM_SELECT_INTERNAL
- AUD_E_CDT
- AUD_E_CFG
- AUD_E_GPCNT
- AUD_E_GPCNT_CTL
- AUD_E_INT_MSK
- AUD_E_INT_MSTAT
- AUD_E_INT_SSTAT
- AUD_E_INT_STAT
- AUD_E_IQ
- AUD_E_UP_CLUSTER_1
- AUD_E_UP_CLUSTER_2
- AUD_E_UP_CLUSTER_3
- AUD_E_UP_CMDS
- AUD_FAWDETCTL
- AUD_FAWDETWINCTL
- AUD_FIFO_FUNC_EN_N
- AUD_FM_MODE_ENABLE
- AUD_FUNC_EN_N
- AUD_GATE
- AUD_GNAME_AUX
- AUD_GNAME_HDMI
- AUD_GNAME_IEC
- AUD_GNAME_LINE
- AUD_HARMONIC_MULT
- AUD_HDMIW_INFOFR
- AUD_HDMI_CTS
- AUD_HDMI_STATUS
- AUD_HDMI_STATUSG_MASK_FUNCRST
- AUD_HDMI_STATUS_MASK_SRDBG
- AUD_HDMI_STATUS_MASK_UNDERRUN
- AUD_HP_MD_IIR4_1
- AUD_HP_PROG_IIR4_1
- AUD_HW_CMASTER
- AUD_HW_DIECIN1
- AUD_HW_EPCMOUT1
- AUD_HW_EPCMOUT2
- AUD_HW_EPCMOUT3
- AUD_HW_EPCMOUT6
- AUD_HW_HIECOUT1
- AUD_HW_HPCMOUT1
- AUD_HW_IECIN1
- AUD_HW_IECOUT1
- AUD_HW_PCMIN1
- AUD_HW_PCMIN2
- AUD_HW_PCMIN3
- AUD_HW_PCMOUT1
- AUD_HW_PCMOUT2
- AUD_HW_PCMOUT3
- AUD_I2SCNTL
- AUD_I2SINPUTCNTL
- AUD_I2SOUTPUTCNTL
- AUD_I2S_FREQUENCY_MAX
- AUD_I2S_FREQUENCY_MIN
- AUD_I2S_RA_DDS
- AUD_IF
- AUD_IF_UPDATE
- AUD_IIR1_0_SEL
- AUD_IIR1_0_SHIFT
- AUD_IIR1_1_SEL
- AUD_IIR1_1_SHIFT
- AUD_IIR1_2_SEL
- AUD_IIR1_2_SHIFT
- AUD_IIR1_3_SEL
- AUD_IIR1_3_SHIFT
- AUD_IIR1_4_SEL
- AUD_IIR1_4_SHIFT
- AUD_IIR1_5_SEL
- AUD_IIR1_5_SHIFT
- AUD_IIR2_0_SEL
- AUD_IIR2_0_SHIFT
- AUD_IIR2_1_SEL
- AUD_IIR2_1_SHIFT
- AUD_IIR2_2_SEL
- AUD_IIR2_2_SHIFT
- AUD_IIR2_3_SEL
- AUD_IIR2_3_SHIFT
- AUD_IIR3_0_SEL
- AUD_IIR3_0_SHIFT
- AUD_IIR3_1_SEL
- AUD_IIR3_1_SHIFT
- AUD_IIR3_2_SEL
- AUD_IIR3_2_SHIFT
- AUD_IIR4_0_CA0
- AUD_IIR4_0_CA1
- AUD_IIR4_0_CA2
- AUD_IIR4_0_CB0
- AUD_IIR4_0_CB1
- AUD_IIR4_0_SEL
- AUD_IIR4_0_SHIFT
- AUD_IIR4_1_CA0
- AUD_IIR4_1_CA1
- AUD_IIR4_1_CA2
- AUD_IIR4_1_CB0
- AUD_IIR4_1_CB1
- AUD_IIR4_1_SEL
- AUD_IIR4_1_SHIFT
- AUD_IIR4_2_CA0
- AUD_IIR4_2_CA1
- AUD_IIR4_2_CA2
- AUD_IIR4_2_CB0
- AUD_IIR4_2_CB1
- AUD_IIR4_2_SEL
- AUD_IIR4_2_SHIFT
- AUD_INIT
- AUD_INIT_LD
- AUD_INT_A_GPCNT
- AUD_INT_A_GPCNT_CTL
- AUD_INT_A_LNGTH
- AUD_INT_A_MODE
- AUD_INT_BER_IRQ
- AUD_INT_B_GPCNT
- AUD_INT_B_GPCNT_CTL
- AUD_INT_B_LNGTH
- AUD_INT_B_MODE
- AUD_INT_DMA_CTL
- AUD_INT_DN_RISCI1
- AUD_INT_DN_RISCI2
- AUD_INT_DN_SYNC
- AUD_INT_MCHG_IRQ
- AUD_INT_OPC_ERR
- AUD_INT_RDS_DN_RISCI1
- AUD_INT_RDS_DN_RISCI2
- AUD_INT_RDS_DN_SYNC
- AUD_INT_UP_RISCI1
- AUD_INT_UP_RISCI2
- AUD_INT_UP_SYNC
- AUD_IN_EN
- AUD_IO_CTRL
- AUD_LOCK1
- AUD_LOCK2
- AUD_MAX_AVC_REF_LEVEL
- AUD_MAX_FRAGMENT
- AUD_MAX_FRAGMENT_SIZE
- AUD_MAX_SLOTSEL
- AUD_MIN_FRAGMENT
- AUD_MIN_FRAGMENT_SIZE
- AUD_MISC_SEROUT_LRCK_OE
- AUD_MISC_SEROUT_MCLK_OE
- AUD_MISC_SEROUT_OE_REG_BASE
- AUD_MISC_SEROUT_SCLK_OE
- AUD_MISC_SEROUT_SDAT_OE
- AUD_MISC_SEROUT_SPDIF_OE
- AUD_MODE
- AUD_MODE_CHG_TIMER
- AUD_MONO
- AUD_MOUT_AUD_PLL_USER
- AUD_MOUT_SCLK_AUD_I2S
- AUD_MOUT_SCLK_AUD_PCM
- AUD_MST_DIV
- AUD_MST_IN_COUNT
- AUD_MST_LRCLK
- AUD_MST_LRCLK_DIV
- AUD_MST_MCLK_DIV
- AUD_MST_MCLK_GATE
- AUD_MST_MCLK_MUX
- AUD_MST_MUX
- AUD_MST_SCLK
- AUD_MST_SCLK_DIV
- AUD_MST_SCLK_POST_EN
- AUD_MST_SCLK_PRE_EN
- AUD_MST_SYS_DIV
- AUD_MST_SYS_MUX
- AUD_MUX
- AUD_M_CTS_M_PROG_ENABLE
- AUD_M_CTS_M_VALUE_INDEX
- AUD_NAME_CMASTER
- AUD_NAME_DIECIN1
- AUD_NAME_EPCMOUT1
- AUD_NAME_EPCMOUT2
- AUD_NAME_EPCMOUT3
- AUD_NAME_EPCMOUT6
- AUD_NAME_HIECCOMPOUT1
- AUD_NAME_HIECOUT1
- AUD_NAME_HPCMOUT1
- AUD_NAME_IECCOMPOUT1
- AUD_NAME_IECIN1
- AUD_NAME_IECOUT1
- AUD_NAME_PCMIN1
- AUD_NAME_PCMIN2
- AUD_NAME_PCMIN3
- AUD_NAME_PCMOUT1
- AUD_NAME_PCMOUT2
- AUD_NAME_PCMOUT3
- AUD_NGPIO
- AUD_NICAM
- AUD_NICAM_L
- AUD_NICAM_STATUS1
- AUD_NICAM_STATUS2
- AUD_NR_CLK
- AUD_N_ENABLE
- AUD_OUT0_SEL
- AUD_OUT0_SHIFT
- AUD_OUT1_SEL
- AUD_OUT1_SHIFT
- AUD_OUTSYNC_EN
- AUD_OUTSYNC_PRE_EN
- AUD_PCLK_GATE
- AUD_PCM_AFIFO_AFIFO
- AUD_PCM_AFIFO_ASRC
- AUD_PCM_AFIFO_SRC
- AUD_PCM_CLOCK_MASTER_MODE
- AUD_PCM_CLOCK_SLAVE_MODE
- AUD_PCM_CLOCK_SOURCE
- AUD_PCM_EN
- AUD_PCM_EN_DISABLE
- AUD_PCM_EN_ENABLE
- AUD_PCM_EXTENDED_BCK_CYCLE_SYNC
- AUD_PCM_FMT
- AUD_PCM_FMT_EIAJ
- AUD_PCM_FMT_I2S
- AUD_PCM_FMT_PCM_MODE_A
- AUD_PCM_FMT_PCM_MODE_B
- AUD_PCM_MODE
- AUD_PCM_MODE_PCM_MODE_16K
- AUD_PCM_MODE_PCM_MODE_32K
- AUD_PCM_MODE_PCM_MODE_48K
- AUD_PCM_MODE_PCM_MODE_8K
- AUD_PCM_ONE_BCK_CYCLE_SYNC
- AUD_PCM_SYNC_TYPE
- AUD_PCM_WLEN
- AUD_PCM_WLEN_PCM_32_BCK_CYCLES
- AUD_PCM_WLEN_PCM_64_BCK_CYCLES
- AUD_PDET_SHIFT
- AUD_PDET_SRC
- AUD_PDF_DDS_CNST_BYTE0
- AUD_PDF_DDS_CNST_BYTE1
- AUD_PDF_DDS_CNST_BYTE2
- AUD_PHACC_FREQ_8LSB
- AUD_PHACC_FREQ_8MSB
- AUD_PHASE_FIX_CTL
- AUD_PILOT_BQD_1_K0
- AUD_PILOT_BQD_1_K1
- AUD_PILOT_BQD_1_K2
- AUD_PILOT_BQD_1_K3
- AUD_PILOT_BQD_1_K4
- AUD_PILOT_BQD_2_K0
- AUD_PILOT_BQD_2_K1
- AUD_PILOT_BQD_2_K2
- AUD_PILOT_BQD_2_K3
- AUD_PILOT_BQD_2_K4
- AUD_PLLDIV_1_1
- AUD_PLLDIV_1_2
- AUD_PLLDIV_1_3
- AUD_PLLDIV_2_3
- AUD_PLL_A1
- AUD_PLL_A2
- AUD_PLL_APLL
- AUD_PLL_CON0
- AUD_PLL_CON1
- AUD_PLL_CON2
- AUD_PLL_DDS
- AUD_PLL_EN
- AUD_PLL_F1
- AUD_PLL_F2
- AUD_PLL_FDET
- AUD_PLL_FRAC
- AUD_PLL_FREQ_DET
- AUD_PLL_HSC0
- AUD_PLL_IF_SEL
- AUD_PLL_IF_SHIFT
- AUD_PLL_INT
- AUD_PLL_JTAG
- AUD_PLL_LOCK
- AUD_PLL_PRESCALE
- AUD_PLL_RX0
- AUD_PLL_SHIFT
- AUD_PLL_SPMP
- AUD_PLL_SRC
- AUD_PLL_USB0
- AUD_POLY0_DDS_CONSTANT
- AUD_POLYPH80SCALEFAC
- AUD_QAM_MODE
- AUD_RATE_ADJ1
- AUD_RATE_ADJ2
- AUD_RATE_ADJ3
- AUD_RATE_ADJ4
- AUD_RATE_ADJ5
- AUD_RATE_THRES_DMD
- AUD_RATE_THRES_I2S
- AUD_RDSI_SEL
- AUD_RDSI_SHIFT
- AUD_RDSQ_SEL
- AUD_RDSQ_SHIFT
- AUD_RDS_ARRAY_SIZE
- AUD_RDS_LINES
- AUD_RESET_CLKTREE
- AUD_RESET_DDRARB
- AUD_RESET_EQDRC
- AUD_RESET_FRDDR_A
- AUD_RESET_FRDDR_B
- AUD_RESET_FRDDR_C
- AUD_RESET_LOOPBACK
- AUD_RESET_PDM
- AUD_RESET_POWDET
- AUD_RESET_RESAMPLE
- AUD_RESET_SPDIFIN
- AUD_RESET_SPDIFOUT
- AUD_RESET_SPDIFOUT_B
- AUD_RESET_TDMIN_A
- AUD_RESET_TDMIN_B
- AUD_RESET_TDMIN_C
- AUD_RESET_TDMIN_LB
- AUD_RESET_TDMOUT_A
- AUD_RESET_TDMOUT_B
- AUD_RESET_TDMOUT_C
- AUD_RESET_TOACODEC
- AUD_RESET_TODDR_A
- AUD_RESET_TODDR_B
- AUD_RESET_TODDR_C
- AUD_RESET_TOHDMITX
- AUD_RESET_TORAM
- AUD_RING_SIZE
- AUD_SAMPLE_RATE
- AUD_SAMPLE_RATE_176_4
- AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL
- AUD_SAMPLE_RATE_192
- AUD_SAMPLE_RATE_32
- AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL
- AUD_SAMPLE_RATE_44_1
- AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL
- AUD_SAMPLE_RATE_48
- AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL
- AUD_SAMPLE_RATE_88_2
- AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL
- AUD_SAMPLE_RATE_96
- AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL
- AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL
- AUD_SCLK_AUD_UART
- AUD_SCLK_DIV
- AUD_SCLK_I2S
- AUD_SCLK_PCM
- AUD_SCR_OUT_L_MASK
- AUD_SCR_OUT_L_MASK_SFT
- AUD_SCR_OUT_L_SFT
- AUD_SCR_OUT_R_MASK
- AUD_SCR_OUT_R_MASK_SFT
- AUD_SCR_OUT_R_SFT
- AUD_SDM_TEST_L_MASK
- AUD_SDM_TEST_L_MASK_SFT
- AUD_SDM_TEST_L_SFT
- AUD_SDM_TEST_R_MASK
- AUD_SDM_TEST_R_MASK_SFT
- AUD_SDM_TEST_R_SFT
- AUD_SLV_LRCLK_COUNT
- AUD_SLV_SCLK_COUNT
- AUD_SOFT_RESET
- AUD_SRC_A_DMA
- AUD_SRC_B_DMA
- AUD_SRC_C_DMA
- AUD_SRC_D_DMA
- AUD_SRC_E_DMA
- AUD_START_TIMER
- AUD_STATUS
- AUD_STS_CH_STS_MASK
- AUD_STS_IOC_IRQ_MASK
- AUD_TCON0_PDN_22M
- AUD_TCON0_PDN_24M
- AUD_TCON0_PDN_AFE
- AUD_TCON0_PDN_HDMI
- AUD_TCON0_PDN_SPDF
- AUD_TDM_LRLCK
- AUD_TDM_PAD_CTRL
- AUD_TDM_SCLK
- AUD_TDM_SCLK_MUX
- AUD_TDM_SCLK_POST_EN
- AUD_TDM_SCLK_PRE_EN
- AUD_THR_FR
- AUD_TOP_COMM_EXEC_ACTIVE
- AUD_TOP_COMM_EXEC_STOP
- AUD_TOP_COMM_EXEC__A
- AUD_TOP_COMM_EXEC__M
- AUD_TOP_COMM_EXEC__PRE
- AUD_TOP_COMM_EXEC__W
- AUD_TOP_COMM_MB_CTL_CTR_OFF
- AUD_TOP_COMM_MB_CTL_CTR_ON
- AUD_TOP_COMM_MB_CTL__B
- AUD_TOP_COMM_MB_CTL__M
- AUD_TOP_COMM_MB_CTL__PRE
- AUD_TOP_COMM_MB_CTL__W
- AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO
- AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC
- AUD_TOP_COMM_MB_MUX_CTRL_SAOUT
- AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS
- AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ
- AUD_TOP_COMM_MB_MUX_CTRL__B
- AUD_TOP_COMM_MB_MUX_CTRL__M
- AUD_TOP_COMM_MB_MUX_CTRL__PRE
- AUD_TOP_COMM_MB_MUX_CTRL__W
- AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO
- AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC
- AUD_TOP_COMM_MB_MUX_OBS_SAOUT
- AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS
- AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ
- AUD_TOP_COMM_MB_MUX_OBS__B
- AUD_TOP_COMM_MB_MUX_OBS__M
- AUD_TOP_COMM_MB_MUX_OBS__PRE
- AUD_TOP_COMM_MB_MUX_OBS__W
- AUD_TOP_COMM_MB_OBS_OBS_OFF
- AUD_TOP_COMM_MB_OBS_OBS_ON
- AUD_TOP_COMM_MB_OBS__B
- AUD_TOP_COMM_MB_OBS__M
- AUD_TOP_COMM_MB_OBS__PRE
- AUD_TOP_COMM_MB_OBS__W
- AUD_TOP_COMM_MB__A
- AUD_TOP_COMM_MB__M
- AUD_TOP_COMM_MB__PRE
- AUD_TOP_COMM_MB__W
- AUD_TOP_DEMOD_TBO_SEL__A
- AUD_TOP_DEMOD_TBO_SEL__M
- AUD_TOP_DEMOD_TBO_SEL__PRE
- AUD_TOP_DEMOD_TBO_SEL__W
- AUD_TOP_PDN_ADC_CTL_BIT
- AUD_TOP_PDN_AFE_CTL_BIT
- AUD_TOP_PDN_DAC_CTL_BIT
- AUD_TOP_PDN_RESERVED_BIT
- AUD_TOP_PWR_CLK_DIS_CTL_BIT
- AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY
- AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY
- AUD_TOP_TR_CTR_FIFO_EMPTY__B
- AUD_TOP_TR_CTR_FIFO_EMPTY__M
- AUD_TOP_TR_CTR_FIFO_EMPTY__PRE
- AUD_TOP_TR_CTR_FIFO_EMPTY__W
- AUD_TOP_TR_CTR_FIFO_FULL_EMPTY
- AUD_TOP_TR_CTR_FIFO_FULL_FULL
- AUD_TOP_TR_CTR_FIFO_FULL__B
- AUD_TOP_TR_CTR_FIFO_FULL__M
- AUD_TOP_TR_CTR_FIFO_FULL__PRE
- AUD_TOP_TR_CTR_FIFO_FULL__W
- AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED
- AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED
- AUD_TOP_TR_CTR_FIFO_LOCK__B
- AUD_TOP_TR_CTR_FIFO_LOCK__M
- AUD_TOP_TR_CTR_FIFO_LOCK__PRE
- AUD_TOP_TR_CTR_FIFO_LOCK__W
- AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY
- AUD_TOP_TR_CTR_FIFO_RD_RDY_READY
- AUD_TOP_TR_CTR_FIFO_RD_RDY__B
- AUD_TOP_TR_CTR_FIFO_RD_RDY__M
- AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE
- AUD_TOP_TR_CTR_FIFO_RD_RDY__W
- AUD_TOP_TR_CTR__A
- AUD_TOP_TR_CTR__M
- AUD_TOP_TR_CTR__PRE
- AUD_TOP_TR_CTR__W
- AUD_TOP_TR_MDE_FIFO_SIZE__B
- AUD_TOP_TR_MDE_FIFO_SIZE__M
- AUD_TOP_TR_MDE_FIFO_SIZE__PRE
- AUD_TOP_TR_MDE_FIFO_SIZE__W
- AUD_TOP_TR_MDE_RD_LOCK_LOCK
- AUD_TOP_TR_MDE_RD_LOCK_NORMAL
- AUD_TOP_TR_MDE_RD_LOCK__B
- AUD_TOP_TR_MDE_RD_LOCK__M
- AUD_TOP_TR_MDE_RD_LOCK__PRE
- AUD_TOP_TR_MDE_RD_LOCK__W
- AUD_TOP_TR_MDE__A
- AUD_TOP_TR_MDE__M
- AUD_TOP_TR_MDE__PRE
- AUD_TOP_TR_MDE__W
- AUD_TOP_TR_RD_REG_RESULT__B
- AUD_TOP_TR_RD_REG_RESULT__M
- AUD_TOP_TR_RD_REG_RESULT__PRE
- AUD_TOP_TR_RD_REG_RESULT__W
- AUD_TOP_TR_RD_REG__A
- AUD_TOP_TR_RD_REG__M
- AUD_TOP_TR_RD_REG__PRE
- AUD_TOP_TR_RD_REG__W
- AUD_TOP_TR_TIMER_CYCLES__B
- AUD_TOP_TR_TIMER_CYCLES__M
- AUD_TOP_TR_TIMER_CYCLES__PRE
- AUD_TOP_TR_TIMER_CYCLES__W
- AUD_TOP_TR_TIMER__A
- AUD_TOP_TR_TIMER__M
- AUD_TOP_TR_TIMER__PRE
- AUD_TOP_TR_TIMER__W
- AUD_TRIPHASE
- AUD_TX_LCH_RPT
- AUD_TX_LCH_RPT_NO_REPEAT
- AUD_TX_LCH_RPT_REPEAT
- AUD_VBT_16K_MODE
- AUD_VBT_16K_MODE_DISABLE
- AUD_VBT_16K_MODE_ENABLE
- AUD_VER_NUM
- AUD_VOLUME_DB_MAX
- AUD_VOLUME_DB_MIN
- AUD_VOLUME_ZERO_DB
- AUD_VOL_CTL
- AUD_VOL_FADE_TIME
- AUD_VOL_INIT
- AUD_VOL_MAX
- AUD_XDFP_DRAM_1K_D__B
- AUD_XDFP_DRAM_1K_D__M
- AUD_XDFP_DRAM_1K_D__PRE
- AUD_XDFP_DRAM_1K_D__W
- AUD_XDFP_DRAM_1K__A
- AUD_XDFP_DRAM_1K__M
- AUD_XDFP_DRAM_1K__PRE
- AUD_XDFP_DRAM_1K__W
- AUD_XDFP_PRAM_4K_D__B
- AUD_XDFP_PRAM_4K_D__M
- AUD_XDFP_PRAM_4K_D__PRE
- AUD_XDFP_PRAM_4K_D__W
- AUD_XDFP_PRAM_4K__A
- AUD_XDFP_PRAM_4K__M
- AUD_XDFP_PRAM_4K__PRE
- AUD_XDFP_PRAM_4K__W
- AUD_XFP_DRAM_1K_D__B
- AUD_XFP_DRAM_1K_D__M
- AUD_XFP_DRAM_1K_D__PRE
- AUD_XFP_DRAM_1K_D__W
- AUD_XFP_DRAM_1K__A
- AUD_XFP_DRAM_1K__M
- AUD_XFP_DRAM_1K__PRE
- AUD_XFP_DRAM_1K__W
- AUD_XFP_PRAM_4K_D__B
- AUD_XFP_PRAM_4K_D__M
- AUD_XFP_PRAM_4K_D__PRE
- AUD_XFP_PRAM_4K_D__W
- AUD_XFP_PRAM_4K__A
- AUD_XFP_PRAM_4K__M
- AUD_XFP_PRAM_4K__PRE
- AUD_XFP_PRAM_4K__W
- AUD_X_PROG
- AUD_Y_PROG
- AUGMENT_SIZE
- AUI
- AUIPC_BASIC
- AUIPC_OFFSET_MASK
- AUIPC_PAD
- AUI_LOOPBACK
- AUI_ON
- AUI_ONLY
- AUI_SUSPECT
- AUO_PIXCIR_CALIBRATE
- AUO_PIXCIR_EEPROM_CALIB_X_LEN
- AUO_PIXCIR_EEPROM_CALIB_Y_LEN
- AUO_PIXCIR_INT_COMP_COORD
- AUO_PIXCIR_INT_ENABLE
- AUO_PIXCIR_INT_MODE_MASK
- AUO_PIXCIR_INT_PERIODICAL
- AUO_PIXCIR_INT_POL_HIGH
- AUO_PIXCIR_INT_RELEASE
- AUO_PIXCIR_INT_TOUCH_IND
- AUO_PIXCIR_INT_TPNUM_MASK
- AUO_PIXCIR_INT_TPNUM_SHIFT
- AUO_PIXCIR_MAX_AREA
- AUO_PIXCIR_PENUP_TIMEOUT_MS
- AUO_PIXCIR_POWER_ACTIVE
- AUO_PIXCIR_POWER_ALLOW_SLEEP
- AUO_PIXCIR_POWER_DEEP_SLEEP
- AUO_PIXCIR_POWER_IDLE_TIME
- AUO_PIXCIR_POWER_MASK
- AUO_PIXCIR_POWER_SLEEP
- AUO_PIXCIR_RAW_DATA_X_LEN
- AUO_PIXCIR_RAW_DATA_Y_LEN
- AUO_PIXCIR_REG_CALIBRATE
- AUO_PIXCIR_REG_EEPROM_CALIB_X
- AUO_PIXCIR_REG_EEPROM_CALIB_Y
- AUO_PIXCIR_REG_INT_SETTING
- AUO_PIXCIR_REG_INT_WIDTH
- AUO_PIXCIR_REG_POWER_MODE
- AUO_PIXCIR_REG_RAW_DATA_X
- AUO_PIXCIR_REG_RAW_DATA_Y
- AUO_PIXCIR_REG_STRENGTH
- AUO_PIXCIR_REG_STRENGTH_X1_LSB
- AUO_PIXCIR_REG_STRENGTH_X1_MSB
- AUO_PIXCIR_REG_TOUCHAREA_X1
- AUO_PIXCIR_REG_TOUCHAREA_X2
- AUO_PIXCIR_REG_TOUCHAREA_Y1
- AUO_PIXCIR_REG_TOUCHAREA_Y2
- AUO_PIXCIR_REG_VERSION
- AUO_PIXCIR_REG_X1_LSB
- AUO_PIXCIR_REG_X1_MSB
- AUO_PIXCIR_REG_X2_LSB
- AUO_PIXCIR_REG_X2_MSB
- AUO_PIXCIR_REG_X_SENSITIVITY
- AUO_PIXCIR_REG_Y1_LSB
- AUO_PIXCIR_REG_Y1_MSB
- AUO_PIXCIR_REG_Y2_LSB
- AUO_PIXCIR_REG_Y2_MSB
- AUO_PIXCIR_REG_Y_SENSITIVITY
- AUO_PIXCIR_REPORT_POINTS
- AUO_PIXCIR_STRENGTH_ENABLE
- AUREON_AC97_ADDR
- AUREON_AC97_COMMIT
- AUREON_AC97_DATA_HIGH
- AUREON_AC97_DATA_LOW
- AUREON_AC97_DATA_MASK
- AUREON_AC97_RESET
- AUREON_AC97_STEREO
- AUREON_CS8415_CS
- AUREON_DEVICE_DESC
- AUREON_DIGITAL_SEL1
- AUREON_HP_SEL
- AUREON_SPI_CLK
- AUREON_SPI_MISO
- AUREON_SPI_MOSI
- AUREON_WM_CS
- AUREON_WM_RESET
- AUREON_WM_RW
- AURICAL_USB_PID
- AURORA_ACR_ECC_EN
- AURORA_ACR_FORCE_WRITE_BACK_POLICY
- AURORA_ACR_FORCE_WRITE_POLICY_DIS
- AURORA_ACR_FORCE_WRITE_POLICY_MASK
- AURORA_ACR_FORCE_WRITE_POLICY_OFFSET
- AURORA_ACR_FORCE_WRITE_THRO_POLICY
- AURORA_ACR_PARITY_EN
- AURORA_ACR_REPLACEMENT_MASK
- AURORA_ACR_REPLACEMENT_OFFSET
- AURORA_ACR_REPLACEMENT_TYPE_LFSR
- AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU
- AURORA_ACR_REPLACEMENT_TYPE_WAYRR
- AURORA_CACHE_ID
- AURORA_CLEAN_RANGE_REG
- AURORA_CTRL_FW
- AURORA_ERR_ADDR_CAP_ADDR_MASK
- AURORA_ERR_ADDR_CAP_REG
- AURORA_ERR_ATTR_CAP_REG
- AURORA_ERR_ATTR_CAP_VALID
- AURORA_ERR_ATTR_CAP_VALID_OFF
- AURORA_ERR_ATTR_ERR_MSK
- AURORA_ERR_ATTR_ERR_OFF
- AURORA_ERR_ATTR_SRC_MSK
- AURORA_ERR_ATTR_SRC_OFF
- AURORA_ERR_ATTR_TXN_MSK
- AURORA_ERR_ATTR_TXN_OFF
- AURORA_ERR_CNT_CE_MASK
- AURORA_ERR_CNT_CE_OFFSET
- AURORA_ERR_CNT_CLR
- AURORA_ERR_CNT_CLR_OFFSET
- AURORA_ERR_CNT_REG
- AURORA_ERR_CNT_UE_MASK
- AURORA_ERR_CNT_UE_OFFSET
- AURORA_ERR_INJECT_CTL_ADDR_MASK
- AURORA_ERR_INJECT_CTL_EN_ECC
- AURORA_ERR_INJECT_CTL_EN_MASK
- AURORA_ERR_INJECT_CTL_EN_PARITY
- AURORA_ERR_INJECT_CTL_REG
- AURORA_ERR_INJECT_MASK_REG
- AURORA_ERR_WAY_CAP_REG
- AURORA_ERR_WAY_CAP_WAY_MASK
- AURORA_ERR_WAY_CAP_WAY_OFFSET
- AURORA_ERR_WAY_IDX_MSK
- AURORA_ERR_WAY_IDX_OFF
- AURORA_FLUSH_PHY_ADDR_REG
- AURORA_FLUSH_RANGE_REG
- AURORA_INVAL_RANGE_REG
- AURORA_MAJOR
- AURORA_MAX_RANGE_SIZE
- AURORA_RANGE_BASE_ADDR_REG
- AURORA_SYNC_REG
- AURORA_WAY_SIZE_SHIFT
- AUSTRALIA
- AUSTRALIA_HOP_MOD
- AUTHENC
- AUTHENC_CTX
- AUTHENC_DESC_JOB_IO_LEN
- AUTHENTICATED
- AUTHENTICATE_MESSAGE
- AUTHENTICATION_RESPONSE_TIME_OUT
- AUTHENTICATION_TYPE
- AUTHENTICATOR_KEY
- AUTHENTIC_TYPE
- AUTHMETHOD
- AUTHOR
- AUTH_0_ON
- AUTH_1_ON
- AUTH_ABORT_EV
- AUTH_AES_SEL_SHIFT
- AUTH_ALG_AES
- AUTH_ALG_KASUMI
- AUTH_ALG_LEAP
- AUTH_ALG_MASK
- AUTH_ALG_NONE
- AUTH_ALG_OPEN_SYSTEM
- AUTH_ALG_SHA
- AUTH_ALG_SHARED_KEY
- AUTH_ALG_SHIFT
- AUTH_ALG_SNOW3G
- AUTH_ALG_ZUC
- AUTH_ALLOW_UNENCRYPTED
- AUTH_BUSY_SHIFT
- AUTH_CLR_KEYS
- AUTH_DISABLED
- AUTH_ENABLED
- AUTH_ENCRYPT
- AUTH_EVENT
- AUTH_EVEN_TO
- AUTH_FAILED
- AUTH_FIRST_SHIFT
- AUTH_FORCE_CLR_INPUTCTR
- AUTH_GMAC
- AUTH_IGNORE
- AUTH_INVALID
- AUTH_KASUMI_SEL_SHIFT
- AUTH_KEY
- AUTH_KEY_SIZE_MASK
- AUTH_KEY_SIZE_SHIFT
- AUTH_KEY_SZ_AES128
- AUTH_KEY_SZ_AES256
- AUTH_LAST_SHIFT
- AUTH_LEAP
- AUTH_LINK_AUTHENTICATED
- AUTH_LINK_TYPE
- AUTH_MD5
- AUTH_MODE_CCM
- AUTH_MODE_CMAC
- AUTH_MODE_HASH
- AUTH_MODE_HMAC
- AUTH_MODE_MASK
- AUTH_MODE_SHIFT
- AUTH_NONCE_NUM_WORDS_MASK
- AUTH_NONCE_NUM_WORDS_SHIFT
- AUTH_NULL
- AUTH_ODD_TO
- AUTH_OPEN
- AUTH_POS_AFTER
- AUTH_POS_BEFORE
- AUTH_POS_MASK
- AUTH_POS_SHIFT
- AUTH_REQ_MASK
- AUTH_RESULT_RDY_EV
- AUTH_RETRIES_TIME
- AUTH_SHA1
- AUTH_SHA2_SHA224
- AUTH_SHA2_SHA256
- AUTH_SHA2_SHA384
- AUTH_SHA2_SHA512
- AUTH_SHAREDKEY
- AUTH_SHARED_KEY
- AUTH_SIZE_ENUM_10_BYTES
- AUTH_SIZE_ENUM_11_BYTES
- AUTH_SIZE_ENUM_12_BYTES
- AUTH_SIZE_ENUM_13_BYTES
- AUTH_SIZE_ENUM_14_BYTES
- AUTH_SIZE_ENUM_15_BYTES
- AUTH_SIZE_ENUM_16_BYTES
- AUTH_SIZE_ENUM_1_BYTES
- AUTH_SIZE_ENUM_2_BYTES
- AUTH_SIZE_ENUM_3_BYTES
- AUTH_SIZE_ENUM_4_BYTES
- AUTH_SIZE_ENUM_5_BYTES
- AUTH_SIZE_ENUM_6_BYTES
- AUTH_SIZE_ENUM_7_BYTES
- AUTH_SIZE_ENUM_8_BYTES
- AUTH_SIZE_ENUM_9_BYTES
- AUTH_SIZE_MASK
- AUTH_SIZE_SHA1
- AUTH_SIZE_SHA256
- AUTH_SIZE_SHIFT
- AUTH_SNOW3G_SEL_SHIFT
- AUTH_TYPE_ANY
- AUTH_TYPE_CRC32
- AUTH_TYPE_FT_RSN
- AUTH_TYPE_FT_RSN_PSK
- AUTH_TYPE_HMAC_MD5
- AUTH_TYPE_HMAC_SHA1
- AUTH_TYPE_HMAC_SHA256
- AUTH_TYPE_MAX
- AUTH_TYPE_MD5
- AUTH_TYPE_OPEN_SYSTEM
- AUTH_TYPE_RESERVED
- AUTH_TYPE_RSN
- AUTH_TYPE_RSN_PSK
- AUTH_TYPE_SHA1
- AUTH_TYPE_SHA256
- AUTH_TYPE_SHARED_KEY
- AUTH_TYPE_SSL_HMAC_MD5
- AUTH_TYPE_SSL_HMAC_SHA1
- AUTH_TYPE_SSL_HMAC_SHA256
- AUTH_TYPE_TCP_CHECKSUM
- AUTH_TYPE_WAPI_WAI_CERTIFICATE
- AUTH_TYPE_WAPI_WAI_PSK
- AUTH_TYPE_WPA
- AUTH_TYPE_WPA_PSK
- AUTH_WORK_RETRIES_TIME
- AUTH_ZUC_SEL_SHIFT
- AUTO
- AUTOCAL_MODE_AUTOCENTER
- AUTOCAL_MODE_AUTOREPLICATE
- AUTOCAL_MODE_AUTOSCALE
- AUTOCAL_MODE_OFF
- AUTOCHANNELS_ACTIVE
- AUTOCHANNELS_DISABLED
- AUTOCHANNELS_ENABLED
- AUTOCOMMIT_BLOCKS_PMEM
- AUTOCOMMIT_BLOCKS_SSD
- AUTOCOMMIT_MSEC
- AUTOCONF
- AUTOCONFIG_REG
- AUTODET_EN
- AUTODIRECTION
- AUTOECHO
- AUTOEOM
- AUTOFC
- AUTOFS_DEVICE_NAME
- AUTOFS_DEV_IOCTL_ASKUMOUNT
- AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD
- AUTOFS_DEV_IOCTL_CATATONIC
- AUTOFS_DEV_IOCTL_CATATONIC_CMD
- AUTOFS_DEV_IOCTL_CLOSEMOUNT
- AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD
- AUTOFS_DEV_IOCTL_EXPIRE
- AUTOFS_DEV_IOCTL_EXPIRE_CMD
- AUTOFS_DEV_IOCTL_FAIL
- AUTOFS_DEV_IOCTL_FAIL_CMD
- AUTOFS_DEV_IOCTL_IOC_COUNT
- AUTOFS_DEV_IOCTL_IOC_FIRST
- AUTOFS_DEV_IOCTL_ISMOUNTPOINT
- AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD
- AUTOFS_DEV_IOCTL_OPENMOUNT
- AUTOFS_DEV_IOCTL_OPENMOUNT_CMD
- AUTOFS_DEV_IOCTL_PROTOSUBVER
- AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD
- AUTOFS_DEV_IOCTL_PROTOVER
- AUTOFS_DEV_IOCTL_PROTOVER_CMD
- AUTOFS_DEV_IOCTL_READY
- AUTOFS_DEV_IOCTL_READY_CMD
- AUTOFS_DEV_IOCTL_REQUESTER
- AUTOFS_DEV_IOCTL_REQUESTER_CMD
- AUTOFS_DEV_IOCTL_SETPIPEFD
- AUTOFS_DEV_IOCTL_SETPIPEFD_CMD
- AUTOFS_DEV_IOCTL_SIZE
- AUTOFS_DEV_IOCTL_TIMEOUT
- AUTOFS_DEV_IOCTL_TIMEOUT_CMD
- AUTOFS_DEV_IOCTL_VERSION
- AUTOFS_DEV_IOCTL_VERSION_CMD
- AUTOFS_DEV_IOCTL_VERSION_MAJOR
- AUTOFS_DEV_IOCTL_VERSION_MINOR
- AUTOFS_EXP_FORCED
- AUTOFS_EXP_IMMEDIATE
- AUTOFS_EXP_LEAVES
- AUTOFS_EXP_NORMAL
- AUTOFS_INF_EXPIRING
- AUTOFS_INF_PENDING
- AUTOFS_INF_WANT_EXPIRE
- AUTOFS_IOCTL
- AUTOFS_IOC_ASKUMOUNT
- AUTOFS_IOC_ASKUMOUNT_CMD
- AUTOFS_IOC_CATATONIC
- AUTOFS_IOC_CATATONIC_CMD
- AUTOFS_IOC_COUNT
- AUTOFS_IOC_EXPIRE
- AUTOFS_IOC_EXPIRE_CMD
- AUTOFS_IOC_EXPIRE_MULTI
- AUTOFS_IOC_EXPIRE_MULTI_CMD
- AUTOFS_IOC_FAIL
- AUTOFS_IOC_FAIL_CMD
- AUTOFS_IOC_FIRST
- AUTOFS_IOC_PROTOSUBVER
- AUTOFS_IOC_PROTOSUBVER_CMD
- AUTOFS_IOC_PROTOVER
- AUTOFS_IOC_PROTOVER_CMD
- AUTOFS_IOC_READY
- AUTOFS_IOC_READY_CMD
- AUTOFS_IOC_SETTIMEOUT
- AUTOFS_IOC_SETTIMEOUT32
- AUTOFS_IOC_SETTIMEOUT_CMD
- AUTOFS_MAX_PROTO_VERSION
- AUTOFS_MINOR
- AUTOFS_MIN_PROTO_VERSION
- AUTOFS_PROTO_SUBVERSION
- AUTOFS_PROTO_VERSION
- AUTOFS_SBI_CATATONIC
- AUTOFS_SBI_IGNORE
- AUTOFS_SBI_MAGIC
- AUTOFS_SBI_STRICTEXPIRE
- AUTOFS_SUPER_MAGIC
- AUTOFS_TYPE_ANY
- AUTOFS_TYPE_DIRECT
- AUTOFS_TYPE_INDIRECT
- AUTOFS_TYPE_OFFSET
- AUTOGAIN_IGNORE_FRAMES
- AUTOIDLE
- AUTOIDLE_LOW
- AUTOINC
- AUTOINCREMENT
- AUTOINC_ADDR
- AUTOINC_DSTX
- AUTOINC_DSTY
- AUTOINCflag
- AUTOLOAD_CFG_BASE
- AUTOLOAD_DONE
- AUTOLOAD_EEPROM
- AUTOLOAD_EFUSE
- AUTOLOAD_ENABLE
- AUTOMATIC_CSTATE_CONVERSION
- AUTOMEDIA
- AUTOMIN
- AUTOMUTE
- AUTONEGO_LINK_TIMER
- AUTONEG_ADVERTISE_10_100_ALL
- AUTONEG_ADVERTISE_10_ALL
- AUTONEG_ADVERTISE_SPEED_DEFAULT
- AUTONEG_ADVERTISE_SPEED_DEFAULT_2500
- AUTONEG_ADV_DEFAULT
- AUTONEG_ADV_MASK
- AUTONEG_BAM
- AUTONEG_CL37
- AUTONEG_CL73
- AUTONEG_COMPLETE
- AUTONEG_DISABLE
- AUTONEG_ENABLE
- AUTONEG_FAST_TIMERS
- AUTONEG_FLOW_CTRL
- AUTONEG_INVALID
- AUTONEG_PARALLEL
- AUTONEG_REMOTE_PHY
- AUTONEG_SGMII_FIBER_AUTODET
- AUTONEG_SPEED
- AUTONEG_TRIES
- AUTONOMOUS_RESET
- AUTOPOLL0
- AUTOPOLL0_BITS
- AUTOPOLL1
- AUTOPOLL1_BITS
- AUTOPOLL2
- AUTOPOLL2_BITS
- AUTOPOLL3
- AUTOPOLL3_BITS
- AUTOPOLL4
- AUTOPOLL4_BITS
- AUTOPOLL5
- AUTOPOLL5_BITS
- AUTOPST
- AUTOP_CYCLE_NSEC
- AUTOP_HDD
- AUTOP_INVALID
- AUTOP_SSD_DFL
- AUTOP_SSD_FAST
- AUTOP_SSD_QD1
- AUTORLS
- AUTORMOD
- AUTORTS
- AUTOSCALE_ON_SS_CLEAR
- AUTOSCSI_BUSY
- AUTOSCSI_RESTART
- AUTOSCSI_START
- AUTOSELECT
- AUTOSEL_TIMING_SEL
- AUTOSENSE_DEVID
- AUTOSENSE_DEVID_MASK
- AUTOSENSE_SIZE_IN_MB
- AUTOSUSPEND_DELAY
- AUTOSUSPEND_DELAY_MS
- AUTOSUSPEND_TIMEOUT
- AUTOTERM
- AUTOTXF
- AUTOVALIDATE
- AUTOWAKEUP_CFG
- AUTOWAKEUP_CFG_AUTOWAKE
- AUTOWAKEUP_CFG_AUTO_LEAD_TIME
- AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
- AUTO_ACK_FRAMEPEND
- AUTO_ACT_WINDOW
- AUTO_ALL_MODES
- AUTO_ANNEX_A
- AUTO_ANNEX_B
- AUTO_ASSIGN
- AUTO_ATN
- AUTO_AUI_10BASET
- AUTO_BLK_ON_OFF
- AUTO_CALIBRATION
- AUTO_CAL_CONFIG
- AUTO_CAL_CONFIG_ENABLE
- AUTO_CAL_CONFIG_START
- AUTO_CAL_STATUS
- AUTO_CAL_STATUS_ACTIVE
- AUTO_CFG_MAX_INS
- AUTO_CFG_MAX_OUTS
- AUTO_CLKLANE_CTRL
- AUTO_CLK_GATE_EN
- AUTO_CLK_GATE_EN_OFST
- AUTO_CMD0
- AUTO_CMD1
- AUTO_CMD2
- AUTO_CMD23
- AUTO_COMMAND_GO
- AUTO_COMMAND_PHASE
- AUTO_CONFIG_CTRL_ADDR
- AUTO_CONFIG_LSL_ADDR
- AUTO_CONFIG_TL_ADDR
- AUTO_CONFIG_USL_ADDR
- AUTO_CONTOUR_FORMATTER
- AUTO_CORR_CCK_MIN_VAL_DEF
- AUTO_CORR_MAX_TH_CCK
- AUTO_CORR_STEP_CCK
- AUTO_CORR_STEP_OFDM
- AUTO_CSC_DISABLE
- AUTO_CSC_ENABLE
- AUTO_CTXSW_ENABLE
- AUTO_DEC
- AUTO_DELINK_EN
- AUTO_DETECT_RES
- AUTO_DETECT_SFP_SUPPORT
- AUTO_ENAB
- AUTO_EOM_RST
- AUTO_EXP_MODE
- AUTO_FB_0
- AUTO_FB_1
- AUTO_FB_NONE
- AUTO_FW_RESET_DISABLED
- AUTO_FW_RESET_ENABLED
- AUTO_GLOW
- AUTO_GUP
- AUTO_HORZ_RATIO
- AUTO_IMMED
- AUTO_INC
- AUTO_INCREMENT_IND_0
- AUTO_INT
- AUTO_INVLD_EN
- AUTO_IRQS
- AUTO_LLT_INIT_LLT
- AUTO_MASK
- AUTO_MEASURE
- AUTO_MODE
- AUTO_MODE_TIME_CONF_REG
- AUTO_MSGIN_00_OR_04
- AUTO_MSGIN_02
- AUTO_MSGIN_03
- AUTO_NEG_BITS
- AUTO_NEG_BUSY
- AUTO_NEG_CNF_OFFSET
- AUTO_NEG_COMPLETE
- AUTO_NEG_ENABLE
- AUTO_NEG_MASK
- AUTO_NET_MII_MODE
- AUTO_NET_SMII_MODE
- AUTO_OFF
- AUTO_ON
- AUTO_PAD_XMIT
- AUTO_PARAMETER
- AUTO_PARAMETER_VALID
- AUTO_PG_EN
- AUTO_PIN_AUX
- AUTO_PIN_CD
- AUTO_PIN_HP_OUT
- AUTO_PIN_LAST
- AUTO_PIN_LINE_IN
- AUTO_PIN_LINE_OUT
- AUTO_PIN_MIC
- AUTO_PIN_SPEAKER_OUT
- AUTO_POLARITY_DISABLE
- AUTO_PREAMBLE
- AUTO_PWG_ENABLE
- AUTO_PWM_MODE
- AUTO_PWRUP_EN
- AUTO_PWR_UP
- AUTO_RATE_00
- AUTO_RATE_05
- AUTO_RATE_10
- AUTO_RATE_20
- AUTO_RATE_IND
- AUTO_READ_DONE_TIMEOUT
- AUTO_READ_INT_REG
- AUTO_RECEIVE_N
- AUTO_REQSENSE
- AUTO_RE_ENABLE_INT
- AUTO_RSP_CFG
- AUTO_RSP_CFG_ACK_CTS_PSM_BIT
- AUTO_RSP_CFG_AR_PREAMBLE
- AUTO_RSP_CFG_AUTORESPONDER
- AUTO_RSP_CFG_BAC_ACK_POLICY
- AUTO_RSP_CFG_CTS_40_MMODE
- AUTO_RSP_CFG_CTS_40_MREF
- AUTO_RSP_CFG_DUAL_CTS_EN
- AUTO_RST_RX
- AUTO_RX_DMA
- AUTO_SEL_ENABLE
- AUTO_STATUS_MASK
- AUTO_STRIP_RCV
- AUTO_SUSPEND_TIMER
- AUTO_TEMP_MAX_FROM_REG
- AUTO_TEMP_MAX_TO_REG
- AUTO_TEMP_MIN_FROM_REG
- AUTO_TEMP_MIN_FROM_REG_DEG
- AUTO_TEMP_MIN_TO_REG
- AUTO_TEMP_OFF_FROM_REG
- AUTO_TEMP_RANGE_FROM_REG
- AUTO_TERM_CAL_DIS
- AUTO_TX_TURNAROUND
- AUTO_TxFLAG
- AUTO_UPDATE_INTERVAL
- AUTO_VBUS_IN_CURR_LIM_SHIFT
- AUTO_VCS
- AUTO_VERT_RATIO
- AUTO_WAKEUP
- AUTO_WHT_ON_OFF
- AUTOnRTS
- AUVI_INPUT
- AUX0_SEL_SDP0
- AUX0_SEL_SDP1
- AUX0_SEL_SDP2
- AUX0_SEL_SDP3
- AUX0_TS_SDP_EN
- AUX1
- AUX1_LS_DONE_INTERRUPT
- AUX1_SEL_SDP0
- AUX1_SEL_SDP1
- AUX1_SEL_SDP2
- AUX1_SEL_SDP3
- AUX1_SW_DONE_INTERRUPT
- AUX1_TS_SDP_EN
- AUX2_LS_DONE_INTERRUPT
- AUX2_SW_DONE_INTERRUPT
- AUX3
- AUX3_LS_DONE_INTERRUPT
- AUX3_SW_DONE_INTERRUPT
- AUX3_YC
- AUX4_LS_DONE_INTERRUPT
- AUX4_SW_DONE_INTERRUPT
- AUX5_LS_DONE_INTERRUPT
- AUX5_SW_DONE_INTERRUPT
- AUX6_LS_DONE_INTERRUPT
- AUX6_SW_DONE_INTERRUPT
- AUXADC_CON1_CLR_V
- AUXADC_CON1_SET_V
- AUXADC_CON2_V
- AUXADC_DATA
- AUXCOREBOOT0_OFFSET
- AUXCOREBOOT1_OFFSET
- AUXCR_MDPPS
- AUXDATA
- AUXDA_DEBOUNCING_CLK
- AUXDA_POLARITY
- AUXDA_SE_EN
- AUXENT
- AUXESZ
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK
- AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT
- AUXIO
- AUXIO_AUX1_FDENS
- AUXIO_AUX1_FTCNT
- AUXIO_AUX1_LED
- AUXIO_AUX1_LTE
- AUXIO_AUX1_MASK
- AUXIO_AUX1_MMUX
- AUXIO_AUX2_MASK
- AUXIO_AUX2_PFAILCLR
- AUXIO_AUX2_PFAILDET
- AUXIO_AUX2_PWR_OFF
- AUXIO_EDGE_ON
- AUXIO_FLPY_DCHG
- AUXIO_FLPY_DENS
- AUXIO_FLPY_DSEL
- AUXIO_FLPY_EJCT
- AUXIO_FLPY_TCNT
- AUXIO_LED
- AUXIO_LED_OFF
- AUXIO_LED_ON
- AUXIO_LINK_TEST
- AUXIO_LTE_OFF
- AUXIO_LTE_ON
- AUXIO_ORMEIN
- AUXIO_ORMEIN4M
- AUXIO_PCIO_CPWR_OFF
- AUXIO_PCIO_LED
- AUXIO_PCIO_SPWR_OFF
- AUXIO_POWER_CLEAR_FAILURE
- AUXIO_POWER_DETECT_FAILURE
- AUXIO_POWER_OFF
- AUXIO_PRIMARY_BASE
- AUXIO_TYPE_EBUS
- AUXIO_TYPE_NODEV
- AUXIO_TYPE_SBUS
- AUXMEMSIZE
- AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK
- AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT
- AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK
- AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT
- AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK
- AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT
- AUXOFF
- AUXOUTDIS
- AUXPAGE
- AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK
- AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT
- AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK
- AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT
- AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK
- AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT
- AUXTRACE_INIT_NR_QUEUES
- AUXV_CNT
- AUXV_DESC_SZ
- AUX_ADDRESS_LEN
- AUX_ADDR_15_8
- AUX_ADDR_19_16
- AUX_ADDR_7_0
- AUX_ANT
- AUX_ANT_CGCS_RX
- AUX_ANT_CG_TRX
- AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK
- AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT
- AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK
- AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT
- AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK
- AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT
- AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK
- AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT
- AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK
- AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT
- AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK
- AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT
- AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK
- AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT
- AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK
- AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT
- AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK
- AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT
- AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK
- AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT
- AUX_BASE_MASK
- AUX_BIT_PERIOD_EXPECTED_DELAY
- AUX_BLOCK
- AUX_BURST_SIZE
- AUX_BUSY
- AUX_BYTES
- AUX_CHANNEL_A
- AUX_CHANNEL_B
- AUX_CHANNEL_C
- AUX_CHANNEL_D
- AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
- AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY
- AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN
- AUX_CHANNEL_OPERATION_FAILED_TIMEOUT
- AUX_CHANNEL_OPERATION_SUCCEEDED
- AUX_CHN_CSC_OFFSET
- AUX_CH_A
- AUX_CH_B
- AUX_CH_BUFFER_SIZE
- AUX_CH_C
- AUX_CH_CTL
- AUX_CH_D
- AUX_CH_DATA1
- AUX_CH_DATA2
- AUX_CH_DATA3
- AUX_CH_DATA4
- AUX_CH_DATA5
- AUX_CH_E
- AUX_CH_F
- AUX_CH_LANE
- AUX_CLK_ACTIVE_SEL_MASK
- AUX_CLK_EN
- AUX_CMD_FIFO_LEN
- AUX_CMD_I2C_MAX
- AUX_CMD_LEN
- AUX_CMD_NATIVE_MAX
- AUX_CMD_REQ
- AUX_CMD_SEND
- AUX_COMMON_REG_LIST
- AUX_COMMON_REG_LIST0
- AUX_CONTROL
- AUX_CONTROL_STATUS
- AUX_CONTROL__AUX_DEGLITCH_EN_MASK
- AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT
- AUX_CONTROL__AUX_EN_MASK
- AUX_CONTROL__AUX_EN__SHIFT
- AUX_CONTROL__AUX_HPD_SEL_MASK
- AUX_CONTROL__AUX_HPD_SEL__SHIFT
- AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK
- AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT
- AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK
- AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT
- AUX_CONTROL__AUX_LS_READ_EN_MASK
- AUX_CONTROL__AUX_LS_READ_EN__SHIFT
- AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK
- AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT
- AUX_CONTROL__AUX_MODE_DET_EN_MASK
- AUX_CONTROL__AUX_MODE_DET_EN__SHIFT
- AUX_CONTROL__AUX_RESET_DONE_MASK
- AUX_CONTROL__AUX_RESET_DONE__SHIFT
- AUX_CONTROL__AUX_RESET_MASK
- AUX_CONTROL__AUX_RESET__SHIFT
- AUX_CONTROL__AUX_TEST_MODE_MASK
- AUX_CONTROL__AUX_TEST_MODE__SHIFT
- AUX_CONTROL__SPARE_0_MASK
- AUX_CONTROL__SPARE_0__SHIFT
- AUX_CONTROL__SPARE_1_MASK
- AUX_CONTROL__SPARE_1__SHIFT
- AUX_CORE_BOOT0_GP_RELEASE
- AUX_CORE_BOOT0_HS_RELEASE
- AUX_CORE_BOOT0_PA
- AUX_COUNT
- AUX_CTL_MISC_CTL
- AUX_CTL_MISC_CTL_AUTOMDIX
- AUX_CTL_MISC_CTL_WIRESPEED
- AUX_CTL_MISC_CTL_WR
- AUX_CTL_MSG_LENGTH
- AUX_CTRL
- AUX_CTRL_FORCE_PCIE_CLK
- AUX_CTRL_WAKE_PCIE_EN
- AUX_DATA
- AUX_DBG
- AUX_DEFER_RETRY_COUNTER
- AUX_DEGLITCH_EN
- AUX_DET_EN
- AUX_DITHER_OFFSET
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT
- AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK
- AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT
- AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK
- AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT
- AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK
- AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT
- AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK
- AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT
- AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK
- AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT
- AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK
- AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT
- AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK
- AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT
- AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK
- AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT
- AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK
- AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK
- AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT
- AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK
- AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT
- AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK
- AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT
- AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK
- AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
- AUX_EN
- AUX_EQ1_SEL
- AUX_EQ2_SEL
- AUX_EQ_SEL_MASK
- AUX_EQ_SEL_SHIFT
- AUX_ERR
- AUX_EXEC_CTRL
- AUX_FUNC_EN_N
- AUX_GL_CSC_OFFSET
- AUX_GL_OFFSET
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK
- AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK
- AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT
- AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK
- AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK
- AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT
- AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT
- AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK
- AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT
- AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK
- AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK
- AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT
- AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK
- AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT
- AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK
- AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK
- AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT
- AUX_HBSC_OFFSET
- AUX_HOST_INVERT
- AUX_HPD_DISCON
- AUX_HPD_SEL
- AUX_HW_RETRY_COUNT_SEL
- AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS
- AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS
- AUX_HW_RETRY_INTERVAL_600_MICROSECONDS
- AUX_HW_RETRY_INTERVAL_800_MICROSECONDS
- AUX_HW_RETRY_INTERVAL_MASK
- AUX_IDENTITY
- AUX_IENABLE
- AUX_IMPCAL_REQ_EN
- AUX_INTERLACE_SEL
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK
- AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK
- AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK
- AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT
- AUX_INTR_VEC_BASE
- AUX_INVALID_REPLY_RETRY_COUNTER
- AUX_IPULSE
- AUX_IRQ_ACT
- AUX_IRQ_ACT_BIT_U
- AUX_IRQ_CTRL
- AUX_IRQ_ENABLE
- AUX_IRQ_HINT
- AUX_IRQ_LEV
- AUX_IRQ_LV12
- AUX_IRQ_LVL_PEND
- AUX_IRQ_PRIORITY
- AUX_IRQ_SELECT
- AUX_IRQ_STATUS_AUX_RPLY_TOUT
- AUX_IRQ_STATUS_AUX_SHORT
- AUX_IRQ_STATUS_NAT_I2C_FAIL
- AUX_ITRIGGER
- AUX_LENGTH
- AUX_LENGTH_LEN
- AUX_LS_DATA__AUX_LS_DATA_MASK
- AUX_LS_DATA__AUX_LS_DATA__SHIFT
- AUX_LS_DATA__AUX_LS_INDEX_MASK
- AUX_LS_DATA__AUX_LS_INDEX__SHIFT
- AUX_LS_READ_EN
- AUX_LS_READ_TRIG
- AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK
- AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT
- AUX_LS_STATUS__AUX_LS_DONE_MASK
- AUX_LS_STATUS__AUX_LS_DONE__SHIFT
- AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK
- AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT
- AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK
- AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT
- AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK
- AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT
- AUX_LS_STATUS__AUX_LS_REQ_MASK
- AUX_LS_STATUS__AUX_LS_REQ__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK
- AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK
- AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK
- AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK
- AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK
- AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK
- AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK
- AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK
- AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK
- AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK
- AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK
- AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK
- AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT
- AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT
- AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK
- AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT
- AUX_LS_STATUS__AUX_LS_UPDATED_MASK
- AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT
- AUX_LS_UPDATE_DISABLE
- AUX_MAX_DEFER_RETRIES
- AUX_MAX_DEFER_WRITE_RETRY
- AUX_MAX_I2C_DEFER_RETRIES
- AUX_MAX_INVALID_REPLY_RETRIES
- AUX_MAX_OFFSET
- AUX_MAX_RETRIES
- AUX_MAX_TIMEOUT_RETRIES
- AUX_MESURE_CONF_REG
- AUX_MISC_MASTER1_EN
- AUX_MISC_MASTER1_EN_SBE_MSK
- AUX_MISC_MASTER1_SMPHR_STATUS
- AUX_MSG
- AUX_NATIVE_READ
- AUX_NATIVE_REPLY_ACK
- AUX_NATIVE_REPLY_DEFER
- AUX_NATIVE_REPLY_MASK
- AUX_NATIVE_REPLY_NAK
- AUX_NATIVE_WRITE
- AUX_OFFSET
- AUX_OPT_BIT0
- AUX_OPT_BIT1
- AUX_OPT_BIT10
- AUX_OPT_BIT11
- AUX_OPT_BIT12
- AUX_OPT_BIT13
- AUX_OPT_BIT14
- AUX_OPT_BIT15
- AUX_OPT_BIT2
- AUX_OPT_BIT3
- AUX_OPT_BIT4
- AUX_OPT_BIT5
- AUX_OPT_BIT6
- AUX_OPT_BIT7
- AUX_OPT_BIT8
- AUX_OPT_BIT9
- AUX_OUT
- AUX_PD
- AUX_PI_EN
- AUX_PLL_FRAC
- AUX_PLL_INT_POST
- AUX_POL_MASK
- AUX_POL_SHIFT
- AUX_POWER_UP_WA_DELAY
- AUX_PRECHARGE_LEN
- AUX_PWR_DET
- AUX_PWR_DETECTED
- AUX_REG
- AUX_REG_LIST
- AUX_REG_READ
- AUX_REG_UPDATE
- AUX_REG_UPDATE_2
- AUX_REG_UPDATE_N
- AUX_REG_WRITE
- AUX_REPLY_PAD_LEN
- AUX_RETRY_INTERVAL
- AUX_ROC_MAX_DELAY
- AUX_ROC_MIN_DELAY
- AUX_ROC_MIN_DURATION
- AUX_ROC_MIN_SAFETY_BUFFER
- AUX_ROC_SAFETY_BUFFER
- AUX_RSZ_OFFSET
- AUX_RTC_CTRL
- AUX_RTC_HIGH
- AUX_RTC_LOW
- AUX_RX_COMM_AUX_DEFER
- AUX_RX_COMM_I2C_DEFER
- AUX_RX_ERROR_FLAGS
- AUX_RX_FILTER_EN
- AUX_RX_HALF_FULL_DET
- AUX_RX_HALF_FULL_MASK
- AUX_RX_OVERFLOW_DET
- AUX_RX_OVERFLOW_MASK
- AUX_SDB_INDEX
- AUX_SDB_NUM
- AUX_SDB_NUM_ALERT
- AUX_SDB_NUM_EMPTY
- AUX_STATUS
- AUX_STATUS_MASK
- AUX_STOP_LEN
- AUX_SW_AUTOINCREMENT_DISABLE
- AUX_SW_CONTROL
- AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK
- AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT
- AUX_SW_CONTROL__AUX_SW_GO_MASK
- AUX_SW_CONTROL__AUX_SW_GO__SHIFT
- AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK
- AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT
- AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK
- AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT
- AUX_SW_DATA
- AUX_SW_DATA_INDEX
- AUX_SW_DATA_MASK
- AUX_SW_DATA_RW
- AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK
- AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT
- AUX_SW_DATA__AUX_SW_DATA_MASK
- AUX_SW_DATA__AUX_SW_DATA_RW_MASK
- AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT
- AUX_SW_DATA__AUX_SW_DATA__SHIFT
- AUX_SW_DATA__AUX_SW_INDEX_MASK
- AUX_SW_DATA__AUX_SW_INDEX__SHIFT
- AUX_SW_DONE
- AUX_SW_DONE_ACK
- AUX_SW_DONE_INT
- AUX_SW_DONE_MASK
- AUX_SW_GO
- AUX_SW_INTERRUPT_CONTROL
- AUX_SW_LS_DONE_INT
- AUX_SW_LS_DONE_MASK
- AUX_SW_NON_AUX_MODE
- AUX_SW_REPLY_GET_BYTE_COUNT
- AUX_SW_REQ
- AUX_SW_RX_HPD_DISCON
- AUX_SW_RX_INVALID_START
- AUX_SW_RX_INVALID_STOP
- AUX_SW_RX_MIN_COUNT_VIOL
- AUX_SW_RX_OVERFLOW
- AUX_SW_RX_PARTIAL_BYTE
- AUX_SW_RX_RECV_INVALID_H
- AUX_SW_RX_RECV_INVALID_V
- AUX_SW_RX_RECV_NO_DET
- AUX_SW_RX_SYNC_INVALID_H
- AUX_SW_RX_SYNC_INVALID_L
- AUX_SW_RX_TIMEOUT
- AUX_SW_RX_TIMEOUT_STATE
- AUX_SW_START_DELAY
- AUX_SW_STATUS
- AUX_SW_STATUS__AUX_ARB_STATUS_MASK
- AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT
- AUX_SW_STATUS__AUX_SW_DONE_MASK
- AUX_SW_STATUS__AUX_SW_DONE__SHIFT
- AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK
- AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT
- AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK
- AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT
- AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK
- AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT
- AUX_SW_STATUS__AUX_SW_REQ_MASK
- AUX_SW_STATUS__AUX_SW_REQ__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK
- AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK
- AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK
- AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK
- AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK
- AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK
- AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK
- AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK
- AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK
- AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK
- AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK
- AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK
- AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT
- AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT
- AUX_SW_WR_BYTES
- AUX_SYNC_LEN
- AUX_SYNT_ENB
- AUX_TC_EN
- AUX_TERMINAL_CTRL_50_OHM
- AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK
- AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT
- AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK
- AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT
- AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK
- AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT
- AUX_TEST_MODE
- AUX_TIMED_OUT_RETRY_COUNTER
- AUX_TIMEOUT
- AUX_TIMEOUT_PERIOD
- AUX_TRACE
- AUX_TRANSACTION_REPLY_AUX_ACK
- AUX_TRANSACTION_REPLY_AUX_DEFER
- AUX_TRANSACTION_REPLY_AUX_NACK
- AUX_TRANSACTION_REPLY_HPD_DISCON
- AUX_TRANSACTION_REPLY_I2C_ACK
- AUX_TRANSACTION_REPLY_I2C_DEFER
- AUX_TRANSACTION_REPLY_I2C_NACK
- AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER
- AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK
- AUX_TRANSACTION_REPLY_INVALID
- AUX_TRANSACTION_TYPE_DP
- AUX_TRANSACTION_TYPE_I2C
- AUX_TX_COMM_DP_TRANSACTION
- AUX_TX_COMM_I2C_TRANSACTION
- AUX_TX_COMM_MASK
- AUX_TX_COMM_MOT
- AUX_TX_COMM_READ
- AUX_TX_COMM_WRITE
- AUX_TX_HALF_FULL_DET
- AUX_TX_HALF_FULL_MASK
- AUX_TX_OVERFLOW_DET
- AUX_TX_OVERFLOW_MASK
- AUX_USER_SP
- AUX_VER_RECORD
- AUX_VOL
- AUX_WAIT_TIMEOUT_MS
- AUX_WINDOW_HORZ_CNTL
- AUX_WINDOW_VERT_CNTL
- AUX_XSCALE_MASK
- AUX_XSCALE_SHIFT
- AUX_YSCALE_MASK
- AUX_YSCALE_SHIFT
- AU_FRMREGPLLACQPHASESCL_REG227H
- AU_STATUS0
- AV7110_BOOT_BASE
- AV7110_BOOT_BLOCK
- AV7110_BOOT_MAX_SIZE
- AV7110_BOOT_SIZE
- AV7110_BOOT_STATE
- AV7110_FW_AUDIO_COMMAND
- AV7110_FW_VIDEO_COMMAND
- AV7110_FW_VIDEO_ZOOM
- AV7110_VIDEO_MODE_NTSC
- AV7110_VIDEO_MODE_PAL
- AVAILABLE
- AVAILABLE_EFUSE_ADDR
- AVAILABLE_EFUSE_ADDR_88E
- AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK
- AVAIL_INTERPOSABLE
- AVAIL_SUBSTREAMS_MASK
- AVAIL_TD
- AVB_AVTP_CAPTURE_A_MARK
- AVB_AVTP_CAPTURE_B_MARK
- AVB_AVTP_MATCH_A_MARK
- AVB_AVTP_MATCH_B_MARK
- AVB_AVTP_MATCH_MARK
- AVB_COL_MARK
- AVB_CRS_MARK
- AVB_GTXREFCLK_MARK
- AVB_GTX_CLK_MARK
- AVB_LINK_MARK
- AVB_MAGIC_MARK
- AVB_MDC_MARK
- AVB_MDIO_MARK
- AVB_PHY_INT_MARK
- AVB_RXD0_MARK
- AVB_RXD1_MARK
- AVB_RXD2_MARK
- AVB_RXD3_MARK
- AVB_RXD4_MARK
- AVB_RXD5_MARK
- AVB_RXD6_MARK
- AVB_RXD7_MARK
- AVB_RX_CLK_MARK
- AVB_RX_DV_MARK
- AVB_RX_ER_MARK
- AVB_TXD0_MARK
- AVB_TXD1_MARK
- AVB_TXD2_MARK
- AVB_TXD3_MARK
- AVB_TXD4_MARK
- AVB_TXD5_MARK
- AVB_TXD6_MARK
- AVB_TXD7_MARK
- AVB_TX_CLK_MARK
- AVB_TX_EN_MARK
- AVB_TX_ER_MARK
- AVCS_CMDRSP_ADSP_EVENT_GET_STATE
- AVCS_CMDRSP_GET_FWK_VERSION
- AVCS_CMD_ADSP_EVENT_GET_STATE
- AVCS_CMD_GET_FWK_VERSION
- AVCS_GET_VERSIONS
- AVCS_GET_VERSIONS_RSP
- AVC_BRIDGECO_ADDR_BYTES
- AVC_BRIDGECO_PLUG_DIR_IN
- AVC_BRIDGECO_PLUG_DIR_OUT
- AVC_BRIDGECO_PLUG_MODE_FUNCTION_BLOCK
- AVC_BRIDGECO_PLUG_MODE_SUBUNIT
- AVC_BRIDGECO_PLUG_MODE_UNIT
- AVC_BRIDGECO_PLUG_TYPE_ADDITION
- AVC_BRIDGECO_PLUG_TYPE_ANA
- AVC_BRIDGECO_PLUG_TYPE_ASYNC
- AVC_BRIDGECO_PLUG_TYPE_DIG
- AVC_BRIDGECO_PLUG_TYPE_ISOC
- AVC_BRIDGECO_PLUG_TYPE_MIDI
- AVC_BRIDGECO_PLUG_TYPE_SYNC
- AVC_BRIDGECO_PLUG_UNIT_ASYNC
- AVC_BRIDGECO_PLUG_UNIT_EXT
- AVC_BRIDGECO_PLUG_UNIT_ISOC
- AVC_CACHE_RECLAIM
- AVC_CACHE_SLOTS
- AVC_CALLBACK_ADD_XPERMS
- AVC_CALLBACK_AUDITALLOW_DISABLE
- AVC_CALLBACK_AUDITALLOW_ENABLE
- AVC_CALLBACK_AUDITDENY_DISABLE
- AVC_CALLBACK_AUDITDENY_ENABLE
- AVC_CALLBACK_GRANT
- AVC_CALLBACK_RESET
- AVC_CALLBACK_REVOKE
- AVC_CALLBACK_TRY_REVOKE
- AVC_CTYPE_CONTROL
- AVC_CTYPE_NOTIFY
- AVC_CTYPE_STATUS
- AVC_DEBUG_APPLICATION_PMT
- AVC_DEBUG_CA2HOST
- AVC_DEBUG_DSD
- AVC_DEBUG_DSIT
- AVC_DEBUG_FCP_PAYLOADS
- AVC_DEBUG_HOST2CA
- AVC_DEBUG_LNB_CONTROL
- AVC_DEBUG_READ_DESCRIPTOR
- AVC_DEBUG_REGISTER_REMOTE_CONTROL
- AVC_DEBUG_TUNE_QPSK
- AVC_DEBUG_TUNE_QPSK2
- AVC_DEF_CACHE_THRESHOLD
- AVC_EXTENDED_PERMS
- AVC_GENERAL_PLUG_DIR_COUNT
- AVC_GENERAL_PLUG_DIR_IN
- AVC_GENERAL_PLUG_DIR_OUT
- AVC_GENERIC_FRAME_MAXIMUM_BYTES
- AVC_NONBLOCKING
- AVC_OPCODE_DSD
- AVC_OPCODE_DSIT
- AVC_OPCODE_READ_DESCRIPTOR
- AVC_OPCODE_VENDOR
- AVC_PLUG_INFO_BUF_BYTES
- AVC_RESPONSE_ACCEPTED
- AVC_RESPONSE_CHANGED
- AVC_RESPONSE_INTERIM
- AVC_RESPONSE_STABLE
- AVC_STRICT
- AVC_SUBUNIT_TYPE_TUNER
- AVC_SUBUNIT_TYPE_UNIT
- AVC_SW_VERSION_ENTRY
- AVC_UNIT_SPEC_ID_ENTRY
- AVDD
- AVDEC_DISABLE
- AVDEC_ENABLE
- AVDEC_STATUS
- AVD_FLAGS_PERMISSIVE
- AVECR
- AVERAGE_CURRENT
- AVERAGE_LENGTH
- AVERAGE_POWER
- AVERAGING_TIME_INTERVAL
- AVERMEDIA_VOLAR_A868R
- AVE_CFGR
- AVE_CFGR_CHE
- AVE_CFGR_FLE
- AVE_CFGR_IPFCEN
- AVE_CFGR_MII
- AVE_DEFAULT_MSG_ENABLE
- AVE_DESCC
- AVE_DESCC_RD0
- AVE_DESCC_RDSTP
- AVE_DESCC_STATUS_MASK
- AVE_DESCC_TD
- AVE_DESCID_RX
- AVE_DESCID_TX
- AVE_DESC_OFS_ADDRL
- AVE_DESC_OFS_ADDRU
- AVE_DESC_OFS_CMDSTS
- AVE_DESC_RX_PERMIT
- AVE_DESC_RX_SUSPEND
- AVE_DESC_SIZE_32
- AVE_DESC_SIZE_64
- AVE_DESC_START
- AVE_DESC_STOP
- AVE_FORCE_TXINTCNT
- AVE_FRAME_HEADROOM
- AVE_GIMR
- AVE_GISR
- AVE_GI_PHY
- AVE_GI_RXDROP
- AVE_GI_RXERR
- AVE_GI_RXIINT
- AVE_GI_RXOVF
- AVE_GI_TX
- AVE_GRR
- AVE_GRR_GRST
- AVE_GRR_PHYRST
- AVE_GRR_RXFFR
- AVE_IDR
- AVE_IIRQC
- AVE_IIRQC_BSCK
- AVE_IIRQC_EN0
- AVE_INTM_COUNT
- AVE_LINKSEL
- AVE_LINKSEL_100M
- AVE_MAX_CLKS
- AVE_MAX_ETHFRAME
- AVE_MAX_RSTS
- AVE_MDIOAR
- AVE_MDIOCTR
- AVE_MDIOCTR_RREQ
- AVE_MDIOCTR_WREQ
- AVE_MDIORDR
- AVE_MDIOSR
- AVE_MDIOSR_STS
- AVE_MDIOWDR
- AVE_NR_RXDESC
- AVE_NR_TXDESC
- AVE_PFEN
- AVE_PFMBIT
- AVE_PFMBIT_BASE
- AVE_PFMBIT_MASK
- AVE_PFMBYTE
- AVE_PFMBYTE_BASE
- AVE_PFMBYTE_MASK0
- AVE_PFMBYTE_MASK1
- AVE_PFNUM_BROADCAST
- AVE_PFNUM_FILTER
- AVE_PFNUM_MULTICAST
- AVE_PFNUM_UNICAST
- AVE_PFSEL
- AVE_PFSEL_BASE
- AVE_PF_MULTICAST_SIZE
- AVE_PF_SIZE
- AVE_PKTF
- AVE_PKTF_BASE
- AVE_PM_OPS
- AVE_RSTCTRL
- AVE_RSTCTRL_RMIIRST
- AVE_RXCR
- AVE_RXCR_AFEN
- AVE_RXCR_DRPEN
- AVE_RXCR_FDUPEN
- AVE_RXCR_FLOCTR
- AVE_RXCR_MPSIZ_MASK
- AVE_RXCR_RXEN
- AVE_RXDC0
- AVE_RXDC0_ADDR
- AVE_RXDC0_ADDR_START
- AVE_RXDC0_SIZE
- AVE_RXDM_32
- AVE_RXDM_64
- AVE_RXDM_SIZE_32
- AVE_RXDM_SIZE_64
- AVE_RXMAC1R
- AVE_RXMAC2R
- AVE_STS_1ST
- AVE_STS_CSER
- AVE_STS_CSSV
- AVE_STS_EC
- AVE_STS_INTR
- AVE_STS_LAST
- AVE_STS_NOCSUM
- AVE_STS_OK
- AVE_STS_OWC
- AVE_STS_OWN
- AVE_STS_PKTLEN_RX_MASK
- AVE_STS_PKTLEN_TX_MASK
- AVE_TXCR
- AVE_TXCR_FLOCTR
- AVE_TXCR_TXSPD_100
- AVE_TXCR_TXSPD_1G
- AVE_TXDC
- AVE_TXDC_ADDR
- AVE_TXDC_ADDR_START
- AVE_TXDC_SIZE
- AVE_TXDM_32
- AVE_TXDM_64
- AVE_TXDM_SIZE_32
- AVE_TXDM_SIZE_64
- AVE_VR
- AVFSFUSETABLE
- AVFSGB0_Vdroop_Enable_MASK
- AVFSGB0_Vdroop_Enable_SHIFT
- AVFSGB1_Vdroop_Enable_MASK
- AVFSGB1_Vdroop_Enable_SHIFT
- AVFSGB_VDROOP_TABLE_MAX_ENTRIES
- AVFSTABLE
- AVFS_CURVE
- AVFS_CksOff_AvfsGbv_t
- AVFS_CksOff_BtcGbv_t
- AVFS_CksOff_Gbv_t
- AVFS_EN_LSB
- AVFS_EN_MSB
- AVFS_Margin_t
- AVFS_Sclk_Offset_t
- AVFS_VOLTAGE_COUNT
- AVFS_VOLTAGE_GFX
- AVFS_VOLTAGE_SOC
- AVFS_VOLTAGE_TYPE_e
- AVFS_meanNsigma_t
- AVGWEIGHT
- AVGWEIGHT_SENNAVGWEIGHT_SHIFT
- AVGWEIGHT_SENPAVGWEIGHT_SHIFT
- AVG_1
- AVG_16
- AVG_4
- AVG_8
- AVG_AMPDU_SIZE
- AVG_ENTRIES
- AVG_FACTOR
- AVG_FREQ
- AVG_PERF_COUNTER
- AVG_PKT_SIZE
- AVG_SHIFT
- AVG_SIZE
- AVG_THERMAL_NUM
- AVG_THERMAL_NUM_8723B
- AVG_THERMAL_NUM_8723BE
- AVG_THERMAL_NUM_8812A
- AVG_THERMAL_NUM_88E
- AVIC_EDGE_CLR
- AVIC_EDGE_STATUS
- AVIC_ENABLE_MASK
- AVIC_ENABLE_SHIFT
- AVIC_FIPNDH
- AVIC_FIPNDL
- AVIC_FIQ_STATUS
- AVIC_FIVECSR
- AVIC_GATAG
- AVIC_GATAG_TO_VCPUID
- AVIC_GATAG_TO_VMID
- AVIC_HPA_MASK
- AVIC_INTCNTL
- AVIC_INTDISNUM
- AVIC_INTENABLEH
- AVIC_INTENABLEL
- AVIC_INTENNUM
- AVIC_INTFRCH
- AVIC_INTFRCL
- AVIC_INTSRCH
- AVIC_INTSRCL
- AVIC_INTTYPEH
- AVIC_INTTYPEL
- AVIC_INT_DUAL_EDGE
- AVIC_INT_ENABLE
- AVIC_INT_ENABLE_CLR
- AVIC_INT_EVENT
- AVIC_INT_SELECT
- AVIC_INT_SENSE
- AVIC_INT_TRIGGER
- AVIC_INT_TRIGGER_CLR
- AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
- AVIC_IPI_FAILURE_INVALID_INT_TYPE
- AVIC_IPI_FAILURE_INVALID_TARGET
- AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
- AVIC_IRQ_STATUS
- AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
- AVIC_LOGICAL_ID_ENTRY_VALID_BIT
- AVIC_LOGICAL_ID_ENTRY_VALID_MASK
- AVIC_MAX_PHYSICAL_ID_COUNT
- AVIC_NIMASK
- AVIC_NIPNDH
- AVIC_NIPNDL
- AVIC_NIPRIORITY
- AVIC_NIVECSR
- AVIC_NUM_IRQS
- AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
- AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
- AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
- AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
- AVIC_RAW_STATUS
- AVIC_UNACCEL_ACCESS_OFFSET_MASK
- AVIC_UNACCEL_ACCESS_VECTOR_MASK
- AVIC_UNACCEL_ACCESS_WRITE_MASK
- AVIC_VCPU_ID_BITS
- AVIC_VCPU_ID_MASK
- AVIC_VM_ID_BITS
- AVIC_VM_ID_MASK
- AVIC_VM_ID_NR
- AVILA_MAX_DEV
- AVILA_SCL_PIN
- AVILA_SDA_PIN
- AVIVOD_H
- AVIVO_CP_DYN_CNTL
- AVIVO_CP_FORCEON
- AVIVO_CRTC_DISP_READ_REQUEST_DISABLE
- AVIVO_CRTC_EN
- AVIVO_D1CRTC_BLANK_CONTROL
- AVIVO_D1CRTC_CONTROL
- AVIVO_D1CRTC_FRAME_COUNT
- AVIVO_D1CRTC_H_BLANK_START_END
- AVIVO_D1CRTC_H_SYNC_A
- AVIVO_D1CRTC_H_SYNC_A_CNTL
- AVIVO_D1CRTC_H_SYNC_B
- AVIVO_D1CRTC_H_SYNC_B_CNTL
- AVIVO_D1CRTC_H_TOTAL
- AVIVO_D1CRTC_INTERLACE_CONTROL
- AVIVO_D1CRTC_INTERLACE_STATUS
- AVIVO_D1CRTC_STATUS
- AVIVO_D1CRTC_STATUS_HV_COUNT
- AVIVO_D1CRTC_STATUS_POSITION
- AVIVO_D1CRTC_STEREO_CONTROL
- AVIVO_D1CRTC_UPDATE_LOCK
- AVIVO_D1CRTC_V_BLANK
- AVIVO_D1CRTC_V_BLANK_START_END
- AVIVO_D1CRTC_V_SYNC_A
- AVIVO_D1CRTC_V_SYNC_A_CNTL
- AVIVO_D1CRTC_V_SYNC_B
- AVIVO_D1CRTC_V_SYNC_B_CNTL
- AVIVO_D1CRTC_V_TOTAL
- AVIVO_D1CURSOR_EN
- AVIVO_D1CURSOR_MODE_24BPP
- AVIVO_D1CURSOR_MODE_MASK
- AVIVO_D1CURSOR_MODE_SHIFT
- AVIVO_D1CURSOR_UPDATE_LOCK
- AVIVO_D1CUR_CONTROL
- AVIVO_D1CUR_HOT_SPOT
- AVIVO_D1CUR_POSITION
- AVIVO_D1CUR_SIZE
- AVIVO_D1CUR_SURFACE_ADDRESS
- AVIVO_D1CUR_UPDATE
- AVIVO_D1GRPH_CONTROL
- AVIVO_D1GRPH_CONTROL_16BPP_AI88
- AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
- AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444
- AVIVO_D1GRPH_CONTROL_16BPP_MONO16
- AVIVO_D1GRPH_CONTROL_16BPP_RGB565
- AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010
- AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010
- AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
- AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL
- AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616
- AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
- AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
- AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
- AVIVO_D1GRPH_CONTROL_DEPTH_64BPP
- AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
- AVIVO_D1GRPH_ENABLE
- AVIVO_D1GRPH_FLIP_CONTROL
- AVIVO_D1GRPH_LUT_SEL
- AVIVO_D1GRPH_MACRO_ADDRESS_MODE
- AVIVO_D1GRPH_PITCH
- AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
- AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
- AVIVO_D1GRPH_SURFACE_OFFSET_X
- AVIVO_D1GRPH_SURFACE_OFFSET_Y
- AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN
- AVIVO_D1GRPH_SURFACE_UPDATE_PENDING
- AVIVO_D1GRPH_SWAP_RB
- AVIVO_D1GRPH_TILED
- AVIVO_D1GRPH_UPDATE
- AVIVO_D1GRPH_UPDATE_LOCK
- AVIVO_D1GRPH_X_END
- AVIVO_D1GRPH_X_START
- AVIVO_D1GRPH_Y_END
- AVIVO_D1GRPH_Y_START
- AVIVO_D1MODE_DATA_FORMAT
- AVIVO_D1MODE_DESKTOP_HEIGHT
- AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT
- AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM
- AVIVO_D1MODE_INTERLEAVE_EN
- AVIVO_D1MODE_INT_MASK
- AVIVO_D1MODE_MASTER_UPDATE_LOCK
- AVIVO_D1MODE_MASTER_UPDATE_MODE
- AVIVO_D1MODE_VBLANK_STATUS
- AVIVO_D1MODE_VIEWPORT_SIZE
- AVIVO_D1MODE_VIEWPORT_START
- AVIVO_D1MODE_VLINE_START_END
- AVIVO_D1MODE_VLINE_STAT
- AVIVO_D1MODE_VLINE_STATUS
- AVIVO_D1SCL_SCALER_ENABLE
- AVIVO_D1SCL_SCALER_TAP_CONTROL
- AVIVO_D1SCL_UPDATE
- AVIVO_D1SCL_UPDATE_LOCK
- AVIVO_D1VGA_CONTROL
- AVIVO_D1_VBLANK_INTERRUPT
- AVIVO_D2CRTC_BLANK_CONTROL
- AVIVO_D2CRTC_CONTROL
- AVIVO_D2CRTC_FRAME_COUNT
- AVIVO_D2CRTC_H_BLANK_START_END
- AVIVO_D2CRTC_H_SYNC_A
- AVIVO_D2CRTC_H_SYNC_A_CNTL
- AVIVO_D2CRTC_H_SYNC_B
- AVIVO_D2CRTC_H_SYNC_B_CNTL
- AVIVO_D2CRTC_H_TOTAL
- AVIVO_D2CRTC_INTERLACE_CONTROL
- AVIVO_D2CRTC_INTERLACE_STATUS
- AVIVO_D2CRTC_STATUS_POSITION
- AVIVO_D2CRTC_STEREO_CONTROL
- AVIVO_D2CRTC_V_BLANK_START_END
- AVIVO_D2CRTC_V_SYNC_A
- AVIVO_D2CRTC_V_SYNC_A_CNTL
- AVIVO_D2CRTC_V_SYNC_B
- AVIVO_D2CRTC_V_SYNC_B_CNTL
- AVIVO_D2CRTC_V_TOTAL
- AVIVO_D2CUR_CONTROL
- AVIVO_D2CUR_POSITION
- AVIVO_D2CUR_SIZE
- AVIVO_D2CUR_SURFACE_ADDRESS
- AVIVO_D2GRPH_CONTROL
- AVIVO_D2GRPH_ENABLE
- AVIVO_D2GRPH_FLIP_CONTROL
- AVIVO_D2GRPH_LUT_SEL
- AVIVO_D2GRPH_PITCH
- AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS
- AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS
- AVIVO_D2GRPH_SURFACE_OFFSET_X
- AVIVO_D2GRPH_SURFACE_OFFSET_Y
- AVIVO_D2GRPH_UPDATE
- AVIVO_D2GRPH_X_END
- AVIVO_D2GRPH_X_START
- AVIVO_D2GRPH_Y_END
- AVIVO_D2GRPH_Y_START
- AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT
- AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM
- AVIVO_D2MODE_INT_MASK
- AVIVO_D2MODE_VBLANK_STATUS
- AVIVO_D2MODE_VIEWPORT_SIZE
- AVIVO_D2MODE_VIEWPORT_START
- AVIVO_D2MODE_VLINE_START_END
- AVIVO_D2MODE_VLINE_STATUS
- AVIVO_D2SCL_SCALER_ENABLE
- AVIVO_D2SCL_SCALER_TAP_CONTROL
- AVIVO_D2VGA_CONTROL
- AVIVO_D2_VBLANK_INTERRUPT
- AVIVO_DACA_ENABLE
- AVIVO_DACA_FORCE_OUTPUT_CNTL
- AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY
- AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE
- AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN
- AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED
- AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT
- AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN
- AVIVO_DACA_POWERDOWN
- AVIVO_DACA_POWERDOWN_BLUE
- AVIVO_DACA_POWERDOWN_GREEN
- AVIVO_DACA_POWERDOWN_POWERDOWN
- AVIVO_DACA_POWERDOWN_RED
- AVIVO_DACA_SOURCE_SELECT
- AVIVO_DACB_ENABLE
- AVIVO_DACB_FORCE_OUTPUT_CNTL
- AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY
- AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE
- AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN
- AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED
- AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT
- AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN
- AVIVO_DACB_POWERDOWN
- AVIVO_DACB_POWERDOWN_BLUE
- AVIVO_DACB_POWERDOWN_GREEN
- AVIVO_DACB_POWERDOWN_POWERDOWN
- AVIVO_DACB_POWERDOWN_RED
- AVIVO_DACB_SOURCE_SELECT
- AVIVO_DAC_ENABLE
- AVIVO_DAC_SOURCE_CRTC1
- AVIVO_DAC_SOURCE_CRTC2
- AVIVO_DAC_SOURCE_TV
- AVIVO_DC_CRTC_MASTER_EN
- AVIVO_DC_CRTC_TV_CONTROL
- AVIVO_DC_GPIO_DDC1_A
- AVIVO_DC_GPIO_DDC1_EN
- AVIVO_DC_GPIO_DDC1_MASK
- AVIVO_DC_GPIO_DDC1_Y
- AVIVO_DC_GPIO_DDC2_A
- AVIVO_DC_GPIO_DDC2_EN
- AVIVO_DC_GPIO_DDC2_MASK
- AVIVO_DC_GPIO_DDC2_Y
- AVIVO_DC_GPIO_DDC3_A
- AVIVO_DC_GPIO_DDC3_EN
- AVIVO_DC_GPIO_DDC3_MASK
- AVIVO_DC_GPIO_DDC3_Y
- AVIVO_DC_GPIO_HPD_A
- AVIVO_DC_GPIO_HPD_Y
- AVIVO_DC_I2C_ABORT
- AVIVO_DC_I2C_ABORT_HDCP_I2C
- AVIVO_DC_I2C_ADDR_COUNT
- AVIVO_DC_I2C_ARBITRATION
- AVIVO_DC_I2C_CLK_DRIVE_EN
- AVIVO_DC_I2C_CONTROL1
- AVIVO_DC_I2C_CONTROL2
- AVIVO_DC_I2C_CONTROL3
- AVIVO_DC_I2C_DATA
- AVIVO_DC_I2C_DATA_COUNT
- AVIVO_DC_I2C_DATA_DRIVE_EN
- AVIVO_DC_I2C_DATA_DRIVE_SEL
- AVIVO_DC_I2C_DONE
- AVIVO_DC_I2C_EN
- AVIVO_DC_I2C_GO
- AVIVO_DC_I2C_HALT
- AVIVO_DC_I2C_HW_NEEDS_I2C
- AVIVO_DC_I2C_HW_USING_I2C
- AVIVO_DC_I2C_INTERRUPT_AK
- AVIVO_DC_I2C_INTERRUPT_CONTROL
- AVIVO_DC_I2C_INTERRUPT_ENABLE
- AVIVO_DC_I2C_INTERRUPT_STATUS
- AVIVO_DC_I2C_NACK
- AVIVO_DC_I2C_PIN_SELECT
- AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY
- AVIVO_DC_I2C_RECEIVE
- AVIVO_DC_I2C_RESET
- AVIVO_DC_I2C_SOFT_RESET
- AVIVO_DC_I2C_START
- AVIVO_DC_I2C_STATUS1
- AVIVO_DC_I2C_STOP
- AVIVO_DC_I2C_SW_CAN_USE_I2C
- AVIVO_DC_I2C_SW_DONE_USING_I2C
- AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C
- AVIVO_DC_I2C_TIME_LIMIT
- AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY
- AVIVO_DC_LB_DISP1_END_ADR_MASK
- AVIVO_DC_LB_DISP1_END_ADR_SHIFT
- AVIVO_DC_LB_MEMORY_SPLIT
- AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF
- AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q
- AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q
- AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY
- AVIVO_DC_LB_MEMORY_SPLIT_MASK
- AVIVO_DC_LB_MEMORY_SPLIT_SHIFT
- AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE
- AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
- AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
- AVIVO_DC_LUTA_BLACK_OFFSET_RED
- AVIVO_DC_LUTA_CONTROL
- AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
- AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
- AVIVO_DC_LUTA_WHITE_OFFSET_RED
- AVIVO_DC_LUTB_BLACK_OFFSET_BLUE
- AVIVO_DC_LUTB_BLACK_OFFSET_GREEN
- AVIVO_DC_LUTB_BLACK_OFFSET_RED
- AVIVO_DC_LUTB_CONTROL
- AVIVO_DC_LUTB_WHITE_OFFSET_BLUE
- AVIVO_DC_LUTB_WHITE_OFFSET_GREEN
- AVIVO_DC_LUTB_WHITE_OFFSET_RED
- AVIVO_DC_LUT_30_COLOR
- AVIVO_DC_LUT_AUTOFILL
- AVIVO_DC_LUT_PWL_DATA
- AVIVO_DC_LUT_READ_PIPE_SELECT
- AVIVO_DC_LUT_RW_INDEX
- AVIVO_DC_LUT_RW_MODE
- AVIVO_DC_LUT_RW_SELECT
- AVIVO_DC_LUT_SEQ_COLOR
- AVIVO_DC_LUT_WRITE_EN_MASK
- AVIVO_DDIA_BIT_DEPTH_CONTROL
- AVIVO_DISPLAY_INT_STATUS
- AVIVO_DISP_INTERRUPT_STATUS
- AVIVO_DVGA_CONTROL_MODE_ENABLE
- AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN
- AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT
- AVIVO_DVGA_CONTROL_ROTATE
- AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT
- AVIVO_DVGA_CONTROL_TIMING_SELECT
- AVIVO_DVOA_BIT_DEPTH_CONTROL
- AVIVO_DxMODE_INT_MASK
- AVIVO_E2_DYN_CNTL
- AVIVO_E2_FORCEON
- AVIVO_EXT1_PPLL_CNTL
- AVIVO_EXT1_PPLL_FB_DIV
- AVIVO_EXT1_PPLL_POST_DIV
- AVIVO_EXT1_PPLL_POST_DIV_SRC
- AVIVO_EXT1_PPLL_REF_DIV
- AVIVO_EXT1_PPLL_REF_DIV_SRC
- AVIVO_EXT1_PPLL_UPDATE_CNTL
- AVIVO_EXT1_PPLL_UPDATE_LOCK
- AVIVO_EXT2_PPLL_CNTL
- AVIVO_EXT2_PPLL_FB_DIV
- AVIVO_EXT2_PPLL_POST_DIV
- AVIVO_EXT2_PPLL_POST_DIV_SRC
- AVIVO_EXT2_PPLL_REF_DIV
- AVIVO_EXT2_PPLL_REF_DIV_SRC
- AVIVO_EXT2_PPLL_UPDATE_CNTL
- AVIVO_EXT2_PPLL_UPDATE_LOCK
- AVIVO_HDP_FB_LOCATION
- AVIVO_IDCT_DYN_CNTL
- AVIVO_IDCT_FORCEON
- AVIVO_LUT_10BIT_BYPASS_EN
- AVIVO_LVDS_BACKLIGHT_CNTL
- AVIVO_LVDS_BACKLIGHT_CNTL_EN
- AVIVO_LVDS_BACKLIGHT_LEVEL_MASK
- AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT
- AVIVO_LVTMA_BIT_DEPTH_CONTROL
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH
- AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
- AVIVO_LVTMA_BLON
- AVIVO_LVTMA_BLON_OVRD
- AVIVO_LVTMA_BLON_POL
- AVIVO_LVTMA_CNTL
- AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE
- AVIVO_LVTMA_CNTL_ENABLE
- AVIVO_LVTMA_CNTL_HDMI_EN
- AVIVO_LVTMA_CNTL_HPD_MASK
- AVIVO_LVTMA_CNTL_HPD_SELECT
- AVIVO_LVTMA_CNTL_PIXEL_ENCODING
- AVIVO_LVTMA_CNTL_SWAP
- AVIVO_LVTMA_CNTL_SYNC_PHASE
- AVIVO_LVTMA_COLOR_FORMAT
- AVIVO_LVTMA_DATA_SYNCHRONIZATION
- AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL
- AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG
- AVIVO_LVTMA_DCBALANCER_CONTROL
- AVIVO_LVTMA_DCBALANCER_CONTROL_EN
- AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE
- AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN
- AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT
- AVIVO_LVTMA_DIGON
- AVIVO_LVTMA_DIGON_OVRD
- AVIVO_LVTMA_DIGON_POL
- AVIVO_LVTMA_PWRSEQ_EN
- AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK
- AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK
- AVIVO_LVTMA_PWRSEQ_STATE_BLON
- AVIVO_LVTMA_PWRSEQ_STATE_DIGON
- AVIVO_LVTMA_PWRSEQ_STATE_DONE
- AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT
- AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN
- AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R
- AVIVO_LVTMA_PWRSEQ_TARGET_STATE
- AVIVO_LVTMA_SOURCE_SELECT
- AVIVO_LVTMA_SYNCEN
- AVIVO_LVTMA_SYNCEN_OVRD
- AVIVO_LVTMA_SYNCEN_POL
- AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP
- AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL
- AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT
- AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL
- AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL
- AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE
- AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT
- AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN
- AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET
- AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK
- AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS
- AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK
- AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS
- AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN
- AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK
- AVIVO_MC_DATA
- AVIVO_MC_INDEX
- AVIVO_P1PLL_CNTL
- AVIVO_P1PLL_INT_SS_CNTL
- AVIVO_P1PLL_TMDSA_CNTL
- AVIVO_P2PLL_CNTL
- AVIVO_P2PLL_INT_SS_CNTL
- AVIVO_P2PLL_LVTMA_CNTL
- AVIVO_PCLK_CRTC1_CNTL
- AVIVO_PCLK_CRTC2_CNTL
- AVIVO_SEL_DDC1
- AVIVO_SEL_DDC2
- AVIVO_SEL_DDC3
- AVIVO_TMDSA_BIT_DEPTH_CONTROL
- AVIVO_TMDSA_CLOCK_ENABLE
- AVIVO_TMDSA_CNTL
- AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE
- AVIVO_TMDSA_CNTL_ENABLE
- AVIVO_TMDSA_CNTL_HDMI_EN
- AVIVO_TMDSA_CNTL_HPD_MASK
- AVIVO_TMDSA_CNTL_HPD_SELECT
- AVIVO_TMDSA_CNTL_PIXEL_ENCODING
- AVIVO_TMDSA_CNTL_SWAP
- AVIVO_TMDSA_CNTL_SYNC_PHASE
- AVIVO_TMDSA_DATA_SYNCHRONIZATION
- AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL
- AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG
- AVIVO_TMDSA_DCBALANCER_CONTROL
- AVIVO_TMDSA_DCBALANCER_CONTROL_EN
- AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE
- AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN
- AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT
- AVIVO_TMDSA_SOURCE_SELECT
- AVIVO_TMDSA_TRANSMITTER_CONTROL
- AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP
- AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL
- AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT
- AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL
- AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL
- AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE
- AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT
- AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN
- AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET
- AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK
- AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS
- AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK
- AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS
- AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA
- AVIVO_TMDSA_TRANSMITTER_ENABLE
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN
- AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK
- AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE
- AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE
- AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK
- AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH
- AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH
- AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN
- AVIVO_VBLANK_ACK
- AVIVO_VGA_RENDER_CONTROL
- AVIVO_VGA_VSTATUS_CNTL_MASK
- AVI_ACTIVE_FORMAT_VALID
- AVI_CODED_FRAME_ASPECT_16_9
- AVI_CODED_FRAME_ASPECT_4_3
- AVI_CODED_FRAME_ASPECT_NO_DATA
- AVI_COLORIMETRY_EXTENDED
- AVI_COLORIMETRY_ITU709
- AVI_COLORIMETRY_NO_DATA
- AVI_COLORIMETRY_SMPTE_170M
- AVI_COLOR_MODE_RGB
- AVI_COLOR_MODE_YCBCR422
- AVI_COLOR_MODE_YCBCR444
- AVI_IF
- AVI_IFRAME_LINE_NUMBER
- AVI_IF_UPDATE
- AVI_UNDERSCANNED_DISPLAY_VALID
- AVL_IRQ_ASSERTED
- AVL_IRQ_ENABLE
- AVL_PCIE_IENR
- AVL_PCIE_ISR
- AVL_RAM
- AVMB1_ADDCARD
- AVMB1_ADDCARD_WITH_TYPE
- AVMB1_COMPAT
- AVMB1_GET_CARDINFO
- AVMB1_LOAD
- AVMB1_LOAD_AND_CONFIG
- AVMB1_PORTLEN
- AVMB1_REGISTERCARD_IS_OBSOLETE
- AVMB1_REMOVECARD
- AVMB1_RESETCARD
- AVMFRITZ_REV
- AVM_B1DMA_DEBUG
- AVM_C4_DEBUG
- AVM_C4_POLLDEBUG
- AVM_CARDTYPE_B1
- AVM_CARDTYPE_M1
- AVM_CARDTYPE_M2
- AVM_CARDTYPE_T1
- AVM_CTL
- AVM_FLAG
- AVM_FRITZ_PCI
- AVM_FRITZ_PCIV2
- AVM_HDLC_1
- AVM_HDLC_2
- AVM_HDLC_FIFO_1
- AVM_HDLC_FIFO_2
- AVM_HDLC_STATUS_1
- AVM_HDLC_STATUS_2
- AVM_ISACX_DATA
- AVM_ISACX_INDEX
- AVM_ISAC_FIFO
- AVM_ISAC_REG_HIGH
- AVM_ISAC_REG_LOW
- AVM_MAXVERSION
- AVM_NCCI_PER_CHANNEL
- AVM_STATUS0_DIS_TIMER
- AVM_STATUS0_ENA_IRQ
- AVM_STATUS0_IRQ_HDLC
- AVM_STATUS0_IRQ_ISAC
- AVM_STATUS0_IRQ_MASK
- AVM_STATUS0_IRQ_TIMER
- AVM_STATUS0_RESET
- AVM_STATUS0_RES_TIMER
- AVM_STATUS0_TESTBIT
- AVM_STATUS1_ENA_IOM
- AVM_STATUS1_INT_SEL
- AVM_cleanup
- AVM_init
- AVOTON_GPIO
- AVOUTLEN
- AVPLL_A1
- AVPLL_A2
- AVPLL_A3
- AVPLL_A4
- AVPLL_A5
- AVPLL_A6
- AVPLL_A7
- AVPLL_A8
- AVPLL_B1
- AVPLL_B2
- AVPLL_B3
- AVPLL_B4
- AVPLL_B5
- AVPLL_B6
- AVPLL_B7
- AVPLL_B8
- AVPLL_CTRL
- AVR_PWRCTL_CMD
- AVR_PWRCTL_PWROFF
- AVR_PWRCTL_RESET
- AVR_QUOT
- AVS1_MARK
- AVS2_MARK
- AVSNB_CONFIG__AvsEnabledForPstates_MASK
- AVSNB_CONFIG__AvsEnabledForPstates__SHIFT
- AVSNB_CONFIG__AvsOverrideEnabled_MASK
- AVSNB_CONFIG__AvsOverrideEnabled__SHIFT
- AVSNB_CONFIG__AvsOverrideOffset_MASK
- AVSNB_CONFIG__AvsOverrideOffset__SHIFT
- AVSNB_CONFIG__AvsPsmTempCompensation_MASK
- AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT
- AVSNB_CONFIG__RESERVED0_MASK
- AVSNB_CONFIG__RESERVED0__SHIFT
- AVSNB_CONFIG__RESERVED1_MASK
- AVSNB_CONFIG__RESERVED1__SHIFT
- AVSNB_CONFIG__RESERVED_MASK
- AVSNB_CONFIG__RESERVED__SHIFT
- AVSYNC_AHB_CLK
- AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK
- AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT
- AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK
- AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT
- AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK
- AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT
- AVSYNC_EDPPIXEL_CLK
- AVSYNC_EXTPCLK_CLK
- AVSYNC_PCLK0_CLK
- AVSYNC_PCLK1_CLK
- AVSYNC_RESET
- AVSYNC_VP_CLK
- AVS_CMD_AVAILABLE
- AVS_CMD_BALANCE
- AVS_CMD_BBM_ENTER
- AVS_CMD_BBM_EXIT
- AVS_CMD_DISABLE
- AVS_CMD_ENABLE
- AVS_CMD_GET_PMAP
- AVS_CMD_GET_PSTATE
- AVS_CMD_S2_ENTER
- AVS_CMD_S2_EXIT
- AVS_CMD_S3_ENTER
- AVS_CMD_S3_EXIT
- AVS_CMD_SET_PMAP
- AVS_CMD_SET_PSTATE
- AVS_CONFIG__AvsEnabledForPstates_MASK
- AVS_CONFIG__AvsEnabledForPstates__SHIFT
- AVS_CONFIG__AvsOverrideEnabled_MASK
- AVS_CONFIG__AvsOverrideEnabled__SHIFT
- AVS_CONFIG__AvsOverrideOffset_MASK
- AVS_CONFIG__AvsOverrideOffset__SHIFT
- AVS_CONFIG__AvsPsmTempCompensation_MASK
- AVS_CONFIG__AvsPsmTempCompensation__SHIFT
- AVS_CONFIG__RESERVED1_MASK
- AVS_CONFIG__RESERVED1__SHIFT
- AVS_CONFIG__RESERVED_MASK
- AVS_CONFIG__RESERVED__SHIFT
- AVS_CPU_L2_INT_MASK
- AVS_CPU_L2_SET0
- AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK
- AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT
- AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK
- AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT
- AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK
- AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT
- AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK
- AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT
- AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK
- AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT
- AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK
- AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT
- AVS_FIRMWARE_MAGIC
- AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK
- AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT
- AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK
- AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT
- AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK
- AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT
- AVS_LOOP_LIMIT
- AVS_MAX_CMD_ARGS
- AVS_MBOX_COMMAND
- AVS_MBOX_FREQUENCY
- AVS_MBOX_HEARTBEAT
- AVS_MBOX_MAGIC
- AVS_MBOX_MV0
- AVS_MBOX_MV1
- AVS_MBOX_PARAM
- AVS_MBOX_PSTATE
- AVS_MBOX_PV0
- AVS_MBOX_PV1
- AVS_MBOX_REVISION
- AVS_MBOX_SIGMA_HVT
- AVS_MBOX_SIGMA_SVT
- AVS_MBOX_STATUS
- AVS_MBOX_TEMP0
- AVS_MBOX_TEMP1
- AVS_MBOX_VOLTAGE0
- AVS_MBOX_VOLTAGE1
- AVS_MODE_AVS
- AVS_MODE_DFS
- AVS_MODE_DVFS
- AVS_MODE_DVS
- AVS_PARAM_MULT
- AVS_PSTATE_MAX
- AVS_PSTATE_P0
- AVS_PSTATE_P1
- AVS_PSTATE_P2
- AVS_PSTATE_P3
- AVS_PSTATE_P4
- AVS_STATUS_CLEAR
- AVS_STATUS_FAILURE
- AVS_STATUS_INVALID
- AVS_STATUS_MAP_SET
- AVS_STATUS_MAX
- AVS_STATUS_NO_MAP
- AVS_STATUS_NO_SUPP
- AVS_STATUS_SUCCESS
- AVS_TIMEOUT
- AVS_TMON_EN_OVERTEMP_RESET
- AVS_TMON_EN_OVERTEMP_RESET_msk
- AVS_TMON_EN_TEMP_INT_SRCS
- AVS_TMON_EN_TEMP_INT_SRCS_high
- AVS_TMON_EN_TEMP_INT_SRCS_low
- AVS_TMON_INT_IDLE_TIME
- AVS_TMON_INT_THRESH
- AVS_TMON_INT_THRESH_high_msk
- AVS_TMON_INT_THRESH_high_shift
- AVS_TMON_INT_THRESH_low_msk
- AVS_TMON_INT_THRESH_low_shift
- AVS_TMON_RESET_THRESH
- AVS_TMON_RESET_THRESH_msk
- AVS_TMON_RESET_THRESH_shift
- AVS_TMON_STATUS
- AVS_TMON_STATUS_data_msk
- AVS_TMON_STATUS_data_shift
- AVS_TMON_STATUS_valid_msk
- AVS_TMON_TEMP_INT_CODE
- AVS_TMON_TEMP_MASK
- AVS_TMON_TEMP_MAX
- AVS_TMON_TEMP_MIN
- AVS_TMON_TEMP_OFFSET
- AVS_TMON_TEMP_SLOPE
- AVS_TMON_TP_TEST_ENABLE
- AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK
- AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT
- AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK
- AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT
- AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK
- AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT
- AVTAB_ALLOWED
- AVTAB_AUDITALLOW
- AVTAB_AUDITDENY
- AVTAB_AV
- AVTAB_CHANGE
- AVTAB_ENABLED
- AVTAB_ENABLED_OLD
- AVTAB_MEMBER
- AVTAB_TRANSITION
- AVTAB_TYPE
- AVTAB_XPERMS
- AVTAB_XPERMS_ALLOWED
- AVTAB_XPERMS_AUDITALLOW
- AVTAB_XPERMS_DONTAUDIT
- AVTAB_XPERMS_IOCTLDRIVER
- AVTAB_XPERMS_IOCTLFUNCTION
- AVX_GEN2_OPTSIZE
- AVX_GEN4_OPTSIZE
- AVX_SELECT
- AVX_XOR_SPEED
- AV_ADD
- AV_FIND
- AV_FIND_OR_ADD
- AV_MODE
- AV_PACKETS_PER_XACT
- AV_PES
- AV_PES_STREAM
- AV_SCRATCH_0
- AV_SCRATCH_1
- AV_SCRATCH_2
- AV_SCRATCH_3
- AV_SCRATCH_4
- AV_SCRATCH_5
- AV_SCRATCH_6
- AV_SCRATCH_7
- AV_SCRATCH_8
- AV_SCRATCH_9
- AV_SCRATCH_A
- AV_SCRATCH_B
- AV_SCRATCH_C
- AV_SCRATCH_D
- AV_SCRATCH_E
- AV_SCRATCH_F
- AV_SCRATCH_G
- AV_SCRATCH_H
- AV_SCRATCH_I
- AV_SCRATCH_J
- AV_SCRATCH_K
- AV_SCRATCH_L
- AV_SPARC_ASI_BLK_INIT
- AV_SPARC_ASI_CACHE_SPARING
- AV_SPARC_CBCOND
- AV_SPARC_DIV32
- AV_SPARC_FJFMAU
- AV_SPARC_FMAF
- AV_SPARC_FSMULD
- AV_SPARC_HPC
- AV_SPARC_IMA
- AV_SPARC_MUL32
- AV_SPARC_PAUSE
- AV_SPARC_POPC
- AV_SPARC_RANDOM
- AV_SPARC_TRANS
- AV_SPARC_V8PLUS
- AV_SPARC_VIS
- AV_SPARC_VIS2
- AV_SPARC_VIS3
- AV_VIDEO_CMD_FFWD
- AV_VIDEO_CMD_FREEZE
- AV_VIDEO_CMD_PLAY
- AV_VIDEO_CMD_SLOW
- AV_VIDEO_CMD_STOP
- AV_WAIT_IDLE_BIT
- AW2_SAA7146_H
- AW2_SAA7146_M
- AWACS_SWITCH
- AWACS_VOLUME
- AWAITING_RESPONSE
- AWAKE
- AWB2_ALIGN_MASK
- AWB2_ALIGN_MASK_SFT
- AWB2_ALIGN_SFT
- AWB2_AXI_WR_SIGN_MASK
- AWB2_AXI_WR_SIGN_MASK_SFT
- AWB2_AXI_WR_SIGN_SFT
- AWB2_DATA_MASK
- AWB2_DATA_MASK_SFT
- AWB2_DATA_SFT
- AWB2_HD_MASK
- AWB2_HD_MASK_SFT
- AWB2_HD_SFT
- AWB2_MODE_MASK
- AWB2_MODE_MASK_SFT
- AWB2_MODE_SFT
- AWB2_NORMAL_MODE_MASK
- AWB2_NORMAL_MODE_MASK_SFT
- AWB2_NORMAL_MODE_SFT
- AWB2_ON_MASK
- AWB2_ON_MASK_SFT
- AWB2_ON_SFT
- AWB2_R_MONO_MASK
- AWB2_R_MONO_MASK_SFT
- AWB2_R_MONO_SFT
- AWBB_BLK
- AWB_ACTRL
- AWB_BGAIN_REG
- AWB_BIAS
- AWB_BMAXB_REG
- AWB_BMAX_REG
- AWB_BMINB_REG
- AWB_BMIN_REG
- AWB_CONTROL_DELAY_FORMATTER
- AWB_CONTROL_SPEED_FORMATTER
- AWB_CTL1_REG
- AWB_CTL2_REG
- AWB_CTL_REG
- AWB_CTRL0
- AWB_CTRL1
- AWB_CTRL10
- AWB_CTRL11
- AWB_CTRL12
- AWB_CTRL13
- AWB_CTRL14
- AWB_CTRL15
- AWB_CTRL16
- AWB_CTRL17
- AWB_CTRL18
- AWB_CTRL19
- AWB_CTRL2
- AWB_CTRL20
- AWB_CTRL21
- AWB_CTRL3
- AWB_CTRL4
- AWB_CTRL5
- AWB_CTRL6
- AWB_CTRL7
- AWB_CTRL8
- AWB_CTRL9
- AWB_DATA_MASK
- AWB_DATA_MASK_SFT
- AWB_DATA_SFT
- AWB_ENABE
- AWB_ENABLE
- AWB_GGAIN_REG
- AWB_HD_ALIGN_MASK
- AWB_HD_ALIGN_MASK_SFT
- AWB_HD_ALIGN_SFT
- AWB_HD_MASK
- AWB_HD_MASK_SFT
- AWB_HD_SFT
- AWB_LOCK
- AWB_MANUAL
- AWB_MODE
- AWB_MODE_MASK
- AWB_MODE_MASK_SFT
- AWB_MODE_SFT
- AWB_MSTR_SIGN_MASK
- AWB_MSTR_SIGN_MASK_SFT
- AWB_MSTR_SIGN_SFT
- AWB_NORMAL_MODE_MASK
- AWB_NORMAL_MODE_MASK_SFT
- AWB_NORMAL_MODE_SFT
- AWB_ON
- AWB_ON_MASK
- AWB_ON_MASK_SFT
- AWB_ON_SFT
- AWB_RGAIN_REG
- AWB_RMAXB_REG
- AWB_RMAX_REG
- AWB_RMINB_REG
- AWB_RMIN_REG
- AWB_R_MONO_MASK
- AWB_R_MONO_MASK_SFT
- AWB_R_MONO_SFT
- AWB_WGHT_REG
- AWCACHE_DEFAULT_VALUE
- AWCCR_OFFSET
- AWCR_AAH
- AWCR_AAW
- AWDATA
- AWDATA_RX
- AWE_INIT1
- AWE_INIT2
- AWE_INIT3
- AWE_INIT4
- AWG_DELAY
- AWG_DELAY_ED
- AWG_DELAY_HD
- AWG_DELAY_SD
- AWG_MAX_ARG
- AWG_MAX_INST
- AWG_OPCODE_OFFSET
- AWINPOS
- AWINZ
- AWQOS_AWCACHE_CFG
- AWRITE
- AWRITE_MASK
- AWRITE_SHIFT
- AWUSER_M_CFG_ENABLE
- AX
- AX25_6PACK_HEADER_LEN
- AX25_ADDR_LEN
- AX25_BACKOFF
- AX25_BPQ_HEADER_LEN
- AX25_CBIT
- AX25_COMMAND
- AX25_COND_ACK_PENDING
- AX25_COND_DAMA_MODE
- AX25_COND_OWN_RX_BUSY
- AX25_COND_PEER_RX_BUSY
- AX25_COND_REJECT
- AX25_DAMA_FLAG
- AX25_DEF_AXDEFMODE
- AX25_DEF_BACKOFF
- AX25_DEF_CONMODE
- AX25_DEF_DS_TIMEOUT
- AX25_DEF_EWINDOW
- AX25_DEF_IDLE
- AX25_DEF_IPDEFMODE
- AX25_DEF_N2
- AX25_DEF_PACLEN
- AX25_DEF_PROTOCOL
- AX25_DEF_T1
- AX25_DEF_T2
- AX25_DEF_T3
- AX25_DEF_WINDOW
- AX25_DIGI_HEADER_LEN
- AX25_DISC
- AX25_DM
- AX25_EBIT
- AX25_EMODULUS
- AX25_EPF
- AX25_ESSID_SPARE
- AX25_EXTSEQ
- AX25_FRMR
- AX25_HBIT
- AX25_HEADER_LEN
- AX25_I
- AX25_IAMDIGI
- AX25_IDLE
- AX25_ILLEGAL
- AX25_KERNEL_H
- AX25_KILL
- AX25_KISS_HEADER_LEN
- AX25_MAX_DIGIS
- AX25_MAX_HEADER_LEN
- AX25_MAX_VALUES
- AX25_MODULUS
- AX25_MTU
- AX25_N2
- AX25_NOUID_BLOCK
- AX25_NOUID_DEFAULT
- AX25_PACLEN
- AX25_PF
- AX25_PIDINCL
- AX25_POLLOFF
- AX25_POLLON
- AX25_PROTO_DAMA_MASTER
- AX25_PROTO_DAMA_SLAVE
- AX25_PROTO_MAX
- AX25_PROTO_STD_DUPLEX
- AX25_PROTO_STD_SIMPLEX
- AX25_P_ARP
- AX25_P_ATALK
- AX25_P_ATALK_ARP
- AX25_P_FLEXNET
- AX25_P_IP
- AX25_P_LQ
- AX25_P_NETROM
- AX25_P_ROSE
- AX25_P_SEGMENT
- AX25_P_TEXNET
- AX25_P_TEXT
- AX25_P_VJCOMP
- AX25_P_VJUNCOMP
- AX25_REJ
- AX25_RESPONSE
- AX25_RNR
- AX25_RR
- AX25_S
- AX25_SABM
- AX25_SABME
- AX25_SEG_FIRST
- AX25_SEG_REM
- AX25_SET_RT_IPMODE
- AX25_SSSID_SPARE
- AX25_STATE_0
- AX25_STATE_1
- AX25_STATE_2
- AX25_STATE_3
- AX25_STATE_4
- AX25_T1
- AX25_T1CLAMPHI
- AX25_T1CLAMPLO
- AX25_T2
- AX25_T3
- AX25_TEST
- AX25_U
- AX25_UA
- AX25_UI
- AX25_VALUES_AXDEFMODE
- AX25_VALUES_BACKOFF
- AX25_VALUES_CONMODE
- AX25_VALUES_DS_TIMEOUT
- AX25_VALUES_EWINDOW
- AX25_VALUES_IDLE
- AX25_VALUES_IPDEFMODE
- AX25_VALUES_N2
- AX25_VALUES_PACLEN
- AX25_VALUES_PROTOCOL
- AX25_VALUES_T1
- AX25_VALUES_T2
- AX25_VALUES_T3
- AX25_VALUES_WINDOW
- AX25_WINDOW
- AX25_XID
- AX88140
- AX88172_CMD_READ_NODE_ID
- AX88172_MEDIUM_DEFAULT
- AX88172_MEDIUM_FC
- AX88172_MEDIUM_FD
- AX88172_MEDIUM_TX
- AX88178_MEDIUM_DEFAULT
- AX88179_EEPROM_MAGIC
- AX88179_PHY_ID
- AX88190_init
- AX88772A_PHY14H
- AX88772A_PHY14H_DEFAULT
- AX88772A_PHY15H
- AX88772A_PHY15H_DEFAULT
- AX88772A_PHY16H
- AX88772A_PHY16H_DEFAULT
- AX88772_IPG0_DEFAULT
- AX88772_IPG1_DEFAULT
- AX88772_IPG2_DEFAULT
- AX88772_MEDIUM_DEFAULT
- AX88796
- AX88796L_IO_BASE
- AX88796_PLATFORM
- AXC001_CREG
- AXC001_GPIO_INTC
- AXC001_SLV_AXI2APB
- AXC001_SLV_AXI_TUNNEL
- AXC001_SLV_DDR_PORT0
- AXC001_SLV_DDR_PORT1
- AXC001_SLV_NONE
- AXC001_SLV_SRAM
- AXC003_CREG
- AXC003_MST_AXI_TUNNEL
- AXC003_MST_HS38
- AXESSTEL_PRODUCT_MV110H
- AXESSTEL_VENDOR_ID
- AXFLG_HAS_93CX6
- AXFLG_HAS_EEPROM
- AXFLG_MAC_FROMDEV
- AXFLG_MAC_FROMPLATFORM
- AXF_ERROR
- AXF_ESCAPE
- AXF_INUSE
- AXF_KEEPTEST
- AXF_OUTWAIT
- AXGMAC_CONFIG_0
- AXGMAC_CONFIG_1
- AXG_AO_GATE
- AXG_ARB_FRDDR_A
- AXG_ARB_FRDDR_B
- AXG_ARB_FRDDR_C
- AXG_ARB_TODDR_A
- AXG_ARB_TODDR_B
- AXG_ARB_TODDR_C
- AXG_FIFO_BURST
- AXG_FIFO_CH_MAX
- AXG_FIFO_FORMATS
- AXG_FIFO_MIN_CNT
- AXG_FIFO_MIN_DEPTH
- AXG_FIFO_RATES
- AXG_SPDIFIN_IEC958_MASK
- AXG_SPDIFIN_IEC958_STATUS
- AXG_SPDIFIN_LOCK_RATE
- AXG_TDM_CHANNEL_MAX
- AXG_TDM_FORMATS
- AXG_TDM_NUM_LANES
- AXG_TDM_RATES
- AXI0_READ_DATA_BEATS_TOTAL
- AXI0_READ_REQUESTS_TOTAL
- AXI0_WRITE_DATA_BEATS_TOTAL
- AXI0_WRITE_REQUESTS_TOTAL
- AXI1_READ_DATA_BEATS_TOTAL
- AXI1_READ_REQUESTS_TOTAL
- AXI1_WRITE_DATA_BEATS_TOTAL
- AXI1_WRITE_REQUESTS_TOTAL
- AXI2_READ_DATA_BEATS_TOTAL
- AXI2_READ_REQUESTS_TOTAL
- AXI2_WRITE_DATA_BEATS_TOTAL
- AXI2_WRITE_REQUESTS_TOTAL
- AXI3_AxCACHE_WB_READ_ALLOC
- AXI3_READ_DATA_BEATS_TOTAL
- AXI3_READ_REQUESTS_TOTAL
- AXI3_WRITE_DATA_BEATS_TOTAL
- AXI3_WRITE_REQUESTS_TOTAL
- AXICC_ARCA_VAL
- AXICC_ARCF_VAL
- AXICC_ARCH_VAL
- AXICC_ARCP_VAL
- AXICC_AWCD_VAL
- AXICC_AWCFD_VAL
- AXICC_AWCF_VAL
- AXIDCG
- AXIEID_MASK
- AXIENET_REGS_N
- AXIE_MASK
- AXIM_MON_COMP_VALUE
- AXIM_R
- AXIOHM_DEVICE_ID_EPIC_A225
- AXIOHM_DEVICE_ID_EPIC_A758
- AXIOHM_DEVICE_ID_EPIC_A794
- AXIOHM_DEVICE_ID_MASK
- AXIRDSPERRLOG
- AXIRP_MASK
- AXIS_ADJUST
- AXIS_DMI_MATCH
- AXIS_DMI_MATCH2
- AXIS_MAX
- AXIS_OFFSET
- AXIS_RANGE
- AXIS_SIZE
- AXIS_X
- AXIS_XYZR_MAX
- AXIS_XYZ_MAX
- AXIS_Y
- AXIS_Z
- AXIWP_MASK
- AXIWRSPERRLOG
- AXI_2X1_CG_DISABLE_MASK
- AXI_2X1_CG_DISABLE_MASK_SFT
- AXI_2X1_CG_DISABLE_SFT
- AXI_ACTIVE
- AXI_ADDR_OFFSET_IP
- AXI_AHB_CLK_CFG
- AXI_ARB_BLOCKS
- AXI_BASE_OFFSET
- AXI_BLEN
- AXI_BUS_ERROR_IRQ
- AXI_BUS_ERROR_IRQ_ENA
- AXI_BUS_ERROR_IRQ_ENA_MASK
- AXI_BUS_ERROR_IRQ_MASK
- AXI_CFG
- AXI_CLKGEN_V2_DRP_CNTRL_READ
- AXI_CLKGEN_V2_DRP_CNTRL_SEL
- AXI_CLKGEN_V2_DRP_STATUS_BUSY
- AXI_CLKGEN_V2_REG_CLKSEL
- AXI_CLKGEN_V2_REG_DRP_CNTRL
- AXI_CLKGEN_V2_REG_DRP_STATUS
- AXI_CLKGEN_V2_REG_RESET
- AXI_CLKGEN_V2_RESET_ENABLE
- AXI_CLKGEN_V2_RESET_MMCM_ENABLE
- AXI_CLK_SRC
- AXI_DATA_BEATS_TOTAL
- AXI_DMAC_BUS_TYPE_AXI_MM
- AXI_DMAC_BUS_TYPE_AXI_STREAM
- AXI_DMAC_BUS_TYPE_FIFO
- AXI_DMAC_CTRL_ENABLE
- AXI_DMAC_CTRL_PAUSE
- AXI_DMAC_FLAG_CYCLIC
- AXI_DMAC_FLAG_LAST
- AXI_DMAC_FLAG_PARTIAL_REPORT
- AXI_DMAC_FLAG_PARTIAL_XFER_DONE
- AXI_DMAC_IRQ_EOT
- AXI_DMAC_IRQ_SOT
- AXI_DMAC_REG_ACTIVE_TRANSFER_ID
- AXI_DMAC_REG_CTRL
- AXI_DMAC_REG_CURRENT_DEST_ADDR
- AXI_DMAC_REG_CURRENT_SRC_ADDR
- AXI_DMAC_REG_DEST_ADDRESS
- AXI_DMAC_REG_DEST_STRIDE
- AXI_DMAC_REG_FLAGS
- AXI_DMAC_REG_IRQ_MASK
- AXI_DMAC_REG_IRQ_PENDING
- AXI_DMAC_REG_IRQ_SOURCE
- AXI_DMAC_REG_PARTIAL_XFER_ID
- AXI_DMAC_REG_PARTIAL_XFER_LEN
- AXI_DMAC_REG_SRC_ADDRESS
- AXI_DMAC_REG_SRC_STRIDE
- AXI_DMAC_REG_START_TRANSFER
- AXI_DMAC_REG_STATUS
- AXI_DMAC_REG_TRANSFER_DONE
- AXI_DMAC_REG_TRANSFER_ID
- AXI_DMAC_REG_X_LENGTH
- AXI_DMAC_REG_Y_LENGTH
- AXI_DMAC_SG_UNUSED
- AXI_DMA_BUSWIDTHS
- AXI_EP_CFG_ACCESS
- AXI_ERR_INFO_MSK
- AXI_ERR_INFO_OFF
- AXI_ERR_SHIFT
- AXI_EXTRA_SHIFT
- AXI_HALTACK_REG
- AXI_HALTREQ_REG
- AXI_I2S_BITS_PER_FRAME
- AXI_I2S_CTRL_RX_EN
- AXI_I2S_CTRL_TX_EN
- AXI_I2S_REG_CLK_CTRL
- AXI_I2S_REG_CTRL
- AXI_I2S_REG_RESET
- AXI_I2S_REG_RX_FIFO
- AXI_I2S_REG_STATUS
- AXI_I2S_REG_TX_FIFO
- AXI_I2S_RESET_GLOBAL
- AXI_I2S_RESET_RX_FIFO
- AXI_I2S_RESET_TX_FIFO
- AXI_ID
- AXI_IDLE_REG
- AXI_ID_MODE_REG
- AXI_INT_DMAINT
- AXI_INT_EPCINT
- AXI_INT_PRDEN_CLR_STA
- AXI_INT_PRDEN_CLR_STA_SHIFT
- AXI_INT_PRDERR_STA
- AXI_INT_PRDERR_STA_SHIFT
- AXI_LATENCY_TOO_LONGR_IRQ
- AXI_LATENCY_TOO_LONGR_IRQ_MASK
- AXI_LATENCY_TOO_LONG_IRQ_ENA
- AXI_LATENCY_TOO_LONG_IRQ_ENA_MASK
- AXI_MASKING_REVERT
- AXI_MASTER_CFG_BASE
- AXI_MODE_REG
- AXI_M_CFG
- AXI_M_CFG_ENABLE
- AXI_NON_BLOCKING_WR
- AXI_NOT_SECURE
- AXI_PHYS_BASE
- AXI_PHYS_SIZE
- AXI_RD_BEATS_MASK
- AXI_RD_BEATS_SHIFT
- AXI_READ_DATA_BEATS_ID_0
- AXI_READ_DATA_BEATS_ID_1
- AXI_READ_DATA_BEATS_ID_10
- AXI_READ_DATA_BEATS_ID_11
- AXI_READ_DATA_BEATS_ID_12
- AXI_READ_DATA_BEATS_ID_13
- AXI_READ_DATA_BEATS_ID_14
- AXI_READ_DATA_BEATS_ID_15
- AXI_READ_DATA_BEATS_ID_2
- AXI_READ_DATA_BEATS_ID_3
- AXI_READ_DATA_BEATS_ID_4
- AXI_READ_DATA_BEATS_ID_5
- AXI_READ_DATA_BEATS_ID_6
- AXI_READ_DATA_BEATS_ID_7
- AXI_READ_DATA_BEATS_ID_8
- AXI_READ_DATA_BEATS_ID_9
- AXI_READ_DATA_BEATS_TOTAL
- AXI_READ_REQUESTS_ID_0
- AXI_READ_REQUESTS_ID_1
- AXI_READ_REQUESTS_ID_10
- AXI_READ_REQUESTS_ID_11
- AXI_READ_REQUESTS_ID_12
- AXI_READ_REQUESTS_ID_13
- AXI_READ_REQUESTS_ID_14
- AXI_READ_REQUESTS_ID_15
- AXI_READ_REQUESTS_ID_2
- AXI_READ_REQUESTS_ID_3
- AXI_READ_REQUESTS_ID_4
- AXI_READ_REQUESTS_ID_5
- AXI_READ_REQUESTS_ID_6
- AXI_READ_REQUESTS_ID_7
- AXI_READ_REQUESTS_ID_8
- AXI_READ_REQUESTS_ID_9
- AXI_READ_REQUESTS_TOTAL
- AXI_READ_REQUEST_HELD_OFF
- AXI_REGION_0_SIZE
- AXI_REGION_SIZE
- AXI_REQUEST_HELD_OFF
- AXI_SECURE
- AXI_SLAVE_OPT1
- AXI_SLV_ADDR
- AXI_SPDIF_CTRL_CLKDIV_MASK
- AXI_SPDIF_CTRL_CLKDIV_OFFSET
- AXI_SPDIF_CTRL_TXDATA
- AXI_SPDIF_CTRL_TXEN
- AXI_SPDIF_FREQ_32000
- AXI_SPDIF_FREQ_44100
- AXI_SPDIF_FREQ_48000
- AXI_SPDIF_FREQ_NA
- AXI_SPDIF_REG_CTRL
- AXI_SPDIF_REG_STAT
- AXI_SPDIF_REG_TX_FIFO
- AXI_TOTAL_REQUESTS
- AXI_USER1
- AXI_USER2
- AXI_VIRT_BASE
- AXI_WINDOW_ALIGN_MASK
- AXI_WRAPPER_IO_WRITE
- AXI_WRAPPER_MEM_WRITE
- AXI_WRAPPER_NOR_MSG
- AXI_WRAPPER_TYPE0_CFG
- AXI_WRAPPER_TYPE1_CFG
- AXI_WRITE_DATA_BEATS_ID_0
- AXI_WRITE_DATA_BEATS_ID_1
- AXI_WRITE_DATA_BEATS_ID_10
- AXI_WRITE_DATA_BEATS_ID_11
- AXI_WRITE_DATA_BEATS_ID_12
- AXI_WRITE_DATA_BEATS_ID_13
- AXI_WRITE_DATA_BEATS_ID_14
- AXI_WRITE_DATA_BEATS_ID_15
- AXI_WRITE_DATA_BEATS_ID_2
- AXI_WRITE_DATA_BEATS_ID_3
- AXI_WRITE_DATA_BEATS_ID_4
- AXI_WRITE_DATA_BEATS_ID_5
- AXI_WRITE_DATA_BEATS_ID_6
- AXI_WRITE_DATA_BEATS_ID_7
- AXI_WRITE_DATA_BEATS_ID_8
- AXI_WRITE_DATA_BEATS_ID_9
- AXI_WRITE_DATA_BEATS_TOTAL
- AXI_WRITE_DATA_HELD_OFF
- AXI_WRITE_REQUESTS_ID_0
- AXI_WRITE_REQUESTS_ID_1
- AXI_WRITE_REQUESTS_ID_10
- AXI_WRITE_REQUESTS_ID_11
- AXI_WRITE_REQUESTS_ID_12
- AXI_WRITE_REQUESTS_ID_13
- AXI_WRITE_REQUESTS_ID_14
- AXI_WRITE_REQUESTS_ID_15
- AXI_WRITE_REQUESTS_ID_2
- AXI_WRITE_REQUESTS_ID_3
- AXI_WRITE_REQUESTS_ID_4
- AXI_WRITE_REQUESTS_ID_5
- AXI_WRITE_REQUESTS_ID_6
- AXI_WRITE_REQUESTS_ID_7
- AXI_WRITE_REQUESTS_ID_8
- AXI_WRITE_REQUESTS_ID_9
- AXI_WRITE_REQUESTS_TOTAL
- AXI_WRITE_REQUEST_HELD_OFF
- AXI_WR_BEATS_MASK
- AXI_WR_BEATS_SHIFT
- AXNET_CMD
- AXNET_DATAPORT
- AXNET_GPIO
- AXNET_MII_EEP
- AXNET_RDC_TIMEOUT
- AXNET_RESET
- AXNET_START_PG
- AXNET_STOP_PG
- AXNET_TEST
- AXP152_ALDO12_V_OUT
- AXP152_ALDO_OP_MODE
- AXP152_DCDC1_V_OUT
- AXP152_DCDC2_V_OUT
- AXP152_DCDC2_V_RAMP
- AXP152_DCDC3_V_OUT
- AXP152_DCDC4_V_OUT
- AXP152_DCDC_FREQ
- AXP152_DCDC_MODE
- AXP152_DLDO1_V_OUT
- AXP152_DLDO2_V_OUT
- AXP152_GPIO0_CTRL
- AXP152_GPIO1_CTRL
- AXP152_GPIO2_CTRL
- AXP152_GPIO3_CTRL
- AXP152_GPIO_INPUT
- AXP152_ID
- AXP152_IRQ1_EN
- AXP152_IRQ1_STATE
- AXP152_IRQ2_EN
- AXP152_IRQ2_STATE
- AXP152_IRQ3_EN
- AXP152_IRQ3_STATE
- AXP152_IRQ_ALDO0IN_CONNECT
- AXP152_IRQ_ALDO0IN_REMOVAL
- AXP152_IRQ_DCDC1_V_LOW
- AXP152_IRQ_DCDC2_V_LOW
- AXP152_IRQ_DCDC3_V_LOW
- AXP152_IRQ_DCDC4_V_LOW
- AXP152_IRQ_GPIO0_INPUT
- AXP152_IRQ_GPIO1_INPUT
- AXP152_IRQ_GPIO2_INPUT
- AXP152_IRQ_GPIO3_INPUT
- AXP152_IRQ_LDO0IN_CONNECT
- AXP152_IRQ_LDO0IN_REMOVAL
- AXP152_IRQ_PEK_FAL_EDGE
- AXP152_IRQ_PEK_LONG
- AXP152_IRQ_PEK_RIS_EDGE
- AXP152_IRQ_PEK_SHORT
- AXP152_IRQ_TIMER
- AXP152_LDO0_CTRL
- AXP152_LDO3456_DC1234_CTRL
- AXP152_LDOGPIO2_V_OUT
- AXP152_OFF_CTRL
- AXP152_PEK_KEY
- AXP152_PWM0_DUTY_CYCLE
- AXP152_PWM0_FREQ_X
- AXP152_PWM0_FREQ_Y
- AXP152_PWM1_DUTY_CYCLE
- AXP152_PWM1_FREQ_X
- AXP152_PWM1_FREQ_Y
- AXP152_PWR_OP_MODE
- AXP152_V_OFF
- AXP202_ID
- AXP209_FG_PERCENT
- AXP209_ID
- AXP20X_ACIN_I
- AXP20X_ACIN_I_ADC_H
- AXP20X_ACIN_I_ADC_L
- AXP20X_ACIN_V
- AXP20X_ACIN_V_ADC_H
- AXP20X_ACIN_V_ADC_L
- AXP20X_ADC_CHANNEL
- AXP20X_ADC_CHANNEL_OFFSET
- AXP20X_ADC_EN1
- AXP20X_ADC_EN1_MASK
- AXP20X_ADC_EN1_VBUS_CURR
- AXP20X_ADC_EN1_VBUS_VOLT
- AXP20X_ADC_EN2
- AXP20X_ADC_EN2_MASK
- AXP20X_ADC_RATE
- AXP20X_ADC_RATE_HZ
- AXP20X_ADC_RATE_MASK
- AXP20X_APS_WARN_L1
- AXP20X_APS_WARN_L2
- AXP20X_BATT_CHRG_I
- AXP20X_BATT_CHRG_I_H
- AXP20X_BATT_CHRG_I_L
- AXP20X_BATT_DISCHRG_I
- AXP20X_BATT_DISCHRG_I_H
- AXP20X_BATT_DISCHRG_I_L
- AXP20X_BATT_V
- AXP20X_BATT_V_H
- AXP20X_BATT_V_L
- AXP20X_CC_CTRL
- AXP20X_CHRG_BAK_CTRL
- AXP20X_CHRG_CC_15_8
- AXP20X_CHRG_CC_23_16
- AXP20X_CHRG_CC_31_24
- AXP20X_CHRG_CC_7_0
- AXP20X_CHRG_CTRL1
- AXP20X_CHRG_CTRL1_TGT_4_15V
- AXP20X_CHRG_CTRL1_TGT_4_1V
- AXP20X_CHRG_CTRL1_TGT_4_2V
- AXP20X_CHRG_CTRL1_TGT_4_36V
- AXP20X_CHRG_CTRL1_TGT_CURR
- AXP20X_CHRG_CTRL1_TGT_VOLT
- AXP20X_CHRG_CTRL2
- AXP20X_DATACACHE
- AXP20X_DCDC2
- AXP20X_DCDC2_LDO3_V_RAMP
- AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN
- AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK
- AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE
- AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK
- AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN
- AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK
- AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE
- AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK
- AXP20X_DCDC2_V_OUT
- AXP20X_DCDC2_V_OUT_MASK
- AXP20X_DCDC3
- AXP20X_DCDC3_V_OUT
- AXP20X_DCDC3_V_OUT_MASK
- AXP20X_DCDC_FREQ
- AXP20X_DCDC_MODE
- AXP20X_DISCHRG_CC_15_8
- AXP20X_DISCHRG_CC_23_16
- AXP20X_DISCHRG_CC_31_24
- AXP20X_DISCHRG_CC_7_0
- AXP20X_FG_RES
- AXP20X_FREQ_DCDC_MASK
- AXP20X_FUNCS_NB
- AXP20X_FUNC_ADC
- AXP20X_FUNC_GPIO_IN
- AXP20X_FUNC_GPIO_OUT
- AXP20X_FUNC_LDO
- AXP20X_GPIO0_CTRL
- AXP20X_GPIO0_FUNC_MASK
- AXP20X_GPIO0_V
- AXP20X_GPIO0_V_ADC_H
- AXP20X_GPIO0_V_ADC_L
- AXP20X_GPIO10_IN_RANGE
- AXP20X_GPIO10_IN_RANGE_GPIO0
- AXP20X_GPIO10_IN_RANGE_GPIO0_VAL
- AXP20X_GPIO10_IN_RANGE_GPIO1
- AXP20X_GPIO10_IN_RANGE_GPIO1_VAL
- AXP20X_GPIO1_ADC_IRQ_FAL
- AXP20X_GPIO1_ADC_IRQ_RIS
- AXP20X_GPIO1_CTRL
- AXP20X_GPIO1_FUNC_MASK
- AXP20X_GPIO1_V
- AXP20X_GPIO1_V_ADC_H
- AXP20X_GPIO1_V_ADC_L
- AXP20X_GPIO20_SS
- AXP20X_GPIO2_CTRL
- AXP20X_GPIO3_CTRL
- AXP20X_GPIO_FUNCTIONS
- AXP20X_GPIO_FUNCTION_INPUT
- AXP20X_GPIO_FUNCTION_OUT_HIGH
- AXP20X_GPIO_FUNCTION_OUT_LOW
- AXP20X_IO_DISABLED
- AXP20X_IO_ENABLED
- AXP20X_IPSOUT_V
- AXP20X_IPSOUT_V_HIGH_H
- AXP20X_IPSOUT_V_HIGH_L
- AXP20X_IRQ1_EN
- AXP20X_IRQ1_STATE
- AXP20X_IRQ2_EN
- AXP20X_IRQ2_STATE
- AXP20X_IRQ3_EN
- AXP20X_IRQ3_STATE
- AXP20X_IRQ4_EN
- AXP20X_IRQ4_STATE
- AXP20X_IRQ5_EN
- AXP20X_IRQ5_STATE
- AXP20X_IRQ6_EN
- AXP20X_IRQ6_STATE
- AXP20X_IRQ_ACIN_OVER_V
- AXP20X_IRQ_ACIN_PLUGIN
- AXP20X_IRQ_ACIN_REMOVAL
- AXP20X_IRQ_BATT_ENT_ACT_MODE
- AXP20X_IRQ_BATT_EXIT_ACT_MODE
- AXP20X_IRQ_BATT_PLUGIN
- AXP20X_IRQ_BATT_REMOVAL
- AXP20X_IRQ_BATT_TEMP_HIGH
- AXP20X_IRQ_BATT_TEMP_LOW
- AXP20X_IRQ_CHARG
- AXP20X_IRQ_CHARG_DONE
- AXP20X_IRQ_CHARG_I_LOW
- AXP20X_IRQ_DCDC1_V_LONG
- AXP20X_IRQ_DCDC2_V_LONG
- AXP20X_IRQ_DCDC3_V_LONG
- AXP20X_IRQ_DIE_TEMP_HIGH
- AXP20X_IRQ_GPIO0_INPUT
- AXP20X_IRQ_GPIO1_INPUT
- AXP20X_IRQ_GPIO2_INPUT
- AXP20X_IRQ_GPIO3_INPUT
- AXP20X_IRQ_LOW_PWR_LVL1
- AXP20X_IRQ_LOW_PWR_LVL2
- AXP20X_IRQ_N_OE_PWR_OFF
- AXP20X_IRQ_N_OE_PWR_ON
- AXP20X_IRQ_PEK_FAL_EDGE
- AXP20X_IRQ_PEK_LONG
- AXP20X_IRQ_PEK_RIS_EDGE
- AXP20X_IRQ_PEK_SHORT
- AXP20X_IRQ_TIMER
- AXP20X_IRQ_VBUS_NOT_VALID
- AXP20X_IRQ_VBUS_OVER_V
- AXP20X_IRQ_VBUS_PLUGIN
- AXP20X_IRQ_VBUS_REMOVAL
- AXP20X_IRQ_VBUS_SESS_END
- AXP20X_IRQ_VBUS_SESS_VALID
- AXP20X_IRQ_VBUS_VALID
- AXP20X_IRQ_VBUS_V_LOW
- AXP20X_LDO1
- AXP20X_LDO2
- AXP20X_LDO24_V_OUT
- AXP20X_LDO24_V_OUT_MASK
- AXP20X_LDO3
- AXP20X_LDO3_V_OUT
- AXP20X_LDO3_V_OUT_MASK
- AXP20X_LDO4
- AXP20X_LDO4_V_OUT_1250mV_END
- AXP20X_LDO4_V_OUT_1250mV_START
- AXP20X_LDO4_V_OUT_1250mV_STEPS
- AXP20X_LDO4_V_OUT_1300mV_END
- AXP20X_LDO4_V_OUT_1300mV_START
- AXP20X_LDO4_V_OUT_1300mV_STEPS
- AXP20X_LDO4_V_OUT_2500mV_END
- AXP20X_LDO4_V_OUT_2500mV_START
- AXP20X_LDO4_V_OUT_2500mV_STEPS
- AXP20X_LDO4_V_OUT_2700mV_END
- AXP20X_LDO4_V_OUT_2700mV_START
- AXP20X_LDO4_V_OUT_2700mV_STEPS
- AXP20X_LDO4_V_OUT_3000mV_END
- AXP20X_LDO4_V_OUT_3000mV_START
- AXP20X_LDO4_V_OUT_3000mV_STEPS
- AXP20X_LDO4_V_OUT_NUM_VOLTAGES
- AXP20X_LDO5
- AXP20X_LDO5_V_OUT
- AXP20X_LDO5_V_OUT_MASK
- AXP20X_MUX_ADC
- AXP20X_MUX_GPIO_IN
- AXP20X_MUX_GPIO_OUT
- AXP20X_OCV
- AXP20X_OCV_MAX
- AXP20X_OFF
- AXP20X_OFF_CTRL
- AXP20X_OVER_TMP
- AXP20X_PEK_KEY
- AXP20X_PEK_SHUTDOWN_MASK
- AXP20X_PEK_STARTUP_MASK
- AXP20X_PWR_BATT_H
- AXP20X_PWR_BATT_L
- AXP20X_PWR_BATT_M
- AXP20X_PWR_INPUT_STATUS
- AXP20X_PWR_OP_BATT_ACTIVATED
- AXP20X_PWR_OP_BATT_PRESENT
- AXP20X_PWR_OP_MODE
- AXP20X_PWR_OUT_CTRL
- AXP20X_PWR_OUT_DCDC2_MASK
- AXP20X_PWR_OUT_DCDC3_MASK
- AXP20X_PWR_OUT_EXTEN_MASK
- AXP20X_PWR_OUT_LDO2_MASK
- AXP20X_PWR_OUT_LDO3_MASK
- AXP20X_PWR_OUT_LDO4_MASK
- AXP20X_PWR_STATUS_ACIN_AVAIL
- AXP20X_PWR_STATUS_ACIN_PRESENT
- AXP20X_PWR_STATUS_BAT_CHARGING
- AXP20X_PWR_STATUS_VBUS_PRESENT
- AXP20X_PWR_STATUS_VBUS_USED
- AXP20X_RDC_H
- AXP20X_RDC_L
- AXP20X_REG_ID_MAX
- AXP20X_TEMP_ADC_H
- AXP20X_TEMP_ADC_L
- AXP20X_TIMER_CTRL
- AXP20X_TS_IN
- AXP20X_TS_IN_H
- AXP20X_TS_IN_L
- AXP20X_USB_OTG_STATUS
- AXP20X_USB_STATUS_VBUS_VALID
- AXP20X_VBUS_CLIMIT_100mA
- AXP20X_VBUS_CLIMIT_500mA
- AXP20X_VBUS_CLIMIT_900mA
- AXP20X_VBUS_CLIMIT_MASK
- AXP20X_VBUS_CLIMIT_NONE
- AXP20X_VBUS_I
- AXP20X_VBUS_IPSOUT_MGMT
- AXP20X_VBUS_IPSOUT_MGMT_MASK
- AXP20X_VBUS_I_ADC_H
- AXP20X_VBUS_I_ADC_L
- AXP20X_VBUS_MON
- AXP20X_VBUS_MON_VBUS_VALID
- AXP20X_VBUS_V
- AXP20X_VBUS_VHOLD_MASK
- AXP20X_VBUS_VHOLD_OFFSET
- AXP20X_VBUS_VHOLD_uV
- AXP20X_VBUS_V_ADC_H
- AXP20X_VBUS_V_ADC_L
- AXP20X_V_HTF_CHRG
- AXP20X_V_HTF_DISCHRG
- AXP20X_V_LTF_CHRG
- AXP20X_V_LTF_DISCHRG
- AXP20X_V_OFF
- AXP20X_V_OFF_MASK
- AXP20X_WORKMODE_DCDC2_MASK
- AXP20X_WORKMODE_DCDC3_MASK
- AXP221_ID
- AXP223_ID
- AXP22X_ADC_EN1_MASK
- AXP22X_ADC_RATE_HZ
- AXP22X_ALDO1
- AXP22X_ALDO1_V_OUT
- AXP22X_ALDO1_V_OUT_MASK
- AXP22X_ALDO2
- AXP22X_ALDO2_V_OUT
- AXP22X_ALDO2_V_OUT_MASK
- AXP22X_ALDO3
- AXP22X_ALDO3_V_OUT
- AXP22X_ALDO3_V_OUT_MASK
- AXP22X_BATLOW_THRES1
- AXP22X_BATT_CHRG_I
- AXP22X_BATT_DISCHRG_I
- AXP22X_BATT_V
- AXP22X_CHRG_CTRL1_TGT_4_22V
- AXP22X_CHRG_CTRL1_TGT_4_24V
- AXP22X_CHRG_CTRL3
- AXP22X_DC1SW
- AXP22X_DC5LDO
- AXP22X_DC5LDO_V_OUT
- AXP22X_DC5LDO_V_OUT_MASK
- AXP22X_DCDC1
- AXP22X_DCDC1_V_OUT
- AXP22X_DCDC1_V_OUT_MASK
- AXP22X_DCDC2
- AXP22X_DCDC23_V_RAMP_CTRL
- AXP22X_DCDC2_V_OUT
- AXP22X_DCDC2_V_OUT_MASK
- AXP22X_DCDC3
- AXP22X_DCDC3_V_OUT
- AXP22X_DCDC3_V_OUT_MASK
- AXP22X_DCDC4
- AXP22X_DCDC4_V_OUT
- AXP22X_DCDC4_V_OUT_MASK
- AXP22X_DCDC5
- AXP22X_DCDC5_V_OUT
- AXP22X_DCDC5_V_OUT_MASK
- AXP22X_DLDO1
- AXP22X_DLDO1_V_OUT
- AXP22X_DLDO1_V_OUT_MASK
- AXP22X_DLDO2
- AXP22X_DLDO2_V_OUT
- AXP22X_DLDO2_V_OUT_MASK
- AXP22X_DLDO3
- AXP22X_DLDO3_V_OUT
- AXP22X_DLDO3_V_OUT_MASK
- AXP22X_DLDO4
- AXP22X_DLDO4_V_OUT
- AXP22X_DLDO4_V_OUT_MASK
- AXP22X_ELDO1
- AXP22X_ELDO1_V_OUT
- AXP22X_ELDO1_V_OUT_MASK
- AXP22X_ELDO2
- AXP22X_ELDO2_V_OUT
- AXP22X_ELDO2_V_OUT_MASK
- AXP22X_ELDO3
- AXP22X_ELDO3_V_OUT
- AXP22X_ELDO3_V_OUT_MASK
- AXP22X_FG_VALID
- AXP22X_GPIO_PULL_DOWN
- AXP22X_GPIO_STATE
- AXP22X_IO_DISABLED
- AXP22X_IO_ENABLED
- AXP22X_IRQ_ACIN_OVER_V
- AXP22X_IRQ_ACIN_PLUGIN
- AXP22X_IRQ_ACIN_REMOVAL
- AXP22X_IRQ_BATT_ENT_ACT_MODE
- AXP22X_IRQ_BATT_EXIT_ACT_MODE
- AXP22X_IRQ_BATT_PLUGIN
- AXP22X_IRQ_BATT_REMOVAL
- AXP22X_IRQ_BATT_TEMP_HIGH
- AXP22X_IRQ_BATT_TEMP_LOW
- AXP22X_IRQ_CHARG
- AXP22X_IRQ_CHARG_DONE
- AXP22X_IRQ_DIE_TEMP_HIGH
- AXP22X_IRQ_GPIO0_INPUT
- AXP22X_IRQ_GPIO1_INPUT
- AXP22X_IRQ_LOW_PWR_LVL1
- AXP22X_IRQ_LOW_PWR_LVL2
- AXP22X_IRQ_PEK_FAL_EDGE
- AXP22X_IRQ_PEK_LONG
- AXP22X_IRQ_PEK_RIS_EDGE
- AXP22X_IRQ_PEK_SHORT
- AXP22X_IRQ_TIMER
- AXP22X_IRQ_VBUS_OVER_V
- AXP22X_IRQ_VBUS_PLUGIN
- AXP22X_IRQ_VBUS_REMOVAL
- AXP22X_IRQ_VBUS_V_LOW
- AXP22X_LDO_IO0
- AXP22X_LDO_IO0_V_OUT
- AXP22X_LDO_IO0_V_OUT_MASK
- AXP22X_LDO_IO1
- AXP22X_LDO_IO1_V_OUT
- AXP22X_LDO_IO1_V_OUT_MASK
- AXP22X_MISC_N_VBUSEN_FUNC
- AXP22X_PMIC_TEMP_H
- AXP22X_PMIC_TEMP_L
- AXP22X_PWREN_CTRL1
- AXP22X_PWREN_CTRL2
- AXP22X_PWR_OUT_ALDO1_MASK
- AXP22X_PWR_OUT_ALDO2_MASK
- AXP22X_PWR_OUT_ALDO3_MASK
- AXP22X_PWR_OUT_CTRL1
- AXP22X_PWR_OUT_CTRL2
- AXP22X_PWR_OUT_CTRL3
- AXP22X_PWR_OUT_DC1SW_MASK
- AXP22X_PWR_OUT_DC5LDO_MASK
- AXP22X_PWR_OUT_DCDC1_MASK
- AXP22X_PWR_OUT_DCDC2_MASK
- AXP22X_PWR_OUT_DCDC3_MASK
- AXP22X_PWR_OUT_DCDC4_MASK
- AXP22X_PWR_OUT_DCDC5_MASK
- AXP22X_PWR_OUT_DLDO1_MASK
- AXP22X_PWR_OUT_DLDO2_MASK
- AXP22X_PWR_OUT_DLDO3_MASK
- AXP22X_PWR_OUT_DLDO4_MASK
- AXP22X_PWR_OUT_ELDO1_MASK
- AXP22X_PWR_OUT_ELDO2_MASK
- AXP22X_PWR_OUT_ELDO3_MASK
- AXP22X_PWR_OUT_SW_MASK
- AXP22X_REG_ID_MAX
- AXP22X_RTC_LDO
- AXP22X_TS_ADC_H
- AXP22X_TS_ADC_L
- AXP22X_TS_IN
- AXP22X_WORKMODE_DCDCX_MASK
- AXP288_ADC_BATT_CHRG_I
- AXP288_ADC_BATT_DISCHRG_I
- AXP288_ADC_BATT_V
- AXP288_ADC_EN_MASK
- AXP288_ADC_GP
- AXP288_ADC_NR_CHAN
- AXP288_ADC_PMIC
- AXP288_ADC_TS
- AXP288_ADC_TS_BIAS_20UA
- AXP288_ADC_TS_BIAS_40UA
- AXP288_ADC_TS_BIAS_60UA
- AXP288_ADC_TS_BIAS_80UA
- AXP288_ADC_TS_BIAS_MASK
- AXP288_ADC_TS_CURRENT_OFF
- AXP288_ADC_TS_CURRENT_ON
- AXP288_ADC_TS_CURRENT_ON_OFF_MASK
- AXP288_ADC_TS_CURRENT_ON_ONDEMAND
- AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING
- AXP288_ADC_TS_ENABLE
- AXP288_ADC_TS_PIN_CTRL
- AXP288_BC_DET_STAT
- AXP288_BC_DET_STAT_REG
- AXP288_BC_GLOBAL
- AXP288_BC_GLOBAL_REG
- AXP288_BC_USB_STAT
- AXP288_BC_USB_STAT_REG
- AXP288_BC_VBUS_CNTL
- AXP288_BC_VBUS_CNTL_REG
- AXP288_EXTCON_DEV_NAME
- AXP288_FG_CC_CAP_REG
- AXP288_FG_CC_MTR0_REG
- AXP288_FG_CC_MTR1_REG
- AXP288_FG_DES_CAP0_REG
- AXP288_FG_DES_CAP1_REG
- AXP288_FG_INTR_NUM
- AXP288_FG_LOW_CAP_REG
- AXP288_FG_OCVH_REG
- AXP288_FG_OCVL_REG
- AXP288_FG_OCV_CAP_REG
- AXP288_FG_OCV_CURVE_REG
- AXP288_FG_RDC0_REG
- AXP288_FG_RDC1_REG
- AXP288_FG_TUNE0
- AXP288_FG_TUNE1
- AXP288_FG_TUNE2
- AXP288_FG_TUNE3
- AXP288_FG_TUNE4
- AXP288_FG_TUNE5
- AXP288_GP_ADC_H
- AXP288_GP_ADC_L
- AXP288_ID
- AXP288_IRQ_ABSENT
- AXP288_IRQ_APPEND
- AXP288_IRQ_BC_USB_CHNG
- AXP288_IRQ_CBTO
- AXP288_IRQ_CBTU
- AXP288_IRQ_CHARGING
- AXP288_IRQ_DONE
- AXP288_IRQ_FALLING_ALT
- AXP288_IRQ_GPADC
- AXP288_IRQ_GPIO0
- AXP288_IRQ_GPIO1
- AXP288_IRQ_MV_CHNG
- AXP288_IRQ_OT
- AXP288_IRQ_OV
- AXP288_IRQ_OV_ALT
- AXP288_IRQ_POKL
- AXP288_IRQ_POKN
- AXP288_IRQ_POKO
- AXP288_IRQ_POKP
- AXP288_IRQ_POKS
- AXP288_IRQ_QCBTO
- AXP288_IRQ_QCBTU
- AXP288_IRQ_QWBTO
- AXP288_IRQ_QWBTU
- AXP288_IRQ_RISING_ALT
- AXP288_IRQ_SAFE_ENTER
- AXP288_IRQ_SAFE_QUIT
- AXP288_IRQ_TIMER
- AXP288_IRQ_VBUS_FALL
- AXP288_IRQ_VBUS_RISE
- AXP288_IRQ_WBTO
- AXP288_IRQ_WBTU
- AXP288_IRQ_WL1
- AXP288_IRQ_WL2
- AXP288_PMIC_ADC_H
- AXP288_PMIC_ADC_L
- AXP288_POWER_REASON
- AXP288_PS_BOOT_REASON_REG
- AXP288_PS_STAT_REG
- AXP288_RT_BATT_V_H
- AXP288_RT_BATT_V_L
- AXP288_TS_ADC_H
- AXP288_TS_ADC_L
- AXP803_ALDO1
- AXP803_ALDO2
- AXP803_ALDO3
- AXP803_DC1SW
- AXP803_DCDC1
- AXP803_DCDC1_V_OUT
- AXP803_DCDC1_V_OUT_MASK
- AXP803_DCDC2
- AXP803_DCDC234_1220mV_END
- AXP803_DCDC234_1220mV_START
- AXP803_DCDC234_1220mV_STEPS
- AXP803_DCDC234_500mV_END
- AXP803_DCDC234_500mV_START
- AXP803_DCDC234_500mV_STEPS
- AXP803_DCDC234_NUM_VOLTAGES
- AXP803_DCDC23_POLYPHASE_DUAL
- AXP803_DCDC2_V_OUT
- AXP803_DCDC2_V_OUT_MASK
- AXP803_DCDC3
- AXP803_DCDC3_V_OUT
- AXP803_DCDC3_V_OUT_MASK
- AXP803_DCDC4
- AXP803_DCDC4_V_OUT
- AXP803_DCDC4_V_OUT_MASK
- AXP803_DCDC5
- AXP803_DCDC56_POLYPHASE_DUAL
- AXP803_DCDC5_1140mV_END
- AXP803_DCDC5_1140mV_START
- AXP803_DCDC5_1140mV_STEPS
- AXP803_DCDC5_800mV_END
- AXP803_DCDC5_800mV_START
- AXP803_DCDC5_800mV_STEPS
- AXP803_DCDC5_NUM_VOLTAGES
- AXP803_DCDC5_V_OUT
- AXP803_DCDC5_V_OUT_MASK
- AXP803_DCDC6
- AXP803_DCDC6_1120mV_END
- AXP803_DCDC6_1120mV_START
- AXP803_DCDC6_1120mV_STEPS
- AXP803_DCDC6_600mV_END
- AXP803_DCDC6_600mV_START
- AXP803_DCDC6_600mV_STEPS
- AXP803_DCDC6_NUM_VOLTAGES
- AXP803_DCDC6_V_OUT
- AXP803_DCDC6_V_OUT_MASK
- AXP803_DCDC_FREQ_CTRL
- AXP803_DLDO1
- AXP803_DLDO2
- AXP803_DLDO2_3400mV_END
- AXP803_DLDO2_3400mV_START
- AXP803_DLDO2_3400mV_STEPS
- AXP803_DLDO2_700mV_END
- AXP803_DLDO2_700mV_START
- AXP803_DLDO2_700mV_STEPS
- AXP803_DLDO2_NUM_VOLTAGES
- AXP803_DLDO3
- AXP803_DLDO4
- AXP803_ELDO1
- AXP803_ELDO2
- AXP803_ELDO3
- AXP803_FLDO1
- AXP803_FLDO1_V_OUT
- AXP803_FLDO1_V_OUT_MASK
- AXP803_FLDO2
- AXP803_FLDO2_V_OUT
- AXP803_FLDO2_V_OUT_MASK
- AXP803_ID
- AXP803_IRQ_ACIN_OVER_V
- AXP803_IRQ_ACIN_PLUGIN
- AXP803_IRQ_ACIN_REMOVAL
- AXP803_IRQ_BATT_ACT_TEMP_HIGH
- AXP803_IRQ_BATT_ACT_TEMP_HIGH_END
- AXP803_IRQ_BATT_ACT_TEMP_LOW
- AXP803_IRQ_BATT_ACT_TEMP_LOW_END
- AXP803_IRQ_BATT_CHG_TEMP_HIGH
- AXP803_IRQ_BATT_CHG_TEMP_HIGH_END
- AXP803_IRQ_BATT_CHG_TEMP_LOW
- AXP803_IRQ_BATT_CHG_TEMP_LOW_END
- AXP803_IRQ_BATT_ENT_ACT_MODE
- AXP803_IRQ_BATT_EXIT_ACT_MODE
- AXP803_IRQ_BATT_PLUGIN
- AXP803_IRQ_BATT_REMOVAL
- AXP803_IRQ_BC_USB_CHNG
- AXP803_IRQ_CHARG
- AXP803_IRQ_CHARG_DONE
- AXP803_IRQ_DIE_TEMP_HIGH
- AXP803_IRQ_GPADC
- AXP803_IRQ_GPIO0_INPUT
- AXP803_IRQ_GPIO1_INPUT
- AXP803_IRQ_LOW_PWR_LVL1
- AXP803_IRQ_LOW_PWR_LVL2
- AXP803_IRQ_MV_CHNG
- AXP803_IRQ_PEK_FAL_EDGE
- AXP803_IRQ_PEK_LONG
- AXP803_IRQ_PEK_OVER_OFF
- AXP803_IRQ_PEK_RIS_EDGE
- AXP803_IRQ_PEK_SHORT
- AXP803_IRQ_TIMER
- AXP803_IRQ_VBUS_OVER_V
- AXP803_IRQ_VBUS_PLUGIN
- AXP803_IRQ_VBUS_REMOVAL
- AXP803_LDO_IO0
- AXP803_LDO_IO1
- AXP803_POLYPHASE_CTRL
- AXP803_PWR_OUT_DCDC1_MASK
- AXP803_PWR_OUT_DCDC2_MASK
- AXP803_PWR_OUT_DCDC3_MASK
- AXP803_PWR_OUT_DCDC4_MASK
- AXP803_PWR_OUT_DCDC5_MASK
- AXP803_PWR_OUT_DCDC6_MASK
- AXP803_PWR_OUT_FLDO1_MASK
- AXP803_PWR_OUT_FLDO2_MASK
- AXP803_REG_ID_MAX
- AXP803_RTC_LDO
- AXP806_ALDO1
- AXP806_ALDO1_V_CTRL
- AXP806_ALDO1_V_CTRL_MASK
- AXP806_ALDO2
- AXP806_ALDO2_V_CTRL
- AXP806_ALDO2_V_CTRL_MASK
- AXP806_ALDO3
- AXP806_ALDO3_V_CTRL
- AXP806_ALDO3_V_CTRL_MASK
- AXP806_BLDO1
- AXP806_BLDO1_V_CTRL
- AXP806_BLDO1_V_CTRL_MASK
- AXP806_BLDO2
- AXP806_BLDO2_V_CTRL
- AXP806_BLDO2_V_CTRL_MASK
- AXP806_BLDO3
- AXP806_BLDO3_V_CTRL
- AXP806_BLDO3_V_CTRL_MASK
- AXP806_BLDO4
- AXP806_BLDO4_V_CTRL
- AXP806_BLDO4_V_CTRL_MASK
- AXP806_BUS_ADDR_EXT
- AXP806_CHIP_ID
- AXP806_CLDO1
- AXP806_CLDO1_V_CTRL
- AXP806_CLDO1_V_CTRL_MASK
- AXP806_CLDO2
- AXP806_CLDO2_V_CTRL
- AXP806_CLDO2_V_CTRL_MASK
- AXP806_CLDO3
- AXP806_CLDO3_V_CTRL
- AXP806_CLDO3_V_CTRL_MASK
- AXP806_DCDCA
- AXP806_DCDCABC_POLYPHASE_MASK
- AXP806_DCDCABC_POLYPHASE_TRI
- AXP806_DCDCAB_POLYPHASE_DUAL
- AXP806_DCDCA_1120mV_END
- AXP806_DCDCA_1120mV_START
- AXP806_DCDCA_1120mV_STEPS
- AXP806_DCDCA_600mV_END
- AXP806_DCDCA_600mV_START
- AXP806_DCDCA_600mV_STEPS
- AXP806_DCDCA_NUM_VOLTAGES
- AXP806_DCDCA_V_CTRL
- AXP806_DCDCA_V_CTRL_MASK
- AXP806_DCDCB
- AXP806_DCDCB_V_CTRL
- AXP806_DCDCB_V_CTRL_MASK
- AXP806_DCDCC
- AXP806_DCDCC_V_CTRL
- AXP806_DCDCC_V_CTRL_MASK
- AXP806_DCDCD
- AXP806_DCDCDE_POLYPHASE_DUAL
- AXP806_DCDCD_1600mV_END
- AXP806_DCDCD_1600mV_START
- AXP806_DCDCD_1600mV_STEPS
- AXP806_DCDCD_600mV_END
- AXP806_DCDCD_600mV_START
- AXP806_DCDCD_600mV_STEPS
- AXP806_DCDCD_NUM_VOLTAGES
- AXP806_DCDCD_V_CTRL
- AXP806_DCDCD_V_CTRL_MASK
- AXP806_DCDCE
- AXP806_DCDCE_V_CTRL
- AXP806_DCDCE_V_CTRL_MASK
- AXP806_DCDC_FREQ_CTRL
- AXP806_DCDC_MODE_CTRL1
- AXP806_DCDC_MODE_CTRL2
- AXP806_ID
- AXP806_IRQ_DCDCA_V_LOW
- AXP806_IRQ_DCDCB_V_LOW
- AXP806_IRQ_DCDCC_V_LOW
- AXP806_IRQ_DCDCD_V_LOW
- AXP806_IRQ_DCDCE_V_LOW
- AXP806_IRQ_DIE_TEMP_HIGH_LV1
- AXP806_IRQ_DIE_TEMP_HIGH_LV2
- AXP806_IRQ_POK_FALL
- AXP806_IRQ_POK_LONG
- AXP806_IRQ_POK_RISE
- AXP806_IRQ_POK_SHORT
- AXP806_IRQ_WAKEUP
- AXP806_PWR_OUT_ALDO1_MASK
- AXP806_PWR_OUT_ALDO2_MASK
- AXP806_PWR_OUT_ALDO3_MASK
- AXP806_PWR_OUT_BLDO1_MASK
- AXP806_PWR_OUT_BLDO2_MASK
- AXP806_PWR_OUT_BLDO3_MASK
- AXP806_PWR_OUT_BLDO4_MASK
- AXP806_PWR_OUT_CLDO1_MASK
- AXP806_PWR_OUT_CLDO2_MASK
- AXP806_PWR_OUT_CLDO3_MASK
- AXP806_PWR_OUT_CTRL1
- AXP806_PWR_OUT_CTRL2
- AXP806_PWR_OUT_DCDCA_MASK
- AXP806_PWR_OUT_DCDCB_MASK
- AXP806_PWR_OUT_DCDCC_MASK
- AXP806_PWR_OUT_DCDCD_MASK
- AXP806_PWR_OUT_DCDCE_MASK
- AXP806_PWR_OUT_SW_MASK
- AXP806_REG_ADDR_EXT
- AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE
- AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE
- AXP806_REG_ID_MAX
- AXP806_STARTUP_SRC
- AXP806_SW
- AXP806_VREF_TEMP_WARN_L
- AXP809_ALDO1
- AXP809_ALDO2
- AXP809_ALDO3
- AXP809_DC1SW
- AXP809_DC5LDO
- AXP809_DCDC1
- AXP809_DCDC2
- AXP809_DCDC3
- AXP809_DCDC4
- AXP809_DCDC4_1800mV_END
- AXP809_DCDC4_1800mV_START
- AXP809_DCDC4_1800mV_STEPS
- AXP809_DCDC4_600mV_END
- AXP809_DCDC4_600mV_START
- AXP809_DCDC4_600mV_STEPS
- AXP809_DCDC4_NUM_VOLTAGES
- AXP809_DCDC5
- AXP809_DLDO1
- AXP809_DLDO2
- AXP809_ELDO1
- AXP809_ELDO2
- AXP809_ELDO3
- AXP809_ID
- AXP809_IRQ_ACIN_OVER_V
- AXP809_IRQ_ACIN_PLUGIN
- AXP809_IRQ_ACIN_REMOVAL
- AXP809_IRQ_BATT_ACT_TEMP_HIGH
- AXP809_IRQ_BATT_ACT_TEMP_HIGH_END
- AXP809_IRQ_BATT_ACT_TEMP_LOW
- AXP809_IRQ_BATT_ACT_TEMP_LOW_END
- AXP809_IRQ_BATT_CHG_TEMP_HIGH
- AXP809_IRQ_BATT_CHG_TEMP_HIGH_END
- AXP809_IRQ_BATT_CHG_TEMP_LOW
- AXP809_IRQ_BATT_CHG_TEMP_LOW_END
- AXP809_IRQ_BATT_ENT_ACT_MODE
- AXP809_IRQ_BATT_EXIT_ACT_MODE
- AXP809_IRQ_BATT_PLUGIN
- AXP809_IRQ_BATT_REMOVAL
- AXP809_IRQ_CHARG
- AXP809_IRQ_CHARG_DONE
- AXP809_IRQ_DIE_TEMP_HIGH
- AXP809_IRQ_GPIO0_INPUT
- AXP809_IRQ_GPIO1_INPUT
- AXP809_IRQ_LOW_PWR_LVL1
- AXP809_IRQ_LOW_PWR_LVL2
- AXP809_IRQ_PEK_FAL_EDGE
- AXP809_IRQ_PEK_LONG
- AXP809_IRQ_PEK_OVER_OFF
- AXP809_IRQ_PEK_RIS_EDGE
- AXP809_IRQ_PEK_SHORT
- AXP809_IRQ_TIMER
- AXP809_IRQ_VBUS_OVER_V
- AXP809_IRQ_VBUS_PLUGIN
- AXP809_IRQ_VBUS_REMOVAL
- AXP809_IRQ_VBUS_V_LOW
- AXP809_LDO_IO0
- AXP809_LDO_IO1
- AXP809_REG_ID_MAX
- AXP809_RTC_LDO
- AXP809_SW
- AXP813_ACIN_PATH_CTRL
- AXP813_ACIN_PATH_SEL
- AXP813_ADC_RATE
- AXP813_ADC_RATE_HZ
- AXP813_ADC_RATE_MASK
- AXP813_ALDO1
- AXP813_ALDO2
- AXP813_ALDO3
- AXP813_BATT_V
- AXP813_CHRG_CTRL1_TGT_4_35V
- AXP813_CURR_LIMIT_MASK
- AXP813_CURR_LIMIT_REG_TO_UA
- AXP813_CURR_LIMIT_UA_TO_BIT
- AXP813_DCDC1
- AXP813_DCDC2
- AXP813_DCDC3
- AXP813_DCDC4
- AXP813_DCDC5
- AXP813_DCDC6
- AXP813_DCDC7
- AXP813_DCDC7_V_OUT
- AXP813_DCDC7_V_OUT_MASK
- AXP813_DLDO1
- AXP813_DLDO2
- AXP813_DLDO3
- AXP813_DLDO4
- AXP813_ELDO1
- AXP813_ELDO2
- AXP813_ELDO3
- AXP813_FLDO1
- AXP813_FLDO2
- AXP813_FLDO3
- AXP813_GPIO0_V
- AXP813_ID
- AXP813_LDO_IO0
- AXP813_LDO_IO1
- AXP813_MUX_ADC
- AXP813_PWR_OUT_DCDC7_MASK
- AXP813_REG_ID_MAX
- AXP813_RTC_LDO
- AXP813_SW
- AXP813_TS_GPIO0_ADC_RATE_HZ
- AXP813_TS_IN
- AXP813_VBUS_CLIMIT_1500mA
- AXP813_VBUS_CLIMIT_2000mA
- AXP813_VBUS_CLIMIT_2500mA
- AXP813_VBUS_CLIMIT_900mA
- AXP813_VHOLD_MASK
- AXP813_VHOLD_REG_TO_UV
- AXP813_VHOLD_UV_TO_BIT
- AXP813_V_I_ADC_RATE_HZ
- AXP813_V_I_ADC_RATE_MASK
- AXP_BOOTROM_BASE
- AXP_BOOTROM_SIZE
- AXP_CPU_TO_DRAMCLK
- AXP_CPU_TO_HCLK
- AXP_CPU_TO_NBCLK
- AXP_DESC
- AXP_DESC_FIXED
- AXP_DESC_IO
- AXP_DESC_RANGES
- AXP_DESC_SW
- AXRAM_AXRAM_CHANNEL_COUNT
- AXRAM_AXRAM_CHAN_INCR
- AXRAM_AXRAM_INST_OFFSET
- AXRAM_AXRAM_MODULE_OFFSET
- AXRAM_CHIP_OFFSET
- AXS103_QUAD_CORE_CPU_FREQ_HZ
- AXS10X_MAX_RESETS
- AXSIG
- AXS_MB_CGU
- AXS_MB_CREG
- AXS_MB_MST_TUNNEL_CPU
- AXS_MB_MST_USB_OHCI
- AXS_MB_SLV_AXI_TUNNEL_CPU
- AXS_MB_SLV_AXI_TUNNEL_HAPS
- AXS_MB_SLV_CONTROL
- AXS_MB_SLV_NONE
- AXS_MB_SLV_SRAM
- AXUSER_BASE
- AXUSER_CMD_SMMU_NORMAL
- AXUSER_CMD_TYPE
- AXUSER_FP
- AXUSER_NO
- AXUSER_NS
- AXUSER_SNOOP_ENABLE
- AXUSER_SSV
- AXXIA_CLK_CPU0
- AXXIA_CLK_CPU0_DIV
- AXXIA_CLK_CPU1
- AXXIA_CLK_CPU1_DIV
- AXXIA_CLK_CPU2
- AXXIA_CLK_CPU2_DIV
- AXXIA_CLK_CPU3
- AXXIA_CLK_CPU3_DIV
- AXXIA_CLK_CPU_PLL
- AXXIA_CLK_FAB
- AXXIA_CLK_FAB_DIV
- AXXIA_CLK_FAB_PLL
- AXXIA_CLK_MMC
- AXXIA_CLK_MMC_DIV
- AXXIA_CLK_NRCP
- AXXIA_CLK_NRCP_DIV
- AXXIA_CLK_PER
- AXXIA_CLK_PER_DIV
- AXXIA_CLK_SM0_PLL
- AXXIA_CLK_SM1_PLL
- AXXIA_CLK_SYS
- AXXIA_CLK_SYS_DIV
- AXXIA_CLK_SYS_PLL
- AXXX_CP_CSQ_AVAIL_IB1
- AXXX_CP_CSQ_AVAIL_IB1__MASK
- AXXX_CP_CSQ_AVAIL_IB1__SHIFT
- AXXX_CP_CSQ_AVAIL_IB2
- AXXX_CP_CSQ_AVAIL_IB2__MASK
- AXXX_CP_CSQ_AVAIL_IB2__SHIFT
- AXXX_CP_CSQ_AVAIL_RING
- AXXX_CP_CSQ_AVAIL_RING__MASK
- AXXX_CP_CSQ_AVAIL_RING__SHIFT
- AXXX_CP_CSQ_IB1_STAT_RPTR
- AXXX_CP_CSQ_IB1_STAT_RPTR__MASK
- AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT
- AXXX_CP_CSQ_IB1_STAT_WPTR
- AXXX_CP_CSQ_IB1_STAT_WPTR__MASK
- AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT
- AXXX_CP_CSQ_IB2_STAT_RPTR
- AXXX_CP_CSQ_IB2_STAT_RPTR__MASK
- AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT
- AXXX_CP_CSQ_IB2_STAT_WPTR
- AXXX_CP_CSQ_IB2_STAT_WPTR__MASK
- AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT
- AXXX_CP_CSQ_RB_STAT_RPTR
- AXXX_CP_CSQ_RB_STAT_RPTR__MASK
- AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT
- AXXX_CP_CSQ_RB_STAT_WPTR
- AXXX_CP_CSQ_RB_STAT_WPTR__MASK
- AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT
- AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE
- AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE
- AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE
- AXXX_CP_DEBUG_PREDICATE_DISABLE
- AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE
- AXXX_CP_DEBUG_PREFETCH_PASS_NOPS
- AXXX_CP_DEBUG_PROG_END_PTR_ENABLE
- AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL
- AXXX_CP_INT_CNTL_IB1_INT_MASK
- AXXX_CP_INT_CNTL_IB2_INT_MASK
- AXXX_CP_INT_CNTL_IB_ERROR_MASK
- AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK
- AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK
- AXXX_CP_INT_CNTL_RB_INT_MASK
- AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK
- AXXX_CP_INT_CNTL_SW_INT_MASK
- AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK
- AXXX_CP_MEQ_AVAIL_MEQ
- AXXX_CP_MEQ_AVAIL_MEQ__MASK
- AXXX_CP_MEQ_AVAIL_MEQ__SHIFT
- AXXX_CP_MEQ_THRESHOLDS_MEQ_END
- AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK
- AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT
- AXXX_CP_MEQ_THRESHOLDS_ROQ_END
- AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK
- AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT
- AXXX_CP_ME_CNTL_BUSY
- AXXX_CP_ME_CNTL_HALT
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK
- AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT
- AXXX_CP_RB_CNTL_BLKSZ
- AXXX_CP_RB_CNTL_BLKSZ__MASK
- AXXX_CP_RB_CNTL_BLKSZ__SHIFT
- AXXX_CP_RB_CNTL_BUFSZ
- AXXX_CP_RB_CNTL_BUFSZ__MASK
- AXXX_CP_RB_CNTL_BUFSZ__SHIFT
- AXXX_CP_RB_CNTL_BUF_SWAP
- AXXX_CP_RB_CNTL_BUF_SWAP__MASK
- AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT
- AXXX_CP_RB_CNTL_NO_UPDATE
- AXXX_CP_RB_CNTL_POLL_EN
- AXXX_CP_RB_CNTL_RPTR_WR_EN
- AXXX_CP_RB_RPTR_ADDR_ADDR
- AXXX_CP_RB_RPTR_ADDR_ADDR__MASK
- AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT
- AXXX_CP_RB_RPTR_ADDR_SWAP
- AXXX_CP_RB_RPTR_ADDR_SWAP__MASK
- AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT
- AXXX_CP_STAT_CF_EVENT_FIFO_BUSY
- AXXX_CP_STAT_CP_3D_BUSY
- AXXX_CP_STAT_CP_BUSY
- AXXX_CP_STAT_CP_NRT_BUSY
- AXXX_CP_STAT_CSF_BUSY
- AXXX_CP_STAT_CSF_INDIRECT2_BUSY
- AXXX_CP_STAT_CSF_INDIRECTS_BUSY
- AXXX_CP_STAT_CSF_RING_BUSY
- AXXX_CP_STAT_CSF_ST_BUSY
- AXXX_CP_STAT_EVENT_BUSY
- AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY
- AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY
- AXXX_CP_STAT_MEQ_RING_BUSY
- AXXX_CP_STAT_ME_BUSY
- AXXX_CP_STAT_MIU_RD_REQ_BUSY
- AXXX_CP_STAT_MIU_RD_RETURN_BUSY
- AXXX_CP_STAT_MIU_WR_BUSY
- AXXX_CP_STAT_MIU_WR_C_BUSY
- AXXX_CP_STAT_PFP_BUSY
- AXXX_CP_STAT_PS_EVENT_FIFO_BUSY
- AXXX_CP_STAT_RBIU_BUSY
- AXXX_CP_STAT_RBIU_SCRATCH_BUSY
- AXXX_CP_STAT_RB_EVENT_FIFO_BUSY
- AXXX_CP_STAT_RCIU_BUSY
- AXXX_CP_STAT_RCIU_ME_BUSY
- AXXX_CP_STAT_RCIU_PFP_BUSY
- AXXX_CP_STAT_RING_QUEUE_BUSY
- AXXX_CP_STAT_ST_QUEUE_BUSY
- AXXX_CP_STAT_VS_EVENT_FIFO_BUSY
- AXXX_CP_STQ_AVAIL_ST
- AXXX_CP_STQ_AVAIL_ST__MASK
- AXXX_CP_STQ_AVAIL_ST__SHIFT
- AXXX_SCRATCH_UMSK_SWAP
- AXXX_SCRATCH_UMSK_SWAP__MASK
- AXXX_SCRATCH_UMSK_SWAP__SHIFT
- AXXX_SCRATCH_UMSK_UMSK
- AXXX_SCRATCH_UMSK_UMSK__MASK
- AXXX_SCRATCH_UMSK_UMSK__SHIFT
- AX_ACCESS_EEPROM
- AX_ACCESS_EFUS
- AX_ACCESS_MAC
- AX_ACCESS_PHY
- AX_AX88772A_CHIPCODE
- AX_AX88772B_CHIPCODE
- AX_AX88772_CHIPCODE
- AX_CHIPCODE_MASK
- AX_CLK_SELECT
- AX_CLK_SELECT_ACS
- AX_CLK_SELECT_BCS
- AX_CLK_SELECT_ULR
- AX_CMD_READ_EEPROM
- AX_CMD_READ_GPIOS
- AX_CMD_READ_IPG012
- AX_CMD_READ_MEDIUM_STATUS
- AX_CMD_READ_MII_REG
- AX_CMD_READ_MONITOR_MODE
- AX_CMD_READ_NODE_ID
- AX_CMD_READ_PHY_ID
- AX_CMD_READ_RX_CTL
- AX_CMD_SET_HW_MII
- AX_CMD_SET_SW_MII
- AX_CMD_STATMNGSTS_REG
- AX_CMD_SW_PHY_SELECT
- AX_CMD_SW_PHY_STATUS
- AX_CMD_SW_RESET
- AX_CMD_WRITE_DISABLE
- AX_CMD_WRITE_EEPROM
- AX_CMD_WRITE_ENABLE
- AX_CMD_WRITE_GPIOS
- AX_CMD_WRITE_IPG0
- AX_CMD_WRITE_IPG1
- AX_CMD_WRITE_IPG2
- AX_CMD_WRITE_MEDIUM_MODE
- AX_CMD_WRITE_MII_REG
- AX_CMD_WRITE_MONITOR_MODE
- AX_CMD_WRITE_MULTI_FILTER
- AX_CMD_WRITE_NODE_ID
- AX_CMD_WRITE_RX_CTL
- AX_CPR_ATFD
- AX_CPR_SLCTIN
- AX_CPR_STRB
- AX_CPR_nDOE
- AX_CPR_nINIT
- AX_DATAC
- AX_DEFAULT_RX_CTL
- AX_EEPROM_LEN
- AX_EEPROM_MAGIC
- AX_END
- AX_GPIO_CTRL
- AX_GPIO_CTRL_GPIO1EN
- AX_GPIO_CTRL_GPIO2EN
- AX_GPIO_CTRL_GPIO3EN
- AX_GPIO_GPO0EN
- AX_GPIO_GPO1EN
- AX_GPIO_GPO2EN
- AX_GPIO_GPO_0
- AX_GPIO_GPO_1
- AX_GPIO_GPO_2
- AX_GPIO_RESERVED
- AX_GPIO_RSE
- AX_GPOC_PPDSET
- AX_HOST_EN
- AX_INDXC
- AX_INT_PPLS_LINK
- AX_LEDCTRL
- AX_MAX_MCAST
- AX_MCAST_FILTER_SIZE
- AX_MCAST_FLTSIZE
- AX_MEDIUM_AC
- AX_MEDIUM_ENCK
- AX_MEDIUM_EN_125MHZ
- AX_MEDIUM_FD
- AX_MEDIUM_FULL_DUPLEX
- AX_MEDIUM_GIGAMODE
- AX_MEDIUM_GM
- AX_MEDIUM_JFE
- AX_MEDIUM_JUMBO_EN
- AX_MEDIUM_PF
- AX_MEDIUM_PS
- AX_MEDIUM_RE
- AX_MEDIUM_RECEIVE_EN
- AX_MEDIUM_RFC
- AX_MEDIUM_RXFLOW_CTRLEN
- AX_MEDIUM_SBP
- AX_MEDIUM_SM
- AX_MEDIUM_STATUS_MODE
- AX_MEDIUM_TFC
- AX_MEDIUM_TXFLOW_CTRLEN
- AX_MEMR
- AX_MEMR_EECLK
- AX_MEMR_EECS
- AX_MEMR_EEI
- AX_MEMR_EEO
- AX_MEMR_MDC
- AX_MEMR_MDI
- AX_MEMR_MDIR
- AX_MEMR_MDO
- AX_MONITOR_HSFS
- AX_MONITOR_LINK
- AX_MONITOR_MAGIC
- AX_MONITOR_MOD
- AX_MONITOR_MODE
- AX_MONITOR_MODE_PMEPOL
- AX_MONITOR_MODE_PMETYPE
- AX_MONITOR_MODE_RWLC
- AX_MONITOR_MODE_RWMP
- AX_MTU
- AX_MULFLTARY
- AX_NODE_ID
- AX_OFF
- AX_PAUSE_WATERLVL_HIGH
- AX_PAUSE_WATERLVL_LOW
- AX_PHYPWR_RSTCTL
- AX_PHYPWR_RSTCTL_AT
- AX_PHYPWR_RSTCTL_BZ
- AX_PHYPWR_RSTCTL_IPRL
- AX_PHYSEL_PSEL
- AX_PHYSEL_SSEN
- AX_PHYSEL_SSMII
- AX_PHY_SELECT_EXTERNAL
- AX_PHY_SELECT_INTERNAL
- AX_PHY_SELECT_MASK
- AX_QCTCTRL
- AX_RXCOE_CTL
- AX_RXCOE_IP
- AX_RXCOE_TCP
- AX_RXCOE_TCPV6
- AX_RXCOE_UDP
- AX_RXCOE_UDPV6
- AX_RXHDR_CRC_ERR
- AX_RXHDR_DROP_ERR
- AX_RXHDR_L3CSUM_ERR
- AX_RXHDR_L4CSUM_ERR
- AX_RXHDR_L4_TYPE_MASK
- AX_RXHDR_L4_TYPE_TCP
- AX_RXHDR_L4_TYPE_UDP
- AX_RX_BULKIN_QCTRL
- AX_RX_CTL
- AX_RX_CTL_AB
- AX_RX_CTL_AM
- AX_RX_CTL_AMALL
- AX_RX_CTL_AP
- AX_RX_CTL_DROPCRCERR
- AX_RX_CTL_IPE
- AX_RX_CTL_MFB_16384
- AX_RX_CTL_MFB_2048
- AX_RX_CTL_MFB_4096
- AX_RX_CTL_MFB_8192
- AX_RX_CTL_PRO
- AX_RX_CTL_SEP
- AX_RX_CTL_SO
- AX_RX_CTL_START
- AX_RX_CTL_STOP
- AX_SECLD
- AX_SIZE
- AX_SPR_ACK
- AX_SPR_BUSY
- AX_SPR_ERR
- AX_SPR_PE
- AX_SPR_SLCT
- AX_SROM_ADDR
- AX_SROM_CMD
- AX_SROM_DATA_HIGH
- AX_SROM_DATA_LOW
- AX_SWRESET_BZ
- AX_SWRESET_CLEAR
- AX_SWRESET_IPPD
- AX_SWRESET_IPRL
- AX_SWRESET_PRL
- AX_SWRESET_PRTE
- AX_SWRESET_RR
- AX_SWRESET_RT
- AX_TXCOE_CTL
- AX_TXCOE_IP
- AX_TXCOE_TCP
- AX_TXCOE_TCPV6
- AX_TXCOE_UDP
- AX_TXCOE_UDPV6
- AX_USB_HS
- AX_USB_SS
- AX_USER_DOMAIN_MASK
- AX_USER_DOMAIN_SHIFT
- AYCrCb16161616_10LSB
- AYCrCb16161616_10MSB
- AYCrCb16161616_12LSB
- AYCrCb16161616_12MSB
- AYCrCb8888
- AYRAM_AYRAM_CHANNEL_COUNT
- AYRAM_AYRAM_CHAN_INCR
- AYRAM_AYRAM_INST_OFFSET
- AYRAM_AYRAM_MODULE_OFFSET
- AYRAM_CHIP_OFFSET
- AYUV8_1X32
- AY_END
- AY_OFF
- AY_SIZE
- AZ6007_FIRMWARE
- AZ6007_I2C_RD
- AZ6007_I2C_WR
- AZ6007_POWER
- AZ6007_READ_DATA
- AZ6007_READ_IR
- AZ6007_TS_THROUGH
- AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK
- AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT
- AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK
- AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT
- AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK
- AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT
- AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK
- AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT
- AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK
- AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT
- AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK
- AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT
- AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK
- AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT
- AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK
- AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT
- AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK
- AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT
- AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK
- AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT
- AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK
- AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT
- AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK
- AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT
- AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK
- AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT
- AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK
- AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT
- AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK
- AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT
- AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK
- AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT
- AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK
- AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT
- AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK
- AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT
- AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK
- AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT
- AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK
- AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT
- AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK
- AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT
- AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK
- AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT
- AZALIA_CRC0_CONTROL0__CRC_EN_MASK
- AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT
- AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK
- AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT
- AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK
- AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT
- AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK
- AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT
- AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK
- AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT
- AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK
- AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT
- AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK
- AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT
- AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK
- AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT
- AZALIA_CRC0_RESULT__CRC_RESULT_MASK
- AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT
- AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK
- AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT
- AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK
- AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT
- AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK
- AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT
- AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK
- AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT
- AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK
- AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT
- AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK
- AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT
- AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK
- AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT
- AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK
- AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT
- AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK
- AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT
- AZALIA_CRC1_CONTROL0__CRC_EN_MASK
- AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT
- AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK
- AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT
- AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK
- AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT
- AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK
- AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT
- AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK
- AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT
- AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK
- AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT
- AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK
- AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT
- AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK
- AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT
- AZALIA_CRC1_RESULT__CRC_RESULT_MASK
- AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT
- AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK
- AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT
- AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK
- AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT
- AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK
- AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT
- AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK
- AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT
- AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK
- AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT
- AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK
- AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT
- AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK
- AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK
- AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT
- AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK
- AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT
- AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT
- AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK
- AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT
- AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK
- AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT
- AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK
- AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK
- AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK
- AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT
- AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK
- AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT
- AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK
- AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT
- AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK
- AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK
- AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK
- AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK
- AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK
- AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK
- AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK
- AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT
- AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK
- AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK
- AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK
- AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT
- AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK
- AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT
- AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK
- AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT
- AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK
- AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK
- AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK
- AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK
- AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK
- AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK
- AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK
- AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK
- AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK
- AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT
- AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK
- AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK
- AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT
- AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK
- AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT
- AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK
- AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK
- AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT
- AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK
- AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK
- AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK
- AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK
- AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK
- AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK
- AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK
- AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK
- AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT
- AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK
- AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK
- AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT
- AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK
- AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT
- AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK
- AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK
- AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT
- AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK
- AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT
- AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK
- AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT
- AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK
- AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT
- AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK
- AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT
- AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK
- AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT
- AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK
- AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT
- AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK
- AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK
- AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT
- AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK
- AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT
- AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK
- AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT
- AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK
- AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT
- AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK
- AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT
- AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK
- AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT
- AZALIA_SOFT_RESET_REFCLK_SOFT_RESET
- AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET
- AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC
- AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK
- AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT
- AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK
- AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT
- AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK
- AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT
- AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK
- AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK
- AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT
- AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK
- AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK
- AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT
- AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT
- AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK
- AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT
- AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK
- AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT
- AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK
- AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT
- AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK
- AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK
- AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK
- AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT
- AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK
- AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK
- AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT
- AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK
- AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT
- AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK
- AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT
- AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK
- AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT
- AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK
- AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT
- AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK
- AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT
- AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK
- AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT
- AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK
- AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT
- AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK
- AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT
- AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK
- AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK
- AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK
- AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT
- AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK
- AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT
- AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK
- AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT
- AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK
- AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT
- AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK
- AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT
- AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK
- AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT
- AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK
- AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT
- AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK
- AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT
- AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK
- AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK
- AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT
- AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK
- AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT
- AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK
- AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT
- AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK
- AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT
- AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK
- AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT
- AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK
- AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT
- AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK
- AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK
- AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT
- AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT
- AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK
- AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK
- AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT
- AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK
- AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT
- AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK
- AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT
- AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK
- AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT
- AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK
- AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK
- AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT
- AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK
- AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT
- AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK
- AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK
- AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT
- AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK
- AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT
- AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK
- AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT
- AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK
- AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT
- AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK
- AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT
- AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK
- AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT
- AZF3328_MIXER_ENUM
- AZF3328_MIXER_SWITCH
- AZF3328_MIXER_VOL_MONO
- AZF3328_MIXER_VOL_SPECIAL
- AZF3328_MIXER_VOL_STEREO
- AZF_AC97_REG_EMU_IO_READ
- AZF_AC97_REG_EMU_IO_RW
- AZF_AC97_REG_EMU_IO_WRITE
- AZF_AC97_REG_REAL_IO_READ
- AZF_AC97_REG_REAL_IO_RW
- AZF_AC97_REG_REAL_IO_WRITE
- AZF_AC97_REG_UNSUPPORTED
- AZF_ALIGN
- AZF_CODEC_CAPTURE
- AZF_CODEC_I2S_OUT
- AZF_CODEC_PLAYBACK
- AZF_FREQ
- AZF_FREQ_
- AZF_GAME_LEGACY_IO_PORT
- AZF_IO_OFFS_CODEC_CAPTURE
- AZF_IO_OFFS_CODEC_I2S_OUT
- AZF_IO_OFFS_CODEC_PLAYBACK
- AZF_IO_SIZE_CTRL
- AZF_IO_SIZE_CTRL_PM
- AZF_IO_SIZE_GAME
- AZF_IO_SIZE_GAME_PM
- AZF_IO_SIZE_MIXER
- AZF_IO_SIZE_MIXER_PM
- AZF_IO_SIZE_MPU
- AZF_IO_SIZE_MPU_PM
- AZF_IO_SIZE_OPL3
- AZF_IO_SIZE_OPL3_PM
- AZF_MUTE_BIT
- AZF_PCMDEV_I2S_OUT
- AZF_PCMDEV_STD
- AZF_REG_MASK
- AZF_USE_AC97_LAYER
- AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- AZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- AZT1605
- AZT2316
- AZTECH_BIT_MONO
- AZTECH_BIT_NOT_TUNED
- AZTECH_BIT_TUN_CE
- AZTECH_BIT_TUN_CLK
- AZTECH_BIT_TUN_DATA
- AZTECH_CDROM_MAJOR
- AZTECH_MAX
- AZX_CAP_HDR_ID_MASK
- AZX_CAP_HDR_ID_OFF
- AZX_CAP_HDR_NXT_PTR_MASK
- AZX_CAP_HDR_VER_MASK
- AZX_CAP_HDR_VER_OFF
- AZX_CGCTL_ADSPDCGE
- AZX_CGCTL_MISCBDCGE_MASK
- AZX_CORBCTL_CMEIE
- AZX_CORBCTL_RUN
- AZX_CORBRP_RST
- AZX_CORBSTS_CMEI
- AZX_DCAPS_4K_BDLE_BOUNDARY
- AZX_DCAPS_AMD_WORKAROUND
- AZX_DCAPS_CORBRP_SELF_CLEAR
- AZX_DCAPS_COUNT_LPIB_DELAY
- AZX_DCAPS_CTX_WORKAROUND
- AZX_DCAPS_I915_COMPONENT
- AZX_DCAPS_INTEL_BAYTRAIL
- AZX_DCAPS_INTEL_BRASWELL
- AZX_DCAPS_INTEL_BROADWELL
- AZX_DCAPS_INTEL_BROXTON
- AZX_DCAPS_INTEL_HASWELL
- AZX_DCAPS_INTEL_ICH
- AZX_DCAPS_INTEL_PCH
- AZX_DCAPS_INTEL_PCH_BASE
- AZX_DCAPS_INTEL_PCH_NOPM
- AZX_DCAPS_INTEL_SKYLAKE
- AZX_DCAPS_NO_64BIT
- AZX_DCAPS_NO_ALIGN_BUFSIZE
- AZX_DCAPS_NO_MSI
- AZX_DCAPS_NO_MSI64
- AZX_DCAPS_NO_TCSEL
- AZX_DCAPS_OLD_SSYNC
- AZX_DCAPS_PM_RUNTIME
- AZX_DCAPS_POSFIX_LPIB
- AZX_DCAPS_PRESET_AMD_SB
- AZX_DCAPS_PRESET_ATI_HDMI
- AZX_DCAPS_PRESET_ATI_HDMI_NS
- AZX_DCAPS_PRESET_ATI_SB
- AZX_DCAPS_PRESET_CTHDA
- AZX_DCAPS_PRESET_NVIDIA
- AZX_DCAPS_SEPARATE_STREAM_TAG
- AZX_DCAPS_SNOOP_MASK
- AZX_DCAPS_SNOOP_OFF
- AZX_DCAPS_SNOOP_TYPE
- AZX_DCAPS_SYNC_WRITE
- AZX_DEFAULT_CODECS
- AZX_DPLBASE_ENABLE
- AZX_DRIVER_ATI
- AZX_DRIVER_ATIHDMI
- AZX_DRIVER_ATIHDMI_NS
- AZX_DRIVER_CMEDIA
- AZX_DRIVER_CTHDA
- AZX_DRIVER_CTX
- AZX_DRIVER_GENERIC
- AZX_DRIVER_HDMI
- AZX_DRIVER_ICH
- AZX_DRIVER_NVIDIA
- AZX_DRIVER_PCH
- AZX_DRIVER_SCH
- AZX_DRIVER_SIS
- AZX_DRIVER_SKL
- AZX_DRIVER_TERA
- AZX_DRIVER_ULI
- AZX_DRIVER_VIA
- AZX_DRIVER_ZHAOXIN
- AZX_DRSM_BASE
- AZX_DRSM_CAP_ID
- AZX_DRSM_INTERVAL
- AZX_FORCE_CODEC_MASK
- AZX_GCAP_64OK
- AZX_GCAP_BSS
- AZX_GCAP_ISS
- AZX_GCAP_NSDO
- AZX_GCAP_OSS
- AZX_GCTL_FCNTRL
- AZX_GCTL_RESET
- AZX_GCTL_UNSOL
- AZX_GSTS_FSTS
- AZX_GTS_BASE
- AZX_GTS_CAP_ID
- AZX_GTS_INTERVAL
- AZX_INT_ALL_STREAM
- AZX_INT_CTRL_EN
- AZX_INT_GLOBAL_EN
- AZX_IRS_BUSY
- AZX_IRS_VALID
- AZX_MAX_BDL_ENTRIES
- AZX_MAX_BUF_SIZE
- AZX_MAX_CODECS
- AZX_MAX_CORB_ENTRIES
- AZX_MAX_FRAG
- AZX_MAX_RIRB_ENTRIES
- AZX_MLCTL_CPA
- AZX_MLCTL_CPA_SHIFT
- AZX_MLCTL_SPA
- AZX_MLCTL_SPA_SHIFT
- AZX_ML_BASE
- AZX_ML_CAP_ID
- AZX_ML_INTERVAL
- AZX_NUM_DRIVERS
- AZX_PCIREG_CGCTL
- AZX_PCIREG_PGCTL
- AZX_PCIREG_TCSEL
- AZX_PGCTL_ADSPPGD
- AZX_PGCTL_LSRMD_MASK
- AZX_PM_OPS
- AZX_PPCTL_GPROCEN
- AZX_PPCTL_PIE
- AZX_PPCTL_PROCEN
- AZX_PPHC_BASE
- AZX_PPHC_INTERVAL
- AZX_PPLCCTL_RUN
- AZX_PPLCCTL_STRM_BITS
- AZX_PPLCCTL_STRM_MASK
- AZX_PPLCCTL_STRM_SHIFT
- AZX_PPLCCTL_STRST
- AZX_PPLC_BASE
- AZX_PPLC_INTERVAL
- AZX_PPLC_MULTI
- AZX_PP_CAP_ID
- AZX_RBCTL_DMA_EN
- AZX_RBCTL_IRQ_EN
- AZX_RBCTL_OVERRUN_EN
- AZX_RBSTS_IRQ
- AZX_RBSTS_OVERRUN
- AZX_REG_CAP_HDR
- AZX_REG_CORBCTL
- AZX_REG_CORBLBASE
- AZX_REG_CORBRP
- AZX_REG_CORBSIZE
- AZX_REG_CORBSTS
- AZX_REG_CORBUBASE
- AZX_REG_CORBWP
- AZX_REG_DPLBASE
- AZX_REG_DPUBASE
- AZX_REG_DRSM_CTL
- AZX_REG_GCAP
- AZX_REG_GCAP2
- AZX_REG_GCTL
- AZX_REG_GSTS
- AZX_REG_GTSCC
- AZX_REG_GTS_BASE
- AZX_REG_GTS_GTSCD
- AZX_REG_GTS_GTSCH
- AZX_REG_GTS_GTSCTLAC
- AZX_REG_HSW_EM4
- AZX_REG_HSW_EM5
- AZX_REG_IC
- AZX_REG_INPAY
- AZX_REG_INSTRMPAY
- AZX_REG_INTCTL
- AZX_REG_INTSTS
- AZX_REG_IR
- AZX_REG_IRS
- AZX_REG_LLCH
- AZX_REG_LLPCL
- AZX_REG_LLPCU
- AZX_REG_LLPFOC
- AZX_REG_MASK
- AZX_REG_ML_LCAP
- AZX_REG_ML_LCTL
- AZX_REG_ML_LINPAY
- AZX_REG_ML_LOSIDV
- AZX_REG_ML_LOUTPAY
- AZX_REG_ML_LPSIO
- AZX_REG_ML_LPSOO
- AZX_REG_ML_LSDIID
- AZX_REG_ML_LWALFC
- AZX_REG_ML_MLCD
- AZX_REG_ML_MLCH
- AZX_REG_OLD_SSYNC
- AZX_REG_OUTPAY
- AZX_REG_OUTSTRMPAY
- AZX_REG_PPHCLDPL
- AZX_REG_PPHCLDPU
- AZX_REG_PPHCLLPL
- AZX_REG_PPHCLLPU
- AZX_REG_PPLCCTL
- AZX_REG_PPLCFMT
- AZX_REG_PPLCLLPL
- AZX_REG_PPLCLLPU
- AZX_REG_PP_PPCH
- AZX_REG_PP_PPCTL
- AZX_REG_PP_PPSTS
- AZX_REG_RINTCNT
- AZX_REG_RIRBCTL
- AZX_REG_RIRBLBASE
- AZX_REG_RIRBSIZE
- AZX_REG_RIRBSTS
- AZX_REG_RIRBUBASE
- AZX_REG_RIRBWP
- AZX_REG_SD_BDLPL
- AZX_REG_SD_BDLPU
- AZX_REG_SD_CBL
- AZX_REG_SD_CTL
- AZX_REG_SD_CTL_3B
- AZX_REG_SD_FIFOL
- AZX_REG_SD_FIFOSIZE
- AZX_REG_SD_FIFOW
- AZX_REG_SD_FORMAT
- AZX_REG_SD_LPIB
- AZX_REG_SD_LVI
- AZX_REG_SD_STS
- AZX_REG_SPB_BASE_ADDR
- AZX_REG_SPB_SPBFCCTL
- AZX_REG_SPB_SPBFCH
- AZX_REG_SSYNC
- AZX_REG_STATESTS
- AZX_REG_TSCCL
- AZX_REG_TSCCU
- AZX_REG_VMAJ
- AZX_REG_VMIN
- AZX_REG_VS_D0I3C
- AZX_REG_VS_D0I3C_CIP
- AZX_REG_VS_D0I3C_I3
- AZX_REG_VS_EM1
- AZX_REG_VS_EM2
- AZX_REG_VS_EM2_L1SEN
- AZX_REG_VS_EM3L
- AZX_REG_VS_EM3U
- AZX_REG_VS_EM4L
- AZX_REG_VS_EM4U
- AZX_REG_VS_FIFOTRK
- AZX_REG_VS_FIFOTRK2
- AZX_REG_VS_INRC
- AZX_REG_VS_L2LAHPT
- AZX_REG_VS_L2MAGC
- AZX_REG_VS_LTRC
- AZX_REG_VS_OUTRC
- AZX_REG_VS_PCE
- AZX_REG_VS_SDXDPIB_XBASE
- AZX_REG_VS_SDXDPIB_XINTERVAL
- AZX_REG_VS_SDXEFIFOS_XBASE
- AZX_REG_VS_SDXEFIFOS_XINTERVAL
- AZX_REG_WAKEEN
- AZX_REG_WALFCC
- AZX_REG_WALLCLK
- AZX_RIRBWP_RST
- AZX_RIRB_EX_UNSOL_EV
- AZX_SNOOP_TYPE_ATI
- AZX_SNOOP_TYPE_NONE
- AZX_SNOOP_TYPE_NVIDIA
- AZX_SNOOP_TYPE_SCH
- AZX_SPB_BASE
- AZX_SPB_CAP_ID
- AZX_SPB_INTERVAL
- AZX_SPB_MAXFIFO
- AZX_SPB_SPIB
- AZX_VS_EM2_DUM
- AZ_ANADECT_10BTRX_TH
- AZ_ANADECT_BOTH_01CHNL
- AZ_ANADECT_CHNL_MASK
- AZ_ANADECT_CHNL_SHIFT
- AZ_ANADECT_DEF
- AZ_ANADECT_INTV_MASK
- AZ_ANADECT_INTV_SHIFT
- AZ_ANADECT_LONG
- AZ_ANADECT_THRESH_MASK
- AZ_ANADECT_THRESH_SHIFT
- AZ_CHANNEL_COUNT_CONTROL
- AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK
- AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT
- AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK
- AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT
- AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK
- AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT
- AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK
- AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT
- AZ_CORB_SIZE
- AZ_CORB_SIZE_16ENTRIES_RESERVED
- AZ_CORB_SIZE_256ENTRIES
- AZ_CORB_SIZE_2ENTRIES_RESERVED
- AZ_CORB_SIZE_RESERVED
- AZ_ENDPOINT_REG_INDEX
- AZ_ENDPOINT_REG_WRITE_EN
- AZ_F0_CODEC_ENDPOINT_DATA
- AZ_F0_CODEC_ENDPOINT_INDEX
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8
- AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9
- AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
- AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0
- AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1
- AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER
- AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR
- AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
- AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
- AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
- AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
- AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
- AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
- AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7
- AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8
- AZ_FORCE_CODEC_WAKE
- AZ_GLOBAL_CAPABILITIES
- AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED
- AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED
- AZ_HOT_PLUG_CONTROL
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
- AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
- AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
- AZ_LATENCY_COUNTER_CONTROL
- AZ_LATENCY_COUNTER_NO_RESET
- AZ_LATENCY_COUNTER_RESET_DONE
- AZ_REG_READ
- AZ_REG_WRITE
- AZ_RIRB_SIZE
- AZ_RIRB_SIZE_16ENTRIES_RESERVED
- AZ_RIRB_SIZE_256ENTRIES
- AZ_RIRB_SIZE_2ENTRIES_RESERVED
- AZ_RIRB_SIZE_UNDEFINED
- AZ_RIRB_WRITE_POINTER_DO_RESET
- AZ_RIRB_WRITE_POINTER_NOT_RESET
- AZ_RIRB_WRITE_POINTER_RESET
- AZ_STATE_CHANGE_STATUS
- AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT
- AZ_STATE_CHANGE_STATUS_CODEC_PRESENT
- AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK
- AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT
- AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK
- AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT
- AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK
- AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT
- AZ__MEM_PG
- AZ__MEM_PG__1
- A_
- A_12
- A_24
- A_28
- A_8
- A_A
- A_ADCCR_LCHANENABLE
- A_ADCCR_RCHANENABLE
- A_ADCCR_SAMPLERATE_11
- A_ADCCR_SAMPLERATE_12
- A_ADCCR_SAMPLERATE_8
- A_ADCCR_SAMPLERATE_MASK
- A_ADCIDX
- A_ADCIDX_IDX
- A_ADDR_TRAP_CFG
- A_ADDR_TRAP_CFG_0
- A_ADDR_TRAP_CFG_1
- A_ADDR_TRAP_CFG_2
- A_ADDR_TRAP_CFG_3
- A_ADDR_TRAP_DOWN
- A_ADDR_TRAP_DOWN_0
- A_ADDR_TRAP_DOWN_1
- A_ADDR_TRAP_DOWN_2
- A_ADDR_TRAP_DOWN_3
- A_ADDR_TRAP_INDEX
- A_ADDR_TRAP_REG
- A_ADDR_TRAP_REG_DEBUG
- A_ADDR_TRAP_UP
- A_ADDR_TRAP_UP_0
- A_ADDR_TRAP_UP_1
- A_ADDR_TRAP_UP_2
- A_ADDR_TRAP_UP_3
- A_ADD_VOLUME_IN
- A_AIDL_BDIS
- A_ASM
- A_B
- A_BAND_24GHZ
- A_BAND_5GHZ
- A_BCM1480_BUS_ERR_STATUS_DEBUG
- A_BCM1480_DUART
- A_BCM1480_DUART0
- A_BCM1480_DUART1
- A_BCM1480_DUART_AUX_CTRL_C
- A_BCM1480_DUART_AUX_CTRL_CD
- A_BCM1480_DUART_AUX_CTRL_D
- A_BCM1480_DUART_CHANREG
- A_BCM1480_DUART_CLEAR_OPR_CD
- A_BCM1480_DUART_CLK_SEL_C
- A_BCM1480_DUART_CLK_SEL_D
- A_BCM1480_DUART_CMD_C
- A_BCM1480_DUART_CMD_D
- A_BCM1480_DUART_CTRLREG
- A_BCM1480_DUART_FULL_CTL_C
- A_BCM1480_DUART_FULL_CTL_D
- A_BCM1480_DUART_IMRREG
- A_BCM1480_DUART_IMR_C
- A_BCM1480_DUART_IMR_CD
- A_BCM1480_DUART_IMR_D
- A_BCM1480_DUART_INPORT_CHNG_C
- A_BCM1480_DUART_INPORT_CHNG_CD
- A_BCM1480_DUART_INPORT_CHNG_D
- A_BCM1480_DUART_IN_PORT
- A_BCM1480_DUART_IN_PORT_CD
- A_BCM1480_DUART_ISRREG
- A_BCM1480_DUART_ISR_C
- A_BCM1480_DUART_ISR_CD
- A_BCM1480_DUART_ISR_D
- A_BCM1480_DUART_MODE_REG_1_C
- A_BCM1480_DUART_MODE_REG_1_D
- A_BCM1480_DUART_MODE_REG_2_C
- A_BCM1480_DUART_MODE_REG_2_D
- A_BCM1480_DUART_OPCR_C
- A_BCM1480_DUART_OPCR_CD
- A_BCM1480_DUART_OPCR_D
- A_BCM1480_DUART_OUT_PORT_CD
- A_BCM1480_DUART_RX_HOLD_C
- A_BCM1480_DUART_RX_HOLD_D
- A_BCM1480_DUART_SET_OPR_CD
- A_BCM1480_DUART_STATUS_C
- A_BCM1480_DUART_STATUS_D
- A_BCM1480_DUART_TX_HOLD_C
- A_BCM1480_DUART_TX_HOLD_D
- A_BCM1480_GPIO_INT_ADD_TYPE
- A_BCM1480_HR_BASE
- A_BCM1480_HR_BASE_0
- A_BCM1480_HR_BASE_1
- A_BCM1480_HR_BASE_2
- A_BCM1480_HR_REGISTER
- A_BCM1480_HSP_BASE
- A_BCM1480_HSP_BASE_0
- A_BCM1480_HSP_BASE_1
- A_BCM1480_HSP_BASE_2
- A_BCM1480_HSP_REGISTER
- A_BCM1480_HT_PORT0_HEADER
- A_BCM1480_HT_PORT1_HEADER
- A_BCM1480_HT_PORT2_HEADER
- A_BCM1480_HT_PORT_HEADER
- A_BCM1480_HT_TYPE00_HEADER
- A_BCM1480_IMR_ALIAS_MAILBOX
- A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE
- A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE
- A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE
- A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE
- A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER
- A_BCM1480_IMR_CPU0_BASE
- A_BCM1480_IMR_CPU1_BASE
- A_BCM1480_IMR_CPU2_BASE
- A_BCM1480_IMR_CPU3_BASE
- A_BCM1480_IMR_MAPPER
- A_BCM1480_IMR_REGISTER
- A_BCM1480_IO_PCMCIA_CFG_B
- A_BCM1480_IO_PCMCIA_STATUS_B
- A_BCM1480_L2C_MGMT_TAG_BASE
- A_BCM1480_L2_BANK_ADDRESS
- A_BCM1480_L2_BANK_BASE
- A_BCM1480_L2_BASE
- A_BCM1480_L2_CACHE_DISABLE
- A_BCM1480_L2_ECC_TAG
- A_BCM1480_L2_MAKECACHEDISABLE
- A_BCM1480_L2_MAKE_WAY_DISABLE_HI
- A_BCM1480_L2_MAKE_WAY_DISABLE_LO
- A_BCM1480_L2_MAKE_WAY_ENABLE_HI
- A_BCM1480_L2_MAKE_WAY_ENABLE_LO
- A_BCM1480_L2_MGMT_TAG_BASE
- A_BCM1480_L2_MISC0_VALUE
- A_BCM1480_L2_MISC1_VALUE
- A_BCM1480_L2_MISC2_VALUE
- A_BCM1480_L2_MISC_CONFIG
- A_BCM1480_L2_READ_TAG
- A_BCM1480_L2_WAY_AGENT_3_0
- A_BCM1480_L2_WAY_AGENT_7_4
- A_BCM1480_L2_WAY_ENABLE
- A_BCM1480_L2_WAY_ENABLE_3_0
- A_BCM1480_L2_WAY_ENABLE_7_4
- A_BCM1480_L2_WAY_LOCAL_3_0
- A_BCM1480_L2_WAY_LOCAL_7_4
- A_BCM1480_L2_WAY_REMOTE_3_0
- A_BCM1480_L2_WAY_REMOTE_7_4
- A_BCM1480_MAC_BASE_2
- A_BCM1480_MAC_BASE_3
- A_BCM1480_MAILBOX_REGISTER
- A_BCM1480_MC_BASE
- A_BCM1480_MC_BASE_0
- A_BCM1480_MC_BASE_1
- A_BCM1480_MC_BASE_2
- A_BCM1480_MC_BASE_3
- A_BCM1480_MC_GLB_CONFIG
- A_BCM1480_MC_GLB_ECC_ADDR
- A_BCM1480_MC_GLB_ECC_CORRECT
- A_BCM1480_MC_GLB_ECC_STATUS
- A_BCM1480_MC_GLB_INTLV
- A_BCM1480_MC_GLB_PERF_CNT_CONTROL
- A_BCM1480_MC_REGISTER
- A_BCM1480_NC_BASE
- A_BCM1480_NC_CREDIT_STATUS_REG0
- A_BCM1480_NC_CREDIT_STATUS_REG1
- A_BCM1480_NC_CREDIT_STATUS_REG10
- A_BCM1480_NC_CREDIT_STATUS_REG11
- A_BCM1480_NC_CREDIT_STATUS_REG12
- A_BCM1480_NC_CREDIT_STATUS_REG2
- A_BCM1480_NC_CREDIT_STATUS_REG3
- A_BCM1480_NC_CREDIT_STATUS_REG4
- A_BCM1480_NC_CREDIT_STATUS_REG5
- A_BCM1480_NC_CREDIT_STATUS_REG6
- A_BCM1480_NC_CREDIT_STATUS_REG7
- A_BCM1480_NC_CREDIT_STATUS_REG8
- A_BCM1480_NC_CREDIT_STATUS_REG9
- A_BCM1480_NC_INTERRUPT_ENABLE
- A_BCM1480_NC_INTERRUPT_STATUS
- A_BCM1480_NC_RLD_BAD_ERROR
- A_BCM1480_NC_RLD_COR_ERROR
- A_BCM1480_NC_RLD_ECC_STATUS
- A_BCM1480_NC_RLD_FIELD
- A_BCM1480_NC_RLD_RANDOM_LFSR
- A_BCM1480_NC_RLD_TRIGGER
- A_BCM1480_NC_RLD_WAY_ENABLE
- A_BCM1480_NC_SR_TIMEOUT_COUNTER
- A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL
- A_BCM1480_NC_TIMEOUT_COUNTER
- A_BCM1480_NC_TIMEOUT_COUNTER_SEL
- A_BCM1480_PCI_BASE
- A_BCM1480_PCI_DLL
- A_BCM1480_PCI_RESET
- A_BCM1480_PCI_TYPE00_HEADER
- A_BCM1480_PHYS_GENBUS
- A_BCM1480_PHYS_GENBUS_END
- A_BCM1480_PHYS_HS_SUBSYS
- A_BCM1480_PHYS_HT_CFG_MATCH_BITS
- A_BCM1480_PHYS_HT_CFG_MATCH_BYTES
- A_BCM1480_PHYS_HT_FULLACCESS
- A_BCM1480_PHYS_HT_IO_MATCH_BITS
- A_BCM1480_PHYS_HT_IO_MATCH_BYTES
- A_BCM1480_PHYS_HT_MEM_MATCH_BITS
- A_BCM1480_PHYS_HT_MEM_MATCH_BYTES
- A_BCM1480_PHYS_HT_NODE_ALIAS
- A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS
- A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES
- A_BCM1480_PHYS_HT_UPPER_MATCH_BITS
- A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES
- A_BCM1480_PHYS_IO_SYSTEM
- A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE
- A_BCM1480_PHYS_L2CACHE_WAY0
- A_BCM1480_PHYS_L2CACHE_WAY1
- A_BCM1480_PHYS_L2CACHE_WAY2
- A_BCM1480_PHYS_L2CACHE_WAY3
- A_BCM1480_PHYS_L2CACHE_WAY4
- A_BCM1480_PHYS_L2CACHE_WAY5
- A_BCM1480_PHYS_L2CACHE_WAY6
- A_BCM1480_PHYS_L2CACHE_WAY7
- A_BCM1480_PHYS_L2CACHE_WAY_SIZE
- A_BCM1480_PHYS_L2_CACHE_TEST
- A_BCM1480_PHYS_MEMORY_0
- A_BCM1480_PHYS_MEMORY_1
- A_BCM1480_PHYS_MEMORY_2
- A_BCM1480_PHYS_MEMORY_3
- A_BCM1480_PHYS_MEMORY_EXP
- A_BCM1480_PHYS_MEMORY_EXP_SIZE
- A_BCM1480_PHYS_MEMORY_SIZE
- A_BCM1480_PHYS_PCI_CFG_MATCH_BITS
- A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES
- A_BCM1480_PHYS_PCI_IACK_MATCH_BITS
- A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES
- A_BCM1480_PHYS_PCI_IO_MATCH_BITS
- A_BCM1480_PHYS_PCI_IO_MATCH_BYTES
- A_BCM1480_PHYS_PCI_MEM_MATCH_BITS
- A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES
- A_BCM1480_PHYS_PCI_MISC_MATCH_BITS
- A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES
- A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS
- A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES
- A_BCM1480_PHYS_PCI_UPPER
- A_BCM1480_PHYS_SYSTEM_CTL
- A_BCM1480_PMI_GLB_0
- A_BCM1480_PMI_INT
- A_BCM1480_PMI_INT_0
- A_BCM1480_PMI_INT_OFFSET_0
- A_BCM1480_PMI_LCL_0
- A_BCM1480_PMI_LCL_BASE
- A_BCM1480_PMI_LCL_REGISTER
- A_BCM1480_PMI_OFFSET_0
- A_BCM1480_PMO_GLB_0
- A_BCM1480_PMO_INT
- A_BCM1480_PMO_INT_0
- A_BCM1480_PMO_INT_OFFSET_0
- A_BCM1480_PMO_LCL_0
- A_BCM1480_PMO_LCL_BASE
- A_BCM1480_PMO_LCL_REGISTER
- A_BCM1480_PMO_OFFSET_0
- A_BCM1480_PM_BASE
- A_BCM1480_PM_GLOBALDEBUGMODE_PMI
- A_BCM1480_PM_GLOBALDEBUGMODE_PMO
- A_BCM1480_PM_GLOBALDEBUG_PIB
- A_BCM1480_PM_GLOBALDEBUG_PID
- A_BCM1480_PM_GLOBALDEBUG_POB
- A_BCM1480_PM_GLOBALDEBUG_POD
- A_BCM1480_PM_PMO_MAPPING
- A_BCM1480_SCD_PERF_CNT
- A_BCM1480_SCD_PERF_CNT_0
- A_BCM1480_SCD_PERF_CNT_1
- A_BCM1480_SCD_PERF_CNT_2
- A_BCM1480_SCD_PERF_CNT_3
- A_BCM1480_SCD_PERF_CNT_4
- A_BCM1480_SCD_PERF_CNT_5
- A_BCM1480_SCD_PERF_CNT_6
- A_BCM1480_SCD_PERF_CNT_7
- A_BCM1480_SCD_PERF_CNT_BASE
- A_BCM1480_SCD_PERF_CNT_CFG0
- A_BCM1480_SCD_PERF_CNT_CFG1
- A_BCM1480_SCD_PERF_CNT_CFG_0
- A_BCM1480_SCD_PERF_CNT_CFG_1
- A_BCM1480_SCD_SCRATCH
- A_BCM1480_SCD_WDOG_2
- A_BCM1480_SCD_WDOG_3
- A_BCM1480_SCD_WDOG_BASE
- A_BCM1480_SCD_WDOG_CFG_2
- A_BCM1480_SCD_WDOG_CFG_3
- A_BCM1480_SCD_WDOG_CNT_2
- A_BCM1480_SCD_WDOG_CNT_3
- A_BCM1480_SCD_WDOG_INIT_2
- A_BCM1480_SCD_WDOG_INIT_3
- A_BCM1480_SCD_WDOG_REGISTER
- A_BCM1480_SCD_ZBBUS_CYCLE_COUNT
- A_BCM1480_SCD_ZBBUS_CYCLE_CP0
- A_BCM1480_SCD_ZBBUS_CYCLE_CP1
- A_BCM1480_SCD_ZBBUS_CYCLE_CP2
- A_BCM1480_SCD_ZBBUS_CYCLE_CP3
- A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE
- A_BCM1480_SWDEBUG_SCHEDSTOP
- A_BCM1480_SWPERF_CFG
- A_BCM1480_SWPERF_CNT0
- A_BCM1480_SWPERF_CNT1
- A_BCM1480_SWPERF_CNT2
- A_BCM1480_SWPERF_CNT3
- A_BCM1480_SWTRC_CFG
- A_BCM1480_SWTRC_EVENT
- A_BCM1480_SWTRC_EVENT_0
- A_BCM1480_SWTRC_MATCH_CONTROL
- A_BCM1480_SWTRC_MATCH_CONTROL_0
- A_BCM1480_SWTRC_MATCH_DATA_MASK
- A_BCM1480_SWTRC_MATCH_DATA_MASK_0
- A_BCM1480_SWTRC_MATCH_DATA_VALUE
- A_BCM1480_SWTRC_MATCH_DATA_VALUE_0
- A_BCM1480_SWTRC_MATCH_TAG_MAKS_0
- A_BCM1480_SWTRC_MATCH_TAG_MASK
- A_BCM1480_SWTRC_MATCH_TAG_VALUE
- A_BCM1480_SWTRC_MATCH_TAG_VALUE_0
- A_BCM1480_SWTRC_READ
- A_BCM1480_SWTRC_SEQUENCE
- A_BCM1480_SWTRC_SEQUENCE_0
- A_BDISP12
- A_BDISP8
- A_BIDL_ADIS
- A_BUS_ERR_DATA_0
- A_BUS_ERR_DATA_1
- A_BUS_ERR_DATA_2
- A_BUS_ERR_DATA_3
- A_BUS_ERR_STATUS_DEBUG
- A_BUS_L2_ERRORS
- A_BUS_MEM_IO_ERRORS
- A_C
- A_CAP
- A_CHANNEL
- A_CH_MSK
- A_CIM_BOOT_CFG
- A_CIM_HOST_ACC_CTRL
- A_CIM_HOST_ACC_DATA
- A_CIM_HOST_INT_CAUSE
- A_CIM_HOST_INT_ENABLE
- A_CIM_IBQ_DBG_CFG
- A_CIM_IBQ_DBG_DATA
- A_CIM_SDRAM_ADDR_SIZE
- A_CIM_SDRAM_BASE_ADDR
- A_CNF_10B_2
- A_CNF_10B_T
- A_CNF_AUI
- A_CNF_DC_DC_POLARITY
- A_CNF_EXTND_10B_2
- A_CNF_LOW_RX_SQUELCH
- A_CNF_MEDIA_10B_2
- A_CNF_MEDIA_10B_T
- A_CNF_MEDIA_AUI
- A_CNF_MEDIA_AUTO
- A_CNF_MEDIA_TYPE
- A_CNF_NO_AUTO_POLARITY
- A_CONF
- A_CON_HDLC
- A_CPL_INTR_CAUSE
- A_CPL_INTR_ENABLE
- A_CPL_MAP_TBL_DATA
- A_CPL_SWITCH_CNTRL
- A_CSBA
- A_CSDC
- A_CSFE
- A_CSHG
- A_CSPI_CALENDAR_LEN
- A_CSPI_FIFO_STATUS_ENABLE
- A_CSPI_INTR_ENABLE
- A_CSPI_INTR_STATUS
- A_CSPI_MAXBURST1_MAXBURST2
- A_CSPI_RX_AE_WM
- A_CSPI_RX_AF_WM
- A_CSPI_TRAIN
- A_CTL
- A_CUT_VERSION
- A_C_00000000
- A_C_00000001
- A_C_00000002
- A_C_00000003
- A_C_00000004
- A_C_00000008
- A_C_00000010
- A_C_00000020
- A_C_00000100
- A_C_00000800
- A_C_00010000
- A_C_00100000
- A_C_10000000
- A_C_20000000
- A_C_40000000
- A_C_4f1bbcdc
- A_C_5a7ef9db
- A_C_7fffffff
- A_C_80000000
- A_C_c0000000
- A_C_fffffffe
- A_C_ffffffff
- A_DBG
- A_DBG_SATURATION_ADDR
- A_DBG_SATURATION_OCCURED
- A_DBG_SINGLE_STEP
- A_DBG_STEP_ADDR
- A_DBG_ZC
- A_DBR
- A_DCDC_EN
- A_DEC_M
- A_DEC_N
- A_DEFAULT_MASK
- A_DEFAULT_MASK_SFT
- A_DEFAULT_SFT
- A_DELAY_PS
- A_DICE
- A_DIP4_ERROR_COUNT
- A_DISP_GBR
- A_DISP_PC
- A_DISP_REG_M
- A_DISP_REG_N
- A_DLY_M
- A_DLY_S
- A_DM_0
- A_DM_1
- A_DM_2
- A_DM_3
- A_DM_BASE
- A_DM_CRC_0
- A_DM_CRC_1
- A_DM_CRC_BASE
- A_DM_CRC_REGISTER
- A_DM_PARTIAL
- A_DM_PARTIAL_0
- A_DM_PARTIAL_1
- A_DM_PARTIAL_2
- A_DM_PARTIAL_3
- A_DM_REGISTER
- A_DUART
- A_DUART_AUX_CTRL
- A_DUART_CHANREG
- A_DUART_CLEAR_OPR
- A_DUART_CLK_SEL_A
- A_DUART_CLK_SEL_B
- A_DUART_CMD_A
- A_DUART_CMD_B
- A_DUART_CTRLREG
- A_DUART_FULL_CTL_A
- A_DUART_FULL_CTL_B
- A_DUART_IMR
- A_DUART_IMRREG
- A_DUART_IMR_A
- A_DUART_IMR_B
- A_DUART_INCHREG
- A_DUART_INPORT_CHNG
- A_DUART_INPORT_CHNG_A
- A_DUART_INPORT_CHNG_B
- A_DUART_INPORT_CHNG_DEBUG
- A_DUART_IN_PORT
- A_DUART_ISR
- A_DUART_ISRREG
- A_DUART_ISR_A
- A_DUART_ISR_B
- A_DUART_MODE_REG_1_A
- A_DUART_MODE_REG_1_B
- A_DUART_MODE_REG_2_A
- A_DUART_MODE_REG_2_B
- A_DUART_OPCR
- A_DUART_OPCR_A
- A_DUART_OPCR_B
- A_DUART_OUT_PORT
- A_DUART_RX_HOLD_A
- A_DUART_RX_HOLD_B
- A_DUART_SET_OPR
- A_DUART_STATUS_A
- A_DUART_STATUS_B
- A_DUART_TX_HOLD_A
- A_DUART_TX_HOLD_B
- A_ELMER0_GPI_CFG
- A_ELMER0_GPI_STAT
- A_ELMER0_GPO
- A_ELMER0_INT_CAUSE
- A_ELMER0_INT_ENABLE
- A_ELMER0_PHY_CFG
- A_ELMER0_PORT0_MI1_ADDR
- A_ELMER0_PORT0_MI1_CFG
- A_ELMER0_PORT0_MI1_DATA
- A_ELMER0_PORT0_MI1_OP
- A_ELMER0_PORT1_MI1_ADDR
- A_ELMER0_PORT1_MI1_CFG
- A_ELMER0_PORT1_MI1_DATA
- A_ELMER0_PORT1_MI1_OP
- A_ELMER0_PORT2_MI1_ADDR
- A_ELMER0_PORT2_MI1_CFG
- A_ELMER0_PORT2_MI1_DATA
- A_ELMER0_PORT2_MI1_OP
- A_ELMER0_PORT3_MI1_ADDR
- A_ELMER0_PORT3_MI1_CFG
- A_ELMER0_PORT3_MI1_DATA
- A_ELMER0_PORT3_MI1_OP
- A_ELMER0_VERSION
- A_EMU32OUTH
- A_EMU32OUTL
- A_END
- A_ESPI_CALENDAR_LENGTH
- A_ESPI_CMD_ADDR
- A_ESPI_DIP2_ERR_COUNT
- A_ESPI_FIFO_STATUS_ENABLE
- A_ESPI_GOSTAT
- A_ESPI_INTR_ENABLE
- A_ESPI_INTR_STATUS
- A_ESPI_MAXBURST1_MAXBURST2
- A_ESPI_MISC_CONTROL
- A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK
- A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK
- A_ESPI_RX_RESET
- A_ESPI_SCH_TOKEN0
- A_ESPI_SCH_TOKEN1
- A_ESPI_SCH_TOKEN2
- A_ESPI_SCH_TOKEN3
- A_ESPI_TRAIN
- A_ETRAM_ADDR
- A_ETRAM_CTL
- A_ETRAM_DATA
- A_EXTIN
- A_EXTIN_AC97_L
- A_EXTIN_AC97_R
- A_EXTIN_ADC_L
- A_EXTIN_ADC_R
- A_EXTIN_AUX2_L
- A_EXTIN_AUX2_R
- A_EXTIN_LINE2_L
- A_EXTIN_LINE2_R
- A_EXTIN_OPT_SPDIF_L
- A_EXTIN_OPT_SPDIF_R
- A_EXTIN_SPDIF_CD_L
- A_EXTIN_SPDIF_CD_R
- A_EXTOUT
- A_EXTOUT_AC97_L
- A_EXTOUT_AC97_R
- A_EXTOUT_ACENTER
- A_EXTOUT_ADC_CAP_L
- A_EXTOUT_ADC_CAP_R
- A_EXTOUT_AFRONT_L
- A_EXTOUT_AFRONT_R
- A_EXTOUT_ALFE
- A_EXTOUT_AREAR_L
- A_EXTOUT_AREAR_R
- A_EXTOUT_ASIDE_L
- A_EXTOUT_ASIDE_R
- A_EXTOUT_CENTER
- A_EXTOUT_FRONT_L
- A_EXTOUT_FRONT_R
- A_EXTOUT_HEADPHONE_L
- A_EXTOUT_HEADPHONE_R
- A_EXTOUT_LFE
- A_EXTOUT_MIC_CAP
- A_EXTOUT_REAR_L
- A_EXTOUT_REAR_R
- A_F1
- A_F12
- A_F2
- A_FIFO_DATA0
- A_FIFO_DATA0_NOINC
- A_FIFO_DATA1
- A_FIFO_DATA1_NOINC
- A_FIFO_DATA2
- A_FIFO_DATA2_NOINC
- A_FIFO_SEQ
- A_FXBUS
- A_FXBUS2
- A_FXGPREGBASE
- A_FXRT1
- A_FXRT2
- A_FXRT_CHANNELA
- A_FXRT_CHANNELB
- A_FXRT_CHANNELC
- A_FXRT_CHANNELD
- A_FXRT_CHANNELE
- A_FXRT_CHANNELF
- A_FXRT_CHANNELG
- A_FXRT_CHANNELH
- A_FXSENDAMOUNT_E_MASK
- A_FXSENDAMOUNT_F_MASK
- A_FXSENDAMOUNT_G_MASK
- A_FXSENDAMOUNT_H_MASK
- A_FXWC1
- A_FXWC2
- A_F_EDGE_STS
- A_GBR
- A_GMAC_BACKOFF_SEED
- A_GMAC_CSR
- A_GMAC_IFS
- A_GMAC_JUMBO_FRAME_LEN
- A_GMAC_LNK_DLY
- A_GMAC_MACID_HI
- A_GMAC_MACID_LO
- A_GMAC_MCAST_HI
- A_GMAC_MCAST_LO
- A_GMAC_MCAST_MASK_HI
- A_GMAC_MCAST_MASK_LO
- A_GMAC_PAUSETIME
- A_GMAC_RMT_CNT
- A_GMAC_RMT_DATA
- A_GMAC_TXF_THRES
- A_GPINPUT_MASK
- A_GPIO_BASE
- A_GPIO_CLR_EDGE
- A_GPIO_DIRECTION
- A_GPIO_GLITCH
- A_GPIO_INPUT_INVERT
- A_GPIO_INT_ADD_TYPE
- A_GPIO_INT_TYPE
- A_GPIO_PIN_CLR
- A_GPIO_PIN_SET
- A_GPIO_READ
- A_GPOUTPUT_MASK
- A_GPR
- A_GPR_ACCU
- A_GPR_COND
- A_GPR_DBAC
- A_GPR_DBACE
- A_GPR_IRQ
- A_GPR_NOISE0
- A_GPR_NOISE1
- A_H
- A_HIGH_CHANS
- A_HIWORD_OPA_MASK
- A_HIWORD_OPCODE_MASK
- A_HIWORD_RESULT_MASK
- A_HR
- A_HWM
- A_I2C_CFG
- A_I2S_CAPTURE_192000
- A_I2S_CAPTURE_44100
- A_I2S_CAPTURE_48000
- A_I2S_CAPTURE_96000
- A_I2S_CAPTURE_RATE_MASK
- A_IDX16
- A_IDX32
- A_IDX8
- A_IMM
- A_IMR_CPU0_BASE
- A_IMR_CPU1_BASE
- A_IMR_MAPPER
- A_IMR_REGISTER
- A_INC_M
- A_INC_N
- A_INDIC
- A_INDICATOR
- A_IND_M
- A_IND_N
- A_IND_R0_REG_M
- A_IND_R0_REG_N
- A_INI_MASK
- A_INI_MASK_SFT
- A_INI_SFT
- A_IOCFG
- A_IOCFG_DIGITAL_JACK
- A_IOCFG_DISABLE_AC97_FRONT
- A_IOCFG_DISABLE_ANALOG
- A_IOCFG_ENABLE_DIGITAL
- A_IOCFG_ENABLE_DIGITAL_AUDIGY4
- A_IOCFG_FRONT_JACK
- A_IOCFG_GPOUT0
- A_IOCFG_GPOUT1
- A_IOCFG_GPOUT2
- A_IOCFG_MULTIPURPOSE_JACK
- A_IOCFG_PHONES_JACK
- A_IOCFG_REAR_JACK
- A_IOCFG_UNKNOWN_20
- A_IO_DRIVE
- A_IO_DRIVE_0
- A_IO_DRIVE_1
- A_IO_DRIVE_2
- A_IO_DRIVE_3
- A_IO_DRIVE_BASE
- A_IO_EXT_BASE
- A_IO_EXT_CFG_BASE
- A_IO_EXT_CS_BASE
- A_IO_EXT_MULT_SIZE_BASE
- A_IO_EXT_REG
- A_IO_EXT_START_ADDR_BASE
- A_IO_EXT_TIME_CFG0_BASE
- A_IO_EXT_TIME_CFG1_BASE
- A_IO_INTERRUPT_ADDR0
- A_IO_INTERRUPT_ADDR1
- A_IO_INTERRUPT_DATA0
- A_IO_INTERRUPT_DATA1
- A_IO_INTERRUPT_DATA2
- A_IO_INTERRUPT_DATA3
- A_IO_INTERRUPT_PARITY
- A_IO_INTERRUPT_STATUS
- A_IO_PCMCIA_CFG
- A_IO_PCMCIA_STATUS
- A_IRQ_MSK
- A_ITRAM_ADDR
- A_ITRAM_CTL
- A_ITRAM_DATA
- A_L
- A_L2C_MGMT_TAG_BASE
- A_L2_CACHE_DISABLE
- A_L2_ECC_TAG
- A_L2_EEC_ADDRESS
- A_L2_MAKECACHEDISABLE
- A_L2_MAKEDISABLE
- A_L2_MGMT_TAG_BASE
- A_L2_MISC_CONFIG
- A_L2_READ_ADDRESS
- A_L2_READ_MISC
- A_L2_READ_TAG
- A_L2_WAY_DISABLE
- A_LIMB_1
- A_LOWORD_OPX_MASK
- A_LOWORD_OPY_MASK
- A_LOW_CHANS
- A_MACH
- A_MACL
- A_MAC_BASE_0
- A_MAC_BASE_1
- A_MAC_BASE_2
- A_MAC_BASE_3
- A_MAC_CHANNEL_BASE
- A_MAC_DMA_CHANNEL_BASE
- A_MAC_DMA_REGISTER
- A_MAC_REGISTER
- A_MAILBOX_REGISTER
- A_MASK
- A_MAX
- A_MC3_BD_ADDR
- A_MC3_BD_DATA0
- A_MC3_BD_DATA1
- A_MC3_BD_DATA2
- A_MC3_BD_DATA3
- A_MC3_BD_DATA4
- A_MC3_BD_OP
- A_MC3_BIST_ADDR_BEG
- A_MC3_BIST_ADDR_END
- A_MC3_BIST_DATA
- A_MC3_BIST_OP
- A_MC3_CE_ADDR
- A_MC3_CE_DATA0
- A_MC3_CE_DATA1
- A_MC3_CE_DATA2
- A_MC3_CE_DATA3
- A_MC3_CE_DATA4
- A_MC3_CFG
- A_MC3_ECC_CNTL
- A_MC3_EXT_MODE
- A_MC3_INT_CAUSE
- A_MC3_INT_ENABLE
- A_MC3_MODE
- A_MC3_PRECHARG
- A_MC3_REFRESH
- A_MC3_STROBE
- A_MC3_UE_ADDR
- A_MC3_UE_DATA0
- A_MC3_UE_DATA1
- A_MC3_UE_DATA2
- A_MC3_UE_DATA3
- A_MC3_UE_DATA4
- A_MC4_BD_ADDR
- A_MC4_BD_DATA0
- A_MC4_BD_DATA1
- A_MC4_BD_DATA2
- A_MC4_BD_DATA3
- A_MC4_BD_DATA4
- A_MC4_BD_OP
- A_MC4_BIST_ADDR_BEG
- A_MC4_BIST_ADDR_END
- A_MC4_BIST_DATA
- A_MC4_BIST_OP
- A_MC4_CE_ADDR
- A_MC4_CE_DATA0
- A_MC4_CE_DATA1
- A_MC4_CE_DATA2
- A_MC4_CE_DATA3
- A_MC4_CE_DATA4
- A_MC4_CFG
- A_MC4_ECC_CNTL
- A_MC4_EXT_MODE
- A_MC4_INT_CAUSE
- A_MC4_INT_ENABLE
- A_MC4_MODE
- A_MC4_REFRESH
- A_MC4_STROBE
- A_MC4_UE_ADDR
- A_MC4_UE_DATA0
- A_MC4_UE_DATA1
- A_MC4_UE_DATA2
- A_MC4_UE_DATA3
- A_MC4_UE_DATA4
- A_MC5_ACK_LRN_CMD
- A_MC5_ACK_SRCH_CMD
- A_MC5_AOPEN_LRN_CMD
- A_MC5_AOPEN_SRCH_CMD
- A_MC5_CONFIG
- A_MC5_DATA_READ_CMD
- A_MC5_DATA_WRITE_CMD
- A_MC5_DBGI_CONFIG
- A_MC5_DBGI_REQ_ADDR0
- A_MC5_DBGI_REQ_ADDR1
- A_MC5_DBGI_REQ_ADDR2
- A_MC5_DBGI_REQ_CMD
- A_MC5_DBGI_REQ_DATA0
- A_MC5_DBGI_REQ_DATA1
- A_MC5_DBGI_REQ_DATA2
- A_MC5_DBGI_REQ_DATA3
- A_MC5_DBGI_REQ_DATA4
- A_MC5_DBGI_REQ_MASK0
- A_MC5_DBGI_REQ_MASK1
- A_MC5_DBGI_REQ_MASK2
- A_MC5_DBGI_REQ_MASK3
- A_MC5_DBGI_REQ_MASK4
- A_MC5_DBGI_RSP_DATA0
- A_MC5_DBGI_RSP_DATA1
- A_MC5_DBGI_RSP_DATA2
- A_MC5_DBGI_RSP_DATA3
- A_MC5_DBGI_RSP_DATA4
- A_MC5_DBGI_RSP_LAST_CMD
- A_MC5_DBGI_RSP_STATUS
- A_MC5_DB_ACK_LRN_CMD
- A_MC5_DB_ACK_SRCH_CMD
- A_MC5_DB_AOPEN_LRN_CMD
- A_MC5_DB_AOPEN_SRCH_CMD
- A_MC5_DB_CONFIG
- A_MC5_DB_DATA_READ_CMD
- A_MC5_DB_DATA_WRITE_CMD
- A_MC5_DB_DBGI_CONFIG
- A_MC5_DB_DBGI_REQ_ADDR0
- A_MC5_DB_DBGI_REQ_ADDR1
- A_MC5_DB_DBGI_REQ_ADDR2
- A_MC5_DB_DBGI_REQ_CMD
- A_MC5_DB_DBGI_REQ_DATA0
- A_MC5_DB_DBGI_REQ_DATA1
- A_MC5_DB_DBGI_REQ_DATA2
- A_MC5_DB_DBGI_RSP_DATA0
- A_MC5_DB_DBGI_RSP_DATA1
- A_MC5_DB_DBGI_RSP_DATA2
- A_MC5_DB_DBGI_RSP_STATUS
- A_MC5_DB_ELOOKUP_CMD
- A_MC5_DB_FILTER_TABLE
- A_MC5_DB_ILOOKUP_CMD
- A_MC5_DB_INT_CAUSE
- A_MC5_DB_INT_ENABLE
- A_MC5_DB_PART_ID_INDEX
- A_MC5_DB_POPEN_DATA_WR_CMD
- A_MC5_DB_POPEN_MASK_WR_CMD
- A_MC5_DB_ROUTING_TABLE_INDEX
- A_MC5_DB_RSP_LATENCY
- A_MC5_DB_SERVER_INDEX
- A_MC5_DB_SYN_LRN_CMD
- A_MC5_DB_SYN_SRCH_CMD
- A_MC5_ELOOKUP_CMD
- A_MC5_ILOOKUP_CMD
- A_MC5_INT_CAUSE
- A_MC5_INT_ENABLE
- A_MC5_INT_PTID
- A_MC5_INT_TID
- A_MC5_LIP_RAM_ADDR
- A_MC5_LIP_RAM_DATA
- A_MC5_MASK_WRITE_CMD
- A_MC5_PARITY_LATENCY
- A_MC5_PART_ID_INDEX
- A_MC5_POPEN_DATA_WR_CMD
- A_MC5_POPEN_MASK_WR_CMD
- A_MC5_RESET_MAX
- A_MC5_ROUTING_TABLE_INDEX
- A_MC5_RSP_LATENCY
- A_MC5_SERVER_INDEX
- A_MC5_SIZE
- A_MC5_SYN_LRN_CMD
- A_MC5_SYN_SRCH_CMD
- A_MC5_WR_LRN_VERIFY
- A_MC7_BD_ADDR
- A_MC7_BD_DATA0
- A_MC7_BD_DATA1
- A_MC7_BD_OP
- A_MC7_BIST_ADDR_BEG
- A_MC7_BIST_ADDR_END
- A_MC7_BIST_DATA
- A_MC7_BIST_OP
- A_MC7_CAL
- A_MC7_CE_ADDR
- A_MC7_CE_DATA0
- A_MC7_CE_DATA1
- A_MC7_CE_DATA2
- A_MC7_CFG
- A_MC7_DLL
- A_MC7_ECC
- A_MC7_ERR_ADDR
- A_MC7_EXT_MODE1
- A_MC7_EXT_MODE2
- A_MC7_EXT_MODE3
- A_MC7_INT_CAUSE
- A_MC7_INT_ENABLE
- A_MC7_MODE
- A_MC7_PARM
- A_MC7_PRE
- A_MC7_REF
- A_MC7_UE_ADDR
- A_MC7_UE_DATA0
- A_MC7_UE_DATA1
- A_MC7_UE_DATA2
- A_MC_BASE
- A_MC_BASE_0
- A_MC_BASE_1
- A_MC_REGISTER
- A_MI0_ADDR
- A_MI0_CLK
- A_MI0_CSR
- A_MI0_DATA_EXT
- A_MI0_DATA_INT
- A_MI1_ADDR
- A_MI1_CFG
- A_MI1_DATA
- A_MI1_OP
- A_MICIDX
- A_MICIDX_IDX
- A_MICROCODEBASE
- A_MID_CHANS
- A_MODE_MAX_RIX
- A_MPS_CFG
- A_MPS_INT_CAUSE
- A_MPS_INT_ENABLE
- A_MST_CTLR
- A_MUCMD1
- A_MUCMD2
- A_MUDATA1
- A_MUDATA2
- A_MUSTAT1
- A_MUSTAT2
- A_MXRI64
- A_N
- A_NORMAL
- A_OF_PORT_A
- A_OP
- A_P
- A_P16VIN
- A_PAGES
- A_PCB
- A_PCICFG_INTR_CAUSE
- A_PCICFG_INTR_ENABLE
- A_PCICFG_MODE
- A_PCICFG_PCIX_CMD
- A_PCICFG_PM_CSR
- A_PCICFG_VPD_ADDR
- A_PCICFG_VPD_DATA
- A_PCIE_CFG
- A_PCIE_INT_CAUSE
- A_PCIE_INT_ENABLE
- A_PCIE_MODE
- A_PCIE_PEX_CTRL0
- A_PCIE_PEX_CTRL1
- A_PCIE_PEX_ERR
- A_PCIX_CFG
- A_PCIX_INT_CAUSE
- A_PCIX_INT_ENABLE
- A_PCIX_MODE
- A_PCI_TYPE00_HEADER
- A_PCI_TYPE01_HEADER
- A_PCM_192000
- A_PCM_44100
- A_PCM_48000
- A_PCM_96000
- A_PCM_RATE_MASK
- A_PHYS_GENBUS
- A_PHYS_GENBUS_END
- A_PHYS_IO_SYSTEM
- A_PHYS_L2CACHE_TOTAL_SIZE
- A_PHYS_L2CACHE_WAY0
- A_PHYS_L2CACHE_WAY1
- A_PHYS_L2CACHE_WAY2
- A_PHYS_L2CACHE_WAY3
- A_PHYS_L2CACHE_WAY_SIZE
- A_PHYS_L2_CACHE_TEST
- A_PHYS_LDTPCI_CFG_MATCH_BITS
- A_PHYS_LDTPCI_CFG_MATCH_BYTES
- A_PHYS_LDTPCI_IO_MATCH_BITS
- A_PHYS_LDTPCI_IO_MATCH_BITS_32
- A_PHYS_LDTPCI_IO_MATCH_BYTES
- A_PHYS_LDTPCI_IO_MATCH_BYTES_32
- A_PHYS_LDT_EXP
- A_PHYS_LDT_SPECIAL_MATCH_BITS
- A_PHYS_LDT_SPECIAL_MATCH_BYTES
- A_PHYS_MEMORY_0
- A_PHYS_MEMORY_1
- A_PHYS_MEMORY_2
- A_PHYS_MEMORY_3
- A_PHYS_MEMORY_EXP
- A_PHYS_MEMORY_EXP_SIZE
- A_PHYS_MEMORY_SIZE
- A_PHYS_PCI_FULLACCESS_BITS
- A_PHYS_PCI_FULLACCESS_BYTES
- A_PHYS_RESERVED
- A_PHYS_RESERVED_SPECIAL_LDT
- A_PHYS_SYSTEM_CTL
- A_PL_CAUSE
- A_PL_CLI
- A_PL_ENABLE
- A_PL_INT_CAUSE0
- A_PL_INT_ENABLE0
- A_PL_REV
- A_PL_RST
- A_PM1_RX_CFG
- A_PM1_RX_INT_CAUSE
- A_PM1_RX_INT_ENABLE
- A_PM1_RX_MODE
- A_PM1_TX_CFG
- A_PM1_TX_INT_CAUSE
- A_PM1_TX_INT_ENABLE
- A_PM1_TX_MODE
- A_PORT_CONFIG
- A_PR
- A_PTR_ADDRESS_MASK
- A_PUNC
- A_PUT_OUTPUT
- A_PUT_STEREO_OUTPUT
- A_R0
- A_R0_GBR
- A_R18
- A_RAM_STATUS
- A_RAT_INTR_CAUSE
- A_RAT_INTR_ENABLE
- A_RAT_NO_ROUTE
- A_RAT_ROUTE_CONTROL
- A_RAT_ROUTE_TABLE_DATA
- A_RAT_ROUTE_TABLE_INDEX
- A_REG_B
- A_REG_M
- A_REG_N
- A_REQ_TMROUT
- A_RX_DROP_COUNT0
- A_RX_DROP_COUNT1
- A_RX_DROP_THRESHOLD
- A_R_EDGE_STS
- A_S
- A_S10
- A_S10B
- A_S11
- A_S11I
- A_S14
- A_S16
- A_S18
- A_S3
- A_S6
- A_S7
- A_S7N
- A_SAMPLE_RATE
- A_SAMPLE_RATE_NOT_USED
- A_SAMPLE_RATE_UNKNOWN
- A_SCD_BUS_ERR_STATUS
- A_SCD_BUS_ERR_STATUS_DEBUG
- A_SCD_JTAG_BASE
- A_SCD_PERF_CNT
- A_SCD_PERF_CNT_0
- A_SCD_PERF_CNT_1
- A_SCD_PERF_CNT_2
- A_SCD_PERF_CNT_3
- A_SCD_PERF_CNT_CFG
- A_SCD_SCRATCH
- A_SCD_SYSTEM_CFG
- A_SCD_SYSTEM_MANUF
- A_SCD_SYSTEM_REVISION
- A_SCD_TIMER_0
- A_SCD_TIMER_1
- A_SCD_TIMER_2
- A_SCD_TIMER_3
- A_SCD_TIMER_BASE
- A_SCD_TIMER_CFG_0
- A_SCD_TIMER_CFG_1
- A_SCD_TIMER_CFG_2
- A_SCD_TIMER_CFG_3
- A_SCD_TIMER_CNT_0
- A_SCD_TIMER_CNT_1
- A_SCD_TIMER_CNT_2
- A_SCD_TIMER_CNT_3
- A_SCD_TIMER_INIT_0
- A_SCD_TIMER_INIT_1
- A_SCD_TIMER_INIT_2
- A_SCD_TIMER_INIT_3
- A_SCD_TIMER_REGISTER
- A_SCD_TRACE_CFG
- A_SCD_TRACE_EVENT
- A_SCD_TRACE_EVENT_0
- A_SCD_TRACE_EVENT_1
- A_SCD_TRACE_EVENT_2
- A_SCD_TRACE_EVENT_3
- A_SCD_TRACE_EVENT_4
- A_SCD_TRACE_EVENT_5
- A_SCD_TRACE_EVENT_6
- A_SCD_TRACE_EVENT_7
- A_SCD_TRACE_READ
- A_SCD_TRACE_SEQUENCE
- A_SCD_TRACE_SEQUENCE_0
- A_SCD_TRACE_SEQUENCE_1
- A_SCD_TRACE_SEQUENCE_2
- A_SCD_TRACE_SEQUENCE_3
- A_SCD_TRACE_SEQUENCE_4
- A_SCD_TRACE_SEQUENCE_5
- A_SCD_TRACE_SEQUENCE_6
- A_SCD_TRACE_SEQUENCE_7
- A_SCD_WDOG_0
- A_SCD_WDOG_1
- A_SCD_WDOG_BASE
- A_SCD_WDOG_CFG_0
- A_SCD_WDOG_CFG_1
- A_SCD_WDOG_CNT_0
- A_SCD_WDOG_CNT_1
- A_SCD_WDOG_INIT_0
- A_SCD_WDOG_INIT_1
- A_SCD_WDOG_REGISTER
- A_SCD_ZBBUS_CYCLE_COUNT
- A_SCD_ZBBUS_CYCLE_CP0
- A_SCD_ZBBUS_CYCLE_CP1
- A_SDRC0_V
- A_SENDAMOUNTS
- A_SER_BASE_0
- A_SER_BASE_1
- A_SER_CHANNEL_BASE
- A_SER_DMA_CHANNEL_BASE
- A_SER_DMA_REGISTER
- A_SER_REGISTER
- A_SF_DATA
- A_SF_OP
- A_SGR
- A_SG_CMD0BASELWR
- A_SG_CMD0BASEUPR
- A_SG_CMD0PTR
- A_SG_CMD0SIZE
- A_SG_CMD1BASELWR
- A_SG_CMD1BASEUPR
- A_SG_CMD1PTR
- A_SG_CMD1SIZE
- A_SG_CMDQ_CREDIT_TH
- A_SG_CONTEXT_CMD
- A_SG_CONTEXT_DATA0
- A_SG_CONTEXT_DATA1
- A_SG_CONTEXT_DATA2
- A_SG_CONTEXT_DATA3
- A_SG_CONTEXT_MASK0
- A_SG_CONTEXT_MASK1
- A_SG_CONTEXT_MASK2
- A_SG_CONTEXT_MASK3
- A_SG_CONTROL
- A_SG_CQ_CONTEXT_BADDR
- A_SG_DATA_INTR
- A_SG_DOORBELL
- A_SG_DRB_PRI_THRESH
- A_SG_EGR_CNTX_BADDR
- A_SG_EGR_RCQ_DRB_THRSH
- A_SG_FL0BASELWR
- A_SG_FL0BASEUPR
- A_SG_FL0PTR
- A_SG_FL0SIZE
- A_SG_FL1BASELWR
- A_SG_FL1BASEUPR
- A_SG_FL1PTR
- A_SG_FL1SIZE
- A_SG_FLTHRESHOLD
- A_SG_GTS
- A_SG_HI_DRB_HI_THRSH
- A_SG_HI_DRB_LO_THRSH
- A_SG_INTRTIMER
- A_SG_INT_CAUSE
- A_SG_INT_ENABLE
- A_SG_KDOORBELL
- A_SG_LO_DRB_HI_THRSH
- A_SG_LO_DRB_LO_THRSH
- A_SG_OCO_BASE
- A_SG_RESPACCUTIMER
- A_SG_RSPBASELWR
- A_SG_RSPBASEUPR
- A_SG_RSPQUEUECREDIT
- A_SG_RSPQ_CREDIT_RETURN
- A_SG_RSPQ_FL_STATUS
- A_SG_RSPSIZE
- A_SG_SLEEPING
- A_SG_TIMER_TICK
- A_SG_VERSION
- A_SIZE_16
- A_SIZE_32
- A_SIZE_8
- A_SIZE_FIX
- A_SIZE_LVL2
- A_SL_CFG
- A_SMB_0
- A_SMB_1
- A_SMB_BASE
- A_SMB_CMD_0
- A_SMB_CMD_1
- A_SMB_CONTROL_0
- A_SMB_CONTROL_1
- A_SMB_DATA_0
- A_SMB_DATA_1
- A_SMB_FREQ_0
- A_SMB_FREQ_1
- A_SMB_GLOBAL_TIME_CFG
- A_SMB_PEC_0
- A_SMB_PEC_1
- A_SMB_REGISTER
- A_SMB_START_0
- A_SMB_START_1
- A_SMB_STATUS_0
- A_SMB_STATUS_1
- A_SMB_XTRA_0
- A_SMB_XTRA_1
- A_SOURCE
- A_SPC
- A_SPDIF_192000
- A_SPDIF_44100
- A_SPDIF_48000
- A_SPDIF_96000
- A_SPDIF_RATE_MASK
- A_SPDIF_SAMPLERATE
- A_SPRA
- A_SPRC
- A_SPRI
- A_SPSC
- A_SR
- A_SRP_DETECT
- A_SRT3
- A_SRT4
- A_SRT5
- A_SSC_GEN
- A_SSC_M
- A_SSC_PERI
- A_SSC_S
- A_SSR
- A_ST_B1_RX
- A_ST_B1_TX
- A_ST_B2_RX
- A_ST_B2_TX
- A_ST_CLK_DLY
- A_ST_CTRL0
- A_ST_CTRL1
- A_ST_CTRL2
- A_ST_D_RX
- A_ST_D_TX
- A_ST_E_RX
- A_ST_RD_STA
- A_ST_RD_STATE
- A_ST_SQ_RD
- A_ST_SQ_WR
- A_ST_WR_STATE
- A_SUBCH_CFG
- A_SUPPORTED_RATES
- A_SWITCH
- A_SWITCH_NEG
- A_T
- A_T3DBG_GPIO_ACT_LOW
- A_T3DBG_GPIO_EN
- A_T3DBG_INT_CAUSE
- A_T3DBG_INT_ENABLE
- A_TANKMEMCTLREGBASE
- A_TANKMEMCTLREG_MASK
- A_TBLSZ
- A_TDOF
- A_TIME_SLOT1
- A_TIME_SLOT2
- A_TOTAL_SIZE_CODE
- A_TOTAL_SIZE_GPR
- A_TOTAL_SIZE_TANKMEM_ADDR
- A_TOTAL_SIZE_TANKMEM_DATA
- A_TPI_ADDR
- A_TPI_CSR
- A_TPI_PAR
- A_TPI_RD_DATA
- A_TPI_WR_DATA
- A_TP_2MSL
- A_TP_BACKOFF0
- A_TP_BACKOFF1
- A_TP_BACKOFF2
- A_TP_BACKOFF3
- A_TP_CCTRL_TABLE
- A_TP_CMM_MM_BASE
- A_TP_CMM_MM_MAX_PSTRUCT
- A_TP_CMM_MM_PS_FLST_BASE
- A_TP_CMM_MM_RX_FLST_BASE
- A_TP_CMM_MM_TX_FLST_BASE
- A_TP_CMM_TIMER_BASE
- A_TP_CM_FC_MODE
- A_TP_CM_MM_BASE
- A_TP_CM_MM_MAX_P
- A_TP_CM_MM_P_FLST_BASE
- A_TP_CM_MM_RX_FLST_BASE
- A_TP_CM_MM_TX_FLST_BASE
- A_TP_CM_SIZE
- A_TP_CM_TIMER_BASE
- A_TP_DACK_CONFIG
- A_TP_DACK_TIME
- A_TP_DACK_TIMER
- A_TP_EGRESS_CONFIG
- A_TP_EMBED_OP_FIELD0
- A_TP_EMBED_OP_FIELD1
- A_TP_EMBED_OP_FIELD2
- A_TP_EMBED_OP_FIELD3
- A_TP_EMBED_OP_FIELD4
- A_TP_EMBED_OP_FIELD5
- A_TP_FAST_FINWAIT2_TIME
- A_TP_FINWAIT2_TIME
- A_TP_FINWAIT2_TIMER
- A_TP_GLOBAL_CONFIG
- A_TP_GLOBAL_RX_CREDITS
- A_TP_INIT_SRTT
- A_TP_INT_CAUSE
- A_TP_INT_ENABLE
- A_TP_IN_CONFIG
- A_TP_KEEP_IDLE
- A_TP_KEEP_INTVL
- A_TP_MIB_DATA
- A_TP_MIB_INDEX
- A_TP_MIB_RDATA
- A_TP_MOD_CHANNEL_WEIGHT
- A_TP_MOD_RATE_LIMIT
- A_TP_MSL
- A_TP_MTU_PORT_TABLE
- A_TP_MTU_REG0
- A_TP_MTU_REG1
- A_TP_MTU_REG2
- A_TP_MTU_REG3
- A_TP_MTU_REG4
- A_TP_MTU_REG5
- A_TP_MTU_REG6
- A_TP_MTU_REG7
- A_TP_MTU_TABLE
- A_TP_OUT_CONFIG
- A_TP_PARA_REG0
- A_TP_PARA_REG1
- A_TP_PARA_REG2
- A_TP_PARA_REG3
- A_TP_PARA_REG4
- A_TP_PARA_REG5
- A_TP_PARA_REG6
- A_TP_PARA_REG7
- A_TP_PC_CONFIG
- A_TP_PC_CONFIG2
- A_TP_PC_CONGESTION_CNTL
- A_TP_PERS_MAX
- A_TP_PERS_MIN
- A_TP_PIO_ADDR
- A_TP_PIO_DATA
- A_TP_PMM_RX_BASE
- A_TP_PMM_RX_MAX_PAGE
- A_TP_PMM_RX_PAGE_SIZE
- A_TP_PMM_SIZE
- A_TP_PMM_TX_BASE
- A_TP_PMM_TX_MAX_PAGE
- A_TP_PMM_TX_PAGE_SIZE
- A_TP_PM_DEFRAG_BASE
- A_TP_PM_RX_BASE
- A_TP_PM_RX_MAX_PGS
- A_TP_PM_RX_PG_SIZE
- A_TP_PM_SIZE
- A_TP_PM_TX_BASE
- A_TP_PM_TX_MAX_PGS
- A_TP_PM_TX_PG_SIZE
- A_TP_PROXY_FLOW_CNTL
- A_TP_QOS_REG0
- A_TP_QOS_REG1
- A_TP_QOS_REG2
- A_TP_QOS_REG3
- A_TP_QOS_REG4
- A_TP_QOS_REG5
- A_TP_QOS_REG6
- A_TP_QOS_REG7
- A_TP_RESET
- A_TP_RSS_CONFIG
- A_TP_RSS_LKP_TABLE
- A_TP_RSS_MAP_TABLE
- A_TP_RXT_MAX
- A_TP_RXT_MIN
- A_TP_RX_TRC_KEY0
- A_TP_SHIFT_CNT
- A_TP_SYNC_TIME_HI
- A_TP_SYNC_TIME_LO
- A_TP_TCP_BACKOFF_REG0
- A_TP_TCP_BACKOFF_REG1
- A_TP_TCP_BACKOFF_REG2
- A_TP_TCP_BACKOFF_REG3
- A_TP_TCP_OPTIONS
- A_TP_TIMER_RESOLUTION
- A_TP_TIMER_SEPARATOR
- A_TP_TM_PIO_ADDR
- A_TP_TM_PIO_DATA
- A_TP_TX_DROP_CFG_CH0
- A_TP_TX_DROP_CNT_CH0
- A_TP_TX_DROP_CONFIG
- A_TP_TX_DROP_COUNT
- A_TP_TX_DROP_MODE
- A_TP_TX_MOD_Q1_Q0_RATE_LIMIT
- A_TP_TX_MOD_QUEUE_REQ_MAP
- A_TP_TX_MOD_QUEUE_WEIGHT0
- A_TP_TX_MOD_QUEUE_WEIGHT1
- A_TP_TX_MOD_QUE_TABLE
- A_TP_TX_RESOURCE_LIMIT
- A_TP_TX_TRC_KEY0
- A_TTB
- A_TTDA
- A_TTDD
- A_TX_DROP_COUNT0
- A_TX_DROP_COUNT1
- A_U14
- A_U18
- A_U3
- A_U5
- A_U6
- A_U7
- A_U7A
- A_U7B
- A_ULPRX_CTL
- A_ULPRX_INT_CAUSE
- A_ULPRX_INT_ENABLE
- A_ULPRX_ISCSI_LLIMIT
- A_ULPRX_ISCSI_PSZ
- A_ULPRX_ISCSI_TAGMASK
- A_ULPRX_ISCSI_ULIMIT
- A_ULPRX_PBL_LLIMIT
- A_ULPRX_PBL_ULIMIT
- A_ULPRX_RQ_LLIMIT
- A_ULPRX_RQ_ULIMIT
- A_ULPRX_STAG_LLIMIT
- A_ULPRX_STAG_ULIMIT
- A_ULPRX_TDDP_LLIMIT
- A_ULPRX_TDDP_PSZ
- A_ULPRX_TDDP_TAGMASK
- A_ULPRX_TDDP_ULIMIT
- A_ULPTX_CONFIG
- A_ULPTX_DMA_WEIGHT
- A_ULPTX_INT_CAUSE
- A_ULPTX_INT_ENABLE
- A_ULPTX_PBL_LLIMIT
- A_ULPTX_PBL_ULIMIT
- A_ULPTX_TPT_LLIMIT
- A_ULPTX_TPT_ULIMIT
- A_ULP_HREG_DATA
- A_ULP_HREG_INDEX
- A_ULP_INT_CAUSE
- A_ULP_INT_ENABLE
- A_ULP_PIO_CTRL
- A_ULP_TAGMASK
- A_ULP_ULIMIT
- A_VBR
- A_VBUS_ERR
- A_VDSO
- A_VID_FORM
- A_VIT_BER_0
- A_VIT_BER_TIMER_0
- A_VTUNE_M
- A_VVAR
- A_W
- A_WAIT_BCON
- A_WAIT_BCON_TIMER
- A_WAIT_ENUM
- A_WAIT_VFALL
- A_WAIT_VRISE
- A_X16
- A_XGM_INT_CAUSE
- A_XGM_INT_ENABLE
- A_XGM_INT_STATUS
- A_XGM_PAUSE_TIMER
- A_XGM_PORT_CFG
- A_XGM_RESET_CTRL
- A_XGM_RGMII_IMP
- A_XGM_RXFIFO_CFG
- A_XGM_RX_CFG
- A_XGM_RX_CTRL
- A_XGM_RX_EXACT_MATCH_HIGH_1
- A_XGM_RX_EXACT_MATCH_LOW_1
- A_XGM_RX_EXACT_MATCH_LOW_2
- A_XGM_RX_EXACT_MATCH_LOW_3
- A_XGM_RX_EXACT_MATCH_LOW_4
- A_XGM_RX_EXACT_MATCH_LOW_5
- A_XGM_RX_EXACT_MATCH_LOW_6
- A_XGM_RX_EXACT_MATCH_LOW_7
- A_XGM_RX_EXACT_MATCH_LOW_8
- A_XGM_RX_HASH_HIGH
- A_XGM_RX_HASH_LOW
- A_XGM_RX_MAX_PKT_SIZE
- A_XGM_RX_MAX_PKT_SIZE_ERR_CNT
- A_XGM_RX_SPI4_SOP_EOP_CNT
- A_XGM_SERDES_CTRL
- A_XGM_SERDES_CTRL0
- A_XGM_SERDES_STAT0
- A_XGM_SERDES_STAT1
- A_XGM_SERDES_STAT2
- A_XGM_SERDES_STAT3
- A_XGM_SERDES_STATUS0
- A_XGM_SERDES_STATUS1
- A_XGM_STAT_CTRL
- A_XGM_STAT_RX_1024_1518B_FRAMES
- A_XGM_STAT_RX_128_255B_FRAMES
- A_XGM_STAT_RX_1519_MAXB_FRAMES
- A_XGM_STAT_RX_256_511B_FRAMES
- A_XGM_STAT_RX_512_1023B_FRAMES
- A_XGM_STAT_RX_64B_FRAMES
- A_XGM_STAT_RX_65_127B_FRAMES
- A_XGM_STAT_RX_BCAST_FRAMES
- A_XGM_STAT_RX_BYTES_HIGH
- A_XGM_STAT_RX_BYTES_LOW
- A_XGM_STAT_RX_CRC_ERR_FRAMES
- A_XGM_STAT_RX_FRAMES_HIGH
- A_XGM_STAT_RX_FRAMES_LOW
- A_XGM_STAT_RX_JABBER_FRAMES
- A_XGM_STAT_RX_LENGTH_ERR_FRAMES
- A_XGM_STAT_RX_MCAST_FRAMES
- A_XGM_STAT_RX_OVERSIZE_FRAMES
- A_XGM_STAT_RX_PAUSE_FRAMES
- A_XGM_STAT_RX_SHORT_FRAMES
- A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES
- A_XGM_STAT_TX_1024_1518B_FRAMES
- A_XGM_STAT_TX_128_255B_FRAMES
- A_XGM_STAT_TX_1519_MAXB_FRAMES
- A_XGM_STAT_TX_256_511B_FRAMES
- A_XGM_STAT_TX_512_1023B_FRAMES
- A_XGM_STAT_TX_64B_FRAMES
- A_XGM_STAT_TX_65_127B_FRAMES
- A_XGM_STAT_TX_BCAST
- A_XGM_STAT_TX_BYTE_HIGH
- A_XGM_STAT_TX_BYTE_LOW
- A_XGM_STAT_TX_ERR_FRAMES
- A_XGM_STAT_TX_FRAME_HIGH
- A_XGM_STAT_TX_FRAME_LOW
- A_XGM_STAT_TX_MCAST
- A_XGM_STAT_TX_PAUSE
- A_XGM_TXFIFO_CFG
- A_XGM_TX_CFG
- A_XGM_TX_CTRL
- A_XGM_TX_PAUSE_QUANTA
- A_XGM_TX_SPI4_SOP_EOP_CNT
- A_XGM_XAUI_ACT_CTRL
- A_XGM_XAUI_IMP
- A_XGM_XGM_INT_DISABLE
- A_XGM_XGM_INT_ENABLE
- A_Z1
- A_Z12
- A_Z1H
- A_Z1L
- A_Z2
- A_Z2H
- A_Z2L
- AadHash
- AadLen
- AbnormalIntr
- Abort
- AbortCmd
- AcceptAll
- AcceptAllIPMulti
- AcceptAllMulticast
- AcceptAllPhys
- AcceptBroadcast
- AcceptErr
- AcceptMultiHash
- AcceptMulticast
- AcceptMyPhys
- AcceptRunt
- AckIntr
- AcmAvg
- AcmFwCtrl
- AcmFw_BeqStatus
- AcmFw_ViqStatus
- AcmFw_VoqStatus
- AcmHwCtrl
- AcmHw_BeqEn
- AcmHw_BeqEn_8723B
- AcmHw_BeqStatus
- AcmHw_BeqStatus_8723B
- AcmHw_HwEn
- AcmHw_HwEn_8723B
- AcmHw_ViqEn
- AcmHw_ViqEn_8723B
- AcmHw_ViqStatus
- AcmHw_ViqStatus_8723B
- AcmHw_VoqEn
- AcmHw_VoqEn_8723B
- AcmHw_VoqStatus
- AcmHw_VoqStatus_8723B
- AcpBootLevel
- AcpBootLevel_MASK
- AcpBootLevel_SHIFT
- AcpiDisplayType_CRT1
- AcpiDisplayType_CRT2
- AcpiDisplayType_DFP1
- AcpiDisplayType_DFP2
- AcpiDisplayType_DFP3
- AcpiDisplayType_DFP4
- AcpiDisplayType_DFP5
- AcpiDisplayType_DFP6
- AcpiDisplayType_LCD1
- AcpiDisplayType_LCD2
- ActivateBAEntry
- ActiveCRT
- ActiveCRT2
- ActiveDUO
- ActiveLCD
- ActiveNonExpanding
- ActiveNonExpandingShift
- ActivePAL
- ActivePALShift
- ActiveTV
- AdapHighCmdNotFull
- AdapHighCmdQue
- AdapHighCmdQueue
- AdapHighRespNotFull
- AdapHighRespQue
- AdapHighRespQueue
- AdapInternalError
- AdapNormCmdNotFull
- AdapNormCmdQue
- AdapNormCmdQueue
- AdapNormRespNotFull
- AdapNormRespQue
- AdapNormRespQueue
- AdapPrintfDone
- AdapterClass
- AdapterControlBlock
- AdapterCtlBlk
- AdapterFailure
- AdapterMicroFib
- AdapterOwned
- AdapterProcessed
- Adaptive_SIR
- AddColReg
- AddIPChksum
- AddPIDFilter
- AddReorderEntry
- AddTCPChksum
- AddUDPChksum
- AddrLong
- AddrMode
- AdjustARB_SEQ
- AdmissionConfirm
- AdmissionRequest
- AdmitTS
- AdvAbortQueue
- AdvBuildCarrierFreelist
- AdvExeScsiQueue
- AdvFindSignature
- AdvGet3550EEPConfig
- AdvGet38C0800EEPConfig
- AdvGet38C1600EEPConfig
- AdvGetChipVersion
- AdvISR
- AdvInitAsc3550Driver
- AdvInitAsc38C0800Driver
- AdvInitAsc38C1600Driver
- AdvInitFrom3550EEP
- AdvInitFrom38C0800EEP
- AdvInitFrom38C1600EEP
- AdvInitGetConfig
- AdvIsIntPending
- AdvLoadMicrocode
- AdvPortAddr
- AdvReadByteLram
- AdvReadByteRegister
- AdvReadEEPWord
- AdvReadWordAutoIncLram
- AdvReadWordLram
- AdvReadWordRegister
- AdvResetChipAndSB
- AdvResetDevice
- AdvResetSB
- AdvSendIdleCmd
- AdvSet3550EEPConfig
- AdvSet38C0800EEPConfig
- AdvSet38C1600EEPConfig
- AdvWaitEEPCmd
- AdvWriteByteLram
- AdvWriteByteRegister
- AdvWriteDWordLramNoSwap
- AdvWriteDWordRegister
- AdvWriteWordAutoIncLram
- AdvWriteWordLram
- AdvWriteWordRegister
- Agent_OnLoad
- Agent_OnUnload
- AgfaCl20
- AgmAvfsData_t
- AhdocPHY
- AhdocPHYID0
- AifBuCacheDataLoss
- AifBuCacheDataRecover
- AifBuManagerEvent
- AifCmdAPIReport
- AifCmdDriverNotify
- AifCmdEventNotify
- AifCmdJobProgress
- AifDenMorphComplete
- AifDenVolumeExtendComplete
- AifEnAddContainer
- AifEnAddJBOD
- AifEnBatteryEvent
- AifEnConfigChange
- AifEnContainerChange
- AifEnDeleteContainer
- AifEnDeleteJBOD
- AifEnDeviceFailure
- AifEnEnclosureManagement
- AifEnExpEvent
- AifExeFirmwarePanic
- AifHighPriority
- AifJobCtrZero
- AifJobStsRunning
- AifJobStsSuccess
- AifNativeDeviceAdd
- AifNativeDeviceRemove
- AifRawDeviceRemove
- AifReqAPIJobFinish
- AifReqAPIJobStart
- AifReqAPIJobUpdate
- AifReqEvent
- AifReqJobList
- AifReqJobReport
- AifReqJobsForCtr
- AifReqJobsForScsi
- AifReqResumeJob
- AifReqSendAPIReport
- AifReqSuspendJob
- AifReqTerminateJob
- AifRequest
- AiptekMiniPenCam13
- AiptekPocketDV
- Alerting_UUIE
- Alerting_UUIE_fastStart
- AlignErr
- AlignMask
- Aligned
- Aligned16
- AllPersist
- Allexception
- Allflags
- AllocCommonBuffers
- AllocMidQEntry
- AllocateRingBuffers
- AllocatedFromPool
- AltRxPromisc
- AlwaysFDX
- Am79C960
- AmiAlloc
- AmiFree
- AmiInit
- AmiInterrupt
- AmiIrqCleanUp
- AmiIrqInit
- AmiMixerInit
- AmiMixerIoctl
- AmiPlay
- AmiPlayNextFrame
- AmiSetFormat
- AmiSetTreble
- AmiSetVolume
- AmiSilence
- AmiStateInfo
- AmiWriteSqSetup
- AnalogTV_Info
- AnegAdv
- AnegPeer
- Anonymous
- Ant_x1
- Ant_x2
- AntennaDiversityValue
- Antenna_A
- Antenna_B
- Antenna_MAX
- ApiFib
- Ar5416RateSize
- Arc
- ArcAddChild
- ArcClose
- ArcDeleteComponent
- ArcEnterInteractiveMode
- ArcExecute
- ArcFlushAllCaches
- ArcGetChild
- ArcGetComponent
- ArcGetConfigurationData
- ArcGetDirectoryEntry
- ArcGetDisplayStatus
- ArcGetEnvironmentVariable
- ArcGetFileInformation
- ArcGetMemoryDescriptor
- ArcGetParent
- ArcGetPeer
- ArcGetReadStatus
- ArcGetRelativeTime
- ArcGetSystemId
- ArcGetTime
- ArcHalt
- ArcInvoke
- ArcLoad
- ArcMount
- ArcOpen
- ArcPowerDown
- ArcProto
- ArcRead
- ArcReboot
- ArcRestart
- ArcSaveConfiguration
- ArcSeek
- ArcSetEnvironmentVariable
- ArcSetFileInformation
- ArcWrite
- AreaStipplePattern_indexed
- Arowana300KCMOSCamera
- ArrayMode
- AscAckInterrupt
- AscAllocFreeQueue
- AscAllocMultipleFreeQueue
- AscAsyncFix
- AscCalSDTRData
- AscDisableInterrupt
- AscEnableInterrupt
- AscEnableIsaDma
- AscExeScsiQueue
- AscFindSignature
- AscGetChipBiosAddress
- AscGetChipCfgLsw
- AscGetChipCfgMsw
- AscGetChipControl
- AscGetChipEEPCmd
- AscGetChipEEPData
- AscGetChipIFC
- AscGetChipLramAddr
- AscGetChipLramData
- AscGetChipScsiCtrl
- AscGetChipScsiID
- AscGetChipSignatureByte
- AscGetChipSignatureWord
- AscGetChipStatus
- AscGetChipSyn
- AscGetChipVerNo
- AscGetChipVersion
- AscGetEEPConfig
- AscGetExtraControl
- AscGetIsaDmaChannel
- AscGetIsaDmaSpeed
- AscGetMCodeInitSDTRAtID
- AscGetMCodeSDTRDoneAtID
- AscGetMaxDmaCount
- AscGetNumOfFreeQueue
- AscGetPCAddr
- AscGetQDoneInProgress
- AscGetRiscVarDoneQTail
- AscGetRiscVarFreeQHead
- AscGetSynPeriodIndex
- AscGetVarDoneQTail
- AscGetVarFreeQHead
- AscHostReqRiscHalt
- AscISR
- AscInitAsc1000Driver
- AscInitAscDvcVar
- AscInitFromEEP
- AscInitGetConfig
- AscInitLram
- AscInitMicroCodeVar
- AscInitQLinkVar
- AscInitSetConfig
- AscIsChipHalted
- AscIsIntPending
- AscIsrChipHalted
- AscIsrQDone
- AscLoadMicroCode
- AscMemDWordCopyPtrToLram
- AscMemSumLramWord
- AscMemWordCopyPtrFromLram
- AscMemWordCopyPtrToLram
- AscMemWordSetLram
- AscMsgOutSDTR
- AscPutMCodeInitSDTRAtID
- AscPutMCodeSDTRDoneAtID
- AscPutQDoneInProgress
- AscPutReadyQueue
- AscPutReadySgListQueue
- AscPutRiscVarDoneQTail
- AscPutRiscVarFreeQHead
- AscPutVarDoneQTail
- AscPutVarFreeQHead
- AscReadChipAX
- AscReadChipDA0
- AscReadChipDA1
- AscReadChipDC0
- AscReadChipDC1
- AscReadChipDmaSpeed
- AscReadChipDvcID
- AscReadChipFIFO_H
- AscReadChipFIFO_L
- AscReadChipIH
- AscReadChipIX
- AscReadChipQP
- AscReadEEPWord
- AscReadLramByte
- AscReadLramWord
- AscResetChipAndScsiBus
- AscSendScsiQueue
- AscSetBank
- AscSetChipCfgLsw
- AscSetChipCfgMsw
- AscSetChipControl
- AscSetChipEEPCmd
- AscSetChipEEPData
- AscSetChipIFC
- AscSetChipIH
- AscSetChipLramAddr
- AscSetChipLramData
- AscSetChipSDTR
- AscSetChipScsiID
- AscSetChipStatus
- AscSetChipSyn
- AscSetChipSynRegAtID
- AscSetEEPConfig
- AscSetEEPConfigOnce
- AscSetExtraControl
- AscSetIsaDmaChannel
- AscSetIsaDmaSpeed
- AscSetLibErrorCode
- AscSetPCAddr
- AscSetRunChipSynRegAtID
- AscSgListToQueue
- AscStartChip
- AscStopChip
- AscStopQueueExe
- AscTestExternalLram
- AscWaitEEPRead
- AscWaitEEPWrite
- AscWriteChipAX
- AscWriteChipDA0
- AscWriteChipDA1
- AscWriteChipDC0
- AscWriteChipDC1
- AscWriteChipDmaSpeed
- AscWriteChipDvcID
- AscWriteChipFIFO_H
- AscWriteChipFIFO_L
- AscWriteChipIH
- AscWriteChipIX
- AscWriteChipQP
- AscWriteEEPCmdReg
- AscWriteEEPDataReg
- AscWriteEEPWord
- AscWriteLramByte
- AscWriteLramWord
- AsicStateEx
- Assert
- AssignAcl
- Associated_AP
- Async
- AsyncCIOFIFOPointer
- AsyncIo
- AtaAlloc
- AtaFree
- AtaInterrupt
- AtaIrqCleanUp
- AtaIrqInit
- AtaMixerIoctl
- AtaPlay
- AtaPlayNextFrame
- AtaSetBass
- AtaSetTreble
- AtaSqOpen
- AtaWriteSqSetup
- AtmelFWType
- AtomicReadBlock
- AtomicReadReg32
- AttrOn
- Audio
- AudioBuffState
- AudioController
- AudioDAC
- AudioMp2
- AudioPCM
- AudioPES
- AudioPID
- AudioState
- Audit_bad
- Audit_bitmask
- Audit_bittest
- Audit_equal
- Audit_ge
- Audit_gt
- Audit_le
- Audit_lt
- Audit_not_equal
- AutoDetected
- AutoVLANtagging
- AutoVLANuntagging
- Autoselect
- Available_0x1c
- Available_0x1d
- AverageGraphicsActivity
- AverageMemoryActivity
- AvfsDebugTable_t
- AvfsDebugTable_t_NV10
- AvfsDebugTable_t_NV14
- AvfsFuseOverride_t
- AvfsTable_t
- Avx
- AxCACHE_B
- AxCACHE_M
- AxCACHE_MASK
- AxCACHE_RA
- AxCACHE_WA
[..]