CONFIG_MBAR 162 arch/m68k/coldfire/head.S #ifdef CONFIG_MBAR CONFIG_MBAR 42 arch/m68k/include/asm/coldfire.h #ifdef CONFIG_MBAR CONFIG_MBAR 43 arch/m68k/include/asm/coldfire.h #define MCF_MBAR CONFIG_MBAR CONFIG_MBAR 21 arch/m68k/include/asm/m54xxpci.h #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */ CONFIG_MBAR 22 arch/m68k/include/asm/m54xxpci.h #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */ CONFIG_MBAR 23 arch/m68k/include/asm/m54xxpci.h #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */ CONFIG_MBAR 24 arch/m68k/include/asm/m54xxpci.h #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */ CONFIG_MBAR 25 arch/m68k/include/asm/m54xxpci.h #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */ CONFIG_MBAR 26 arch/m68k/include/asm/m54xxpci.h #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */ CONFIG_MBAR 27 arch/m68k/include/asm/m54xxpci.h #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */ CONFIG_MBAR 28 arch/m68k/include/asm/m54xxpci.h #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */ CONFIG_MBAR 29 arch/m68k/include/asm/m54xxpci.h #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */ CONFIG_MBAR 30 arch/m68k/include/asm/m54xxpci.h #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */ CONFIG_MBAR 31 arch/m68k/include/asm/m54xxpci.h #define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */ CONFIG_MBAR 33 arch/m68k/include/asm/m54xxpci.h #define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */ CONFIG_MBAR 34 arch/m68k/include/asm/m54xxpci.h #define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */ CONFIG_MBAR 35 arch/m68k/include/asm/m54xxpci.h #define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */ CONFIG_MBAR 36 arch/m68k/include/asm/m54xxpci.h #define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */ CONFIG_MBAR 37 arch/m68k/include/asm/m54xxpci.h #define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */ CONFIG_MBAR 38 arch/m68k/include/asm/m54xxpci.h #define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */ CONFIG_MBAR 39 arch/m68k/include/asm/m54xxpci.h #define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */ CONFIG_MBAR 40 arch/m68k/include/asm/m54xxpci.h #define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */ CONFIG_MBAR 41 arch/m68k/include/asm/m54xxpci.h #define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */ CONFIG_MBAR 42 arch/m68k/include/asm/m54xxpci.h #define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */ CONFIG_MBAR 43 arch/m68k/include/asm/m54xxpci.h #define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */ CONFIG_MBAR 45 arch/m68k/include/asm/m54xxpci.h #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */ CONFIG_MBAR 46 arch/m68k/include/asm/m54xxpci.h #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */ CONFIG_MBAR 47 arch/m68k/include/asm/m54xxpci.h #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */ CONFIG_MBAR 48 arch/m68k/include/asm/m54xxpci.h #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */ CONFIG_MBAR 49 arch/m68k/include/asm/m54xxpci.h #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */ CONFIG_MBAR 50 arch/m68k/include/asm/m54xxpci.h #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */ CONFIG_MBAR 51 arch/m68k/include/asm/m54xxpci.h #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */ CONFIG_MBAR 52 arch/m68k/include/asm/m54xxpci.h #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */ CONFIG_MBAR 53 arch/m68k/include/asm/m54xxpci.h #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */ CONFIG_MBAR 54 arch/m68k/include/asm/m54xxpci.h #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */ CONFIG_MBAR 55 arch/m68k/include/asm/m54xxpci.h #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */ CONFIG_MBAR 56 arch/m68k/include/asm/m54xxpci.h #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */ CONFIG_MBAR 57 arch/m68k/include/asm/m54xxpci.h #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */ CONFIG_MBAR 58 arch/m68k/include/asm/m54xxpci.h #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */ CONFIG_MBAR 60 arch/m68k/include/asm/m54xxpci.h #define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */ CONFIG_MBAR 61 arch/m68k/include/asm/m54xxpci.h #define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */ CONFIG_MBAR 62 arch/m68k/include/asm/m54xxpci.h #define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */ CONFIG_MBAR 63 arch/m68k/include/asm/m54xxpci.h #define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */ CONFIG_MBAR 64 arch/m68k/include/asm/m54xxpci.h #define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */ CONFIG_MBAR 65 arch/m68k/include/asm/m54xxpci.h #define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */ CONFIG_MBAR 66 arch/m68k/include/asm/m54xxpci.h #define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */ CONFIG_MBAR 67 arch/m68k/include/asm/m54xxpci.h #define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */ CONFIG_MBAR 68 arch/m68k/include/asm/m54xxpci.h #define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */ CONFIG_MBAR 69 arch/m68k/include/asm/m54xxpci.h #define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */ CONFIG_MBAR 70 arch/m68k/include/asm/m54xxpci.h #define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */ CONFIG_MBAR 71 arch/m68k/include/asm/m54xxpci.h #define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */ CONFIG_MBAR 72 arch/m68k/include/asm/m54xxpci.h #define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */ CONFIG_MBAR 74 arch/m68k/include/asm/m54xxpci.h #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */ CONFIG_MBAR 75 arch/m68k/include/asm/m54xxpci.h #define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */