asyh 181 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nv50_head_atom *asyh) asyh 183 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.cpp = 0; asyh 188 drivers/gpu/drm/nouveau/dispnv50/base507c.c struct nv50_head_atom *asyh) asyh 193 drivers/gpu/drm/nouveau/dispnv50/base507c.c ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, asyh 201 drivers/gpu/drm/nouveau/dispnv50/base507c.c if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1)) asyh 202 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->state.color_mgmt_changed = true; asyh 205 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.depth = fb->format->depth; asyh 206 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.cpp = fb->format->cpp[0]; asyh 207 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.x = asyw->state.src.x1 >> 16; asyh 208 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.y = asyw->state.src.y1 >> 16; asyh 209 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.w = asyw->state.fb->width; asyh 210 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.h = asyw->state.fb->height; asyh 216 drivers/gpu/drm/nouveau/dispnv50/base507c.c if (!asyh->base.depth) asyh 217 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.depth = asyh->base.cpp * 8; asyh 51 drivers/gpu/drm/nouveau/dispnv50/curs507a.c curs507a_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh, asyh 56 drivers/gpu/drm/nouveau/dispnv50/curs507a.c if (asyh->curs.handle != handle || asyh->curs.offset != offset) { asyh 57 drivers/gpu/drm/nouveau/dispnv50/curs507a.c asyh->curs.handle = handle; asyh 58 drivers/gpu/drm/nouveau/dispnv50/curs507a.c asyh->curs.offset = offset; asyh 59 drivers/gpu/drm/nouveau/dispnv50/curs507a.c asyh->set.curs = asyh->curs.visible; asyh 65 drivers/gpu/drm/nouveau/dispnv50/curs507a.c struct nv50_head_atom *asyh) asyh 67 drivers/gpu/drm/nouveau/dispnv50/curs507a.c asyh->curs.visible = false; asyh 72 drivers/gpu/drm/nouveau/dispnv50/curs507a.c struct nv50_head_atom *asyh) asyh 77 drivers/gpu/drm/nouveau/dispnv50/curs507a.c ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, asyh 81 drivers/gpu/drm/nouveau/dispnv50/curs507a.c asyh->curs.visible = asyw->state.visible; asyh 82 drivers/gpu/drm/nouveau/dispnv50/curs507a.c if (ret || !asyh->curs.visible) asyh 88 drivers/gpu/drm/nouveau/dispnv50/curs507a.c ret = head->func->curs_layout(head, asyw, asyh); asyh 92 drivers/gpu/drm/nouveau/dispnv50/curs507a.c return head->func->curs_format(head, asyw, asyh); asyh 26 drivers/gpu/drm/nouveau/dispnv50/dac507d.c struct nv50_head_atom *asyh) asyh 30 drivers/gpu/drm/nouveau/dispnv50/dac507d.c if (asyh) { asyh 31 drivers/gpu/drm/nouveau/dispnv50/dac507d.c sync |= asyh->or.nvsync << 1; asyh 32 drivers/gpu/drm/nouveau/dispnv50/dac507d.c sync |= asyh->or.nhsync; asyh 26 drivers/gpu/drm/nouveau/dispnv50/dac907d.c struct nv50_head_atom *asyh) asyh 358 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); asyh 367 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.bpc = connector->display_info.bpc; asyh 391 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); asyh 396 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); asyh 397 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.depth = 0; asyh 781 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); asyh 808 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.bpc = min(connector->display_info.bpc, 8U); asyh 809 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3); asyh 813 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.pbn); asyh 817 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->dp.tu = slots; asyh 1408 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh, u8 proto, u8 depth) asyh 1413 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!asyh) { asyh 1420 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->or.depth = depth; asyh 1423 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); asyh 1459 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); asyh 1460 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_display_mode *mode = &asyh->state.adjusted_mode; asyh 1527 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->or.bpc == 8) asyh 1534 drivers/gpu/drm/nouveau/dispnv50/disp.c depth = nv50_dp_bpc_to_depth(asyh->or.bpc); asyh 1548 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); asyh 1677 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); asyh 1685 drivers/gpu/drm/nouveau/dispnv50/disp.c switch (asyh->or.bpc) { asyh 1686 drivers/gpu/drm/nouveau/dispnv50/disp.c case 10: asyh->or.depth = 0x6; break; asyh 1687 drivers/gpu/drm/nouveau/dispnv50/disp.c case 8: asyh->or.depth = 0x5; break; asyh 1688 drivers/gpu/drm/nouveau/dispnv50/disp.c case 6: asyh->or.depth = 0x2; break; asyh 1689 drivers/gpu/drm/nouveau/dispnv50/disp.c default: asyh->or.depth = 0x0; break; asyh 1702 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); asyh 1849 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); asyh 1853 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->clr.mask, asyh->set.mask); asyh 1860 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->clr.mask) { asyh 1861 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_head_flush_clr(head, asyh, atom->flush_disable); asyh 1932 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); asyh 1936 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->set.mask, asyh->clr.mask); asyh 1938 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->set.mask) { asyh 1939 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_head_flush_set(head, asyh); asyh 35 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh, bool flush) asyh 38 drivers/gpu/drm/nouveau/dispnv50/head.c .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), asyh 46 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 48 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.view ) head->func->view (head, asyh); asyh 49 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.mode ) head->func->mode (head, asyh); asyh 50 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.core ) head->func->core_set(head, asyh); asyh 51 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.olut ) { asyh 52 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.offset = nv50_lut_load(&head->olut, asyh 53 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.buffer, asyh 54 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->state.gamma_lut, asyh 55 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.load); asyh 56 drivers/gpu/drm/nouveau/dispnv50/head.c head->func->olut_set(head, asyh); asyh 58 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.curs ) head->func->curs_set(head, asyh); asyh 59 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.base ) head->func->base (head, asyh); asyh 60 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.ovly ) head->func->ovly (head, asyh); asyh 61 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.dither ) head->func->dither (head, asyh); asyh 62 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.procamp) head->func->procamp (head, asyh); asyh 63 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.or ) head->func->or (head, asyh); asyh 68 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh, asyh 74 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; asyh 75 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; asyh 76 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.procamp = true; asyh 81 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh, asyh 87 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->base.depth > asyh->or.bpc * 3) asyh 94 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->or.bpc >= 8) asyh 100 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->dither.enable = mode; asyh 101 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->dither.bits = mode >> 1; asyh 102 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->dither.mode = mode >> 3; asyh 103 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.dither = true; asyh 108 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh, asyh 112 drivers/gpu/drm/nouveau/dispnv50/head.c struct drm_display_mode *omode = &asyh->state.adjusted_mode; asyh 113 drivers/gpu/drm/nouveau/dispnv50/head.c struct drm_display_mode *umode = &asyh->state.mode; asyh 137 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.iW = umode->hdisplay; asyh 138 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.iH = umode_vdisplay; asyh 141 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oW = omode_hdisplay; asyh 142 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oH = omode_vdisplay; asyh 153 drivers/gpu/drm/nouveau/dispnv50/head.c u32 r = (asyh->view.oH << 19) / asyh->view.oW; asyh 156 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oW -= (bX * 2); asyh 157 drivers/gpu/drm/nouveau/dispnv50/head.c if (bY) asyh->view.oH -= (bY * 2); asyh 158 drivers/gpu/drm/nouveau/dispnv50/head.c else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; asyh 160 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oW -= (asyh->view.oW >> 4) + 32; asyh 161 drivers/gpu/drm/nouveau/dispnv50/head.c if (bY) asyh->view.oH -= (bY * 2); asyh 162 drivers/gpu/drm/nouveau/dispnv50/head.c else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; asyh 174 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oW = min(asyh->view.iW, asyh->view.oW); asyh 175 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oH = min(asyh->view.iH, asyh->view.oH); asyh 193 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) { asyh 195 drivers/gpu/drm/nouveau/dispnv50/head.c u32 r = (asyh->view.iW << 19) / asyh->view.iH; asyh 196 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; asyh 199 drivers/gpu/drm/nouveau/dispnv50/head.c u32 r = (asyh->view.iH << 19) / asyh->view.iW; asyh 200 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; asyh 207 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.view = true; asyh 212 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh) asyh 215 drivers/gpu/drm/nouveau/dispnv50/head.c struct drm_property_blob *olut = asyh->state.gamma_lut; asyh 222 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->wndw.olut) { asyh 226 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->wndw.olut != asyh->wndw.mask) asyh 233 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.handle = 0; asyh 237 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.handle = disp->core->chan.vram.handle; asyh 238 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.buffer = !asyh->olut.buffer; asyh 239 drivers/gpu/drm/nouveau/dispnv50/head.c head->func->olut(head, asyh); asyh 244 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 246 drivers/gpu/drm/nouveau/dispnv50/head.c struct drm_display_mode *mode = &asyh->state.adjusted_mode; asyh 247 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_mode *m = &asyh->mode; asyh 287 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); asyh 288 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); asyh 289 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.or = head->func->or != NULL; asyh 290 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.mode = true; asyh 299 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh = nv50_head_atom(state); asyh 305 drivers/gpu/drm/nouveau/dispnv50/head.c NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); asyh 306 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->state.active) { asyh 307 drivers/gpu/drm/nouveau/dispnv50/head.c for_each_new_connector_in_state(asyh->state.state, conn, conns, i) { asyh 316 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->state.mode_changed) asyh 318 drivers/gpu/drm/nouveau/dispnv50/head.c if (armh->base.depth != asyh->base.depth) asyh 324 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.mask = ~0; asyh 325 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.or = head->func->or != NULL; asyh 328 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->state.mode_changed || asyh->state.connectors_changed) asyh 329 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_atomic_check_mode(head, asyh); asyh 331 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->state.color_mgmt_changed || asyh 332 drivers/gpu/drm/nouveau/dispnv50/head.c memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) { asyh 333 drivers/gpu/drm/nouveau/dispnv50/head.c int ret = nv50_head_atomic_check_lut(head, asyh); asyh 337 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.visible = asyh->olut.handle != 0; asyh 342 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_atomic_check_view(armh, asyh, asyc); asyh 344 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_atomic_check_dither(armh, asyh, asyc); asyh 346 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_head_atomic_check_procamp(armh, asyh, asyc); asyh 350 drivers/gpu/drm/nouveau/dispnv50/head.c head->func->core_calc(head, asyh); asyh 351 drivers/gpu/drm/nouveau/dispnv50/head.c if (!asyh->core.visible) asyh 352 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.visible = false; asyh 355 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.base = armh->base.cpp != asyh->base.cpp; asyh 356 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; asyh 358 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut.visible = false; asyh 359 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->core.visible = false; asyh 360 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->curs.visible = false; asyh 361 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->base.cpp = 0; asyh 362 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->ovly.cpp = 0; asyh 365 drivers/gpu/drm/nouveau/dispnv50/head.c if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { asyh 366 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->core.visible) { asyh 367 drivers/gpu/drm/nouveau/dispnv50/head.c if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) asyh 368 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.core = true; asyh 371 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.core = true; asyh 374 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->curs.visible) { asyh 375 drivers/gpu/drm/nouveau/dispnv50/head.c if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) asyh 376 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.curs = true; asyh 379 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.curs = true; asyh 382 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->olut.visible) { asyh 383 drivers/gpu/drm/nouveau/dispnv50/head.c if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut))) asyh 384 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.olut = true; asyh 387 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.olut = true; asyh 390 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.olut = armh->olut.visible; asyh 391 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.core = armh->core.visible; asyh 392 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.curs = armh->curs.visible; asyh 393 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.olut = asyh->olut.visible; asyh 394 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.core = asyh->core.visible; asyh 395 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.curs = asyh->curs.visible; asyh 398 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->clr.mask || asyh->set.mask) asyh 399 drivers/gpu/drm/nouveau/dispnv50/head.c nv50_atom(asyh->state.state)->lock_core = true; asyh 412 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh = nv50_head_atom(state); asyh 413 drivers/gpu/drm/nouveau/dispnv50/head.c __drm_atomic_helper_crtc_destroy_state(&asyh->state); asyh 414 drivers/gpu/drm/nouveau/dispnv50/head.c kfree(asyh); asyh 421 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh; asyh 422 drivers/gpu/drm/nouveau/dispnv50/head.c if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) asyh 424 drivers/gpu/drm/nouveau/dispnv50/head.c __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); asyh 425 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->wndw = armh->wndw; asyh 426 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->view = armh->view; asyh 427 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->mode = armh->mode; asyh 428 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->olut = armh->olut; asyh 429 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->core = armh->core; asyh 430 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->curs = armh->curs; asyh 431 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->base = armh->base; asyh 432 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->ovly = armh->ovly; asyh 433 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->dither = armh->dither; asyh 434 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->procamp = armh->procamp; asyh 435 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->or = armh->or; asyh 436 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->dp = armh->dp; asyh 437 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.mask = 0; asyh 438 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.mask = 0; asyh 439 drivers/gpu/drm/nouveau/dispnv50/head.c return &asyh->state; asyh 445 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_head_atom *asyh; asyh 447 drivers/gpu/drm/nouveau/dispnv50/head.c if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) asyh 453 drivers/gpu/drm/nouveau/dispnv50/head.c __drm_atomic_helper_crtc_reset(crtc, &asyh->state); asyh 26 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 32 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->procamp.sat.sin << 20 | asyh 33 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->procamp.sat.cos << 8); asyh 39 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 45 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->dither.mode << 3 | asyh 46 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->dither.bits << 1 | asyh 47 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->dither.enable); asyh 53 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 59 drivers/gpu/drm/nouveau/dispnv50/head507d.c if (asyh->ovly.cpp) { asyh 60 drivers/gpu/drm/nouveau/dispnv50/head507d.c switch (asyh->ovly.cpp) { asyh 80 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 86 drivers/gpu/drm/nouveau/dispnv50/head507d.c if (asyh->base.cpp) { asyh 87 drivers/gpu/drm/nouveau/dispnv50/head507d.c switch (asyh->base.cpp) { asyh 119 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 125 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, 0x80000000 | asyh->curs.layout << 26 | asyh 126 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->curs.format << 24); asyh 127 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->curs.offset >> 8); asyh 134 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_head_atom *asyh) asyh 137 drivers/gpu/drm/nouveau/dispnv50/head507d.c case 0xcf: asyh->curs.format = 1; break; asyh 147 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_head_atom *asyh) asyh 150 drivers/gpu/drm/nouveau/dispnv50/head507d.c case 32: asyh->curs.layout = 0; break; asyh 151 drivers/gpu/drm/nouveau/dispnv50/head507d.c case 64: asyh->curs.layout = 1; break; asyh 171 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 177 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.offset >> 8); asyh 179 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.h << 16 | asyh->core.w); asyh 180 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.layout << 20 | asyh 181 drivers/gpu/drm/nouveau/dispnv50/head507d.c (asyh->core.pitch >> 8) << 8 | asyh 182 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.blocks << 8 | asyh 183 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.blockh); asyh 184 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.kind << 16 | asyh 185 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.format << 8); asyh 186 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.handle); asyh 188 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->core.y << 16 | asyh->core.x); asyh 195 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->set.curs = asyh->curs.visible; asyh 196 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->set.olut = asyh->olut.handle != 0; asyh 201 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_core_calc(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 204 drivers/gpu/drm/nouveau/dispnv50/head507d.c if ((asyh->core.visible = (asyh->base.cpp != 0))) { asyh 205 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.x = asyh->base.x; asyh 206 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.y = asyh->base.y; asyh 207 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.w = asyh->base.w; asyh 208 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.h = asyh->base.h; asyh 210 drivers/gpu/drm/nouveau/dispnv50/head507d.c if ((asyh->core.visible = (asyh->ovly.cpp != 0)) || asyh 211 drivers/gpu/drm/nouveau/dispnv50/head507d.c (asyh->core.visible = asyh->curs.visible)) { asyh 217 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.x = 0; asyh 218 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.y = 0; asyh 219 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.w = asyh->state.mode.hdisplay; asyh 220 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.h = asyh->state.mode.vdisplay; asyh 222 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.handle = disp->core->chan.vram.handle; asyh 223 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.offset = 0; asyh 224 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.format = 0xcf; asyh 225 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.kind = 0; asyh 226 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.layout = 1; asyh 227 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.blockh = 0; asyh 228 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.blocks = 0; asyh 229 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; asyh 245 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 251 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, 0x80000000 | asyh->olut.mode << 30); asyh 252 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->olut.offset >> 8); asyh 275 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 277 drivers/gpu/drm/nouveau/dispnv50/head507d.c if (asyh->base.cpp == 1) asyh 278 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->olut.mode = 0; asyh 280 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->olut.mode = 1; asyh 282 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->olut.load = head507d_olut_load; asyh 286 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 289 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_head_mode *m = &asyh->mode; asyh 302 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->mode.v.blankus); asyh 310 drivers/gpu/drm/nouveau/dispnv50/head507d.c head507d_view(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 318 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->view.iH << 16 | asyh->view.iW); asyh 320 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->view.oH << 16 | asyh->view.oW); asyh 321 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_data(push, asyh->view.oH << 16 | asyh->view.oW); asyh 40 drivers/gpu/drm/nouveau/dispnv50/head827d.c head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 46 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, 0x80000000 | asyh->curs.layout << 26 | asyh 47 drivers/gpu/drm/nouveau/dispnv50/head827d.c asyh->curs.format << 24); asyh 48 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->curs.offset >> 8); asyh 50 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->curs.handle); asyh 56 drivers/gpu/drm/nouveau/dispnv50/head827d.c head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 62 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.offset >> 8); asyh 64 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.h << 16 | asyh->core.w); asyh 65 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.layout << 20 | asyh 66 drivers/gpu/drm/nouveau/dispnv50/head827d.c (asyh->core.pitch >> 8) << 8 | asyh 67 drivers/gpu/drm/nouveau/dispnv50/head827d.c asyh->core.blocks << 8 | asyh 68 drivers/gpu/drm/nouveau/dispnv50/head827d.c asyh->core.blockh); asyh 69 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.format << 8); asyh 70 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.handle); asyh 72 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->core.y << 16 | asyh->core.x); asyh 92 drivers/gpu/drm/nouveau/dispnv50/head827d.c head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 98 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, 0x80000000 | asyh->olut.mode << 30); asyh 99 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->olut.offset >> 8); asyh 101 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_data(push, asyh->olut.handle); asyh 26 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 32 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, 0x00000001 | asyh->or.depth << 6 | asyh 33 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->or.nvsync << 4 | asyh 34 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->or.nhsync << 3); asyh 36 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->mode.interlace); asyh 42 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 48 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->procamp.sat.sin << 20 | asyh 49 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->procamp.sat.cos << 8); asyh 55 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 61 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->dither.mode << 3 | asyh 62 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->dither.bits << 1 | asyh 63 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->dither.enable); asyh 69 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 75 drivers/gpu/drm/nouveau/dispnv50/head907d.c if (asyh->ovly.cpp) { asyh 76 drivers/gpu/drm/nouveau/dispnv50/head907d.c switch (asyh->ovly.cpp) { asyh 97 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 103 drivers/gpu/drm/nouveau/dispnv50/head907d.c if (asyh->base.cpp) { asyh 104 drivers/gpu/drm/nouveau/dispnv50/head907d.c switch (asyh->base.cpp) { asyh 138 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 144 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, 0x80000000 | asyh->curs.layout << 26 | asyh 145 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->curs.format << 24); asyh 146 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->curs.offset >> 8); asyh 148 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->curs.handle); asyh 166 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 172 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.offset >> 8); asyh 174 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.h << 16 | asyh->core.w); asyh 175 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.layout << 24 | asyh 176 drivers/gpu/drm/nouveau/dispnv50/head907d.c (asyh->core.pitch >> 8) << 8 | asyh 177 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->core.blocks << 8 | asyh 178 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->core.blockh); asyh 179 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.format << 8); asyh 180 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.handle); asyh 182 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->core.y << 16 | asyh->core.x); asyh 202 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 208 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, 0x80000000 | asyh->olut.mode << 24); asyh 209 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->olut.offset >> 8); asyh 211 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->olut.handle); asyh 234 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 236 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->olut.mode = 7; asyh 237 drivers/gpu/drm/nouveau/dispnv50/head907d.c asyh->olut.load = head907d_olut_load; asyh 241 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 244 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_head_mode *m = &asyh->mode; asyh 266 drivers/gpu/drm/nouveau/dispnv50/head907d.c head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 274 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->view.iH << 16 | asyh->view.iW); asyh 276 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->view.oH << 16 | asyh->view.oW); asyh 277 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->view.oH << 16 | asyh->view.oW); asyh 278 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, asyh->view.oH << 16 | asyh->view.oW); asyh 26 drivers/gpu/drm/nouveau/dispnv50/head917d.c head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 32 drivers/gpu/drm/nouveau/dispnv50/head917d.c evo_data(push, asyh->dither.mode << 3 | asyh 33 drivers/gpu/drm/nouveau/dispnv50/head917d.c asyh->dither.bits << 1 | asyh 34 drivers/gpu/drm/nouveau/dispnv50/head917d.c asyh->dither.enable); asyh 40 drivers/gpu/drm/nouveau/dispnv50/head917d.c head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 46 drivers/gpu/drm/nouveau/dispnv50/head917d.c if (asyh->base.cpp) { asyh 47 drivers/gpu/drm/nouveau/dispnv50/head917d.c switch (asyh->base.cpp) { asyh 68 drivers/gpu/drm/nouveau/dispnv50/head917d.c struct nv50_head_atom *asyh) asyh 71 drivers/gpu/drm/nouveau/dispnv50/head917d.c case 32: asyh->curs.layout = 0; break; asyh 72 drivers/gpu/drm/nouveau/dispnv50/head917d.c case 64: asyh->curs.layout = 1; break; asyh 73 drivers/gpu/drm/nouveau/dispnv50/head917d.c case 128: asyh->curs.layout = 2; break; asyh 74 drivers/gpu/drm/nouveau/dispnv50/head917d.c case 256: asyh->curs.layout = 3; break; asyh 27 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 35 drivers/gpu/drm/nouveau/dispnv50/headc37d.c switch (asyh->or.depth) { asyh 36 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 6: asyh->or.depth = 5; break; asyh 37 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 5: asyh->or.depth = 4; break; asyh 38 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 2: asyh->or.depth = 1; break; asyh 39 drivers/gpu/drm/nouveau/dispnv50/headc37d.c case 0: asyh->or.depth = 4; break; asyh 47 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.depth << 4 | asyh 48 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.nvsync << 3 | asyh 49 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->or.nhsync << 2); asyh 55 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 62 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->procamp.sat.sin << 16 | asyh 63 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->procamp.sat.cos << 4); asyh 69 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 75 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->dither.mode << 8 | asyh 76 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->dither.bits << 4 | asyh 77 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->dither.enable); asyh 97 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 104 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->curs.layout << 8 | asyh 105 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->curs.format << 0); asyh 108 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->curs.handle); asyh 110 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->curs.offset >> 8); asyh 117 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_head_atom *asyh) asyh 119 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->curs.format = asyw->image.format; asyh 136 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 142 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->olut.output_mode << 8 | asyh 143 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.range << 4 | asyh 144 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.size); asyh 145 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->olut.offset >> 8); asyh 146 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, asyh->olut.handle); asyh 152 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 154 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.mode = 2; asyh 155 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.size = 0; asyh 156 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.range = 0; asyh 157 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.output_mode = 1; asyh 158 drivers/gpu/drm/nouveau/dispnv50/headc37d.c asyh->olut.load = head907d_olut_load; asyh 162 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 165 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_head_mode *m = &asyh->mode; asyh 186 drivers/gpu/drm/nouveau/dispnv50/headc37d.c headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 192 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); asyh 194 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); asyh 27 drivers/gpu/drm/nouveau/dispnv50/headc57d.c headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 35 drivers/gpu/drm/nouveau/dispnv50/headc57d.c switch (asyh->or.depth) { asyh 36 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 6: asyh->or.depth = 5; break; asyh 37 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 5: asyh->or.depth = 4; break; asyh 38 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 2: asyh->or.depth = 1; break; asyh 39 drivers/gpu/drm/nouveau/dispnv50/headc57d.c case 0: asyh->or.depth = 4; break; asyh 47 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.depth << 4 | asyh 48 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.nvsync << 3 | asyh 49 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->or.nhsync << 2); asyh 55 drivers/gpu/drm/nouveau/dispnv50/headc57d.c headc57d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 63 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->procamp.sat.sin << 16 | asyh 64 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->procamp.sat.cos << 4); asyh 85 drivers/gpu/drm/nouveau/dispnv50/headc57d.c headc57d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 91 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_data(push, asyh->olut.size << 8 | asyh 92 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.mode << 2 | asyh 93 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.output_mode); asyh 95 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_data(push, asyh->olut.handle); asyh 96 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_data(push, asyh->olut.offset >> 8); asyh 155 drivers/gpu/drm/nouveau/dispnv50/headc57d.c headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 157 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.mode = 2; /* DIRECT10 */ asyh 158 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.size = 4 /* VSS header. */ + 1024 + 1 /* Entries. */; asyh 159 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.output_mode = 1; /* INTERPOLATE_ENABLE. */ asyh 160 drivers/gpu/drm/nouveau/dispnv50/headc57d.c if (asyh->state.gamma_lut && asyh 161 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->state.gamma_lut->length / sizeof(struct drm_color_lut) == 256) asyh 162 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.load = headc57d_olut_load_8; asyh 164 drivers/gpu/drm/nouveau/dispnv50/headc57d.c asyh->olut.load = headc57d_olut_load; asyh 168 drivers/gpu/drm/nouveau/dispnv50/headc57d.c headc57d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) asyh 171 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_head_mode *m = &asyh->mode; asyh 120 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nv50_head_atom *asyh) asyh 122 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c asyh->ovly.cpp = 0; asyh 127 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c struct nv50_head_atom *asyh) asyh 132 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, asyh 139 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c asyh->ovly.cpp = fb->format->cpp[0]; asyh 26 drivers/gpu/drm/nouveau/dispnv50/pior507d.c struct nv50_head_atom *asyh) asyh 30 drivers/gpu/drm/nouveau/dispnv50/pior507d.c if (asyh) { asyh 31 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.depth << 16; asyh 32 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.nvsync << 13; asyh 33 drivers/gpu/drm/nouveau/dispnv50/pior507d.c ctrl |= asyh->or.nhsync << 12; asyh 26 drivers/gpu/drm/nouveau/dispnv50/sor507d.c struct nv50_head_atom *asyh) asyh 30 drivers/gpu/drm/nouveau/dispnv50/sor507d.c if (asyh) { asyh 31 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.depth << 16; asyh 32 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.nvsync << 13; asyh 33 drivers/gpu/drm/nouveau/dispnv50/sor507d.c ctrl |= asyh->or.nhsync << 12; asyh 28 drivers/gpu/drm/nouveau/dispnv50/sor907d.c struct nv50_head_atom *asyh) asyh 26 drivers/gpu/drm/nouveau/dispnv50/sorc37d.c struct nv50_head_atom *asyh) asyh 183 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_head_atom *asyh) asyh 187 drivers/gpu/drm/nouveau/dispnv50/wndw.c wndw->func->release(wndw, asyw, asyh); asyh 235 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_head_atom *asyh) asyh 270 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (!asyh->state.async_flip) asyh 318 drivers/gpu/drm/nouveau/dispnv50/wndw.c return wndw->func->acquire(wndw, asyw, asyh); asyh 325 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_head_atom *asyh) asyh 327 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct drm_property_blob *ilut = asyh->state.degamma_lut; asyh 341 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (!(ilut = asyh->state.gamma_lut)) { asyh 347 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.olut |= BIT(wndw->id); asyh 349 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.olut &= ~BIT(wndw->id); asyh 375 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (wndw->func->csc && asyh->state.ctm) { asyh 376 drivers/gpu/drm/nouveau/dispnv50/wndw.c const struct drm_color_ctm *ctm = asyh->state.ctm->data; asyh 386 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->state.async_flip = false; asyh 396 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_head_atom *harm = NULL, *asyh = NULL; asyh 406 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); asyh 407 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (IS_ERR(asyh)) asyh 408 drivers/gpu/drm/nouveau/dispnv50/wndw.c return PTR_ERR(asyh); asyh 409 drivers/gpu/drm/nouveau/dispnv50/wndw.c modeset = drm_atomic_crtc_needs_modeset(&asyh->state); asyh 410 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->visible = asyh->state.active; asyh 425 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->state.color_mgmt_changed || asyh 428 drivers/gpu/drm/nouveau/dispnv50/wndw.c nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); asyh 433 drivers/gpu/drm/nouveau/dispnv50/wndw.c armw, asyw, asyh); asyh 437 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.mask |= BIT(wndw->id); asyh 484 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv50_head_atom *asyh; asyh 510 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); asyh 511 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (IS_ERR(asyh)) asyh 512 drivers/gpu/drm/nouveau/dispnv50/wndw.c return PTR_ERR(asyh); asyh 514 drivers/gpu/drm/nouveau/dispnv50/wndw.c wndw->func->prepare(wndw, asyh, asyw); asyh 54 drivers/gpu/drm/nouveau/dispnv50/wndw.h struct nv50_head_atom *asyh); asyh 56 drivers/gpu/drm/nouveau/dispnv50/wndw.h struct nv50_head_atom *asyh); asyh 57 drivers/gpu/drm/nouveau/dispnv50/wndw.h void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh, asyh 218 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c struct nv50_head_atom *asyh) asyh 224 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c struct nv50_head_atom *asyh) asyh 226 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c return drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,