asy 36 drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c const u32 coff = (state == &dac->asy) * 0x20000 + dac->id * 0x20; asy 256 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.link = ior->asy.link; asy 297 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.link = dp->outp.ior->asy.link; asy 309 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.link = dp->outp.ior->asy.link; asy 315 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.link = dp->outp.ior->asy.link; asy 323 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c init.link = dp->outp.ior->asy.link; asy 462 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (ior->asy.head & (1 << head->id)) { asy 463 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000; asy 464 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c datakbps += khz * head->asy.or.depth; asy 28 drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h } arm, asy; asy 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c const u32 hoff = (state == &head->asy) * 0x20000 + head->id * 0x300; asy 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h } arm, asy; asy 113 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h return nv50_ior_base(ior) + ((ior->asy.link == 2) * 0x80); asy 202 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_outp *outp = ior->asy.outp; asy 220 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (ior->asy.proto == LVDS) { asy 221 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (head->asy.or.depth == 24) asy 224 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (ior->asy.link == 3) asy 228 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c data = nvbios_ocfg_match(bios, data, ior->asy.proto_evo, flags, asy 232 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ior->asy.proto_evo, flags); asy 240 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c id, ior->asy.proto_evo, flags, khz); asy 247 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c init.link = ior->asy.link; asy 282 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (ior->asy.head & (1 << head->id)) { asy 317 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_super_ied_on(head, ior, 1, head->asy.hz / 1000); asy 328 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c const u32 khz = head->asy.hz / 1000; asy 338 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c h = head->asy.hblanke + head->asy.htotal - head->asy.hblanks - 7; asy 344 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c v = head->asy.vblanks - head->asy.vblanke - 25; asy 352 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr; asy 433 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c const u32 khz = head->asy.hz / 1000; asy 452 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (ior->type == SOR && ior->asy.proto == LVDS) { asy 453 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18; asy 454 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ior->asy.link = (disp->sor.lvdsconf & 0x0100) ? 3 : 1; asy 458 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if ((outp = ior->asy.outp) && outp->func->acquire) asy 465 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->func->rgclk(head, ior->asy.rgdiv); asy 468 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (ior->type == SOR && ior->asy.proto == DP) asy 481 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c const u32 khz = head->asy.hz / 1000; asy 534 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c head->func->state(head, &head->asy); asy 539 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ior->func->state(ior, &ior->asy); asy 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c if ((outp = ior->arm.outp) && ior->arm.outp != ior->asy.outp) { asy 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c if ((outp = ior->asy.outp)) { asy 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c if (ior->asy.outp != ior->arm.outp) { asy 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c ior->arm.outp = ior->asy.outp; asy 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c outp->ior->asy.outp = NULL; asy 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c outp->ior->asy.outp = outp; asy 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c outp->ior->asy.link = outp->info.sorconf.link; asy 144 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c if (!ior->identity && !ior->asy.outp && ior->arm.outp == outp) asy 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c !ior->asy.outp && ior->type == type && !ior->arm.outp && asy 160 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c if (!ior->identity && !ior->asy.outp && ior->type == type && asy 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c if (state->head && state == &ior->asy) { asy 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_head_state *state = &head->asy; asy 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c args->v0.link = outp->ior->asy.link; asy 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c if (sor->asy.proto == TMDS) { asy 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 div1 = sor->asy.link == 3; asy 125 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c u32 div2 = sor->asy.link == 3; asy 126 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c if (sor->asy.proto == TMDS) { asy 139 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20; asy 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c if (sor->asy.link & 1) asy 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c u32 link = ior ? (ior->asy.link == 2) : 0; asy 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c const int div = sor->asy.link == 3;