ast                13 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast                15 drivers/gpu/drm/ast/ast_dp501.c 	return request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
ast                18 drivers/gpu/drm/ast/ast_dp501.c static void send_ack(struct ast_private *ast)
ast                21 drivers/gpu/drm/ast/ast_dp501.c 	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
ast                23 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
ast                26 drivers/gpu/drm/ast/ast_dp501.c static void send_nack(struct ast_private *ast)
ast                29 drivers/gpu/drm/ast/ast_dp501.c 	sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
ast                31 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
ast                34 drivers/gpu/drm/ast/ast_dp501.c static bool wait_ack(struct ast_private *ast)
ast                39 drivers/gpu/drm/ast/ast_dp501.c 		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
ast                50 drivers/gpu/drm/ast/ast_dp501.c static bool wait_nack(struct ast_private *ast)
ast                55 drivers/gpu/drm/ast/ast_dp501.c 		waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
ast                66 drivers/gpu/drm/ast/ast_dp501.c static void set_cmd_trigger(struct ast_private *ast)
ast                68 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
ast                71 drivers/gpu/drm/ast/ast_dp501.c static void clear_cmd_trigger(struct ast_private *ast)
ast                73 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
ast                77 drivers/gpu/drm/ast/ast_dp501.c static bool wait_fw_ready(struct ast_private *ast)
ast                82 drivers/gpu/drm/ast/ast_dp501.c 		waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
ast                96 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast                98 drivers/gpu/drm/ast/ast_dp501.c 	if (wait_nack(ast)) {
ast                99 drivers/gpu/drm/ast/ast_dp501.c 		send_nack(ast);
ast               100 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
ast               101 drivers/gpu/drm/ast/ast_dp501.c 		send_ack(ast);
ast               102 drivers/gpu/drm/ast/ast_dp501.c 		set_cmd_trigger(ast);
ast               104 drivers/gpu/drm/ast/ast_dp501.c 			if (wait_ack(ast)) {
ast               105 drivers/gpu/drm/ast/ast_dp501.c 				clear_cmd_trigger(ast);
ast               106 drivers/gpu/drm/ast/ast_dp501.c 				send_nack(ast);
ast               111 drivers/gpu/drm/ast/ast_dp501.c 	clear_cmd_trigger(ast);
ast               112 drivers/gpu/drm/ast/ast_dp501.c 	send_nack(ast);
ast               118 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               120 drivers/gpu/drm/ast/ast_dp501.c 	if (wait_nack(ast)) {
ast               121 drivers/gpu/drm/ast/ast_dp501.c 		send_nack(ast);
ast               122 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
ast               123 drivers/gpu/drm/ast/ast_dp501.c 		send_ack(ast);
ast               124 drivers/gpu/drm/ast/ast_dp501.c 		if (wait_ack(ast)) {
ast               125 drivers/gpu/drm/ast/ast_dp501.c 			send_nack(ast);
ast               129 drivers/gpu/drm/ast/ast_dp501.c 	send_nack(ast);
ast               136 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               141 drivers/gpu/drm/ast/ast_dp501.c 	if (wait_ack(ast) == false)
ast               143 drivers/gpu/drm/ast/ast_dp501.c 	tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
ast               145 drivers/gpu/drm/ast/ast_dp501.c 	if (wait_nack(ast) == false) {
ast               146 drivers/gpu/drm/ast/ast_dp501.c 		send_nack(ast);
ast               149 drivers/gpu/drm/ast/ast_dp501.c 	send_nack(ast);
ast               153 drivers/gpu/drm/ast/ast_dp501.c static void clear_cmd(struct ast_private *ast)
ast               155 drivers/gpu/drm/ast/ast_dp501.c 	send_nack(ast);
ast               156 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
ast               168 drivers/gpu/drm/ast/ast_dp501.c static u32 get_fw_base(struct ast_private *ast)
ast               170 drivers/gpu/drm/ast/ast_dp501.c 	return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
ast               175 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               179 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
ast               181 drivers/gpu/drm/ast/ast_dp501.c 		boot_address = get_fw_base(ast);
ast               183 drivers/gpu/drm/ast/ast_dp501.c 			*(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
ast               191 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               197 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
ast               200 drivers/gpu/drm/ast/ast_dp501.c 		if (ast->dp501_fw_addr) {
ast               201 drivers/gpu/drm/ast/ast_dp501.c 			fw_addr = ast->dp501_fw_addr;
ast               204 drivers/gpu/drm/ast/ast_dp501.c 			if (!ast->dp501_fw &&
ast               208 drivers/gpu/drm/ast/ast_dp501.c 			fw_addr = (u8 *)ast->dp501_fw->data;
ast               209 drivers/gpu/drm/ast/ast_dp501.c 			len = ast->dp501_fw->size;
ast               212 drivers/gpu/drm/ast/ast_dp501.c 		ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
ast               213 drivers/gpu/drm/ast/ast_dp501.c 		data = ast_mindwm(ast, 0x1e6e0004);
ast               234 drivers/gpu/drm/ast/ast_dp501.c 			ast_moutdwm(ast, boot_address + i, data);
ast               238 drivers/gpu/drm/ast/ast_dp501.c 		ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
ast               241 drivers/gpu/drm/ast/ast_dp501.c 		ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
ast               242 drivers/gpu/drm/ast/ast_dp501.c 		ast_moutdwm(ast, 0x1e6e2100, 1);
ast               245 drivers/gpu/drm/ast/ast_dp501.c 		data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff;		/* D[11:9] = 100b: UEFI handling */
ast               247 drivers/gpu/drm/ast/ast_dp501.c 		ast_moutdwm(ast, 0x1e6e2040, data);
ast               249 drivers/gpu/drm/ast/ast_dp501.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
ast               251 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
ast               258 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               262 drivers/gpu/drm/ast/ast_dp501.c 	boot_address = get_fw_base(ast);
ast               266 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_mindwm(ast, boot_address + offset);
ast               272 drivers/gpu/drm/ast/ast_dp501.c 	*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
ast               286 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               289 drivers/gpu/drm/ast/ast_dp501.c 	boot_address = get_fw_base(ast);
ast               293 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_mindwm(ast, boot_address + offset);
ast               299 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_mindwm(ast, boot_address + offset);
ast               306 drivers/gpu/drm/ast/ast_dp501.c 		data = ast_mindwm(ast, boot_address + offset + i);
ast               315 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               318 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0xf004, 0x1e6e0000);
ast               319 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0xf000, 0x1);
ast               320 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0x12000, 0x1688a8a8);
ast               322 drivers/gpu/drm/ast/ast_dp501.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast               325 drivers/gpu/drm/ast/ast_dp501.c 		data = ast_read32(ast, 0x12008);
ast               329 drivers/gpu/drm/ast/ast_dp501.c 		ast_write32(ast, 0x12008, data);
ast               331 drivers/gpu/drm/ast/ast_dp501.c 		if (ast->chip == AST2300) {
ast               332 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x12084);
ast               335 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x12084, data);
ast               337 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x12088);
ast               340 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x12088, data);
ast               342 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x12090);
ast               346 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x12090, data);
ast               348 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x12088);
ast               351 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x12088, data);
ast               353 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x1208c);
ast               356 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x1208c, data);
ast               358 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x120a4);
ast               361 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x120a4, data);
ast               363 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x120a8);
ast               366 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x120a8, data);
ast               368 drivers/gpu/drm/ast/ast_dp501.c 			data = ast_read32(ast, 0x12094);
ast               371 drivers/gpu/drm/ast/ast_dp501.c 			ast_write32(ast, 0x12094, data);
ast               376 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_read32(ast, 0x1202c);
ast               378 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0x1202c, data);
ast               381 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
ast               388 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               396 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0xf004, 0x1e6e0000);
ast               397 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0xf000, 0x1);
ast               400 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0x12000, 0x1688a8a8);
ast               401 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0x12000, 0x1688a8a8);
ast               402 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0x12000, 0x1688a8a8);
ast               405 drivers/gpu/drm/ast/ast_dp501.c 	data = ast_read32(ast, 0x1202c);
ast               407 drivers/gpu/drm/ast/ast_dp501.c 	ast_write32(ast, 0, data);
ast               410 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
ast               415 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               418 drivers/gpu/drm/ast/ast_dp501.c 	if (ast->chip == AST2300 || ast->chip == AST2400) {
ast               419 drivers/gpu/drm/ast/ast_dp501.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
ast               431 drivers/gpu/drm/ast/ast_dp501.c 			if (ast->tx_chip_type == AST_TX_SIL164)
ast               441 drivers/gpu/drm/ast/ast_dp501.c 	struct ast_private *ast = dev->dev_private;
ast               443 drivers/gpu/drm/ast/ast_dp501.c 	release_firmware(ast->dp501_fw);
ast               444 drivers/gpu/drm/ast/ast_dp501.c 	ast->dp501_fw = NULL;
ast               135 drivers/gpu/drm/ast/ast_drv.h static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
ast               137 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->regs + reg); \
ast               146 drivers/gpu/drm/ast/ast_drv.h static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
ast               148 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->ioregs + reg); \
ast               157 drivers/gpu/drm/ast/ast_drv.h static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
ast               158 drivers/gpu/drm/ast/ast_drv.h 	iowrite##x(val, ast->regs + reg);\
ast               166 drivers/gpu/drm/ast/ast_drv.h static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
ast               167 drivers/gpu/drm/ast/ast_drv.h 	iowrite##x(val, ast->ioregs + reg);\
ast               174 drivers/gpu/drm/ast/ast_drv.h static inline void ast_set_index_reg(struct ast_private *ast,
ast               178 drivers/gpu/drm/ast/ast_drv.h 	ast_io_write16(ast, base, ((u16)val << 8) | index);
ast               181 drivers/gpu/drm/ast/ast_drv.h void ast_set_index_reg_mask(struct ast_private *ast,
ast               184 drivers/gpu/drm/ast/ast_drv.h uint8_t ast_get_index_reg(struct ast_private *ast,
ast               186 drivers/gpu/drm/ast/ast_drv.h uint8_t ast_get_index_reg_mask(struct ast_private *ast,
ast               189 drivers/gpu/drm/ast/ast_drv.h static inline void ast_open_key(struct ast_private *ast)
ast               191 drivers/gpu/drm/ast/ast_drv.h 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
ast               284 drivers/gpu/drm/ast/ast_drv.h int ast_mm_init(struct ast_private *ast);
ast               285 drivers/gpu/drm/ast/ast_drv.h void ast_mm_fini(struct ast_private *ast);
ast               296 drivers/gpu/drm/ast/ast_drv.h u32 ast_mindwm(struct ast_private *ast, u32 r);
ast               297 drivers/gpu/drm/ast/ast_drv.h void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
ast                40 drivers/gpu/drm/ast/ast_main.c void ast_set_index_reg_mask(struct ast_private *ast,
ast                45 drivers/gpu/drm/ast/ast_main.c 	ast_io_write8(ast, base, index);
ast                46 drivers/gpu/drm/ast/ast_main.c 	tmp = (ast_io_read8(ast, base + 1) & mask) | val;
ast                47 drivers/gpu/drm/ast/ast_main.c 	ast_set_index_reg(ast, base, index, tmp);
ast                50 drivers/gpu/drm/ast/ast_main.c uint8_t ast_get_index_reg(struct ast_private *ast,
ast                54 drivers/gpu/drm/ast/ast_main.c 	ast_io_write8(ast, base, index);
ast                55 drivers/gpu/drm/ast/ast_main.c 	ret = ast_io_read8(ast, base + 1);
ast                59 drivers/gpu/drm/ast/ast_main.c uint8_t ast_get_index_reg_mask(struct ast_private *ast,
ast                63 drivers/gpu/drm/ast/ast_main.c 	ast_io_write8(ast, base, index);
ast                64 drivers/gpu/drm/ast/ast_main.c 	ret = ast_io_read8(ast, base + 1) & mask;
ast                71 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast = dev->dev_private;
ast                75 drivers/gpu/drm/ast/ast_main.c 	ast->config_mode = ast_use_defaults;
ast                82 drivers/gpu/drm/ast/ast_main.c 		ast->config_mode = ast_use_dt;
ast                96 drivers/gpu/drm/ast/ast_main.c 	jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast                97 drivers/gpu/drm/ast/ast_main.c 	jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
ast               100 drivers/gpu/drm/ast/ast_main.c 		data = ast_read32(ast, 0xf004);
ast               103 drivers/gpu/drm/ast/ast_main.c 			ast->config_mode = ast_use_p2a;
ast               108 drivers/gpu/drm/ast/ast_main.c 			ast_write32(ast, 0xf004, 0x1e6e0000);
ast               109 drivers/gpu/drm/ast/ast_main.c 			ast_write32(ast, 0xf000, 0x1);
ast               110 drivers/gpu/drm/ast/ast_main.c 			*scu_rev = ast_read32(ast, 0x1207c);
ast               121 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast = dev->dev_private;
ast               139 drivers/gpu/drm/ast/ast_main.c 	ast_open_key(ast);
ast               147 drivers/gpu/drm/ast/ast_main.c 		ast->chip = AST1100;
ast               151 drivers/gpu/drm/ast/ast_main.c 			ast->chip = AST2500;
ast               154 drivers/gpu/drm/ast/ast_main.c 			ast->chip = AST2400;
ast               157 drivers/gpu/drm/ast/ast_main.c 			ast->chip = AST2300;
ast               162 drivers/gpu/drm/ast/ast_main.c 				ast->chip = AST1100;
ast               166 drivers/gpu/drm/ast/ast_main.c 				ast->chip = AST2200;
ast               170 drivers/gpu/drm/ast/ast_main.c 				ast->chip = AST2150;
ast               174 drivers/gpu/drm/ast/ast_main.c 				ast->chip = AST2100;
ast               178 drivers/gpu/drm/ast/ast_main.c 			ast->vga2_clone = false;
ast               180 drivers/gpu/drm/ast/ast_main.c 			ast->chip = AST2000;
ast               186 drivers/gpu/drm/ast/ast_main.c 	switch (ast->chip) {
ast               188 drivers/gpu/drm/ast/ast_main.c 		ast->support_wide_screen = true;
ast               191 drivers/gpu/drm/ast/ast_main.c 		ast->support_wide_screen = false;
ast               194 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast               196 drivers/gpu/drm/ast/ast_main.c 			ast->support_wide_screen = true;
ast               198 drivers/gpu/drm/ast/ast_main.c 			ast->support_wide_screen = true;
ast               200 drivers/gpu/drm/ast/ast_main.c 			ast->support_wide_screen = false;
ast               201 drivers/gpu/drm/ast/ast_main.c 			if (ast->chip == AST2300 &&
ast               203 drivers/gpu/drm/ast/ast_main.c 				ast->support_wide_screen = true;
ast               204 drivers/gpu/drm/ast/ast_main.c 			if (ast->chip == AST2400 &&
ast               206 drivers/gpu/drm/ast/ast_main.c 				ast->support_wide_screen = true;
ast               207 drivers/gpu/drm/ast/ast_main.c 			if (ast->chip == AST2500 &&
ast               209 drivers/gpu/drm/ast/ast_main.c 				ast->support_wide_screen = true;
ast               215 drivers/gpu/drm/ast/ast_main.c 	ast->tx_chip_type = AST_TX_NONE;
ast               226 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
ast               228 drivers/gpu/drm/ast/ast_main.c 			ast->tx_chip_type = AST_TX_SIL164;
ast               231 drivers/gpu/drm/ast/ast_main.c 	if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
ast               237 drivers/gpu/drm/ast/ast_main.c 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
ast               240 drivers/gpu/drm/ast/ast_main.c 			ast->tx_chip_type = AST_TX_SIL164;
ast               243 drivers/gpu/drm/ast/ast_main.c 			ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
ast               244 drivers/gpu/drm/ast/ast_main.c 			if (ast->dp501_fw_addr) {
ast               246 drivers/gpu/drm/ast/ast_main.c 				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
ast               247 drivers/gpu/drm/ast/ast_main.c 					kfree(ast->dp501_fw_addr);
ast               248 drivers/gpu/drm/ast/ast_main.c 					ast->dp501_fw_addr = NULL;
ast               253 drivers/gpu/drm/ast/ast_main.c 			ast->tx_chip_type = AST_TX_DP501;
ast               258 drivers/gpu/drm/ast/ast_main.c 	switch(ast->tx_chip_type) {
ast               274 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast = dev->dev_private;
ast               278 drivers/gpu/drm/ast/ast_main.c 	switch (ast->config_mode) {
ast               295 drivers/gpu/drm/ast/ast_main.c 		ast_write32(ast, 0xf004, 0x1e6e0000);
ast               296 drivers/gpu/drm/ast/ast_main.c 		ast_write32(ast, 0xf000, 0x1);
ast               297 drivers/gpu/drm/ast/ast_main.c 		mcr_cfg = ast_read32(ast, 0x10004);
ast               298 drivers/gpu/drm/ast/ast_main.c 		mcr_scu_mpll = ast_read32(ast, 0x10120);
ast               299 drivers/gpu/drm/ast/ast_main.c 		mcr_scu_strap = ast_read32(ast, 0x10170);
ast               303 drivers/gpu/drm/ast/ast_main.c 		ast->dram_bus_width = 16;
ast               304 drivers/gpu/drm/ast/ast_main.c 		ast->dram_type = AST_DRAM_1Gx16;
ast               305 drivers/gpu/drm/ast/ast_main.c 		if (ast->chip == AST2500)
ast               306 drivers/gpu/drm/ast/ast_main.c 			ast->mclk = 800;
ast               308 drivers/gpu/drm/ast/ast_main.c 			ast->mclk = 396;
ast               313 drivers/gpu/drm/ast/ast_main.c 		ast->dram_bus_width = 16;
ast               315 drivers/gpu/drm/ast/ast_main.c 		ast->dram_bus_width = 32;
ast               317 drivers/gpu/drm/ast/ast_main.c 	if (ast->chip == AST2500) {
ast               320 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_1Gx16;
ast               324 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_2Gx16;
ast               327 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_4Gx16;
ast               330 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_8Gx16;
ast               333 drivers/gpu/drm/ast/ast_main.c 	} else if (ast->chip == AST2300 || ast->chip == AST2400) {
ast               336 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_512Mx16;
ast               340 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_1Gx16;
ast               343 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_2Gx16;
ast               346 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_4Gx16;
ast               353 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_512Mx16;
ast               357 drivers/gpu/drm/ast/ast_main.c 				ast->dram_type = AST_DRAM_1Gx16;
ast               359 drivers/gpu/drm/ast/ast_main.c 				ast->dram_type = AST_DRAM_512Mx32;
ast               362 drivers/gpu/drm/ast/ast_main.c 			ast->dram_type = AST_DRAM_1Gx32;
ast               387 drivers/gpu/drm/ast/ast_main.c 	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
ast               397 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast = dev->dev_private;
ast               400 drivers/gpu/drm/ast/ast_main.c 	ast_open_key(ast);
ast               403 drivers/gpu/drm/ast/ast_main.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
ast               411 drivers/gpu/drm/ast/ast_main.c 	jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
ast               429 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast;
ast               433 drivers/gpu/drm/ast/ast_main.c 	ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
ast               434 drivers/gpu/drm/ast/ast_main.c 	if (!ast)
ast               437 drivers/gpu/drm/ast/ast_main.c 	dev->dev_private = ast;
ast               438 drivers/gpu/drm/ast/ast_main.c 	ast->dev = dev;
ast               440 drivers/gpu/drm/ast/ast_main.c 	ast->regs = pci_iomap(dev->pdev, 1, 0);
ast               441 drivers/gpu/drm/ast/ast_main.c 	if (!ast->regs) {
ast               453 drivers/gpu/drm/ast/ast_main.c 		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
ast               457 drivers/gpu/drm/ast/ast_main.c 	if (!ast->ioregs) {
ast               458 drivers/gpu/drm/ast/ast_main.c 		ast->ioregs = pci_iomap(dev->pdev, 2, 0);
ast               459 drivers/gpu/drm/ast/ast_main.c 		if (!ast->ioregs) {
ast               470 drivers/gpu/drm/ast/ast_main.c 	if (ast->chip != AST1180) {
ast               474 drivers/gpu/drm/ast/ast_main.c 		ast->vram_size = ast_get_vram_info(dev);
ast               476 drivers/gpu/drm/ast/ast_main.c 			 ast->mclk, ast->dram_type,
ast               477 drivers/gpu/drm/ast/ast_main.c 			 ast->dram_bus_width, ast->vram_size);
ast               480 drivers/gpu/drm/ast/ast_main.c 	ret = ast_mm_init(ast);
ast               491 drivers/gpu/drm/ast/ast_main.c 	dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
ast               493 drivers/gpu/drm/ast/ast_main.c 	if (ast->chip == AST2100 ||
ast               494 drivers/gpu/drm/ast/ast_main.c 	    ast->chip == AST2200 ||
ast               495 drivers/gpu/drm/ast/ast_main.c 	    ast->chip == AST2300 ||
ast               496 drivers/gpu/drm/ast/ast_main.c 	    ast->chip == AST2400 ||
ast               497 drivers/gpu/drm/ast/ast_main.c 	    ast->chip == AST2500 ||
ast               498 drivers/gpu/drm/ast/ast_main.c 	    ast->chip == AST1180) {
ast               516 drivers/gpu/drm/ast/ast_main.c 	kfree(ast);
ast               523 drivers/gpu/drm/ast/ast_main.c 	struct ast_private *ast = dev->dev_private;
ast               526 drivers/gpu/drm/ast/ast_main.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
ast               529 drivers/gpu/drm/ast/ast_main.c 	kfree(ast->dp501_fw_addr);
ast               533 drivers/gpu/drm/ast/ast_main.c 	ast_mm_fini(ast);
ast               534 drivers/gpu/drm/ast/ast_main.c 	if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET)
ast               535 drivers/gpu/drm/ast/ast_main.c 		pci_iounmap(dev->pdev, ast->ioregs);
ast               536 drivers/gpu/drm/ast/ast_main.c 	pci_iounmap(dev->pdev, ast->regs);
ast               537 drivers/gpu/drm/ast/ast_main.c 	kfree(ast);
ast                54 drivers/gpu/drm/ast/ast_mode.c static inline void ast_load_palette_index(struct ast_private *ast,
ast                58 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
ast                59 drivers/gpu/drm/ast/ast_mode.c 	ast_io_read8(ast, AST_IO_SEQ_PORT);
ast                60 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_DAC_DATA, red);
ast                61 drivers/gpu/drm/ast/ast_mode.c 	ast_io_read8(ast, AST_IO_SEQ_PORT);
ast                62 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_DAC_DATA, green);
ast                63 drivers/gpu/drm/ast/ast_mode.c 	ast_io_read8(ast, AST_IO_SEQ_PORT);
ast                64 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_DAC_DATA, blue);
ast                65 drivers/gpu/drm/ast/ast_mode.c 	ast_io_read8(ast, AST_IO_SEQ_PORT);
ast                70 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast                82 drivers/gpu/drm/ast/ast_mode.c 		ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
ast                89 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               209 drivers/gpu/drm/ast/ast_mode.c 	if (ast->chip == AST1180) {
ast               212 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
ast               213 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
ast               214 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
ast               216 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
ast               218 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
ast               219 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92,
ast               221 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
ast               222 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
ast               223 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
ast               225 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
ast               226 drivers/gpu/drm/ast/ast_mode.c 			ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
ast               237 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               245 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
ast               248 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
ast               253 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
ast               257 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
ast               259 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
ast               262 drivers/gpu/drm/ast/ast_mode.c 	jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
ast               265 drivers/gpu/drm/ast/ast_mode.c 		ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
ast               266 drivers/gpu/drm/ast/ast_mode.c 		ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
ast               268 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
ast               269 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
ast               271 drivers/gpu/drm/ast/ast_mode.c 	jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
ast               272 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
ast               276 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
ast               282 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               286 drivers/gpu/drm/ast/ast_mode.c 	if ((ast->chip == AST2500) &&
ast               290 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
ast               295 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
ast               300 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
ast               305 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
ast               312 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
ast               317 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
ast               322 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
ast               324 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
ast               325 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
ast               335 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
ast               344 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
ast               351 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
ast               360 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
ast               369 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
ast               374 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
ast               376 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
ast               377 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
ast               378 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
ast               381 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
ast               383 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
ast               385 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
ast               390 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               396 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
ast               397 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
ast               403 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = dev->dev_private;
ast               406 drivers/gpu/drm/ast/ast_mode.c 	if (ast->chip == AST2500)
ast               411 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
ast               412 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
ast               413 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
ast               421 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               444 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
ast               445 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
ast               446 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
ast               449 drivers/gpu/drm/ast/ast_mode.c 	if (ast->chip == AST2300 || ast->chip == AST2400 ||
ast               450 drivers/gpu/drm/ast/ast_mode.c 	    ast->chip == AST2500) {
ast               451 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
ast               452 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
ast               453 drivers/gpu/drm/ast/ast_mode.c 	} else if (ast->chip == AST2100 ||
ast               454 drivers/gpu/drm/ast/ast_mode.c 		   ast->chip == AST1100 ||
ast               455 drivers/gpu/drm/ast/ast_mode.c 		   ast->chip == AST2200 ||
ast               456 drivers/gpu/drm/ast/ast_mode.c 		   ast->chip == AST2150) {
ast               457 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
ast               458 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
ast               460 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
ast               461 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
ast               468 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = dev->dev_private;
ast               471 drivers/gpu/drm/ast/ast_mode.c 	jreg  = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
ast               475 drivers/gpu/drm/ast/ast_mode.c 	ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
ast               494 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               498 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
ast               499 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
ast               500 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
ast               506 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               508 drivers/gpu/drm/ast/ast_mode.c 	if (ast->chip == AST1180)
ast               515 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
ast               516 drivers/gpu/drm/ast/ast_mode.c 		if (ast->tx_chip_type == AST_TX_DP501)
ast               521 drivers/gpu/drm/ast/ast_mode.c 		if (ast->tx_chip_type == AST_TX_DP501)
ast               523 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
ast               575 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               578 drivers/gpu/drm/ast/ast_mode.c 	if (ast->chip == AST1180) {
ast               586 drivers/gpu/drm/ast/ast_mode.c 	ast_open_key(ast);
ast               588 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
ast               624 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast               625 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
ast               753 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = connector->dev->dev_private;
ast               757 drivers/gpu/drm/ast/ast_mode.c 	if (ast->tx_chip_type == AST_TX_DP501) {
ast               758 drivers/gpu/drm/ast/ast_mode.c 		ast->dp501_maxclk = 0xff;
ast               765 drivers/gpu/drm/ast/ast_mode.c 			ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
ast               784 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = connector->dev->dev_private;
ast               788 drivers/gpu/drm/ast/ast_mode.c 	if (ast->support_wide_screen) {
ast               800 drivers/gpu/drm/ast/ast_mode.c 		if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
ast               801 drivers/gpu/drm/ast/ast_mode.c 		    (ast->chip == AST2300) || (ast->chip == AST2400) ||
ast               802 drivers/gpu/drm/ast/ast_mode.c 		    (ast->chip == AST2500) || (ast->chip == AST1180)) {
ast               807 drivers/gpu/drm/ast/ast_mode.c 				jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
ast               897 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = dev->dev_private;
ast               928 drivers/gpu/drm/ast/ast_mode.c 	ast->cursor_cache = obj;
ast               936 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = dev->dev_private;
ast               938 drivers/gpu/drm/ast/ast_mode.c 		drm_gem_vram_of_gem(ast->cursor_cache);
ast               941 drivers/gpu/drm/ast/ast_mode.c 	drm_gem_object_put_unlocked(ast->cursor_cache);
ast               961 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = i2c->dev->dev_private;
ast               966 drivers/gpu/drm/ast/ast_mode.c 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
ast               968 drivers/gpu/drm/ast/ast_mode.c 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
ast               973 drivers/gpu/drm/ast/ast_mode.c 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
ast               983 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = i2c->dev->dev_private;
ast               988 drivers/gpu/drm/ast/ast_mode.c 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
ast               990 drivers/gpu/drm/ast/ast_mode.c 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
ast               995 drivers/gpu/drm/ast/ast_mode.c 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
ast              1005 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = i2c->dev->dev_private;
ast              1011 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
ast              1012 drivers/gpu/drm/ast/ast_mode.c 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
ast              1021 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = i2c->dev->dev_private;
ast              1027 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
ast              1028 drivers/gpu/drm/ast/ast_mode.c 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
ast              1081 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast              1087 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
ast              1092 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast              1093 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
ast              1158 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast              1192 drivers/gpu/drm/ast/ast_mode.c 	dst = drm_gem_vram_kmap(drm_gem_vram_of_gem(ast->cursor_cache),
ast              1198 drivers/gpu/drm/ast/ast_mode.c 	dst_gpu = drm_gem_vram_offset(drm_gem_vram_of_gem(ast->cursor_cache));
ast              1204 drivers/gpu/drm/ast/ast_mode.c 	dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
ast              1212 drivers/gpu/drm/ast/ast_mode.c 			drm_gem_vram_of_gem(ast->cursor_cache);
ast              1214 drivers/gpu/drm/ast/ast_mode.c 		dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
ast              1223 drivers/gpu/drm/ast/ast_mode.c 		gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
ast              1225 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
ast              1226 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
ast              1227 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
ast              1232 drivers/gpu/drm/ast/ast_mode.c 	ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
ast              1255 drivers/gpu/drm/ast/ast_mode.c 	struct ast_private *ast = crtc->dev->dev_private;
ast              1259 drivers/gpu/drm/ast/ast_mode.c 	sig = drm_gem_vram_kmap(drm_gem_vram_of_gem(ast->cursor_cache),
ast              1261 drivers/gpu/drm/ast/ast_mode.c 	sig += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
ast              1276 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
ast              1277 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
ast              1278 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
ast              1279 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
ast              1280 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
ast              1281 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
ast                42 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast                44 drivers/gpu/drm/ast/ast_post.c 	ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
ast                45 drivers/gpu/drm/ast/ast_post.c 	ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
ast                50 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast                52 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
ast                58 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast                61 drivers/gpu/drm/ast/ast_post.c 	if (ast->chip == AST1180) {
ast                64 drivers/gpu/drm/ast/ast_post.c 		ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
ast                77 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast                83 drivers/gpu/drm/ast/ast_post.c 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
ast                85 drivers/gpu/drm/ast/ast_post.c 	if (ast->chip == AST2300 || ast->chip == AST2400 ||
ast                86 drivers/gpu/drm/ast/ast_post.c 	    ast->chip == AST2500) {
ast                96 drivers/gpu/drm/ast/ast_post.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
ast               105 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
ast               106 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
ast               110 drivers/gpu/drm/ast/ast_post.c 	if (ast->chip == AST2300 || ast->chip == AST2400 ||
ast               111 drivers/gpu/drm/ast/ast_post.c 	    ast->chip == AST2500)
ast               113 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
ast               116 drivers/gpu/drm/ast/ast_post.c u32 ast_mindwm(struct ast_private *ast, u32 r)
ast               120 drivers/gpu/drm/ast/ast_post.c 	ast_write32(ast, 0xf004, r & 0xffff0000);
ast               121 drivers/gpu/drm/ast/ast_post.c 	ast_write32(ast, 0xf000, 0x1);
ast               124 drivers/gpu/drm/ast/ast_post.c 		data = ast_read32(ast, 0xf004) & 0xffff0000;
ast               126 drivers/gpu/drm/ast/ast_post.c 	return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
ast               129 drivers/gpu/drm/ast/ast_post.c void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
ast               132 drivers/gpu/drm/ast/ast_post.c 	ast_write32(ast, 0xf004, r & 0xffff0000);
ast               133 drivers/gpu/drm/ast/ast_post.c 	ast_write32(ast, 0xf000, 0x1);
ast               135 drivers/gpu/drm/ast/ast_post.c 		data = ast_read32(ast, 0xf004) & 0xffff0000;
ast               137 drivers/gpu/drm/ast/ast_post.c 	ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
ast               168 drivers/gpu/drm/ast/ast_post.c static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
ast               172 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               173 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
ast               176 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
ast               178 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               182 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               183 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
ast               186 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
ast               188 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               192 drivers/gpu/drm/ast/ast_post.c 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
ast               193 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               198 drivers/gpu/drm/ast/ast_post.c static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
ast               202 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               203 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
ast               206 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
ast               208 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               212 drivers/gpu/drm/ast/ast_post.c 	data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
ast               213 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               218 drivers/gpu/drm/ast/ast_post.c static int cbrtest_ast2150(struct ast_private *ast)
ast               223 drivers/gpu/drm/ast/ast_post.c 		if (mmctestburst2_ast2150(ast, i))
ast               228 drivers/gpu/drm/ast/ast_post.c static int cbrscan_ast2150(struct ast_private *ast, int busw)
ast               233 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
ast               235 drivers/gpu/drm/ast/ast_post.c 			if (cbrtest_ast2150(ast))
ast               245 drivers/gpu/drm/ast/ast_post.c static void cbrdlli_ast2150(struct ast_private *ast, int busw)
ast               255 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
ast               256 drivers/gpu/drm/ast/ast_post.c 		data = cbrscan_ast2150(ast, busw);
ast               272 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
ast               279 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast               284 drivers/gpu/drm/ast/ast_post.c 	j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast               287 drivers/gpu/drm/ast/ast_post.c 		if (ast->chip == AST2000) {
ast               289 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0xf004, 0x1e6e0000);
ast               290 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0xf000, 0x1);
ast               291 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x10100, 0xa8);
ast               295 drivers/gpu/drm/ast/ast_post.c 			} while (ast_read32(ast, 0x10100) != 0xa8);
ast               297 drivers/gpu/drm/ast/ast_post.c 			if (ast->chip == AST2100 || ast->chip == 2200)
ast               302 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0xf004, 0x1e6e0000);
ast               303 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0xf000, 0x1);
ast               304 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x12000, 0x1688A8A8);
ast               307 drivers/gpu/drm/ast/ast_post.c 			} while (ast_read32(ast, 0x12000) != 0x01);
ast               309 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x10000, 0xfc600309);
ast               312 drivers/gpu/drm/ast/ast_post.c 			} while (ast_read32(ast, 0x10000) != 0x01);
ast               319 drivers/gpu/drm/ast/ast_post.c 			} else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
ast               321 drivers/gpu/drm/ast/ast_post.c 				if (ast->dram_type == AST_DRAM_1Gx16)
ast               323 drivers/gpu/drm/ast/ast_post.c 				else if (ast->dram_type == AST_DRAM_1Gx32)
ast               326 drivers/gpu/drm/ast/ast_post.c 				temp = ast_read32(ast, 0x12070);
ast               329 drivers/gpu/drm/ast/ast_post.c 				ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
ast               331 drivers/gpu/drm/ast/ast_post.c 				ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
ast               336 drivers/gpu/drm/ast/ast_post.c 		data = ast_read32(ast, 0x10120);
ast               338 drivers/gpu/drm/ast/ast_post.c 			data = ast_read32(ast, 0x10004);
ast               340 drivers/gpu/drm/ast/ast_post.c 				cbrdlli_ast2150(ast, 16); /* 16 bits */
ast               342 drivers/gpu/drm/ast/ast_post.c 				cbrdlli_ast2150(ast, 32); /* 32 bits */
ast               345 drivers/gpu/drm/ast/ast_post.c 		switch (ast->chip) {
ast               347 drivers/gpu/drm/ast/ast_post.c 			temp = ast_read32(ast, 0x10140);
ast               348 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x10140, temp | 0x40);
ast               354 drivers/gpu/drm/ast/ast_post.c 			temp = ast_read32(ast, 0x1200c);
ast               355 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x1200c, temp & 0xfffffffd);
ast               356 drivers/gpu/drm/ast/ast_post.c 			temp = ast_read32(ast, 0x12040);
ast               357 drivers/gpu/drm/ast/ast_post.c 			ast_write32(ast, 0x12040, temp | 0x40);
ast               366 drivers/gpu/drm/ast/ast_post.c 		j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast               373 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast               375 drivers/gpu/drm/ast/ast_post.c 	pci_read_config_dword(ast->dev->pdev, 0x04, &reg);
ast               377 drivers/gpu/drm/ast/ast_post.c 	pci_write_config_dword(ast->dev->pdev, 0x04, reg);
ast               380 drivers/gpu/drm/ast/ast_post.c 	ast_open_key(ast);
ast               384 drivers/gpu/drm/ast/ast_post.c 	if (ast->config_mode == ast_use_p2a) {
ast               385 drivers/gpu/drm/ast/ast_post.c 		if (ast->chip == AST2500)
ast               387 drivers/gpu/drm/ast/ast_post.c 		else if (ast->chip == AST2300 || ast->chip == AST2400)
ast               394 drivers/gpu/drm/ast/ast_post.c 		if (ast->tx_chip_type != AST_TX_NONE)
ast               395 drivers/gpu/drm/ast/ast_post.c 			ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);	/* Enable DVO */
ast               452 drivers/gpu/drm/ast/ast_post.c static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
ast               456 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               457 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
ast               460 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
ast               464 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               468 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x0);
ast               472 drivers/gpu/drm/ast/ast_post.c static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
ast               476 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               477 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
ast               480 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
ast               482 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e0070, 0x0);
ast               486 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1e6e0078);
ast               488 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast               493 drivers/gpu/drm/ast/ast_post.c static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
ast               495 drivers/gpu/drm/ast/ast_post.c 	return mmc_test(ast, datagen, 0xc1);
ast               498 drivers/gpu/drm/ast/ast_post.c static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
ast               500 drivers/gpu/drm/ast/ast_post.c 	return mmc_test2(ast, datagen, 0x41);
ast               503 drivers/gpu/drm/ast/ast_post.c static bool mmc_test_single(struct ast_private *ast, u32 datagen)
ast               505 drivers/gpu/drm/ast/ast_post.c 	return mmc_test(ast, datagen, 0xc5);
ast               508 drivers/gpu/drm/ast/ast_post.c static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
ast               510 drivers/gpu/drm/ast/ast_post.c 	return mmc_test2(ast, datagen, 0x05);
ast               513 drivers/gpu/drm/ast/ast_post.c static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
ast               515 drivers/gpu/drm/ast/ast_post.c 	return mmc_test(ast, datagen, 0x85);
ast               518 drivers/gpu/drm/ast/ast_post.c static int cbr_test(struct ast_private *ast)
ast               522 drivers/gpu/drm/ast/ast_post.c 	data = mmc_test_single2(ast, 0);
ast               526 drivers/gpu/drm/ast/ast_post.c 		data = mmc_test_burst2(ast, i);
ast               537 drivers/gpu/drm/ast/ast_post.c static int cbr_scan(struct ast_private *ast)
ast               543 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
ast               545 drivers/gpu/drm/ast/ast_post.c 			if ((data = cbr_test(ast)) != 0) {
ast               558 drivers/gpu/drm/ast/ast_post.c static u32 cbr_test2(struct ast_private *ast)
ast               562 drivers/gpu/drm/ast/ast_post.c 	data = mmc_test_burst2(ast, 0);
ast               565 drivers/gpu/drm/ast/ast_post.c 	data |= mmc_test_single2(ast, 0);
ast               572 drivers/gpu/drm/ast/ast_post.c static u32 cbr_scan2(struct ast_private *ast)
ast               578 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
ast               580 drivers/gpu/drm/ast/ast_post.c 			if ((data = cbr_test2(ast)) != 0) {
ast               593 drivers/gpu/drm/ast/ast_post.c static bool cbr_test3(struct ast_private *ast)
ast               595 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 0))
ast               597 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_single(ast, 0))
ast               602 drivers/gpu/drm/ast/ast_post.c static bool cbr_scan3(struct ast_private *ast)
ast               607 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
ast               609 drivers/gpu/drm/ast/ast_post.c 			if (cbr_test3(ast))
ast               618 drivers/gpu/drm/ast/ast_post.c static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
ast               629 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
ast               630 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
ast               631 drivers/gpu/drm/ast/ast_post.c 		data = cbr_scan2(ast);
ast               688 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0080, data);
ast               713 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0084, data);
ast               717 drivers/gpu/drm/ast/ast_post.c static void finetuneDQSI(struct ast_private *ast)
ast               726 drivers/gpu/drm/ast/ast_post.c 	reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);
ast               727 drivers/gpu/drm/ast/ast_post.c 	reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);
ast               729 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
ast               744 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, 0);
ast               745 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
ast               746 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
ast               748 drivers/gpu/drm/ast/ast_post.c 				ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
ast               749 drivers/gpu/drm/ast/ast_post.c 				ast_moutdwm(ast, 0x1E6E0070, 0);
ast               750 drivers/gpu/drm/ast/ast_post.c 				ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
ast               751 drivers/gpu/drm/ast/ast_post.c 				if (cbr_scan3(ast)) {
ast               804 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
ast               807 drivers/gpu/drm/ast/ast_post.c static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
ast               812 drivers/gpu/drm/ast/ast_post.c 	finetuneDQSI(ast);
ast               813 drivers/gpu/drm/ast/ast_post.c 	if (finetuneDQI_L(ast, param) == false)
ast               821 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
ast               822 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
ast               823 drivers/gpu/drm/ast/ast_post.c 		data = cbr_scan(ast);
ast               859 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
ast               863 drivers/gpu/drm/ast/ast_post.c static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
ast               867 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
ast               870 drivers/gpu/drm/ast/ast_post.c 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
ast               884 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0190);
ast               912 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
ast               942 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
ast               972 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0230);
ast               986 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0270);
ast              1000 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0290);
ast              1016 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0140);
ast              1034 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
ast              1052 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0160);
ast              1105 drivers/gpu/drm/ast/ast_post.c static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
ast              1110 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast              1111 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
ast              1112 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
ast              1113 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
ast              1115 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
ast              1116 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
ast              1118 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
ast              1121 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
ast              1122 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
ast              1123 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
ast              1124 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
ast              1125 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
ast              1126 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
ast              1127 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
ast              1128 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
ast              1129 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
ast              1130 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
ast              1131 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
ast              1132 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
ast              1133 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
ast              1134 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
ast              1135 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
ast              1136 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast              1137 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast              1138 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0054, 0);
ast              1139 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
ast              1140 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
ast              1141 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast              1142 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
ast              1143 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
ast              1144 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast              1147 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E001C);
ast              1149 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E001C);
ast              1152 drivers/gpu/drm/ast/ast_post.c 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
ast              1156 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0064, data2);
ast              1162 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
ast              1165 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0068, data);
ast              1167 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
ast              1169 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
ast              1170 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0018, data);
ast              1172 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0018, data);
ast              1174 drivers/gpu/drm/ast/ast_post.c 			data = ast_mindwm(ast, 0x1E6E001C);
ast              1177 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E001C);
ast              1180 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
ast              1181 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
ast              1182 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, data);
ast              1184 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
ast              1185 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
ast              1188 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
ast              1189 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast              1190 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
ast              1191 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
ast              1192 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast              1193 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast              1194 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
ast              1195 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
ast              1196 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast              1198 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
ast              1206 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
ast              1209 drivers/gpu/drm/ast/ast_post.c 	if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
ast              1212 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
ast              1215 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast              1216 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x221);
ast              1218 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0070);
ast              1220 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast              1221 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast              1222 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast              1228 drivers/gpu/drm/ast/ast_post.c static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
ast              1232 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
ast              1235 drivers/gpu/drm/ast/ast_post.c 	trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
ast              1249 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0130);
ast              1264 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0190);
ast              1295 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
ast              1329 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
ast              1362 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0230);
ast              1377 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0261);
ast              1393 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0120);
ast              1409 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
ast              1425 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2020, 0x0140);
ast              1475 drivers/gpu/drm/ast/ast_post.c static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
ast              1480 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast              1481 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
ast              1482 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
ast              1483 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
ast              1484 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
ast              1486 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
ast              1489 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
ast              1490 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
ast              1491 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
ast              1492 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
ast              1493 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
ast              1494 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
ast              1495 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
ast              1496 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
ast              1497 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
ast              1498 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
ast              1499 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
ast              1500 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
ast              1501 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
ast              1502 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
ast              1503 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
ast              1504 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast              1505 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast              1506 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0054, 0);
ast              1507 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
ast              1508 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
ast              1509 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast              1510 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
ast              1511 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
ast              1512 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast              1516 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E001C);
ast              1518 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E001C);
ast              1521 drivers/gpu/drm/ast/ast_post.c 		data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
ast              1525 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0064, data2);
ast              1531 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
ast              1534 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0068, data);
ast              1536 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
ast              1538 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
ast              1539 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0018, data);
ast              1541 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E0018, data);
ast              1543 drivers/gpu/drm/ast/ast_post.c 			data = ast_mindwm(ast, 0x1E6E001C);
ast              1546 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E001C);
ast              1549 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
ast              1550 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
ast              1551 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, data);
ast              1553 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
ast              1554 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast              1557 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
ast              1558 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast              1559 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
ast              1560 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
ast              1561 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast              1562 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast              1564 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
ast              1565 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
ast              1566 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast              1567 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
ast              1568 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast              1569 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast              1570 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast              1572 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
ast              1580 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
ast              1581 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
ast              1584 drivers/gpu/drm/ast/ast_post.c 	if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
ast              1589 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast              1590 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x221);
ast              1592 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0070);
ast              1594 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast              1595 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast              1596 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast              1603 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast              1608 drivers/gpu/drm/ast/ast_post.c 	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast              1610 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0xf004, 0x1e6e0000);
ast              1611 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0xf000, 0x1);
ast              1612 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x12000, 0x1688a8a8);
ast              1615 drivers/gpu/drm/ast/ast_post.c 		} while (ast_read32(ast, 0x12000) != 0x1);
ast              1617 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x10000, 0xfc600309);
ast              1620 drivers/gpu/drm/ast/ast_post.c 		} while (ast_read32(ast, 0x10000) != 0x1);
ast              1623 drivers/gpu/drm/ast/ast_post.c 		temp = ast_read32(ast, 0x12008);
ast              1625 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x12008, temp);
ast              1629 drivers/gpu/drm/ast/ast_post.c 		temp = ast_mindwm(ast, 0x1e6e2070);
ast              1667 drivers/gpu/drm/ast/ast_post.c 			get_ddr3_info(ast, &param);
ast              1668 drivers/gpu/drm/ast/ast_post.c 			ddr3_init(ast, &param);
ast              1670 drivers/gpu/drm/ast/ast_post.c 			get_ddr2_info(ast, &param);
ast              1671 drivers/gpu/drm/ast/ast_post.c 			ddr2_init(ast, &param);
ast              1674 drivers/gpu/drm/ast/ast_post.c 		temp = ast_mindwm(ast, 0x1e6e2040);
ast              1675 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
ast              1680 drivers/gpu/drm/ast/ast_post.c 		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast              1684 drivers/gpu/drm/ast/ast_post.c static bool cbr_test_2500(struct ast_private *ast)
ast              1686 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
ast              1687 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
ast              1688 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 0))
ast              1690 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_single_2500(ast, 0))
ast              1695 drivers/gpu/drm/ast/ast_post.c static bool ddr_test_2500(struct ast_private *ast)
ast              1697 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
ast              1698 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
ast              1699 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 0))
ast              1701 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 1))
ast              1703 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 2))
ast              1705 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_burst(ast, 3))
ast              1707 drivers/gpu/drm/ast/ast_post.c 	if (!mmc_test_single_2500(ast, 0))
ast              1712 drivers/gpu/drm/ast/ast_post.c static void ddr_init_common_2500(struct ast_private *ast)
ast              1714 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
ast              1715 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
ast              1716 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
ast              1717 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
ast              1718 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
ast              1719 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
ast              1720 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
ast              1721 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast              1722 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
ast              1723 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
ast              1724 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
ast              1725 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
ast              1726 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
ast              1727 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
ast              1728 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
ast              1729 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
ast              1730 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
ast              1731 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
ast              1732 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
ast              1735 drivers/gpu/drm/ast/ast_post.c static void ddr_phy_init_2500(struct ast_private *ast)
ast              1740 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
ast              1743 drivers/gpu/drm/ast/ast_post.c 			data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
ast              1748 drivers/gpu/drm/ast/ast_post.c 			data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
ast              1753 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast              1755 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
ast              1759 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
ast              1769 drivers/gpu/drm/ast/ast_post.c static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
ast              1773 drivers/gpu/drm/ast/ast_post.c 	reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
ast              1774 drivers/gpu/drm/ast/ast_post.c 	reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
ast              1776 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0xA0100000, 0x41424344);
ast              1777 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x90100000, 0x35363738);
ast              1778 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
ast              1779 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
ast              1782 drivers/gpu/drm/ast/ast_post.c 	if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
ast              1786 drivers/gpu/drm/ast/ast_post.c 	} else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
ast              1790 drivers/gpu/drm/ast/ast_post.c 	} else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
ast              1796 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, reg_04);
ast              1797 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0014, reg_14);
ast              1800 drivers/gpu/drm/ast/ast_post.c static void enable_cache_2500(struct ast_private *ast)
ast              1804 drivers/gpu/drm/ast/ast_post.c 	reg_04 = ast_mindwm(ast, 0x1E6E0004);
ast              1805 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
ast              1808 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E0004);
ast              1810 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
ast              1813 drivers/gpu/drm/ast/ast_post.c static void set_mpll_2500(struct ast_private *ast)
ast              1818 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast              1819 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
ast              1821 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, addr, 0x0);
ast              1824 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
ast              1826 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
ast              1827 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
ast              1831 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
ast              1836 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E2020, param);
ast              1840 drivers/gpu/drm/ast/ast_post.c static void reset_mmc_2500(struct ast_private *ast)
ast              1842 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E78505C, 0x00000004);
ast              1843 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E785044, 0x00000001);
ast              1844 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E785048, 0x00004755);
ast              1845 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E78504C, 0x00000013);
ast              1847 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E785054, 0x00000077);
ast              1848 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast              1851 drivers/gpu/drm/ast/ast_post.c static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
ast              1854 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
ast              1855 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
ast              1856 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
ast              1857 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
ast              1858 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
ast              1859 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
ast              1860 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
ast              1861 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
ast              1864 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
ast              1865 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
ast              1866 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
ast              1867 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
ast              1868 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
ast              1869 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
ast              1870 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
ast              1871 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
ast              1872 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
ast              1873 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
ast              1874 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
ast              1875 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
ast              1876 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
ast              1877 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
ast              1880 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
ast              1883 drivers/gpu/drm/ast/ast_post.c 	ddr_phy_init_2500(ast);
ast              1885 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
ast              1886 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
ast              1887 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
ast              1889 drivers/gpu/drm/ast/ast_post.c 	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
ast              1890 drivers/gpu/drm/ast/ast_post.c 	enable_cache_2500(ast);
ast              1891 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
ast              1892 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
ast              1895 drivers/gpu/drm/ast/ast_post.c static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
ast              1902 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
ast              1903 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
ast              1904 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
ast              1905 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
ast              1906 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);	     /* MODEREG4/6 */
ast              1907 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);	     /* MODEREG5 */
ast              1908 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
ast              1909 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);	     /* MODEREG1/3 */
ast              1912 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
ast              1913 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
ast              1914 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
ast              1915 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
ast              1916 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
ast              1917 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
ast              1918 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
ast              1919 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
ast              1920 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
ast              1921 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
ast              1922 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
ast              1923 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
ast              1924 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
ast              1925 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
ast              1926 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
ast              1929 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
ast              1937 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
ast              1939 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast              1940 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast              1941 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
ast              1943 drivers/gpu/drm/ast/ast_post.c 			ddr_phy_init_2500(ast);
ast              1944 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
ast              1945 drivers/gpu/drm/ast/ast_post.c 			if (cbr_test_2500(ast)) {
ast              1947 drivers/gpu/drm/ast/ast_post.c 				data = ast_mindwm(ast, 0x1E6E03D0);
ast              1960 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
ast              1970 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast              1971 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast              1972 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
ast              1974 drivers/gpu/drm/ast/ast_post.c 			ddr_phy_init_2500(ast);
ast              1975 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
ast              1976 drivers/gpu/drm/ast/ast_post.c 			if (cbr_test_2500(ast)) {
ast              1987 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
ast              1988 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
ast              1990 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
ast              1993 drivers/gpu/drm/ast/ast_post.c 	ddr_phy_init_2500(ast);
ast              1995 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
ast              1996 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
ast              1997 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
ast              1999 drivers/gpu/drm/ast/ast_post.c 	check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
ast              2000 drivers/gpu/drm/ast/ast_post.c 	enable_cache_2500(ast);
ast              2001 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
ast              2002 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
ast              2005 drivers/gpu/drm/ast/ast_post.c static bool ast_dram_init_2500(struct ast_private *ast)
ast              2013 drivers/gpu/drm/ast/ast_post.c 		set_mpll_2500(ast);
ast              2014 drivers/gpu/drm/ast/ast_post.c 		reset_mmc_2500(ast);
ast              2015 drivers/gpu/drm/ast/ast_post.c 		ddr_init_common_2500(ast);
ast              2017 drivers/gpu/drm/ast/ast_post.c 		data = ast_mindwm(ast, 0x1E6E2070);
ast              2019 drivers/gpu/drm/ast/ast_post.c 			ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
ast              2021 drivers/gpu/drm/ast/ast_post.c 			ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
ast              2022 drivers/gpu/drm/ast/ast_post.c 	} while (!ddr_test_2500(ast));
ast              2024 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
ast              2027 drivers/gpu/drm/ast/ast_post.c 	data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
ast              2028 drivers/gpu/drm/ast/ast_post.c 	ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
ast              2035 drivers/gpu/drm/ast/ast_post.c 	struct ast_private *ast = dev->dev_private;
ast              2039 drivers/gpu/drm/ast/ast_post.c 	reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast              2042 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
ast              2043 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e600084, 0x00010000);
ast              2044 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e600088, 0x00000000);
ast              2045 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
ast              2046 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0xf004, 0x1e6e0000);
ast              2047 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0xf000, 0x1);
ast              2048 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x12000, 0x1688a8a8);
ast              2049 drivers/gpu/drm/ast/ast_post.c 		while (ast_read32(ast, 0x12000) != 0x1)
ast              2052 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x10000, 0xfc600309);
ast              2053 drivers/gpu/drm/ast/ast_post.c 		while (ast_read32(ast, 0x10000) != 0x1)
ast              2057 drivers/gpu/drm/ast/ast_post.c 		temp = ast_read32(ast, 0x12008);
ast              2059 drivers/gpu/drm/ast/ast_post.c 		ast_write32(ast, 0x12008, temp);
ast              2062 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
ast              2063 drivers/gpu/drm/ast/ast_post.c 		temp  = ast_mindwm(ast, 0x1e6e2094);
ast              2065 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e2094, temp);
ast              2066 drivers/gpu/drm/ast/ast_post.c 		temp  = ast_mindwm(ast, 0x1e6e2070);
ast              2068 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
ast              2070 drivers/gpu/drm/ast/ast_post.c 			ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
ast              2073 drivers/gpu/drm/ast/ast_post.c 		if (!ast_dram_init_2500(ast))
ast              2076 drivers/gpu/drm/ast/ast_post.c 		temp = ast_mindwm(ast, 0x1e6e2040);
ast              2077 drivers/gpu/drm/ast/ast_post.c 		ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
ast              2082 drivers/gpu/drm/ast/ast_post.c 		reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
ast                37 drivers/gpu/drm/ast/ast_ttm.c int ast_mm_init(struct ast_private *ast)
ast                41 drivers/gpu/drm/ast/ast_ttm.c 	struct drm_device *dev = ast->dev;
ast                45 drivers/gpu/drm/ast/ast_ttm.c 		ast->vram_size, &drm_gem_vram_mm_funcs);
ast                54 drivers/gpu/drm/ast/ast_ttm.c 	ast->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
ast                60 drivers/gpu/drm/ast/ast_ttm.c void ast_mm_fini(struct ast_private *ast)
ast                62 drivers/gpu/drm/ast/ast_ttm.c 	struct drm_device *dev = ast->dev;
ast                66 drivers/gpu/drm/ast/ast_ttm.c 	arch_phys_wc_del(ast->fb_mtrr);
ast              2808 fs/dlm/lock.c  			 void (*ast) (void *astparam),
ast              2847 fs/dlm/lock.c  	if (!ast || !lksb)
ast              2861 fs/dlm/lock.c  	args->astfn = ast;
ast              3417 fs/dlm/lock.c  	     void (*ast) (void *astarg),
ast              3440 fs/dlm/lock.c  	error = set_lock_args(mode, lksb, flags, namelen, 0, ast,
ast               171 fs/ocfs2/dlm/dlmapi.h 			dlm_astlockfunc_t *ast,
ast               218 fs/ocfs2/dlm/dlmast.c 	fn = lock->ast;
ast               352 fs/ocfs2/dlm/dlmcommon.h 	dlm_astlockfunc_t *ast;
ast               392 fs/ocfs2/dlm/dlmlock.c 	newlock->ast = NULL;
ast               544 fs/ocfs2/dlm/dlmlock.c 			const char *name, int namelen, dlm_astlockfunc_t *ast,
ast               608 fs/ocfs2/dlm/dlmlock.c 		if (lock->lksb != lksb || lock->ast != ast ||
ast               612 fs/ocfs2/dlm/dlmlock.c 			     "astdata=%p\n", lksb, ast, bast, data);
ast               614 fs/ocfs2/dlm/dlmlock.c 			     "astdata=%p\n", lock->lksb, lock->ast,
ast               674 fs/ocfs2/dlm/dlmlock.c 		lock->ast = ast;