asic_blank_start  733 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	int vesa_sync_start, asic_blank_end, asic_blank_start;
asic_blank_start 1197 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			asic_blank_start = asic_blank_end +
asic_blank_start 1203 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			pipe->pipe_dlg_param.vblank_start = asic_blank_start;
asic_blank_start  151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	uint32_t asic_blank_start;
asic_blank_start  181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	asic_blank_start = patched_crtc_timing.h_total -
asic_blank_start  185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	asic_blank_end = asic_blank_start -
asic_blank_start  191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			OTG_H_BLANK_START, asic_blank_start,
asic_blank_start  222 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	asic_blank_start = patched_crtc_timing.v_total -
asic_blank_start  226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	asic_blank_end = asic_blank_start -
asic_blank_start  232 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			OTG_V_BLANK_START, asic_blank_start,