ase 17 arch/arm/include/asm/tls.h str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it ase 29 arch/arm/include/asm/tls.h strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it ase 23 arch/arm/include/asm/vfpmacros.h LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} ase 25 arch/arm/include/asm/vfpmacros.h LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} ase 32 arch/arm/include/asm/vfpmacros.h ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} ase 33 arch/arm/include/asm/vfpmacros.h addeq \base, \base, #32*4 @ step over unused register space ase 38 arch/arm/include/asm/vfpmacros.h ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} ase 39 arch/arm/include/asm/vfpmacros.h addne \base, \base, #32*4 @ step over unused register space ase 47 arch/arm/include/asm/vfpmacros.h STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} ase 49 arch/arm/include/asm/vfpmacros.h STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} ase 56 arch/arm/include/asm/vfpmacros.h stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} ase 57 arch/arm/include/asm/vfpmacros.h addeq \base, \base, #32*4 @ step over unused register space ase 62 arch/arm/include/asm/vfpmacros.h stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} ase 63 arch/arm/include/asm/vfpmacros.h addne \base, \base, #32*4 @ step over unused register space ase 45 arch/arm/mach-tegra/sleep.h 1001: ldr \tmp, [\base] ase 110 arch/arm/mach-tegra/sleep.h mov32 \tmp1, \base ase 29 arch/arm64/include/asm/kvm_ptrauth.h stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)] ase 32 arch/arm64/include/asm/kvm_ptrauth.h stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)] ase 35 arch/arm64/include/asm/kvm_ptrauth.h stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)] ase 38 arch/arm64/include/asm/kvm_ptrauth.h stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)] ase 41 arch/arm64/include/asm/kvm_ptrauth.h stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APGAKEYLO_EL1)] ase 45 arch/arm64/include/asm/kvm_ptrauth.h ldp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)] ase 48 arch/arm64/include/asm/kvm_ptrauth.h ldp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)] ase 51 arch/arm64/include/asm/kvm_ptrauth.h ldp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)] ase 54 arch/arm64/include/asm/kvm_ptrauth.h ldp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)] ase 57 arch/arm64/include/asm/kvm_ptrauth.h ldp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APGAKEYLO_EL1)] ase 265 arch/mips/include/asm/asmmacro.h ld.b $w\wd, \off(\base) ase 274 arch/mips/include/asm/asmmacro.h ld.h $w\wd, \off(\base) ase 283 arch/mips/include/asm/asmmacro.h ld.w $w\wd, \off(\base) ase 292 arch/mips/include/asm/asmmacro.h ld.d $w\wd, \off(\base) ase 301 arch/mips/include/asm/asmmacro.h st.b $w\wd, \off(\base) ase 310 arch/mips/include/asm/asmmacro.h st.h $w\wd, \off(\base) ase 319 arch/mips/include/asm/asmmacro.h st.w $w\wd, \off(\base) ase 328 arch/mips/include/asm/asmmacro.h st.d $w\wd, \off(\base) ase 396 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 406 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 416 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 426 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 436 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 446 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 456 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 466 arch/mips/include/asm/asmmacro.h PTR_ADDU $1, \base, \off ase 17 arch/mips/include/asm/cpu-features.h #define __ase(ase) (cpu_data[0].ases & (ase)) ase 32 arch/mips/include/asm/cpu-features.h #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) ase 42 arch/mips/include/asm/cpu-features.h #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) ase 53 arch/mips/include/asm/cpu-features.h #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) ase 270 arch/s390/include/asm/vx-insn.h VLVG \v, \gr, \index, \base, 0 ase 295 arch/s390/include/asm/vx-insn.h GR_NUM b2, \base ase 305 arch/s390/include/asm/vx-insn.h GR_NUM b2, \base ase 311 arch/s390/include/asm/vx-insn.h VLEx \vr1, \disp, \index, \base, \m3, 0x00 ase 314 arch/s390/include/asm/vx-insn.h VLEx \vr1, \disp, \index, \base, \m3, 0x01 ase 317 arch/s390/include/asm/vx-insn.h VLEx \vr1, \disp, \index, \base, \m3, 0x03 ase 320 arch/s390/include/asm/vx-insn.h VLEx \vr1, \disp, \index, \base, \m3, 0x02 ase 346 arch/s390/include/asm/vx-insn.h GR_NUM b2, \base ase 353 arch/s390/include/asm/vx-insn.h VLGV \gr, \vr, \disp, \base, 0 ase 356 arch/s390/include/asm/vx-insn.h VLGV \gr, \vr, \disp, \base, 1 ase 359 arch/s390/include/asm/vx-insn.h VLGV \gr, \vr, \disp, \base, 2 ase 362 arch/s390/include/asm/vx-insn.h VLGV \gr, \vr, \disp, \base, 3 ase 369 arch/s390/include/asm/vx-insn.h GR_NUM b2, \base /* Base register */ ase 379 arch/s390/include/asm/vx-insn.h GR_NUM b2, \base /* Base register */ ase 49 arch/x86/include/asm/unwind_hints.h .if \base == %rsp ase 55 arch/x86/include/asm/unwind_hints.h .elseif \base == %rbp ase 57 arch/x86/include/asm/unwind_hints.h .elseif \base == %rdi ase 59 arch/x86/include/asm/unwind_hints.h .elseif \base == %rdx ase 61 arch/x86/include/asm/unwind_hints.h .elseif \base == %r10 ase 82 arch/x86/include/asm/unwind_hints.h UNWIND_HINT_REGS base=\base offset=\offset iret=1 ase 210 drivers/net/ethernet/mellanox/mlx5/core/port.c MLX5_SET(paos_reg, in, ase, 1); ase 4406 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); ase 8578 include/linux/mlx5/mlx5_ifc.h u8 ase[0x1]; ase 8912 include/linux/mlx5/mlx5_ifc.h u8 ase[0x1];