array_mode       2835 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		tiling_info->gfx8.array_mode =
array_mode       2845 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
array_mode        163 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.array_mode,
array_mode        252 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 					update->plane_info->tiling_info.gfx8.array_mode,
array_mode        376 drivers/gpu/drm/amd/display/dc/dc_hw_types.h 		enum array_mode_values array_mode;
array_mode        103 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 	switch (tiling_info->gfx8.array_mode) {
array_mode        381 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 				GRPH_ARRAY_MODE, info->gfx8.array_mode,
array_mode       1845 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
array_mode        192 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 	set_reg_field_value(value, info->gfx8.array_mode,
array_mode        544 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 	switch (tiling_info->gfx8.array_mode) {
array_mode        240 drivers/gpu/drm/radeon/r600_cs.c 	int array_mode;
array_mode        262 drivers/gpu/drm/radeon/r600_cs.c 	switch (values->array_mode) {
array_mode        358 drivers/gpu/drm/radeon/r600_cs.c 	unsigned array_mode;
array_mode        378 drivers/gpu/drm/radeon/r600_cs.c 	array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
array_mode        381 drivers/gpu/drm/radeon/r600_cs.c 	array_check.array_mode = array_mode;
array_mode        394 drivers/gpu/drm/radeon/r600_cs.c 	switch (array_mode) {
array_mode        415 drivers/gpu/drm/radeon/r600_cs.c 			 __func__, __LINE__, pitch, pitch_align, array_mode);
array_mode        420 drivers/gpu/drm/radeon/r600_cs.c 			 __func__, __LINE__, height, height_align, array_mode);
array_mode        425 drivers/gpu/drm/radeon/r600_cs.c 			 base_offset, base_align, array_mode);
array_mode        432 drivers/gpu/drm/radeon/r600_cs.c 	switch (array_mode) {
array_mode        444 drivers/gpu/drm/radeon/r600_cs.c 		if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
array_mode        453 drivers/gpu/drm/radeon/r600_cs.c 				 __func__, i, array_mode,
array_mode        526 drivers/gpu/drm/radeon/r600_cs.c 	int array_mode;
array_mode        576 drivers/gpu/drm/radeon/r600_cs.c 		array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
array_mode        577 drivers/gpu/drm/radeon/r600_cs.c 		array_check.array_mode = array_mode;
array_mode        590 drivers/gpu/drm/radeon/r600_cs.c 		switch (array_mode) {
array_mode        606 drivers/gpu/drm/radeon/r600_cs.c 					__func__, __LINE__, pitch, pitch_align, array_mode);
array_mode        611 drivers/gpu/drm/radeon/r600_cs.c 					__func__, __LINE__, height, height_align, array_mode);
array_mode        616 drivers/gpu/drm/radeon/r600_cs.c 					base_offset, base_align, array_mode);
array_mode        625 drivers/gpu/drm/radeon/r600_cs.c 					array_mode,
array_mode       1515 drivers/gpu/drm/radeon/r600_cs.c 	array_check.array_mode = G_038000_TILE_MODE(word0);
array_mode       1597 drivers/gpu/drm/radeon/r600_cs.c 			 array_check.array_mode, format, word2,