arb_regs 4759 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) arb_regs 4765 drivers/gpu/drm/amd/amdgpu/si_dpm.c arb_regs->mc_arb_rfsh_rate = arb_regs 4776 drivers/gpu/drm/amd/amdgpu/si_dpm.c arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); arb_regs 4777 drivers/gpu/drm/amd/amdgpu/si_dpm.c arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); arb_regs 4778 drivers/gpu/drm/amd/amdgpu/si_dpm.c arb_regs->mc_arb_burst_time = (u8)burst_time; arb_regs 4789 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; arb_regs 4793 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); arb_regs 4800 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u8 *)&arb_regs, arb_regs 5128 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; arb_regs 5132 drivers/gpu/drm/amd/amdgpu/si_dpm.c &arb_regs); arb_regs 5143 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u8 *)&arb_regs, arb_regs 1623 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs arb_regs 1641 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); arb_regs 1642 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); arb_regs 1643 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c arb_regs->McArbBurstTime = (uint8_t)burstTime; arb_regs 1653 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SMU7_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1656 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable)); arb_regs 1663 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c &arb_regs.entries[i][j]); arb_regs 1674 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (uint8_t *)&arb_regs, arb_regs 1499 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs) arb_regs 1520 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); arb_regs 1521 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); arb_regs 1522 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->McArbBurstTime = (uint8_t)burstTime; arb_regs 1523 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->TRRDS = (uint8_t)trrds; arb_regs 1524 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->TRRDL = (uint8_t)trrdl; arb_regs 1533 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c struct SMU73_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1542 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c &arb_regs.entries[i][j]); arb_regs 1552 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint8_t *)&arb_regs, arb_regs 1586 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs arb_regs 1604 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); arb_regs 1605 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); arb_regs 1606 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c arb_regs->McArbBurstTime = (uint8_t)burstTime; arb_regs 1616 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1619 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable)); arb_regs 1626 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &arb_regs.entries[i][j]); arb_regs 1638 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint8_t *)&arb_regs, arb_regs 1338 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) arb_regs 1355 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); arb_regs 1356 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); arb_regs 1357 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c arb_regs->McArbBurstTime = (uint8_t)burst_time; arb_regs 1366 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct SMU74_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1375 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c &arb_regs.entries[i][j]); arb_regs 1386 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint8_t *)&arb_regs, arb_regs 1461 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs arb_regs 1479 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); arb_regs 1480 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); arb_regs 1481 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c arb_regs->McArbBurstTime = (uint8_t)burstTime; arb_regs 1492 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1495 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); arb_regs 1502 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &arb_regs.entries[i][j]); arb_regs 1513 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint8_t *)&arb_regs, arb_regs 1255 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs) arb_regs 1277 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); arb_regs 1278 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); arb_regs 1279 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time); arb_regs 1280 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate); arb_regs 1281 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3); arb_regs 1290 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct SMU75_Discrete_MCArbDramTimingTable arb_regs; arb_regs 1294 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable)); arb_regs 1301 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c &arb_regs.entries[i][j]); arb_regs 1310 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint8_t *)&arb_regs, arb_regs 2525 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) arb_regs 2539 drivers/gpu/drm/radeon/ci_dpm.c arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); arb_regs 2540 drivers/gpu/drm/radeon/ci_dpm.c arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); arb_regs 2541 drivers/gpu/drm/radeon/ci_dpm.c arb_regs->McArbBurstTime = (u8)burst_time; arb_regs 2549 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_MCArbDramTimingTable arb_regs; arb_regs 2553 drivers/gpu/drm/radeon/ci_dpm.c memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); arb_regs 2560 drivers/gpu/drm/radeon/ci_dpm.c &arb_regs.entries[i][j]); arb_regs 2569 drivers/gpu/drm/radeon/ci_dpm.c (u8 *)&arb_regs, arb_regs 1617 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) arb_regs 1622 drivers/gpu/drm/radeon/ni_dpm.c arb_regs->mc_arb_rfsh_rate = arb_regs 1631 drivers/gpu/drm/radeon/ni_dpm.c arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); arb_regs 1632 drivers/gpu/drm/radeon/ni_dpm.c arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); arb_regs 1644 drivers/gpu/drm/radeon/ni_dpm.c SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; arb_regs 1648 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); arb_regs 1656 drivers/gpu/drm/radeon/ni_dpm.c (u8 *)&arb_regs, arb_regs 4295 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) arb_regs 4301 drivers/gpu/drm/radeon/si_dpm.c arb_regs->mc_arb_rfsh_rate = arb_regs 4312 drivers/gpu/drm/radeon/si_dpm.c arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); arb_regs 4313 drivers/gpu/drm/radeon/si_dpm.c arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); arb_regs 4314 drivers/gpu/drm/radeon/si_dpm.c arb_regs->mc_arb_burst_time = (u8)burst_time; arb_regs 4325 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; arb_regs 4329 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); arb_regs 4336 drivers/gpu/drm/radeon/si_dpm.c (u8 *)&arb_regs, arb_regs 4665 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; arb_regs 4669 drivers/gpu/drm/radeon/si_dpm.c &arb_regs); arb_regs 4680 drivers/gpu/drm/radeon/si_dpm.c (u8 *)&arb_regs,