arb_control3      832 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
arb_control3      952 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
arb_control3      953 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = arb_control3;
arb_control3      969 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
arb_control3     2166 drivers/gpu/drm/radeon/evergreen.c 	u32 tmp, arb_control3;
arb_control3     2284 drivers/gpu/drm/radeon/evergreen.c 	arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
arb_control3     2285 drivers/gpu/drm/radeon/evergreen.c 	tmp = arb_control3;
arb_control3     2301 drivers/gpu/drm/radeon/evergreen.c 	WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
arb_control3     2311 drivers/gpu/drm/radeon/si.c 	u32 tmp, arb_control3;
arb_control3     2435 drivers/gpu/drm/radeon/si.c 	arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
arb_control3     2436 drivers/gpu/drm/radeon/si.c 	tmp = arb_control3;
arb_control3     2452 drivers/gpu/drm/radeon/si.c 	WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);