ar7_irq_base 37 arch/mips/ar7/irq.c static int ar7_irq_base; ar7_irq_base 41 arch/mips/ar7/irq.c writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_irq_base 42 arch/mips/ar7/irq.c REG(ESR_OFFSET(d->irq - ar7_irq_base))); ar7_irq_base 47 arch/mips/ar7/irq.c writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_irq_base 48 arch/mips/ar7/irq.c REG(ECR_OFFSET(d->irq - ar7_irq_base))); ar7_irq_base 53 arch/mips/ar7/irq.c writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_irq_base 54 arch/mips/ar7/irq.c REG(CR_OFFSET(d->irq - ar7_irq_base))); ar7_irq_base 59 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); ar7_irq_base 64 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); ar7_irq_base 69 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); ar7_irq_base 105 arch/mips/ar7/irq.c ar7_irq_base = base; ar7_irq_base 120 arch/mips/ar7/irq.c setup_irq(ar7_irq_base, &ar7_cascade_action); ar7_irq_base 138 arch/mips/ar7/irq.c do_IRQ(ar7_irq_base + irq); ar7_irq_base 147 arch/mips/ar7/irq.c do_IRQ(ar7_irq_base + i + 40);