apic_base_msr    4257 arch/x86/kvm/vmx/vmx.c 	struct msr_data apic_base_msr;
apic_base_msr    4271 arch/x86/kvm/vmx/vmx.c 		apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
apic_base_msr    4274 arch/x86/kvm/vmx/vmx.c 			apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
apic_base_msr    4275 arch/x86/kvm/vmx/vmx.c 		apic_base_msr.host_initiated = true;
apic_base_msr    4276 arch/x86/kvm/vmx/vmx.c 		kvm_set_apic_base(vcpu, &apic_base_msr);
apic_base_msr    8866 arch/x86/kvm/x86.c 	struct msr_data apic_base_msr;
apic_base_msr    8876 arch/x86/kvm/x86.c 	apic_base_msr.data = sregs->apic_base;
apic_base_msr    8877 arch/x86/kvm/x86.c 	apic_base_msr.host_initiated = true;
apic_base_msr    8878 arch/x86/kvm/x86.c 	if (kvm_set_apic_base(vcpu, &apic_base_msr))