apcr 114 arch/arm/mach-mmp/pm-mmp2.c uint32_t idle_cfg, apcr; apcr 117 arch/arm/mach-mmp/pm-mmp2.c apcr = __raw_readl(MPMU_PCR_PJ); apcr 118 arch/arm/mach-mmp/pm-mmp2.c apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD apcr 124 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */ apcr 125 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */ apcr 128 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_SLPEN; apcr 131 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */ apcr 134 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */ apcr 135 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */ apcr 137 arch/arm/mach-mmp/pm-mmp2.c apcr |= MPMU_PCR_PJ_SPSD; apcr 146 arch/arm/mach-mmp/pm-mmp2.c apcr &= ~MPMU_PCR_PJ_SPSD; apcr 151 arch/arm/mach-mmp/pm-mmp2.c apcr |= (1 << 30) | (1 << 25); apcr 155 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(apcr, MPMU_PCR_PJ); /* 0xfe086000 */ apcr 219 arch/arm/mach-mmp/pm-mmp2.c uint32_t apcr; apcr 240 arch/arm/mach-mmp/pm-mmp2.c apcr = __raw_readl(MPMU_PCR_PJ); apcr 241 arch/arm/mach-mmp/pm-mmp2.c apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD apcr 243 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(apcr, MPMU_PCR_PJ); apcr 29 arch/arm/mach-mmp/pm-pxa910.c uint32_t awucrm = 0, apcr = 0; apcr 37 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP2; apcr 42 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP3; apcr 46 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP3; apcr 50 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP3; apcr 55 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 59 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 63 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 67 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 71 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 75 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 79 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP4; apcr 85 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP5; apcr 92 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP6; apcr 97 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP7; apcr 102 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPWP2; apcr 115 arch/arm/mach-mmp/pm-pxa910.c if (apcr) { apcr 116 arch/arm/mach-mmp/pm-pxa910.c apcr = ~apcr & __raw_readl(MPMU_APCR); apcr 117 arch/arm/mach-mmp/pm-pxa910.c __raw_writel(apcr, MPMU_APCR); apcr 124 arch/arm/mach-mmp/pm-pxa910.c if (apcr) { apcr 125 arch/arm/mach-mmp/pm-pxa910.c apcr |= __raw_readl(MPMU_APCR); apcr 126 arch/arm/mach-mmp/pm-pxa910.c __raw_writel(apcr, MPMU_APCR); apcr 134 arch/arm/mach-mmp/pm-pxa910.c uint32_t idle_cfg, apcr; apcr 137 arch/arm/mach-mmp/pm-pxa910.c apcr = __raw_readl(MPMU_APCR); apcr 139 arch/arm/mach-mmp/pm-pxa910.c apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD apcr 147 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD; apcr 150 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */ apcr 151 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */ apcr 154 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */ apcr 157 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */ apcr 175 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD apcr 179 arch/arm/mach-mmp/pm-pxa910.c apcr |= MPMU_APCR_SLPEN; apcr 183 arch/arm/mach-mmp/pm-pxa910.c __raw_writel(apcr, MPMU_APCR);