apb_csr_base      146 drivers/pci/controller/pcie-mobiveil.c 	void __iomem *apb_csr_base;	/* MSI register base */
apb_csr_base      391 drivers/pci/controller/pcie-mobiveil.c 	msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
apb_csr_base      395 drivers/pci/controller/pcie-mobiveil.c 		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
apb_csr_base      403 drivers/pci/controller/pcie-mobiveil.c 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
apb_csr_base      405 drivers/pci/controller/pcie-mobiveil.c 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
apb_csr_base      414 drivers/pci/controller/pcie-mobiveil.c 		msi_status = readl_relaxed(pcie->apb_csr_base +
apb_csr_base      448 drivers/pci/controller/pcie-mobiveil.c 	pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
apb_csr_base      449 drivers/pci/controller/pcie-mobiveil.c 	if (IS_ERR(pcie->apb_csr_base))
apb_csr_base      450 drivers/pci/controller/pcie-mobiveil.c 		return PTR_ERR(pcie->apb_csr_base);
apb_csr_base      574 drivers/pci/controller/pcie-mobiveil.c 		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
apb_csr_base      576 drivers/pci/controller/pcie-mobiveil.c 		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
apb_csr_base      577 drivers/pci/controller/pcie-mobiveil.c 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
apb_csr_base      578 drivers/pci/controller/pcie-mobiveil.c 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);