alpha_en 399 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); alpha_en 1419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; alpha_en 2507 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; alpha_en 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c uint32_t alpha_en; alpha_en 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c alpha_en = 1; alpha_en 347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c alpha_en = 0; alpha_en 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); alpha_en 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ alpha_en 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ alpha_en 459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (scl_data->lb_params.alpha_en alpha_en 2272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; alpha_en 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c uint32_t alpha_en = 1; alpha_en 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c alpha_en = 0; alpha_en 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); alpha_en 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->lb_params.alpha_en alpha_en 154 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h bool alpha_en;