allowed_vdd_sclk_table  671 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
allowed_vdd_sclk_table  679 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
allowed_vdd_sclk_table  681 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
allowed_vdd_sclk_table  693 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
allowed_vdd_sclk_table  695 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				allowed_vdd_sclk_table->entries[i].clk) {
allowed_vdd_sclk_table  697 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				allowed_vdd_sclk_table->entries[i].clk;
allowed_vdd_sclk_table  718 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
allowed_vdd_sclk_table  725 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;