allowed_vdd_mclk_table  673 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
allowed_vdd_mclk_table  684 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
allowed_vdd_mclk_table  686 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
allowed_vdd_mclk_table  703 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
allowed_vdd_mclk_table  707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
allowed_vdd_mclk_table  709 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			allowed_vdd_mclk_table->entries[i].clk) {
allowed_vdd_mclk_table  711 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				allowed_vdd_mclk_table->entries[i].clk;
allowed_vdd_mclk_table  719 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
allowed_vdd_mclk_table  726 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
allowed_vdd_mclk_table  728 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (NULL != allowed_vdd_mclk_table) {
allowed_vdd_mclk_table  730 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
allowed_vdd_mclk_table  731 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
allowed_vdd_mclk_table  734 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
allowed_vdd_mclk_table  737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
allowed_vdd_mclk_table  739 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (NULL != allowed_vdd_mclk_table) {
allowed_vdd_mclk_table  744 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
allowed_vdd_mclk_table  745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
allowed_vdd_mclk_table  748 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;