allowed_sclk_vddc_table 2458 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
allowed_sclk_vddc_table 2462 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
allowed_sclk_vddc_table 2465 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
allowed_sclk_vddc_table 2476 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
allowed_sclk_vddc_table 2477 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
allowed_sclk_vddc_table 2480 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
allowed_sclk_vddc_table 2484 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
allowed_sclk_vddc_table 3444 drivers/gpu/drm/radeon/ci_dpm.c 	struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
allowed_sclk_vddc_table 3452 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_sclk_vddc_table == NULL)
allowed_sclk_vddc_table 3454 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_sclk_vddc_table->count < 1)
allowed_sclk_vddc_table 3480 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
allowed_sclk_vddc_table 3483 drivers/gpu/drm/radeon/ci_dpm.c 		     allowed_sclk_vddc_table->entries[i].clk)) {
allowed_sclk_vddc_table 3485 drivers/gpu/drm/radeon/ci_dpm.c 				allowed_sclk_vddc_table->entries[i].clk;
allowed_sclk_vddc_table 3505 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
allowed_sclk_vddc_table 3507 drivers/gpu/drm/radeon/ci_dpm.c 			allowed_sclk_vddc_table->entries[i].v;
allowed_sclk_vddc_table 3512 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
allowed_sclk_vddc_table 4920 drivers/gpu/drm/radeon/ci_dpm.c 	struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
allowed_sclk_vddc_table 4927 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_sclk_vddc_table == NULL)
allowed_sclk_vddc_table 4929 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_sclk_vddc_table->count < 1)
allowed_sclk_vddc_table 4940 drivers/gpu/drm/radeon/ci_dpm.c 	pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
allowed_sclk_vddc_table 4942 drivers/gpu/drm/radeon/ci_dpm.c 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
allowed_sclk_vddc_table 4949 drivers/gpu/drm/radeon/ci_dpm.c 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
allowed_sclk_vddc_table 4951 drivers/gpu/drm/radeon/ci_dpm.c 		allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
allowed_sclk_vddc_table 4953 drivers/gpu/drm/radeon/ci_dpm.c 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;