allowed_sclk_vdd_table 2075 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
allowed_sclk_vdd_table 2080 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
allowed_sclk_vdd_table 2083 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
allowed_sclk_vdd_table 2095 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
allowed_sclk_vdd_table 2099 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
allowed_sclk_vdd_table  772 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
allowed_sclk_vdd_table  777 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
allowed_sclk_vdd_table  779 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
allowed_sclk_vdd_table  788 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
allowed_sclk_vdd_table  792 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;