allowed_reg_base 2621 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t allowed_reg_base; allowed_reg_base 2628 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base = GDS_APPEND_COUNT_0; allowed_reg_base 2629 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; allowed_reg_base 2630 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base >>= 2; allowed_reg_base 2633 drivers/gpu/drm/radeon/evergreen_cs.c if (areg < allowed_reg_base || areg > (allowed_reg_base + 11)) { allowed_reg_base 3496 drivers/gpu/drm/radeon/evergreen_cs.c uint32_t allowed_reg_base; allowed_reg_base 3503 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base = GDS_APPEND_COUNT_0; allowed_reg_base 3504 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; allowed_reg_base 3505 drivers/gpu/drm/radeon/evergreen_cs.c allowed_reg_base >>= 2; allowed_reg_base 3508 drivers/gpu/drm/radeon/evergreen_cs.c if (areg < allowed_reg_base || areg > (allowed_reg_base + 11)) {