allowed_mclk_vddc_table 2459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
allowed_mclk_vddc_table 2469 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
allowed_mclk_vddc_table 2472 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
allowed_mclk_vddc_table 2482 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
allowed_mclk_vddc_table 4922 drivers/gpu/drm/radeon/ci_dpm.c 	struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
allowed_mclk_vddc_table 4931 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_vddc_table == NULL)
allowed_mclk_vddc_table 4933 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_vddc_table->count < 1)
allowed_mclk_vddc_table 4951 drivers/gpu/drm/radeon/ci_dpm.c 		allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;