allowed_mclk_vdd_table 2077 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
allowed_mclk_vdd_table 2087 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
allowed_mclk_vdd_table 2090 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
allowed_mclk_vdd_table 2097 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
allowed_mclk_vdd_table 2101 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
allowed_mclk_vdd_table  774 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
allowed_mclk_vdd_table  782 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
allowed_mclk_vdd_table  784 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
allowed_mclk_vdd_table  790 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
allowed_mclk_vdd_table  794 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;