allowed_mclk_table 3446 drivers/gpu/drm/radeon/ci_dpm.c 	struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
allowed_mclk_table 3456 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_table == NULL)
allowed_mclk_table 3458 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_table->count < 1)
allowed_mclk_table 3493 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < allowed_mclk_table->count; i++) {
allowed_mclk_table 3496 drivers/gpu/drm/radeon/ci_dpm.c 		     allowed_mclk_table->entries[i].clk)) {
allowed_mclk_table 3498 drivers/gpu/drm/radeon/ci_dpm.c 				allowed_mclk_table->entries[i].clk;
allowed_mclk_table 3514 drivers/gpu/drm/radeon/ci_dpm.c 	allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
allowed_mclk_table 3515 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_table) {
allowed_mclk_table 3516 drivers/gpu/drm/radeon/ci_dpm.c 		for (i = 0; i < allowed_mclk_table->count; i++) {
allowed_mclk_table 3518 drivers/gpu/drm/radeon/ci_dpm.c 				allowed_mclk_table->entries[i].v;
allowed_mclk_table 3521 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
allowed_mclk_table 3524 drivers/gpu/drm/radeon/ci_dpm.c 	allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
allowed_mclk_table 3525 drivers/gpu/drm/radeon/ci_dpm.c 	if (allowed_mclk_table) {
allowed_mclk_table 3526 drivers/gpu/drm/radeon/ci_dpm.c 		for (i = 0; i < allowed_mclk_table->count; i++) {
allowed_mclk_table 3528 drivers/gpu/drm/radeon/ci_dpm.c 				allowed_mclk_table->entries[i].v;
allowed_mclk_table 3531 drivers/gpu/drm/radeon/ci_dpm.c 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;