allowed_dep_table 679 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table, allowed_dep_table 683 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count), allowed_dep_table 687 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->count = allowed_dep_table->count; allowed_dep_table 689 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].clk = allowed_dep_table->entries[i].clk; allowed_dep_table 690 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd; allowed_dep_table 691 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset; allowed_dep_table 692 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc; allowed_dep_table 693 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx; allowed_dep_table 694 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci; allowed_dep_table 695 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd; allowed_dep_table 696 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].phases = allowed_dep_table->entries[i].phases; allowed_dep_table 697 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable; allowed_dep_table 698 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset; allowed_dep_table 118 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,