align_entry 501 arch/alpha/kernel/core_cia.c arena->align_entry = 4; align_entry 293 arch/alpha/kernel/core_marvel.c hose->sg_isa->align_entry = 8; /* cache line boundary */ align_entry 311 arch/alpha/kernel/core_marvel.c hose->sg_pci->align_entry = 8; /* cache line boundary */ align_entry 321 arch/alpha/kernel/core_titan.c hose->sg_isa->align_entry = 8; /* 64KB for ISA */ align_entry 325 arch/alpha/kernel/core_titan.c hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ align_entry 325 arch/alpha/kernel/core_tsunami.c hose->sg_isa->align_entry = 4; align_entry 330 arch/alpha/kernel/core_tsunami.c hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */ align_entry 143 arch/alpha/kernel/pci_impl.h unsigned int align_entry; align_entry 120 arch/alpha/kernel/pci_iommu.c arena->align_entry = 1; align_entry 203 arch/alpha/kernel/pci_iommu.c mask = max(align, arena->align_entry) - 1; align_entry 535 arch/alpha/kernel/sys_dp264.c hose_head->sg_isa->align_entry = 4; align_entry 536 arch/alpha/kernel/sys_dp264.c hose_head->sg_pci->align_entry = 4;