afec0 664 drivers/gpu/drm/vc4/vc4_dsi.c u32 afec0 = DSI_PORT_READ(PHY_AFEC0); afec0 667 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); afec0 669 drivers/gpu/drm/vc4/vc4_dsi.c afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); afec0 671 drivers/gpu/drm/vc4/vc4_dsi.c DSI_PORT_WRITE(PHY_AFEC0, afec0); afec0 871 drivers/gpu/drm/vc4/vc4_dsi.c u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | afec0 875 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; afec0 878 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI0_PHY_AFEC0_RESET; afec0 880 drivers/gpu/drm/vc4/vc4_dsi.c DSI_PORT_WRITE(PHY_AFEC0, afec0); afec0 887 drivers/gpu/drm/vc4/vc4_dsi.c u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | afec0 896 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; afec0 898 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; afec0 900 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; afec0 902 drivers/gpu/drm/vc4/vc4_dsi.c afec0 |= DSI1_PHY_AFEC0_RESET; afec0 904 drivers/gpu/drm/vc4/vc4_dsi.c DSI_PORT_WRITE(PHY_AFEC0, afec0);