aeqe 72 drivers/crypto/hisilicon/qm.c #define QM_AEQE_PHASE(aeqe) (((aeqe)->dw0 >> 16) & 0x1) aeqe 538 drivers/crypto/hisilicon/qm.c struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head; aeqe 544 drivers/crypto/hisilicon/qm.c while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) { aeqe 545 drivers/crypto/hisilicon/qm.c type = aeqe->dw0 >> QM_AEQE_TYPE_SHIFT; aeqe 555 drivers/crypto/hisilicon/qm.c aeqe = qm->aeqe; aeqe 558 drivers/crypto/hisilicon/qm.c aeqe++; aeqe 1649 drivers/crypto/hisilicon/qm.c QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH); aeqe 1659 drivers/crypto/hisilicon/qm.c qm->aeqe, (unsigned long)qm->aeqe_dma, aeqe 141 drivers/crypto/hisilicon/qm.h struct qm_aeqe *aeqe; aeqe 831 drivers/infiniband/hw/bnxt_re/main.c void *aeqe, void *obj) aeqe 838 drivers/infiniband/hw/bnxt_re/main.c type = ((struct creq_base *)aeqe)->type; aeqe 840 drivers/infiniband/hw/bnxt_re/main.c unaffi_async = aeqe; aeqe 843 drivers/infiniband/hw/bnxt_re/main.c affi_async = aeqe; aeqe 284 drivers/infiniband/hw/bnxt_re/qplib_rcfw.h void *aeqe, void *obj)); aeqe 3701 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe, int qpn) aeqe 3706 drivers/infiniband/hw/hns/hns_roce_hw_v1.c switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M, aeqe 3735 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe, aeqe 3741 drivers/infiniband/hw/hns/hns_roce_hw_v1.c switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M, aeqe 3770 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe, aeqe 3777 drivers/infiniband/hw/hns/hns_roce_hw_v1.c qpn = roce_get_field(aeqe->event.qp_event.qp, aeqe 3780 drivers/infiniband/hw/hns/hns_roce_hw_v1.c phy_port = roce_get_field(aeqe->event.qp_event.qp, aeqe 3792 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn); aeqe 3795 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn); aeqe 3805 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe, aeqe 3811 drivers/infiniband/hw/hns/hns_roce_hw_v1.c cqn = roce_get_field(aeqe->event.cq_event.cq, aeqe 3833 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe) aeqe 3837 drivers/infiniband/hw/hns/hns_roce_hw_v1.c switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M, aeqe 3874 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index); aeqe 3876 drivers/infiniband/hw/hns/hns_roce_hw_v1.c return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^ aeqe 3877 drivers/infiniband/hw/hns/hns_roce_hw_v1.c !!(eq->cons_index & eq->entries)) ? aeqe : NULL; aeqe 3884 drivers/infiniband/hw/hns/hns_roce_hw_v1.c struct hns_roce_aeqe *aeqe; aeqe 3888 drivers/infiniband/hw/hns/hns_roce_hw_v1.c while ((aeqe = next_aeqe_sw_v1(eq))) { aeqe 3896 drivers/infiniband/hw/hns/hns_roce_hw_v1.c aeqe, aeqe 3897 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_get_field(aeqe->asyn, aeqe 3900 drivers/infiniband/hw/hns/hns_roce_hw_v1.c event_type = roce_get_field(aeqe->asyn, aeqe 3919 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type); aeqe 3929 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type); aeqe 3936 drivers/infiniband/hw/hns/hns_roce_hw_v1.c le16_to_cpu(aeqe->event.cmd.token), aeqe 3937 drivers/infiniband/hw/hns/hns_roce_hw_v1.c aeqe->event.cmd.status, aeqe 3938 drivers/infiniband/hw/hns/hns_roce_hw_v1.c le64_to_cpu(aeqe->event.cmd.out_param aeqe 3942 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hns_roce_v1_db_overflow_handle(hr_dev, aeqe); aeqe 3946 drivers/infiniband/hw/hns/hns_roce_hw_v1.c roce_get_field(aeqe->event.ce_event.ceqe, aeqe 5012 drivers/infiniband/hw/hns/hns_roce_hw_v2.c struct hns_roce_aeqe *aeqe; aeqe 5015 drivers/infiniband/hw/hns/hns_roce_hw_v2.c aeqe = get_aeqe_v2(eq, eq->cons_index); aeqe 5017 drivers/infiniband/hw/hns/hns_roce_hw_v2.c aeqe = mhop_get_aeqe(eq, eq->cons_index); aeqe 5019 drivers/infiniband/hw/hns/hns_roce_hw_v2.c return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ aeqe 5020 drivers/infiniband/hw/hns/hns_roce_hw_v2.c !!(eq->cons_index & eq->entries)) ? aeqe : NULL; aeqe 5027 drivers/infiniband/hw/hns/hns_roce_hw_v2.c struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); aeqe 5035 drivers/infiniband/hw/hns/hns_roce_hw_v2.c while (aeqe) { aeqe 5041 drivers/infiniband/hw/hns/hns_roce_hw_v2.c event_type = roce_get_field(aeqe->asyn, aeqe 5044 drivers/infiniband/hw/hns/hns_roce_hw_v2.c sub_type = roce_get_field(aeqe->asyn, aeqe 5047 drivers/infiniband/hw/hns/hns_roce_hw_v2.c qpn = roce_get_field(aeqe->event.qp_event.qp, aeqe 5050 drivers/infiniband/hw/hns/hns_roce_hw_v2.c cqn = roce_get_field(aeqe->event.cq_event.cq, aeqe 5053 drivers/infiniband/hw/hns/hns_roce_hw_v2.c srqn = roce_get_field(aeqe->event.srq_event.srq, aeqe 5080 drivers/infiniband/hw/hns/hns_roce_hw_v2.c le16_to_cpu(aeqe->event.cmd.token), aeqe 5081 drivers/infiniband/hw/hns/hns_roce_hw_v2.c aeqe->event.cmd.status, aeqe 5082 drivers/infiniband/hw/hns/hns_roce_hw_v2.c le64_to_cpu(aeqe->event.cmd.out_param)); aeqe 5104 drivers/infiniband/hw/hns/hns_roce_hw_v2.c aeqe = next_aeqe_sw_v2(eq); aeqe 1774 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u64 *aeqe; aeqe 1779 drivers/infiniband/hw/i40iw/i40iw_ctrl.c aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq); aeqe 1780 drivers/infiniband/hw/i40iw/i40iw_ctrl.c get_64bit_val(aeqe, 0, &compl_ctx); aeqe 1781 drivers/infiniband/hw/i40iw/i40iw_ctrl.c get_64bit_val(aeqe, 8, &temp); aeqe 1787 drivers/infiniband/hw/i40iw/i40iw_ctrl.c i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16); aeqe 533 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c struct hinic_aeq_elem *aeqe; aeqe 537 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c aeqe = GET_AEQ_ELEM(eq, i); aeqe 538 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c aeqe->desc = cpu_to_be32(init_val);