adpa_reg 94 drivers/gpu/drm/gma500/cdv_intel_crt.c u32 adpa_reg; adpa_reg 101 drivers/gpu/drm/gma500/cdv_intel_crt.c adpa_reg = ADPA; adpa_reg 124 drivers/gpu/drm/gma500/cdv_intel_crt.c REG_WRITE(adpa_reg, adpa); adpa_reg 60 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg; adpa_reg 74 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg, enum pipe *pipe) adpa_reg 78 drivers/gpu/drm/i915/display/intel_crt.c val = I915_READ(adpa_reg); adpa_reg 102 drivers/gpu/drm/i915/display/intel_crt.c ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); adpa_reg 115 drivers/gpu/drm/i915/display/intel_crt.c tmp = I915_READ(crt->adpa_reg); adpa_reg 204 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, adpa); adpa_reg 437 drivers/gpu/drm/i915/display/intel_crt.c save_adpa = adpa = I915_READ(crt->adpa_reg); adpa_reg 444 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, adpa); adpa_reg 447 drivers/gpu/drm/i915/display/intel_crt.c crt->adpa_reg, adpa_reg 453 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, save_adpa); adpa_reg 454 drivers/gpu/drm/i915/display/intel_crt.c POSTING_READ(crt->adpa_reg); adpa_reg 459 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); adpa_reg 493 drivers/gpu/drm/i915/display/intel_crt.c save_adpa = adpa = I915_READ(crt->adpa_reg); adpa_reg 498 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, adpa); adpa_reg 500 drivers/gpu/drm/i915/display/intel_crt.c if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, adpa_reg 503 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, save_adpa); adpa_reg 507 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); adpa_reg 913 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); adpa_reg 916 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(crt->adpa_reg, adpa); adpa_reg 917 drivers/gpu/drm/i915/display/intel_crt.c POSTING_READ(crt->adpa_reg); adpa_reg 954 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg; adpa_reg 958 drivers/gpu/drm/i915/display/intel_crt.c adpa_reg = PCH_ADPA; adpa_reg 960 drivers/gpu/drm/i915/display/intel_crt.c adpa_reg = VLV_ADPA; adpa_reg 962 drivers/gpu/drm/i915/display/intel_crt.c adpa_reg = ADPA; adpa_reg 964 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(adpa_reg); adpa_reg 974 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | adpa_reg 976 drivers/gpu/drm/i915/display/intel_crt.c if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) adpa_reg 978 drivers/gpu/drm/i915/display/intel_crt.c I915_WRITE(adpa_reg, adpa); adpa_reg 1014 drivers/gpu/drm/i915/display/intel_crt.c crt->adpa_reg = adpa_reg; adpa_reg 17 drivers/gpu/drm/i915/display/intel_crt.h i915_reg_t adpa_reg, enum pipe *pipe);