adpa               93 drivers/gpu/drm/gma500/cdv_intel_crt.c 	u32 adpa, dpll_md;
adpa              113 drivers/gpu/drm/gma500/cdv_intel_crt.c 	adpa = 0;
adpa              115 drivers/gpu/drm/gma500/cdv_intel_crt.c 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
adpa              117 drivers/gpu/drm/gma500/cdv_intel_crt.c 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
adpa              120 drivers/gpu/drm/gma500/cdv_intel_crt.c 		adpa |= ADPA_PIPE_A_SELECT;
adpa              122 drivers/gpu/drm/gma500/cdv_intel_crt.c 		adpa |= ADPA_PIPE_B_SELECT;
adpa              124 drivers/gpu/drm/gma500/cdv_intel_crt.c 	REG_WRITE(adpa_reg, adpa);
adpa              166 drivers/gpu/drm/i915/display/intel_crt.c 	u32 adpa;
adpa              169 drivers/gpu/drm/i915/display/intel_crt.c 		adpa = ADPA_HOTPLUG_BITS;
adpa              171 drivers/gpu/drm/i915/display/intel_crt.c 		adpa = 0;
adpa              174 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
adpa              176 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
adpa              182 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
adpa              184 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_PIPE_SEL(crtc->pipe);
adpa              191 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_DAC_ENABLE;
adpa              194 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
adpa              197 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
adpa              200 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
adpa              204 drivers/gpu/drm/i915/display/intel_crt.c 	I915_WRITE(crt->adpa_reg, adpa);
adpa              427 drivers/gpu/drm/i915/display/intel_crt.c 	u32 adpa;
adpa              437 drivers/gpu/drm/i915/display/intel_crt.c 		save_adpa = adpa = I915_READ(crt->adpa_reg);
adpa              438 drivers/gpu/drm/i915/display/intel_crt.c 		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa              440 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
adpa              442 drivers/gpu/drm/i915/display/intel_crt.c 			adpa &= ~ADPA_DAC_ENABLE;
adpa              444 drivers/gpu/drm/i915/display/intel_crt.c 		I915_WRITE(crt->adpa_reg, adpa);
adpa              459 drivers/gpu/drm/i915/display/intel_crt.c 	adpa = I915_READ(crt->adpa_reg);
adpa              460 drivers/gpu/drm/i915/display/intel_crt.c 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
adpa              464 drivers/gpu/drm/i915/display/intel_crt.c 	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
adpa              475 drivers/gpu/drm/i915/display/intel_crt.c 	u32 adpa;
adpa              493 drivers/gpu/drm/i915/display/intel_crt.c 	save_adpa = adpa = I915_READ(crt->adpa_reg);
adpa              494 drivers/gpu/drm/i915/display/intel_crt.c 	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa              496 drivers/gpu/drm/i915/display/intel_crt.c 	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
adpa              498 drivers/gpu/drm/i915/display/intel_crt.c 	I915_WRITE(crt->adpa_reg, adpa);
adpa              507 drivers/gpu/drm/i915/display/intel_crt.c 	adpa = I915_READ(crt->adpa_reg);
adpa              508 drivers/gpu/drm/i915/display/intel_crt.c 	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
adpa              513 drivers/gpu/drm/i915/display/intel_crt.c 	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
adpa              911 drivers/gpu/drm/i915/display/intel_crt.c 		u32 adpa;
adpa              913 drivers/gpu/drm/i915/display/intel_crt.c 		adpa = I915_READ(crt->adpa_reg);
adpa              914 drivers/gpu/drm/i915/display/intel_crt.c 		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
adpa              915 drivers/gpu/drm/i915/display/intel_crt.c 		adpa |= ADPA_HOTPLUG_BITS;
adpa              916 drivers/gpu/drm/i915/display/intel_crt.c 		I915_WRITE(crt->adpa_reg, adpa);
adpa              919 drivers/gpu/drm/i915/display/intel_crt.c 		DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
adpa              955 drivers/gpu/drm/i915/display/intel_crt.c 	u32 adpa;
adpa              964 drivers/gpu/drm/i915/display/intel_crt.c 	adpa = I915_READ(adpa_reg);
adpa              965 drivers/gpu/drm/i915/display/intel_crt.c 	if ((adpa & ADPA_DAC_ENABLE) == 0) {
adpa              974 drivers/gpu/drm/i915/display/intel_crt.c 		I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
adpa              978 drivers/gpu/drm/i915/display/intel_crt.c 		I915_WRITE(adpa_reg, adpa);
adpa              200 drivers/video/fbdev/intelfb/intelfb.h 	u32 adpa;
adpa              575 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa = INREG(ADPA);
adpa              803 drivers/video/fbdev/intelfb/intelfbhw.c 	printk("	ADPA:			0x%08x\n", hw->adpa);
adpa             1086 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
adpa             1093 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
adpa             1095 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
adpa             1099 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
adpa             1100 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
adpa             1103 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
adpa             1104 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa |= ADPA_DPMS_D0;
adpa             1106 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->adpa |= ADPA_DAC_ENABLE;
adpa             1418 drivers/video/fbdev/intelfb/intelfbhw.c 	OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);