adj_mode          680 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 			     const struct drm_display_mode *adj_mode)
adj_mode          690 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		hsync_offset = adj_mode->crtc_hsync_start -
adj_mode          691 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 			       adj_mode->crtc_hdisplay;
adj_mode          692 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		vsync_offset = adj_mode->crtc_vsync_start -
adj_mode          693 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 			       adj_mode->crtc_vdisplay;
adj_mode          694 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		hsync_len = adj_mode->crtc_hsync_end -
adj_mode          695 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 			    adj_mode->crtc_hsync_start;
adj_mode          696 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		vsync_len = adj_mode->crtc_vsync_end -
adj_mode          697 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 			    adj_mode->crtc_vsync_start;
adj_mode          718 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		hsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PHSYNC);
adj_mode          719 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		vsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PVSYNC);
adj_mode          729 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC)
adj_mode          734 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC)
adj_mode          765 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 		adv7533_mode_set(adv7511, adj_mode);
adj_mode          767 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 	drm_mode_copy(&adv7511->curr_mode, adj_mode);
adj_mode          843 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 				    const struct drm_display_mode *adj_mode)
adj_mode          847 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 	adv7511_mode_set(adv, mode, adj_mode);
adj_mode           74 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c 				   struct drm_display_mode *adj_mode)
adj_mode          645 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	struct drm_display_mode adj_mode;
adj_mode          659 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 		drm_mode_copy(&adj_mode, mode);
adj_mode          663 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 			if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
adj_mode          666 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 		ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
adj_mode          675 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 				 struct drm_display_mode *adj_mode)
adj_mode          679 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 	drm_mode_copy(&dsi->cur_mode, adj_mode);
adj_mode          155 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 			    struct drm_display_mode *adj_mode)
adj_mode          167 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
adj_mode          172 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 			     struct drm_display_mode *adj_mode)
adj_mode          214 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	ade_set_pix_clk(ctx, mode, adj_mode);
adj_mode          480 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
adj_mode          484 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	ade_ldi_set_mode(ctx, mode, adj_mode);
adj_mode          493 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
adj_mode          497 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 	ade_ldi_set_mode(ctx, mode, adj_mode);
adj_mode          403 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	struct drm_display_mode *adj_mode = &state->adjusted_mode;
adj_mode          404 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
adj_mode          412 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		r->y2 = adj_mode->vdisplay;
adj_mode          417 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	drm_mode_debug_printmodeline(adj_mode);
adj_mode          508 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		struct drm_display_mode *adj_mode)
adj_mode          512 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (!connector || !adj_mode)
adj_mode          516 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		if (cur_mode->vdisplay == adj_mode->vdisplay &&
adj_mode          517 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		    cur_mode->hdisplay == adj_mode->hdisplay &&
adj_mode          518 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		    drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) {
adj_mode          519 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			adj_mode->private = cur_mode->private;
adj_mode          520 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			adj_mode->private_flags |= cur_mode->private_flags;
adj_mode          553 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct drm_display_mode *adj_mode;
adj_mode          570 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	adj_mode = &crtc_state->adjusted_mode;
adj_mode          580 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	_dpu_encoder_adjust_mode(conn_state->connector, adj_mode);
adj_mode          590 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			if (!phys->ops.mode_fixup(phys, mode, adj_mode))
adj_mode          600 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
adj_mode          616 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags,
adj_mode          617 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			adj_mode->private_flags);
adj_mode          946 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				      struct drm_display_mode *adj_mode)
adj_mode          992 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
adj_mode         1079 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				phys->ops.mode_set(phys, mode, adj_mode);
adj_mode           46 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		struct drm_display_mode *adj_mode)
adj_mode          179 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		struct drm_display_mode *adj_mode)
adj_mode          184 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !mode || !adj_mode) {
adj_mode          188 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	phys_enc->cached_mode = *adj_mode;
adj_mode          190 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	drm_mode_debug_printmodeline(adj_mode);
adj_mode          221 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		struct drm_display_mode *adj_mode)
adj_mode          375 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		struct drm_display_mode *adj_mode)
adj_mode          382 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (adj_mode) {
adj_mode          383 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		phys_enc->cached_mode = *adj_mode;
adj_mode          384 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		drm_mode_debug_printmodeline(adj_mode);
adj_mode          251 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 				    struct drm_display_mode *adj_mode)
adj_mode          258 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 					      struct drm_display_mode *adj_mode)
adj_mode          262 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 	clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
adj_mode          483 drivers/gpu/drm/rockchip/inno_hdmi.c 				       struct drm_display_mode *adj_mode)
adj_mode          487 drivers/gpu/drm/rockchip/inno_hdmi.c 	inno_hdmi_setup(hdmi, adj_mode);
adj_mode          490 drivers/gpu/drm/rockchip/inno_hdmi.c 	memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
adj_mode          509 drivers/gpu/drm/rockchip/inno_hdmi.c 					 struct drm_display_mode *adj_mode)
adj_mode          380 drivers/gpu/drm/rockchip/rk3066_hdmi.c 			     struct drm_display_mode *adj_mode)
adj_mode          385 drivers/gpu/drm/rockchip/rk3066_hdmi.c 	memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
adj_mode          427 drivers/gpu/drm/rockchip/rk3066_hdmi.c 			       struct drm_display_mode *adj_mode)
adj_mode           19 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c 					   struct drm_display_mode *adj_mode)
adj_mode          141 drivers/gpu/drm/zte/zx_hdmi.c 				     struct drm_display_mode *adj_mode)
adj_mode          149 drivers/gpu/drm/zte/zx_tvenc.c 				      struct drm_display_mode *adj_mode)
adj_mode           33 drivers/video/backlight/tdo24m.c 	int (*adj_mode)(struct tdo24m *lcd, int mode);
adj_mode          271 drivers/video/backlight/tdo24m.c 	err = lcd->adj_mode(lcd, lcd->mode);
adj_mode          322 drivers/video/backlight/tdo24m.c 	return lcd->adj_mode(lcd, mode);
adj_mode          376 drivers/video/backlight/tdo24m.c 		lcd->adj_mode = tdo24m_adj_mode;
adj_mode          379 drivers/video/backlight/tdo24m.c 		lcd->adj_mode = tdo35s_adj_mode;