acr 143 arch/arm/mach-omap2/omap-secure.c u32 acr; acr 146 arch/arm/mach-omap2/omap-secure.c asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr 147 arch/arm/mach-omap2/omap-secure.c acr &= ~clear_bits; acr 148 arch/arm/mach-omap2/omap-secure.c acr |= set_bits; acr 153 arch/arm/mach-omap2/omap-secure.c 1, acr, 0, 0, 0); acr 77 arch/arm/mach-omap2/omap-smp.c u32 acr, revidr; acr 85 arch/arm/mach-omap2/omap-smp.c asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr 94 arch/arm/mach-omap2/omap-smp.c if ((acr & acr_mask) == acr_mask) acr 97 arch/arm/mach-omap2/omap-smp.c acr |= acr_mask; acr 98 arch/arm/mach-omap2/omap-smp.c omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); acr 123 arch/arm/mach-omap2/omap-smp.c u32 acr, acr_mask; acr 125 arch/arm/mach-omap2/omap-smp.c asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr 133 arch/arm/mach-omap2/omap-smp.c if ((acr & acr_mask) == acr_mask) acr 136 arch/arm/mach-omap2/omap-smp.c acr |= acr_mask; acr 137 arch/arm/mach-omap2/omap-smp.c omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); acr 625 arch/arm/mm/cache-l2x0.c u32 acr = get_auxcr(); acr 627 arch/arm/mm/cache-l2x0.c pr_debug("Cortex-A9 ACR=0x%08x\n", acr); acr 629 arch/arm/mm/cache-l2x0.c if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO)) acr 632 arch/arm/mm/cache-l2x0.c if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3))) acr 177 arch/powerpc/include/asm/mpc52xx_psc.h u8 acr; acr 180 arch/powerpc/include/asm/mpc52xx_psc.h #define mpc52xx_psc_acr ipcr_acr.acr acr 324 arch/powerpc/include/asm/mpc52xx_psc.h u8 acr; /* PSC + 0x1c */ acr 1832 drivers/atm/iphase.c vc->acr = cellrate_to_float(iadev->LineRate); acr 1834 drivers/atm/iphase.c vc->acr = cellrate_to_float(vcc->qos.txtp.pcr); acr 1836 drivers/atm/iphase.c vcc->qos.txtp.max_pcr,vc->acr);) acr 255 drivers/atm/iphase.h u_short acr; acr 1469 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); acr 1475 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); acr 1478 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); acr 1482 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); acr 1485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); acr 1489 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); acr 1492 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); acr 1511 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); acr 1517 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); acr 1520 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); acr 1524 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); acr 1527 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); acr 1531 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); acr 1534 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); acr 1395 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); acr 1407 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); acr 1410 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); acr 1414 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); acr 1417 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); acr 1421 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); acr 1424 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); acr 1432 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); acr 1437 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT)); acr 1438 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); acr 1440 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); acr 1441 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); acr 1443 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); acr 1444 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); acr 45 drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h struct nvkm_acr *acr; acr 76 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, acr 243 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_ls_ucode_img_load(const struct acr_r352 *acr, acr 247 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct nvkm_subdev *subdev = acr->base.subdev; acr 248 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct acr_r352_ls_func *func = acr->func->ls_func[falcon_id]; acr 302 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_ls_img_fill_headers(struct acr_r352 *acr, acr 313 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c whdr->bootstrap_owner = acr->base.boot_falcon; acr 317 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->lazy_bootstrap & BIT(_img->falcon_id)) acr 361 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (_img->falcon_id == acr->base.boot_falcon) acr 381 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) acr 405 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c offset = acr_r352_ls_img_fill_headers(acr, img, offset); acr 415 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, acr 449 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); acr 481 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_prepare_ls_blob(struct acr_r352 *acr, struct nvkm_secboot *sb) acr 483 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct nvkm_subdev *subdev = acr->base.subdev; acr 486 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c unsigned long managed_falcons = acr->base.managed_falcons; acr 500 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c img = acr->func->ls_ucode_img_load(acr, sb, falcon_id); acr 502 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->base.optional_falcons & BIT(falcon_id)) { acr 517 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.managed_falcons = managed_falcons; acr 523 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->func->ls_func[acr->base.boot_falcon] && acr 524 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c (managed_falcons & BIT(acr->base.boot_falcon))) { acr 527 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (falcon_id == acr->base.boot_falcon) acr 530 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->lazy_bootstrap |= BIT(falcon_id); acr 538 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c image_wpr_size = acr->func->ls_fill_headers(acr, &imgs); acr 547 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (wpr_size == 0 && acr->func->shadow_blob) acr 552 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c false, NULL, &acr->ls_blob); acr 561 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_addr = acr->ls_blob->addr; acr 562 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->func->shadow_blob) acr 563 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_addr += acr->ls_blob->size / 2; acr 579 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr); acr 581 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_gpuobj_del(&acr->ls_blob); acr 597 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, acr 601 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct nvkm_gpuobj *ls_blob = acr->ls_blob; acr 653 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb, acr 679 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->func->fixup_hs_desc(acr, sb, desc); acr 715 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb) acr 721 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->firmware_ok) acr 725 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_prepare_ls_blob(acr, sb); acr 730 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (!acr->load_blob) { acr 731 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_load", acr 732 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c &acr->load_blob, acr 733 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c &acr->load_bl_header, true); acr 740 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_unload", acr 741 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c &acr->unload_blob, acr 742 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c &acr->unload_bl_header, false); acr 748 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (!acr->hsbl_blob) { acr 749 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->hsbl_blob = nvkm_acr_load_firmware(subdev, "acr/bl", 0); acr 750 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (IS_ERR(acr->hsbl_blob)) { acr 751 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = PTR_ERR(acr->hsbl_blob); acr 752 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->hsbl_blob = NULL; acr 756 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->base.boot_falcon != NVKM_SECBOOT_FALCON_PMU) { acr 757 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->hsbl_unload_blob = nvkm_acr_load_firmware(subdev, acr 759 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (IS_ERR(acr->hsbl_unload_blob)) { acr 760 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = PTR_ERR(acr->hsbl_unload_blob); acr 761 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->hsbl_unload_blob = NULL; acr 765 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->hsbl_unload_blob = acr->hsbl_blob; acr 769 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->firmware_ok = true; acr 784 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct acr_r352 *acr = acr_r352(_acr); acr 785 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const u32 bl_desc_size = acr->func->hs_bl_desc_size; acr 798 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (blob == acr->load_blob) { acr 799 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c load_hdr = &acr->load_bl_header; acr 800 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c bl = acr->hsbl_blob; acr 801 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c } else if (blob == acr->unload_blob) { acr 802 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c load_hdr = &acr->unload_bl_header; acr 803 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c bl = acr->hsbl_unload_blob; acr 827 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); acr 840 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_shutdown(struct acr_r352 *acr, struct nvkm_secboot *sb) acr 846 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->unload_blob && sb->wpr_set) { acr 850 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = sb->func->run_blob(sb, acr->unload_blob, sb->halt_falcon); acr 865 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->falcon_state[i] = NON_SECURE; acr 877 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_wpr_is_set(const struct acr_r352 *acr, const struct nvkm_secboot *sb) acr 895 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_range_lo = acr->ls_blob->addr; acr 896 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c wpr_range_hi = wpr_range_lo + acr->ls_blob->size; acr 904 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) acr 907 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c unsigned long managed_falcons = acr->base.managed_falcons; acr 915 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_load_blobs(acr, sb); acr 920 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = sb->func->run_blob(sb, acr->load_blob, sb->boot_falcon); acr 923 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c sb->wpr_set = acr_r352_wpr_is_set(acr, sb); acr 940 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->func->ls_func[falcon_id]; acr 943 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = func->post_run(&acr->base, sb); acr 959 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_reset_nopmu(struct acr_r352 *acr, struct nvkm_secboot *sb, acr 972 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_shutdown(acr, sb); acr 976 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_bootstrap(acr, sb); acr 982 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->falcon_state[falcon] = RESET; acr 998 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct acr_r352 *acr = acr_r352(_acr); acr 1005 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = acr_r352_bootstrap(acr, sb); acr 1013 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c return acr_r352_reset_nopmu(acr, sb, falcon_mask); acr 1047 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct acr_r352 *acr = acr_r352(_acr); acr 1049 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c return acr_r352_shutdown(acr, sb); acr 1055 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct acr_r352 *acr = acr_r352(_acr); acr 1057 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_gpuobj_del(&acr->unload_blob); acr 1060 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c kfree(acr->hsbl_unload_blob); acr 1061 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c kfree(acr->hsbl_blob); acr 1062 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_gpuobj_del(&acr->load_blob); acr 1063 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_gpuobj_del(&acr->ls_blob); acr 1065 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c kfree(acr); acr 1138 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_generate_pmu_bl_desc(const struct nvkm_acr *acr, acr 1143 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct nvkm_pmu *pmu = acr->subdev->device->pmu; acr 1215 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct acr_r352 *acr; acr 1224 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr = kzalloc(sizeof(*acr), GFP_KERNEL); acr 1225 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (!acr) acr 1228 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.boot_falcon = boot_falcon; acr 1229 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.managed_falcons = managed_falcons; acr 1230 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.func = &acr_r352_base_func; acr 1231 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->func = func; acr 1233 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c return &acr->base; acr 153 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h #define acr_r352(acr) container_of(acr, struct acr_r352, base) acr 31 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, acr 116 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c acr_r361_generate_pmu_bl_desc(const struct nvkm_acr *acr, acr 121 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c const struct nvkm_pmu *pmu = acr->subdev->device->pmu; acr 161 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c acr_r361_generate_sec2_bl_desc(const struct nvkm_acr *acr, acr 166 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c const struct nvkm_sec2 *sec = acr->subdev->device->sec2; acr 63 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c acr_r364_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, acr 67 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c struct nvkm_gpuobj *ls_blob = acr->ls_blob; acr 74 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c if (acr->func->shadow_blob) acr 85 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r364.c if (acr->func->shadow_blob) acr 112 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c acr_r367_ls_ucode_img_load(const struct acr_r352 *acr, acr 116 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c const struct nvkm_subdev *subdev = acr->base.subdev; acr 117 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c const struct acr_r352_ls_func *func = acr->func->ls_func[falcon_id]; acr 160 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c acr_r367_ls_img_fill_headers(struct acr_r352 *acr, acr 171 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c whdr->bootstrap_owner = acr->base.boot_falcon; acr 176 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (acr->lazy_bootstrap & BIT(_img->falcon_id)) acr 220 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (_img->falcon_id == acr->base.boot_falcon) acr 237 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c acr_r367_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) acr 261 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c offset = acr_r367_ls_img_fill_headers(acr, img, offset); acr 268 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c acr_r367_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, acr 301 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); acr 352 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c acr_r367_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, acr 356 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c struct nvkm_gpuobj *ls_blob = acr->ls_blob; acr 363 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (acr->func->shadow_blob) acr 374 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (acr->func->shadow_blob) acr 31 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c acr_r370_generate_flcn_bl_desc(const struct nvkm_acr *acr, acr 85 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr, acr 90 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c const struct nvkm_sec2 *sec = acr->subdev->device->sec2; acr 30 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c acr_r375_generate_pmu_bl_desc(const struct nvkm_acr *acr, acr 35 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c const struct nvkm_pmu *pmu = acr->subdev->device->pmu; acr 108 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c if ((falcon_mask | sb->acr->managed_falcons) != sb->acr->managed_falcons) { acr 113 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c return sb->acr->func->reset(sb->acr, sb, falcon_mask); acr 125 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c return sb->acr->managed_falcons & BIT(fid); acr 134 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c switch (sb->acr->boot_falcon) { acr 146 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c nvkm_secboot_falcon_name[sb->acr->boot_falcon]); acr 195 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c nvkm_secboot_ctor(const struct nvkm_secboot_func *func, struct nvkm_acr *acr, acr 203 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c sb->acr = acr; acr 204 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c acr->subdev = &sb->subdev; acr 207 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c for_each_set_bit(fid, &sb->acr->managed_falcons, acr 68 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = sb->acr->func->load(sb->acr, falcon, blob, vma->addr); acr 129 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c if (sb->acr->func->oneinit) { acr 130 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = sb->acr->func->oneinit(sb->acr, sb); acr 143 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c if (sb->acr->func->fini) acr 144 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = sb->acr->func->fini(sb->acr, sb, suspend); acr 154 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c sb->acr->func->dtor(sb->acr); acr 178 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c struct nvkm_acr *acr; acr 180 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) | acr 182 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c if (IS_ERR(acr)) acr 183 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c return PTR_ERR(acr); acr 192 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base); acr 109 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c struct nvkm_acr *acr; acr 112 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | acr 114 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c if (IS_ERR(acr)) acr 115 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c return PTR_ERR(acr); acr 117 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU); acr 124 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base); acr 150 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c struct nvkm_acr *acr; acr 152 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c acr = acr_r367_new(NVKM_SECBOOT_FALCON_SEC2, acr 156 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c if (IS_ERR(acr)) acr 157 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c return PTR_ERR(acr); acr 166 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c ret = nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); acr 30 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c struct nvkm_acr *acr; acr 32 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c acr = acr_r370_new(NVKM_SECBOOT_FALCON_SEC2, acr 36 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c if (IS_ERR(acr)) acr 37 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c return PTR_ERR(acr); acr 40 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c acr->func->dtor(acr); acr 45 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c return nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); acr 55 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c struct nvkm_acr *acr; acr 57 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) | acr 60 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c if (IS_ERR(acr)) acr 61 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c return PTR_ERR(acr); acr 70 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c ret = nvkm_secboot_ctor(&gp10b_secboot, acr, device, index, &gsb->base); acr 122 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c acr_ls_pmu_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) acr 134 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_secboot_falcon_name[acr->boot_falcon]); acr 160 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb) acr 174 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_secboot_falcon_name[acr->boot_falcon]); acr 171 drivers/gpu/drm/radeon/dce3_1_afmt.c const struct radeon_hdmi_acr *acr) acr 181 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_CTS_32(acr->cts_32khz), acr 184 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_N_32(acr->n_32khz), acr 188 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_CTS_44(acr->cts_44_1khz), acr 191 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_N_44(acr->n_44_1khz), acr 195 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_CTS_48(acr->cts_48khz), acr 198 drivers/gpu/drm/radeon/dce3_1_afmt.c HDMI0_ACR_N_48(acr->n_48khz), acr 68 drivers/gpu/drm/radeon/evergreen_hdmi.c const struct radeon_hdmi_acr *acr) acr 87 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); acr 88 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); acr 90 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); acr 91 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); acr 93 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); acr 94 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); acr 178 drivers/gpu/drm/radeon/r600_hdmi.c const struct radeon_hdmi_acr *acr) acr 193 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_CTS_32(acr->cts_32khz), acr 196 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_N_32(acr->n_32khz), acr 200 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_CTS_44(acr->cts_44_1khz), acr 203 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_N_44(acr->n_44_1khz), acr 207 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_CTS_48(acr->cts_48khz), acr 210 drivers/gpu/drm/radeon/r600_hdmi.c HDMI0_ACR_N_48(acr->n_48khz), acr 83 drivers/gpu/drm/radeon/radeon_audio.c const struct radeon_hdmi_acr *acr); acr 85 drivers/gpu/drm/radeon/radeon_audio.c const struct radeon_hdmi_acr *acr); acr 87 drivers/gpu/drm/radeon/radeon_audio.c const struct radeon_hdmi_acr *acr); acr 624 drivers/gpu/drm/radeon/radeon_audio.c const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); acr 632 drivers/gpu/drm/radeon/radeon_audio.c radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); acr 57 drivers/gpu/drm/radeon/radeon_audio.h const struct radeon_hdmi_acr *acr); acr 565 drivers/iio/adc/at91-sama5d2_adc.c u32 tsmr, acr; acr 599 drivers/iio/adc/at91-sama5d2_adc.c acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); acr 600 drivers/iio/adc/at91-sama5d2_adc.c acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; acr 601 drivers/iio/adc/at91-sama5d2_adc.c acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; acr 602 drivers/iio/adc/at91-sama5d2_adc.c at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); acr 338 drivers/ipack/devices/ipoctal.c iowrite8(ACR_BRG_SET2, &block_regs[i].w.acr); acr 70 drivers/ipack/devices/scc2698.h u8 d4, acr; /* Auxiliary control register of block */ acr 376 drivers/power/supply/ds2760_battery.c unsigned char acr[2]; acr 382 drivers/power/supply/ds2760_battery.c acr[0] = acr_val >> 8; acr 383 drivers/power/supply/ds2760_battery.c acr[1] = acr_val & 0xff; acr 385 drivers/power/supply/ds2760_battery.c if (w1_ds2760_write(di->dev, acr, DS2760_CURRENT_ACCUM_MSB, 2) < 2) acr 543 drivers/tty/serial/8250/8250_port.c serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); acr 546 drivers/tty/serial/8250/8250_port.c serial_icr_write(up, UART_ACR, up->acr); acr 898 drivers/tty/serial/8250/8250_port.c up->acr = 0; acr 1499 drivers/tty/serial/8250/8250_port.c up->acr |= UART_ACR_TXDIS; acr 1500 drivers/tty/serial/8250/8250_port.c serial_icr_write(up, UART_ACR, up->acr); acr 1526 drivers/tty/serial/8250/8250_port.c if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { acr 1527 drivers/tty/serial/8250/8250_port.c up->acr &= ~UART_ACR_TXDIS; acr 1528 drivers/tty/serial/8250/8250_port.c serial_icr_write(up, UART_ACR, up->acr); acr 2076 drivers/tty/serial/8250/8250_port.c up->acr = 0; acr 272 drivers/tty/serial/sccnxp.c u8 acr; acr 312 drivers/tty/serial/sccnxp.c u8 i, acr = 0, csr = 0, mr0 = 0; acr 333 drivers/tty/serial/sccnxp.c acr = baud_std[i].acr; acr 348 drivers/tty/serial/sccnxp.c sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); acr 90 drivers/tty/serial/sunsu.c unsigned char acr; acr 180 drivers/tty/serial/sunsu.c serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); acr 183 drivers/tty/serial/sunsu.c serial_icr_write(up, UART_ACR, up->acr); acr 277 drivers/tty/serial/sunsu.c up->acr |= UART_ACR_TXDIS; acr 278 drivers/tty/serial/sunsu.c serial_icr_write(up, UART_ACR, up->acr); acr 295 drivers/tty/serial/sunsu.c if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { acr 296 drivers/tty/serial/sunsu.c up->acr &= ~UART_ACR_TXDIS; acr 297 drivers/tty/serial/sunsu.c serial_icr_write(up, UART_ACR, up->acr); acr 628 drivers/tty/serial/sunsu.c up->acr = 0; acr 111 drivers/video/fbdev/cg14.c u8 acr; /* Aux Control */ acr 100 include/linux/serial_8250.h unsigned char acr; acr 93 sound/aoa/codecs/tas.c u8 acr; acr 491 sound/aoa/codecs/tas.c ucontrol->value.enumerated.item[0] = !!(tas->acr & TAS_ACR_INPUT_B); acr 505 sound/aoa/codecs/tas.c oldacr = tas->acr; acr 512 sound/aoa/codecs/tas.c tas->acr &= ~(TAS_ACR_INPUT_B | TAS_ACR_B_MONAUREAL); acr 514 sound/aoa/codecs/tas.c tas->acr |= TAS_ACR_INPUT_B | TAS_ACR_B_MONAUREAL | acr 516 sound/aoa/codecs/tas.c if (oldacr == tas->acr) { acr 521 sound/aoa/codecs/tas.c tas_write_reg(tas, TAS_REG_ACR, 1, &tas->acr); acr 689 sound/aoa/codecs/tas.c tas->acr |= TAS_ACR_ANALOG_PDOWN; acr 690 sound/aoa/codecs/tas.c if (tas_write_reg(tas, TAS_REG_ACR, 1, &tas->acr)) acr 705 sound/aoa/codecs/tas.c tas->acr &= ~TAS_ACR_ANALOG_PDOWN; acr 706 sound/aoa/codecs/tas.c if (tas_write_reg(tas, TAS_REG_ACR, 1, &tas->acr)) acr 749 sound/aoa/codecs/tas.c tas->acr |= TAS_ACR_ANALOG_PDOWN; acr 750 sound/aoa/codecs/tas.c tas_write_reg(tas, TAS_REG_ACR, 1, &tas->acr); acr 221 sound/soc/sh/dma-sh7760.c unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); acr 223 sound/soc/sh/dma-sh7760.c BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD; acr 228 sound/soc/sh/dma-sh7760.c unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); acr 230 sound/soc/sh/dma-sh7760.c BRGREG(BRGACR) = acr | ACR_TDS; acr 235 sound/soc/sh/dma-sh7760.c unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); acr 237 sound/soc/sh/dma-sh7760.c BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD; acr 242 sound/soc/sh/dma-sh7760.c unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS); acr 244 sound/soc/sh/dma-sh7760.c BRGREG(BRGACR) = acr | ACR_RDS;