acq 56 arch/arm64/include/asm/atomic_ll_sc.h #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ acq 66 arch/arm64/include/asm/atomic_ll_sc.h "1: ld" #acq "xr %w0, %2\n" \ acq 78 arch/arm64/include/asm/atomic_ll_sc.h #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \ acq 88 arch/arm64/include/asm/atomic_ll_sc.h "1: ld" #acq "xr %w0, %3\n" \ acq 155 arch/arm64/include/asm/atomic_ll_sc.h #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ acq 165 arch/arm64/include/asm/atomic_ll_sc.h "1: ld" #acq "xr %0, %2\n" \ acq 177 arch/arm64/include/asm/atomic_ll_sc.h #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\ acq 187 arch/arm64/include/asm/atomic_ll_sc.h "1: ld" #acq "xr %0, %3\n" \ acq 259 arch/arm64/include/asm/atomic_ll_sc.h #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ acq 279 arch/arm64/include/asm/atomic_ll_sc.h "1: ld" #acq "xr" #sfx "\t%" #w "[oldval], %[v]\n" \ acq 21 arch/arm64/include/asm/cmpxchg.h #define __XCHG_CASE(w, sfx, name, sz, mb, nop_lse, acq, acq_lse, rel, cl) \ acq 30 arch/arm64/include/asm/cmpxchg.h "1: ld" #acq "xr" #sfx "\t%" #w "0, %2\n" \ acq 42 arch/ia64/include/asm/atomic.h } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \ acq 57 arch/ia64/include/asm/atomic.h } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old); \ acq 98 arch/ia64/include/asm/atomic.h ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \ acq 106 arch/ia64/include/asm/atomic.h ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \ acq 137 arch/ia64/include/asm/atomic.h } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \ acq 152 arch/ia64/include/asm/atomic.h } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); \ acq 183 arch/ia64/include/asm/atomic.h ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \ acq 191 arch/ia64/include/asm/atomic.h ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \ acq 47 arch/ia64/include/asm/spinlock.h ticket = ia64_fetchadd(1, p, acq); acq 68 arch/ia64/include/asm/spinlock.h return ia64_cmpxchg(acq, &lock->lock, tmp, tmp + 1, sizeof (tmp)) == tmp; acq 171 arch/ia64/include/asm/spinlock.h while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \ acq 116 arch/ia64/include/uapi/asm/cmpxchg.h ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) acq 4225 arch/ia64/kernel/perfmon.c old = ia64_cmpxchg(acq, &thread->pfm_context, NULL, ctx, sizeof(pfm_context_t *)); acq 249 arch/ia64/kernel/smp.c ia64_fetchadd(1, &local_tlb_flush_counts[smp_processor_id()].count, acq); acq 319 arch/ia64/kernel/traps.c if ((last.count & 15) < 5 && (ia64_fetchadd(1, &last.count, acq) & 15) < 5) { acq 125 arch/ia64/mm/tlb.c unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve; acq 330 drivers/net/wireless/ath/ath9k/ath9k.h struct ath_acq acq[IEEE80211_NUM_ACS]; acq 122 drivers/net/wireless/ath/ath9k/channel.c for (j = 0; j < ARRAY_SIZE(ctx->acq); j++) { acq 123 drivers/net/wireless/ath/ath9k/channel.c INIT_LIST_HEAD(&ctx->acq[j].acq_new); acq 124 drivers/net/wireless/ath/ath9k/channel.c INIT_LIST_HEAD(&ctx->acq[j].acq_old); acq 125 drivers/net/wireless/ath/ath9k/channel.c spin_lock_init(&ctx->acq[j].lock); acq 1352 drivers/net/wireless/ath/ath9k/channel.c for (i = 0; i < ARRAY_SIZE(ctx->acq); i++) { acq 1353 drivers/net/wireless/ath/ath9k/channel.c INIT_LIST_HEAD(&ctx->acq[i].acq_new); acq 1354 drivers/net/wireless/ath/ath9k/channel.c INIT_LIST_HEAD(&ctx->acq[i].acq_old); acq 1355 drivers/net/wireless/ath/ath9k/channel.c spin_lock_init(&ctx->acq[i].lock); acq 73 drivers/net/wireless/ath/ath9k/main.c struct ath_acq *acq; acq 75 drivers/net/wireless/ath/ath9k/main.c acq = &sc->cur_chan->acq[txq->mac80211_qnum]; acq 76 drivers/net/wireless/ath/ath9k/main.c if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))