ack_mask          100 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
ack_mask          114 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
ack_mask          128 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
ack_mask          143 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.ack_mask =\
ack_mask          159 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 		.ack_mask =\
ack_mask          114 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 	.ack_mask = \
ack_mask          103 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
ack_mask          117 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
ack_mask          132 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
ack_mask          147 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.ack_mask =\
ack_mask          163 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c 		.ack_mask =\
ack_mask          195 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c 	.ack_mask = \
ack_mask          197 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c 	.ack_mask = \
ack_mask          193 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c 	.ack_mask = \
ack_mask          134 drivers/gpu/drm/amd/display/dc/irq/irq_service.c 	value = (value & ~info->ack_mask) |
ack_mask          135 drivers/gpu/drm/amd/display/dc/irq/irq_service.c 		(info->ack_value & info->ack_mask);
ack_mask           53 drivers/gpu/drm/amd/display/dc/irq/irq_service.h 	uint32_t ack_mask;
ack_mask           16 drivers/soc/actions/owl-sps-helper.c int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable)
ack_mask           23 drivers/soc/actions/owl-sps-helper.c 	ack = val & ack_mask;
ack_mask           36 drivers/soc/actions/owl-sps-helper.c 		if ((val & ack_mask) == (enable ? ack_mask : 0))
ack_mask           49 drivers/soc/actions/owl-sps.c 	u32 pwr_mask, ack_mask;
ack_mask           51 drivers/soc/actions/owl-sps.c 	ack_mask = BIT(pd->info->ack_bit);
ack_mask           54 drivers/soc/actions/owl-sps.c 	return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
ack_mask           36 drivers/soc/rockchip/pm_domains.c 	int ack_mask;
ack_mask           94 drivers/soc/rockchip/pm_domains.c 	.ack_mask = (ack),				\
ack_mask          106 drivers/soc/rockchip/pm_domains.c 	.ack_mask = (ack),				\
ack_mask          114 drivers/soc/rockchip/pm_domains.c 	.ack_mask = (ack),				\
ack_mask          176 drivers/soc/rockchip/pm_domains.c 	target_ack = idle ? pd_info->ack_mask : 0;
ack_mask          178 drivers/soc/rockchip/pm_domains.c 					(val & pd_info->ack_mask) == target_ack,
ack_mask            9 include/linux/soc/actions/owl-sps.h int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);