access_one_channel_only  389 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 		DC_LOG_BANDWIDTH_CALCS("	[bool] access_one_channel_only[%d]:%d", i, data->access_one_channel_only[i]);
access_one_channel_only  280 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[0] = 0;
access_one_channel_only  281 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[1] = 0;
access_one_channel_only  282 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[2] = 0;
access_one_channel_only  283 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[3] = 0;
access_one_channel_only  334 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->access_one_channel_only[i] = data->lpt_en[i];
access_one_channel_only  338 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->access_one_channel_only[i] = 0;
access_one_channel_only  379 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
access_one_channel_only  380 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
access_one_channel_only  369 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	bool access_one_channel_only[maximum_number_of_surfaces];