a_hash           4278 drivers/crypto/chelsio/chcr_algo.c 	struct ahash_alg *a_hash;
a_hash           4314 drivers/crypto/chelsio/chcr_algo.c 			a_hash = &driver_algs[i].alg.hash;
a_hash           4315 drivers/crypto/chelsio/chcr_algo.c 			a_hash->update = chcr_ahash_update;
a_hash           4316 drivers/crypto/chelsio/chcr_algo.c 			a_hash->final = chcr_ahash_final;
a_hash           4317 drivers/crypto/chelsio/chcr_algo.c 			a_hash->finup = chcr_ahash_finup;
a_hash           4318 drivers/crypto/chelsio/chcr_algo.c 			a_hash->digest = chcr_ahash_digest;
a_hash           4319 drivers/crypto/chelsio/chcr_algo.c 			a_hash->export = chcr_ahash_export;
a_hash           4320 drivers/crypto/chelsio/chcr_algo.c 			a_hash->import = chcr_ahash_import;
a_hash           4321 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.statesize = SZ_AHASH_REQ_CTX;
a_hash           4322 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.base.cra_priority = CHCR_CRA_PRIORITY;
a_hash           4323 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.base.cra_module = THIS_MODULE;
a_hash           4324 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC;
a_hash           4325 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.base.cra_alignmask = 0;
a_hash           4326 drivers/crypto/chelsio/chcr_algo.c 			a_hash->halg.base.cra_exit = NULL;
a_hash           4329 drivers/crypto/chelsio/chcr_algo.c 				a_hash->halg.base.cra_init = chcr_hmac_cra_init;
a_hash           4330 drivers/crypto/chelsio/chcr_algo.c 				a_hash->halg.base.cra_exit = chcr_hmac_cra_exit;
a_hash           4331 drivers/crypto/chelsio/chcr_algo.c 				a_hash->init = chcr_hmac_init;
a_hash           4332 drivers/crypto/chelsio/chcr_algo.c 				a_hash->setkey = chcr_ahash_setkey;
a_hash           4333 drivers/crypto/chelsio/chcr_algo.c 				a_hash->halg.base.cra_ctxsize = SZ_AHASH_H_CTX;
a_hash           4335 drivers/crypto/chelsio/chcr_algo.c 				a_hash->init = chcr_sha_init;
a_hash           4336 drivers/crypto/chelsio/chcr_algo.c 				a_hash->halg.base.cra_ctxsize = SZ_AHASH_CTX;
a_hash           4337 drivers/crypto/chelsio/chcr_algo.c 				a_hash->halg.base.cra_init = chcr_sha_cra_init;
a_hash            575 drivers/infiniband/core/iwpm_util.c 	u32 a_hash, b_hash;
a_hash            578 drivers/infiniband/core/iwpm_util.c 		a_hash = iwpm_ipv4_jhash((struct sockaddr_in *) a_sockaddr);
a_hash            582 drivers/infiniband/core/iwpm_util.c 		a_hash = iwpm_ipv6_jhash((struct sockaddr_in6 *) a_sockaddr);
a_hash            589 drivers/infiniband/core/iwpm_util.c 	if (a_hash == b_hash) /* if port mapper isn't available */
a_hash            590 drivers/infiniband/core/iwpm_util.c 		*hash = a_hash;
a_hash            592 drivers/infiniband/core/iwpm_util.c 		*hash = jhash_2words(a_hash, b_hash, 0);