_width 29 drivers/clk/actions/owl-divider.h #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ _width 33 drivers/clk/actions/owl-divider.h .width = _width, \ _width 39 drivers/clk/actions/owl-divider.h _shift, _width, _table, _div_flags, _flags) \ _width 41 drivers/clk/actions/owl-divider.h .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \ _width 35 drivers/clk/actions/owl-factor.h #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ _width 39 drivers/clk/actions/owl-factor.h .width = _width, \ _width 45 drivers/clk/actions/owl-factor.h _shift, _width, _table, _fct_flags, _flags) \ _width 48 drivers/clk/actions/owl-factor.h _width, _fct_flags, _table), \ _width 27 drivers/clk/actions/owl-mux.h #define OWL_MUX_HW(_reg, _shift, _width) \ _width 31 drivers/clk/actions/owl-mux.h .width = _width, \ _width 35 drivers/clk/actions/owl-mux.h _shift, _width, _flags) \ _width 37 drivers/clk/actions/owl-mux.h .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \ _width 42 drivers/clk/actions/owl-pll.h _width, _min_mul, _max_mul, _delay, _table) \ _width 48 drivers/clk/actions/owl-pll.h .width = _width, \ _width 56 drivers/clk/actions/owl-pll.h _shift, _width, _min_mul, _max_mul, _table, _flags) \ _width 59 drivers/clk/actions/owl-pll.h _width, _min_mul, _max_mul, \ _width 71 drivers/clk/actions/owl-pll.h _shift, _width, _min_mul, _max_mul, _table, _flags) \ _width 74 drivers/clk/actions/owl-pll.h _width, _min_mul, _max_mul, \ _width 85 drivers/clk/actions/owl-pll.h _shift, _width, _min_mul, _max_mul, _delay, _table, \ _width 89 drivers/clk/actions/owl-pll.h _width, _min_mul, _max_mul, \ _width 299 drivers/clk/bcm/clk-kona.h #define DIVIDER(_offset, _shift, _width) \ _width 303 drivers/clk/bcm/clk-kona.h .u.s.width = (_width), \ _width 309 drivers/clk/bcm/clk-kona.h #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ _width 313 drivers/clk/bcm/clk-kona.h .u.s.width = (_width), \ _width 350 drivers/clk/bcm/clk-kona.h #define SELECTOR(_offset, _shift, _width) \ _width 354 drivers/clk/bcm/clk-kona.h .width = (_width), \ _width 1119 drivers/clk/clk-stm32mp1.c #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ _width 1129 drivers/clk/clk-stm32mp1.c .width = _width,\ _width 1136 drivers/clk/clk-stm32mp1.c #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ _width 1137 drivers/clk/clk-stm32mp1.c DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ _width 1140 drivers/clk/clk-stm32mp1.c #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ _width 1150 drivers/clk/clk-stm32mp1.c .width = _width,\ _width 1246 drivers/clk/clk-stm32mp1.c #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ _width 1251 drivers/clk/clk-stm32mp1.c .width = _width,\ _width 1259 drivers/clk/clk-stm32mp1.c #define _MUX(_offset, _shift, _width, _mux_flags)\ _width 1260 drivers/clk/clk-stm32mp1.c _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\ _width 1597 drivers/clk/clk-stm32mp1.c #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ _width 1602 drivers/clk/clk-stm32mp1.c .width = _width,\ _width 1610 drivers/clk/clk-stm32mp1.c #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ _width 1611 drivers/clk/clk-stm32mp1.c _K_MUX(_id, _offset, _shift, _width, _mux_flags,\ _width 1614 drivers/clk/clk-stm32mp1.c #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ _width 1615 drivers/clk/clk-stm32mp1.c _K_MUX(_id, _offset, _shift, _width, _mux_flags,\ _width 467 drivers/clk/mediatek/clk-mt8516.c #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ _width 473 drivers/clk/mediatek/clk-mt8516.c .div_width = _width, \ _width 82 drivers/clk/mediatek/clk-mtk.h _width, _gate, _flags, _muxflags) { \ _width 87 drivers/clk/mediatek/clk-mtk.h .mux_width = _width, \ _width 101 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _width 104 drivers/clk/mediatek/clk-mtk.h _shift, _width, _gate, _flags, 0) _width 110 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ _width 111 drivers/clk/mediatek/clk-mtk.h MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _width 114 drivers/clk/mediatek/clk-mtk.h #define MUX(_id, _name, _parents, _reg, _shift, _width) \ _width 116 drivers/clk/mediatek/clk-mtk.h _shift, _width, CLK_SET_RATE_PARENT) _width 118 drivers/clk/mediatek/clk-mtk.h #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ _width 123 drivers/clk/mediatek/clk-mtk.h .mux_width = _width, \ _width 190 drivers/clk/mediatek/clk-mtk.h #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ _width 196 drivers/clk/mediatek/clk-mtk.h .div_width = _width, \ _width 46 drivers/clk/mediatek/clk-mux.h _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _width 55 drivers/clk/mediatek/clk-mux.h .mux_width = _width, \ _width 65 drivers/clk/mediatek/clk-mux.h _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _width 68 drivers/clk/mediatek/clk-mux.h _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _width 73 drivers/clk/mediatek/clk-mux.h _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _width 77 drivers/clk/mediatek/clk-mux.h _width, _gate, _upd_ofs, _upd, \ _width 59 drivers/clk/meson/axg-audio.c #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ _width 64 drivers/clk/meson/axg-audio.c .width = (_width), \ _width 245 drivers/clk/meson/axg-audio.c #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ _width 252 drivers/clk/meson/axg-audio.c .width = (_width), \ _width 257 drivers/clk/meson/axg-audio.c .width = (_width), \ _width 262 drivers/clk/meson/axg-audio.c .width = (_width), \ _width 13 drivers/clk/meson/clk-phase.c #define phase_step(_width) (360 / (1 << (_width))) _width 172 drivers/clk/nxp/clk-lpc18xx-cgu.c #define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \ _width 178 drivers/clk/nxp/clk-lpc18xx-cgu.c .width = _width, \ _width 1130 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ _width 1140 drivers/clk/nxp/clk-lpc32xx.c .width = (_width), \ _width 59 drivers/clk/pistachio/clk.h #define DIV(_id, _name, _pname, _reg, _width) \ _width 63 drivers/clk/pistachio/clk.h .width = _width, \ _width 69 drivers/clk/pistachio/clk.h #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ _width 73 drivers/clk/pistachio/clk.h .width = _width, \ _width 27 drivers/clk/sprd/div.h #define _SPRD_DIV_CLK(_shift, _width) \ _width 30 drivers/clk/sprd/div.h .width = _width, \ _width 39 drivers/clk/sprd/div.h _shift, _width, _flags) \ _width 41 drivers/clk/sprd/div.h .div = _SPRD_DIV_CLK(_shift, _width), \ _width 32 drivers/clk/sprd/mux.h #define _SPRD_MUX_CLK(_shift, _width, _table) \ _width 35 drivers/clk/sprd/mux.h .width = _width, \ _width 40 drivers/clk/sprd/mux.h _reg, _shift, _width, \ _width 43 drivers/clk/sprd/mux.h .mux = _SPRD_MUX_CLK(_shift, _width, _table), \ _width 55 drivers/clk/sprd/mux.h _shift, _width, _flags) \ _width 57 drivers/clk/sprd/mux.h _reg, _shift, _width, _flags) _width 43 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ _width 46 drivers/clk/sunxi-ng/ccu_div.h .width = _width, \ _width 51 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ _width 52 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0) _width 54 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ _width 57 drivers/clk/sunxi-ng/ccu_div.h .width = _width, \ _width 63 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ _width 64 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags) _width 66 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ _width 67 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags) _width 69 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \ _width 70 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0) _width 72 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \ _width 73 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _offset, 0, 0) _width 75 drivers/clk/sunxi-ng/ccu_div.h #define _SUNXI_CCU_DIV(_shift, _width) \ _width 76 drivers/clk/sunxi-ng/ccu_div.h _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0) _width 88 drivers/clk/sunxi-ng/ccu_div.h _shift, _width, \ _width 91 drivers/clk/sunxi-ng/ccu_div.h .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \ _width 105 drivers/clk/sunxi-ng/ccu_div.h _shift, _width, \ _width 108 drivers/clk/sunxi-ng/ccu_div.h _shift, _width, _table, 0, \ _width 17 drivers/clk/sunxi-ng/ccu_mult.h #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ _width 23 drivers/clk/sunxi-ng/ccu_mult.h .width = _width, \ _width 26 drivers/clk/sunxi-ng/ccu_mult.h #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ _width 27 drivers/clk/sunxi-ng/ccu_mult.h _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0) _width 29 drivers/clk/sunxi-ng/ccu_mult.h #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ _width 30 drivers/clk/sunxi-ng/ccu_mult.h _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0) _width 32 drivers/clk/sunxi-ng/ccu_mult.h #define _SUNXI_CCU_MULT(_shift, _width) \ _width 33 drivers/clk/sunxi-ng/ccu_mult.h _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0) _width 32 drivers/clk/sunxi-ng/ccu_mux.h #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ _width 35 drivers/clk/sunxi-ng/ccu_mux.h .width = _width, \ _width 39 drivers/clk/sunxi-ng/ccu_mux.h #define _SUNXI_CCU_MUX(_shift, _width) \ _width 40 drivers/clk/sunxi-ng/ccu_mux.h _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL) _width 51 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _width 55 drivers/clk/sunxi-ng/ccu_mux.h .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \ _width 66 drivers/clk/sunxi-ng/ccu_mux.h _shift, _width, _gate, _flags) \ _width 68 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _width 71 drivers/clk/sunxi-ng/ccu_mux.h #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ _width 74 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, 0, _flags) _width 20 drivers/clk/sunxi-ng/ccu_phase.h #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ _width 23 drivers/clk/sunxi-ng/ccu_phase.h .width = _width, \ _width 98 drivers/clk/zte/clk.h #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ _width 102 drivers/clk/zte/clk.h .mask = BIT(_width) - 1, \ _width 114 drivers/clk/zte/clk.h #define MUX(_id, _name, _parent, _reg, _shift, _width) \ _width 115 drivers/clk/zte/clk.h MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0) _width 122 drivers/clk/zte/clk.h #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ _width 127 drivers/clk/zte/clk.h .width = _width, \ _width 37 drivers/gpu/drm/gma500/framebuffer.c #define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) _width 454 drivers/infiniband/core/sysfs.c #define PORT_PMA_ATTR(_name, _counter, _width, _offset) \ _width 457 drivers/infiniband/core/sysfs.c .index = (_offset) | ((_width) << 16) | ((_counter) << 24), \ _width 461 drivers/infiniband/core/sysfs.c #define PORT_PMA_ATTR_EXT(_name, _width, _offset) \ _width 464 drivers/infiniband/core/sysfs.c .index = (_offset) | ((_width) << 16), \ _width 1386 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define GET_BITS(_var, _index, _width) \ _width 1387 drivers/net/ethernet/amd/xgbe/xgbe-common.h (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) _width 1389 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define SET_BITS(_var, _index, _width, _val) \ _width 1391 drivers/net/ethernet/amd/xgbe/xgbe-common.h (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ _width 1392 drivers/net/ethernet/amd/xgbe/xgbe-common.h (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ _width 1395 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define GET_BITS_LE(_var, _index, _width) \ _width 1396 drivers/net/ethernet/amd/xgbe/xgbe-common.h ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) _width 1398 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define SET_BITS_LE(_var, _index, _width, _val) \ _width 1400 drivers/net/ethernet/amd/xgbe/xgbe-common.h (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ _width 1402 drivers/net/ethernet/amd/xgbe/xgbe-common.h ((0x1 << (_width)) - 1)) << (_index))); \ _width 303 drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ _width 306 drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h .width = _width, \ _width 37 drivers/pinctrl/berlin/berlin.h #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ _width 41 drivers/pinctrl/berlin/berlin.h .bit_width = _width, \ _width 796 drivers/pinctrl/pinctrl-bm1880.c #define BM1880_PINCONF_DAT(_width) \ _width 798 drivers/pinctrl/pinctrl-bm1880.c .drv_bits = _width, \ _width 51 drivers/soc/sunxi/sunxi_sram.c #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ _width 56 drivers/soc/sunxi/sunxi_sram.c .width = _width, \ _width 36 drivers/video/fbdev/vermilion/vermilion.c #define VML_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) _width 25 include/uapi/linux/v4l2-dv-timings.h #define V4L2_INIT_BT_TIMINGS(_width, args...) \ _width 26 include/uapi/linux/v4l2-dv-timings.h { .bt = { _width , ## args } } _width 28 include/uapi/linux/v4l2-dv-timings.h #define V4L2_INIT_BT_TIMINGS(_width, args...) \ _width 29 include/uapi/linux/v4l2-dv-timings.h .bt = { _width , ## args }