AFMT_VBI_PACKET_CONTROL1   80 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (REG(AFMT_VBI_PACKET_CONTROL1)) {
AFMT_VBI_PACKET_CONTROL1  134 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
AFMT_VBI_PACKET_CONTROL1  141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (REG(AFMT_VBI_PACKET_CONTROL1)) {
AFMT_VBI_PACKET_CONTROL1  144 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  148 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  152 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  156 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  160 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  164 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  168 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  172 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  103 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
AFMT_VBI_PACKET_CONTROL1  650 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t AFMT_VBI_PACKET_CONTROL1;
AFMT_VBI_PACKET_CONTROL1  123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1  826 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
AFMT_VBI_PACKET_CONTROL1  832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
AFMT_VBI_PACKET_CONTROL1   47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
AFMT_VBI_PACKET_CONTROL1  116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t AFMT_VBI_PACKET_CONTROL1;
AFMT_VBI_PACKET_CONTROL1  268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, 1);