_reg 23 arch/arm/kvm/emulate.c #define REG_OFFSET(_reg) \ _reg 24 arch/arm/kvm/emulate.c (offsetof(struct kvm_regs, _reg) / sizeof(u32)) _reg 25 arch/arm/mach-mmp/clock.h #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ _reg 27 arch/arm/mach-mmp/clock.h .clk_rst = APBC_##_reg, \ _reg 33 arch/arm/mach-mmp/clock.h #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ _reg 35 arch/arm/mach-mmp/clock.h .clk_rst = APBC_##_reg, \ _reg 41 arch/arm/mach-mmp/clock.h #define APMU_CLK(_name, _reg, _eval, _rate) \ _reg 43 arch/arm/mach-mmp/clock.h .clk_rst = APMU_##_reg, \ _reg 49 arch/arm/mach-mmp/clock.h #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ _reg 51 arch/arm/mach-mmp/clock.h .clk_rst = APMU_##_reg, \ _reg 17 arch/arm64/kvm/regmap.c #define REG_OFFSET(_reg) \ _reg 18 arch/arm64/kvm/regmap.c (offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long)) _reg 475 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ _reg 478 arch/mips/include/asm/kvm_host.h return cop0->reg[(_reg)][(sel)]; \ _reg 483 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = val; \ _reg 487 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ _reg 491 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val; \ _reg 496 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~val; \ _reg 503 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~_mask; \ _reg 504 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val & _mask; \ _reg 508 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ _reg 512 arch/mips/include/asm/kvm_host.h _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ _reg 517 arch/mips/include/asm/kvm_host.h _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ _reg 523 arch/mips/include/asm/kvm_host.h _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ _reg 533 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ _reg 545 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ _reg 564 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \ _reg 567 arch/mips/include/asm/kvm_host.h write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ _reg 571 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \ _reg 616 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_RW_SW(name, type, _reg, sel) \ _reg 617 arch/mips/include/asm/kvm_host.h __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ _reg 620 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_SET_SW(name, type, _reg, sel) \ _reg 621 arch/mips/include/asm/kvm_host.h __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ _reg 624 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel) \ _reg 625 arch/mips/include/asm/kvm_host.h __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ _reg 657 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_RW_HW(name, type, _reg, sel) \ _reg 658 arch/mips/include/asm/kvm_host.h __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ _reg 659 arch/mips/include/asm/kvm_host.h __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ _reg 661 arch/mips/include/asm/kvm_host.h __BUILD_KVM_SAVE_VZ(name, _reg, sel) _reg 663 arch/mips/include/asm/kvm_host.h #define __BUILD_KVM_SET_HW(name, type, _reg, sel) \ _reg 664 arch/mips/include/asm/kvm_host.h __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ _reg 665 arch/mips/include/asm/kvm_host.h __BUILD_KVM_SET_VZ(name, type, _reg, sel) \ _reg 14 arch/mips/include/asm/mach-pic32/pic32.h #define PIC32_CLR(_reg) ((_reg) + 0x04) _reg 15 arch/mips/include/asm/mach-pic32/pic32.h #define PIC32_SET(_reg) ((_reg) + 0x08) _reg 16 arch/mips/include/asm/mach-pic32/pic32.h #define PIC32_INV(_reg) ((_reg) + 0x0C) _reg 77 arch/sh/kernel/cpu/sh2a/clock-sh7264.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 78 arch/sh/kernel/cpu/sh2a/clock-sh7264.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 105 arch/sh/kernel/cpu/sh2a/clock-sh7269.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 106 arch/sh/kernel/cpu/sh2a/clock-sh7269.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 105 arch/sh/kernel/cpu/sh4a/clock-sh7343.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 106 arch/sh/kernel/cpu/sh4a/clock-sh7343.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 125 arch/sh/kernel/cpu/sh4a/clock-sh7343.c #define MSTP(_parent, _reg, _bit, _flags) \ _reg 126 arch/sh/kernel/cpu/sh4a/clock-sh7343.c SH_CLK_MSTP32(_parent, _reg, _bit, _flags) _reg 108 arch/sh/kernel/cpu/sh4a/clock-sh7366.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 109 arch/sh/kernel/cpu/sh4a/clock-sh7366.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 128 arch/sh/kernel/cpu/sh4a/clock-sh7366.c #define MSTP(_parent, _reg, _bit, _flags) \ _reg 129 arch/sh/kernel/cpu/sh4a/clock-sh7366.c SH_CLK_MSTP32(_parent, _reg, _bit, _flags) _reg 108 arch/sh/kernel/cpu/sh4a/clock-sh7722.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 109 arch/sh/kernel/cpu/sh4a/clock-sh7722.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 111 arch/sh/kernel/cpu/sh4a/clock-sh7723.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 112 arch/sh/kernel/cpu/sh4a/clock-sh7723.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 150 arch/sh/kernel/cpu/sh4a/clock-sh7724.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 151 arch/sh/kernel/cpu/sh4a/clock-sh7724.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 69 arch/sh/kernel/cpu/sh4a/clock-sh7734.c #define DIV4(_reg, _bit, _mask, _flags) \ _reg 70 arch/sh/kernel/cpu/sh4a/clock-sh7734.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _reg 6946 arch/x86/kvm/vmx/vmx.c #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ _reg 6947 arch/x86/kvm/vmx/vmx.c if (entry && (entry->_reg & (_cpuid_mask))) \ _reg 29 drivers/clk/actions/owl-divider.h #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ _reg 31 drivers/clk/actions/owl-divider.h .reg = _reg, \ _reg 38 drivers/clk/actions/owl-divider.h #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ _reg 41 drivers/clk/actions/owl-divider.h .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \ _reg 35 drivers/clk/actions/owl-factor.h #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ _reg 37 drivers/clk/actions/owl-factor.h .reg = _reg, \ _reg 44 drivers/clk/actions/owl-factor.h #define OWL_FACTOR(_struct, _name, _parent, _reg, \ _reg 47 drivers/clk/actions/owl-factor.h .factor_hw = OWL_FACTOR_HW(_reg, _shift, \ _reg 27 drivers/clk/actions/owl-gate.h #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ _reg 29 drivers/clk/actions/owl-gate.h .reg = _reg, \ _reg 34 drivers/clk/actions/owl-gate.h #define OWL_GATE(_struct, _name, _parent, _reg, \ _reg 37 drivers/clk/actions/owl-gate.h .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ _reg 47 drivers/clk/actions/owl-gate.h #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ _reg 50 drivers/clk/actions/owl-gate.h .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ _reg 27 drivers/clk/actions/owl-mux.h #define OWL_MUX_HW(_reg, _shift, _width) \ _reg 29 drivers/clk/actions/owl-mux.h .reg = _reg, \ _reg 34 drivers/clk/actions/owl-mux.h #define OWL_MUX(_struct, _name, _parents, _reg, \ _reg 37 drivers/clk/actions/owl-mux.h .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \ _reg 41 drivers/clk/actions/owl-pll.h #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _reg 44 drivers/clk/actions/owl-pll.h .reg = _reg, \ _reg 55 drivers/clk/actions/owl-pll.h #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ _reg 58 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _reg 70 drivers/clk/actions/owl-pll.h #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ _reg 73 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _reg 84 drivers/clk/actions/owl-pll.h #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ _reg 88 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _reg 91 drivers/clk/at91/pmc.h #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) _reg 918 drivers/clk/mediatek/clk-mt2701.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _reg 922 drivers/clk/mediatek/clk-mt2701.c .reg = _reg, \ _reg 1166 drivers/clk/mediatek/clk-mt2712.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 1172 drivers/clk/mediatek/clk-mt2712.c .reg = _reg, \ _reg 1189 drivers/clk/mediatek/clk-mt2712.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 1192 drivers/clk/mediatek/clk-mt2712.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 1142 drivers/clk/mediatek/clk-mt6779.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 1149 drivers/clk/mediatek/clk-mt6779.c .reg = _reg, \ _reg 1169 drivers/clk/mediatek/clk-mt6779.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 1174 drivers/clk/mediatek/clk-mt6779.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 614 drivers/clk/mediatek/clk-mt6797.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 619 drivers/clk/mediatek/clk-mt6797.c .reg = _reg, \ _reg 634 drivers/clk/mediatek/clk-mt6797.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 637 drivers/clk/mediatek/clk-mt6797.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 24 drivers/clk/mediatek/clk-mt7622.c #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ _reg 29 drivers/clk/mediatek/clk-mt7622.c .reg = _reg, \ _reg 45 drivers/clk/mediatek/clk-mt7622.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 48 drivers/clk/mediatek/clk-mt7622.c PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ _reg 24 drivers/clk/mediatek/clk-mt7629.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 29 drivers/clk/mediatek/clk-mt7629.c .reg = _reg, \ _reg 45 drivers/clk/mediatek/clk-mt7629.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 48 drivers/clk/mediatek/clk-mt7629.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 596 drivers/clk/mediatek/clk-mt8135.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ _reg 599 drivers/clk/mediatek/clk-mt8135.c .reg = _reg, \ _reg 1025 drivers/clk/mediatek/clk-mt8173.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 1030 drivers/clk/mediatek/clk-mt8173.c .reg = _reg, \ _reg 1045 drivers/clk/mediatek/clk-mt8173.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 1048 drivers/clk/mediatek/clk-mt8173.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 1067 drivers/clk/mediatek/clk-mt8183.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 1074 drivers/clk/mediatek/clk-mt8183.c .reg = _reg, \ _reg 1094 drivers/clk/mediatek/clk-mt8183.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 1099 drivers/clk/mediatek/clk-mt8183.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ _reg 467 drivers/clk/mediatek/clk-mt8516.c #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ _reg 471 drivers/clk/mediatek/clk-mt8516.c .div_reg = _reg, \ _reg 736 drivers/clk/mediatek/clk-mt8516.c #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 741 drivers/clk/mediatek/clk-mt8516.c .reg = _reg, \ _reg 756 drivers/clk/mediatek/clk-mt8516.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 759 drivers/clk/mediatek/clk-mt8516.c PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _reg 81 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ _reg 85 drivers/clk/mediatek/clk-mtk.h .mux_reg = _reg, \ _reg 88 drivers/clk/mediatek/clk-mtk.h .gate_reg = _reg, \ _reg 101 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _reg 103 drivers/clk/mediatek/clk-mtk.h MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ _reg 110 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ _reg 111 drivers/clk/mediatek/clk-mtk.h MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _reg 114 drivers/clk/mediatek/clk-mtk.h #define MUX(_id, _name, _parents, _reg, _shift, _width) \ _reg 115 drivers/clk/mediatek/clk-mtk.h MUX_FLAGS(_id, _name, _parents, _reg, \ _reg 118 drivers/clk/mediatek/clk-mtk.h #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ _reg 121 drivers/clk/mediatek/clk-mtk.h .mux_reg = _reg, \ _reg 190 drivers/clk/mediatek/clk-mtk.h #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ _reg 194 drivers/clk/mediatek/clk-mtk.h .div_reg = _reg, \ _reg 27 drivers/clk/meson/axg-audio.c #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \ _reg 30 drivers/clk/meson/axg-audio.c .offset = (_reg), \ _reg 42 drivers/clk/meson/axg-audio.c #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \ _reg 45 drivers/clk/meson/axg-audio.c .offset = (_reg), \ _reg 59 drivers/clk/meson/axg-audio.c #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ _reg 62 drivers/clk/meson/axg-audio.c .offset = (_reg), \ _reg 126 drivers/clk/meson/axg-audio.c #define AUD_MST_MUX(_name, _reg, _flag) \ _reg 127 drivers/clk/meson/axg-audio.c AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ _reg 130 drivers/clk/meson/axg-audio.c #define AUD_MST_MCLK_MUX(_name, _reg) \ _reg 131 drivers/clk/meson/axg-audio.c AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) _reg 133 drivers/clk/meson/axg-audio.c #define AUD_MST_SYS_MUX(_name, _reg) \ _reg 134 drivers/clk/meson/axg-audio.c AUD_MST_MUX(_name, _reg, 0) _reg 148 drivers/clk/meson/axg-audio.c #define AUD_MST_DIV(_name, _reg, _flag) \ _reg 149 drivers/clk/meson/axg-audio.c AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ _reg 152 drivers/clk/meson/axg-audio.c #define AUD_MST_MCLK_DIV(_name, _reg) \ _reg 153 drivers/clk/meson/axg-audio.c AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) _reg 155 drivers/clk/meson/axg-audio.c #define AUD_MST_SYS_DIV(_name, _reg) \ _reg 156 drivers/clk/meson/axg-audio.c AUD_MST_DIV(_name, _reg, 0) _reg 170 drivers/clk/meson/axg-audio.c #define AUD_MST_MCLK_GATE(_name, _reg) \ _reg 171 drivers/clk/meson/axg-audio.c AUD_GATE(_name, _reg, 31, aud_##_name##_div, \ _reg 187 drivers/clk/meson/axg-audio.c #define AUD_MST_SCLK_PRE_EN(_name, _reg) \ _reg 188 drivers/clk/meson/axg-audio.c AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ _reg 198 drivers/clk/meson/axg-audio.c #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ _reg 203 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 208 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 222 drivers/clk/meson/axg-audio.c #define AUD_MST_SCLK_DIV(_name, _reg) \ _reg 223 drivers/clk/meson/axg-audio.c AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ _reg 234 drivers/clk/meson/axg-audio.c #define AUD_MST_SCLK_POST_EN(_name, _reg) \ _reg 235 drivers/clk/meson/axg-audio.c AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ _reg 245 drivers/clk/meson/axg-audio.c #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ _reg 250 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 255 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 260 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 274 drivers/clk/meson/axg-audio.c #define AUD_MST_SCLK(_name, _reg) \ _reg 275 drivers/clk/meson/axg-audio.c AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ _reg 285 drivers/clk/meson/axg-audio.c #define AUD_MST_LRCLK_DIV(_name, _reg) \ _reg 286 drivers/clk/meson/axg-audio.c AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ _reg 296 drivers/clk/meson/axg-audio.c #define AUD_MST_LRCLK(_name, _reg) \ _reg 297 drivers/clk/meson/axg-audio.c AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ _reg 326 drivers/clk/meson/axg-audio.c #define AUD_TDM_SCLK_MUX(_name, _reg) \ _reg 327 drivers/clk/meson/axg-audio.c AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ _reg 339 drivers/clk/meson/axg-audio.c #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ _reg 340 drivers/clk/meson/axg-audio.c AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ _reg 351 drivers/clk/meson/axg-audio.c #define AUD_TDM_SCLK_POST_EN(_name, _reg) \ _reg 352 drivers/clk/meson/axg-audio.c AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ _reg 363 drivers/clk/meson/axg-audio.c #define AUD_TDM_SCLK(_name, _reg) \ _reg 367 drivers/clk/meson/axg-audio.c .reg_off = (_reg), \ _reg 410 drivers/clk/meson/axg-audio.c #define AUD_TDM_LRLCK(_name, _reg) \ _reg 411 drivers/clk/meson/axg-audio.c AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ _reg 424 drivers/clk/meson/axg-audio.c #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ _reg 425 drivers/clk/meson/axg-audio.c AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \ _reg 1099 drivers/clk/meson/axg.c #define MESON_GATE(_name, _reg, _bit) \ _reg 1100 drivers/clk/meson/axg.c MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) _reg 114 drivers/clk/meson/clk-regmap.h #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ _reg 117 drivers/clk/meson/clk-regmap.h .offset = (_reg), \ _reg 129 drivers/clk/meson/clk-regmap.h #define MESON_PCLK(_name, _reg, _bit, _pname) \ _reg 130 drivers/clk/meson/clk-regmap.h __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) _reg 132 drivers/clk/meson/clk-regmap.h #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ _reg 133 drivers/clk/meson/clk-regmap.h __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) _reg 43 drivers/clk/meson/g12a-aoclk.c #define AXG_AO_GATE(_name, _reg, _bit) \ _reg 46 drivers/clk/meson/g12a-aoclk.c .offset = (_reg), \ _reg 3865 drivers/clk/meson/g12a.c #define MESON_GATE(_name, _reg, _bit) \ _reg 3866 drivers/clk/meson/g12a.c MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) _reg 3868 drivers/clk/meson/g12a.c #define MESON_GATE_RO(_name, _reg, _bit) \ _reg 3869 drivers/clk/meson/g12a.c MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw) _reg 2591 drivers/clk/meson/gxbb.c #define MESON_GATE(_name, _reg, _bit) \ _reg 2592 drivers/clk/meson/gxbb.c MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) _reg 2570 drivers/clk/meson/meson8b.c #define MESON_GATE(_name, _reg, _bit) \ _reg 2571 drivers/clk/meson/meson8b.c MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) _reg 158 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_DIV(_name, _reg, _shift, _table) \ _reg 160 drivers/clk/mvebu/armada-37xx-periph.c .reg = (void *)_reg, \ _reg 168 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ _reg 173 drivers/clk/mvebu/armada-37xx-periph.c .reg_div = (void *)_reg, \ _reg 185 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ _reg 188 drivers/clk/mvebu/armada-37xx-periph.c static PERIPH_DIV(_name, _reg, _shift1, _table); _reg 190 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ _reg 192 drivers/clk/mvebu/armada-37xx-periph.c static PERIPH_DIV(_name, _reg, _shift, _table); _reg 1093 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \ _reg 1101 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ _reg 1109 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ _reg 1119 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ _reg 1130 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ _reg 1138 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ _reg 1149 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ _reg 1157 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ _reg 1166 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \ _reg 1174 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ _reg 19 drivers/clk/pistachio/clk.h #define GATE(_id, _name, _pname, _reg, _shift) \ _reg 22 drivers/clk/pistachio/clk.h .reg = _reg, \ _reg 39 drivers/clk/pistachio/clk.h #define MUX(_id, _name, _pnames, _reg, _shift) \ _reg 42 drivers/clk/pistachio/clk.h .reg = _reg, \ _reg 59 drivers/clk/pistachio/clk.h #define DIV(_id, _name, _pname, _reg, _width) \ _reg 62 drivers/clk/pistachio/clk.h .reg = _reg, \ _reg 69 drivers/clk/pistachio/clk.h #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ _reg 72 drivers/clk/pistachio/clk.h .reg = _reg, \ _reg 119 drivers/clk/pistachio/clk.h #define PLL(_id, _name, _pname, _type, _reg, _rates) \ _reg 122 drivers/clk/pistachio/clk.h .reg_base = _reg, \ _reg 130 drivers/clk/pistachio/clk.h #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ _reg 133 drivers/clk/pistachio/clk.h .reg_base = _reg, \ _reg 79 drivers/clk/renesas/r9a06g032-clocks.c #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \ _reg 82 drivers/clk/renesas/r9a06g032-clocks.c .reg = _reg, .div_min = _min, .div_max = _max, \ _reg 21 drivers/clk/sprd/composite.h #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ _reg 28 drivers/clk/sprd/composite.h .reg = _reg, \ _reg 36 drivers/clk/sprd/composite.h #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ _reg 38 drivers/clk/sprd/composite.h SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \ _reg 38 drivers/clk/sprd/div.h #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ _reg 44 drivers/clk/sprd/div.h .reg = _reg, \ _reg 21 drivers/clk/sprd/gate.h #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ _reg 29 drivers/clk/sprd/gate.h .reg = _reg, \ _reg 37 drivers/clk/sprd/gate.h #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ _reg 39 drivers/clk/sprd/gate.h SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \ _reg 43 drivers/clk/sprd/gate.h #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ _reg 45 drivers/clk/sprd/gate.h SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ _reg 40 drivers/clk/sprd/mux.h _reg, _shift, _width, \ _reg 46 drivers/clk/sprd/mux.h .reg = _reg, \ _reg 54 drivers/clk/sprd/mux.h #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ _reg 57 drivers/clk/sprd/mux.h _reg, _shift, _width, _flags) _reg 64 drivers/clk/sprd/pll.h #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ _reg 78 drivers/clk/sprd/pll.h .reg = _reg, \ _reg 86 drivers/clk/sprd/pll.h #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ _reg 89 drivers/clk/sprd/pll.h SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ _reg 93 drivers/clk/sprd/pll.h #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ _reg 95 drivers/clk/sprd/pll.h SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ _reg 87 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ _reg 95 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ _reg 104 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ _reg 107 drivers/clk/sunxi-ng/ccu_div.h SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ _reg 113 drivers/clk/sunxi-ng/ccu_div.h _reg, \ _reg 122 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ _reg 130 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _reg 135 drivers/clk/sunxi-ng/ccu_div.h _reg, _mshift, _mwidth, \ _reg 139 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ _reg 144 drivers/clk/sunxi-ng/ccu_div.h _reg, _mshift, _mwidth, \ _reg 149 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _reg 156 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ _reg 164 drivers/clk/sunxi-ng/ccu_div.h #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ _reg 166 drivers/clk/sunxi-ng/ccu_div.h SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ _reg 19 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ _reg 23 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ _reg 31 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ _reg 35 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ _reg 43 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ _reg 47 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ _reg 59 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ _reg 63 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ _reg 71 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ _reg 75 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ _reg 34 drivers/clk/sunxi-ng/ccu_mp.h #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ _reg 46 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ _reg 55 drivers/clk/sunxi-ng/ccu_mp.h #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _reg 66 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ _reg 74 drivers/clk/sunxi-ng/ccu_mp.h #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ _reg 79 drivers/clk/sunxi-ng/ccu_mp.h SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _reg 103 drivers/clk/sunxi-ng/ccu_mp.h #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _reg 111 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ _reg 45 drivers/clk/sunxi-ng/ccu_mult.h #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 53 drivers/clk/sunxi-ng/ccu_mult.h .reg = _reg, \ _reg 51 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _reg 57 drivers/clk/sunxi-ng/ccu_mux.h .reg = _reg, \ _reg 65 drivers/clk/sunxi-ng/ccu_mux.h #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ _reg 68 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _reg 71 drivers/clk/sunxi-ng/ccu_mux.h #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ _reg 74 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, 0, _flags) _reg 33 drivers/clk/sunxi-ng/ccu_nk.h #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ _reg 45 drivers/clk/sunxi-ng/ccu_nk.h .reg = _reg, \ _reg 34 drivers/clk/sunxi-ng/ccu_nkm.h #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ _reg 48 drivers/clk/sunxi-ng/ccu_nkm.h .reg = _reg, \ _reg 56 drivers/clk/sunxi-ng/ccu_nkm.h #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 68 drivers/clk/sunxi-ng/ccu_nkm.h .reg = _reg, \ _reg 35 drivers/clk/sunxi-ng/ccu_nkmp.h #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 49 drivers/clk/sunxi-ng/ccu_nkmp.h .reg = _reg, \ _reg 38 drivers/clk/sunxi-ng/ccu_nm.h #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 52 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ _reg 61 drivers/clk/sunxi-ng/ccu_nm.h #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 76 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ _reg 86 drivers/clk/sunxi-ng/ccu_nm.h _reg, _min_rate, \ _reg 102 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ _reg 112 drivers/clk/sunxi-ng/ccu_nm.h _parent, _reg, \ _reg 131 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ _reg 140 drivers/clk/sunxi-ng/ccu_nm.h #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _reg 150 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ _reg 20 drivers/clk/sunxi-ng/ccu_phase.h #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ _reg 25 drivers/clk/sunxi-ng/ccu_phase.h .reg = _reg, \ _reg 42 drivers/clk/sunxi-ng/ccu_sdm.h _reg, _reg_enable) \ _reg 48 drivers/clk/sunxi-ng/ccu_sdm.h .tuning_reg = _reg, \ _reg 95 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ _reg 102 drivers/clk/uniphier/clk-uniphier.h .reg = (_reg), \ _reg 37 drivers/clk/zte/clk.h #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ _reg 39 drivers/clk/zte/clk.h .reg_base = (void __iomem *) _reg, \ _reg 52 drivers/clk/zte/clk.h #define ZX296718_PLL(_name, _parent, _reg, _table) \ _reg 53 drivers/clk/zte/clk.h ZX_PLL(_name, _parent, _reg, _table, 0xff, 30) _reg 60 drivers/clk/zte/clk.h #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ _reg 63 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ _reg 98 drivers/clk/zte/clk.h #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ _reg 101 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ _reg 114 drivers/clk/zte/clk.h #define MUX(_id, _name, _parent, _reg, _shift, _width) \ _reg 115 drivers/clk/zte/clk.h MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0) _reg 122 drivers/clk/zte/clk.h #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ _reg 125 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ _reg 147 drivers/clk/zte/clk.h #define AUDIO_DIV(_id, _name, _parent, _reg) \ _reg 149 drivers/clk/zte/clk.h .reg_base = (void __iomem *) _reg, \ _reg 145 drivers/dma/pxa_dma.c #define _phy_readl_relaxed(phy, _reg) \ _reg 146 drivers/dma/pxa_dma.c readl_relaxed((phy)->base + _reg((phy)->idx)) _reg 147 drivers/dma/pxa_dma.c #define phy_readl_relaxed(phy, _reg) \ _reg 150 drivers/dma/pxa_dma.c _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ _reg 152 drivers/dma/pxa_dma.c "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \ _reg 156 drivers/dma/pxa_dma.c #define phy_writel(phy, val, _reg) \ _reg 158 drivers/dma/pxa_dma.c writel((val), (phy)->base + _reg((phy)->idx)); \ _reg 161 drivers/dma/pxa_dma.c __func__, (u32)(val), #_reg); \ _reg 163 drivers/dma/pxa_dma.c #define phy_writel_relaxed(phy, val, _reg) \ _reg 165 drivers/dma/pxa_dma.c writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ _reg 168 drivers/dma/pxa_dma.c __func__, (u32)(val), #_reg); \ _reg 257 drivers/edac/thunderx_edac.c #define DEBUGFS_REG_ATTR(_type, _name, _reg) \ _reg 265 drivers/edac/thunderx_edac.c sprintf(buf, "0x%016llx", readq(pdata->regs + _reg)); \ _reg 281 drivers/edac/thunderx_edac.c writeq(val, pdata->regs + _reg); \ _reg 1238 drivers/edac/thunderx_edac.c #define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg) _reg 1918 drivers/edac/thunderx_edac.c #define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg) _reg 29 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_DIR_BITS(_reg) \ _reg 30 drivers/gpio/gpio-max77650.c ((_reg) & MAX77650_GPIO_DIR_MASK) _reg 31 drivers/gpio/gpio-max77650.c #define MAX77650_GPIO_INVAL_BITS(_reg) \ _reg 32 drivers/gpio/gpio-max77650.c (((_reg) & MAX77650_GPIO_INVAL_MASK) >> 1) _reg 35 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ _reg 60 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ _reg 77 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ _reg 32 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .type ## _reg = REG(DC_GPIO_GENERIC_## type),\ _reg 40 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h .type ## _reg = REG(DC_GPIO_HPD_## type),\ _reg 80 drivers/gpu/drm/i915/gvt/reg.h #define REG_50080_TO_PIPE(_reg) ({ \ _reg 81 drivers/gpu/drm/i915/gvt/reg.h typeof(_reg) (reg) = (_reg); \ _reg 87 drivers/gpu/drm/i915/gvt/reg.h #define REG_50080_TO_PLANE(_reg) ({ \ _reg 88 drivers/gpu/drm/i915/gvt/reg.h typeof(_reg) (reg) = (_reg); \ _reg 572 drivers/gpu/drm/i915/i915_cmd_parser.c #define REG32(_reg, ...) \ _reg 573 drivers/gpu/drm/i915/i915_cmd_parser.c { .addr = (_reg), __VA_ARGS__ } _reg 582 drivers/gpu/drm/i915/i915_cmd_parser.c #define REG64(_reg) \ _reg 583 drivers/gpu/drm/i915/i915_cmd_parser.c { .addr = _reg }, \ _reg 584 drivers/gpu/drm/i915/i915_cmd_parser.c { .addr = _reg ## _UDW } _reg 586 drivers/gpu/drm/i915/i915_cmd_parser.c #define REG64_IDX(_reg, idx) \ _reg 587 drivers/gpu/drm/i915/i915_cmd_parser.c { .addr = _reg(idx) }, \ _reg 588 drivers/gpu/drm/i915/i915_cmd_parser.c { .addr = _reg ## _UDW(idx) } _reg 33 drivers/gpu/drm/msm/adreno/a6xx_gpu.h #define A6XX_PROTECT_RW(_reg, _len) \ _reg 35 drivers/gpu/drm/msm/adreno/a6xx_gpu.h (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) _reg 42 drivers/gpu/drm/msm/adreno/a6xx_gpu.h #define A6XX_PROTECT_RDONLY(_reg, _len) \ _reg 43 drivers/gpu/drm/msm/adreno/a6xx_gpu.h ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) _reg 50 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \ _reg 52 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h .registers = _reg, \ _reg 53 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h .count = ARRAY_SIZE(_reg), \ _reg 123 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \ _reg 125 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h .registers = _reg, .count = ARRAY_SIZE(_reg) } _reg 20 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 _reg 291 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define PKT4(_reg, _cnt) \ _reg 293 drivers/gpu/drm/msm/adreno/adreno_gpu.h (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) _reg 382 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define ADRENO_PROTECT_RW(_reg, _len) \ _reg 384 drivers/gpu/drm/msm/adreno/adreno_gpu.h ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) _reg 391 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define ADRENO_PROTECT_RDONLY(_reg, _len) \ _reg 393 drivers/gpu/drm/msm/adreno/adreno_gpu.h ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) _reg 178 drivers/i2c/busses/i2c-brcmstb.c #define __bsc_readl(_reg) ioread32be(_reg) _reg 179 drivers/i2c/busses/i2c-brcmstb.c #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) _reg 181 drivers/i2c/busses/i2c-brcmstb.c #define __bsc_readl(_reg) ioread32(_reg) _reg 182 drivers/i2c/busses/i2c-brcmstb.c #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) _reg 185 drivers/i2c/busses/i2c-brcmstb.c #define bsc_readl(_dev, _reg) \ _reg 186 drivers/i2c/busses/i2c-brcmstb.c __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) _reg 188 drivers/i2c/busses/i2c-brcmstb.c #define bsc_writel(_dev, _val, _reg) \ _reg 189 drivers/i2c/busses/i2c-brcmstb.c __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) _reg 38 drivers/iio/accel/dmard06.c #define DMARD06_ACCEL_CHANNEL(_axis, _reg) { \ _reg 40 drivers/iio/accel/dmard06.c .address = _reg, \ _reg 47 drivers/iio/accel/dmard06.c #define DMARD06_TEMP_CHANNEL(_reg) { \ _reg 49 drivers/iio/accel/dmard06.c .address = _reg, \ _reg 43 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \ _reg 48 drivers/iio/adc/axp20x_adc.c .address = _reg, \ _reg 54 drivers/iio/adc/axp20x_adc.c #define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \ _reg 59 drivers/iio/adc/axp20x_adc.c .address = _reg, \ _reg 24 drivers/irqchip/irq-madera.c #define MADERA_IRQ(_irq, _reg) \ _reg 26 drivers/irqchip/irq-madera.c .reg_offset = (_reg) - MADERA_IRQ1_STATUS_2, \ _reg 119 drivers/irqchip/irq-pic32-evic.c #define IRQ_REG_MASK(_hwirq, _reg, _mask) \ _reg 121 drivers/irqchip/irq-pic32-evic.c _reg = _hwirq / 32; \ _reg 214 drivers/media/dvb-frontends/stv0910.c #define SET_FIELD(_reg, _val) \ _reg 215 drivers/media/dvb-frontends/stv0910.c write_field(state, state->nr ? FSTV0910_P2_##_reg : \ _reg 216 drivers/media/dvb-frontends/stv0910.c FSTV0910_P1_##_reg, _val) _reg 218 drivers/media/dvb-frontends/stv0910.c #define SET_REG(_reg, _val) \ _reg 219 drivers/media/dvb-frontends/stv0910.c write_reg(state, state->nr ? RSTV0910_P2_##_reg : \ _reg 220 drivers/media/dvb-frontends/stv0910.c RSTV0910_P1_##_reg, _val) _reg 222 drivers/media/dvb-frontends/stv0910.c #define GET_REG(_reg, _val) \ _reg 223 drivers/media/dvb-frontends/stv0910.c read_reg(state, state->nr ? RSTV0910_P2_##_reg : \ _reg 224 drivers/media/dvb-frontends/stv0910.c RSTV0910_P1_##_reg, _val) _reg 61 drivers/media/i2c/smiapp/smiapp-quirk.h #define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \ _reg 63 drivers/media/i2c/smiapp/smiapp-quirk.h .reg = (u16)_reg, \ _reg 179 drivers/media/tuners/mc44s803_priv.h #define MC44S803_REG_SM(_val, _reg) \ _reg 180 drivers/media/tuners/mc44s803_priv.h (((_val) << _reg##_S) & (_reg)) _reg 183 drivers/media/tuners/mc44s803_priv.h #define MC44S803_REG_MS(_val, _reg) \ _reg 184 drivers/media/tuners/mc44s803_priv.h (((_val) & (_reg)) >> _reg##_S) _reg 30 drivers/mfd/rc5t583.c #define DEEPSLEEP_INIT(_id, _reg, _pos) \ _reg 32 drivers/mfd/rc5t583.c .reg_add = RC5T583_##_reg, \ _reg 59 drivers/mfd/tps6586x.c #define TPS6586X_IRQ(_reg, _mask) \ _reg 61 drivers/mfd/tps6586x.c .mask_reg = (_reg) - TPS6586X_INT_MASK1, \ _reg 82 drivers/mfd/tps80031.c #define TPS80031_IRQ(_reg, _mask) \ _reg 84 drivers/mfd/tps80031.c .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \ _reg 125 drivers/mfd/tps80031.c #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \ _reg 127 drivers/mfd/tps80031.c .reg = TPS80031_CFG_INPUT_PUPD##_reg, \ _reg 497 drivers/misc/ad525x_dpot.c #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \ _reg 501 drivers/misc/ad525x_dpot.c return sysfs_show_reg(dev, attr, buf, _reg); \ _reg 504 drivers/misc/ad525x_dpot.c #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \ _reg 509 drivers/misc/ad525x_dpot.c return sysfs_set_reg(dev, attr, buf, count, _reg); \ _reg 1440 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_IOREAD(_pdata, _reg) \ _reg 1441 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread32((_pdata)->xgmac_regs + _reg) _reg 1443 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1444 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ _reg 1445 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1446 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1448 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_IOWRITE(_pdata, _reg, _val) \ _reg 1449 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite32((_val), (_pdata)->xgmac_regs + _reg) _reg 1451 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1453 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ _reg 1455 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1456 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1457 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_IOWRITE((_pdata), _reg, reg_val); \ _reg 1464 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ _reg 1466 drivers/net/ethernet/amd/xgbe/xgbe-common.h MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) _reg 1468 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ _reg 1469 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ _reg 1470 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1471 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1473 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ _reg 1475 drivers/net/ethernet/amd/xgbe/xgbe-common.h MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) _reg 1477 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ _reg 1479 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ _reg 1481 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1482 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1483 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ _reg 1490 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_DMA_IOREAD(_channel, _reg) \ _reg 1491 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread32((_channel)->dma_regs + _reg) _reg 1493 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ _reg 1494 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ _reg 1495 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1496 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1498 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ _reg 1499 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite32((_val), (_channel)->dma_regs + _reg) _reg 1501 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ _reg 1503 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ _reg 1505 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1506 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1507 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ _reg 1548 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR0_IOREAD(_pdata, _reg) \ _reg 1549 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread16((_pdata)->sir0_regs + _reg) _reg 1551 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1552 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ _reg 1553 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1554 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1556 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR0_IOWRITE(_pdata, _reg, _val) \ _reg 1557 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite16((_val), (_pdata)->sir0_regs + _reg) _reg 1559 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1561 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ _reg 1563 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1564 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1565 drivers/net/ethernet/amd/xgbe/xgbe-common.h XSIR0_IOWRITE((_pdata), _reg, reg_val); \ _reg 1568 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR1_IOREAD(_pdata, _reg) \ _reg 1569 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread16((_pdata)->sir1_regs + _reg) _reg 1571 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1572 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ _reg 1573 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1574 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1576 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR1_IOWRITE(_pdata, _reg, _val) \ _reg 1577 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite16((_val), (_pdata)->sir1_regs + _reg) _reg 1579 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1581 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ _reg 1583 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1584 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1585 drivers/net/ethernet/amd/xgbe/xgbe-common.h XSIR1_IOWRITE((_pdata), _reg, reg_val); \ _reg 1591 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XRXTX_IOREAD(_pdata, _reg) \ _reg 1592 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread16((_pdata)->rxtx_regs + _reg) _reg 1594 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1595 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ _reg 1596 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1597 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1599 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XRXTX_IOWRITE(_pdata, _reg, _val) \ _reg 1600 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite16((_val), (_pdata)->rxtx_regs + _reg) _reg 1602 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1604 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ _reg 1606 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1607 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1608 drivers/net/ethernet/amd/xgbe/xgbe-common.h XRXTX_IOWRITE((_pdata), _reg, reg_val); \ _reg 1624 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XP_IOREAD(_pdata, _reg) \ _reg 1625 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread32((_pdata)->xprop_regs + (_reg)) _reg 1627 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XP_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1628 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XP_IOREAD((_pdata), (_reg)), \ _reg 1629 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1630 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1632 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XP_IOWRITE(_pdata, _reg, _val) \ _reg 1633 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite32((_val), (_pdata)->xprop_regs + (_reg)) _reg 1635 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1637 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XP_IOREAD((_pdata), (_reg)); \ _reg 1639 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1640 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1641 drivers/net/ethernet/amd/xgbe/xgbe-common.h XP_IOWRITE((_pdata), (_reg), reg_val); \ _reg 1657 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XI2C_IOREAD(_pdata, _reg) \ _reg 1658 drivers/net/ethernet/amd/xgbe/xgbe-common.h ioread32((_pdata)->xi2c_regs + (_reg)) _reg 1660 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ _reg 1661 drivers/net/ethernet/amd/xgbe/xgbe-common.h GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ _reg 1662 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1663 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH) _reg 1665 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XI2C_IOWRITE(_pdata, _reg, _val) \ _reg 1666 drivers/net/ethernet/amd/xgbe/xgbe-common.h iowrite32((_val), (_pdata)->xi2c_regs + (_reg)) _reg 1668 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ _reg 1670 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \ _reg 1672 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_INDEX, \ _reg 1673 drivers/net/ethernet/amd/xgbe/xgbe-common.h _reg##_##_field##_WIDTH, (_val)); \ _reg 1674 drivers/net/ethernet/amd/xgbe/xgbe-common.h XI2C_IOWRITE((_pdata), (_reg), reg_val); \ _reg 1682 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_READ(_pdata, _mmd, _reg) \ _reg 1684 drivers/net/ethernet/amd/xgbe/xgbe-common.h MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) _reg 1686 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ _reg 1687 drivers/net/ethernet/amd/xgbe/xgbe-common.h (XMDIO_READ((_pdata), _mmd, _reg) & _mask) _reg 1689 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ _reg 1691 drivers/net/ethernet/amd/xgbe/xgbe-common.h MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) _reg 1693 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ _reg 1695 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ _reg 1698 drivers/net/ethernet/amd/xgbe/xgbe-common.h XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ _reg 62 drivers/net/ethernet/freescale/fs_enet/mac-fec.c #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) _reg 65 drivers/net/ethernet/freescale/fs_enet/mac-fec.c #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) _reg 68 drivers/net/ethernet/freescale/fs_enet/mac-fec.c #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) _reg 71 drivers/net/ethernet/freescale/fs_enet/mac-fec.c #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) _reg 152 drivers/net/ethernet/micrel/ks8851.c #define MK_OP(_byteen, _reg) (BYTE_EN(_byteen) | (_reg) << (8+2) | (_reg) >> 6) _reg 124 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ _reg 125 drivers/net/wireless/ath/ath5k/ath5k.h ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ _reg 126 drivers/net/wireless/ath/ath5k/ath5k.h (((_val) << _flags##_S) & (_flags)), _reg) _reg 128 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ _reg 129 drivers/net/wireless/ath/ath5k/ath5k.h ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ _reg 130 drivers/net/wireless/ath/ath5k/ath5k.h (_mask)) | (_flags), _reg) _reg 132 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ _reg 133 drivers/net/wireless/ath/ath5k/ath5k.h ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) _reg 135 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ _reg 136 drivers/net/wireless/ath/ath5k/ath5k.h ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) _reg 139 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_READ_Q(ah, _reg, _queue) \ _reg 140 drivers/net/wireless/ath/ath5k/ath5k.h (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ _reg 142 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ _reg 143 drivers/net/wireless/ath/ath5k/ath5k.h ath5k_hw_reg_write(ah, (1 << _queue), _reg) _reg 145 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ _reg 146 drivers/net/wireless/ath/ath5k/ath5k.h _reg |= 1 << _queue; \ _reg 149 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ _reg 150 drivers/net/wireless/ath/ath5k/ath5k.h _reg &= ~(1 << _queue); \ _reg 24 drivers/net/wireless/ath/ath9k/debug.c #define REG_WRITE_D(_ah, _reg, _val) \ _reg 25 drivers/net/wireless/ath/ath9k/debug.c ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) _reg 26 drivers/net/wireless/ath/ath9k/debug.c #define REG_READ_D(_ah, _reg) \ _reg 27 drivers/net/wireless/ath/ath9k/debug.c ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) _reg 79 drivers/net/wireless/ath/ath9k/hw.h #define REG_WRITE(_ah, _reg, _val) \ _reg 80 drivers/net/wireless/ath/ath9k/hw.h (_ah)->reg_ops.write((_ah), (_val), (_reg)) _reg 82 drivers/net/wireless/ath/ath9k/hw.h #define REG_READ(_ah, _reg) \ _reg 83 drivers/net/wireless/ath/ath9k/hw.h (_ah)->reg_ops.read((_ah), (_reg)) _reg 88 drivers/net/wireless/ath/ath9k/hw.h #define REG_RMW(_ah, _reg, _set, _clr) \ _reg 89 drivers/net/wireless/ath/ath9k/hw.h (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) _reg 24 drivers/net/wireless/ath/hw.c #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) _reg 26 drivers/net/wireless/ath/key.c #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) _reg 560 drivers/net/wireless/mediatek/mt76/mt76.h #define mt76_get_field(_dev, _reg, _field) \ _reg 561 drivers/net/wireless/mediatek/mt76/mt76.h FIELD_GET(_field, mt76_rr(dev, _reg)) _reg 563 drivers/net/wireless/mediatek/mt76/mt76.h #define mt76_rmw_field(_dev, _reg, _field, _val) \ _reg 564 drivers/net/wireless/mediatek/mt76/mt76.h mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) _reg 566 drivers/net/wireless/mediatek/mt76/mt76.h #define __mt76_rmw_field(_dev, _reg, _field, _val) \ _reg 567 drivers/net/wireless/mediatek/mt76/mt76.h __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) _reg 297 drivers/net/wireless/mediatek/mt7601u/mt7601u.h #define mt76_rmw_field(_dev, _reg, _field, _val) \ _reg 298 drivers/net/wireless/mediatek/mt7601u/mt7601u.h mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) _reg 499 drivers/pinctrl/pinctrl-pistachio.c #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \ _reg 506 drivers/pinctrl/pinctrl-pistachio.c .scenario_reg = _reg, \ _reg 662 drivers/pinctrl/pinctrl-pistachio.c #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \ _reg 671 drivers/pinctrl/pinctrl-pistachio.c .mux_reg = _reg, \ _reg 73 drivers/pinctrl/qcom/pinctrl-msm.c return readl(pctrl->regs[g->tile] + g->name##_reg); \ _reg 78 drivers/pinctrl/qcom/pinctrl-msm.c writel(val, pctrl->regs[g->tile] + g->name##_reg); \ _reg 21 drivers/power/supply/max77650-charger.c #define MAX77650_CHG_DETAILS_BITS(_reg) \ _reg 22 drivers/power/supply/max77650-charger.c (((_reg) & MAX77650_CHG_DETAILS_MASK) >> 4) _reg 52 drivers/power/supply/max77650-charger.c #define MAX77650_CHGIN_DETAILS_BITS(_reg) \ _reg 53 drivers/power/supply/max77650-charger.c (((_reg) & MAX77650_CHGIN_DETAILS_MASK) >> 2) _reg 60 drivers/power/supply/max77650-charger.c #define MAX77650_CHARGER_CHG_CHARGING(_reg) \ _reg 61 drivers/power/supply/max77650-charger.c (((_reg) & MAX77650_CHARGER_CHG_MASK) > 1) _reg 26 drivers/regulator/da9063-regulator.c #define BFIELD(_reg, _mask) \ _reg 27 drivers/regulator/da9063-regulator.c REG_FIELD(_reg, __builtin_ffs((int)_mask) - 1, \ _reg 16 drivers/regulator/max77650-regulator.c #define MAX77650_REGULATOR_EN_CTRL_BITS(_reg) \ _reg 17 drivers/regulator/max77650-regulator.c ((_reg) & MAX77650_REGULATOR_EN_CTRL_MASK) _reg 287 drivers/regulator/max8997-regulator.c int *_reg, int *_shift, int *_mask) _reg 345 drivers/regulator/max8997-regulator.c *_reg = reg; _reg 118 drivers/regulator/max8998.c int *_reg, int *_shift, int *_mask) _reg 173 drivers/regulator/max8998.c *_reg = reg; _reg 243 drivers/regulator/mc13783-regulator.c #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \ _reg 244 drivers/regulator/mc13783-regulator.c MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) _reg 245 drivers/regulator/mc13783-regulator.c #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \ _reg 246 drivers/regulator/mc13783-regulator.c MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) _reg 55 drivers/regulator/mc13xxx.h #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ _reg 66 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ _reg 67 drivers/regulator/mc13xxx.h .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ _reg 73 drivers/regulator/mc13xxx.h #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ _reg 84 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ _reg 85 drivers/regulator/mc13xxx.h .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ _reg 88 drivers/regulator/mc13xxx.h #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ _reg 99 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ _reg 100 drivers/regulator/mc13xxx.h .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ _reg 103 drivers/regulator/mc13xxx.h #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ _reg 104 drivers/regulator/mc13xxx.h MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops) _reg 105 drivers/regulator/mc13xxx.h #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ _reg 106 drivers/regulator/mc13xxx.h MC13xxx_DEFINE(REGU, _name, _node, _reg, _vsel_reg, _voltages, ops) _reg 103 drivers/regulator/pcap-regulator.c #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \ _reg 105 drivers/regulator/pcap-regulator.c .reg = _reg, \ _reg 371 drivers/regulator/tps6524x-regulator.c #define __MK_FIELD(_reg, _mask, _shift) \ _reg 372 drivers/regulator/tps6524x-regulator.c { .reg = (_reg), .mask = (_mask), .shift = (_shift), } _reg 28 drivers/reset/reset-uniphier.c #define UNIPHIER_RESET(_id, _reg, _bit) \ _reg 31 drivers/reset/reset-uniphier.c .reg = (_reg), \ _reg 35 drivers/reset/reset-uniphier.c #define UNIPHIER_RESETX(_id, _reg, _bit) \ _reg 38 drivers/reset/reset-uniphier.c .reg = (_reg), \ _reg 57 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_CORE(_reg, _bit) \ _reg 58 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) _reg 60 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_SBC(_reg, _bit) \ _reg 61 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) _reg 63 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_LPM(_reg, _bit) \ _reg 64 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) _reg 54 drivers/scsi/csiostor/csio_wr.c #define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \ _reg 55 drivers/scsi/csiostor/csio_wr.c csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg##_A) _reg 51 drivers/soc/sunxi/sunxi_sram.c #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ _reg 54 drivers/soc/sunxi/sunxi_sram.c .reg = _reg, \ _reg 39 drivers/staging/rtl8723bs/hal/odm_interface.h #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) _reg 44 include/linux/bitfield.h #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ _reg 52 include/linux/bitfield.h BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \ _reg 93 include/linux/bitfield.h #define FIELD_GET(_mask, _reg) \ _reg 95 include/linux/bitfield.h __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ _reg 96 include/linux/bitfield.h (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ _reg 52 include/linux/mfd/max77650.h #define MAX77650_CID_BITS(_reg) (_reg & MAX77650_CID_MASK) _reg 1086 include/linux/regmap.h #define REG_FIELD(_reg, _lsb, _msb) { \ _reg 1087 include/linux/regmap.h .reg = _reg, \ _reg 151 include/linux/sh_clk.h #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ _reg 154 include/linux/sh_clk.h .enable_reg = (void __iomem *)_reg, \ _reg 175 include/linux/sh_clk.h #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ _reg 178 include/linux/sh_clk.h .enable_reg = (void __iomem *)_reg, \ _reg 188 include/linux/sh_clk.h #define SH_CLK_DIV6(_parent, _reg, _flags) \ _reg 191 include/linux/sh_clk.h .enable_reg = (void __iomem *)_reg, \ _reg 205 include/linux/sh_clk.h #define SH_CLK_FSIDIV(_reg, _parent) \ _reg 207 include/linux/sh_clk.h .enable_reg = (void __iomem *)_reg, \ _reg 597 sound/soc/codecs/adau1373.c #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ _reg 599 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \ _reg 600 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \ _reg 601 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \ _reg 602 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \ _reg 603 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \ _reg 604 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \ _reg 605 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \ _reg 606 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \ _reg 642 sound/soc/codecs/adau1373.c #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ _reg 644 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \ _reg 645 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \ _reg 646 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \ _reg 647 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \ _reg 648 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \ _reg 649 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \ _reg 650 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \ _reg 664 sound/soc/codecs/adau1373.c #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \ _reg 666 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \ _reg 667 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \ _reg 668 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \ _reg 669 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \ _reg 670 sound/soc/codecs/adau1373.c SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \ _reg 508 sound/soc/sh/rcar/dma.c #define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8) _reg 509 sound/soc/sh/rcar/dma.c #define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc) _reg 511 sound/soc/sh/rcar/dma.c #define RDMA_SSIU_I_N(addr, i, j) (addr ##_reg - 0x00441000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4))) _reg 514 sound/soc/sh/rcar/dma.c #define RDMA_SSIU_I_P(addr, i, j) (addr ##_reg - 0x00141000 + (0x1000 * (i)) + (((j) / 4) * 0xA000) + (((j) % 4) * 0x400) - (0x4000 * ((i) / 9) * ((j) / 4))) _reg 517 sound/soc/sh/rcar/dma.c #define RDMA_SRC_I_N(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i)) _reg 518 sound/soc/sh/rcar/dma.c #define RDMA_SRC_O_N(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i)) _reg 520 sound/soc/sh/rcar/dma.c #define RDMA_SRC_I_P(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i)) _reg 521 sound/soc/sh/rcar/dma.c #define RDMA_SRC_O_P(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i)) _reg 523 sound/soc/sh/rcar/dma.c #define RDMA_CMD_O_N(addr, i) (addr ##_reg - 0x004f8000 + (0x400 * i)) _reg 524 sound/soc/sh/rcar/dma.c #define RDMA_CMD_O_P(addr, i) (addr ##_reg - 0x001f8000 + (0x400 * i))