_r1                84 drivers/clk/renesas/r9a06g032-clocks.c #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
_r1                88 drivers/clk/renesas/r9a06g032-clocks.c 			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
_r1               134 drivers/pinctrl/mediatek/pinctrl-mtk-common.h #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0)	\
_r1               139 drivers/pinctrl/mediatek/pinctrl-mtk-common.h 		.r1_bit = _r1,		\
_r1                23 drivers/scsi/aic94xx/aic94xx_sds.c 	u8 _r1;
_r1                29 drivers/scsi/aic94xx/aic94xx_sds.c 	u8   _r1[2];
_r1                64 include/scsi/scsi.h 	__u8 _r1;			/* reserved */