_pclk_dbg_div      80 drivers/clk/rockchip/clk-rk3128.c #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div)			\
_pclk_dbg_div      83 drivers/clk/rockchip/clk-rk3128.c 	.val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK,	\
_pclk_dbg_div      89 drivers/clk/rockchip/clk-rk3128.c #define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div)	\
_pclk_dbg_div      93 drivers/clk/rockchip/clk-rk3128.c 		RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div),		\