_pclk_dbg          78 drivers/clk/rockchip/clk-px30.c #define PX30_CLKSEL0(_aclk_core, _pclk_dbg)				\
_pclk_dbg          83 drivers/clk/rockchip/clk-px30.c 	       HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK,	\
_pclk_dbg          87 drivers/clk/rockchip/clk-px30.c #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_pclk_dbg          91 drivers/clk/rockchip/clk-px30.c 		PX30_CLKSEL0(_aclk_core, _pclk_dbg),			\
_pclk_dbg          74 drivers/clk/rockchip/clk-rk3308.c #define RK3308_CLKSEL0(_aclk_core, _pclk_dbg)				\
_pclk_dbg          79 drivers/clk/rockchip/clk-rk3308.c 	       HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK,	\
_pclk_dbg          83 drivers/clk/rockchip/clk-rk3308.c #define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_pclk_dbg          87 drivers/clk/rockchip/clk-rk3308.c 		RK3308_CLKSEL0(_aclk_core, _pclk_dbg),			\
_pclk_dbg          93 drivers/clk/rockchip/clk-rk3328.c #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg)				\
_pclk_dbg          98 drivers/clk/rockchip/clk-rk3328.c 	       HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK,	\
_pclk_dbg         102 drivers/clk/rockchip/clk-rk3328.c #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_pclk_dbg         106 drivers/clk/rockchip/clk-rk3328.c 		RK3328_CLKSEL1(_aclk_core, _pclk_dbg),			\