_o 18 drivers/gpu/drm/armada/armada_crtc.h #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ _o 21 drivers/gpu/drm/armada/armada_crtc.h __reg[_i].offset = _o; \ _o 27 drivers/gpu/drm/armada/armada_crtc.h #define armada_reg_queue_set(_r, _i, _v, _o) \ _o 28 drivers/gpu/drm/armada/armada_crtc.h armada_reg_queue_mod(_r, _i, _v, ~0, _o) _o 21 drivers/gpu/drm/msm/adreno/a5xx_power.c #define AGC_MSG_PAYLOAD(_o) ((AGC_MSG_BASE + 5) + (_o)) _o 88 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h u64 _a = (a), _c = (c), _d = (d), _o = _a >> s, _s = _c << s; \ _o 93 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h iowrite##t##_native(_d, &_m[_o++]); \ _o 95 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h memset_io(&_m[_o], _d, _s); \ _o 377 drivers/net/dsa/mt7530.h #define MIB_DESC(_s, _o, _n) \ _o 380 drivers/net/dsa/mt7530.h .offset = (_o), \ _o 22 drivers/net/dsa/qca8k.c #define MIB_DESC(_s, _o, _n) \ _o 25 drivers/net/dsa/qca8k.c .offset = (_o), \ _o 244 drivers/net/wireless/ath/ath5k/eeprom.h #define AR5K_EEPROM_READ(_o, _v) do { \ _o 245 drivers/net/wireless/ath/ath5k/eeprom.h if (!ath5k_hw_nvram_read(ah, (_o), &(_v))) \ _o 249 drivers/net/wireless/ath/ath5k/eeprom.h #define AR5K_EEPROM_READ_HDR(_o, _v) \ _o 250 drivers/net/wireless/ath/ath5k/eeprom.h AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \ _o 788 drivers/scsi/aic94xx/aic94xx_dump.c #define DDB0_FIELDA(__name, _o) \ _o 790 drivers/scsi/aic94xx/aic94xx_dump.c offsetof(struct asd_ddb_seq_shared, __name)+_o) _o 79 fs/erofs/tagptr.h #define tagptr_cmpxchg(_ptptr, _o, _n) ({ \ _o 81 fs/erofs/tagptr.h typeof(_o) o = (_o); \