_lrclk_div        286 drivers/clk/meson/axg-audio.c 	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
_lrclk_div        298 drivers/clk/meson/axg-audio.c 		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)