_inner_outer 62 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c #define DR_MASK_IS_L2_DST(_spec, _misc, _inner_outer) (_spec.first_vid || \ _inner_outer 66 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_second_vid || \ _inner_outer 67 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_second_cfi || \ _inner_outer 68 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_second_prio || \ _inner_outer 69 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_second_cvlan_tag || \ _inner_outer 70 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_second_svlan_tag) _inner_outer 72 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c #define DR_MASK_IS_ETH_L4_SET(_spec, _misc, _inner_outer) ( \ _inner_outer 76 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc)._inner_outer##_ipv6_flow_label) _inner_outer 78 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c #define DR_MASK_IS_ETH_L4_MISC_SET(_misc3, _inner_outer) ( \ _inner_outer 79 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc3)._inner_outer##_tcp_seq_num || \ _inner_outer 80 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc3)._inner_outer##_tcp_ack_num) _inner_outer 82 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c #define DR_MASK_IS_FIRST_MPLS_SET(_misc2, _inner_outer) ( \ _inner_outer 83 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc2)._inner_outer##_first_mpls_label || \ _inner_outer 84 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc2)._inner_outer##_first_mpls_exp || \ _inner_outer 85 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc2)._inner_outer##_first_mpls_s_bos || \ _inner_outer 86 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (_misc2)._inner_outer##_first_mpls_ttl)