_gate 38 drivers/clk/actions/owl-composite.h _mux, _gate, _div, _flags) \ _gate 41 drivers/clk/actions/owl-composite.h .gate_hw = _gate, \ _gate 53 drivers/clk/actions/owl-composite.h _gate, _div, _flags) \ _gate 55 drivers/clk/actions/owl-composite.h .gate_hw = _gate, \ _gate 67 drivers/clk/actions/owl-composite.h _mux, _gate, _factor, _flags) \ _gate 70 drivers/clk/actions/owl-composite.h .gate_hw = _gate, \ _gate 82 drivers/clk/actions/owl-composite.h _gate, _mul, _div, _flags) \ _gate 84 drivers/clk/actions/owl-composite.h .gate_hw = _gate, \ _gate 98 drivers/clk/actions/owl-composite.h _mux, _gate, _flags) \ _gate 101 drivers/clk/actions/owl-composite.h .gate_hw = _gate, \ _gate 525 drivers/clk/clk-stm32f4.c #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) _gate 663 drivers/clk/clk-stm32mp1.c #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate) _gate 1186 drivers/clk/clk-stm32mp1.c #define STM32_GATE(_id, _name, _parent, _flags, _gate)\ _gate 1192 drivers/clk/clk-stm32mp1.c .cfg = (struct stm32_gate_cfg *) {_gate},\ _gate 1270 drivers/clk/clk-stm32mp1.c #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ _gate 1278 drivers/clk/clk-stm32mp1.c _gate,\ _gate 82 drivers/clk/mediatek/clk-mtk.h _width, _gate, _flags, _muxflags) { \ _gate 89 drivers/clk/mediatek/clk-mtk.h .gate_shift = _gate, \ _gate 102 drivers/clk/mediatek/clk-mtk.h _gate, _flags) \ _gate 104 drivers/clk/mediatek/clk-mtk.h _shift, _width, _gate, _flags, 0) _gate 110 drivers/clk/mediatek/clk-mtk.h #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ _gate 112 drivers/clk/mediatek/clk-mtk.h _gate, CLK_SET_RATE_PARENT) _gate 47 drivers/clk/mediatek/clk-mux.h _gate, _upd_ofs, _upd, _flags, _ops) { \ _gate 56 drivers/clk/mediatek/clk-mux.h .gate_shift = _gate, \ _gate 66 drivers/clk/mediatek/clk-mux.h _gate, _upd_ofs, _upd, _flags) \ _gate 69 drivers/clk/mediatek/clk-mux.h _gate, _upd_ofs, _upd, _flags, \ _gate 74 drivers/clk/mediatek/clk-mux.h _gate, _upd_ofs, _upd) \ _gate 77 drivers/clk/mediatek/clk-mux.h _width, _gate, _upd_ofs, _upd, \ _gate 1206 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ _gate 1215 drivers/clk/nxp/clk-lpc32xx.c .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\ _gate 1216 drivers/clk/nxp/clk-lpc32xx.c &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \ _gate 89 drivers/clk/sunxi-ng/ccu_div.h _table, _gate, _flags) \ _gate 93 drivers/clk/sunxi-ng/ccu_div.h .enable = _gate, \ _gate 116 drivers/clk/sunxi-ng/ccu_div.h _gate, _flags) \ _gate 118 drivers/clk/sunxi-ng/ccu_div.h .enable = _gate, \ _gate 132 drivers/clk/sunxi-ng/ccu_div.h _gate, _flags) \ _gate 137 drivers/clk/sunxi-ng/ccu_div.h _gate, _flags) _gate 150 drivers/clk/sunxi-ng/ccu_div.h _mshift, _mwidth, _gate, \ _gate 153 drivers/clk/sunxi-ng/ccu_div.h .enable = _gate, \ _gate 19 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ _gate 21 drivers/clk/sunxi-ng/ccu_gate.h .enable = _gate, \ _gate 31 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ _gate 33 drivers/clk/sunxi-ng/ccu_gate.h .enable = _gate, \ _gate 43 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ _gate 45 drivers/clk/sunxi-ng/ccu_gate.h .enable = _gate, \ _gate 59 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ _gate 61 drivers/clk/sunxi-ng/ccu_gate.h .enable = _gate, \ _gate 71 drivers/clk/sunxi-ng/ccu_gate.h #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ _gate 73 drivers/clk/sunxi-ng/ccu_gate.h .enable = _gate, \ _gate 38 drivers/clk/sunxi-ng/ccu_mp.h _gate, _postdiv, _flags) \ _gate 40 drivers/clk/sunxi-ng/ccu_mp.h .enable = _gate, \ _gate 59 drivers/clk/sunxi-ng/ccu_mp.h _gate, _flags) \ _gate 61 drivers/clk/sunxi-ng/ccu_mp.h .enable = _gate, \ _gate 46 drivers/clk/sunxi-ng/ccu_mult.h _mshift, _mwidth, _gate, _lock, \ _gate 49 drivers/clk/sunxi-ng/ccu_mult.h .enable = _gate, \ _gate 51 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _gate 54 drivers/clk/sunxi-ng/ccu_mux.h .enable = _gate, \ _gate 66 drivers/clk/sunxi-ng/ccu_mux.h _shift, _width, _gate, _flags) \ _gate 68 drivers/clk/sunxi-ng/ccu_mux.h _reg, _shift, _width, _gate, \ _gate 36 drivers/clk/sunxi-ng/ccu_nk.h _gate, _lock, _postdiv, \ _gate 39 drivers/clk/sunxi-ng/ccu_nk.h .enable = _gate, \ _gate 39 drivers/clk/sunxi-ng/ccu_nkm.h _gate, _lock, _flags) \ _gate 41 drivers/clk/sunxi-ng/ccu_nkm.h .enable = _gate, \ _gate 60 drivers/clk/sunxi-ng/ccu_nkm.h _gate, _lock, _flags) \ _gate 62 drivers/clk/sunxi-ng/ccu_nkm.h .enable = _gate, \ _gate 40 drivers/clk/sunxi-ng/ccu_nkmp.h _gate, _lock, _flags) \ _gate 42 drivers/clk/sunxi-ng/ccu_nkmp.h .enable = _gate, \ _gate 43 drivers/clk/sunxi-ng/ccu_nm.h _gate, _lock, _flags) \ _gate 45 drivers/clk/sunxi-ng/ccu_nm.h .enable = _gate, \ _gate 66 drivers/clk/sunxi-ng/ccu_nm.h _gate, _lock, _flags) \ _gate 68 drivers/clk/sunxi-ng/ccu_nm.h .enable = _gate, \ _gate 91 drivers/clk/sunxi-ng/ccu_nm.h _gate, _lock, _flags) \ _gate 93 drivers/clk/sunxi-ng/ccu_nm.h .enable = _gate, \ _gate 119 drivers/clk/sunxi-ng/ccu_nm.h _gate, _lock, _flags) \ _gate 121 drivers/clk/sunxi-ng/ccu_nm.h .enable = _gate, \ _gate 143 drivers/clk/sunxi-ng/ccu_nm.h _gate, _lock, _flags) \ _gate 145 drivers/clk/sunxi-ng/ccu_nm.h .enable = _gate, \ _gate 42 scripts/gcc-plugins/gcc-generate-gimple-pass.h #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) _gate 106 scripts/gcc-plugins/gcc-generate-ipa-pass.h #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) _gate 42 scripts/gcc-plugins/gcc-generate-rtl-pass.h #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate) _gate 42 scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h #define __GATE(n) _GCC_PLUGIN_CONCAT2(n, _gate)