_core_m0 130 drivers/clk/rockchip/clk-rk3288.c #define RK3288_CLKSEL0(_core_m0, _core_mp) \ _core_m0 133 drivers/clk/rockchip/clk-rk3288.c .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \ _core_m0 150 drivers/clk/rockchip/clk-rk3288.c #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \ _core_m0 154 drivers/clk/rockchip/clk-rk3288.c RK3288_CLKSEL0(_core_m0, _core_mp), \