_bit_idx 27 drivers/clk/actions/owl-gate.h #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ _bit_idx 30 drivers/clk/actions/owl-gate.h .bit_idx = _bit_idx, \ _bit_idx 35 drivers/clk/actions/owl-gate.h _bit_idx, _gate_flags, _flags) \ _bit_idx 37 drivers/clk/actions/owl-gate.h .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ _bit_idx 48 drivers/clk/actions/owl-gate.h _bit_idx, _gate_flags, _flags) \ _bit_idx 50 drivers/clk/actions/owl-gate.h .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ _bit_idx 41 drivers/clk/actions/owl-pll.h #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _bit_idx 46 drivers/clk/actions/owl-pll.h .bit_idx = _bit_idx, \ _bit_idx 55 drivers/clk/actions/owl-pll.h #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ _bit_idx 58 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _bit_idx 70 drivers/clk/actions/owl-pll.h #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ _bit_idx 73 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _bit_idx 84 drivers/clk/actions/owl-pll.h #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ _bit_idx 88 drivers/clk/actions/owl-pll.h .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ _bit_idx 598 drivers/clk/clk-stm32h7.c #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\ _bit_idx 603 drivers/clk/clk-stm32h7.c .bit_idx = _bit_idx,\ _bit_idx 608 drivers/clk/clk-stm32h7.c #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\ _bit_idx 609 drivers/clk/clk-stm32h7.c OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0) _bit_idx 938 drivers/clk/clk-stm32h7.c #define M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ _bit_idx 943 drivers/clk/clk-stm32h7.c .gate = &(struct gate_cfg) {_gate_offset, _bit_idx },\ _bit_idx 950 drivers/clk/clk-stm32h7.c #define M_ODF(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ _bit_idx 952 drivers/clk/clk-stm32h7.c M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ _bit_idx 986 drivers/clk/clk-stm32h7.c #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\ _bit_idx 989 drivers/clk/clk-stm32h7.c .bit_idx = _bit_idx,\ _bit_idx 995 drivers/clk/clk-stm32h7.c #define PER_CLK(_gate_offset, _bit_idx, _name, _parent)\ _bit_idx 996 drivers/clk/clk-stm32h7.c PER_CLKF(_gate_offset, _bit_idx, _name, _parent, 0) _bit_idx 1064 drivers/clk/clk-stm32h7.c #define KER_CLKF(_gate_offset, _bit_idx,\ _bit_idx 1069 drivers/clk/clk-stm32h7.c .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\ _bit_idx 1077 drivers/clk/clk-stm32h7.c #define KER_CLK(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\ _bit_idx 1079 drivers/clk/clk-stm32h7.c KER_CLKF(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\ _bit_idx 1082 drivers/clk/clk-stm32h7.c #define KER_CLKF_NOMUX(_gate_offset, _bit_idx,\ _bit_idx 1086 drivers/clk/clk-stm32h7.c .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\ _bit_idx 1092 drivers/clk/clk-stm32mp1.c #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ _bit_idx 1100 drivers/clk/clk-stm32mp1.c .bit_idx = _bit_idx,\ _bit_idx 1181 drivers/clk/clk-stm32mp1.c #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\ _bit_idx 1183 drivers/clk/clk-stm32mp1.c _offset_set, _bit_idx, 0) _bit_idx 1221 drivers/clk/clk-stm32mp1.c #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ _bit_idx 1223 drivers/clk/clk-stm32mp1.c _GATE_MP1(_offset, _bit_idx, _gate_flags))