_bit 29 arch/arc/include/asm/bitops.h static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 60 arch/arc/include/asm/bitops.h static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 107 arch/arc/include/asm/bitops.h static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 124 arch/arc/include/asm/bitops.h static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 142 arch/arc/include/asm/bitops.h static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 160 arch/arc/include/asm/bitops.h static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 194 arch/arc/include/asm/bitops.h static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \ _bit 204 arch/arc/include/asm/bitops.h static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ _bit 77 arch/sh/kernel/cpu/sh2a/clock-sh7264.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 78 arch/sh/kernel/cpu/sh2a/clock-sh7264.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 105 arch/sh/kernel/cpu/sh2a/clock-sh7269.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 106 arch/sh/kernel/cpu/sh2a/clock-sh7269.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 105 arch/sh/kernel/cpu/sh4a/clock-sh7343.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 106 arch/sh/kernel/cpu/sh4a/clock-sh7343.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 125 arch/sh/kernel/cpu/sh4a/clock-sh7343.c #define MSTP(_parent, _reg, _bit, _flags) \ _bit 126 arch/sh/kernel/cpu/sh4a/clock-sh7343.c SH_CLK_MSTP32(_parent, _reg, _bit, _flags) _bit 108 arch/sh/kernel/cpu/sh4a/clock-sh7366.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 109 arch/sh/kernel/cpu/sh4a/clock-sh7366.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 128 arch/sh/kernel/cpu/sh4a/clock-sh7366.c #define MSTP(_parent, _reg, _bit, _flags) \ _bit 129 arch/sh/kernel/cpu/sh4a/clock-sh7366.c SH_CLK_MSTP32(_parent, _reg, _bit, _flags) _bit 108 arch/sh/kernel/cpu/sh4a/clock-sh7722.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 109 arch/sh/kernel/cpu/sh4a/clock-sh7722.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 111 arch/sh/kernel/cpu/sh4a/clock-sh7723.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 112 arch/sh/kernel/cpu/sh4a/clock-sh7723.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 150 arch/sh/kernel/cpu/sh4a/clock-sh7724.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 151 arch/sh/kernel/cpu/sh4a/clock-sh7724.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 69 arch/sh/kernel/cpu/sh4a/clock-sh7734.c #define DIV4(_reg, _bit, _mask, _flags) \ _bit 70 arch/sh/kernel/cpu/sh4a/clock-sh7734.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _bit 62 arch/sh/kernel/cpu/sh4a/clock-sh7757.c #define DIV4(_bit, _mask, _flags) \ _bit 63 arch/sh/kernel/cpu/sh4a/clock-sh7757.c SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) _bit 66 arch/sh/kernel/cpu/sh4a/clock-sh7785.c #define DIV4(_bit, _mask, _flags) \ _bit 67 arch/sh/kernel/cpu/sh4a/clock-sh7785.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _bit 67 arch/sh/kernel/cpu/sh4a/clock-sh7786.c #define DIV4(_bit, _mask, _flags) \ _bit 68 arch/sh/kernel/cpu/sh4a/clock-sh7786.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _bit 61 arch/sh/kernel/cpu/sh4a/clock-shx3.c #define DIV4(_bit, _mask, _flags) \ _bit 62 arch/sh/kernel/cpu/sh4a/clock-shx3.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _bit 99 drivers/clk/bcm/clk-kona.h #define POLICY(_offset, _bit) \ _bit 102 drivers/clk/bcm/clk-kona.h .bit = (_bit), \ _bit 383 drivers/clk/bcm/clk-kona.h #define TRIGGER(_offset, _bit) \ _bit 386 drivers/clk/bcm/clk-kona.h .bit = (_bit), \ _bit 442 drivers/clk/bcm/clk-kona.h #define CCU_LVM_EN(_offset, _bit) \ _bit 445 drivers/clk/bcm/clk-kona.h .bit = (_bit), \ _bit 89 drivers/clk/clk-oxnas.c #define OXNAS_GATE(_name, _bit, _parents) \ _bit 91 drivers/clk/clk-oxnas.c .bit = (_bit), \ _bit 34 drivers/clk/meson/axg-aoclk.c #define AXG_AO_GATE(_name, _bit) \ _bit 38 drivers/clk/meson/axg-aoclk.c .bit_idx = (_bit), \ _bit 27 drivers/clk/meson/axg-audio.c #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \ _bit 31 drivers/clk/meson/axg-audio.c .bit_idx = (_bit), \ _bit 76 drivers/clk/meson/axg-audio.c #define AUD_PCLK_GATE(_name, _bit) \ _bit 80 drivers/clk/meson/axg-audio.c .bit_idx = (_bit), \ _bit 1099 drivers/clk/meson/axg.c #define MESON_GATE(_name, _reg, _bit) \ _bit 1100 drivers/clk/meson/axg.c MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) _bit 114 drivers/clk/meson/clk-regmap.h #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ _bit 118 drivers/clk/meson/clk-regmap.h .bit_idx = (_bit), \ _bit 129 drivers/clk/meson/clk-regmap.h #define MESON_PCLK(_name, _reg, _bit, _pname) \ _bit 130 drivers/clk/meson/clk-regmap.h __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) _bit 132 drivers/clk/meson/clk-regmap.h #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ _bit 133 drivers/clk/meson/clk-regmap.h __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) _bit 43 drivers/clk/meson/g12a-aoclk.c #define AXG_AO_GATE(_name, _reg, _bit) \ _bit 47 drivers/clk/meson/g12a-aoclk.c .bit_idx = (_bit), \ _bit 3865 drivers/clk/meson/g12a.c #define MESON_GATE(_name, _reg, _bit) \ _bit 3866 drivers/clk/meson/g12a.c MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) _bit 3868 drivers/clk/meson/g12a.c #define MESON_GATE_RO(_name, _reg, _bit) \ _bit 3869 drivers/clk/meson/g12a.c MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw) _bit 23 drivers/clk/meson/gxbb-aoclk.c #define GXBB_AO_GATE(_name, _bit) \ _bit 27 drivers/clk/meson/gxbb-aoclk.c .bit_idx = (_bit), \ _bit 2591 drivers/clk/meson/gxbb.c #define MESON_GATE(_name, _reg, _bit) \ _bit 2592 drivers/clk/meson/gxbb.c MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) _bit 2570 drivers/clk/meson/meson8b.c #define MESON_GATE(_name, _reg, _bit) \ _bit 2571 drivers/clk/meson/meson8b.c MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) _bit 128 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_GATE(_name, _bit) \ _bit 131 drivers/clk/mvebu/armada-37xx-periph.c .bit_idx = _bit, \ _bit 180 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ _bit 181 drivers/clk/mvebu/armada-37xx-periph.c static PERIPH_GATE(_name, _bit); \ _bit 185 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ _bit 186 drivers/clk/mvebu/armada-37xx-periph.c static PERIPH_GATE(_name, _bit); \ _bit 190 drivers/clk/mvebu/armada-37xx-periph.c #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ _bit 191 drivers/clk/mvebu/armada-37xx-periph.c static PERIPH_GATE(_name, _bit); \ _bit 1149 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ _bit 1158 drivers/clk/nxp/clk-lpc32xx.c .bit_idx = (_bit), \ _bit 95 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ _bit 103 drivers/clk/uniphier/clk-uniphier.h .bit = (_bit), \ _bit 60 drivers/clk/zte/clk.h #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ _bit 64 drivers/clk/zte/clk.h .bit_idx = (_bit), \ _bit 802 drivers/input/misc/uinput.c #define uinput_set_bit(_arg, _bit, _max) \ _bit 809 drivers/input/misc/uinput.c else set_bit((_arg), udev->dev->_bit); \ _bit 848 drivers/iommu/amd_iommu_init.c int _bit = bit & 0x3f; _bit 850 drivers/iommu/amd_iommu_init.c amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); _bit 856 drivers/iommu/amd_iommu_init.c int _bit = bit & 0x3f; _bit 858 drivers/iommu/amd_iommu_init.c return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; _bit 938 drivers/memory/tegra/tegra114.c #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ _bit 944 drivers/memory/tegra/tegra114.c .bit = _bit, \ _bit 990 drivers/memory/tegra/tegra124.c #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ _bit 996 drivers/memory/tegra/tegra124.c .bit = _bit, \ _bit 170 drivers/memory/tegra/tegra20.c #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ _bit 177 drivers/memory/tegra/tegra20.c .bit = _bit, \ _bit 1080 drivers/memory/tegra/tegra210.c #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ _bit 1086 drivers/memory/tegra/tegra210.c .bit = _bit, \ _bit 960 drivers/memory/tegra/tegra30.c #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ _bit 966 drivers/memory/tegra/tegra30.c .bit = _bit, \ _bit 318 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h #define FW_CMD_IO_CLR(rtlpriv, _bit) \ _bit 321 drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.h rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \ _bit 31 drivers/pinctrl/mediatek/pinctrl-mt2701.c #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ _bit 35 drivers/pinctrl/mediatek/pinctrl-mt2701.c .bit = _bit, \ _bit 109 drivers/pinctrl/mediatek/pinctrl-mtk-common.h #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ _bit 113 drivers/pinctrl/mediatek/pinctrl-mtk-common.h .bit = _bit, \ _bit 157 drivers/pinctrl/mediatek/pinctrl-mtk-common.h #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ _bit 161 drivers/pinctrl/mediatek/pinctrl-mtk-common.h .bit = _bit, \ _bit 28 drivers/reset/reset-uniphier.c #define UNIPHIER_RESET(_id, _reg, _bit) \ _bit 32 drivers/reset/reset-uniphier.c .bit = (_bit), \ _bit 35 drivers/reset/reset-uniphier.c #define UNIPHIER_RESETX(_id, _reg, _bit) \ _bit 39 drivers/reset/reset-uniphier.c .bit = (_bit), \ _bit 18 drivers/reset/sti/reset-stih407.c #define STIH407_PDN_0(_bit) \ _bit 19 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) _bit 20 drivers/reset/sti/reset-stih407.c #define STIH407_PDN_1(_bit) \ _bit 21 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) _bit 22 drivers/reset/sti/reset-stih407.c #define STIH407_PDN_ETH(_bit, _stat) \ _bit 23 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) _bit 57 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_CORE(_reg, _bit) \ _bit 58 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) _bit 60 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_SBC(_reg, _bit) \ _bit 61 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) _bit 63 drivers/reset/sti/reset-stih407.c #define STIH407_SRST_LPM(_reg, _bit) \ _bit 64 drivers/reset/sti/reset-stih407.c _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) _bit 40 drivers/staging/rtl8723bs/hal/odm_interface.h #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) _bit 2780 drivers/target/target_core_configfs.c #define ALUA_SUPPORTED_STATE_ATTR(_name, _bit) \ _bit 2786 drivers/target/target_core_configfs.c !!(t->tg_pt_gp_alua_supported_states & _bit)); \ _bit 2813 drivers/target/target_core_configfs.c t->tg_pt_gp_alua_supported_states |= _bit; \ _bit 2815 drivers/target/target_core_configfs.c t->tg_pt_gp_alua_supported_states &= ~_bit; \