_aclk_core         78 drivers/clk/rockchip/clk-px30.c #define PX30_CLKSEL0(_aclk_core, _pclk_dbg)				\
_aclk_core         81 drivers/clk/rockchip/clk-px30.c 	.val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK,		\
_aclk_core         87 drivers/clk/rockchip/clk-px30.c #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_aclk_core         91 drivers/clk/rockchip/clk-px30.c 		PX30_CLKSEL0(_aclk_core, _pclk_dbg),			\
_aclk_core        115 drivers/clk/rockchip/clk-rk3188.c #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb)	\
_aclk_core        118 drivers/clk/rockchip/clk-rk3188.c 		.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
_aclk_core        160 drivers/clk/rockchip/clk-rk3188.c #define RK3188_CLKSEL1(_aclk_core)		\
_aclk_core        163 drivers/clk/rockchip/clk-rk3188.c 		.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
_aclk_core        166 drivers/clk/rockchip/clk-rk3188.c #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core)	\
_aclk_core        171 drivers/clk/rockchip/clk-rk3188.c 			RK3188_CLKSEL1(_aclk_core),		\
_aclk_core         74 drivers/clk/rockchip/clk-rk3308.c #define RK3308_CLKSEL0(_aclk_core, _pclk_dbg)				\
_aclk_core         77 drivers/clk/rockchip/clk-rk3308.c 	.val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK,		\
_aclk_core         83 drivers/clk/rockchip/clk-rk3308.c #define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_aclk_core         87 drivers/clk/rockchip/clk-rk3308.c 		RK3308_CLKSEL0(_aclk_core, _pclk_dbg),			\
_aclk_core         93 drivers/clk/rockchip/clk-rk3328.c #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg)				\
_aclk_core         96 drivers/clk/rockchip/clk-rk3328.c 	.val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK,		\
_aclk_core        102 drivers/clk/rockchip/clk-rk3328.c #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
_aclk_core        106 drivers/clk/rockchip/clk-rk3328.c 		RK3328_CLKSEL1(_aclk_core, _pclk_dbg),			\