__loop_cache_all   56 arch/xtensa/include/asm/cacheasm.h 	.macro	__loop_cache_all ar at insn size line_width max_immed
__loop_cache_all   86 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
__loop_cache_all   96 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
__loop_cache_all  106 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
__loop_cache_all  116 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
__loop_cache_all  126 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
__loop_cache_all  136 arch/xtensa/include/asm/cacheasm.h 	__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \